1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 232 233 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 234 235 { TC_VENDORID, TC_DEVICEID_3C996 }, 236 237 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 238 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 239 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 240 241 { 0, 0 } 242 }; 243 244 static const struct bge_vendor { 245 uint16_t v_id; 246 const char *v_name; 247 } bge_vendors[] = { 248 { ALTEON_VENDORID, "Alteon" }, 249 { ALTIMA_VENDORID, "Altima" }, 250 { APPLE_VENDORID, "Apple" }, 251 { BCOM_VENDORID, "Broadcom" }, 252 { SK_VENDORID, "SysKonnect" }, 253 { TC_VENDORID, "3Com" }, 254 { FJTSU_VENDORID, "Fujitsu" }, 255 256 { 0, NULL } 257 }; 258 259 static const struct bge_revision { 260 uint32_t br_chipid; 261 const char *br_name; 262 } bge_revisions[] = { 263 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 264 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 265 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 266 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 267 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 268 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 269 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 270 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 271 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 272 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 273 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 274 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 275 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 276 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 277 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 278 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 279 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 280 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 281 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 282 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 283 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 284 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 285 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 286 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 287 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 288 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 289 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 290 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 291 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 292 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 293 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 294 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 295 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 296 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 297 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 298 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 299 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 300 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 301 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 302 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 303 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 304 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 305 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 306 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 307 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 308 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 309 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 310 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 311 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 312 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 313 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 314 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 315 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 316 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 317 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 318 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 319 /* 5754 and 5787 share the same ASIC ID */ 320 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 321 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 322 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 323 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 324 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 325 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 326 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 327 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 328 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 329 330 { 0, NULL } 331 }; 332 333 /* 334 * Some defaults for major revisions, so that newer steppings 335 * that we don't know about have a shot at working. 336 */ 337 static const struct bge_revision bge_majorrevs[] = { 338 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 339 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 340 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 341 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 342 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 343 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 344 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 345 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 346 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 347 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 348 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 349 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 350 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 351 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 352 /* 5754 and 5787 share the same ASIC ID */ 353 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 354 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 355 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 356 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 357 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 358 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 359 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 360 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 361 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 362 363 { 0, NULL } 364 }; 365 366 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 367 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 368 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 369 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 370 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 371 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 372 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 373 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 374 375 static uint32_t bge_chipid(device_t); 376 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 377 static const struct bge_revision * bge_lookup_rev(uint32_t); 378 379 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 380 381 static int bge_probe(device_t); 382 static int bge_attach(device_t); 383 static int bge_detach(device_t); 384 static int bge_suspend(device_t); 385 static int bge_resume(device_t); 386 static void bge_release_resources(struct bge_softc *); 387 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 388 static int bge_dma_alloc(struct bge_softc *); 389 static void bge_dma_free(struct bge_softc *); 390 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 391 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 392 393 static void bge_devinfo(struct bge_softc *); 394 static int bge_mbox_reorder(struct bge_softc *); 395 396 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 397 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 398 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 399 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 400 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 401 402 static void bge_txeof(struct bge_softc *, uint16_t); 403 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 404 static int bge_rxeof(struct bge_softc *, uint16_t, int); 405 406 static void bge_asf_driver_up (struct bge_softc *); 407 static void bge_tick(void *); 408 static void bge_stats_clear_regs(struct bge_softc *); 409 static void bge_stats_update(struct bge_softc *); 410 static void bge_stats_update_regs(struct bge_softc *); 411 static struct mbuf *bge_check_short_dma(struct mbuf *); 412 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 413 uint16_t *, uint16_t *); 414 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 415 416 static void bge_intr(void *); 417 static int bge_msi_intr(void *); 418 static void bge_intr_task(void *, int); 419 static void bge_start_locked(struct ifnet *); 420 static void bge_start(struct ifnet *); 421 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 422 static void bge_init_locked(struct bge_softc *); 423 static void bge_init(void *); 424 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 425 static void bge_stop(struct bge_softc *); 426 static void bge_watchdog(struct bge_softc *); 427 static int bge_shutdown(device_t); 428 static int bge_ifmedia_upd_locked(struct ifnet *); 429 static int bge_ifmedia_upd(struct ifnet *); 430 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 431 432 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 433 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 434 435 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 436 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 437 438 static void bge_setpromisc(struct bge_softc *); 439 static void bge_setmulti(struct bge_softc *); 440 static void bge_setvlan(struct bge_softc *); 441 442 static __inline void bge_rxreuse_std(struct bge_softc *, int); 443 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 444 static int bge_newbuf_std(struct bge_softc *, int); 445 static int bge_newbuf_jumbo(struct bge_softc *, int); 446 static int bge_init_rx_ring_std(struct bge_softc *); 447 static void bge_free_rx_ring_std(struct bge_softc *); 448 static int bge_init_rx_ring_jumbo(struct bge_softc *); 449 static void bge_free_rx_ring_jumbo(struct bge_softc *); 450 static void bge_free_tx_ring(struct bge_softc *); 451 static int bge_init_tx_ring(struct bge_softc *); 452 453 static int bge_chipinit(struct bge_softc *); 454 static int bge_blockinit(struct bge_softc *); 455 static uint32_t bge_dma_swap_options(struct bge_softc *); 456 457 static int bge_has_eaddr(struct bge_softc *); 458 static uint32_t bge_readmem_ind(struct bge_softc *, int); 459 static void bge_writemem_ind(struct bge_softc *, int, int); 460 static void bge_writembx(struct bge_softc *, int, int); 461 #ifdef notdef 462 static uint32_t bge_readreg_ind(struct bge_softc *, int); 463 #endif 464 static void bge_writemem_direct(struct bge_softc *, int, int); 465 static void bge_writereg_ind(struct bge_softc *, int, int); 466 467 static int bge_miibus_readreg(device_t, int, int); 468 static int bge_miibus_writereg(device_t, int, int, int); 469 static void bge_miibus_statchg(device_t); 470 #ifdef DEVICE_POLLING 471 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 472 #endif 473 474 #define BGE_RESET_SHUTDOWN 0 475 #define BGE_RESET_START 1 476 #define BGE_RESET_SUSPEND 2 477 static void bge_sig_post_reset(struct bge_softc *, int); 478 static void bge_sig_legacy(struct bge_softc *, int); 479 static void bge_sig_pre_reset(struct bge_softc *, int); 480 static void bge_stop_fw(struct bge_softc *); 481 static int bge_reset(struct bge_softc *); 482 static void bge_link_upd(struct bge_softc *); 483 484 static void bge_ape_lock_init(struct bge_softc *); 485 static void bge_ape_read_fw_ver(struct bge_softc *); 486 static int bge_ape_lock(struct bge_softc *, int); 487 static void bge_ape_unlock(struct bge_softc *, int); 488 static void bge_ape_send_event(struct bge_softc *, uint32_t); 489 static void bge_ape_driver_state_change(struct bge_softc *, int); 490 491 /* 492 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 493 * leak information to untrusted users. It is also known to cause alignment 494 * traps on certain architectures. 495 */ 496 #ifdef BGE_REGISTER_DEBUG 497 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 498 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 499 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 500 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 501 #endif 502 static void bge_add_sysctls(struct bge_softc *); 503 static void bge_add_sysctl_stats_regs(struct bge_softc *, 504 struct sysctl_ctx_list *, struct sysctl_oid_list *); 505 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 506 struct sysctl_oid_list *); 507 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 508 509 static device_method_t bge_methods[] = { 510 /* Device interface */ 511 DEVMETHOD(device_probe, bge_probe), 512 DEVMETHOD(device_attach, bge_attach), 513 DEVMETHOD(device_detach, bge_detach), 514 DEVMETHOD(device_shutdown, bge_shutdown), 515 DEVMETHOD(device_suspend, bge_suspend), 516 DEVMETHOD(device_resume, bge_resume), 517 518 /* MII interface */ 519 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 520 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 521 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 522 523 DEVMETHOD_END 524 }; 525 526 static driver_t bge_driver = { 527 "bge", 528 bge_methods, 529 sizeof(struct bge_softc) 530 }; 531 532 static devclass_t bge_devclass; 533 534 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 535 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 536 537 static int bge_allow_asf = 1; 538 539 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 540 541 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 542 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 543 "Allow ASF mode if available"); 544 545 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 546 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 547 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 548 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 549 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 550 551 static int 552 bge_has_eaddr(struct bge_softc *sc) 553 { 554 #ifdef __sparc64__ 555 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 556 device_t dev; 557 uint32_t subvendor; 558 559 dev = sc->bge_dev; 560 561 /* 562 * The on-board BGEs found in sun4u machines aren't fitted with 563 * an EEPROM which means that we have to obtain the MAC address 564 * via OFW and that some tests will always fail. We distinguish 565 * such BGEs by the subvendor ID, which also has to be obtained 566 * from OFW instead of the PCI configuration space as the latter 567 * indicates Broadcom as the subvendor of the netboot interface. 568 * For early Blade 1500 and 2500 we even have to check the OFW 569 * device path as the subvendor ID always defaults to Broadcom 570 * there. 571 */ 572 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 573 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 574 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 575 return (0); 576 memset(buf, 0, sizeof(buf)); 577 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 578 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 579 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 580 return (0); 581 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 582 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 583 return (0); 584 } 585 #endif 586 return (1); 587 } 588 589 static uint32_t 590 bge_readmem_ind(struct bge_softc *sc, int off) 591 { 592 device_t dev; 593 uint32_t val; 594 595 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 596 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 597 return (0); 598 599 dev = sc->bge_dev; 600 601 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 602 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 603 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 604 return (val); 605 } 606 607 static void 608 bge_writemem_ind(struct bge_softc *sc, int off, int val) 609 { 610 device_t dev; 611 612 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 613 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 614 return; 615 616 dev = sc->bge_dev; 617 618 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 619 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 620 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 621 } 622 623 #ifdef notdef 624 static uint32_t 625 bge_readreg_ind(struct bge_softc *sc, int off) 626 { 627 device_t dev; 628 629 dev = sc->bge_dev; 630 631 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 632 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 633 } 634 #endif 635 636 static void 637 bge_writereg_ind(struct bge_softc *sc, int off, int val) 638 { 639 device_t dev; 640 641 dev = sc->bge_dev; 642 643 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 644 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 645 } 646 647 static void 648 bge_writemem_direct(struct bge_softc *sc, int off, int val) 649 { 650 CSR_WRITE_4(sc, off, val); 651 } 652 653 static void 654 bge_writembx(struct bge_softc *sc, int off, int val) 655 { 656 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 657 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 658 659 CSR_WRITE_4(sc, off, val); 660 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 661 CSR_READ_4(sc, off); 662 } 663 664 /* 665 * Clear all stale locks and select the lock for this driver instance. 666 */ 667 static void 668 bge_ape_lock_init(struct bge_softc *sc) 669 { 670 uint32_t bit, regbase; 671 int i; 672 673 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 674 regbase = BGE_APE_LOCK_GRANT; 675 else 676 regbase = BGE_APE_PER_LOCK_GRANT; 677 678 /* Clear any stale locks. */ 679 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 680 switch (i) { 681 case BGE_APE_LOCK_PHY0: 682 case BGE_APE_LOCK_PHY1: 683 case BGE_APE_LOCK_PHY2: 684 case BGE_APE_LOCK_PHY3: 685 bit = BGE_APE_LOCK_GRANT_DRIVER0; 686 break; 687 default: 688 if (sc->bge_func_addr == 0) 689 bit = BGE_APE_LOCK_GRANT_DRIVER0; 690 else 691 bit = (1 << sc->bge_func_addr); 692 } 693 APE_WRITE_4(sc, regbase + 4 * i, bit); 694 } 695 696 /* Select the PHY lock based on the device's function number. */ 697 switch (sc->bge_func_addr) { 698 case 0: 699 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 700 break; 701 case 1: 702 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 703 break; 704 case 2: 705 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 706 break; 707 case 3: 708 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 709 break; 710 default: 711 device_printf(sc->bge_dev, 712 "PHY lock not supported on this function\n"); 713 } 714 } 715 716 /* 717 * Check for APE firmware, set flags, and print version info. 718 */ 719 static void 720 bge_ape_read_fw_ver(struct bge_softc *sc) 721 { 722 const char *fwtype; 723 uint32_t apedata, features; 724 725 /* Check for a valid APE signature in shared memory. */ 726 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 727 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 728 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 729 return; 730 } 731 732 /* Check if APE firmware is running. */ 733 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 734 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 735 device_printf(sc->bge_dev, "APE signature found " 736 "but FW status not ready! 0x%08x\n", apedata); 737 return; 738 } 739 740 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 741 742 /* Fetch the APE firwmare type and version. */ 743 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 744 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 745 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 746 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 747 fwtype = "NCSI"; 748 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 749 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 750 fwtype = "DASH"; 751 } else 752 fwtype = "UNKN"; 753 754 /* Print the APE firmware version. */ 755 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 756 fwtype, 757 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 758 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 759 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 760 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 761 } 762 763 static int 764 bge_ape_lock(struct bge_softc *sc, int locknum) 765 { 766 uint32_t bit, gnt, req, status; 767 int i, off; 768 769 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 770 return (0); 771 772 /* Lock request/grant registers have different bases. */ 773 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 774 req = BGE_APE_LOCK_REQ; 775 gnt = BGE_APE_LOCK_GRANT; 776 } else { 777 req = BGE_APE_PER_LOCK_REQ; 778 gnt = BGE_APE_PER_LOCK_GRANT; 779 } 780 781 off = 4 * locknum; 782 783 switch (locknum) { 784 case BGE_APE_LOCK_GPIO: 785 /* Lock required when using GPIO. */ 786 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 787 return (0); 788 if (sc->bge_func_addr == 0) 789 bit = BGE_APE_LOCK_REQ_DRIVER0; 790 else 791 bit = (1 << sc->bge_func_addr); 792 break; 793 case BGE_APE_LOCK_GRC: 794 /* Lock required to reset the device. */ 795 if (sc->bge_func_addr == 0) 796 bit = BGE_APE_LOCK_REQ_DRIVER0; 797 else 798 bit = (1 << sc->bge_func_addr); 799 break; 800 case BGE_APE_LOCK_MEM: 801 /* Lock required when accessing certain APE memory. */ 802 if (sc->bge_func_addr == 0) 803 bit = BGE_APE_LOCK_REQ_DRIVER0; 804 else 805 bit = (1 << sc->bge_func_addr); 806 break; 807 case BGE_APE_LOCK_PHY0: 808 case BGE_APE_LOCK_PHY1: 809 case BGE_APE_LOCK_PHY2: 810 case BGE_APE_LOCK_PHY3: 811 /* Lock required when accessing PHYs. */ 812 bit = BGE_APE_LOCK_REQ_DRIVER0; 813 break; 814 default: 815 return (EINVAL); 816 } 817 818 /* Request a lock. */ 819 APE_WRITE_4(sc, req + off, bit); 820 821 /* Wait up to 1 second to acquire lock. */ 822 for (i = 0; i < 20000; i++) { 823 status = APE_READ_4(sc, gnt + off); 824 if (status == bit) 825 break; 826 DELAY(50); 827 } 828 829 /* Handle any errors. */ 830 if (status != bit) { 831 device_printf(sc->bge_dev, "APE lock %d request failed! " 832 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 833 locknum, req + off, bit & 0xFFFF, gnt + off, 834 status & 0xFFFF); 835 /* Revoke the lock request. */ 836 APE_WRITE_4(sc, gnt + off, bit); 837 return (EBUSY); 838 } 839 840 return (0); 841 } 842 843 static void 844 bge_ape_unlock(struct bge_softc *sc, int locknum) 845 { 846 uint32_t bit, gnt; 847 int off; 848 849 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 850 return; 851 852 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 853 gnt = BGE_APE_LOCK_GRANT; 854 else 855 gnt = BGE_APE_PER_LOCK_GRANT; 856 857 off = 4 * locknum; 858 859 switch (locknum) { 860 case BGE_APE_LOCK_GPIO: 861 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 862 return; 863 if (sc->bge_func_addr == 0) 864 bit = BGE_APE_LOCK_GRANT_DRIVER0; 865 else 866 bit = (1 << sc->bge_func_addr); 867 break; 868 case BGE_APE_LOCK_GRC: 869 if (sc->bge_func_addr == 0) 870 bit = BGE_APE_LOCK_GRANT_DRIVER0; 871 else 872 bit = (1 << sc->bge_func_addr); 873 break; 874 case BGE_APE_LOCK_MEM: 875 if (sc->bge_func_addr == 0) 876 bit = BGE_APE_LOCK_GRANT_DRIVER0; 877 else 878 bit = (1 << sc->bge_func_addr); 879 break; 880 case BGE_APE_LOCK_PHY0: 881 case BGE_APE_LOCK_PHY1: 882 case BGE_APE_LOCK_PHY2: 883 case BGE_APE_LOCK_PHY3: 884 bit = BGE_APE_LOCK_GRANT_DRIVER0; 885 break; 886 default: 887 return; 888 } 889 890 APE_WRITE_4(sc, gnt + off, bit); 891 } 892 893 /* 894 * Send an event to the APE firmware. 895 */ 896 static void 897 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 898 { 899 uint32_t apedata; 900 int i; 901 902 /* NCSI does not support APE events. */ 903 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 904 return; 905 906 /* Wait up to 1ms for APE to service previous event. */ 907 for (i = 10; i > 0; i--) { 908 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 909 break; 910 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 911 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 912 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 913 BGE_APE_EVENT_STATUS_EVENT_PENDING); 914 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 915 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 916 break; 917 } 918 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 919 DELAY(100); 920 } 921 if (i == 0) 922 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 923 event); 924 } 925 926 static void 927 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 928 { 929 uint32_t apedata, event; 930 931 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 932 return; 933 934 switch (kind) { 935 case BGE_RESET_START: 936 /* If this is the first load, clear the load counter. */ 937 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 938 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 939 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 940 else { 941 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 942 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 943 } 944 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 945 BGE_APE_HOST_SEG_SIG_MAGIC); 946 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 947 BGE_APE_HOST_SEG_LEN_MAGIC); 948 949 /* Add some version info if bge(4) supports it. */ 950 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 951 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 952 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 953 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 954 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 955 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 956 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 957 BGE_APE_HOST_DRVR_STATE_START); 958 event = BGE_APE_EVENT_STATUS_STATE_START; 959 break; 960 case BGE_RESET_SHUTDOWN: 961 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 962 BGE_APE_HOST_DRVR_STATE_UNLOAD); 963 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 964 break; 965 case BGE_RESET_SUSPEND: 966 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 967 break; 968 default: 969 return; 970 } 971 972 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 973 BGE_APE_EVENT_STATUS_STATE_CHNGE); 974 } 975 976 /* 977 * Map a single buffer address. 978 */ 979 980 static void 981 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 982 { 983 struct bge_dmamap_arg *ctx; 984 985 if (error) 986 return; 987 988 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 989 990 ctx = arg; 991 ctx->bge_busaddr = segs->ds_addr; 992 } 993 994 static uint8_t 995 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 996 { 997 uint32_t access, byte = 0; 998 int i; 999 1000 /* Lock. */ 1001 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1002 for (i = 0; i < 8000; i++) { 1003 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1004 break; 1005 DELAY(20); 1006 } 1007 if (i == 8000) 1008 return (1); 1009 1010 /* Enable access. */ 1011 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1012 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1013 1014 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1015 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1016 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1017 DELAY(10); 1018 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1019 DELAY(10); 1020 break; 1021 } 1022 } 1023 1024 if (i == BGE_TIMEOUT * 10) { 1025 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1026 return (1); 1027 } 1028 1029 /* Get result. */ 1030 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1031 1032 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1033 1034 /* Disable access. */ 1035 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1036 1037 /* Unlock. */ 1038 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1039 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1040 1041 return (0); 1042 } 1043 1044 /* 1045 * Read a sequence of bytes from NVRAM. 1046 */ 1047 static int 1048 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1049 { 1050 int err = 0, i; 1051 uint8_t byte = 0; 1052 1053 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1054 return (1); 1055 1056 for (i = 0; i < cnt; i++) { 1057 err = bge_nvram_getbyte(sc, off + i, &byte); 1058 if (err) 1059 break; 1060 *(dest + i) = byte; 1061 } 1062 1063 return (err ? 1 : 0); 1064 } 1065 1066 /* 1067 * Read a byte of data stored in the EEPROM at address 'addr.' The 1068 * BCM570x supports both the traditional bitbang interface and an 1069 * auto access interface for reading the EEPROM. We use the auto 1070 * access method. 1071 */ 1072 static uint8_t 1073 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1074 { 1075 int i; 1076 uint32_t byte = 0; 1077 1078 /* 1079 * Enable use of auto EEPROM access so we can avoid 1080 * having to use the bitbang method. 1081 */ 1082 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1083 1084 /* Reset the EEPROM, load the clock period. */ 1085 CSR_WRITE_4(sc, BGE_EE_ADDR, 1086 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1087 DELAY(20); 1088 1089 /* Issue the read EEPROM command. */ 1090 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1091 1092 /* Wait for completion */ 1093 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1094 DELAY(10); 1095 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1096 break; 1097 } 1098 1099 if (i == BGE_TIMEOUT * 10) { 1100 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1101 return (1); 1102 } 1103 1104 /* Get result. */ 1105 byte = CSR_READ_4(sc, BGE_EE_DATA); 1106 1107 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1108 1109 return (0); 1110 } 1111 1112 /* 1113 * Read a sequence of bytes from the EEPROM. 1114 */ 1115 static int 1116 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1117 { 1118 int i, error = 0; 1119 uint8_t byte = 0; 1120 1121 for (i = 0; i < cnt; i++) { 1122 error = bge_eeprom_getbyte(sc, off + i, &byte); 1123 if (error) 1124 break; 1125 *(dest + i) = byte; 1126 } 1127 1128 return (error ? 1 : 0); 1129 } 1130 1131 static int 1132 bge_miibus_readreg(device_t dev, int phy, int reg) 1133 { 1134 struct bge_softc *sc; 1135 uint32_t val; 1136 int i; 1137 1138 sc = device_get_softc(dev); 1139 1140 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1141 return (0); 1142 1143 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1144 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1145 CSR_WRITE_4(sc, BGE_MI_MODE, 1146 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1147 DELAY(80); 1148 } 1149 1150 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1151 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1152 1153 /* Poll for the PHY register access to complete. */ 1154 for (i = 0; i < BGE_TIMEOUT; i++) { 1155 DELAY(10); 1156 val = CSR_READ_4(sc, BGE_MI_COMM); 1157 if ((val & BGE_MICOMM_BUSY) == 0) { 1158 DELAY(5); 1159 val = CSR_READ_4(sc, BGE_MI_COMM); 1160 break; 1161 } 1162 } 1163 1164 if (i == BGE_TIMEOUT) { 1165 device_printf(sc->bge_dev, 1166 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1167 phy, reg, val); 1168 val = 0; 1169 } 1170 1171 /* Restore the autopoll bit if necessary. */ 1172 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1173 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1174 DELAY(80); 1175 } 1176 1177 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1178 1179 if (val & BGE_MICOMM_READFAIL) 1180 return (0); 1181 1182 return (val & 0xFFFF); 1183 } 1184 1185 static int 1186 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1187 { 1188 struct bge_softc *sc; 1189 int i; 1190 1191 sc = device_get_softc(dev); 1192 1193 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1194 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1195 return (0); 1196 1197 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1198 return (0); 1199 1200 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1201 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1202 CSR_WRITE_4(sc, BGE_MI_MODE, 1203 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1204 DELAY(80); 1205 } 1206 1207 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1208 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1209 1210 for (i = 0; i < BGE_TIMEOUT; i++) { 1211 DELAY(10); 1212 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1213 DELAY(5); 1214 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1215 break; 1216 } 1217 } 1218 1219 /* Restore the autopoll bit if necessary. */ 1220 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1221 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1222 DELAY(80); 1223 } 1224 1225 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1226 1227 if (i == BGE_TIMEOUT) 1228 device_printf(sc->bge_dev, 1229 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1230 phy, reg, val); 1231 1232 return (0); 1233 } 1234 1235 static void 1236 bge_miibus_statchg(device_t dev) 1237 { 1238 struct bge_softc *sc; 1239 struct mii_data *mii; 1240 uint32_t mac_mode, rx_mode, tx_mode; 1241 1242 sc = device_get_softc(dev); 1243 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1244 return; 1245 mii = device_get_softc(sc->bge_miibus); 1246 1247 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1248 (IFM_ACTIVE | IFM_AVALID)) { 1249 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1250 case IFM_10_T: 1251 case IFM_100_TX: 1252 sc->bge_link = 1; 1253 break; 1254 case IFM_1000_T: 1255 case IFM_1000_SX: 1256 case IFM_2500_SX: 1257 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1258 sc->bge_link = 1; 1259 else 1260 sc->bge_link = 0; 1261 break; 1262 default: 1263 sc->bge_link = 0; 1264 break; 1265 } 1266 } else 1267 sc->bge_link = 0; 1268 if (sc->bge_link == 0) 1269 return; 1270 1271 /* 1272 * APE firmware touches these registers to keep the MAC 1273 * connected to the outside world. Try to keep the 1274 * accesses atomic. 1275 */ 1276 1277 /* Set the port mode (MII/GMII) to match the link speed. */ 1278 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1279 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1280 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1281 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1282 1283 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1284 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1285 mac_mode |= BGE_PORTMODE_GMII; 1286 else 1287 mac_mode |= BGE_PORTMODE_MII; 1288 1289 /* Set MAC flow control behavior to match link flow control settings. */ 1290 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1291 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1292 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1293 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1294 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1295 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1296 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1297 } else 1298 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1299 1300 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1301 DELAY(40); 1302 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1303 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1304 } 1305 1306 /* 1307 * Intialize a standard receive ring descriptor. 1308 */ 1309 static int 1310 bge_newbuf_std(struct bge_softc *sc, int i) 1311 { 1312 struct mbuf *m; 1313 struct bge_rx_bd *r; 1314 bus_dma_segment_t segs[1]; 1315 bus_dmamap_t map; 1316 int error, nsegs; 1317 1318 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1319 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1320 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1321 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1322 if (m == NULL) 1323 return (ENOBUFS); 1324 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1325 } else { 1326 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1327 if (m == NULL) 1328 return (ENOBUFS); 1329 m->m_len = m->m_pkthdr.len = MCLBYTES; 1330 } 1331 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1332 m_adj(m, ETHER_ALIGN); 1333 1334 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1335 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1336 if (error != 0) { 1337 m_freem(m); 1338 return (error); 1339 } 1340 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1341 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1342 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1343 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1344 sc->bge_cdata.bge_rx_std_dmamap[i]); 1345 } 1346 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1347 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1348 sc->bge_cdata.bge_rx_std_sparemap = map; 1349 sc->bge_cdata.bge_rx_std_chain[i] = m; 1350 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1351 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1352 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1353 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1354 r->bge_flags = BGE_RXBDFLAG_END; 1355 r->bge_len = segs[0].ds_len; 1356 r->bge_idx = i; 1357 1358 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1359 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1360 1361 return (0); 1362 } 1363 1364 /* 1365 * Initialize a jumbo receive ring descriptor. This allocates 1366 * a jumbo buffer from the pool managed internally by the driver. 1367 */ 1368 static int 1369 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1370 { 1371 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1372 bus_dmamap_t map; 1373 struct bge_extrx_bd *r; 1374 struct mbuf *m; 1375 int error, nsegs; 1376 1377 MGETHDR(m, M_NOWAIT, MT_DATA); 1378 if (m == NULL) 1379 return (ENOBUFS); 1380 1381 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1382 if (!(m->m_flags & M_EXT)) { 1383 m_freem(m); 1384 return (ENOBUFS); 1385 } 1386 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1387 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1388 m_adj(m, ETHER_ALIGN); 1389 1390 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1391 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1392 if (error != 0) { 1393 m_freem(m); 1394 return (error); 1395 } 1396 1397 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1398 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1399 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1400 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1401 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1402 } 1403 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1404 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1405 sc->bge_cdata.bge_rx_jumbo_sparemap; 1406 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1407 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1408 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1409 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1410 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1411 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1412 1413 /* 1414 * Fill in the extended RX buffer descriptor. 1415 */ 1416 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1417 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1418 r->bge_idx = i; 1419 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1420 switch (nsegs) { 1421 case 4: 1422 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1423 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1424 r->bge_len3 = segs[3].ds_len; 1425 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1426 case 3: 1427 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1428 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1429 r->bge_len2 = segs[2].ds_len; 1430 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1431 case 2: 1432 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1433 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1434 r->bge_len1 = segs[1].ds_len; 1435 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1436 case 1: 1437 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1438 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1439 r->bge_len0 = segs[0].ds_len; 1440 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1441 break; 1442 default: 1443 panic("%s: %d segments\n", __func__, nsegs); 1444 } 1445 1446 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1447 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1448 1449 return (0); 1450 } 1451 1452 static int 1453 bge_init_rx_ring_std(struct bge_softc *sc) 1454 { 1455 int error, i; 1456 1457 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1458 sc->bge_std = 0; 1459 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1460 if ((error = bge_newbuf_std(sc, i)) != 0) 1461 return (error); 1462 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1463 } 1464 1465 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1466 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1467 1468 sc->bge_std = 0; 1469 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1470 1471 return (0); 1472 } 1473 1474 static void 1475 bge_free_rx_ring_std(struct bge_softc *sc) 1476 { 1477 int i; 1478 1479 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1480 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1481 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1482 sc->bge_cdata.bge_rx_std_dmamap[i], 1483 BUS_DMASYNC_POSTREAD); 1484 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1485 sc->bge_cdata.bge_rx_std_dmamap[i]); 1486 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1487 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1488 } 1489 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1490 sizeof(struct bge_rx_bd)); 1491 } 1492 } 1493 1494 static int 1495 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1496 { 1497 struct bge_rcb *rcb; 1498 int error, i; 1499 1500 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1501 sc->bge_jumbo = 0; 1502 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1503 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1504 return (error); 1505 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1506 } 1507 1508 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1509 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1510 1511 sc->bge_jumbo = 0; 1512 1513 /* Enable the jumbo receive producer ring. */ 1514 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1515 rcb->bge_maxlen_flags = 1516 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1517 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1518 1519 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1520 1521 return (0); 1522 } 1523 1524 static void 1525 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1526 { 1527 int i; 1528 1529 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1530 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1531 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1532 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1533 BUS_DMASYNC_POSTREAD); 1534 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1535 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1536 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1537 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1538 } 1539 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1540 sizeof(struct bge_extrx_bd)); 1541 } 1542 } 1543 1544 static void 1545 bge_free_tx_ring(struct bge_softc *sc) 1546 { 1547 int i; 1548 1549 if (sc->bge_ldata.bge_tx_ring == NULL) 1550 return; 1551 1552 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1553 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1554 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1555 sc->bge_cdata.bge_tx_dmamap[i], 1556 BUS_DMASYNC_POSTWRITE); 1557 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1558 sc->bge_cdata.bge_tx_dmamap[i]); 1559 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1560 sc->bge_cdata.bge_tx_chain[i] = NULL; 1561 } 1562 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1563 sizeof(struct bge_tx_bd)); 1564 } 1565 } 1566 1567 static int 1568 bge_init_tx_ring(struct bge_softc *sc) 1569 { 1570 sc->bge_txcnt = 0; 1571 sc->bge_tx_saved_considx = 0; 1572 1573 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1574 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1575 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1576 1577 /* Initialize transmit producer index for host-memory send ring. */ 1578 sc->bge_tx_prodidx = 0; 1579 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1580 1581 /* 5700 b2 errata */ 1582 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1583 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1584 1585 /* NIC-memory send ring not used; initialize to zero. */ 1586 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1587 /* 5700 b2 errata */ 1588 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1589 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1590 1591 return (0); 1592 } 1593 1594 static void 1595 bge_setpromisc(struct bge_softc *sc) 1596 { 1597 struct ifnet *ifp; 1598 1599 BGE_LOCK_ASSERT(sc); 1600 1601 ifp = sc->bge_ifp; 1602 1603 /* Enable or disable promiscuous mode as needed. */ 1604 if (ifp->if_flags & IFF_PROMISC) 1605 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1606 else 1607 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1608 } 1609 1610 static void 1611 bge_setmulti(struct bge_softc *sc) 1612 { 1613 struct ifnet *ifp; 1614 struct ifmultiaddr *ifma; 1615 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1616 int h, i; 1617 1618 BGE_LOCK_ASSERT(sc); 1619 1620 ifp = sc->bge_ifp; 1621 1622 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1623 for (i = 0; i < 4; i++) 1624 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1625 return; 1626 } 1627 1628 /* First, zot all the existing filters. */ 1629 for (i = 0; i < 4; i++) 1630 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1631 1632 /* Now program new ones. */ 1633 if_maddr_rlock(ifp); 1634 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1635 if (ifma->ifma_addr->sa_family != AF_LINK) 1636 continue; 1637 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1638 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1639 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1640 } 1641 if_maddr_runlock(ifp); 1642 1643 for (i = 0; i < 4; i++) 1644 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1645 } 1646 1647 static void 1648 bge_setvlan(struct bge_softc *sc) 1649 { 1650 struct ifnet *ifp; 1651 1652 BGE_LOCK_ASSERT(sc); 1653 1654 ifp = sc->bge_ifp; 1655 1656 /* Enable or disable VLAN tag stripping as needed. */ 1657 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1658 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1659 else 1660 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1661 } 1662 1663 static void 1664 bge_sig_pre_reset(struct bge_softc *sc, int type) 1665 { 1666 1667 /* 1668 * Some chips don't like this so only do this if ASF is enabled 1669 */ 1670 if (sc->bge_asf_mode) 1671 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1672 1673 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1674 switch (type) { 1675 case BGE_RESET_START: 1676 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1677 BGE_FW_DRV_STATE_START); 1678 break; 1679 case BGE_RESET_SHUTDOWN: 1680 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1681 BGE_FW_DRV_STATE_UNLOAD); 1682 break; 1683 case BGE_RESET_SUSPEND: 1684 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1685 BGE_FW_DRV_STATE_SUSPEND); 1686 break; 1687 } 1688 } 1689 1690 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1691 bge_ape_driver_state_change(sc, type); 1692 } 1693 1694 static void 1695 bge_sig_post_reset(struct bge_softc *sc, int type) 1696 { 1697 1698 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1699 switch (type) { 1700 case BGE_RESET_START: 1701 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1702 BGE_FW_DRV_STATE_START_DONE); 1703 /* START DONE */ 1704 break; 1705 case BGE_RESET_SHUTDOWN: 1706 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1707 BGE_FW_DRV_STATE_UNLOAD_DONE); 1708 break; 1709 } 1710 } 1711 if (type == BGE_RESET_SHUTDOWN) 1712 bge_ape_driver_state_change(sc, type); 1713 } 1714 1715 static void 1716 bge_sig_legacy(struct bge_softc *sc, int type) 1717 { 1718 1719 if (sc->bge_asf_mode) { 1720 switch (type) { 1721 case BGE_RESET_START: 1722 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1723 BGE_FW_DRV_STATE_START); 1724 break; 1725 case BGE_RESET_SHUTDOWN: 1726 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1727 BGE_FW_DRV_STATE_UNLOAD); 1728 break; 1729 } 1730 } 1731 } 1732 1733 static void 1734 bge_stop_fw(struct bge_softc *sc) 1735 { 1736 int i; 1737 1738 if (sc->bge_asf_mode) { 1739 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1740 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1741 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1742 1743 for (i = 0; i < 100; i++ ) { 1744 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1745 BGE_RX_CPU_DRV_EVENT)) 1746 break; 1747 DELAY(10); 1748 } 1749 } 1750 } 1751 1752 static uint32_t 1753 bge_dma_swap_options(struct bge_softc *sc) 1754 { 1755 uint32_t dma_options; 1756 1757 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1758 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1759 #if BYTE_ORDER == BIG_ENDIAN 1760 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1761 #endif 1762 return (dma_options); 1763 } 1764 1765 /* 1766 * Do endian, PCI and DMA initialization. 1767 */ 1768 static int 1769 bge_chipinit(struct bge_softc *sc) 1770 { 1771 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1772 uint16_t val; 1773 int i; 1774 1775 /* Set endianness before we access any non-PCI registers. */ 1776 misc_ctl = BGE_INIT; 1777 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1778 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1779 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1780 1781 /* 1782 * Clear the MAC statistics block in the NIC's 1783 * internal memory. 1784 */ 1785 for (i = BGE_STATS_BLOCK; 1786 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1787 BGE_MEMWIN_WRITE(sc, i, 0); 1788 1789 for (i = BGE_STATUS_BLOCK; 1790 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1791 BGE_MEMWIN_WRITE(sc, i, 0); 1792 1793 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1794 /* 1795 * Fix data corruption caused by non-qword write with WB. 1796 * Fix master abort in PCI mode. 1797 * Fix PCI latency timer. 1798 */ 1799 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1800 val |= (1 << 10) | (1 << 12) | (1 << 13); 1801 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1802 } 1803 1804 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1805 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1806 /* 1807 * For the 57766 and non Ax versions of 57765, bootcode 1808 * needs to setup the PCIE Fast Training Sequence (FTS) 1809 * value to prevent transmit hangs. 1810 */ 1811 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1812 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1813 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1814 BGE_CPMU_PADRNG_CTL_RDIV2); 1815 } 1816 } 1817 1818 /* 1819 * Set up the PCI DMA control register. 1820 */ 1821 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1822 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1823 if (sc->bge_flags & BGE_FLAG_PCIE) { 1824 if (sc->bge_mps >= 256) 1825 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1826 else 1827 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1828 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1829 if (BGE_IS_5714_FAMILY(sc)) { 1830 /* 256 bytes for read and write. */ 1831 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1832 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1833 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1834 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1835 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1836 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1837 /* 1838 * In the BCM5703, the DMA read watermark should 1839 * be set to less than or equal to the maximum 1840 * memory read byte count of the PCI-X command 1841 * register. 1842 */ 1843 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1844 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1845 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1846 /* 1536 bytes for read, 384 bytes for write. */ 1847 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1848 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1849 } else { 1850 /* 384 bytes for read and write. */ 1851 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1852 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1853 0x0F; 1854 } 1855 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1856 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1857 uint32_t tmp; 1858 1859 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1860 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1861 if (tmp == 6 || tmp == 7) 1862 dma_rw_ctl |= 1863 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1864 1865 /* Set PCI-X DMA write workaround. */ 1866 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1867 } 1868 } else { 1869 /* Conventional PCI bus: 256 bytes for read and write. */ 1870 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1871 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1872 1873 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1874 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1875 dma_rw_ctl |= 0x0F; 1876 } 1877 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1878 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1879 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1880 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1881 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1882 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1883 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1884 if (BGE_IS_5717_PLUS(sc)) { 1885 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1886 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1887 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1888 /* 1889 * Enable HW workaround for controllers that misinterpret 1890 * a status tag update and leave interrupts permanently 1891 * disabled. 1892 */ 1893 if (!BGE_IS_57765_PLUS(sc) && 1894 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1895 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1896 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1897 } 1898 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1899 1900 /* 1901 * Set up general mode register. 1902 */ 1903 mode_ctl = bge_dma_swap_options(sc); 1904 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1905 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1906 /* Retain Host-2-BMC settings written by APE firmware. */ 1907 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1908 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1909 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1910 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1911 } 1912 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1913 BGE_MODECTL_TX_NO_PHDR_CSUM; 1914 1915 /* 1916 * BCM5701 B5 have a bug causing data corruption when using 1917 * 64-bit DMA reads, which can be terminated early and then 1918 * completed later as 32-bit accesses, in combination with 1919 * certain bridges. 1920 */ 1921 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1922 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1923 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1924 1925 /* 1926 * Tell the firmware the driver is running 1927 */ 1928 if (sc->bge_asf_mode & ASF_STACKUP) 1929 mode_ctl |= BGE_MODECTL_STACKUP; 1930 1931 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1932 1933 /* 1934 * Disable memory write invalidate. Apparently it is not supported 1935 * properly by these devices. Also ensure that INTx isn't disabled, 1936 * as these chips need it even when using MSI. 1937 */ 1938 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1939 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1940 1941 /* Set the timer prescaler (always 66 MHz). */ 1942 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1943 1944 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1945 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1946 DELAY(40); /* XXX */ 1947 1948 /* Put PHY into ready state */ 1949 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1950 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1951 DELAY(40); 1952 } 1953 1954 return (0); 1955 } 1956 1957 static int 1958 bge_blockinit(struct bge_softc *sc) 1959 { 1960 struct bge_rcb *rcb; 1961 bus_size_t vrcb; 1962 bge_hostaddr taddr; 1963 uint32_t dmactl, rdmareg, val; 1964 int i, limit; 1965 1966 /* 1967 * Initialize the memory window pointer register so that 1968 * we can access the first 32K of internal NIC RAM. This will 1969 * allow us to set up the TX send ring RCBs and the RX return 1970 * ring RCBs, plus other things which live in NIC memory. 1971 */ 1972 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1973 1974 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1975 1976 if (!(BGE_IS_5705_PLUS(sc))) { 1977 /* Configure mbuf memory pool */ 1978 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1979 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1981 else 1982 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1983 1984 /* Configure DMA resource pool */ 1985 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1986 BGE_DMA_DESCRIPTORS); 1987 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1988 } 1989 1990 /* Configure mbuf pool watermarks */ 1991 if (BGE_IS_5717_PLUS(sc)) { 1992 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1993 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1994 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1995 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1996 } else { 1997 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1998 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1999 } 2000 } else if (!BGE_IS_5705_PLUS(sc)) { 2001 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2002 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2003 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2004 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2005 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2008 } else { 2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2012 } 2013 2014 /* Configure DMA resource watermarks */ 2015 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2016 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2017 2018 /* Enable buffer manager */ 2019 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2020 /* 2021 * Change the arbitration algorithm of TXMBUF read request to 2022 * round-robin instead of priority based for BCM5719. When 2023 * TXFIFO is almost empty, RDMA will hold its request until 2024 * TXFIFO is not almost empty. 2025 */ 2026 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2027 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2028 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2029 2030 /* Poll for buffer manager start indication */ 2031 for (i = 0; i < BGE_TIMEOUT; i++) { 2032 DELAY(10); 2033 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2034 break; 2035 } 2036 2037 if (i == BGE_TIMEOUT) { 2038 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2039 return (ENXIO); 2040 } 2041 2042 /* Enable flow-through queues */ 2043 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2044 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2045 2046 /* Wait until queue initialization is complete */ 2047 for (i = 0; i < BGE_TIMEOUT; i++) { 2048 DELAY(10); 2049 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2050 break; 2051 } 2052 2053 if (i == BGE_TIMEOUT) { 2054 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2055 return (ENXIO); 2056 } 2057 2058 /* 2059 * Summary of rings supported by the controller: 2060 * 2061 * Standard Receive Producer Ring 2062 * - This ring is used to feed receive buffers for "standard" 2063 * sized frames (typically 1536 bytes) to the controller. 2064 * 2065 * Jumbo Receive Producer Ring 2066 * - This ring is used to feed receive buffers for jumbo sized 2067 * frames (i.e. anything bigger than the "standard" frames) 2068 * to the controller. 2069 * 2070 * Mini Receive Producer Ring 2071 * - This ring is used to feed receive buffers for "mini" 2072 * sized frames to the controller. 2073 * - This feature required external memory for the controller 2074 * but was never used in a production system. Should always 2075 * be disabled. 2076 * 2077 * Receive Return Ring 2078 * - After the controller has placed an incoming frame into a 2079 * receive buffer that buffer is moved into a receive return 2080 * ring. The driver is then responsible to passing the 2081 * buffer up to the stack. Many versions of the controller 2082 * support multiple RR rings. 2083 * 2084 * Send Ring 2085 * - This ring is used for outgoing frames. Many versions of 2086 * the controller support multiple send rings. 2087 */ 2088 2089 /* Initialize the standard receive producer ring control block. */ 2090 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2091 rcb->bge_hostaddr.bge_addr_lo = 2092 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2093 rcb->bge_hostaddr.bge_addr_hi = 2094 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2095 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2096 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2097 if (BGE_IS_5717_PLUS(sc)) { 2098 /* 2099 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2100 * Bits 15-2 : Maximum RX frame size 2101 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2102 * Bit 0 : Reserved 2103 */ 2104 rcb->bge_maxlen_flags = 2105 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2106 } else if (BGE_IS_5705_PLUS(sc)) { 2107 /* 2108 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2109 * Bits 15-2 : Reserved (should be 0) 2110 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2111 * Bit 0 : Reserved 2112 */ 2113 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2114 } else { 2115 /* 2116 * Ring size is always XXX entries 2117 * Bits 31-16: Maximum RX frame size 2118 * Bits 15-2 : Reserved (should be 0) 2119 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2120 * Bit 0 : Reserved 2121 */ 2122 rcb->bge_maxlen_flags = 2123 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2124 } 2125 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2126 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2127 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2128 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2129 else 2130 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2131 /* Write the standard receive producer ring control block. */ 2132 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2133 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2134 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2135 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2136 2137 /* Reset the standard receive producer ring producer index. */ 2138 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2139 2140 /* 2141 * Initialize the jumbo RX producer ring control 2142 * block. We set the 'ring disabled' bit in the 2143 * flags field until we're actually ready to start 2144 * using this ring (i.e. once we set the MTU 2145 * high enough to require it). 2146 */ 2147 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2148 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2149 /* Get the jumbo receive producer ring RCB parameters. */ 2150 rcb->bge_hostaddr.bge_addr_lo = 2151 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2152 rcb->bge_hostaddr.bge_addr_hi = 2153 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2154 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2155 sc->bge_cdata.bge_rx_jumbo_ring_map, 2156 BUS_DMASYNC_PREREAD); 2157 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2158 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2159 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2160 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2161 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2162 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2163 else 2164 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2165 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2166 rcb->bge_hostaddr.bge_addr_hi); 2167 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2168 rcb->bge_hostaddr.bge_addr_lo); 2169 /* Program the jumbo receive producer ring RCB parameters. */ 2170 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2171 rcb->bge_maxlen_flags); 2172 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2173 /* Reset the jumbo receive producer ring producer index. */ 2174 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2175 } 2176 2177 /* Disable the mini receive producer ring RCB. */ 2178 if (BGE_IS_5700_FAMILY(sc)) { 2179 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2180 rcb->bge_maxlen_flags = 2181 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2182 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2183 rcb->bge_maxlen_flags); 2184 /* Reset the mini receive producer ring producer index. */ 2185 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2186 } 2187 2188 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2189 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2190 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2191 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2192 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2193 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2194 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2195 } 2196 /* 2197 * The BD ring replenish thresholds control how often the 2198 * hardware fetches new BD's from the producer rings in host 2199 * memory. Setting the value too low on a busy system can 2200 * starve the hardware and recue the throughpout. 2201 * 2202 * Set the BD ring replentish thresholds. The recommended 2203 * values are 1/8th the number of descriptors allocated to 2204 * each ring. 2205 * XXX The 5754 requires a lower threshold, so it might be a 2206 * requirement of all 575x family chips. The Linux driver sets 2207 * the lower threshold for all 5705 family chips as well, but there 2208 * are reports that it might not need to be so strict. 2209 * 2210 * XXX Linux does some extra fiddling here for the 5906 parts as 2211 * well. 2212 */ 2213 if (BGE_IS_5705_PLUS(sc)) 2214 val = 8; 2215 else 2216 val = BGE_STD_RX_RING_CNT / 8; 2217 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2218 if (BGE_IS_JUMBO_CAPABLE(sc)) 2219 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2220 BGE_JUMBO_RX_RING_CNT/8); 2221 if (BGE_IS_5717_PLUS(sc)) { 2222 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2223 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2224 } 2225 2226 /* 2227 * Disable all send rings by setting the 'ring disabled' bit 2228 * in the flags field of all the TX send ring control blocks, 2229 * located in NIC memory. 2230 */ 2231 if (!BGE_IS_5705_PLUS(sc)) 2232 /* 5700 to 5704 had 16 send rings. */ 2233 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2234 else if (BGE_IS_57765_PLUS(sc) || 2235 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2236 limit = 2; 2237 else if (BGE_IS_5717_PLUS(sc)) 2238 limit = 4; 2239 else 2240 limit = 1; 2241 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2242 for (i = 0; i < limit; i++) { 2243 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2244 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2245 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2246 vrcb += sizeof(struct bge_rcb); 2247 } 2248 2249 /* Configure send ring RCB 0 (we use only the first ring) */ 2250 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2251 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2252 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2253 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2254 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2255 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2256 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2257 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2258 else 2259 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2260 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2261 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2262 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2263 2264 /* 2265 * Disable all receive return rings by setting the 2266 * 'ring diabled' bit in the flags field of all the receive 2267 * return ring control blocks, located in NIC memory. 2268 */ 2269 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2270 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2271 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2272 /* Should be 17, use 16 until we get an SRAM map. */ 2273 limit = 16; 2274 } else if (!BGE_IS_5705_PLUS(sc)) 2275 limit = BGE_RX_RINGS_MAX; 2276 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2277 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2278 BGE_IS_57765_PLUS(sc)) 2279 limit = 4; 2280 else 2281 limit = 1; 2282 /* Disable all receive return rings. */ 2283 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2284 for (i = 0; i < limit; i++) { 2285 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2286 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2287 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2288 BGE_RCB_FLAG_RING_DISABLED); 2289 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2290 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2291 (i * (sizeof(uint64_t))), 0); 2292 vrcb += sizeof(struct bge_rcb); 2293 } 2294 2295 /* 2296 * Set up receive return ring 0. Note that the NIC address 2297 * for RX return rings is 0x0. The return rings live entirely 2298 * within the host, so the nicaddr field in the RCB isn't used. 2299 */ 2300 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2301 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2302 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2303 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2304 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2305 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2306 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2307 2308 /* Set random backoff seed for TX */ 2309 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2310 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2311 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2312 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2313 BGE_TX_BACKOFF_SEED_MASK); 2314 2315 /* Set inter-packet gap */ 2316 val = 0x2620; 2317 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2318 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2319 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2320 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2321 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2322 2323 /* 2324 * Specify which ring to use for packets that don't match 2325 * any RX rules. 2326 */ 2327 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2328 2329 /* 2330 * Configure number of RX lists. One interrupt distribution 2331 * list, sixteen active lists, one bad frames class. 2332 */ 2333 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2334 2335 /* Inialize RX list placement stats mask. */ 2336 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2337 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2338 2339 /* Disable host coalescing until we get it set up */ 2340 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2341 2342 /* Poll to make sure it's shut down. */ 2343 for (i = 0; i < BGE_TIMEOUT; i++) { 2344 DELAY(10); 2345 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2346 break; 2347 } 2348 2349 if (i == BGE_TIMEOUT) { 2350 device_printf(sc->bge_dev, 2351 "host coalescing engine failed to idle\n"); 2352 return (ENXIO); 2353 } 2354 2355 /* Set up host coalescing defaults */ 2356 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2357 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2358 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2359 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2360 if (!(BGE_IS_5705_PLUS(sc))) { 2361 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2362 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2363 } 2364 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2365 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2366 2367 /* Set up address of statistics block */ 2368 if (!(BGE_IS_5705_PLUS(sc))) { 2369 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2370 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2371 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2372 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2373 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2374 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2375 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2376 } 2377 2378 /* Set up address of status block */ 2379 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2380 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2381 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2382 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2383 2384 /* Set up status block size. */ 2385 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2386 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2387 val = BGE_STATBLKSZ_FULL; 2388 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2389 } else { 2390 val = BGE_STATBLKSZ_32BYTE; 2391 bzero(sc->bge_ldata.bge_status_block, 32); 2392 } 2393 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2394 sc->bge_cdata.bge_status_map, 2395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2396 2397 /* Turn on host coalescing state machine */ 2398 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2399 2400 /* Turn on RX BD completion state machine and enable attentions */ 2401 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2402 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2403 2404 /* Turn on RX list placement state machine */ 2405 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2406 2407 /* Turn on RX list selector state machine. */ 2408 if (!(BGE_IS_5705_PLUS(sc))) 2409 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2410 2411 /* Turn on DMA, clear stats. */ 2412 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2413 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2414 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2415 BGE_MACMODE_FRMHDR_DMA_ENB; 2416 2417 if (sc->bge_flags & BGE_FLAG_TBI) 2418 val |= BGE_PORTMODE_TBI; 2419 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2420 val |= BGE_PORTMODE_GMII; 2421 else 2422 val |= BGE_PORTMODE_MII; 2423 2424 /* Allow APE to send/receive frames. */ 2425 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2426 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2427 2428 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2429 DELAY(40); 2430 2431 /* Set misc. local control, enable interrupts on attentions */ 2432 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2433 2434 #ifdef notdef 2435 /* Assert GPIO pins for PHY reset */ 2436 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2437 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2438 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2439 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2440 #endif 2441 2442 /* Turn on DMA completion state machine */ 2443 if (!(BGE_IS_5705_PLUS(sc))) 2444 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2445 2446 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2447 2448 /* Enable host coalescing bug fix. */ 2449 if (BGE_IS_5755_PLUS(sc)) 2450 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2451 2452 /* Request larger DMA burst size to get better performance. */ 2453 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2454 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2455 2456 /* Turn on write DMA state machine */ 2457 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2458 DELAY(40); 2459 2460 /* Turn on read DMA state machine */ 2461 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2462 2463 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2464 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2465 2466 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2467 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2468 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2469 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2470 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2471 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2472 if (sc->bge_flags & BGE_FLAG_PCIE) 2473 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2474 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2475 val |= BGE_RDMAMODE_TSO4_ENABLE; 2476 if (sc->bge_flags & BGE_FLAG_TSO3 || 2477 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2478 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2479 val |= BGE_RDMAMODE_TSO6_ENABLE; 2480 } 2481 2482 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2483 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2484 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2485 BGE_RDMAMODE_H2BNC_VLAN_DET; 2486 /* 2487 * Allow multiple outstanding read requests from 2488 * non-LSO read DMA engine. 2489 */ 2490 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2491 } 2492 2493 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2494 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2495 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2496 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2497 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2498 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2499 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2500 else 2501 rdmareg = BGE_RDMA_RSRVCTRL; 2502 dmactl = CSR_READ_4(sc, rdmareg); 2503 /* 2504 * Adjust tx margin to prevent TX data corruption and 2505 * fix internal FIFO overflow. 2506 */ 2507 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2508 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2509 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2510 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2511 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2512 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2513 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2514 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2515 } 2516 /* 2517 * Enable fix for read DMA FIFO overruns. 2518 * The fix is to limit the number of RX BDs 2519 * the hardware would fetch at a fime. 2520 */ 2521 CSR_WRITE_4(sc, rdmareg, dmactl | 2522 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2523 } 2524 2525 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2526 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2527 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2528 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2529 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2530 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2531 /* 2532 * Allow 4KB burst length reads for non-LSO frames. 2533 * Enable 512B burst length reads for buffer descriptors. 2534 */ 2535 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2536 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2537 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2538 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2539 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2540 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2541 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2542 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2543 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2544 } 2545 2546 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2547 DELAY(40); 2548 2549 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2550 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2551 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2552 if ((val & 0xFFFF) > BGE_FRAMELEN) 2553 break; 2554 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2555 break; 2556 } 2557 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2558 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2559 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2560 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2561 else 2562 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2563 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2564 } 2565 } 2566 2567 /* Turn on RX data completion state machine */ 2568 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2569 2570 /* Turn on RX BD initiator state machine */ 2571 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2572 2573 /* Turn on RX data and RX BD initiator state machine */ 2574 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2575 2576 /* Turn on Mbuf cluster free state machine */ 2577 if (!(BGE_IS_5705_PLUS(sc))) 2578 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2579 2580 /* Turn on send BD completion state machine */ 2581 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2582 2583 /* Turn on send data completion state machine */ 2584 val = BGE_SDCMODE_ENABLE; 2585 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2586 val |= BGE_SDCMODE_CDELAY; 2587 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2588 2589 /* Turn on send data initiator state machine */ 2590 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2591 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2592 BGE_SDIMODE_HW_LSO_PRE_DMA); 2593 else 2594 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2595 2596 /* Turn on send BD initiator state machine */ 2597 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2598 2599 /* Turn on send BD selector state machine */ 2600 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2601 2602 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2603 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2604 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2605 2606 /* ack/clear link change events */ 2607 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2608 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2609 BGE_MACSTAT_LINK_CHANGED); 2610 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2611 2612 /* 2613 * Enable attention when the link has changed state for 2614 * devices that use auto polling. 2615 */ 2616 if (sc->bge_flags & BGE_FLAG_TBI) { 2617 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2618 } else { 2619 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2620 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2621 DELAY(80); 2622 } 2623 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2624 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2625 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2626 BGE_EVTENB_MI_INTERRUPT); 2627 } 2628 2629 /* 2630 * Clear any pending link state attention. 2631 * Otherwise some link state change events may be lost until attention 2632 * is cleared by bge_intr() -> bge_link_upd() sequence. 2633 * It's not necessary on newer BCM chips - perhaps enabling link 2634 * state change attentions implies clearing pending attention. 2635 */ 2636 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2637 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2638 BGE_MACSTAT_LINK_CHANGED); 2639 2640 /* Enable link state change attentions. */ 2641 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2642 2643 return (0); 2644 } 2645 2646 static const struct bge_revision * 2647 bge_lookup_rev(uint32_t chipid) 2648 { 2649 const struct bge_revision *br; 2650 2651 for (br = bge_revisions; br->br_name != NULL; br++) { 2652 if (br->br_chipid == chipid) 2653 return (br); 2654 } 2655 2656 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2657 if (br->br_chipid == BGE_ASICREV(chipid)) 2658 return (br); 2659 } 2660 2661 return (NULL); 2662 } 2663 2664 static const struct bge_vendor * 2665 bge_lookup_vendor(uint16_t vid) 2666 { 2667 const struct bge_vendor *v; 2668 2669 for (v = bge_vendors; v->v_name != NULL; v++) 2670 if (v->v_id == vid) 2671 return (v); 2672 2673 return (NULL); 2674 } 2675 2676 static uint32_t 2677 bge_chipid(device_t dev) 2678 { 2679 uint32_t id; 2680 2681 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2682 BGE_PCIMISCCTL_ASICREV_SHIFT; 2683 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2684 /* 2685 * Find the ASCI revision. Different chips use different 2686 * registers. 2687 */ 2688 switch (pci_get_device(dev)) { 2689 case BCOM_DEVICEID_BCM5717: 2690 case BCOM_DEVICEID_BCM5718: 2691 case BCOM_DEVICEID_BCM5719: 2692 case BCOM_DEVICEID_BCM5720: 2693 case BCOM_DEVICEID_BCM5725: 2694 case BCOM_DEVICEID_BCM5727: 2695 case BCOM_DEVICEID_BCM5762: 2696 id = pci_read_config(dev, 2697 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2698 break; 2699 case BCOM_DEVICEID_BCM57761: 2700 case BCOM_DEVICEID_BCM57762: 2701 case BCOM_DEVICEID_BCM57765: 2702 case BCOM_DEVICEID_BCM57766: 2703 case BCOM_DEVICEID_BCM57781: 2704 case BCOM_DEVICEID_BCM57785: 2705 case BCOM_DEVICEID_BCM57791: 2706 case BCOM_DEVICEID_BCM57795: 2707 id = pci_read_config(dev, 2708 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2709 break; 2710 default: 2711 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2712 } 2713 } 2714 return (id); 2715 } 2716 2717 /* 2718 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2719 * against our list and return its name if we find a match. 2720 * 2721 * Note that since the Broadcom controller contains VPD support, we 2722 * try to get the device name string from the controller itself instead 2723 * of the compiled-in string. It guarantees we'll always announce the 2724 * right product name. We fall back to the compiled-in string when 2725 * VPD is unavailable or corrupt. 2726 */ 2727 static int 2728 bge_probe(device_t dev) 2729 { 2730 char buf[96]; 2731 char model[64]; 2732 const struct bge_revision *br; 2733 const char *pname; 2734 struct bge_softc *sc; 2735 const struct bge_type *t = bge_devs; 2736 const struct bge_vendor *v; 2737 uint32_t id; 2738 uint16_t did, vid; 2739 2740 sc = device_get_softc(dev); 2741 sc->bge_dev = dev; 2742 vid = pci_get_vendor(dev); 2743 did = pci_get_device(dev); 2744 while(t->bge_vid != 0) { 2745 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2746 id = bge_chipid(dev); 2747 br = bge_lookup_rev(id); 2748 if (bge_has_eaddr(sc) && 2749 pci_get_vpd_ident(dev, &pname) == 0) 2750 snprintf(model, sizeof(model), "%s", pname); 2751 else { 2752 v = bge_lookup_vendor(vid); 2753 snprintf(model, sizeof(model), "%s %s", 2754 v != NULL ? v->v_name : "Unknown", 2755 br != NULL ? br->br_name : 2756 "NetXtreme/NetLink Ethernet Controller"); 2757 } 2758 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2759 model, br != NULL ? "" : "unknown ", id); 2760 device_set_desc_copy(dev, buf); 2761 return (BUS_PROBE_DEFAULT); 2762 } 2763 t++; 2764 } 2765 2766 return (ENXIO); 2767 } 2768 2769 static void 2770 bge_dma_free(struct bge_softc *sc) 2771 { 2772 int i; 2773 2774 /* Destroy DMA maps for RX buffers. */ 2775 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2776 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2777 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2778 sc->bge_cdata.bge_rx_std_dmamap[i]); 2779 } 2780 if (sc->bge_cdata.bge_rx_std_sparemap) 2781 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2782 sc->bge_cdata.bge_rx_std_sparemap); 2783 2784 /* Destroy DMA maps for jumbo RX buffers. */ 2785 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2786 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2787 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2788 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2789 } 2790 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2791 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2792 sc->bge_cdata.bge_rx_jumbo_sparemap); 2793 2794 /* Destroy DMA maps for TX buffers. */ 2795 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2796 if (sc->bge_cdata.bge_tx_dmamap[i]) 2797 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2798 sc->bge_cdata.bge_tx_dmamap[i]); 2799 } 2800 2801 if (sc->bge_cdata.bge_rx_mtag) 2802 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2803 if (sc->bge_cdata.bge_mtag_jumbo) 2804 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2805 if (sc->bge_cdata.bge_tx_mtag) 2806 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2807 2808 /* Destroy standard RX ring. */ 2809 if (sc->bge_cdata.bge_rx_std_ring_map) 2810 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2811 sc->bge_cdata.bge_rx_std_ring_map); 2812 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2813 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2814 sc->bge_ldata.bge_rx_std_ring, 2815 sc->bge_cdata.bge_rx_std_ring_map); 2816 2817 if (sc->bge_cdata.bge_rx_std_ring_tag) 2818 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2819 2820 /* Destroy jumbo RX ring. */ 2821 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2822 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2823 sc->bge_cdata.bge_rx_jumbo_ring_map); 2824 2825 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2826 sc->bge_ldata.bge_rx_jumbo_ring) 2827 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2828 sc->bge_ldata.bge_rx_jumbo_ring, 2829 sc->bge_cdata.bge_rx_jumbo_ring_map); 2830 2831 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2832 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2833 2834 /* Destroy RX return ring. */ 2835 if (sc->bge_cdata.bge_rx_return_ring_map) 2836 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2837 sc->bge_cdata.bge_rx_return_ring_map); 2838 2839 if (sc->bge_cdata.bge_rx_return_ring_map && 2840 sc->bge_ldata.bge_rx_return_ring) 2841 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2842 sc->bge_ldata.bge_rx_return_ring, 2843 sc->bge_cdata.bge_rx_return_ring_map); 2844 2845 if (sc->bge_cdata.bge_rx_return_ring_tag) 2846 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2847 2848 /* Destroy TX ring. */ 2849 if (sc->bge_cdata.bge_tx_ring_map) 2850 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2851 sc->bge_cdata.bge_tx_ring_map); 2852 2853 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2854 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2855 sc->bge_ldata.bge_tx_ring, 2856 sc->bge_cdata.bge_tx_ring_map); 2857 2858 if (sc->bge_cdata.bge_tx_ring_tag) 2859 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2860 2861 /* Destroy status block. */ 2862 if (sc->bge_cdata.bge_status_map) 2863 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2864 sc->bge_cdata.bge_status_map); 2865 2866 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2867 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2868 sc->bge_ldata.bge_status_block, 2869 sc->bge_cdata.bge_status_map); 2870 2871 if (sc->bge_cdata.bge_status_tag) 2872 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2873 2874 /* Destroy statistics block. */ 2875 if (sc->bge_cdata.bge_stats_map) 2876 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2877 sc->bge_cdata.bge_stats_map); 2878 2879 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2880 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2881 sc->bge_ldata.bge_stats, 2882 sc->bge_cdata.bge_stats_map); 2883 2884 if (sc->bge_cdata.bge_stats_tag) 2885 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2886 2887 if (sc->bge_cdata.bge_buffer_tag) 2888 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2889 2890 /* Destroy the parent tag. */ 2891 if (sc->bge_cdata.bge_parent_tag) 2892 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2893 } 2894 2895 static int 2896 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2897 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2898 bus_addr_t *paddr, const char *msg) 2899 { 2900 struct bge_dmamap_arg ctx; 2901 int error; 2902 2903 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2904 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2905 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2906 if (error != 0) { 2907 device_printf(sc->bge_dev, 2908 "could not create %s dma tag\n", msg); 2909 return (ENOMEM); 2910 } 2911 /* Allocate DMA'able memory for ring. */ 2912 error = bus_dmamem_alloc(*tag, (void **)ring, 2913 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2914 if (error != 0) { 2915 device_printf(sc->bge_dev, 2916 "could not allocate DMA'able memory for %s\n", msg); 2917 return (ENOMEM); 2918 } 2919 /* Load the address of the ring. */ 2920 ctx.bge_busaddr = 0; 2921 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2922 &ctx, BUS_DMA_NOWAIT); 2923 if (error != 0) { 2924 device_printf(sc->bge_dev, 2925 "could not load DMA'able memory for %s\n", msg); 2926 return (ENOMEM); 2927 } 2928 *paddr = ctx.bge_busaddr; 2929 return (0); 2930 } 2931 2932 static int 2933 bge_dma_alloc(struct bge_softc *sc) 2934 { 2935 bus_addr_t lowaddr; 2936 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2937 int i, error; 2938 2939 lowaddr = BUS_SPACE_MAXADDR; 2940 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2941 lowaddr = BGE_DMA_MAXADDR; 2942 /* 2943 * Allocate the parent bus DMA tag appropriate for PCI. 2944 */ 2945 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2946 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2947 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2948 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2949 if (error != 0) { 2950 device_printf(sc->bge_dev, 2951 "could not allocate parent dma tag\n"); 2952 return (ENOMEM); 2953 } 2954 2955 /* Create tag for standard RX ring. */ 2956 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2957 &sc->bge_cdata.bge_rx_std_ring_tag, 2958 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2959 &sc->bge_cdata.bge_rx_std_ring_map, 2960 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2961 if (error) 2962 return (error); 2963 2964 /* Create tag for RX return ring. */ 2965 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2966 &sc->bge_cdata.bge_rx_return_ring_tag, 2967 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2968 &sc->bge_cdata.bge_rx_return_ring_map, 2969 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2970 if (error) 2971 return (error); 2972 2973 /* Create tag for TX ring. */ 2974 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2975 &sc->bge_cdata.bge_tx_ring_tag, 2976 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2977 &sc->bge_cdata.bge_tx_ring_map, 2978 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2979 if (error) 2980 return (error); 2981 2982 /* 2983 * Create tag for status block. 2984 * Because we only use single Tx/Rx/Rx return ring, use 2985 * minimum status block size except BCM5700 AX/BX which 2986 * seems to want to see full status block size regardless 2987 * of configured number of ring. 2988 */ 2989 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2990 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2991 sbsz = BGE_STATUS_BLK_SZ; 2992 else 2993 sbsz = 32; 2994 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2995 &sc->bge_cdata.bge_status_tag, 2996 (uint8_t **)&sc->bge_ldata.bge_status_block, 2997 &sc->bge_cdata.bge_status_map, 2998 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2999 if (error) 3000 return (error); 3001 3002 /* Create tag for statistics block. */ 3003 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3004 &sc->bge_cdata.bge_stats_tag, 3005 (uint8_t **)&sc->bge_ldata.bge_stats, 3006 &sc->bge_cdata.bge_stats_map, 3007 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3008 if (error) 3009 return (error); 3010 3011 /* Create tag for jumbo RX ring. */ 3012 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3013 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3014 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3015 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3016 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3017 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3018 if (error) 3019 return (error); 3020 } 3021 3022 /* Create parent tag for buffers. */ 3023 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3024 /* 3025 * XXX 3026 * watchdog timeout issue was observed on BCM5704 which 3027 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3028 * Both limiting DMA address space to 32bits and flushing 3029 * mailbox write seem to address the issue. 3030 */ 3031 if (sc->bge_pcixcap != 0) 3032 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3033 } 3034 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3035 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3036 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3037 &sc->bge_cdata.bge_buffer_tag); 3038 if (error != 0) { 3039 device_printf(sc->bge_dev, 3040 "could not allocate buffer dma tag\n"); 3041 return (ENOMEM); 3042 } 3043 /* Create tag for Tx mbufs. */ 3044 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3045 txsegsz = BGE_TSOSEG_SZ; 3046 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3047 } else { 3048 txsegsz = MCLBYTES; 3049 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3050 } 3051 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3052 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3053 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3054 &sc->bge_cdata.bge_tx_mtag); 3055 3056 if (error) { 3057 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3058 return (ENOMEM); 3059 } 3060 3061 /* Create tag for Rx mbufs. */ 3062 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3063 rxmaxsegsz = MJUM9BYTES; 3064 else 3065 rxmaxsegsz = MCLBYTES; 3066 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3067 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3068 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3069 3070 if (error) { 3071 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3072 return (ENOMEM); 3073 } 3074 3075 /* Create DMA maps for RX buffers. */ 3076 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3077 &sc->bge_cdata.bge_rx_std_sparemap); 3078 if (error) { 3079 device_printf(sc->bge_dev, 3080 "can't create spare DMA map for RX\n"); 3081 return (ENOMEM); 3082 } 3083 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3084 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3085 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3086 if (error) { 3087 device_printf(sc->bge_dev, 3088 "can't create DMA map for RX\n"); 3089 return (ENOMEM); 3090 } 3091 } 3092 3093 /* Create DMA maps for TX buffers. */ 3094 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3095 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3096 &sc->bge_cdata.bge_tx_dmamap[i]); 3097 if (error) { 3098 device_printf(sc->bge_dev, 3099 "can't create DMA map for TX\n"); 3100 return (ENOMEM); 3101 } 3102 } 3103 3104 /* Create tags for jumbo RX buffers. */ 3105 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3106 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3107 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3108 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3109 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3110 if (error) { 3111 device_printf(sc->bge_dev, 3112 "could not allocate jumbo dma tag\n"); 3113 return (ENOMEM); 3114 } 3115 /* Create DMA maps for jumbo RX buffers. */ 3116 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3117 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3118 if (error) { 3119 device_printf(sc->bge_dev, 3120 "can't create spare DMA map for jumbo RX\n"); 3121 return (ENOMEM); 3122 } 3123 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3124 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3125 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3126 if (error) { 3127 device_printf(sc->bge_dev, 3128 "can't create DMA map for jumbo RX\n"); 3129 return (ENOMEM); 3130 } 3131 } 3132 } 3133 3134 return (0); 3135 } 3136 3137 /* 3138 * Return true if this device has more than one port. 3139 */ 3140 static int 3141 bge_has_multiple_ports(struct bge_softc *sc) 3142 { 3143 device_t dev = sc->bge_dev; 3144 u_int b, d, f, fscan, s; 3145 3146 d = pci_get_domain(dev); 3147 b = pci_get_bus(dev); 3148 s = pci_get_slot(dev); 3149 f = pci_get_function(dev); 3150 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3151 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3152 return (1); 3153 return (0); 3154 } 3155 3156 /* 3157 * Return true if MSI can be used with this device. 3158 */ 3159 static int 3160 bge_can_use_msi(struct bge_softc *sc) 3161 { 3162 int can_use_msi = 0; 3163 3164 if (sc->bge_msi == 0) 3165 return (0); 3166 3167 /* Disable MSI for polling(4). */ 3168 #ifdef DEVICE_POLLING 3169 return (0); 3170 #endif 3171 switch (sc->bge_asicrev) { 3172 case BGE_ASICREV_BCM5714_A0: 3173 case BGE_ASICREV_BCM5714: 3174 /* 3175 * Apparently, MSI doesn't work when these chips are 3176 * configured in single-port mode. 3177 */ 3178 if (bge_has_multiple_ports(sc)) 3179 can_use_msi = 1; 3180 break; 3181 case BGE_ASICREV_BCM5750: 3182 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3183 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3184 can_use_msi = 1; 3185 break; 3186 default: 3187 if (BGE_IS_575X_PLUS(sc)) 3188 can_use_msi = 1; 3189 } 3190 return (can_use_msi); 3191 } 3192 3193 static int 3194 bge_mbox_reorder(struct bge_softc *sc) 3195 { 3196 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3197 static const struct mbox_reorder { 3198 const uint16_t vendor; 3199 const uint16_t device; 3200 const char *desc; 3201 } mbox_reorder_lists[] = { 3202 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3203 }; 3204 devclass_t pci, pcib; 3205 device_t bus, dev; 3206 int i; 3207 3208 pci = devclass_find("pci"); 3209 pcib = devclass_find("pcib"); 3210 dev = sc->bge_dev; 3211 bus = device_get_parent(dev); 3212 for (;;) { 3213 dev = device_get_parent(bus); 3214 bus = device_get_parent(dev); 3215 if (device_get_devclass(dev) != pcib) 3216 break; 3217 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3218 if (pci_get_vendor(dev) == 3219 mbox_reorder_lists[i].vendor && 3220 pci_get_device(dev) == 3221 mbox_reorder_lists[i].device) { 3222 device_printf(sc->bge_dev, 3223 "enabling MBOX workaround for %s\n", 3224 mbox_reorder_lists[i].desc); 3225 return (1); 3226 } 3227 } 3228 if (device_get_devclass(bus) != pci) 3229 break; 3230 } 3231 return (0); 3232 } 3233 3234 static void 3235 bge_devinfo(struct bge_softc *sc) 3236 { 3237 uint32_t cfg, clk; 3238 3239 device_printf(sc->bge_dev, 3240 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3241 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3242 if (sc->bge_flags & BGE_FLAG_PCIE) 3243 printf("PCI-E\n"); 3244 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3245 printf("PCI-X "); 3246 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3247 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3248 clk = 133; 3249 else { 3250 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3251 switch (clk) { 3252 case 0: 3253 clk = 33; 3254 break; 3255 case 2: 3256 clk = 50; 3257 break; 3258 case 4: 3259 clk = 66; 3260 break; 3261 case 6: 3262 clk = 100; 3263 break; 3264 case 7: 3265 clk = 133; 3266 break; 3267 } 3268 } 3269 printf("%u MHz\n", clk); 3270 } else { 3271 if (sc->bge_pcixcap != 0) 3272 printf("PCI on PCI-X "); 3273 else 3274 printf("PCI "); 3275 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3276 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3277 clk = 66; 3278 else 3279 clk = 33; 3280 if (cfg & BGE_PCISTATE_32BIT_BUS) 3281 printf("%u MHz; 32bit\n", clk); 3282 else 3283 printf("%u MHz; 64bit\n", clk); 3284 } 3285 } 3286 3287 static int 3288 bge_attach(device_t dev) 3289 { 3290 struct ifnet *ifp; 3291 struct bge_softc *sc; 3292 uint32_t hwcfg = 0, misccfg, pcistate; 3293 u_char eaddr[ETHER_ADDR_LEN]; 3294 int capmask, error, msicount, reg, rid, trys; 3295 3296 sc = device_get_softc(dev); 3297 sc->bge_dev = dev; 3298 3299 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3300 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3301 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3302 3303 /* 3304 * Map control/status registers. 3305 */ 3306 pci_enable_busmaster(dev); 3307 3308 rid = PCIR_BAR(0); 3309 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3310 RF_ACTIVE); 3311 3312 if (sc->bge_res == NULL) { 3313 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3314 error = ENXIO; 3315 goto fail; 3316 } 3317 3318 /* Save various chip information. */ 3319 sc->bge_func_addr = pci_get_function(dev); 3320 sc->bge_chipid = bge_chipid(dev); 3321 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3322 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3323 3324 /* Set default PHY address. */ 3325 sc->bge_phy_addr = 1; 3326 /* 3327 * PHY address mapping for various devices. 3328 * 3329 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3330 * ---------+-------+-------+-------+-------+ 3331 * BCM57XX | 1 | X | X | X | 3332 * BCM5704 | 1 | X | 1 | X | 3333 * BCM5717 | 1 | 8 | 2 | 9 | 3334 * BCM5719 | 1 | 8 | 2 | 9 | 3335 * BCM5720 | 1 | 8 | 2 | 9 | 3336 * 3337 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3338 * ---------+-------+-------+-------+-------+ 3339 * BCM57XX | X | X | X | X | 3340 * BCM5704 | X | X | X | X | 3341 * BCM5717 | X | X | X | X | 3342 * BCM5719 | 3 | 10 | 4 | 11 | 3343 * BCM5720 | X | X | X | X | 3344 * 3345 * Other addresses may respond but they are not 3346 * IEEE compliant PHYs and should be ignored. 3347 */ 3348 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3349 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3350 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3351 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3352 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3353 BGE_SGDIGSTS_IS_SERDES) 3354 sc->bge_phy_addr = sc->bge_func_addr + 8; 3355 else 3356 sc->bge_phy_addr = sc->bge_func_addr + 1; 3357 } else { 3358 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3359 BGE_CPMU_PHY_STRAP_IS_SERDES) 3360 sc->bge_phy_addr = sc->bge_func_addr + 8; 3361 else 3362 sc->bge_phy_addr = sc->bge_func_addr + 1; 3363 } 3364 } 3365 3366 if (bge_has_eaddr(sc)) 3367 sc->bge_flags |= BGE_FLAG_EADDR; 3368 3369 /* Save chipset family. */ 3370 switch (sc->bge_asicrev) { 3371 case BGE_ASICREV_BCM5762: 3372 case BGE_ASICREV_BCM57765: 3373 case BGE_ASICREV_BCM57766: 3374 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3375 /* FALLTHROUGH */ 3376 case BGE_ASICREV_BCM5717: 3377 case BGE_ASICREV_BCM5719: 3378 case BGE_ASICREV_BCM5720: 3379 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3380 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3381 BGE_FLAG_JUMBO_FRAME; 3382 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3383 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3384 /* 3385 * Enable work around for DMA engine miscalculation 3386 * of TXMBUF available space. 3387 */ 3388 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3389 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3390 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3391 /* Jumbo frame on BCM5719 A0 does not work. */ 3392 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3393 } 3394 } 3395 break; 3396 case BGE_ASICREV_BCM5755: 3397 case BGE_ASICREV_BCM5761: 3398 case BGE_ASICREV_BCM5784: 3399 case BGE_ASICREV_BCM5785: 3400 case BGE_ASICREV_BCM5787: 3401 case BGE_ASICREV_BCM57780: 3402 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3403 BGE_FLAG_5705_PLUS; 3404 break; 3405 case BGE_ASICREV_BCM5700: 3406 case BGE_ASICREV_BCM5701: 3407 case BGE_ASICREV_BCM5703: 3408 case BGE_ASICREV_BCM5704: 3409 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3410 break; 3411 case BGE_ASICREV_BCM5714_A0: 3412 case BGE_ASICREV_BCM5780: 3413 case BGE_ASICREV_BCM5714: 3414 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3415 /* FALLTHROUGH */ 3416 case BGE_ASICREV_BCM5750: 3417 case BGE_ASICREV_BCM5752: 3418 case BGE_ASICREV_BCM5906: 3419 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3420 /* FALLTHROUGH */ 3421 case BGE_ASICREV_BCM5705: 3422 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3423 break; 3424 } 3425 3426 /* Identify chips with APE processor. */ 3427 switch (sc->bge_asicrev) { 3428 case BGE_ASICREV_BCM5717: 3429 case BGE_ASICREV_BCM5719: 3430 case BGE_ASICREV_BCM5720: 3431 case BGE_ASICREV_BCM5761: 3432 case BGE_ASICREV_BCM5762: 3433 sc->bge_flags |= BGE_FLAG_APE; 3434 break; 3435 } 3436 3437 /* Chips with APE need BAR2 access for APE registers/memory. */ 3438 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3439 rid = PCIR_BAR(2); 3440 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3441 RF_ACTIVE); 3442 if (sc->bge_res2 == NULL) { 3443 device_printf (sc->bge_dev, 3444 "couldn't map BAR2 memory\n"); 3445 error = ENXIO; 3446 goto fail; 3447 } 3448 3449 /* Enable APE register/memory access by host driver. */ 3450 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3451 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3452 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3453 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3454 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3455 3456 bge_ape_lock_init(sc); 3457 bge_ape_read_fw_ver(sc); 3458 } 3459 3460 /* Add SYSCTLs, requires the chipset family to be set. */ 3461 bge_add_sysctls(sc); 3462 3463 /* Identify the chips that use an CPMU. */ 3464 if (BGE_IS_5717_PLUS(sc) || 3465 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3466 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3467 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3468 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3469 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3470 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3471 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3472 else 3473 sc->bge_mi_mode = BGE_MIMODE_BASE; 3474 /* Enable auto polling for BCM570[0-5]. */ 3475 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3476 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3477 3478 /* 3479 * All Broadcom controllers have 4GB boundary DMA bug. 3480 * Whenever an address crosses a multiple of the 4GB boundary 3481 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3482 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3483 * state machine will lockup and cause the device to hang. 3484 */ 3485 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3486 3487 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3488 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3489 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3490 3491 /* 3492 * BCM5719 cannot handle DMA requests for DMA segments that 3493 * have larger than 4KB in size. However the maximum DMA 3494 * segment size created in DMA tag is 4KB for TSO, so we 3495 * wouldn't encounter the issue here. 3496 */ 3497 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3498 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3499 3500 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3501 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3502 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3503 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3504 sc->bge_flags |= BGE_FLAG_5788; 3505 } 3506 3507 capmask = BMSR_DEFCAPMASK; 3508 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3509 (misccfg == 0x4000 || misccfg == 0x8000)) || 3510 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3511 pci_get_vendor(dev) == BCOM_VENDORID && 3512 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3513 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3514 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3515 (pci_get_vendor(dev) == BCOM_VENDORID && 3516 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3517 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3518 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3519 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3520 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3521 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3522 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3523 /* These chips are 10/100 only. */ 3524 capmask &= ~BMSR_EXTSTAT; 3525 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3526 } 3527 3528 /* 3529 * Some controllers seem to require a special firmware to use 3530 * TSO. But the firmware is not available to FreeBSD and Linux 3531 * claims that the TSO performed by the firmware is slower than 3532 * hardware based TSO. Moreover the firmware based TSO has one 3533 * known bug which can't handle TSO if Ethernet header + IP/TCP 3534 * header is greater than 80 bytes. A workaround for the TSO 3535 * bug exist but it seems it's too expensive than not using 3536 * TSO at all. Some hardwares also have the TSO bug so limit 3537 * the TSO to the controllers that are not affected TSO issues 3538 * (e.g. 5755 or higher). 3539 */ 3540 if (BGE_IS_5717_PLUS(sc)) { 3541 /* BCM5717 requires different TSO configuration. */ 3542 sc->bge_flags |= BGE_FLAG_TSO3; 3543 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3544 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3545 /* TSO on BCM5719 A0 does not work. */ 3546 sc->bge_flags &= ~BGE_FLAG_TSO3; 3547 } 3548 } else if (BGE_IS_5755_PLUS(sc)) { 3549 /* 3550 * BCM5754 and BCM5787 shares the same ASIC id so 3551 * explicit device id check is required. 3552 * Due to unknown reason TSO does not work on BCM5755M. 3553 */ 3554 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3555 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3556 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3557 sc->bge_flags |= BGE_FLAG_TSO; 3558 } 3559 3560 /* 3561 * Check if this is a PCI-X or PCI Express device. 3562 */ 3563 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3564 /* 3565 * Found a PCI Express capabilities register, this 3566 * must be a PCI Express device. 3567 */ 3568 sc->bge_flags |= BGE_FLAG_PCIE; 3569 sc->bge_expcap = reg; 3570 /* Extract supported maximum payload size. */ 3571 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3572 PCIER_DEVICE_CAP, 2); 3573 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3574 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3575 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3576 sc->bge_expmrq = 2048; 3577 else 3578 sc->bge_expmrq = 4096; 3579 pci_set_max_read_req(dev, sc->bge_expmrq); 3580 } else { 3581 /* 3582 * Check if the device is in PCI-X Mode. 3583 * (This bit is not valid on PCI Express controllers.) 3584 */ 3585 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3586 sc->bge_pcixcap = reg; 3587 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3588 BGE_PCISTATE_PCI_BUSMODE) == 0) 3589 sc->bge_flags |= BGE_FLAG_PCIX; 3590 } 3591 3592 /* 3593 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3594 * not actually a MAC controller bug but an issue with the embedded 3595 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3596 */ 3597 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3598 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3599 /* 3600 * Some PCI-X bridges are known to trigger write reordering to 3601 * the mailbox registers. Typical phenomena is watchdog timeouts 3602 * caused by out-of-order TX completions. Enable workaround for 3603 * PCI-X devices that live behind these bridges. 3604 * Note, PCI-X controllers can run in PCI mode so we can't use 3605 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3606 */ 3607 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3608 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3609 /* 3610 * Allocate the interrupt, using MSI if possible. These devices 3611 * support 8 MSI messages, but only the first one is used in 3612 * normal operation. 3613 */ 3614 rid = 0; 3615 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3616 sc->bge_msicap = reg; 3617 if (bge_can_use_msi(sc)) { 3618 msicount = pci_msi_count(dev); 3619 if (msicount > 1) 3620 msicount = 1; 3621 } else 3622 msicount = 0; 3623 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3624 rid = 1; 3625 sc->bge_flags |= BGE_FLAG_MSI; 3626 } 3627 } 3628 3629 /* 3630 * All controllers except BCM5700 supports tagged status but 3631 * we use tagged status only for MSI case on BCM5717. Otherwise 3632 * MSI on BCM5717 does not work. 3633 */ 3634 #ifndef DEVICE_POLLING 3635 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3636 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3637 #endif 3638 3639 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3640 RF_SHAREABLE | RF_ACTIVE); 3641 3642 if (sc->bge_irq == NULL) { 3643 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3644 error = ENXIO; 3645 goto fail; 3646 } 3647 3648 bge_devinfo(sc); 3649 3650 sc->bge_asf_mode = 0; 3651 /* No ASF if APE present. */ 3652 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3653 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3654 BGE_SRAM_DATA_SIG_MAGIC)) { 3655 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3656 BGE_HWCFG_ASF) { 3657 sc->bge_asf_mode |= ASF_ENABLE; 3658 sc->bge_asf_mode |= ASF_STACKUP; 3659 if (BGE_IS_575X_PLUS(sc)) 3660 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3661 } 3662 } 3663 } 3664 3665 bge_stop_fw(sc); 3666 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3667 if (bge_reset(sc)) { 3668 device_printf(sc->bge_dev, "chip reset failed\n"); 3669 error = ENXIO; 3670 goto fail; 3671 } 3672 3673 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3674 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3675 3676 if (bge_chipinit(sc)) { 3677 device_printf(sc->bge_dev, "chip initialization failed\n"); 3678 error = ENXIO; 3679 goto fail; 3680 } 3681 3682 error = bge_get_eaddr(sc, eaddr); 3683 if (error) { 3684 device_printf(sc->bge_dev, 3685 "failed to read station address\n"); 3686 error = ENXIO; 3687 goto fail; 3688 } 3689 3690 /* 5705 limits RX return ring to 512 entries. */ 3691 if (BGE_IS_5717_PLUS(sc)) 3692 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3693 else if (BGE_IS_5705_PLUS(sc)) 3694 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3695 else 3696 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3697 3698 if (bge_dma_alloc(sc)) { 3699 device_printf(sc->bge_dev, 3700 "failed to allocate DMA resources\n"); 3701 error = ENXIO; 3702 goto fail; 3703 } 3704 3705 /* Set default tuneable values. */ 3706 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3707 sc->bge_rx_coal_ticks = 150; 3708 sc->bge_tx_coal_ticks = 150; 3709 sc->bge_rx_max_coal_bds = 10; 3710 sc->bge_tx_max_coal_bds = 10; 3711 3712 /* Initialize checksum features to use. */ 3713 sc->bge_csum_features = BGE_CSUM_FEATURES; 3714 if (sc->bge_forced_udpcsum != 0) 3715 sc->bge_csum_features |= CSUM_UDP; 3716 3717 /* Set up ifnet structure */ 3718 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3719 if (ifp == NULL) { 3720 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3721 error = ENXIO; 3722 goto fail; 3723 } 3724 ifp->if_softc = sc; 3725 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3726 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3727 ifp->if_ioctl = bge_ioctl; 3728 ifp->if_start = bge_start; 3729 ifp->if_init = bge_init; 3730 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3731 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3732 IFQ_SET_READY(&ifp->if_snd); 3733 ifp->if_hwassist = sc->bge_csum_features; 3734 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3735 IFCAP_VLAN_MTU; 3736 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3737 ifp->if_hwassist |= CSUM_TSO; 3738 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3739 } 3740 #ifdef IFCAP_VLAN_HWCSUM 3741 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3742 #endif 3743 ifp->if_capenable = ifp->if_capabilities; 3744 #ifdef DEVICE_POLLING 3745 ifp->if_capabilities |= IFCAP_POLLING; 3746 #endif 3747 3748 /* 3749 * 5700 B0 chips do not support checksumming correctly due 3750 * to hardware bugs. 3751 */ 3752 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3753 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3754 ifp->if_capenable &= ~IFCAP_HWCSUM; 3755 ifp->if_hwassist = 0; 3756 } 3757 3758 /* 3759 * Figure out what sort of media we have by checking the 3760 * hardware config word in the first 32k of NIC internal memory, 3761 * or fall back to examining the EEPROM if necessary. 3762 * Note: on some BCM5700 cards, this value appears to be unset. 3763 * If that's the case, we have to rely on identifying the NIC 3764 * by its PCI subsystem ID, as we do below for the SysKonnect 3765 * SK-9D41. 3766 */ 3767 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3768 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3769 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3770 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3771 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3772 sizeof(hwcfg))) { 3773 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3774 error = ENXIO; 3775 goto fail; 3776 } 3777 hwcfg = ntohl(hwcfg); 3778 } 3779 3780 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3781 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3782 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3783 if (BGE_IS_5705_PLUS(sc)) { 3784 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3785 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3786 } else 3787 sc->bge_flags |= BGE_FLAG_TBI; 3788 } 3789 3790 /* Set various PHY bug flags. */ 3791 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3792 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3793 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3794 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3795 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3796 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3797 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3798 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3799 if (pci_get_subvendor(dev) == DELL_VENDORID) 3800 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3801 if ((BGE_IS_5705_PLUS(sc)) && 3802 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3803 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3804 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3805 !BGE_IS_5717_PLUS(sc)) { 3806 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3807 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3808 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3809 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3810 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3811 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3812 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3813 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3814 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3815 } else 3816 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3817 } 3818 3819 /* 3820 * Don't enable Ethernet@WireSpeed for the 5700 or the 3821 * 5705 A0 and A1 chips. 3822 */ 3823 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3824 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3825 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3826 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3827 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3828 3829 if (sc->bge_flags & BGE_FLAG_TBI) { 3830 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3831 bge_ifmedia_sts); 3832 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3833 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3834 0, NULL); 3835 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3836 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3837 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3838 } else { 3839 /* 3840 * Do transceiver setup and tell the firmware the 3841 * driver is down so we can try to get access the 3842 * probe if ASF is running. Retry a couple of times 3843 * if we get a conflict with the ASF firmware accessing 3844 * the PHY. 3845 */ 3846 trys = 0; 3847 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3848 again: 3849 bge_asf_driver_up(sc); 3850 3851 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3852 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3853 MIIF_DOPAUSE); 3854 if (error != 0) { 3855 if (trys++ < 4) { 3856 device_printf(sc->bge_dev, "Try again\n"); 3857 bge_miibus_writereg(sc->bge_dev, 3858 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3859 goto again; 3860 } 3861 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3862 goto fail; 3863 } 3864 3865 /* 3866 * Now tell the firmware we are going up after probing the PHY 3867 */ 3868 if (sc->bge_asf_mode & ASF_STACKUP) 3869 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3870 } 3871 3872 /* 3873 * When using the BCM5701 in PCI-X mode, data corruption has 3874 * been observed in the first few bytes of some received packets. 3875 * Aligning the packet buffer in memory eliminates the corruption. 3876 * Unfortunately, this misaligns the packet payloads. On platforms 3877 * which do not support unaligned accesses, we will realign the 3878 * payloads by copying the received packets. 3879 */ 3880 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3881 sc->bge_flags & BGE_FLAG_PCIX) 3882 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3883 3884 /* 3885 * Call MI attach routine. 3886 */ 3887 ether_ifattach(ifp, eaddr); 3888 3889 /* Tell upper layer we support long frames. */ 3890 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3891 3892 /* 3893 * Hookup IRQ last. 3894 */ 3895 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3896 /* Take advantage of single-shot MSI. */ 3897 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3898 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3899 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3900 taskqueue_thread_enqueue, &sc->bge_tq); 3901 if (sc->bge_tq == NULL) { 3902 device_printf(dev, "could not create taskqueue.\n"); 3903 ether_ifdetach(ifp); 3904 error = ENOMEM; 3905 goto fail; 3906 } 3907 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3908 "%s taskq", device_get_nameunit(sc->bge_dev)); 3909 if (error != 0) { 3910 device_printf(dev, "could not start threads.\n"); 3911 ether_ifdetach(ifp); 3912 goto fail; 3913 } 3914 error = bus_setup_intr(dev, sc->bge_irq, 3915 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3916 &sc->bge_intrhand); 3917 } else 3918 error = bus_setup_intr(dev, sc->bge_irq, 3919 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3920 &sc->bge_intrhand); 3921 3922 if (error) { 3923 ether_ifdetach(ifp); 3924 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3925 } 3926 3927 fail: 3928 if (error) 3929 bge_detach(dev); 3930 return (error); 3931 } 3932 3933 static int 3934 bge_detach(device_t dev) 3935 { 3936 struct bge_softc *sc; 3937 struct ifnet *ifp; 3938 3939 sc = device_get_softc(dev); 3940 ifp = sc->bge_ifp; 3941 3942 #ifdef DEVICE_POLLING 3943 if (ifp->if_capenable & IFCAP_POLLING) 3944 ether_poll_deregister(ifp); 3945 #endif 3946 3947 if (device_is_attached(dev)) { 3948 ether_ifdetach(ifp); 3949 BGE_LOCK(sc); 3950 bge_stop(sc); 3951 BGE_UNLOCK(sc); 3952 callout_drain(&sc->bge_stat_ch); 3953 } 3954 3955 if (sc->bge_tq) 3956 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3957 3958 if (sc->bge_flags & BGE_FLAG_TBI) 3959 ifmedia_removeall(&sc->bge_ifmedia); 3960 else if (sc->bge_miibus != NULL) { 3961 bus_generic_detach(dev); 3962 device_delete_child(dev, sc->bge_miibus); 3963 } 3964 3965 bge_release_resources(sc); 3966 3967 return (0); 3968 } 3969 3970 static void 3971 bge_release_resources(struct bge_softc *sc) 3972 { 3973 device_t dev; 3974 3975 dev = sc->bge_dev; 3976 3977 if (sc->bge_tq != NULL) 3978 taskqueue_free(sc->bge_tq); 3979 3980 if (sc->bge_intrhand != NULL) 3981 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3982 3983 if (sc->bge_irq != NULL) 3984 bus_release_resource(dev, SYS_RES_IRQ, 3985 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3986 3987 if (sc->bge_flags & BGE_FLAG_MSI) 3988 pci_release_msi(dev); 3989 3990 if (sc->bge_res != NULL) 3991 bus_release_resource(dev, SYS_RES_MEMORY, 3992 PCIR_BAR(0), sc->bge_res); 3993 3994 if (sc->bge_res2 != NULL) 3995 bus_release_resource(dev, SYS_RES_MEMORY, 3996 PCIR_BAR(2), sc->bge_res2); 3997 3998 if (sc->bge_ifp != NULL) 3999 if_free(sc->bge_ifp); 4000 4001 bge_dma_free(sc); 4002 4003 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4004 BGE_LOCK_DESTROY(sc); 4005 } 4006 4007 static int 4008 bge_reset(struct bge_softc *sc) 4009 { 4010 device_t dev; 4011 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4012 void (*write_op)(struct bge_softc *, int, int); 4013 uint16_t devctl; 4014 int i; 4015 4016 dev = sc->bge_dev; 4017 4018 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4019 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4020 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4021 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4022 4023 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4024 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4025 if (sc->bge_flags & BGE_FLAG_PCIE) 4026 write_op = bge_writemem_direct; 4027 else 4028 write_op = bge_writemem_ind; 4029 } else 4030 write_op = bge_writereg_ind; 4031 4032 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4033 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4034 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4035 for (i = 0; i < 8000; i++) { 4036 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4037 BGE_NVRAMSWARB_GNT1) 4038 break; 4039 DELAY(20); 4040 } 4041 if (i == 8000) { 4042 if (bootverbose) 4043 device_printf(dev, "NVRAM lock timedout!\n"); 4044 } 4045 } 4046 /* Take APE lock when performing reset. */ 4047 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4048 4049 /* Save some important PCI state. */ 4050 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4051 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4052 4053 pci_write_config(dev, BGE_PCI_MISC_CTL, 4054 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4055 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4056 4057 /* Disable fastboot on controllers that support it. */ 4058 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4059 BGE_IS_5755_PLUS(sc)) { 4060 if (bootverbose) 4061 device_printf(dev, "Disabling fastboot\n"); 4062 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4063 } 4064 4065 /* 4066 * Write the magic number to SRAM at offset 0xB50. 4067 * When firmware finishes its initialization it will 4068 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4069 */ 4070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4071 4072 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4073 4074 /* XXX: Broadcom Linux driver. */ 4075 if (sc->bge_flags & BGE_FLAG_PCIE) { 4076 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4077 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4078 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4079 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4080 } 4081 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4082 /* Prevent PCIE link training during global reset */ 4083 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4084 reset |= 1 << 29; 4085 } 4086 } 4087 4088 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4089 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4090 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4091 val | BGE_VCPU_STATUS_DRV_RESET); 4092 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4093 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4094 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4095 } 4096 4097 /* 4098 * Set GPHY Power Down Override to leave GPHY 4099 * powered up in D0 uninitialized. 4100 */ 4101 if (BGE_IS_5705_PLUS(sc) && 4102 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4103 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4104 4105 /* Issue global reset */ 4106 write_op(sc, BGE_MISC_CFG, reset); 4107 4108 if (sc->bge_flags & BGE_FLAG_PCIE) 4109 DELAY(100 * 1000); 4110 else 4111 DELAY(1000); 4112 4113 /* XXX: Broadcom Linux driver. */ 4114 if (sc->bge_flags & BGE_FLAG_PCIE) { 4115 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4116 DELAY(500000); /* wait for link training to complete */ 4117 val = pci_read_config(dev, 0xC4, 4); 4118 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4119 } 4120 devctl = pci_read_config(dev, 4121 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4122 /* Clear enable no snoop and disable relaxed ordering. */ 4123 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4124 PCIEM_CTL_NOSNOOP_ENABLE); 4125 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4126 devctl, 2); 4127 pci_set_max_read_req(dev, sc->bge_expmrq); 4128 /* Clear error status. */ 4129 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4130 PCIEM_STA_CORRECTABLE_ERROR | 4131 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4132 PCIEM_STA_UNSUPPORTED_REQ, 2); 4133 } 4134 4135 /* Reset some of the PCI state that got zapped by reset. */ 4136 pci_write_config(dev, BGE_PCI_MISC_CTL, 4137 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4138 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4139 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4140 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4141 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4142 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4143 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4144 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4145 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4146 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4147 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4148 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4149 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4150 /* 4151 * Disable PCI-X relaxed ordering to ensure status block update 4152 * comes first then packet buffer DMA. Otherwise driver may 4153 * read stale status block. 4154 */ 4155 if (sc->bge_flags & BGE_FLAG_PCIX) { 4156 devctl = pci_read_config(dev, 4157 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4158 devctl &= ~PCIXM_COMMAND_ERO; 4159 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4160 devctl &= ~PCIXM_COMMAND_MAX_READ; 4161 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4162 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4163 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4164 PCIXM_COMMAND_MAX_READ); 4165 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4166 } 4167 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4168 devctl, 2); 4169 } 4170 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4171 if (BGE_IS_5714_FAMILY(sc)) { 4172 /* This chip disables MSI on reset. */ 4173 if (sc->bge_flags & BGE_FLAG_MSI) { 4174 val = pci_read_config(dev, 4175 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4176 pci_write_config(dev, 4177 sc->bge_msicap + PCIR_MSI_CTRL, 4178 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4179 val = CSR_READ_4(sc, BGE_MSI_MODE); 4180 CSR_WRITE_4(sc, BGE_MSI_MODE, 4181 val | BGE_MSIMODE_ENABLE); 4182 } 4183 val = CSR_READ_4(sc, BGE_MARB_MODE); 4184 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4185 } else 4186 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4187 4188 /* Fix up byte swapping. */ 4189 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4190 4191 val = CSR_READ_4(sc, BGE_MAC_MODE); 4192 val = (val & ~mac_mode_mask) | mac_mode; 4193 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4194 DELAY(40); 4195 4196 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4197 4198 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4199 for (i = 0; i < BGE_TIMEOUT; i++) { 4200 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4201 if (val & BGE_VCPU_STATUS_INIT_DONE) 4202 break; 4203 DELAY(100); 4204 } 4205 if (i == BGE_TIMEOUT) { 4206 device_printf(dev, "reset timed out\n"); 4207 return (1); 4208 } 4209 } else { 4210 /* 4211 * Poll until we see the 1's complement of the magic number. 4212 * This indicates that the firmware initialization is complete. 4213 * We expect this to fail if no chip containing the Ethernet 4214 * address is fitted though. 4215 */ 4216 for (i = 0; i < BGE_TIMEOUT; i++) { 4217 DELAY(10); 4218 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4219 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4220 break; 4221 } 4222 4223 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4224 device_printf(dev, 4225 "firmware handshake timed out, found 0x%08x\n", 4226 val); 4227 /* BCM57765 A0 needs additional time before accessing. */ 4228 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4229 DELAY(10 * 1000); /* XXX */ 4230 } 4231 4232 /* 4233 * The 5704 in TBI mode apparently needs some special 4234 * adjustment to insure the SERDES drive level is set 4235 * to 1.2V. 4236 */ 4237 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4238 sc->bge_flags & BGE_FLAG_TBI) { 4239 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4240 val = (val & ~0xFFF) | 0x880; 4241 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4242 } 4243 4244 /* XXX: Broadcom Linux driver. */ 4245 if (sc->bge_flags & BGE_FLAG_PCIE && 4246 !BGE_IS_5717_PLUS(sc) && 4247 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4248 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4249 /* Enable Data FIFO protection. */ 4250 val = CSR_READ_4(sc, 0x7C00); 4251 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4252 } 4253 4254 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4255 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4256 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4257 4258 return (0); 4259 } 4260 4261 static __inline void 4262 bge_rxreuse_std(struct bge_softc *sc, int i) 4263 { 4264 struct bge_rx_bd *r; 4265 4266 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4267 r->bge_flags = BGE_RXBDFLAG_END; 4268 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4269 r->bge_idx = i; 4270 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4271 } 4272 4273 static __inline void 4274 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4275 { 4276 struct bge_extrx_bd *r; 4277 4278 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4279 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4280 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4281 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4282 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4283 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4284 r->bge_idx = i; 4285 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4286 } 4287 4288 /* 4289 * Frame reception handling. This is called if there's a frame 4290 * on the receive return list. 4291 * 4292 * Note: we have to be able to handle two possibilities here: 4293 * 1) the frame is from the jumbo receive ring 4294 * 2) the frame is from the standard receive ring 4295 */ 4296 4297 static int 4298 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4299 { 4300 struct ifnet *ifp; 4301 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4302 uint16_t rx_cons; 4303 4304 rx_cons = sc->bge_rx_saved_considx; 4305 4306 /* Nothing to do. */ 4307 if (rx_cons == rx_prod) 4308 return (rx_npkts); 4309 4310 ifp = sc->bge_ifp; 4311 4312 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4313 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4314 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4315 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4316 if (BGE_IS_JUMBO_CAPABLE(sc) && 4317 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4318 (MCLBYTES - ETHER_ALIGN)) 4319 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4320 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4321 4322 while (rx_cons != rx_prod) { 4323 struct bge_rx_bd *cur_rx; 4324 uint32_t rxidx; 4325 struct mbuf *m = NULL; 4326 uint16_t vlan_tag = 0; 4327 int have_tag = 0; 4328 4329 #ifdef DEVICE_POLLING 4330 if (ifp->if_capenable & IFCAP_POLLING) { 4331 if (sc->rxcycles <= 0) 4332 break; 4333 sc->rxcycles--; 4334 } 4335 #endif 4336 4337 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4338 4339 rxidx = cur_rx->bge_idx; 4340 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4341 4342 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4343 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4344 have_tag = 1; 4345 vlan_tag = cur_rx->bge_vlan_tag; 4346 } 4347 4348 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4349 jumbocnt++; 4350 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4351 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4352 bge_rxreuse_jumbo(sc, rxidx); 4353 continue; 4354 } 4355 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4356 bge_rxreuse_jumbo(sc, rxidx); 4357 ifp->if_iqdrops++; 4358 continue; 4359 } 4360 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4361 } else { 4362 stdcnt++; 4363 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4364 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4365 bge_rxreuse_std(sc, rxidx); 4366 continue; 4367 } 4368 if (bge_newbuf_std(sc, rxidx) != 0) { 4369 bge_rxreuse_std(sc, rxidx); 4370 ifp->if_iqdrops++; 4371 continue; 4372 } 4373 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4374 } 4375 4376 ifp->if_ipackets++; 4377 #ifndef __NO_STRICT_ALIGNMENT 4378 /* 4379 * For architectures with strict alignment we must make sure 4380 * the payload is aligned. 4381 */ 4382 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4383 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4384 cur_rx->bge_len); 4385 m->m_data += ETHER_ALIGN; 4386 } 4387 #endif 4388 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4389 m->m_pkthdr.rcvif = ifp; 4390 4391 if (ifp->if_capenable & IFCAP_RXCSUM) 4392 bge_rxcsum(sc, cur_rx, m); 4393 4394 /* 4395 * If we received a packet with a vlan tag, 4396 * attach that information to the packet. 4397 */ 4398 if (have_tag) { 4399 m->m_pkthdr.ether_vtag = vlan_tag; 4400 m->m_flags |= M_VLANTAG; 4401 } 4402 4403 if (holdlck != 0) { 4404 BGE_UNLOCK(sc); 4405 (*ifp->if_input)(ifp, m); 4406 BGE_LOCK(sc); 4407 } else 4408 (*ifp->if_input)(ifp, m); 4409 rx_npkts++; 4410 4411 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4412 return (rx_npkts); 4413 } 4414 4415 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4416 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4417 if (stdcnt > 0) 4418 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4419 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4420 4421 if (jumbocnt > 0) 4422 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4423 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4424 4425 sc->bge_rx_saved_considx = rx_cons; 4426 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4427 if (stdcnt) 4428 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4429 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4430 if (jumbocnt) 4431 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4432 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4433 #ifdef notyet 4434 /* 4435 * This register wraps very quickly under heavy packet drops. 4436 * If you need correct statistics, you can enable this check. 4437 */ 4438 if (BGE_IS_5705_PLUS(sc)) 4439 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4440 #endif 4441 return (rx_npkts); 4442 } 4443 4444 static void 4445 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4446 { 4447 4448 if (BGE_IS_5717_PLUS(sc)) { 4449 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4450 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4451 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4452 if ((cur_rx->bge_error_flag & 4453 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4454 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4455 } 4456 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4457 m->m_pkthdr.csum_data = 4458 cur_rx->bge_tcp_udp_csum; 4459 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4460 CSUM_PSEUDO_HDR; 4461 } 4462 } 4463 } else { 4464 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4465 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4466 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4467 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4468 } 4469 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4470 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4471 m->m_pkthdr.csum_data = 4472 cur_rx->bge_tcp_udp_csum; 4473 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4474 CSUM_PSEUDO_HDR; 4475 } 4476 } 4477 } 4478 4479 static void 4480 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4481 { 4482 struct bge_tx_bd *cur_tx; 4483 struct ifnet *ifp; 4484 4485 BGE_LOCK_ASSERT(sc); 4486 4487 /* Nothing to do. */ 4488 if (sc->bge_tx_saved_considx == tx_cons) 4489 return; 4490 4491 ifp = sc->bge_ifp; 4492 4493 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4494 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4495 /* 4496 * Go through our tx ring and free mbufs for those 4497 * frames that have been sent. 4498 */ 4499 while (sc->bge_tx_saved_considx != tx_cons) { 4500 uint32_t idx; 4501 4502 idx = sc->bge_tx_saved_considx; 4503 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4504 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4505 ifp->if_opackets++; 4506 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4507 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4508 sc->bge_cdata.bge_tx_dmamap[idx], 4509 BUS_DMASYNC_POSTWRITE); 4510 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4511 sc->bge_cdata.bge_tx_dmamap[idx]); 4512 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4513 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4514 } 4515 sc->bge_txcnt--; 4516 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4517 } 4518 4519 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4520 if (sc->bge_txcnt == 0) 4521 sc->bge_timer = 0; 4522 } 4523 4524 #ifdef DEVICE_POLLING 4525 static int 4526 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4527 { 4528 struct bge_softc *sc = ifp->if_softc; 4529 uint16_t rx_prod, tx_cons; 4530 uint32_t statusword; 4531 int rx_npkts = 0; 4532 4533 BGE_LOCK(sc); 4534 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4535 BGE_UNLOCK(sc); 4536 return (rx_npkts); 4537 } 4538 4539 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4540 sc->bge_cdata.bge_status_map, 4541 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4542 /* Fetch updates from the status block. */ 4543 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4544 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4545 4546 statusword = sc->bge_ldata.bge_status_block->bge_status; 4547 /* Clear the status so the next pass only sees the changes. */ 4548 sc->bge_ldata.bge_status_block->bge_status = 0; 4549 4550 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4551 sc->bge_cdata.bge_status_map, 4552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4553 4554 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4555 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4556 sc->bge_link_evt++; 4557 4558 if (cmd == POLL_AND_CHECK_STATUS) 4559 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4560 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4561 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4562 bge_link_upd(sc); 4563 4564 sc->rxcycles = count; 4565 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4566 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4567 BGE_UNLOCK(sc); 4568 return (rx_npkts); 4569 } 4570 bge_txeof(sc, tx_cons); 4571 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4572 bge_start_locked(ifp); 4573 4574 BGE_UNLOCK(sc); 4575 return (rx_npkts); 4576 } 4577 #endif /* DEVICE_POLLING */ 4578 4579 static int 4580 bge_msi_intr(void *arg) 4581 { 4582 struct bge_softc *sc; 4583 4584 sc = (struct bge_softc *)arg; 4585 /* 4586 * This interrupt is not shared and controller already 4587 * disabled further interrupt. 4588 */ 4589 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4590 return (FILTER_HANDLED); 4591 } 4592 4593 static void 4594 bge_intr_task(void *arg, int pending) 4595 { 4596 struct bge_softc *sc; 4597 struct ifnet *ifp; 4598 uint32_t status, status_tag; 4599 uint16_t rx_prod, tx_cons; 4600 4601 sc = (struct bge_softc *)arg; 4602 ifp = sc->bge_ifp; 4603 4604 BGE_LOCK(sc); 4605 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4606 BGE_UNLOCK(sc); 4607 return; 4608 } 4609 4610 /* Get updated status block. */ 4611 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4612 sc->bge_cdata.bge_status_map, 4613 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4614 4615 /* Save producer/consumer indices. */ 4616 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4617 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4618 status = sc->bge_ldata.bge_status_block->bge_status; 4619 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4620 /* Dirty the status flag. */ 4621 sc->bge_ldata.bge_status_block->bge_status = 0; 4622 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4623 sc->bge_cdata.bge_status_map, 4624 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4625 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4626 status_tag = 0; 4627 4628 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4629 bge_link_upd(sc); 4630 4631 /* Let controller work. */ 4632 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4633 4634 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4635 sc->bge_rx_saved_considx != rx_prod) { 4636 /* Check RX return ring producer/consumer. */ 4637 BGE_UNLOCK(sc); 4638 bge_rxeof(sc, rx_prod, 0); 4639 BGE_LOCK(sc); 4640 } 4641 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4642 /* Check TX ring producer/consumer. */ 4643 bge_txeof(sc, tx_cons); 4644 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4645 bge_start_locked(ifp); 4646 } 4647 BGE_UNLOCK(sc); 4648 } 4649 4650 static void 4651 bge_intr(void *xsc) 4652 { 4653 struct bge_softc *sc; 4654 struct ifnet *ifp; 4655 uint32_t statusword; 4656 uint16_t rx_prod, tx_cons; 4657 4658 sc = xsc; 4659 4660 BGE_LOCK(sc); 4661 4662 ifp = sc->bge_ifp; 4663 4664 #ifdef DEVICE_POLLING 4665 if (ifp->if_capenable & IFCAP_POLLING) { 4666 BGE_UNLOCK(sc); 4667 return; 4668 } 4669 #endif 4670 4671 /* 4672 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4673 * disable interrupts by writing nonzero like we used to, since with 4674 * our current organization this just gives complications and 4675 * pessimizations for re-enabling interrupts. We used to have races 4676 * instead of the necessary complications. Disabling interrupts 4677 * would just reduce the chance of a status update while we are 4678 * running (by switching to the interrupt-mode coalescence 4679 * parameters), but this chance is already very low so it is more 4680 * efficient to get another interrupt than prevent it. 4681 * 4682 * We do the ack first to ensure another interrupt if there is a 4683 * status update after the ack. We don't check for the status 4684 * changing later because it is more efficient to get another 4685 * interrupt than prevent it, not quite as above (not checking is 4686 * a smaller optimization than not toggling the interrupt enable, 4687 * since checking doesn't involve PCI accesses and toggling require 4688 * the status check). So toggling would probably be a pessimization 4689 * even with MSI. It would only be needed for using a task queue. 4690 */ 4691 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4692 4693 /* 4694 * Do the mandatory PCI flush as well as get the link status. 4695 */ 4696 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4697 4698 /* Make sure the descriptor ring indexes are coherent. */ 4699 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4700 sc->bge_cdata.bge_status_map, 4701 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4702 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4703 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4704 sc->bge_ldata.bge_status_block->bge_status = 0; 4705 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4706 sc->bge_cdata.bge_status_map, 4707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4708 4709 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4710 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4711 statusword || sc->bge_link_evt) 4712 bge_link_upd(sc); 4713 4714 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4715 /* Check RX return ring producer/consumer. */ 4716 bge_rxeof(sc, rx_prod, 1); 4717 } 4718 4719 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4720 /* Check TX ring producer/consumer. */ 4721 bge_txeof(sc, tx_cons); 4722 } 4723 4724 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4725 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4726 bge_start_locked(ifp); 4727 4728 BGE_UNLOCK(sc); 4729 } 4730 4731 static void 4732 bge_asf_driver_up(struct bge_softc *sc) 4733 { 4734 if (sc->bge_asf_mode & ASF_STACKUP) { 4735 /* Send ASF heartbeat aprox. every 2s */ 4736 if (sc->bge_asf_count) 4737 sc->bge_asf_count --; 4738 else { 4739 sc->bge_asf_count = 2; 4740 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4741 BGE_FW_CMD_DRV_ALIVE); 4742 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4743 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4744 BGE_FW_HB_TIMEOUT_SEC); 4745 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4746 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4747 BGE_RX_CPU_DRV_EVENT); 4748 } 4749 } 4750 } 4751 4752 static void 4753 bge_tick(void *xsc) 4754 { 4755 struct bge_softc *sc = xsc; 4756 struct mii_data *mii = NULL; 4757 4758 BGE_LOCK_ASSERT(sc); 4759 4760 /* Synchronize with possible callout reset/stop. */ 4761 if (callout_pending(&sc->bge_stat_ch) || 4762 !callout_active(&sc->bge_stat_ch)) 4763 return; 4764 4765 if (BGE_IS_5705_PLUS(sc)) 4766 bge_stats_update_regs(sc); 4767 else 4768 bge_stats_update(sc); 4769 4770 /* XXX Add APE heartbeat check here? */ 4771 4772 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4773 mii = device_get_softc(sc->bge_miibus); 4774 /* 4775 * Do not touch PHY if we have link up. This could break 4776 * IPMI/ASF mode or produce extra input errors 4777 * (extra errors was reported for bcm5701 & bcm5704). 4778 */ 4779 if (!sc->bge_link) 4780 mii_tick(mii); 4781 } else { 4782 /* 4783 * Since in TBI mode auto-polling can't be used we should poll 4784 * link status manually. Here we register pending link event 4785 * and trigger interrupt. 4786 */ 4787 #ifdef DEVICE_POLLING 4788 /* In polling mode we poll link state in bge_poll(). */ 4789 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4790 #endif 4791 { 4792 sc->bge_link_evt++; 4793 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4794 sc->bge_flags & BGE_FLAG_5788) 4795 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4796 else 4797 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4798 } 4799 } 4800 4801 bge_asf_driver_up(sc); 4802 bge_watchdog(sc); 4803 4804 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4805 } 4806 4807 static void 4808 bge_stats_update_regs(struct bge_softc *sc) 4809 { 4810 struct ifnet *ifp; 4811 struct bge_mac_stats *stats; 4812 uint32_t val; 4813 4814 ifp = sc->bge_ifp; 4815 stats = &sc->bge_mac_stats; 4816 4817 stats->ifHCOutOctets += 4818 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4819 stats->etherStatsCollisions += 4820 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4821 stats->outXonSent += 4822 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4823 stats->outXoffSent += 4824 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4825 stats->dot3StatsInternalMacTransmitErrors += 4826 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4827 stats->dot3StatsSingleCollisionFrames += 4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4829 stats->dot3StatsMultipleCollisionFrames += 4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4831 stats->dot3StatsDeferredTransmissions += 4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4833 stats->dot3StatsExcessiveCollisions += 4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4835 stats->dot3StatsLateCollisions += 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4837 stats->ifHCOutUcastPkts += 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4839 stats->ifHCOutMulticastPkts += 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4841 stats->ifHCOutBroadcastPkts += 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4843 4844 stats->ifHCInOctets += 4845 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4846 stats->etherStatsFragments += 4847 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4848 stats->ifHCInUcastPkts += 4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4850 stats->ifHCInMulticastPkts += 4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4852 stats->ifHCInBroadcastPkts += 4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4854 stats->dot3StatsFCSErrors += 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4856 stats->dot3StatsAlignmentErrors += 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4858 stats->xonPauseFramesReceived += 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4860 stats->xoffPauseFramesReceived += 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4862 stats->macControlFramesReceived += 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4864 stats->xoffStateEntered += 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4866 stats->dot3StatsFramesTooLong += 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4868 stats->etherStatsJabbers += 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4870 stats->etherStatsUndersizePkts += 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4872 4873 stats->FramesDroppedDueToFilters += 4874 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4875 stats->DmaWriteQueueFull += 4876 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4877 stats->DmaWriteHighPriQueueFull += 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4879 stats->NoMoreRxBDs += 4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4881 /* 4882 * XXX 4883 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4884 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4885 * includes number of unwanted multicast frames. This comes 4886 * from silicon bug and known workaround to get rough(not 4887 * exact) counter is to enable interrupt on MBUF low water 4888 * attention. This can be accomplished by setting 4889 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4890 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4891 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4892 * However that change would generate more interrupts and 4893 * there are still possibilities of losing multiple frames 4894 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4895 * Given that the workaround still would not get correct 4896 * counter I don't think it's worth to implement it. So 4897 * ignore reading the counter on controllers that have the 4898 * silicon bug. 4899 */ 4900 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4901 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4902 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4903 stats->InputDiscards += 4904 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4905 stats->InputErrors += 4906 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4907 stats->RecvThresholdHit += 4908 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4909 4910 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4911 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4912 stats->InputErrors); 4913 4914 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4915 /* 4916 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4917 * frames, it's safe to disable workaround for DMA engine's 4918 * miscalculation of TXMBUF space. 4919 */ 4920 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4921 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4922 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4923 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4924 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4925 else 4926 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4927 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4928 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4929 } 4930 } 4931 } 4932 4933 static void 4934 bge_stats_clear_regs(struct bge_softc *sc) 4935 { 4936 4937 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4938 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4939 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4950 4951 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4952 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4965 4966 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4967 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4968 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4969 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4970 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4973 } 4974 4975 static void 4976 bge_stats_update(struct bge_softc *sc) 4977 { 4978 struct ifnet *ifp; 4979 bus_size_t stats; 4980 uint32_t cnt; /* current register value */ 4981 4982 ifp = sc->bge_ifp; 4983 4984 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4985 4986 #define READ_STAT(sc, stats, stat) \ 4987 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4988 4989 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4990 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4991 sc->bge_tx_collisions = cnt; 4992 4993 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4994 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4995 sc->bge_rx_nobds = cnt; 4996 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4997 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 4998 sc->bge_rx_inerrs = cnt; 4999 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5000 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 5001 sc->bge_rx_discards = cnt; 5002 5003 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5004 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 5005 sc->bge_tx_discards = cnt; 5006 5007 #undef READ_STAT 5008 } 5009 5010 /* 5011 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5012 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5013 * but when such padded frames employ the bge IP/TCP checksum offload, 5014 * the hardware checksum assist gives incorrect results (possibly 5015 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5016 * If we pad such runts with zeros, the onboard checksum comes out correct. 5017 */ 5018 static __inline int 5019 bge_cksum_pad(struct mbuf *m) 5020 { 5021 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5022 struct mbuf *last; 5023 5024 /* If there's only the packet-header and we can pad there, use it. */ 5025 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5026 M_TRAILINGSPACE(m) >= padlen) { 5027 last = m; 5028 } else { 5029 /* 5030 * Walk packet chain to find last mbuf. We will either 5031 * pad there, or append a new mbuf and pad it. 5032 */ 5033 for (last = m; last->m_next != NULL; last = last->m_next); 5034 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5035 /* Allocate new empty mbuf, pad it. Compact later. */ 5036 struct mbuf *n; 5037 5038 MGET(n, M_NOWAIT, MT_DATA); 5039 if (n == NULL) 5040 return (ENOBUFS); 5041 n->m_len = 0; 5042 last->m_next = n; 5043 last = n; 5044 } 5045 } 5046 5047 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5048 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5049 last->m_len += padlen; 5050 m->m_pkthdr.len += padlen; 5051 5052 return (0); 5053 } 5054 5055 static struct mbuf * 5056 bge_check_short_dma(struct mbuf *m) 5057 { 5058 struct mbuf *n; 5059 int found; 5060 5061 /* 5062 * If device receive two back-to-back send BDs with less than 5063 * or equal to 8 total bytes then the device may hang. The two 5064 * back-to-back send BDs must in the same frame for this failure 5065 * to occur. Scan mbuf chains and see whether two back-to-back 5066 * send BDs are there. If this is the case, allocate new mbuf 5067 * and copy the frame to workaround the silicon bug. 5068 */ 5069 for (n = m, found = 0; n != NULL; n = n->m_next) { 5070 if (n->m_len < 8) { 5071 found++; 5072 if (found > 1) 5073 break; 5074 continue; 5075 } 5076 found = 0; 5077 } 5078 5079 if (found > 1) { 5080 n = m_defrag(m, M_NOWAIT); 5081 if (n == NULL) 5082 m_freem(m); 5083 } else 5084 n = m; 5085 return (n); 5086 } 5087 5088 static struct mbuf * 5089 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5090 uint16_t *flags) 5091 { 5092 struct ip *ip; 5093 struct tcphdr *tcp; 5094 struct mbuf *n; 5095 uint16_t hlen; 5096 uint32_t poff; 5097 5098 if (M_WRITABLE(m) == 0) { 5099 /* Get a writable copy. */ 5100 n = m_dup(m, M_NOWAIT); 5101 m_freem(m); 5102 if (n == NULL) 5103 return (NULL); 5104 m = n; 5105 } 5106 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5107 if (m == NULL) 5108 return (NULL); 5109 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5110 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5111 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5112 if (m == NULL) 5113 return (NULL); 5114 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5115 m = m_pullup(m, poff + (tcp->th_off << 2)); 5116 if (m == NULL) 5117 return (NULL); 5118 /* 5119 * It seems controller doesn't modify IP length and TCP pseudo 5120 * checksum. These checksum computed by upper stack should be 0. 5121 */ 5122 *mss = m->m_pkthdr.tso_segsz; 5123 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5124 ip->ip_sum = 0; 5125 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5126 /* Clear pseudo checksum computed by TCP stack. */ 5127 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5128 tcp->th_sum = 0; 5129 /* 5130 * Broadcom controllers uses different descriptor format for 5131 * TSO depending on ASIC revision. Due to TSO-capable firmware 5132 * license issue and lower performance of firmware based TSO 5133 * we only support hardware based TSO. 5134 */ 5135 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5136 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5137 if (sc->bge_flags & BGE_FLAG_TSO3) { 5138 /* 5139 * For BCM5717 and newer controllers, hardware based TSO 5140 * uses the 14 lower bits of the bge_mss field to store the 5141 * MSS and the upper 2 bits to store the lowest 2 bits of 5142 * the IP/TCP header length. The upper 6 bits of the header 5143 * length are stored in the bge_flags[14:10,4] field. Jumbo 5144 * frames are supported. 5145 */ 5146 *mss |= ((hlen & 0x3) << 14); 5147 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5148 } else { 5149 /* 5150 * For BCM5755 and newer controllers, hardware based TSO uses 5151 * the lower 11 bits to store the MSS and the upper 5 bits to 5152 * store the IP/TCP header length. Jumbo frames are not 5153 * supported. 5154 */ 5155 *mss |= (hlen << 11); 5156 } 5157 return (m); 5158 } 5159 5160 /* 5161 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5162 * pointers to descriptors. 5163 */ 5164 static int 5165 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5166 { 5167 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5168 bus_dmamap_t map; 5169 struct bge_tx_bd *d; 5170 struct mbuf *m = *m_head; 5171 uint32_t idx = *txidx; 5172 uint16_t csum_flags, mss, vlan_tag; 5173 int nsegs, i, error; 5174 5175 csum_flags = 0; 5176 mss = 0; 5177 vlan_tag = 0; 5178 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5179 m->m_next != NULL) { 5180 *m_head = bge_check_short_dma(m); 5181 if (*m_head == NULL) 5182 return (ENOBUFS); 5183 m = *m_head; 5184 } 5185 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5186 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5187 if (*m_head == NULL) 5188 return (ENOBUFS); 5189 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5190 BGE_TXBDFLAG_CPU_POST_DMA; 5191 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5192 if (m->m_pkthdr.csum_flags & CSUM_IP) 5193 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5194 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5195 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5196 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5197 (error = bge_cksum_pad(m)) != 0) { 5198 m_freem(m); 5199 *m_head = NULL; 5200 return (error); 5201 } 5202 } 5203 } 5204 5205 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5206 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5207 m->m_pkthdr.len > ETHER_MAX_LEN) 5208 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5209 if (sc->bge_forced_collapse > 0 && 5210 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5211 /* 5212 * Forcedly collapse mbuf chains to overcome hardware 5213 * limitation which only support a single outstanding 5214 * DMA read operation. 5215 */ 5216 if (sc->bge_forced_collapse == 1) 5217 m = m_defrag(m, M_NOWAIT); 5218 else 5219 m = m_collapse(m, M_NOWAIT, 5220 sc->bge_forced_collapse); 5221 if (m == NULL) 5222 m = *m_head; 5223 *m_head = m; 5224 } 5225 } 5226 5227 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5228 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5229 &nsegs, BUS_DMA_NOWAIT); 5230 if (error == EFBIG) { 5231 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5232 if (m == NULL) { 5233 m_freem(*m_head); 5234 *m_head = NULL; 5235 return (ENOBUFS); 5236 } 5237 *m_head = m; 5238 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5239 m, segs, &nsegs, BUS_DMA_NOWAIT); 5240 if (error) { 5241 m_freem(m); 5242 *m_head = NULL; 5243 return (error); 5244 } 5245 } else if (error != 0) 5246 return (error); 5247 5248 /* Check if we have enough free send BDs. */ 5249 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5250 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5251 return (ENOBUFS); 5252 } 5253 5254 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5255 5256 if (m->m_flags & M_VLANTAG) { 5257 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5258 vlan_tag = m->m_pkthdr.ether_vtag; 5259 } 5260 5261 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5262 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5263 /* 5264 * 5725 family of devices corrupts TSO packets when TSO DMA 5265 * buffers cross into regions which are within MSS bytes of 5266 * a 4GB boundary. If we encounter the condition, drop the 5267 * packet. 5268 */ 5269 for (i = 0; ; i++) { 5270 d = &sc->bge_ldata.bge_tx_ring[idx]; 5271 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5272 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5273 d->bge_len = segs[i].ds_len; 5274 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5275 d->bge_addr.bge_addr_lo) 5276 break; 5277 d->bge_flags = csum_flags; 5278 d->bge_vlan_tag = vlan_tag; 5279 d->bge_mss = mss; 5280 if (i == nsegs - 1) 5281 break; 5282 BGE_INC(idx, BGE_TX_RING_CNT); 5283 } 5284 if (i != nsegs - 1) { 5285 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5286 BUS_DMASYNC_POSTWRITE); 5287 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5288 m_freem(*m_head); 5289 *m_head = NULL; 5290 return (EIO); 5291 } 5292 } else { 5293 for (i = 0; ; i++) { 5294 d = &sc->bge_ldata.bge_tx_ring[idx]; 5295 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5296 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5297 d->bge_len = segs[i].ds_len; 5298 d->bge_flags = csum_flags; 5299 d->bge_vlan_tag = vlan_tag; 5300 d->bge_mss = mss; 5301 if (i == nsegs - 1) 5302 break; 5303 BGE_INC(idx, BGE_TX_RING_CNT); 5304 } 5305 } 5306 5307 /* Mark the last segment as end of packet... */ 5308 d->bge_flags |= BGE_TXBDFLAG_END; 5309 5310 /* 5311 * Insure that the map for this transmission 5312 * is placed at the array index of the last descriptor 5313 * in this chain. 5314 */ 5315 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5316 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5317 sc->bge_cdata.bge_tx_chain[idx] = m; 5318 sc->bge_txcnt += nsegs; 5319 5320 BGE_INC(idx, BGE_TX_RING_CNT); 5321 *txidx = idx; 5322 5323 return (0); 5324 } 5325 5326 /* 5327 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5328 * to the mbuf data regions directly in the transmit descriptors. 5329 */ 5330 static void 5331 bge_start_locked(struct ifnet *ifp) 5332 { 5333 struct bge_softc *sc; 5334 struct mbuf *m_head; 5335 uint32_t prodidx; 5336 int count; 5337 5338 sc = ifp->if_softc; 5339 BGE_LOCK_ASSERT(sc); 5340 5341 if (!sc->bge_link || 5342 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5343 IFF_DRV_RUNNING) 5344 return; 5345 5346 prodidx = sc->bge_tx_prodidx; 5347 5348 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5349 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5351 break; 5352 } 5353 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5354 if (m_head == NULL) 5355 break; 5356 5357 /* 5358 * Pack the data into the transmit ring. If we 5359 * don't have room, set the OACTIVE flag and wait 5360 * for the NIC to drain the ring. 5361 */ 5362 if (bge_encap(sc, &m_head, &prodidx)) { 5363 if (m_head == NULL) 5364 break; 5365 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5366 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5367 break; 5368 } 5369 ++count; 5370 5371 /* 5372 * If there's a BPF listener, bounce a copy of this frame 5373 * to him. 5374 */ 5375 #ifdef ETHER_BPF_MTAP 5376 ETHER_BPF_MTAP(ifp, m_head); 5377 #else 5378 BPF_MTAP(ifp, m_head); 5379 #endif 5380 } 5381 5382 if (count > 0) { 5383 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5384 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5385 /* Transmit. */ 5386 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5387 /* 5700 b2 errata */ 5388 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5389 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5390 5391 sc->bge_tx_prodidx = prodidx; 5392 5393 /* 5394 * Set a timeout in case the chip goes out to lunch. 5395 */ 5396 sc->bge_timer = BGE_TX_TIMEOUT; 5397 } 5398 } 5399 5400 /* 5401 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5402 * to the mbuf data regions directly in the transmit descriptors. 5403 */ 5404 static void 5405 bge_start(struct ifnet *ifp) 5406 { 5407 struct bge_softc *sc; 5408 5409 sc = ifp->if_softc; 5410 BGE_LOCK(sc); 5411 bge_start_locked(ifp); 5412 BGE_UNLOCK(sc); 5413 } 5414 5415 static void 5416 bge_init_locked(struct bge_softc *sc) 5417 { 5418 struct ifnet *ifp; 5419 uint16_t *m; 5420 uint32_t mode; 5421 5422 BGE_LOCK_ASSERT(sc); 5423 5424 ifp = sc->bge_ifp; 5425 5426 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5427 return; 5428 5429 /* Cancel pending I/O and flush buffers. */ 5430 bge_stop(sc); 5431 5432 bge_stop_fw(sc); 5433 bge_sig_pre_reset(sc, BGE_RESET_START); 5434 bge_reset(sc); 5435 bge_sig_legacy(sc, BGE_RESET_START); 5436 bge_sig_post_reset(sc, BGE_RESET_START); 5437 5438 bge_chipinit(sc); 5439 5440 /* 5441 * Init the various state machines, ring 5442 * control blocks and firmware. 5443 */ 5444 if (bge_blockinit(sc)) { 5445 device_printf(sc->bge_dev, "initialization failure\n"); 5446 return; 5447 } 5448 5449 ifp = sc->bge_ifp; 5450 5451 /* Specify MTU. */ 5452 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5453 ETHER_HDR_LEN + ETHER_CRC_LEN + 5454 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5455 5456 /* Load our MAC address. */ 5457 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5458 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5459 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5460 5461 /* Program promiscuous mode. */ 5462 bge_setpromisc(sc); 5463 5464 /* Program multicast filter. */ 5465 bge_setmulti(sc); 5466 5467 /* Program VLAN tag stripping. */ 5468 bge_setvlan(sc); 5469 5470 /* Override UDP checksum offloading. */ 5471 if (sc->bge_forced_udpcsum == 0) 5472 sc->bge_csum_features &= ~CSUM_UDP; 5473 else 5474 sc->bge_csum_features |= CSUM_UDP; 5475 if (ifp->if_capabilities & IFCAP_TXCSUM && 5476 ifp->if_capenable & IFCAP_TXCSUM) { 5477 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5478 ifp->if_hwassist |= sc->bge_csum_features; 5479 } 5480 5481 /* Init RX ring. */ 5482 if (bge_init_rx_ring_std(sc) != 0) { 5483 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5484 bge_stop(sc); 5485 return; 5486 } 5487 5488 /* 5489 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5490 * memory to insure that the chip has in fact read the first 5491 * entry of the ring. 5492 */ 5493 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5494 uint32_t v, i; 5495 for (i = 0; i < 10; i++) { 5496 DELAY(20); 5497 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5498 if (v == (MCLBYTES - ETHER_ALIGN)) 5499 break; 5500 } 5501 if (i == 10) 5502 device_printf (sc->bge_dev, 5503 "5705 A0 chip failed to load RX ring\n"); 5504 } 5505 5506 /* Init jumbo RX ring. */ 5507 if (BGE_IS_JUMBO_CAPABLE(sc) && 5508 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5509 (MCLBYTES - ETHER_ALIGN)) { 5510 if (bge_init_rx_ring_jumbo(sc) != 0) { 5511 device_printf(sc->bge_dev, 5512 "no memory for jumbo Rx buffers.\n"); 5513 bge_stop(sc); 5514 return; 5515 } 5516 } 5517 5518 /* Init our RX return ring index. */ 5519 sc->bge_rx_saved_considx = 0; 5520 5521 /* Init our RX/TX stat counters. */ 5522 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5523 5524 /* Init TX ring. */ 5525 bge_init_tx_ring(sc); 5526 5527 /* Enable TX MAC state machine lockup fix. */ 5528 mode = CSR_READ_4(sc, BGE_TX_MODE); 5529 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5530 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5531 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5532 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5533 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5534 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5535 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5536 } 5537 /* Turn on transmitter. */ 5538 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5539 DELAY(100); 5540 5541 /* Turn on receiver. */ 5542 mode = CSR_READ_4(sc, BGE_RX_MODE); 5543 if (BGE_IS_5755_PLUS(sc)) 5544 mode |= BGE_RXMODE_IPV6_ENABLE; 5545 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5546 DELAY(10); 5547 5548 /* 5549 * Set the number of good frames to receive after RX MBUF 5550 * Low Watermark has been reached. After the RX MAC receives 5551 * this number of frames, it will drop subsequent incoming 5552 * frames until the MBUF High Watermark is reached. 5553 */ 5554 if (BGE_IS_57765_PLUS(sc)) 5555 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5556 else 5557 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5558 5559 /* Clear MAC statistics. */ 5560 if (BGE_IS_5705_PLUS(sc)) 5561 bge_stats_clear_regs(sc); 5562 5563 /* Tell firmware we're alive. */ 5564 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5565 5566 #ifdef DEVICE_POLLING 5567 /* Disable interrupts if we are polling. */ 5568 if (ifp->if_capenable & IFCAP_POLLING) { 5569 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5570 BGE_PCIMISCCTL_MASK_PCI_INTR); 5571 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5572 } else 5573 #endif 5574 5575 /* Enable host interrupts. */ 5576 { 5577 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5578 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5579 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5580 } 5581 5582 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5583 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5584 5585 bge_ifmedia_upd_locked(ifp); 5586 5587 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5588 } 5589 5590 static void 5591 bge_init(void *xsc) 5592 { 5593 struct bge_softc *sc = xsc; 5594 5595 BGE_LOCK(sc); 5596 bge_init_locked(sc); 5597 BGE_UNLOCK(sc); 5598 } 5599 5600 /* 5601 * Set media options. 5602 */ 5603 static int 5604 bge_ifmedia_upd(struct ifnet *ifp) 5605 { 5606 struct bge_softc *sc = ifp->if_softc; 5607 int res; 5608 5609 BGE_LOCK(sc); 5610 res = bge_ifmedia_upd_locked(ifp); 5611 BGE_UNLOCK(sc); 5612 5613 return (res); 5614 } 5615 5616 static int 5617 bge_ifmedia_upd_locked(struct ifnet *ifp) 5618 { 5619 struct bge_softc *sc = ifp->if_softc; 5620 struct mii_data *mii; 5621 struct mii_softc *miisc; 5622 struct ifmedia *ifm; 5623 5624 BGE_LOCK_ASSERT(sc); 5625 5626 ifm = &sc->bge_ifmedia; 5627 5628 /* If this is a 1000baseX NIC, enable the TBI port. */ 5629 if (sc->bge_flags & BGE_FLAG_TBI) { 5630 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5631 return (EINVAL); 5632 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5633 case IFM_AUTO: 5634 /* 5635 * The BCM5704 ASIC appears to have a special 5636 * mechanism for programming the autoneg 5637 * advertisement registers in TBI mode. 5638 */ 5639 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5640 uint32_t sgdig; 5641 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5642 if (sgdig & BGE_SGDIGSTS_DONE) { 5643 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5644 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5645 sgdig |= BGE_SGDIGCFG_AUTO | 5646 BGE_SGDIGCFG_PAUSE_CAP | 5647 BGE_SGDIGCFG_ASYM_PAUSE; 5648 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5649 sgdig | BGE_SGDIGCFG_SEND); 5650 DELAY(5); 5651 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5652 } 5653 } 5654 break; 5655 case IFM_1000_SX: 5656 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5657 BGE_CLRBIT(sc, BGE_MAC_MODE, 5658 BGE_MACMODE_HALF_DUPLEX); 5659 } else { 5660 BGE_SETBIT(sc, BGE_MAC_MODE, 5661 BGE_MACMODE_HALF_DUPLEX); 5662 } 5663 DELAY(40); 5664 break; 5665 default: 5666 return (EINVAL); 5667 } 5668 return (0); 5669 } 5670 5671 sc->bge_link_evt++; 5672 mii = device_get_softc(sc->bge_miibus); 5673 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5674 PHY_RESET(miisc); 5675 mii_mediachg(mii); 5676 5677 /* 5678 * Force an interrupt so that we will call bge_link_upd 5679 * if needed and clear any pending link state attention. 5680 * Without this we are not getting any further interrupts 5681 * for link state changes and thus will not UP the link and 5682 * not be able to send in bge_start_locked. The only 5683 * way to get things working was to receive a packet and 5684 * get an RX intr. 5685 * bge_tick should help for fiber cards and we might not 5686 * need to do this here if BGE_FLAG_TBI is set but as 5687 * we poll for fiber anyway it should not harm. 5688 */ 5689 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5690 sc->bge_flags & BGE_FLAG_5788) 5691 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5692 else 5693 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5694 5695 return (0); 5696 } 5697 5698 /* 5699 * Report current media status. 5700 */ 5701 static void 5702 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5703 { 5704 struct bge_softc *sc = ifp->if_softc; 5705 struct mii_data *mii; 5706 5707 BGE_LOCK(sc); 5708 5709 if ((ifp->if_flags & IFF_UP) == 0) { 5710 BGE_UNLOCK(sc); 5711 return; 5712 } 5713 if (sc->bge_flags & BGE_FLAG_TBI) { 5714 ifmr->ifm_status = IFM_AVALID; 5715 ifmr->ifm_active = IFM_ETHER; 5716 if (CSR_READ_4(sc, BGE_MAC_STS) & 5717 BGE_MACSTAT_TBI_PCS_SYNCHED) 5718 ifmr->ifm_status |= IFM_ACTIVE; 5719 else { 5720 ifmr->ifm_active |= IFM_NONE; 5721 BGE_UNLOCK(sc); 5722 return; 5723 } 5724 ifmr->ifm_active |= IFM_1000_SX; 5725 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5726 ifmr->ifm_active |= IFM_HDX; 5727 else 5728 ifmr->ifm_active |= IFM_FDX; 5729 BGE_UNLOCK(sc); 5730 return; 5731 } 5732 5733 mii = device_get_softc(sc->bge_miibus); 5734 mii_pollstat(mii); 5735 ifmr->ifm_active = mii->mii_media_active; 5736 ifmr->ifm_status = mii->mii_media_status; 5737 5738 BGE_UNLOCK(sc); 5739 } 5740 5741 static int 5742 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5743 { 5744 struct bge_softc *sc = ifp->if_softc; 5745 struct ifreq *ifr = (struct ifreq *) data; 5746 struct mii_data *mii; 5747 int flags, mask, error = 0; 5748 5749 switch (command) { 5750 case SIOCSIFMTU: 5751 if (BGE_IS_JUMBO_CAPABLE(sc) || 5752 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5753 if (ifr->ifr_mtu < ETHERMIN || 5754 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5755 error = EINVAL; 5756 break; 5757 } 5758 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5759 error = EINVAL; 5760 break; 5761 } 5762 BGE_LOCK(sc); 5763 if (ifp->if_mtu != ifr->ifr_mtu) { 5764 ifp->if_mtu = ifr->ifr_mtu; 5765 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5766 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5767 bge_init_locked(sc); 5768 } 5769 } 5770 BGE_UNLOCK(sc); 5771 break; 5772 case SIOCSIFFLAGS: 5773 BGE_LOCK(sc); 5774 if (ifp->if_flags & IFF_UP) { 5775 /* 5776 * If only the state of the PROMISC flag changed, 5777 * then just use the 'set promisc mode' command 5778 * instead of reinitializing the entire NIC. Doing 5779 * a full re-init means reloading the firmware and 5780 * waiting for it to start up, which may take a 5781 * second or two. Similarly for ALLMULTI. 5782 */ 5783 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5784 flags = ifp->if_flags ^ sc->bge_if_flags; 5785 if (flags & IFF_PROMISC) 5786 bge_setpromisc(sc); 5787 if (flags & IFF_ALLMULTI) 5788 bge_setmulti(sc); 5789 } else 5790 bge_init_locked(sc); 5791 } else { 5792 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5793 bge_stop(sc); 5794 } 5795 } 5796 sc->bge_if_flags = ifp->if_flags; 5797 BGE_UNLOCK(sc); 5798 error = 0; 5799 break; 5800 case SIOCADDMULTI: 5801 case SIOCDELMULTI: 5802 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5803 BGE_LOCK(sc); 5804 bge_setmulti(sc); 5805 BGE_UNLOCK(sc); 5806 error = 0; 5807 } 5808 break; 5809 case SIOCSIFMEDIA: 5810 case SIOCGIFMEDIA: 5811 if (sc->bge_flags & BGE_FLAG_TBI) { 5812 error = ifmedia_ioctl(ifp, ifr, 5813 &sc->bge_ifmedia, command); 5814 } else { 5815 mii = device_get_softc(sc->bge_miibus); 5816 error = ifmedia_ioctl(ifp, ifr, 5817 &mii->mii_media, command); 5818 } 5819 break; 5820 case SIOCSIFCAP: 5821 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5822 #ifdef DEVICE_POLLING 5823 if (mask & IFCAP_POLLING) { 5824 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5825 error = ether_poll_register(bge_poll, ifp); 5826 if (error) 5827 return (error); 5828 BGE_LOCK(sc); 5829 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5830 BGE_PCIMISCCTL_MASK_PCI_INTR); 5831 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5832 ifp->if_capenable |= IFCAP_POLLING; 5833 BGE_UNLOCK(sc); 5834 } else { 5835 error = ether_poll_deregister(ifp); 5836 /* Enable interrupt even in error case */ 5837 BGE_LOCK(sc); 5838 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5839 BGE_PCIMISCCTL_MASK_PCI_INTR); 5840 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5841 ifp->if_capenable &= ~IFCAP_POLLING; 5842 BGE_UNLOCK(sc); 5843 } 5844 } 5845 #endif 5846 if ((mask & IFCAP_TXCSUM) != 0 && 5847 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5848 ifp->if_capenable ^= IFCAP_TXCSUM; 5849 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5850 ifp->if_hwassist |= sc->bge_csum_features; 5851 else 5852 ifp->if_hwassist &= ~sc->bge_csum_features; 5853 } 5854 5855 if ((mask & IFCAP_RXCSUM) != 0 && 5856 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5857 ifp->if_capenable ^= IFCAP_RXCSUM; 5858 5859 if ((mask & IFCAP_TSO4) != 0 && 5860 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5861 ifp->if_capenable ^= IFCAP_TSO4; 5862 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5863 ifp->if_hwassist |= CSUM_TSO; 5864 else 5865 ifp->if_hwassist &= ~CSUM_TSO; 5866 } 5867 5868 if (mask & IFCAP_VLAN_MTU) { 5869 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5870 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5871 bge_init(sc); 5872 } 5873 5874 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5875 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5876 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5877 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5878 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5879 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5880 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5881 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5882 BGE_LOCK(sc); 5883 bge_setvlan(sc); 5884 BGE_UNLOCK(sc); 5885 } 5886 #ifdef VLAN_CAPABILITIES 5887 VLAN_CAPABILITIES(ifp); 5888 #endif 5889 break; 5890 default: 5891 error = ether_ioctl(ifp, command, data); 5892 break; 5893 } 5894 5895 return (error); 5896 } 5897 5898 static void 5899 bge_watchdog(struct bge_softc *sc) 5900 { 5901 struct ifnet *ifp; 5902 uint32_t status; 5903 5904 BGE_LOCK_ASSERT(sc); 5905 5906 if (sc->bge_timer == 0 || --sc->bge_timer) 5907 return; 5908 5909 /* If pause frames are active then don't reset the hardware. */ 5910 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5911 status = CSR_READ_4(sc, BGE_RX_STS); 5912 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5913 /* 5914 * If link partner has us in XOFF state then wait for 5915 * the condition to clear. 5916 */ 5917 CSR_WRITE_4(sc, BGE_RX_STS, status); 5918 sc->bge_timer = BGE_TX_TIMEOUT; 5919 return; 5920 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5921 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5922 /* 5923 * If link partner has us in XOFF state then wait for 5924 * the condition to clear. 5925 */ 5926 CSR_WRITE_4(sc, BGE_RX_STS, status); 5927 sc->bge_timer = BGE_TX_TIMEOUT; 5928 return; 5929 } 5930 /* 5931 * Any other condition is unexpected and the controller 5932 * should be reset. 5933 */ 5934 } 5935 5936 ifp = sc->bge_ifp; 5937 5938 if_printf(ifp, "watchdog timeout -- resetting\n"); 5939 5940 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5941 bge_init_locked(sc); 5942 5943 ifp->if_oerrors++; 5944 } 5945 5946 static void 5947 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5948 { 5949 int i; 5950 5951 BGE_CLRBIT(sc, reg, bit); 5952 5953 for (i = 0; i < BGE_TIMEOUT; i++) { 5954 if ((CSR_READ_4(sc, reg) & bit) == 0) 5955 return; 5956 DELAY(100); 5957 } 5958 } 5959 5960 /* 5961 * Stop the adapter and free any mbufs allocated to the 5962 * RX and TX lists. 5963 */ 5964 static void 5965 bge_stop(struct bge_softc *sc) 5966 { 5967 struct ifnet *ifp; 5968 5969 BGE_LOCK_ASSERT(sc); 5970 5971 ifp = sc->bge_ifp; 5972 5973 callout_stop(&sc->bge_stat_ch); 5974 5975 /* Disable host interrupts. */ 5976 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5977 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5978 5979 /* 5980 * Tell firmware we're shutting down. 5981 */ 5982 bge_stop_fw(sc); 5983 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5984 5985 /* 5986 * Disable all of the receiver blocks. 5987 */ 5988 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5989 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5990 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5991 if (BGE_IS_5700_FAMILY(sc)) 5992 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5993 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5996 5997 /* 5998 * Disable all of the transmit blocks. 5999 */ 6000 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6001 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6002 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6003 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6004 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6005 if (BGE_IS_5700_FAMILY(sc)) 6006 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6008 6009 /* 6010 * Shut down all of the memory managers and related 6011 * state machines. 6012 */ 6013 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6014 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6015 if (BGE_IS_5700_FAMILY(sc)) 6016 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6017 6018 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6019 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6020 if (!(BGE_IS_5705_PLUS(sc))) { 6021 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6022 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6023 } 6024 /* Update MAC statistics. */ 6025 if (BGE_IS_5705_PLUS(sc)) 6026 bge_stats_update_regs(sc); 6027 6028 bge_reset(sc); 6029 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6030 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6031 6032 /* 6033 * Keep the ASF firmware running if up. 6034 */ 6035 if (sc->bge_asf_mode & ASF_STACKUP) 6036 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6037 else 6038 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6039 6040 /* Free the RX lists. */ 6041 bge_free_rx_ring_std(sc); 6042 6043 /* Free jumbo RX list. */ 6044 if (BGE_IS_JUMBO_CAPABLE(sc)) 6045 bge_free_rx_ring_jumbo(sc); 6046 6047 /* Free TX buffers. */ 6048 bge_free_tx_ring(sc); 6049 6050 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6051 6052 /* Clear MAC's link state (PHY may still have link UP). */ 6053 if (bootverbose && sc->bge_link) 6054 if_printf(sc->bge_ifp, "link DOWN\n"); 6055 sc->bge_link = 0; 6056 6057 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6058 } 6059 6060 /* 6061 * Stop all chip I/O so that the kernel's probe routines don't 6062 * get confused by errant DMAs when rebooting. 6063 */ 6064 static int 6065 bge_shutdown(device_t dev) 6066 { 6067 struct bge_softc *sc; 6068 6069 sc = device_get_softc(dev); 6070 BGE_LOCK(sc); 6071 bge_stop(sc); 6072 BGE_UNLOCK(sc); 6073 6074 return (0); 6075 } 6076 6077 static int 6078 bge_suspend(device_t dev) 6079 { 6080 struct bge_softc *sc; 6081 6082 sc = device_get_softc(dev); 6083 BGE_LOCK(sc); 6084 bge_stop(sc); 6085 BGE_UNLOCK(sc); 6086 6087 return (0); 6088 } 6089 6090 static int 6091 bge_resume(device_t dev) 6092 { 6093 struct bge_softc *sc; 6094 struct ifnet *ifp; 6095 6096 sc = device_get_softc(dev); 6097 BGE_LOCK(sc); 6098 ifp = sc->bge_ifp; 6099 if (ifp->if_flags & IFF_UP) { 6100 bge_init_locked(sc); 6101 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6102 bge_start_locked(ifp); 6103 } 6104 BGE_UNLOCK(sc); 6105 6106 return (0); 6107 } 6108 6109 static void 6110 bge_link_upd(struct bge_softc *sc) 6111 { 6112 struct mii_data *mii; 6113 uint32_t link, status; 6114 6115 BGE_LOCK_ASSERT(sc); 6116 6117 /* Clear 'pending link event' flag. */ 6118 sc->bge_link_evt = 0; 6119 6120 /* 6121 * Process link state changes. 6122 * Grrr. The link status word in the status block does 6123 * not work correctly on the BCM5700 rev AX and BX chips, 6124 * according to all available information. Hence, we have 6125 * to enable MII interrupts in order to properly obtain 6126 * async link changes. Unfortunately, this also means that 6127 * we have to read the MAC status register to detect link 6128 * changes, thereby adding an additional register access to 6129 * the interrupt handler. 6130 * 6131 * XXX: perhaps link state detection procedure used for 6132 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6133 */ 6134 6135 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6136 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6137 status = CSR_READ_4(sc, BGE_MAC_STS); 6138 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6139 mii = device_get_softc(sc->bge_miibus); 6140 mii_pollstat(mii); 6141 if (!sc->bge_link && 6142 mii->mii_media_status & IFM_ACTIVE && 6143 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6144 sc->bge_link++; 6145 if (bootverbose) 6146 if_printf(sc->bge_ifp, "link UP\n"); 6147 } else if (sc->bge_link && 6148 (!(mii->mii_media_status & IFM_ACTIVE) || 6149 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6150 sc->bge_link = 0; 6151 if (bootverbose) 6152 if_printf(sc->bge_ifp, "link DOWN\n"); 6153 } 6154 6155 /* Clear the interrupt. */ 6156 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6157 BGE_EVTENB_MI_INTERRUPT); 6158 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6159 BRGPHY_MII_ISR); 6160 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6161 BRGPHY_MII_IMR, BRGPHY_INTRS); 6162 } 6163 return; 6164 } 6165 6166 if (sc->bge_flags & BGE_FLAG_TBI) { 6167 status = CSR_READ_4(sc, BGE_MAC_STS); 6168 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6169 if (!sc->bge_link) { 6170 sc->bge_link++; 6171 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6172 BGE_CLRBIT(sc, BGE_MAC_MODE, 6173 BGE_MACMODE_TBI_SEND_CFGS); 6174 DELAY(40); 6175 } 6176 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6177 if (bootverbose) 6178 if_printf(sc->bge_ifp, "link UP\n"); 6179 if_link_state_change(sc->bge_ifp, 6180 LINK_STATE_UP); 6181 } 6182 } else if (sc->bge_link) { 6183 sc->bge_link = 0; 6184 if (bootverbose) 6185 if_printf(sc->bge_ifp, "link DOWN\n"); 6186 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6187 } 6188 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6189 /* 6190 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6191 * in status word always set. Workaround this bug by reading 6192 * PHY link status directly. 6193 */ 6194 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6195 6196 if (link != sc->bge_link || 6197 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6198 mii = device_get_softc(sc->bge_miibus); 6199 mii_pollstat(mii); 6200 if (!sc->bge_link && 6201 mii->mii_media_status & IFM_ACTIVE && 6202 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6203 sc->bge_link++; 6204 if (bootverbose) 6205 if_printf(sc->bge_ifp, "link UP\n"); 6206 } else if (sc->bge_link && 6207 (!(mii->mii_media_status & IFM_ACTIVE) || 6208 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6209 sc->bge_link = 0; 6210 if (bootverbose) 6211 if_printf(sc->bge_ifp, "link DOWN\n"); 6212 } 6213 } 6214 } else { 6215 /* 6216 * For controllers that call mii_tick, we have to poll 6217 * link status. 6218 */ 6219 mii = device_get_softc(sc->bge_miibus); 6220 mii_pollstat(mii); 6221 bge_miibus_statchg(sc->bge_dev); 6222 } 6223 6224 /* Disable MAC attention when link is up. */ 6225 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6226 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6227 BGE_MACSTAT_LINK_CHANGED); 6228 } 6229 6230 static void 6231 bge_add_sysctls(struct bge_softc *sc) 6232 { 6233 struct sysctl_ctx_list *ctx; 6234 struct sysctl_oid_list *children; 6235 char tn[32]; 6236 int unit; 6237 6238 ctx = device_get_sysctl_ctx(sc->bge_dev); 6239 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6240 6241 #ifdef BGE_REGISTER_DEBUG 6242 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6243 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6244 "Debug Information"); 6245 6246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6247 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6248 "MAC Register Read"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6251 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6252 "APE Register Read"); 6253 6254 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6255 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6256 "Memory Read"); 6257 6258 #endif 6259 6260 unit = device_get_unit(sc->bge_dev); 6261 /* 6262 * A common design characteristic for many Broadcom client controllers 6263 * is that they only support a single outstanding DMA read operation 6264 * on the PCIe bus. This means that it will take twice as long to fetch 6265 * a TX frame that is split into header and payload buffers as it does 6266 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6267 * these controllers, coalescing buffers to reduce the number of memory 6268 * reads is effective way to get maximum performance(about 940Mbps). 6269 * Without collapsing TX buffers the maximum TCP bulk transfer 6270 * performance is about 850Mbps. However forcing coalescing mbufs 6271 * consumes a lot of CPU cycles, so leave it off by default. 6272 */ 6273 sc->bge_forced_collapse = 0; 6274 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6275 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6276 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6277 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6278 "Number of fragmented TX buffers of a frame allowed before " 6279 "forced collapsing"); 6280 6281 sc->bge_msi = 1; 6282 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6283 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6285 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6286 6287 /* 6288 * It seems all Broadcom controllers have a bug that can generate UDP 6289 * datagrams with checksum value 0 when TX UDP checksum offloading is 6290 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6291 * Even though the probability of generating such UDP datagrams is 6292 * low, I don't want to see FreeBSD boxes to inject such datagrams 6293 * into network so disable UDP checksum offloading by default. Users 6294 * still override this behavior by setting a sysctl variable, 6295 * dev.bge.0.forced_udpcsum. 6296 */ 6297 sc->bge_forced_udpcsum = 0; 6298 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6299 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6300 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6301 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6302 "Enable UDP checksum offloading even if controller can " 6303 "generate UDP checksum value 0"); 6304 6305 if (BGE_IS_5705_PLUS(sc)) 6306 bge_add_sysctl_stats_regs(sc, ctx, children); 6307 else 6308 bge_add_sysctl_stats(sc, ctx, children); 6309 } 6310 6311 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6312 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6313 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6314 desc) 6315 6316 static void 6317 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6318 struct sysctl_oid_list *parent) 6319 { 6320 struct sysctl_oid *tree; 6321 struct sysctl_oid_list *children, *schildren; 6322 6323 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6324 NULL, "BGE Statistics"); 6325 schildren = children = SYSCTL_CHILDREN(tree); 6326 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6327 children, COSFramesDroppedDueToFilters, 6328 "FramesDroppedDueToFilters"); 6329 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6330 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6331 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6332 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6333 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6334 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6335 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6336 children, ifInDiscards, "InputDiscards"); 6337 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6338 children, ifInErrors, "InputErrors"); 6339 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6340 children, nicRecvThresholdHit, "RecvThresholdHit"); 6341 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6342 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6343 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6344 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6345 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6346 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6347 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6348 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6349 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6350 children, nicRingStatusUpdate, "RingStatusUpdate"); 6351 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6352 children, nicInterrupts, "Interrupts"); 6353 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6354 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6355 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6356 children, nicSendThresholdHit, "SendThresholdHit"); 6357 6358 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6359 NULL, "BGE RX Statistics"); 6360 children = SYSCTL_CHILDREN(tree); 6361 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6362 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6363 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6364 children, rxstats.etherStatsFragments, "Fragments"); 6365 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6366 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6367 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6368 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6369 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6370 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6371 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6372 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6373 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6374 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6375 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6376 children, rxstats.xoffPauseFramesReceived, 6377 "xoffPauseFramesReceived"); 6378 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6379 children, rxstats.macControlFramesReceived, 6380 "ControlFramesReceived"); 6381 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6382 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6383 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6384 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6385 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6386 children, rxstats.etherStatsJabbers, "Jabbers"); 6387 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6388 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6390 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6391 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6392 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6393 6394 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6395 NULL, "BGE TX Statistics"); 6396 children = SYSCTL_CHILDREN(tree); 6397 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6398 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6399 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6400 children, txstats.etherStatsCollisions, "Collisions"); 6401 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6402 children, txstats.outXonSent, "XonSent"); 6403 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6404 children, txstats.outXoffSent, "XoffSent"); 6405 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6406 children, txstats.flowControlDone, "flowControlDone"); 6407 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6408 children, txstats.dot3StatsInternalMacTransmitErrors, 6409 "InternalMacTransmitErrors"); 6410 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6411 children, txstats.dot3StatsSingleCollisionFrames, 6412 "SingleCollisionFrames"); 6413 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6414 children, txstats.dot3StatsMultipleCollisionFrames, 6415 "MultipleCollisionFrames"); 6416 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6417 children, txstats.dot3StatsDeferredTransmissions, 6418 "DeferredTransmissions"); 6419 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6420 children, txstats.dot3StatsExcessiveCollisions, 6421 "ExcessiveCollisions"); 6422 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6423 children, txstats.dot3StatsLateCollisions, 6424 "LateCollisions"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6426 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6427 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6428 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6429 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6430 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6431 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6432 children, txstats.dot3StatsCarrierSenseErrors, 6433 "CarrierSenseErrors"); 6434 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6435 children, txstats.ifOutDiscards, "Discards"); 6436 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6437 children, txstats.ifOutErrors, "Errors"); 6438 } 6439 6440 #undef BGE_SYSCTL_STAT 6441 6442 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6443 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6444 6445 static void 6446 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6447 struct sysctl_oid_list *parent) 6448 { 6449 struct sysctl_oid *tree; 6450 struct sysctl_oid_list *child, *schild; 6451 struct bge_mac_stats *stats; 6452 6453 stats = &sc->bge_mac_stats; 6454 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6455 NULL, "BGE Statistics"); 6456 schild = child = SYSCTL_CHILDREN(tree); 6457 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6458 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6459 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6460 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6461 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6462 &stats->DmaWriteHighPriQueueFull, 6463 "NIC DMA Write High Priority Queue Full"); 6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6465 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6467 &stats->InputDiscards, "Discarded Input Frames"); 6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6469 &stats->InputErrors, "Input Errors"); 6470 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6471 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6472 6473 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6474 NULL, "BGE RX Statistics"); 6475 child = SYSCTL_CHILDREN(tree); 6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6477 &stats->ifHCInOctets, "Inbound Octets"); 6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6479 &stats->etherStatsFragments, "Fragments"); 6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6481 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6483 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6485 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6487 &stats->dot3StatsFCSErrors, "FCS Errors"); 6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6489 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6491 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6493 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6495 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6497 &stats->xoffStateEntered, "XOFF State Entered"); 6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6499 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6501 &stats->etherStatsJabbers, "Jabbers"); 6502 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6503 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6504 6505 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6506 NULL, "BGE TX Statistics"); 6507 child = SYSCTL_CHILDREN(tree); 6508 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6509 &stats->ifHCOutOctets, "Outbound Octets"); 6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6511 &stats->etherStatsCollisions, "TX Collisions"); 6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6513 &stats->outXonSent, "XON Sent"); 6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6515 &stats->outXoffSent, "XOFF Sent"); 6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6517 &stats->dot3StatsInternalMacTransmitErrors, 6518 "Internal MAC TX Errors"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6520 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6521 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6522 &stats->dot3StatsMultipleCollisionFrames, 6523 "Multiple Collision Frames"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6525 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6527 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6529 &stats->dot3StatsLateCollisions, "Late Collisions"); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6531 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6533 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6534 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6535 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6536 } 6537 6538 #undef BGE_SYSCTL_STAT_ADD64 6539 6540 static int 6541 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6542 { 6543 struct bge_softc *sc; 6544 uint32_t result; 6545 int offset; 6546 6547 sc = (struct bge_softc *)arg1; 6548 offset = arg2; 6549 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6550 offsetof(bge_hostaddr, bge_addr_lo)); 6551 return (sysctl_handle_int(oidp, &result, 0, req)); 6552 } 6553 6554 #ifdef BGE_REGISTER_DEBUG 6555 static int 6556 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6557 { 6558 struct bge_softc *sc; 6559 uint16_t *sbdata; 6560 int error, result, sbsz; 6561 int i, j; 6562 6563 result = -1; 6564 error = sysctl_handle_int(oidp, &result, 0, req); 6565 if (error || (req->newptr == NULL)) 6566 return (error); 6567 6568 if (result == 1) { 6569 sc = (struct bge_softc *)arg1; 6570 6571 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6572 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6573 sbsz = BGE_STATUS_BLK_SZ; 6574 else 6575 sbsz = 32; 6576 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6577 printf("Status Block:\n"); 6578 BGE_LOCK(sc); 6579 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6580 sc->bge_cdata.bge_status_map, 6581 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6582 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6583 printf("%06x:", i); 6584 for (j = 0; j < 8; j++) 6585 printf(" %04x", sbdata[i++]); 6586 printf("\n"); 6587 } 6588 6589 printf("Registers:\n"); 6590 for (i = 0x800; i < 0xA00; ) { 6591 printf("%06x:", i); 6592 for (j = 0; j < 8; j++) { 6593 printf(" %08x", CSR_READ_4(sc, i)); 6594 i += 4; 6595 } 6596 printf("\n"); 6597 } 6598 BGE_UNLOCK(sc); 6599 6600 printf("Hardware Flags:\n"); 6601 if (BGE_IS_5717_PLUS(sc)) 6602 printf(" - 5717 Plus\n"); 6603 if (BGE_IS_5755_PLUS(sc)) 6604 printf(" - 5755 Plus\n"); 6605 if (BGE_IS_575X_PLUS(sc)) 6606 printf(" - 575X Plus\n"); 6607 if (BGE_IS_5705_PLUS(sc)) 6608 printf(" - 5705 Plus\n"); 6609 if (BGE_IS_5714_FAMILY(sc)) 6610 printf(" - 5714 Family\n"); 6611 if (BGE_IS_5700_FAMILY(sc)) 6612 printf(" - 5700 Family\n"); 6613 if (sc->bge_flags & BGE_FLAG_JUMBO) 6614 printf(" - Supports Jumbo Frames\n"); 6615 if (sc->bge_flags & BGE_FLAG_PCIX) 6616 printf(" - PCI-X Bus\n"); 6617 if (sc->bge_flags & BGE_FLAG_PCIE) 6618 printf(" - PCI Express Bus\n"); 6619 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6620 printf(" - No 3 LEDs\n"); 6621 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6622 printf(" - RX Alignment Bug\n"); 6623 } 6624 6625 return (error); 6626 } 6627 6628 static int 6629 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6630 { 6631 struct bge_softc *sc; 6632 int error; 6633 uint16_t result; 6634 uint32_t val; 6635 6636 result = -1; 6637 error = sysctl_handle_int(oidp, &result, 0, req); 6638 if (error || (req->newptr == NULL)) 6639 return (error); 6640 6641 if (result < 0x8000) { 6642 sc = (struct bge_softc *)arg1; 6643 val = CSR_READ_4(sc, result); 6644 printf("reg 0x%06X = 0x%08X\n", result, val); 6645 } 6646 6647 return (error); 6648 } 6649 6650 static int 6651 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6652 { 6653 struct bge_softc *sc; 6654 int error; 6655 uint16_t result; 6656 uint32_t val; 6657 6658 result = -1; 6659 error = sysctl_handle_int(oidp, &result, 0, req); 6660 if (error || (req->newptr == NULL)) 6661 return (error); 6662 6663 if (result < 0x8000) { 6664 sc = (struct bge_softc *)arg1; 6665 val = APE_READ_4(sc, result); 6666 printf("reg 0x%06X = 0x%08X\n", result, val); 6667 } 6668 6669 return (error); 6670 } 6671 6672 static int 6673 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6674 { 6675 struct bge_softc *sc; 6676 int error; 6677 uint16_t result; 6678 uint32_t val; 6679 6680 result = -1; 6681 error = sysctl_handle_int(oidp, &result, 0, req); 6682 if (error || (req->newptr == NULL)) 6683 return (error); 6684 6685 if (result < 0x8000) { 6686 sc = (struct bge_softc *)arg1; 6687 val = bge_readmem_ind(sc, result); 6688 printf("mem 0x%06X = 0x%08X\n", result, val); 6689 } 6690 6691 return (error); 6692 } 6693 #endif 6694 6695 static int 6696 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6697 { 6698 6699 if (sc->bge_flags & BGE_FLAG_EADDR) 6700 return (1); 6701 6702 #ifdef __sparc64__ 6703 OF_getetheraddr(sc->bge_dev, ether_addr); 6704 return (0); 6705 #endif 6706 return (1); 6707 } 6708 6709 static int 6710 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6711 { 6712 uint32_t mac_addr; 6713 6714 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6715 if ((mac_addr >> 16) == 0x484b) { 6716 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6717 ether_addr[1] = (uint8_t)mac_addr; 6718 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6719 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6720 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6721 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6722 ether_addr[5] = (uint8_t)mac_addr; 6723 return (0); 6724 } 6725 return (1); 6726 } 6727 6728 static int 6729 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6730 { 6731 int mac_offset = BGE_EE_MAC_OFFSET; 6732 6733 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6734 mac_offset = BGE_EE_MAC_OFFSET_5906; 6735 6736 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6737 ETHER_ADDR_LEN)); 6738 } 6739 6740 static int 6741 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6742 { 6743 6744 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6745 return (1); 6746 6747 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6748 ETHER_ADDR_LEN)); 6749 } 6750 6751 static int 6752 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6753 { 6754 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6755 /* NOTE: Order is critical */ 6756 bge_get_eaddr_fw, 6757 bge_get_eaddr_mem, 6758 bge_get_eaddr_nvram, 6759 bge_get_eaddr_eeprom, 6760 NULL 6761 }; 6762 const bge_eaddr_fcn_t *func; 6763 6764 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6765 if ((*func)(sc, eaddr) == 0) 6766 break; 6767 } 6768 return (*func == NULL ? ENXIO : 0); 6769 } 6770