1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 41 * 42 * The Broadcom BCM5700 is based on technology originally developed by 43 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 44 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 45 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 46 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 47 * frames, highly configurable RX filtering, and 16 RX and TX queues 48 * (which, along with RX filter rules, can be used for QOS applications). 49 * Other features, such as TCP segmentation, may be available as part 50 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 51 * firmware images can be stored in hardware and need not be compiled 52 * into the driver. 53 * 54 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 55 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 56 * 57 * The BCM5701 is a single-chip solution incorporating both the BCM5700 58 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 59 * does not support external SSRAM. 60 * 61 * Broadcom also produces a variation of the BCM5700 under the "Altima" 62 * brand name, which is functionally similar but lacks PCI-X support. 63 * 64 * Without external SSRAM, you can only have at most 4 TX rings, 65 * and the use of the mini RX ring is disabled. This seems to imply 66 * that these features are simply not available on the BCM5701. As a 67 * result, this driver does not implement any support for the mini RX 68 * ring. 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_device_polling.h" 73 #endif 74 75 #include <sys/param.h> 76 #include <sys/endian.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/module.h> 83 #include <sys/socket.h> 84 #include <sys/sysctl.h> 85 #include <sys/taskqueue.h> 86 87 #include <net/debugnet.h> 88 #include <net/if.h> 89 #include <net/if_var.h> 90 #include <net/if_arp.h> 91 #include <net/ethernet.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 95 #include <net/bpf.h> 96 97 #include <net/if_types.h> 98 #include <net/if_vlan_var.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 #include "miidevs.h" 113 #include <dev/mii/brgphyreg.h> 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 118 #include <dev/bge/if_bgereg.h> 119 120 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 121 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 122 123 MODULE_DEPEND(bge, pci, 1, 1, 1); 124 MODULE_DEPEND(bge, ether, 1, 1, 1); 125 MODULE_DEPEND(bge, miibus, 1, 1, 1); 126 127 /* "device miibus" required. See GENERIC if you get errors here. */ 128 #include "miibus_if.h" 129 130 /* 131 * Various supported device vendors/types and their names. Note: the 132 * spec seems to indicate that the hardware still has Alteon's vendor 133 * ID burned into it, though it will always be overriden by the vendor 134 * ID in the EEPROM. Just to be safe, we cover all possibilities. 135 */ 136 static const struct bge_type { 137 uint16_t bge_vid; 138 uint16_t bge_did; 139 } bge_devs[] = { 140 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 142 143 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 146 147 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 148 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 235 236 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 237 238 { TC_VENDORID, TC_DEVICEID_3C996 }, 239 240 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 241 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 242 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 243 { 0, 0 } 244 }; 245 246 static const struct bge_vendor { 247 uint16_t v_id; 248 const char *v_name; 249 } bge_vendors[] = { 250 { ALTEON_VENDORID, "Alteon" }, 251 { ALTIMA_VENDORID, "Altima" }, 252 { APPLE_VENDORID, "Apple" }, 253 { BCOM_VENDORID, "Broadcom" }, 254 { SK_VENDORID, "SysKonnect" }, 255 { TC_VENDORID, "3Com" }, 256 { FJTSU_VENDORID, "Fujitsu" }, 257 { 0, NULL } 258 }; 259 260 static const struct bge_revision { 261 uint32_t br_chipid; 262 const char *br_name; 263 } bge_revisions[] = { 264 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 265 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 266 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 267 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 268 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 269 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 270 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 271 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 272 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 273 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 274 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 275 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 276 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 277 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 278 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 279 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 280 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 281 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 282 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 283 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 284 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 285 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 286 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 287 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 288 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 289 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 290 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 291 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 292 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 293 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 294 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 295 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 296 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 297 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 298 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 299 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 300 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 301 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 302 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 303 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 304 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 305 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 306 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 307 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 308 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 309 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" }, 310 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 311 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 312 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 313 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 314 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 315 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 316 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 317 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 318 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 319 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 320 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 321 /* 5754 and 5787 share the same ASIC ID */ 322 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 323 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 324 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 325 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 326 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 327 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 328 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 329 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 330 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 331 { 0, NULL } 332 }; 333 334 /* 335 * Some defaults for major revisions, so that newer steppings 336 * that we don't know about have a shot at working. 337 */ 338 static const struct bge_revision bge_majorrevs[] = { 339 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 340 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 341 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 342 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 343 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 344 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 345 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 346 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 347 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 348 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 349 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 350 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 351 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 352 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 353 /* 5754 and 5787 share the same ASIC ID */ 354 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 355 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 356 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 357 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 358 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 359 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 360 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 361 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 362 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 363 { 0, NULL } 364 }; 365 366 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 367 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 368 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 369 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 370 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 371 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 372 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 373 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 374 375 static uint32_t bge_chipid(device_t); 376 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 377 static const struct bge_revision * bge_lookup_rev(uint32_t); 378 379 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 380 381 static int bge_probe(device_t); 382 static int bge_attach(device_t); 383 static int bge_detach(device_t); 384 static int bge_suspend(device_t); 385 static int bge_resume(device_t); 386 static void bge_release_resources(struct bge_softc *); 387 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 388 static int bge_dma_alloc(struct bge_softc *); 389 static void bge_dma_free(struct bge_softc *); 390 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 391 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 392 393 static void bge_devinfo(struct bge_softc *); 394 static int bge_mbox_reorder(struct bge_softc *); 395 396 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 397 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 398 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 399 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 400 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 401 402 static void bge_txeof(struct bge_softc *, uint16_t); 403 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 404 static int bge_rxeof(struct bge_softc *, uint16_t, int); 405 406 static void bge_asf_driver_up (struct bge_softc *); 407 static void bge_tick(void *); 408 static void bge_stats_clear_regs(struct bge_softc *); 409 static void bge_stats_update(struct bge_softc *); 410 static void bge_stats_update_regs(struct bge_softc *); 411 static struct mbuf *bge_check_short_dma(struct mbuf *); 412 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 413 uint16_t *, uint16_t *); 414 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 415 416 static void bge_intr(void *); 417 static int bge_msi_intr(void *); 418 static void bge_intr_task(void *, int); 419 static void bge_start(if_t); 420 static void bge_start_locked(if_t); 421 static void bge_start_tx(struct bge_softc *, uint32_t); 422 static int bge_ioctl(if_t, u_long, caddr_t); 423 static void bge_init_locked(struct bge_softc *); 424 static void bge_init(void *); 425 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 426 static void bge_stop(struct bge_softc *); 427 static void bge_watchdog(struct bge_softc *); 428 static int bge_shutdown(device_t); 429 static int bge_ifmedia_upd_locked(if_t); 430 static int bge_ifmedia_upd(if_t); 431 static void bge_ifmedia_sts(if_t, struct ifmediareq *); 432 static uint64_t bge_get_counter(if_t, ift_counter); 433 434 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 435 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 436 437 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 438 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 439 440 static void bge_setpromisc(struct bge_softc *); 441 static void bge_setmulti(struct bge_softc *); 442 static void bge_setvlan(struct bge_softc *); 443 444 static __inline void bge_rxreuse_std(struct bge_softc *, int); 445 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 446 static int bge_newbuf_std(struct bge_softc *, int); 447 static int bge_newbuf_jumbo(struct bge_softc *, int); 448 static int bge_init_rx_ring_std(struct bge_softc *); 449 static void bge_free_rx_ring_std(struct bge_softc *); 450 static int bge_init_rx_ring_jumbo(struct bge_softc *); 451 static void bge_free_rx_ring_jumbo(struct bge_softc *); 452 static void bge_free_tx_ring(struct bge_softc *); 453 static int bge_init_tx_ring(struct bge_softc *); 454 455 static int bge_chipinit(struct bge_softc *); 456 static int bge_blockinit(struct bge_softc *); 457 static uint32_t bge_dma_swap_options(struct bge_softc *); 458 459 static int bge_has_eaddr(struct bge_softc *); 460 static uint32_t bge_readmem_ind(struct bge_softc *, int); 461 static void bge_writemem_ind(struct bge_softc *, int, int); 462 static void bge_writembx(struct bge_softc *, int, int); 463 #ifdef notdef 464 static uint32_t bge_readreg_ind(struct bge_softc *, int); 465 #endif 466 static void bge_writemem_direct(struct bge_softc *, int, int); 467 static void bge_writereg_ind(struct bge_softc *, int, int); 468 469 static int bge_miibus_readreg(device_t, int, int); 470 static int bge_miibus_writereg(device_t, int, int, int); 471 static void bge_miibus_statchg(device_t); 472 #ifdef DEVICE_POLLING 473 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 474 #endif 475 476 #define BGE_RESET_SHUTDOWN 0 477 #define BGE_RESET_START 1 478 #define BGE_RESET_SUSPEND 2 479 static void bge_sig_post_reset(struct bge_softc *, int); 480 static void bge_sig_legacy(struct bge_softc *, int); 481 static void bge_sig_pre_reset(struct bge_softc *, int); 482 static void bge_stop_fw(struct bge_softc *); 483 static int bge_reset(struct bge_softc *); 484 static void bge_link_upd(struct bge_softc *); 485 486 static void bge_ape_lock_init(struct bge_softc *); 487 static void bge_ape_read_fw_ver(struct bge_softc *); 488 static int bge_ape_lock(struct bge_softc *, int); 489 static void bge_ape_unlock(struct bge_softc *, int); 490 static void bge_ape_send_event(struct bge_softc *, uint32_t); 491 static void bge_ape_driver_state_change(struct bge_softc *, int); 492 493 /* 494 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 495 * leak information to untrusted users. It is also known to cause alignment 496 * traps on certain architectures. 497 */ 498 #ifdef BGE_REGISTER_DEBUG 499 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 500 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 501 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 502 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 503 #endif 504 static void bge_add_sysctls(struct bge_softc *); 505 static void bge_add_sysctl_stats_regs(struct bge_softc *, 506 struct sysctl_ctx_list *, struct sysctl_oid_list *); 507 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 508 struct sysctl_oid_list *); 509 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 510 511 DEBUGNET_DEFINE(bge); 512 513 static device_method_t bge_methods[] = { 514 /* Device interface */ 515 DEVMETHOD(device_probe, bge_probe), 516 DEVMETHOD(device_attach, bge_attach), 517 DEVMETHOD(device_detach, bge_detach), 518 DEVMETHOD(device_shutdown, bge_shutdown), 519 DEVMETHOD(device_suspend, bge_suspend), 520 DEVMETHOD(device_resume, bge_resume), 521 522 /* MII interface */ 523 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 524 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 525 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 526 527 DEVMETHOD_END 528 }; 529 530 static driver_t bge_driver = { 531 "bge", 532 bge_methods, 533 sizeof(struct bge_softc) 534 }; 535 536 static devclass_t bge_devclass; 537 538 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 539 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs, 540 nitems(bge_devs) - 1); 541 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 542 543 static int bge_allow_asf = 1; 544 545 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 546 "BGE driver parameters"); 547 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 548 "Allow ASF mode if available"); 549 550 static int 551 bge_has_eaddr(struct bge_softc *sc) 552 { 553 return (1); 554 } 555 556 static uint32_t 557 bge_readmem_ind(struct bge_softc *sc, int off) 558 { 559 device_t dev; 560 uint32_t val; 561 562 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 563 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 564 return (0); 565 566 dev = sc->bge_dev; 567 568 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 569 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 570 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 571 return (val); 572 } 573 574 static void 575 bge_writemem_ind(struct bge_softc *sc, int off, int val) 576 { 577 device_t dev; 578 579 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 580 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 581 return; 582 583 dev = sc->bge_dev; 584 585 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 586 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 587 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 588 } 589 590 #ifdef notdef 591 static uint32_t 592 bge_readreg_ind(struct bge_softc *sc, int off) 593 { 594 device_t dev; 595 596 dev = sc->bge_dev; 597 598 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 599 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 600 } 601 #endif 602 603 static void 604 bge_writereg_ind(struct bge_softc *sc, int off, int val) 605 { 606 device_t dev; 607 608 dev = sc->bge_dev; 609 610 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 611 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 612 } 613 614 static void 615 bge_writemem_direct(struct bge_softc *sc, int off, int val) 616 { 617 CSR_WRITE_4(sc, off, val); 618 } 619 620 static void 621 bge_writembx(struct bge_softc *sc, int off, int val) 622 { 623 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 624 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 625 626 CSR_WRITE_4(sc, off, val); 627 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 628 CSR_READ_4(sc, off); 629 } 630 631 /* 632 * Clear all stale locks and select the lock for this driver instance. 633 */ 634 static void 635 bge_ape_lock_init(struct bge_softc *sc) 636 { 637 uint32_t bit, regbase; 638 int i; 639 640 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 641 regbase = BGE_APE_LOCK_GRANT; 642 else 643 regbase = BGE_APE_PER_LOCK_GRANT; 644 645 /* Clear any stale locks. */ 646 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 647 switch (i) { 648 case BGE_APE_LOCK_PHY0: 649 case BGE_APE_LOCK_PHY1: 650 case BGE_APE_LOCK_PHY2: 651 case BGE_APE_LOCK_PHY3: 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 break; 654 default: 655 if (sc->bge_func_addr == 0) 656 bit = BGE_APE_LOCK_GRANT_DRIVER0; 657 else 658 bit = (1 << sc->bge_func_addr); 659 } 660 APE_WRITE_4(sc, regbase + 4 * i, bit); 661 } 662 663 /* Select the PHY lock based on the device's function number. */ 664 switch (sc->bge_func_addr) { 665 case 0: 666 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 667 break; 668 case 1: 669 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 670 break; 671 case 2: 672 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 673 break; 674 case 3: 675 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 676 break; 677 default: 678 device_printf(sc->bge_dev, 679 "PHY lock not supported on this function\n"); 680 } 681 } 682 683 /* 684 * Check for APE firmware, set flags, and print version info. 685 */ 686 static void 687 bge_ape_read_fw_ver(struct bge_softc *sc) 688 { 689 const char *fwtype; 690 uint32_t apedata, features; 691 692 /* Check for a valid APE signature in shared memory. */ 693 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 694 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 695 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 696 return; 697 } 698 699 /* Check if APE firmware is running. */ 700 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 701 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 702 device_printf(sc->bge_dev, "APE signature found " 703 "but FW status not ready! 0x%08x\n", apedata); 704 return; 705 } 706 707 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 708 709 /* Fetch the APE firwmare type and version. */ 710 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 711 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 712 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 714 fwtype = "NCSI"; 715 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 716 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 717 fwtype = "DASH"; 718 } else 719 fwtype = "UNKN"; 720 721 /* Print the APE firmware version. */ 722 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 723 fwtype, 724 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 725 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 726 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 727 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 728 } 729 730 static int 731 bge_ape_lock(struct bge_softc *sc, int locknum) 732 { 733 uint32_t bit, gnt, req, status; 734 int i, off; 735 736 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 737 return (0); 738 739 /* Lock request/grant registers have different bases. */ 740 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 741 req = BGE_APE_LOCK_REQ; 742 gnt = BGE_APE_LOCK_GRANT; 743 } else { 744 req = BGE_APE_PER_LOCK_REQ; 745 gnt = BGE_APE_PER_LOCK_GRANT; 746 } 747 748 off = 4 * locknum; 749 750 switch (locknum) { 751 case BGE_APE_LOCK_GPIO: 752 /* Lock required when using GPIO. */ 753 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 754 return (0); 755 if (sc->bge_func_addr == 0) 756 bit = BGE_APE_LOCK_REQ_DRIVER0; 757 else 758 bit = (1 << sc->bge_func_addr); 759 break; 760 case BGE_APE_LOCK_GRC: 761 /* Lock required to reset the device. */ 762 if (sc->bge_func_addr == 0) 763 bit = BGE_APE_LOCK_REQ_DRIVER0; 764 else 765 bit = (1 << sc->bge_func_addr); 766 break; 767 case BGE_APE_LOCK_MEM: 768 /* Lock required when accessing certain APE memory. */ 769 if (sc->bge_func_addr == 0) 770 bit = BGE_APE_LOCK_REQ_DRIVER0; 771 else 772 bit = (1 << sc->bge_func_addr); 773 break; 774 case BGE_APE_LOCK_PHY0: 775 case BGE_APE_LOCK_PHY1: 776 case BGE_APE_LOCK_PHY2: 777 case BGE_APE_LOCK_PHY3: 778 /* Lock required when accessing PHYs. */ 779 bit = BGE_APE_LOCK_REQ_DRIVER0; 780 break; 781 default: 782 return (EINVAL); 783 } 784 785 /* Request a lock. */ 786 APE_WRITE_4(sc, req + off, bit); 787 788 /* Wait up to 1 second to acquire lock. */ 789 for (i = 0; i < 20000; i++) { 790 status = APE_READ_4(sc, gnt + off); 791 if (status == bit) 792 break; 793 DELAY(50); 794 } 795 796 /* Handle any errors. */ 797 if (status != bit) { 798 device_printf(sc->bge_dev, "APE lock %d request failed! " 799 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 800 locknum, req + off, bit & 0xFFFF, gnt + off, 801 status & 0xFFFF); 802 /* Revoke the lock request. */ 803 APE_WRITE_4(sc, gnt + off, bit); 804 return (EBUSY); 805 } 806 807 return (0); 808 } 809 810 static void 811 bge_ape_unlock(struct bge_softc *sc, int locknum) 812 { 813 uint32_t bit, gnt; 814 int off; 815 816 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 817 return; 818 819 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 820 gnt = BGE_APE_LOCK_GRANT; 821 else 822 gnt = BGE_APE_PER_LOCK_GRANT; 823 824 off = 4 * locknum; 825 826 switch (locknum) { 827 case BGE_APE_LOCK_GPIO: 828 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 829 return; 830 if (sc->bge_func_addr == 0) 831 bit = BGE_APE_LOCK_GRANT_DRIVER0; 832 else 833 bit = (1 << sc->bge_func_addr); 834 break; 835 case BGE_APE_LOCK_GRC: 836 if (sc->bge_func_addr == 0) 837 bit = BGE_APE_LOCK_GRANT_DRIVER0; 838 else 839 bit = (1 << sc->bge_func_addr); 840 break; 841 case BGE_APE_LOCK_MEM: 842 if (sc->bge_func_addr == 0) 843 bit = BGE_APE_LOCK_GRANT_DRIVER0; 844 else 845 bit = (1 << sc->bge_func_addr); 846 break; 847 case BGE_APE_LOCK_PHY0: 848 case BGE_APE_LOCK_PHY1: 849 case BGE_APE_LOCK_PHY2: 850 case BGE_APE_LOCK_PHY3: 851 bit = BGE_APE_LOCK_GRANT_DRIVER0; 852 break; 853 default: 854 return; 855 } 856 857 APE_WRITE_4(sc, gnt + off, bit); 858 } 859 860 /* 861 * Send an event to the APE firmware. 862 */ 863 static void 864 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 865 { 866 uint32_t apedata; 867 int i; 868 869 /* NCSI does not support APE events. */ 870 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 871 return; 872 873 /* Wait up to 1ms for APE to service previous event. */ 874 for (i = 10; i > 0; i--) { 875 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 876 break; 877 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 878 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 879 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 880 BGE_APE_EVENT_STATUS_EVENT_PENDING); 881 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 882 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 883 break; 884 } 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 DELAY(100); 887 } 888 if (i == 0) 889 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 890 event); 891 } 892 893 static void 894 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 895 { 896 uint32_t apedata, event; 897 898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 899 return; 900 901 switch (kind) { 902 case BGE_RESET_START: 903 /* If this is the first load, clear the load counter. */ 904 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 905 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 906 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 907 else { 908 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 910 } 911 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 912 BGE_APE_HOST_SEG_SIG_MAGIC); 913 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 914 BGE_APE_HOST_SEG_LEN_MAGIC); 915 916 /* Add some version info if bge(4) supports it. */ 917 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 918 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 919 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 920 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 921 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 922 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 924 BGE_APE_HOST_DRVR_STATE_START); 925 event = BGE_APE_EVENT_STATUS_STATE_START; 926 break; 927 case BGE_RESET_SHUTDOWN: 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_UNLOAD); 930 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 931 break; 932 case BGE_RESET_SUSPEND: 933 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 934 break; 935 default: 936 return; 937 } 938 939 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 940 BGE_APE_EVENT_STATUS_STATE_CHNGE); 941 } 942 943 /* 944 * Map a single buffer address. 945 */ 946 947 static void 948 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 949 { 950 struct bge_dmamap_arg *ctx; 951 952 if (error) 953 return; 954 955 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 956 957 ctx = arg; 958 ctx->bge_busaddr = segs->ds_addr; 959 } 960 961 static uint8_t 962 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 963 { 964 uint32_t access, byte = 0; 965 int i; 966 967 /* Lock. */ 968 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 969 for (i = 0; i < 8000; i++) { 970 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 971 break; 972 DELAY(20); 973 } 974 if (i == 8000) 975 return (1); 976 977 /* Enable access. */ 978 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 979 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 980 981 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 982 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 983 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 984 DELAY(10); 985 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 986 DELAY(10); 987 break; 988 } 989 } 990 991 if (i == BGE_TIMEOUT * 10) { 992 if_printf(sc->bge_ifp, "nvram read timed out\n"); 993 return (1); 994 } 995 996 /* Get result. */ 997 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 998 999 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1000 1001 /* Disable access. */ 1002 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1003 1004 /* Unlock. */ 1005 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1006 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1007 1008 return (0); 1009 } 1010 1011 /* 1012 * Read a sequence of bytes from NVRAM. 1013 */ 1014 static int 1015 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1016 { 1017 int err = 0, i; 1018 uint8_t byte = 0; 1019 1020 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1021 return (1); 1022 1023 for (i = 0; i < cnt; i++) { 1024 err = bge_nvram_getbyte(sc, off + i, &byte); 1025 if (err) 1026 break; 1027 *(dest + i) = byte; 1028 } 1029 1030 return (err ? 1 : 0); 1031 } 1032 1033 /* 1034 * Read a byte of data stored in the EEPROM at address 'addr.' The 1035 * BCM570x supports both the traditional bitbang interface and an 1036 * auto access interface for reading the EEPROM. We use the auto 1037 * access method. 1038 */ 1039 static uint8_t 1040 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1041 { 1042 int i; 1043 uint32_t byte = 0; 1044 1045 /* 1046 * Enable use of auto EEPROM access so we can avoid 1047 * having to use the bitbang method. 1048 */ 1049 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1050 1051 /* Reset the EEPROM, load the clock period. */ 1052 CSR_WRITE_4(sc, BGE_EE_ADDR, 1053 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1054 DELAY(20); 1055 1056 /* Issue the read EEPROM command. */ 1057 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1058 1059 /* Wait for completion */ 1060 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1061 DELAY(10); 1062 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1063 break; 1064 } 1065 1066 if (i == BGE_TIMEOUT * 10) { 1067 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1068 return (1); 1069 } 1070 1071 /* Get result. */ 1072 byte = CSR_READ_4(sc, BGE_EE_DATA); 1073 1074 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1075 1076 return (0); 1077 } 1078 1079 /* 1080 * Read a sequence of bytes from the EEPROM. 1081 */ 1082 static int 1083 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1084 { 1085 int i, error = 0; 1086 uint8_t byte = 0; 1087 1088 for (i = 0; i < cnt; i++) { 1089 error = bge_eeprom_getbyte(sc, off + i, &byte); 1090 if (error) 1091 break; 1092 *(dest + i) = byte; 1093 } 1094 1095 return (error ? 1 : 0); 1096 } 1097 1098 static int 1099 bge_miibus_readreg(device_t dev, int phy, int reg) 1100 { 1101 struct bge_softc *sc; 1102 uint32_t val; 1103 int i; 1104 1105 sc = device_get_softc(dev); 1106 1107 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1108 return (0); 1109 1110 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1111 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1112 CSR_WRITE_4(sc, BGE_MI_MODE, 1113 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1114 DELAY(80); 1115 } 1116 1117 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1118 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1119 1120 /* Poll for the PHY register access to complete. */ 1121 for (i = 0; i < BGE_TIMEOUT; i++) { 1122 DELAY(10); 1123 val = CSR_READ_4(sc, BGE_MI_COMM); 1124 if ((val & BGE_MICOMM_BUSY) == 0) { 1125 DELAY(5); 1126 val = CSR_READ_4(sc, BGE_MI_COMM); 1127 break; 1128 } 1129 } 1130 1131 if (i == BGE_TIMEOUT) { 1132 device_printf(sc->bge_dev, 1133 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1134 phy, reg, val); 1135 val = 0; 1136 } 1137 1138 /* Restore the autopoll bit if necessary. */ 1139 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1140 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1141 DELAY(80); 1142 } 1143 1144 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1145 1146 if (val & BGE_MICOMM_READFAIL) 1147 return (0); 1148 1149 return (val & 0xFFFF); 1150 } 1151 1152 static int 1153 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1154 { 1155 struct bge_softc *sc; 1156 int i; 1157 1158 sc = device_get_softc(dev); 1159 1160 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1161 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1162 return (0); 1163 1164 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1165 return (0); 1166 1167 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1168 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1169 CSR_WRITE_4(sc, BGE_MI_MODE, 1170 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1171 DELAY(80); 1172 } 1173 1174 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1175 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1176 1177 for (i = 0; i < BGE_TIMEOUT; i++) { 1178 DELAY(10); 1179 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1180 DELAY(5); 1181 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1182 break; 1183 } 1184 } 1185 1186 /* Restore the autopoll bit if necessary. */ 1187 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1188 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1189 DELAY(80); 1190 } 1191 1192 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1193 1194 if (i == BGE_TIMEOUT) 1195 device_printf(sc->bge_dev, 1196 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1197 phy, reg, val); 1198 1199 return (0); 1200 } 1201 1202 static void 1203 bge_miibus_statchg(device_t dev) 1204 { 1205 struct bge_softc *sc; 1206 struct mii_data *mii; 1207 uint32_t mac_mode, rx_mode, tx_mode; 1208 1209 sc = device_get_softc(dev); 1210 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1211 return; 1212 mii = device_get_softc(sc->bge_miibus); 1213 1214 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1215 (IFM_ACTIVE | IFM_AVALID)) { 1216 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1217 case IFM_10_T: 1218 case IFM_100_TX: 1219 sc->bge_link = 1; 1220 break; 1221 case IFM_1000_T: 1222 case IFM_1000_SX: 1223 case IFM_2500_SX: 1224 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1225 sc->bge_link = 1; 1226 else 1227 sc->bge_link = 0; 1228 break; 1229 default: 1230 sc->bge_link = 0; 1231 break; 1232 } 1233 } else 1234 sc->bge_link = 0; 1235 if (sc->bge_link == 0) 1236 return; 1237 1238 /* 1239 * APE firmware touches these registers to keep the MAC 1240 * connected to the outside world. Try to keep the 1241 * accesses atomic. 1242 */ 1243 1244 /* Set the port mode (MII/GMII) to match the link speed. */ 1245 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1246 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1247 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1248 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1249 1250 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1251 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1252 mac_mode |= BGE_PORTMODE_GMII; 1253 else 1254 mac_mode |= BGE_PORTMODE_MII; 1255 1256 /* Set MAC flow control behavior to match link flow control settings. */ 1257 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1258 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1259 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1260 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1261 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1262 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1263 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1264 } else 1265 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1266 1267 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1268 DELAY(40); 1269 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1270 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1271 } 1272 1273 /* 1274 * Intialize a standard receive ring descriptor. 1275 */ 1276 static int 1277 bge_newbuf_std(struct bge_softc *sc, int i) 1278 { 1279 struct mbuf *m; 1280 struct bge_rx_bd *r; 1281 bus_dma_segment_t segs[1]; 1282 bus_dmamap_t map; 1283 int error, nsegs; 1284 1285 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1286 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1287 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1288 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1289 if (m == NULL) 1290 return (ENOBUFS); 1291 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1292 } else { 1293 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1294 if (m == NULL) 1295 return (ENOBUFS); 1296 m->m_len = m->m_pkthdr.len = MCLBYTES; 1297 } 1298 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1299 m_adj(m, ETHER_ALIGN); 1300 1301 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1302 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1303 if (error != 0) { 1304 m_freem(m); 1305 return (error); 1306 } 1307 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1308 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1309 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1310 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1311 sc->bge_cdata.bge_rx_std_dmamap[i]); 1312 } 1313 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1314 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1315 sc->bge_cdata.bge_rx_std_sparemap = map; 1316 sc->bge_cdata.bge_rx_std_chain[i] = m; 1317 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1318 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1319 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1320 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1321 r->bge_flags = BGE_RXBDFLAG_END; 1322 r->bge_len = segs[0].ds_len; 1323 r->bge_idx = i; 1324 1325 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1326 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1327 1328 return (0); 1329 } 1330 1331 /* 1332 * Initialize a jumbo receive ring descriptor. This allocates 1333 * a jumbo buffer from the pool managed internally by the driver. 1334 */ 1335 static int 1336 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1337 { 1338 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1339 bus_dmamap_t map; 1340 struct bge_extrx_bd *r; 1341 struct mbuf *m; 1342 int error, nsegs; 1343 1344 MGETHDR(m, M_NOWAIT, MT_DATA); 1345 if (m == NULL) 1346 return (ENOBUFS); 1347 1348 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) { 1349 m_freem(m); 1350 return (ENOBUFS); 1351 } 1352 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1353 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1354 m_adj(m, ETHER_ALIGN); 1355 1356 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1357 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1358 if (error != 0) { 1359 m_freem(m); 1360 return (error); 1361 } 1362 1363 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1364 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1365 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1366 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1367 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1368 } 1369 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1370 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1371 sc->bge_cdata.bge_rx_jumbo_sparemap; 1372 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1373 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1374 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1375 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1376 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1377 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1378 1379 /* 1380 * Fill in the extended RX buffer descriptor. 1381 */ 1382 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1383 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1384 r->bge_idx = i; 1385 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1386 switch (nsegs) { 1387 case 4: 1388 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1389 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1390 r->bge_len3 = segs[3].ds_len; 1391 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1392 case 3: 1393 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1394 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1395 r->bge_len2 = segs[2].ds_len; 1396 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1397 case 2: 1398 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1399 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1400 r->bge_len1 = segs[1].ds_len; 1401 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1402 case 1: 1403 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1404 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1405 r->bge_len0 = segs[0].ds_len; 1406 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1407 break; 1408 default: 1409 panic("%s: %d segments\n", __func__, nsegs); 1410 } 1411 1412 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1413 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1414 1415 return (0); 1416 } 1417 1418 static int 1419 bge_init_rx_ring_std(struct bge_softc *sc) 1420 { 1421 int error, i; 1422 1423 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1424 sc->bge_std = 0; 1425 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1426 if ((error = bge_newbuf_std(sc, i)) != 0) 1427 return (error); 1428 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1429 } 1430 1431 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1432 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1433 1434 sc->bge_std = 0; 1435 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1436 1437 return (0); 1438 } 1439 1440 static void 1441 bge_free_rx_ring_std(struct bge_softc *sc) 1442 { 1443 int i; 1444 1445 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1446 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1447 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1448 sc->bge_cdata.bge_rx_std_dmamap[i], 1449 BUS_DMASYNC_POSTREAD); 1450 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1451 sc->bge_cdata.bge_rx_std_dmamap[i]); 1452 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1453 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1454 } 1455 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1456 sizeof(struct bge_rx_bd)); 1457 } 1458 } 1459 1460 static int 1461 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1462 { 1463 struct bge_rcb *rcb; 1464 int error, i; 1465 1466 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1467 sc->bge_jumbo = 0; 1468 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1469 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1470 return (error); 1471 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1472 } 1473 1474 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1475 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1476 1477 sc->bge_jumbo = 0; 1478 1479 /* Enable the jumbo receive producer ring. */ 1480 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1481 rcb->bge_maxlen_flags = 1482 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1483 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1484 1485 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1486 1487 return (0); 1488 } 1489 1490 static void 1491 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1492 { 1493 int i; 1494 1495 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1496 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1497 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1498 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1499 BUS_DMASYNC_POSTREAD); 1500 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1501 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1502 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1503 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1504 } 1505 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1506 sizeof(struct bge_extrx_bd)); 1507 } 1508 } 1509 1510 static void 1511 bge_free_tx_ring(struct bge_softc *sc) 1512 { 1513 int i; 1514 1515 if (sc->bge_ldata.bge_tx_ring == NULL) 1516 return; 1517 1518 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1519 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1520 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1521 sc->bge_cdata.bge_tx_dmamap[i], 1522 BUS_DMASYNC_POSTWRITE); 1523 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1524 sc->bge_cdata.bge_tx_dmamap[i]); 1525 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1526 sc->bge_cdata.bge_tx_chain[i] = NULL; 1527 } 1528 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1529 sizeof(struct bge_tx_bd)); 1530 } 1531 } 1532 1533 static int 1534 bge_init_tx_ring(struct bge_softc *sc) 1535 { 1536 sc->bge_txcnt = 0; 1537 sc->bge_tx_saved_considx = 0; 1538 1539 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1540 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1541 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1542 1543 /* Initialize transmit producer index for host-memory send ring. */ 1544 sc->bge_tx_prodidx = 0; 1545 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1546 1547 /* 5700 b2 errata */ 1548 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1549 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1550 1551 /* NIC-memory send ring not used; initialize to zero. */ 1552 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1553 /* 5700 b2 errata */ 1554 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1555 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1556 1557 return (0); 1558 } 1559 1560 static void 1561 bge_setpromisc(struct bge_softc *sc) 1562 { 1563 if_t ifp; 1564 1565 BGE_LOCK_ASSERT(sc); 1566 1567 ifp = sc->bge_ifp; 1568 1569 /* Enable or disable promiscuous mode as needed. */ 1570 if (if_getflags(ifp) & IFF_PROMISC) 1571 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1572 else 1573 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1574 } 1575 1576 static u_int 1577 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1578 { 1579 uint32_t *hashes = arg; 1580 int h; 1581 1582 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F; 1583 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1584 1585 return (1); 1586 } 1587 1588 static void 1589 bge_setmulti(struct bge_softc *sc) 1590 { 1591 if_t ifp; 1592 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1593 int i; 1594 1595 BGE_LOCK_ASSERT(sc); 1596 1597 ifp = sc->bge_ifp; 1598 1599 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 1600 for (i = 0; i < 4; i++) 1601 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1602 return; 1603 } 1604 1605 /* First, zot all the existing filters. */ 1606 for (i = 0; i < 4; i++) 1607 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1608 1609 if_foreach_llmaddr(ifp, bge_hash_maddr, hashes); 1610 1611 for (i = 0; i < 4; i++) 1612 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1613 } 1614 1615 static void 1616 bge_setvlan(struct bge_softc *sc) 1617 { 1618 if_t ifp; 1619 1620 BGE_LOCK_ASSERT(sc); 1621 1622 ifp = sc->bge_ifp; 1623 1624 /* Enable or disable VLAN tag stripping as needed. */ 1625 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1626 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1627 else 1628 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1629 } 1630 1631 static void 1632 bge_sig_pre_reset(struct bge_softc *sc, int type) 1633 { 1634 1635 /* 1636 * Some chips don't like this so only do this if ASF is enabled 1637 */ 1638 if (sc->bge_asf_mode) 1639 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1640 1641 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1642 switch (type) { 1643 case BGE_RESET_START: 1644 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1645 BGE_FW_DRV_STATE_START); 1646 break; 1647 case BGE_RESET_SHUTDOWN: 1648 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1649 BGE_FW_DRV_STATE_UNLOAD); 1650 break; 1651 case BGE_RESET_SUSPEND: 1652 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1653 BGE_FW_DRV_STATE_SUSPEND); 1654 break; 1655 } 1656 } 1657 1658 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1659 bge_ape_driver_state_change(sc, type); 1660 } 1661 1662 static void 1663 bge_sig_post_reset(struct bge_softc *sc, int type) 1664 { 1665 1666 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1667 switch (type) { 1668 case BGE_RESET_START: 1669 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1670 BGE_FW_DRV_STATE_START_DONE); 1671 /* START DONE */ 1672 break; 1673 case BGE_RESET_SHUTDOWN: 1674 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1675 BGE_FW_DRV_STATE_UNLOAD_DONE); 1676 break; 1677 } 1678 } 1679 if (type == BGE_RESET_SHUTDOWN) 1680 bge_ape_driver_state_change(sc, type); 1681 } 1682 1683 static void 1684 bge_sig_legacy(struct bge_softc *sc, int type) 1685 { 1686 1687 if (sc->bge_asf_mode) { 1688 switch (type) { 1689 case BGE_RESET_START: 1690 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1691 BGE_FW_DRV_STATE_START); 1692 break; 1693 case BGE_RESET_SHUTDOWN: 1694 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1695 BGE_FW_DRV_STATE_UNLOAD); 1696 break; 1697 } 1698 } 1699 } 1700 1701 static void 1702 bge_stop_fw(struct bge_softc *sc) 1703 { 1704 int i; 1705 1706 if (sc->bge_asf_mode) { 1707 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1708 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1709 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1710 1711 for (i = 0; i < 100; i++ ) { 1712 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1713 BGE_RX_CPU_DRV_EVENT)) 1714 break; 1715 DELAY(10); 1716 } 1717 } 1718 } 1719 1720 static uint32_t 1721 bge_dma_swap_options(struct bge_softc *sc) 1722 { 1723 uint32_t dma_options; 1724 1725 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1726 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1727 #if BYTE_ORDER == BIG_ENDIAN 1728 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1729 #endif 1730 return (dma_options); 1731 } 1732 1733 /* 1734 * Do endian, PCI and DMA initialization. 1735 */ 1736 static int 1737 bge_chipinit(struct bge_softc *sc) 1738 { 1739 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1740 uint16_t val; 1741 int i; 1742 1743 /* Set endianness before we access any non-PCI registers. */ 1744 misc_ctl = BGE_INIT; 1745 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1746 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1747 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1748 1749 /* 1750 * Clear the MAC statistics block in the NIC's 1751 * internal memory. 1752 */ 1753 for (i = BGE_STATS_BLOCK; 1754 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1755 BGE_MEMWIN_WRITE(sc, i, 0); 1756 1757 for (i = BGE_STATUS_BLOCK; 1758 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1759 BGE_MEMWIN_WRITE(sc, i, 0); 1760 1761 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1762 /* 1763 * Fix data corruption caused by non-qword write with WB. 1764 * Fix master abort in PCI mode. 1765 * Fix PCI latency timer. 1766 */ 1767 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1768 val |= (1 << 10) | (1 << 12) | (1 << 13); 1769 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1770 } 1771 1772 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1773 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1774 /* 1775 * For the 57766 and non Ax versions of 57765, bootcode 1776 * needs to setup the PCIE Fast Training Sequence (FTS) 1777 * value to prevent transmit hangs. 1778 */ 1779 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1780 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1781 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1782 BGE_CPMU_PADRNG_CTL_RDIV2); 1783 } 1784 } 1785 1786 /* 1787 * Set up the PCI DMA control register. 1788 */ 1789 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1790 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1791 if (sc->bge_flags & BGE_FLAG_PCIE) { 1792 if (sc->bge_mps >= 256) 1793 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1794 else 1795 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1796 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1797 if (BGE_IS_5714_FAMILY(sc)) { 1798 /* 256 bytes for read and write. */ 1799 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1800 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1801 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1802 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1803 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1804 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1805 /* 1806 * In the BCM5703, the DMA read watermark should 1807 * be set to less than or equal to the maximum 1808 * memory read byte count of the PCI-X command 1809 * register. 1810 */ 1811 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1812 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1813 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1814 /* 1536 bytes for read, 384 bytes for write. */ 1815 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1816 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1817 } else { 1818 /* 384 bytes for read and write. */ 1819 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1820 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1821 0x0F; 1822 } 1823 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1824 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1825 uint32_t tmp; 1826 1827 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1828 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1829 if (tmp == 6 || tmp == 7) 1830 dma_rw_ctl |= 1831 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1832 1833 /* Set PCI-X DMA write workaround. */ 1834 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1835 } 1836 } else { 1837 /* Conventional PCI bus: 256 bytes for read and write. */ 1838 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1839 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1840 1841 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1842 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1843 dma_rw_ctl |= 0x0F; 1844 } 1845 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1846 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1847 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1848 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1849 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1850 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1851 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1852 if (BGE_IS_5717_PLUS(sc)) { 1853 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1854 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1855 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1856 /* 1857 * Enable HW workaround for controllers that misinterpret 1858 * a status tag update and leave interrupts permanently 1859 * disabled. 1860 */ 1861 if (!BGE_IS_57765_PLUS(sc) && 1862 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1863 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1864 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1865 } 1866 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1867 1868 /* 1869 * Set up general mode register. 1870 */ 1871 mode_ctl = bge_dma_swap_options(sc); 1872 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1873 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1874 /* Retain Host-2-BMC settings written by APE firmware. */ 1875 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1876 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1877 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1878 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1879 } 1880 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1881 BGE_MODECTL_TX_NO_PHDR_CSUM; 1882 1883 /* 1884 * BCM5701 B5 have a bug causing data corruption when using 1885 * 64-bit DMA reads, which can be terminated early and then 1886 * completed later as 32-bit accesses, in combination with 1887 * certain bridges. 1888 */ 1889 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1890 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1891 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1892 1893 /* 1894 * Tell the firmware the driver is running 1895 */ 1896 if (sc->bge_asf_mode & ASF_STACKUP) 1897 mode_ctl |= BGE_MODECTL_STACKUP; 1898 1899 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1900 1901 /* 1902 * Disable memory write invalidate. Apparently it is not supported 1903 * properly by these devices. 1904 */ 1905 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1906 1907 /* Set the timer prescaler (always 66 MHz). */ 1908 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1909 1910 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1911 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1912 DELAY(40); /* XXX */ 1913 1914 /* Put PHY into ready state */ 1915 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1916 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1917 DELAY(40); 1918 } 1919 1920 return (0); 1921 } 1922 1923 static int 1924 bge_blockinit(struct bge_softc *sc) 1925 { 1926 struct bge_rcb *rcb; 1927 bus_size_t vrcb; 1928 bge_hostaddr taddr; 1929 uint32_t dmactl, rdmareg, val; 1930 int i, limit; 1931 1932 /* 1933 * Initialize the memory window pointer register so that 1934 * we can access the first 32K of internal NIC RAM. This will 1935 * allow us to set up the TX send ring RCBs and the RX return 1936 * ring RCBs, plus other things which live in NIC memory. 1937 */ 1938 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1939 1940 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1941 1942 if (!(BGE_IS_5705_PLUS(sc))) { 1943 /* Configure mbuf memory pool */ 1944 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1945 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1946 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1947 else 1948 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1949 1950 /* Configure DMA resource pool */ 1951 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1952 BGE_DMA_DESCRIPTORS); 1953 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1954 } 1955 1956 /* Configure mbuf pool watermarks */ 1957 if (BGE_IS_5717_PLUS(sc)) { 1958 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1959 if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1962 } else { 1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1965 } 1966 } else if (!BGE_IS_5705_PLUS(sc)) { 1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1970 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1974 } else { 1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1977 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1978 } 1979 1980 /* Configure DMA resource watermarks */ 1981 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1982 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1983 1984 /* Enable buffer manager */ 1985 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1986 /* 1987 * Change the arbitration algorithm of TXMBUF read request to 1988 * round-robin instead of priority based for BCM5719. When 1989 * TXFIFO is almost empty, RDMA will hold its request until 1990 * TXFIFO is not almost empty. 1991 */ 1992 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 1993 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1994 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1995 1996 /* Poll for buffer manager start indication */ 1997 for (i = 0; i < BGE_TIMEOUT; i++) { 1998 DELAY(10); 1999 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2000 break; 2001 } 2002 2003 if (i == BGE_TIMEOUT) { 2004 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2005 return (ENXIO); 2006 } 2007 2008 /* Enable flow-through queues */ 2009 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2010 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2011 2012 /* Wait until queue initialization is complete */ 2013 for (i = 0; i < BGE_TIMEOUT; i++) { 2014 DELAY(10); 2015 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2016 break; 2017 } 2018 2019 if (i == BGE_TIMEOUT) { 2020 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2021 return (ENXIO); 2022 } 2023 2024 /* 2025 * Summary of rings supported by the controller: 2026 * 2027 * Standard Receive Producer Ring 2028 * - This ring is used to feed receive buffers for "standard" 2029 * sized frames (typically 1536 bytes) to the controller. 2030 * 2031 * Jumbo Receive Producer Ring 2032 * - This ring is used to feed receive buffers for jumbo sized 2033 * frames (i.e. anything bigger than the "standard" frames) 2034 * to the controller. 2035 * 2036 * Mini Receive Producer Ring 2037 * - This ring is used to feed receive buffers for "mini" 2038 * sized frames to the controller. 2039 * - This feature required external memory for the controller 2040 * but was never used in a production system. Should always 2041 * be disabled. 2042 * 2043 * Receive Return Ring 2044 * - After the controller has placed an incoming frame into a 2045 * receive buffer that buffer is moved into a receive return 2046 * ring. The driver is then responsible to passing the 2047 * buffer up to the stack. Many versions of the controller 2048 * support multiple RR rings. 2049 * 2050 * Send Ring 2051 * - This ring is used for outgoing frames. Many versions of 2052 * the controller support multiple send rings. 2053 */ 2054 2055 /* Initialize the standard receive producer ring control block. */ 2056 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2057 rcb->bge_hostaddr.bge_addr_lo = 2058 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2059 rcb->bge_hostaddr.bge_addr_hi = 2060 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2061 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2062 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2063 if (BGE_IS_5717_PLUS(sc)) { 2064 /* 2065 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2066 * Bits 15-2 : Maximum RX frame size 2067 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2068 * Bit 0 : Reserved 2069 */ 2070 rcb->bge_maxlen_flags = 2071 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2072 } else if (BGE_IS_5705_PLUS(sc)) { 2073 /* 2074 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2075 * Bits 15-2 : Reserved (should be 0) 2076 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2077 * Bit 0 : Reserved 2078 */ 2079 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2080 } else { 2081 /* 2082 * Ring size is always XXX entries 2083 * Bits 31-16: Maximum RX frame size 2084 * Bits 15-2 : Reserved (should be 0) 2085 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2086 * Bit 0 : Reserved 2087 */ 2088 rcb->bge_maxlen_flags = 2089 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2090 } 2091 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2092 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2093 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2094 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2095 else 2096 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2097 /* Write the standard receive producer ring control block. */ 2098 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2099 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2100 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2101 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2102 2103 /* Reset the standard receive producer ring producer index. */ 2104 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2105 2106 /* 2107 * Initialize the jumbo RX producer ring control 2108 * block. We set the 'ring disabled' bit in the 2109 * flags field until we're actually ready to start 2110 * using this ring (i.e. once we set the MTU 2111 * high enough to require it). 2112 */ 2113 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2114 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2115 /* Get the jumbo receive producer ring RCB parameters. */ 2116 rcb->bge_hostaddr.bge_addr_lo = 2117 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2118 rcb->bge_hostaddr.bge_addr_hi = 2119 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2120 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2121 sc->bge_cdata.bge_rx_jumbo_ring_map, 2122 BUS_DMASYNC_PREREAD); 2123 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2124 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2125 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2126 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2127 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2128 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2129 else 2130 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2131 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2132 rcb->bge_hostaddr.bge_addr_hi); 2133 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2134 rcb->bge_hostaddr.bge_addr_lo); 2135 /* Program the jumbo receive producer ring RCB parameters. */ 2136 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2137 rcb->bge_maxlen_flags); 2138 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2139 /* Reset the jumbo receive producer ring producer index. */ 2140 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2141 } 2142 2143 /* Disable the mini receive producer ring RCB. */ 2144 if (BGE_IS_5700_FAMILY(sc)) { 2145 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2146 rcb->bge_maxlen_flags = 2147 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2148 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2149 rcb->bge_maxlen_flags); 2150 /* Reset the mini receive producer ring producer index. */ 2151 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2152 } 2153 2154 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2155 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2156 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2157 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2158 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2159 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2160 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2161 } 2162 /* 2163 * The BD ring replenish thresholds control how often the 2164 * hardware fetches new BD's from the producer rings in host 2165 * memory. Setting the value too low on a busy system can 2166 * starve the hardware and recue the throughpout. 2167 * 2168 * Set the BD ring replentish thresholds. The recommended 2169 * values are 1/8th the number of descriptors allocated to 2170 * each ring. 2171 * XXX The 5754 requires a lower threshold, so it might be a 2172 * requirement of all 575x family chips. The Linux driver sets 2173 * the lower threshold for all 5705 family chips as well, but there 2174 * are reports that it might not need to be so strict. 2175 * 2176 * XXX Linux does some extra fiddling here for the 5906 parts as 2177 * well. 2178 */ 2179 if (BGE_IS_5705_PLUS(sc)) 2180 val = 8; 2181 else 2182 val = BGE_STD_RX_RING_CNT / 8; 2183 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2184 if (BGE_IS_JUMBO_CAPABLE(sc)) 2185 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2186 BGE_JUMBO_RX_RING_CNT/8); 2187 if (BGE_IS_5717_PLUS(sc)) { 2188 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2189 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2190 } 2191 2192 /* 2193 * Disable all send rings by setting the 'ring disabled' bit 2194 * in the flags field of all the TX send ring control blocks, 2195 * located in NIC memory. 2196 */ 2197 if (!BGE_IS_5705_PLUS(sc)) 2198 /* 5700 to 5704 had 16 send rings. */ 2199 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2200 else if (BGE_IS_57765_PLUS(sc) || 2201 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2202 limit = 2; 2203 else if (BGE_IS_5717_PLUS(sc)) 2204 limit = 4; 2205 else 2206 limit = 1; 2207 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2208 for (i = 0; i < limit; i++) { 2209 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2210 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2211 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2212 vrcb += sizeof(struct bge_rcb); 2213 } 2214 2215 /* Configure send ring RCB 0 (we use only the first ring) */ 2216 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2217 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2218 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2219 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2220 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2221 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2222 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2223 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2224 else 2225 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2226 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2227 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2228 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2229 2230 /* 2231 * Disable all receive return rings by setting the 2232 * 'ring diabled' bit in the flags field of all the receive 2233 * return ring control blocks, located in NIC memory. 2234 */ 2235 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2236 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2237 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2238 /* Should be 17, use 16 until we get an SRAM map. */ 2239 limit = 16; 2240 } else if (!BGE_IS_5705_PLUS(sc)) 2241 limit = BGE_RX_RINGS_MAX; 2242 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2243 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2244 BGE_IS_57765_PLUS(sc)) 2245 limit = 4; 2246 else 2247 limit = 1; 2248 /* Disable all receive return rings. */ 2249 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2250 for (i = 0; i < limit; i++) { 2251 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2252 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2253 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2254 BGE_RCB_FLAG_RING_DISABLED); 2255 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2256 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2257 (i * (sizeof(uint64_t))), 0); 2258 vrcb += sizeof(struct bge_rcb); 2259 } 2260 2261 /* 2262 * Set up receive return ring 0. Note that the NIC address 2263 * for RX return rings is 0x0. The return rings live entirely 2264 * within the host, so the nicaddr field in the RCB isn't used. 2265 */ 2266 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2267 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2268 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2269 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2270 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2271 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2272 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2273 2274 /* Set random backoff seed for TX */ 2275 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2276 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2277 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2278 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2279 BGE_TX_BACKOFF_SEED_MASK); 2280 2281 /* Set inter-packet gap */ 2282 val = 0x2620; 2283 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2284 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2285 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2286 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2287 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2288 2289 /* 2290 * Specify which ring to use for packets that don't match 2291 * any RX rules. 2292 */ 2293 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2294 2295 /* 2296 * Configure number of RX lists. One interrupt distribution 2297 * list, sixteen active lists, one bad frames class. 2298 */ 2299 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2300 2301 /* Inialize RX list placement stats mask. */ 2302 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2303 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2304 2305 /* Disable host coalescing until we get it set up */ 2306 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2307 2308 /* Poll to make sure it's shut down. */ 2309 for (i = 0; i < BGE_TIMEOUT; i++) { 2310 DELAY(10); 2311 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2312 break; 2313 } 2314 2315 if (i == BGE_TIMEOUT) { 2316 device_printf(sc->bge_dev, 2317 "host coalescing engine failed to idle\n"); 2318 return (ENXIO); 2319 } 2320 2321 /* Set up host coalescing defaults */ 2322 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2323 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2324 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2325 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2326 if (!(BGE_IS_5705_PLUS(sc))) { 2327 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2328 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2329 } 2330 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2331 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2332 2333 /* Set up address of statistics block */ 2334 if (!(BGE_IS_5705_PLUS(sc))) { 2335 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2336 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2337 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2338 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2339 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2340 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2341 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2342 } 2343 2344 /* Set up address of status block */ 2345 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2346 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2347 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2348 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2349 2350 /* Set up status block size. */ 2351 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2352 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2353 val = BGE_STATBLKSZ_FULL; 2354 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2355 } else { 2356 val = BGE_STATBLKSZ_32BYTE; 2357 bzero(sc->bge_ldata.bge_status_block, 32); 2358 } 2359 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2360 sc->bge_cdata.bge_status_map, 2361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2362 2363 /* Turn on host coalescing state machine */ 2364 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2365 2366 /* Turn on RX BD completion state machine and enable attentions */ 2367 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2368 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2369 2370 /* Turn on RX list placement state machine */ 2371 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2372 2373 /* Turn on RX list selector state machine. */ 2374 if (!(BGE_IS_5705_PLUS(sc))) 2375 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2376 2377 /* Turn on DMA, clear stats. */ 2378 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2379 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2380 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2381 BGE_MACMODE_FRMHDR_DMA_ENB; 2382 2383 if (sc->bge_flags & BGE_FLAG_TBI) 2384 val |= BGE_PORTMODE_TBI; 2385 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2386 val |= BGE_PORTMODE_GMII; 2387 else 2388 val |= BGE_PORTMODE_MII; 2389 2390 /* Allow APE to send/receive frames. */ 2391 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2392 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2393 2394 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2395 DELAY(40); 2396 2397 /* Set misc. local control, enable interrupts on attentions */ 2398 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2399 2400 #ifdef notdef 2401 /* Assert GPIO pins for PHY reset */ 2402 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2403 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2404 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2405 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2406 #endif 2407 2408 /* Turn on DMA completion state machine */ 2409 if (!(BGE_IS_5705_PLUS(sc))) 2410 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2411 2412 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2413 2414 /* Enable host coalescing bug fix. */ 2415 if (BGE_IS_5755_PLUS(sc)) 2416 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2417 2418 /* Request larger DMA burst size to get better performance. */ 2419 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2420 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2421 2422 /* Turn on write DMA state machine */ 2423 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2424 DELAY(40); 2425 2426 /* Turn on read DMA state machine */ 2427 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2428 2429 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2430 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2431 2432 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2433 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2434 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2435 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2436 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2437 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2438 if (sc->bge_flags & BGE_FLAG_PCIE) 2439 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2440 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2441 val |= BGE_RDMAMODE_TSO4_ENABLE; 2442 if (sc->bge_flags & BGE_FLAG_TSO3 || 2443 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2444 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2445 val |= BGE_RDMAMODE_TSO6_ENABLE; 2446 } 2447 2448 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2449 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2450 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2451 BGE_RDMAMODE_H2BNC_VLAN_DET; 2452 /* 2453 * Allow multiple outstanding read requests from 2454 * non-LSO read DMA engine. 2455 */ 2456 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2457 } 2458 2459 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2460 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2461 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2462 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2463 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2465 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2466 else 2467 rdmareg = BGE_RDMA_RSRVCTRL; 2468 dmactl = CSR_READ_4(sc, rdmareg); 2469 /* 2470 * Adjust tx margin to prevent TX data corruption and 2471 * fix internal FIFO overflow. 2472 */ 2473 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2474 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2475 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2477 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2478 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2479 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2480 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2481 } 2482 /* 2483 * Enable fix for read DMA FIFO overruns. 2484 * The fix is to limit the number of RX BDs 2485 * the hardware would fetch at a fime. 2486 */ 2487 CSR_WRITE_4(sc, rdmareg, dmactl | 2488 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2489 } 2490 2491 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2492 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2493 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2494 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2495 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2496 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2497 /* 2498 * Allow 4KB burst length reads for non-LSO frames. 2499 * Enable 512B burst length reads for buffer descriptors. 2500 */ 2501 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2502 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2503 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2504 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2505 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2506 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2507 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2508 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2509 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2510 } 2511 2512 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2513 DELAY(40); 2514 2515 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2516 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2517 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2518 if ((val & 0xFFFF) > BGE_FRAMELEN) 2519 break; 2520 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2521 break; 2522 } 2523 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2524 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2525 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2526 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2527 else 2528 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2529 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2530 } 2531 } 2532 2533 /* Turn on RX data completion state machine */ 2534 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2535 2536 /* Turn on RX BD initiator state machine */ 2537 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2538 2539 /* Turn on RX data and RX BD initiator state machine */ 2540 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2541 2542 /* Turn on Mbuf cluster free state machine */ 2543 if (!(BGE_IS_5705_PLUS(sc))) 2544 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2545 2546 /* Turn on send BD completion state machine */ 2547 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2548 2549 /* Turn on send data completion state machine */ 2550 val = BGE_SDCMODE_ENABLE; 2551 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2552 val |= BGE_SDCMODE_CDELAY; 2553 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2554 2555 /* Turn on send data initiator state machine */ 2556 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2557 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2558 BGE_SDIMODE_HW_LSO_PRE_DMA); 2559 else 2560 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2561 2562 /* Turn on send BD initiator state machine */ 2563 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2564 2565 /* Turn on send BD selector state machine */ 2566 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2567 2568 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2569 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2570 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2571 2572 /* ack/clear link change events */ 2573 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2574 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2575 BGE_MACSTAT_LINK_CHANGED); 2576 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2577 2578 /* 2579 * Enable attention when the link has changed state for 2580 * devices that use auto polling. 2581 */ 2582 if (sc->bge_flags & BGE_FLAG_TBI) { 2583 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2584 } else { 2585 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2586 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2587 DELAY(80); 2588 } 2589 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2590 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2591 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2592 BGE_EVTENB_MI_INTERRUPT); 2593 } 2594 2595 /* 2596 * Clear any pending link state attention. 2597 * Otherwise some link state change events may be lost until attention 2598 * is cleared by bge_intr() -> bge_link_upd() sequence. 2599 * It's not necessary on newer BCM chips - perhaps enabling link 2600 * state change attentions implies clearing pending attention. 2601 */ 2602 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2603 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2604 BGE_MACSTAT_LINK_CHANGED); 2605 2606 /* Enable link state change attentions. */ 2607 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2608 2609 return (0); 2610 } 2611 2612 static const struct bge_revision * 2613 bge_lookup_rev(uint32_t chipid) 2614 { 2615 const struct bge_revision *br; 2616 2617 for (br = bge_revisions; br->br_name != NULL; br++) { 2618 if (br->br_chipid == chipid) 2619 return (br); 2620 } 2621 2622 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2623 if (br->br_chipid == BGE_ASICREV(chipid)) 2624 return (br); 2625 } 2626 2627 return (NULL); 2628 } 2629 2630 static const struct bge_vendor * 2631 bge_lookup_vendor(uint16_t vid) 2632 { 2633 const struct bge_vendor *v; 2634 2635 for (v = bge_vendors; v->v_name != NULL; v++) 2636 if (v->v_id == vid) 2637 return (v); 2638 2639 return (NULL); 2640 } 2641 2642 static uint32_t 2643 bge_chipid(device_t dev) 2644 { 2645 uint32_t id; 2646 2647 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2648 BGE_PCIMISCCTL_ASICREV_SHIFT; 2649 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2650 /* 2651 * Find the ASCI revision. Different chips use different 2652 * registers. 2653 */ 2654 switch (pci_get_device(dev)) { 2655 case BCOM_DEVICEID_BCM5717C: 2656 /* 5717 C0 seems to belong to 5720 line. */ 2657 id = BGE_CHIPID_BCM5720_A0; 2658 break; 2659 case BCOM_DEVICEID_BCM5717: 2660 case BCOM_DEVICEID_BCM5718: 2661 case BCOM_DEVICEID_BCM5719: 2662 case BCOM_DEVICEID_BCM5720: 2663 case BCOM_DEVICEID_BCM5725: 2664 case BCOM_DEVICEID_BCM5727: 2665 case BCOM_DEVICEID_BCM5762: 2666 case BCOM_DEVICEID_BCM57764: 2667 case BCOM_DEVICEID_BCM57767: 2668 case BCOM_DEVICEID_BCM57787: 2669 id = pci_read_config(dev, 2670 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2671 break; 2672 case BCOM_DEVICEID_BCM57761: 2673 case BCOM_DEVICEID_BCM57762: 2674 case BCOM_DEVICEID_BCM57765: 2675 case BCOM_DEVICEID_BCM57766: 2676 case BCOM_DEVICEID_BCM57781: 2677 case BCOM_DEVICEID_BCM57782: 2678 case BCOM_DEVICEID_BCM57785: 2679 case BCOM_DEVICEID_BCM57786: 2680 case BCOM_DEVICEID_BCM57791: 2681 case BCOM_DEVICEID_BCM57795: 2682 id = pci_read_config(dev, 2683 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2684 break; 2685 default: 2686 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2687 } 2688 } 2689 return (id); 2690 } 2691 2692 /* 2693 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2694 * against our list and return its name if we find a match. 2695 * 2696 * Note that since the Broadcom controller contains VPD support, we 2697 * try to get the device name string from the controller itself instead 2698 * of the compiled-in string. It guarantees we'll always announce the 2699 * right product name. We fall back to the compiled-in string when 2700 * VPD is unavailable or corrupt. 2701 */ 2702 static int 2703 bge_probe(device_t dev) 2704 { 2705 char buf[96]; 2706 char model[64]; 2707 const struct bge_revision *br; 2708 const char *pname; 2709 struct bge_softc *sc; 2710 const struct bge_type *t = bge_devs; 2711 const struct bge_vendor *v; 2712 uint32_t id; 2713 uint16_t did, vid; 2714 2715 sc = device_get_softc(dev); 2716 sc->bge_dev = dev; 2717 vid = pci_get_vendor(dev); 2718 did = pci_get_device(dev); 2719 while(t->bge_vid != 0) { 2720 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2721 id = bge_chipid(dev); 2722 br = bge_lookup_rev(id); 2723 if (bge_has_eaddr(sc) && 2724 pci_get_vpd_ident(dev, &pname) == 0) 2725 snprintf(model, sizeof(model), "%s", pname); 2726 else { 2727 v = bge_lookup_vendor(vid); 2728 snprintf(model, sizeof(model), "%s %s", 2729 v != NULL ? v->v_name : "Unknown", 2730 br != NULL ? br->br_name : 2731 "NetXtreme/NetLink Ethernet Controller"); 2732 } 2733 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2734 model, br != NULL ? "" : "unknown ", id); 2735 device_set_desc_copy(dev, buf); 2736 return (BUS_PROBE_DEFAULT); 2737 } 2738 t++; 2739 } 2740 2741 return (ENXIO); 2742 } 2743 2744 static void 2745 bge_dma_free(struct bge_softc *sc) 2746 { 2747 int i; 2748 2749 /* Destroy DMA maps for RX buffers. */ 2750 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2751 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2752 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2753 sc->bge_cdata.bge_rx_std_dmamap[i]); 2754 } 2755 if (sc->bge_cdata.bge_rx_std_sparemap) 2756 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2757 sc->bge_cdata.bge_rx_std_sparemap); 2758 2759 /* Destroy DMA maps for jumbo RX buffers. */ 2760 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2761 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2762 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2763 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2764 } 2765 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2766 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2767 sc->bge_cdata.bge_rx_jumbo_sparemap); 2768 2769 /* Destroy DMA maps for TX buffers. */ 2770 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2771 if (sc->bge_cdata.bge_tx_dmamap[i]) 2772 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2773 sc->bge_cdata.bge_tx_dmamap[i]); 2774 } 2775 2776 if (sc->bge_cdata.bge_rx_mtag) 2777 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2778 if (sc->bge_cdata.bge_mtag_jumbo) 2779 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2780 if (sc->bge_cdata.bge_tx_mtag) 2781 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2782 2783 /* Destroy standard RX ring. */ 2784 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2785 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2786 sc->bge_cdata.bge_rx_std_ring_map); 2787 if (sc->bge_ldata.bge_rx_std_ring) 2788 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2789 sc->bge_ldata.bge_rx_std_ring, 2790 sc->bge_cdata.bge_rx_std_ring_map); 2791 2792 if (sc->bge_cdata.bge_rx_std_ring_tag) 2793 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2794 2795 /* Destroy jumbo RX ring. */ 2796 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2797 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2798 sc->bge_cdata.bge_rx_jumbo_ring_map); 2799 2800 if (sc->bge_ldata.bge_rx_jumbo_ring) 2801 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2802 sc->bge_ldata.bge_rx_jumbo_ring, 2803 sc->bge_cdata.bge_rx_jumbo_ring_map); 2804 2805 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2806 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2807 2808 /* Destroy RX return ring. */ 2809 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2810 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2811 sc->bge_cdata.bge_rx_return_ring_map); 2812 2813 if (sc->bge_ldata.bge_rx_return_ring) 2814 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2815 sc->bge_ldata.bge_rx_return_ring, 2816 sc->bge_cdata.bge_rx_return_ring_map); 2817 2818 if (sc->bge_cdata.bge_rx_return_ring_tag) 2819 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2820 2821 /* Destroy TX ring. */ 2822 if (sc->bge_ldata.bge_tx_ring_paddr) 2823 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2824 sc->bge_cdata.bge_tx_ring_map); 2825 2826 if (sc->bge_ldata.bge_tx_ring) 2827 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2828 sc->bge_ldata.bge_tx_ring, 2829 sc->bge_cdata.bge_tx_ring_map); 2830 2831 if (sc->bge_cdata.bge_tx_ring_tag) 2832 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2833 2834 /* Destroy status block. */ 2835 if (sc->bge_ldata.bge_status_block_paddr) 2836 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2837 sc->bge_cdata.bge_status_map); 2838 2839 if (sc->bge_ldata.bge_status_block) 2840 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2841 sc->bge_ldata.bge_status_block, 2842 sc->bge_cdata.bge_status_map); 2843 2844 if (sc->bge_cdata.bge_status_tag) 2845 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2846 2847 /* Destroy statistics block. */ 2848 if (sc->bge_ldata.bge_stats_paddr) 2849 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2850 sc->bge_cdata.bge_stats_map); 2851 2852 if (sc->bge_ldata.bge_stats) 2853 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2854 sc->bge_ldata.bge_stats, 2855 sc->bge_cdata.bge_stats_map); 2856 2857 if (sc->bge_cdata.bge_stats_tag) 2858 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2859 2860 if (sc->bge_cdata.bge_buffer_tag) 2861 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2862 2863 /* Destroy the parent tag. */ 2864 if (sc->bge_cdata.bge_parent_tag) 2865 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2866 } 2867 2868 static int 2869 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2870 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2871 bus_addr_t *paddr, const char *msg) 2872 { 2873 struct bge_dmamap_arg ctx; 2874 bus_addr_t lowaddr; 2875 bus_size_t ring_end; 2876 int error; 2877 2878 lowaddr = BUS_SPACE_MAXADDR; 2879 again: 2880 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2881 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2882 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2883 if (error != 0) { 2884 device_printf(sc->bge_dev, 2885 "could not create %s dma tag\n", msg); 2886 return (ENOMEM); 2887 } 2888 /* Allocate DMA'able memory for ring. */ 2889 error = bus_dmamem_alloc(*tag, (void **)ring, 2890 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2891 if (error != 0) { 2892 device_printf(sc->bge_dev, 2893 "could not allocate DMA'able memory for %s\n", msg); 2894 return (ENOMEM); 2895 } 2896 /* Load the address of the ring. */ 2897 ctx.bge_busaddr = 0; 2898 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2899 &ctx, BUS_DMA_NOWAIT); 2900 if (error != 0) { 2901 device_printf(sc->bge_dev, 2902 "could not load DMA'able memory for %s\n", msg); 2903 return (ENOMEM); 2904 } 2905 *paddr = ctx.bge_busaddr; 2906 ring_end = *paddr + maxsize; 2907 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2908 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2909 /* 2910 * 4GB boundary crossed. Limit maximum allowable DMA 2911 * address space to 32bit and try again. 2912 */ 2913 bus_dmamap_unload(*tag, *map); 2914 bus_dmamem_free(*tag, *ring, *map); 2915 bus_dma_tag_destroy(*tag); 2916 if (bootverbose) 2917 device_printf(sc->bge_dev, "4GB boundary crossed, " 2918 "limit DMA address space to 32bit for %s\n", msg); 2919 *ring = NULL; 2920 *tag = NULL; 2921 *map = NULL; 2922 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2923 goto again; 2924 } 2925 return (0); 2926 } 2927 2928 static int 2929 bge_dma_alloc(struct bge_softc *sc) 2930 { 2931 bus_addr_t lowaddr; 2932 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2933 int i, error; 2934 2935 lowaddr = BUS_SPACE_MAXADDR; 2936 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2937 lowaddr = BGE_DMA_MAXADDR; 2938 /* 2939 * Allocate the parent bus DMA tag appropriate for PCI. 2940 */ 2941 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2942 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2943 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2944 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2945 if (error != 0) { 2946 device_printf(sc->bge_dev, 2947 "could not allocate parent dma tag\n"); 2948 return (ENOMEM); 2949 } 2950 2951 /* Create tag for standard RX ring. */ 2952 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2953 &sc->bge_cdata.bge_rx_std_ring_tag, 2954 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2955 &sc->bge_cdata.bge_rx_std_ring_map, 2956 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2957 if (error) 2958 return (error); 2959 2960 /* Create tag for RX return ring. */ 2961 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2962 &sc->bge_cdata.bge_rx_return_ring_tag, 2963 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2964 &sc->bge_cdata.bge_rx_return_ring_map, 2965 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2966 if (error) 2967 return (error); 2968 2969 /* Create tag for TX ring. */ 2970 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2971 &sc->bge_cdata.bge_tx_ring_tag, 2972 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2973 &sc->bge_cdata.bge_tx_ring_map, 2974 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2975 if (error) 2976 return (error); 2977 2978 /* 2979 * Create tag for status block. 2980 * Because we only use single Tx/Rx/Rx return ring, use 2981 * minimum status block size except BCM5700 AX/BX which 2982 * seems to want to see full status block size regardless 2983 * of configured number of ring. 2984 */ 2985 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2986 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2987 sbsz = BGE_STATUS_BLK_SZ; 2988 else 2989 sbsz = 32; 2990 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2991 &sc->bge_cdata.bge_status_tag, 2992 (uint8_t **)&sc->bge_ldata.bge_status_block, 2993 &sc->bge_cdata.bge_status_map, 2994 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2995 if (error) 2996 return (error); 2997 2998 /* Create tag for statistics block. */ 2999 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3000 &sc->bge_cdata.bge_stats_tag, 3001 (uint8_t **)&sc->bge_ldata.bge_stats, 3002 &sc->bge_cdata.bge_stats_map, 3003 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3004 if (error) 3005 return (error); 3006 3007 /* Create tag for jumbo RX ring. */ 3008 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3009 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3010 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3011 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3012 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3013 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3014 if (error) 3015 return (error); 3016 } 3017 3018 /* Create parent tag for buffers. */ 3019 boundary = 0; 3020 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3021 boundary = BGE_DMA_BNDRY; 3022 /* 3023 * XXX 3024 * watchdog timeout issue was observed on BCM5704 which 3025 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3026 * Both limiting DMA address space to 32bits and flushing 3027 * mailbox write seem to address the issue. 3028 */ 3029 if (sc->bge_pcixcap != 0) 3030 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3031 } 3032 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 3033 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 3034 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3035 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 3036 if (error != 0) { 3037 device_printf(sc->bge_dev, 3038 "could not allocate buffer dma tag\n"); 3039 return (ENOMEM); 3040 } 3041 /* Create tag for Tx mbufs. */ 3042 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3043 txsegsz = BGE_TSOSEG_SZ; 3044 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3045 } else { 3046 txsegsz = MCLBYTES; 3047 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3048 } 3049 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3050 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3051 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3052 &sc->bge_cdata.bge_tx_mtag); 3053 3054 if (error) { 3055 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3056 return (ENOMEM); 3057 } 3058 3059 /* Create tag for Rx mbufs. */ 3060 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3061 rxmaxsegsz = MJUM9BYTES; 3062 else 3063 rxmaxsegsz = MCLBYTES; 3064 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3065 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3066 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3067 3068 if (error) { 3069 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3070 return (ENOMEM); 3071 } 3072 3073 /* Create DMA maps for RX buffers. */ 3074 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3075 &sc->bge_cdata.bge_rx_std_sparemap); 3076 if (error) { 3077 device_printf(sc->bge_dev, 3078 "can't create spare DMA map for RX\n"); 3079 return (ENOMEM); 3080 } 3081 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3082 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3083 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3084 if (error) { 3085 device_printf(sc->bge_dev, 3086 "can't create DMA map for RX\n"); 3087 return (ENOMEM); 3088 } 3089 } 3090 3091 /* Create DMA maps for TX buffers. */ 3092 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3093 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3094 &sc->bge_cdata.bge_tx_dmamap[i]); 3095 if (error) { 3096 device_printf(sc->bge_dev, 3097 "can't create DMA map for TX\n"); 3098 return (ENOMEM); 3099 } 3100 } 3101 3102 /* Create tags for jumbo RX buffers. */ 3103 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3104 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3105 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3106 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3107 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3108 if (error) { 3109 device_printf(sc->bge_dev, 3110 "could not allocate jumbo dma tag\n"); 3111 return (ENOMEM); 3112 } 3113 /* Create DMA maps for jumbo RX buffers. */ 3114 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3115 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3116 if (error) { 3117 device_printf(sc->bge_dev, 3118 "can't create spare DMA map for jumbo RX\n"); 3119 return (ENOMEM); 3120 } 3121 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3122 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3123 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3124 if (error) { 3125 device_printf(sc->bge_dev, 3126 "can't create DMA map for jumbo RX\n"); 3127 return (ENOMEM); 3128 } 3129 } 3130 } 3131 3132 return (0); 3133 } 3134 3135 /* 3136 * Return true if this device has more than one port. 3137 */ 3138 static int 3139 bge_has_multiple_ports(struct bge_softc *sc) 3140 { 3141 device_t dev = sc->bge_dev; 3142 u_int b, d, f, fscan, s; 3143 3144 d = pci_get_domain(dev); 3145 b = pci_get_bus(dev); 3146 s = pci_get_slot(dev); 3147 f = pci_get_function(dev); 3148 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3149 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3150 return (1); 3151 return (0); 3152 } 3153 3154 /* 3155 * Return true if MSI can be used with this device. 3156 */ 3157 static int 3158 bge_can_use_msi(struct bge_softc *sc) 3159 { 3160 int can_use_msi = 0; 3161 3162 if (sc->bge_msi == 0) 3163 return (0); 3164 3165 /* Disable MSI for polling(4). */ 3166 #ifdef DEVICE_POLLING 3167 return (0); 3168 #endif 3169 switch (sc->bge_asicrev) { 3170 case BGE_ASICREV_BCM5714_A0: 3171 case BGE_ASICREV_BCM5714: 3172 /* 3173 * Apparently, MSI doesn't work when these chips are 3174 * configured in single-port mode. 3175 */ 3176 if (bge_has_multiple_ports(sc)) 3177 can_use_msi = 1; 3178 break; 3179 case BGE_ASICREV_BCM5750: 3180 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3181 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3182 can_use_msi = 1; 3183 break; 3184 case BGE_ASICREV_BCM5784: 3185 /* 3186 * Prevent infinite "watchdog timeout" errors 3187 * in some MacBook Pro and make it work out-of-the-box. 3188 */ 3189 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX) 3190 break; 3191 /* FALLTHROUGH */ 3192 default: 3193 if (BGE_IS_575X_PLUS(sc)) 3194 can_use_msi = 1; 3195 } 3196 return (can_use_msi); 3197 } 3198 3199 static int 3200 bge_mbox_reorder(struct bge_softc *sc) 3201 { 3202 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3203 static const struct mbox_reorder { 3204 const uint16_t vendor; 3205 const uint16_t device; 3206 const char *desc; 3207 } mbox_reorder_lists[] = { 3208 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3209 }; 3210 devclass_t pci, pcib; 3211 device_t bus, dev; 3212 int i; 3213 3214 pci = devclass_find("pci"); 3215 pcib = devclass_find("pcib"); 3216 dev = sc->bge_dev; 3217 bus = device_get_parent(dev); 3218 for (;;) { 3219 dev = device_get_parent(bus); 3220 bus = device_get_parent(dev); 3221 if (device_get_devclass(dev) != pcib) 3222 break; 3223 if (device_get_devclass(bus) != pci) 3224 break; 3225 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3226 if (pci_get_vendor(dev) == 3227 mbox_reorder_lists[i].vendor && 3228 pci_get_device(dev) == 3229 mbox_reorder_lists[i].device) { 3230 device_printf(sc->bge_dev, 3231 "enabling MBOX workaround for %s\n", 3232 mbox_reorder_lists[i].desc); 3233 return (1); 3234 } 3235 } 3236 } 3237 return (0); 3238 } 3239 3240 static void 3241 bge_devinfo(struct bge_softc *sc) 3242 { 3243 uint32_t cfg, clk; 3244 3245 device_printf(sc->bge_dev, 3246 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3247 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3248 if (sc->bge_flags & BGE_FLAG_PCIE) 3249 printf("PCI-E\n"); 3250 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3251 printf("PCI-X "); 3252 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3253 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3254 clk = 133; 3255 else { 3256 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3257 switch (clk) { 3258 case 0: 3259 clk = 33; 3260 break; 3261 case 2: 3262 clk = 50; 3263 break; 3264 case 4: 3265 clk = 66; 3266 break; 3267 case 6: 3268 clk = 100; 3269 break; 3270 case 7: 3271 clk = 133; 3272 break; 3273 } 3274 } 3275 printf("%u MHz\n", clk); 3276 } else { 3277 if (sc->bge_pcixcap != 0) 3278 printf("PCI on PCI-X "); 3279 else 3280 printf("PCI "); 3281 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3282 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3283 clk = 66; 3284 else 3285 clk = 33; 3286 if (cfg & BGE_PCISTATE_32BIT_BUS) 3287 printf("%u MHz; 32bit\n", clk); 3288 else 3289 printf("%u MHz; 64bit\n", clk); 3290 } 3291 } 3292 3293 static int 3294 bge_attach(device_t dev) 3295 { 3296 if_t ifp; 3297 struct bge_softc *sc; 3298 uint32_t hwcfg = 0, misccfg, pcistate; 3299 u_char eaddr[ETHER_ADDR_LEN]; 3300 int capmask, error, reg, rid, trys; 3301 3302 sc = device_get_softc(dev); 3303 sc->bge_dev = dev; 3304 3305 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3306 NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3307 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3308 3309 pci_enable_busmaster(dev); 3310 3311 /* 3312 * Allocate control/status registers. 3313 */ 3314 rid = PCIR_BAR(0); 3315 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3316 RF_ACTIVE); 3317 3318 if (sc->bge_res == NULL) { 3319 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3320 error = ENXIO; 3321 goto fail; 3322 } 3323 3324 /* Save various chip information. */ 3325 sc->bge_func_addr = pci_get_function(dev); 3326 sc->bge_chipid = bge_chipid(dev); 3327 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3328 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3329 3330 /* Set default PHY address. */ 3331 sc->bge_phy_addr = 1; 3332 /* 3333 * PHY address mapping for various devices. 3334 * 3335 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3336 * ---------+-------+-------+-------+-------+ 3337 * BCM57XX | 1 | X | X | X | 3338 * BCM5704 | 1 | X | 1 | X | 3339 * BCM5717 | 1 | 8 | 2 | 9 | 3340 * BCM5719 | 1 | 8 | 2 | 9 | 3341 * BCM5720 | 1 | 8 | 2 | 9 | 3342 * 3343 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3344 * ---------+-------+-------+-------+-------+ 3345 * BCM57XX | X | X | X | X | 3346 * BCM5704 | X | X | X | X | 3347 * BCM5717 | X | X | X | X | 3348 * BCM5719 | 3 | 10 | 4 | 11 | 3349 * BCM5720 | X | X | X | X | 3350 * 3351 * Other addresses may respond but they are not 3352 * IEEE compliant PHYs and should be ignored. 3353 */ 3354 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3355 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3356 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3357 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3358 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3359 BGE_SGDIGSTS_IS_SERDES) 3360 sc->bge_phy_addr = sc->bge_func_addr + 8; 3361 else 3362 sc->bge_phy_addr = sc->bge_func_addr + 1; 3363 } else { 3364 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3365 BGE_CPMU_PHY_STRAP_IS_SERDES) 3366 sc->bge_phy_addr = sc->bge_func_addr + 8; 3367 else 3368 sc->bge_phy_addr = sc->bge_func_addr + 1; 3369 } 3370 } 3371 3372 if (bge_has_eaddr(sc)) 3373 sc->bge_flags |= BGE_FLAG_EADDR; 3374 3375 /* Save chipset family. */ 3376 switch (sc->bge_asicrev) { 3377 case BGE_ASICREV_BCM5762: 3378 case BGE_ASICREV_BCM57765: 3379 case BGE_ASICREV_BCM57766: 3380 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3381 /* FALLTHROUGH */ 3382 case BGE_ASICREV_BCM5717: 3383 case BGE_ASICREV_BCM5719: 3384 case BGE_ASICREV_BCM5720: 3385 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3386 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3387 BGE_FLAG_JUMBO_FRAME; 3388 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3389 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3390 /* 3391 * Enable work around for DMA engine miscalculation 3392 * of TXMBUF available space. 3393 */ 3394 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3395 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3396 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3397 /* Jumbo frame on BCM5719 A0 does not work. */ 3398 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3399 } 3400 } 3401 break; 3402 case BGE_ASICREV_BCM5755: 3403 case BGE_ASICREV_BCM5761: 3404 case BGE_ASICREV_BCM5784: 3405 case BGE_ASICREV_BCM5785: 3406 case BGE_ASICREV_BCM5787: 3407 case BGE_ASICREV_BCM57780: 3408 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3409 BGE_FLAG_5705_PLUS; 3410 break; 3411 case BGE_ASICREV_BCM5700: 3412 case BGE_ASICREV_BCM5701: 3413 case BGE_ASICREV_BCM5703: 3414 case BGE_ASICREV_BCM5704: 3415 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3416 break; 3417 case BGE_ASICREV_BCM5714_A0: 3418 case BGE_ASICREV_BCM5780: 3419 case BGE_ASICREV_BCM5714: 3420 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3421 /* FALLTHROUGH */ 3422 case BGE_ASICREV_BCM5750: 3423 case BGE_ASICREV_BCM5752: 3424 case BGE_ASICREV_BCM5906: 3425 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3426 /* FALLTHROUGH */ 3427 case BGE_ASICREV_BCM5705: 3428 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3429 break; 3430 } 3431 3432 /* Identify chips with APE processor. */ 3433 switch (sc->bge_asicrev) { 3434 case BGE_ASICREV_BCM5717: 3435 case BGE_ASICREV_BCM5719: 3436 case BGE_ASICREV_BCM5720: 3437 case BGE_ASICREV_BCM5761: 3438 case BGE_ASICREV_BCM5762: 3439 sc->bge_flags |= BGE_FLAG_APE; 3440 break; 3441 } 3442 3443 /* Chips with APE need BAR2 access for APE registers/memory. */ 3444 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3445 rid = PCIR_BAR(2); 3446 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3447 RF_ACTIVE); 3448 if (sc->bge_res2 == NULL) { 3449 device_printf (sc->bge_dev, 3450 "couldn't map BAR2 memory\n"); 3451 error = ENXIO; 3452 goto fail; 3453 } 3454 3455 /* Enable APE register/memory access by host driver. */ 3456 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3457 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3458 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3459 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3460 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3461 3462 bge_ape_lock_init(sc); 3463 bge_ape_read_fw_ver(sc); 3464 } 3465 3466 /* Add SYSCTLs, requires the chipset family to be set. */ 3467 bge_add_sysctls(sc); 3468 3469 /* Identify the chips that use an CPMU. */ 3470 if (BGE_IS_5717_PLUS(sc) || 3471 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3472 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3473 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3474 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3475 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3476 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3477 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3478 else 3479 sc->bge_mi_mode = BGE_MIMODE_BASE; 3480 /* Enable auto polling for BCM570[0-5]. */ 3481 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3482 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3483 3484 /* 3485 * All Broadcom controllers have 4GB boundary DMA bug. 3486 * Whenever an address crosses a multiple of the 4GB boundary 3487 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3488 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3489 * state machine will lockup and cause the device to hang. 3490 */ 3491 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3492 3493 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3494 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3495 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3496 3497 /* 3498 * BCM5719 cannot handle DMA requests for DMA segments that 3499 * have larger than 4KB in size. However the maximum DMA 3500 * segment size created in DMA tag is 4KB for TSO, so we 3501 * wouldn't encounter the issue here. 3502 */ 3503 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3504 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3505 3506 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3507 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3508 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3509 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3510 sc->bge_flags |= BGE_FLAG_5788; 3511 } 3512 3513 capmask = BMSR_DEFCAPMASK; 3514 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3515 (misccfg == 0x4000 || misccfg == 0x8000)) || 3516 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3517 pci_get_vendor(dev) == BCOM_VENDORID && 3518 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3519 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3520 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3521 (pci_get_vendor(dev) == BCOM_VENDORID && 3522 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3523 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3524 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3525 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3526 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3527 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3528 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3529 /* These chips are 10/100 only. */ 3530 capmask &= ~BMSR_EXTSTAT; 3531 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3532 } 3533 3534 /* 3535 * Some controllers seem to require a special firmware to use 3536 * TSO. But the firmware is not available to FreeBSD and Linux 3537 * claims that the TSO performed by the firmware is slower than 3538 * hardware based TSO. Moreover the firmware based TSO has one 3539 * known bug which can't handle TSO if Ethernet header + IP/TCP 3540 * header is greater than 80 bytes. A workaround for the TSO 3541 * bug exist but it seems it's too expensive than not using 3542 * TSO at all. Some hardwares also have the TSO bug so limit 3543 * the TSO to the controllers that are not affected TSO issues 3544 * (e.g. 5755 or higher). 3545 */ 3546 if (BGE_IS_5717_PLUS(sc)) { 3547 /* BCM5717 requires different TSO configuration. */ 3548 sc->bge_flags |= BGE_FLAG_TSO3; 3549 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3550 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3551 /* TSO on BCM5719 A0 does not work. */ 3552 sc->bge_flags &= ~BGE_FLAG_TSO3; 3553 } 3554 } else if (BGE_IS_5755_PLUS(sc)) { 3555 /* 3556 * BCM5754 and BCM5787 shares the same ASIC id so 3557 * explicit device id check is required. 3558 * Due to unknown reason TSO does not work on BCM5755M. 3559 */ 3560 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3561 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3562 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3563 sc->bge_flags |= BGE_FLAG_TSO; 3564 } 3565 3566 /* 3567 * Check if this is a PCI-X or PCI Express device. 3568 */ 3569 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3570 /* 3571 * Found a PCI Express capabilities register, this 3572 * must be a PCI Express device. 3573 */ 3574 sc->bge_flags |= BGE_FLAG_PCIE; 3575 sc->bge_expcap = reg; 3576 /* Extract supported maximum payload size. */ 3577 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3578 PCIER_DEVICE_CAP, 2); 3579 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3580 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3581 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3582 sc->bge_expmrq = 2048; 3583 else 3584 sc->bge_expmrq = 4096; 3585 pci_set_max_read_req(dev, sc->bge_expmrq); 3586 } else { 3587 /* 3588 * Check if the device is in PCI-X Mode. 3589 * (This bit is not valid on PCI Express controllers.) 3590 */ 3591 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3592 sc->bge_pcixcap = reg; 3593 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3594 BGE_PCISTATE_PCI_BUSMODE) == 0) 3595 sc->bge_flags |= BGE_FLAG_PCIX; 3596 } 3597 3598 /* 3599 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3600 * not actually a MAC controller bug but an issue with the embedded 3601 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3602 */ 3603 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3604 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3605 /* 3606 * Some PCI-X bridges are known to trigger write reordering to 3607 * the mailbox registers. Typical phenomena is watchdog timeouts 3608 * caused by out-of-order TX completions. Enable workaround for 3609 * PCI-X devices that live behind these bridges. 3610 * Note, PCI-X controllers can run in PCI mode so we can't use 3611 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3612 */ 3613 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3614 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3615 /* 3616 * Allocate the interrupt, using MSI if possible. These devices 3617 * support 8 MSI messages, but only the first one is used in 3618 * normal operation. 3619 */ 3620 rid = 0; 3621 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3622 sc->bge_msicap = reg; 3623 reg = 1; 3624 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3625 rid = 1; 3626 sc->bge_flags |= BGE_FLAG_MSI; 3627 } 3628 } 3629 3630 /* 3631 * All controllers except BCM5700 supports tagged status but 3632 * we use tagged status only for MSI case on BCM5717. Otherwise 3633 * MSI on BCM5717 does not work. 3634 */ 3635 #ifndef DEVICE_POLLING 3636 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3637 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3638 #endif 3639 3640 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3641 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3642 3643 if (sc->bge_irq == NULL) { 3644 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3645 error = ENXIO; 3646 goto fail; 3647 } 3648 3649 bge_devinfo(sc); 3650 3651 sc->bge_asf_mode = 0; 3652 /* No ASF if APE present. */ 3653 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3654 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3655 BGE_SRAM_DATA_SIG_MAGIC)) { 3656 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3657 BGE_HWCFG_ASF) { 3658 sc->bge_asf_mode |= ASF_ENABLE; 3659 sc->bge_asf_mode |= ASF_STACKUP; 3660 if (BGE_IS_575X_PLUS(sc)) 3661 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3662 } 3663 } 3664 } 3665 3666 bge_stop_fw(sc); 3667 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3668 if (bge_reset(sc)) { 3669 device_printf(sc->bge_dev, "chip reset failed\n"); 3670 error = ENXIO; 3671 goto fail; 3672 } 3673 3674 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3675 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3676 3677 if (bge_chipinit(sc)) { 3678 device_printf(sc->bge_dev, "chip initialization failed\n"); 3679 error = ENXIO; 3680 goto fail; 3681 } 3682 3683 error = bge_get_eaddr(sc, eaddr); 3684 if (error) { 3685 device_printf(sc->bge_dev, 3686 "failed to read station address\n"); 3687 error = ENXIO; 3688 goto fail; 3689 } 3690 3691 /* 5705 limits RX return ring to 512 entries. */ 3692 if (BGE_IS_5717_PLUS(sc)) 3693 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3694 else if (BGE_IS_5705_PLUS(sc)) 3695 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3696 else 3697 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3698 3699 if (bge_dma_alloc(sc)) { 3700 device_printf(sc->bge_dev, 3701 "failed to allocate DMA resources\n"); 3702 error = ENXIO; 3703 goto fail; 3704 } 3705 3706 /* Set default tuneable values. */ 3707 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3708 sc->bge_rx_coal_ticks = 150; 3709 sc->bge_tx_coal_ticks = 150; 3710 sc->bge_rx_max_coal_bds = 10; 3711 sc->bge_tx_max_coal_bds = 10; 3712 3713 /* Initialize checksum features to use. */ 3714 sc->bge_csum_features = BGE_CSUM_FEATURES; 3715 if (sc->bge_forced_udpcsum != 0) 3716 sc->bge_csum_features |= CSUM_UDP; 3717 3718 /* Set up ifnet structure */ 3719 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3720 if (ifp == NULL) { 3721 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3722 error = ENXIO; 3723 goto fail; 3724 } 3725 if_setsoftc(ifp, sc); 3726 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3727 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3728 if_setioctlfn(ifp, bge_ioctl); 3729 if_setstartfn(ifp, bge_start); 3730 if_setinitfn(ifp, bge_init); 3731 if_setgetcounterfn(ifp, bge_get_counter); 3732 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3733 if_setsendqready(ifp); 3734 if_sethwassist(ifp, sc->bge_csum_features); 3735 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3736 IFCAP_VLAN_MTU); 3737 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3738 if_sethwassistbits(ifp, CSUM_TSO, 0); 3739 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3740 } 3741 #ifdef IFCAP_VLAN_HWCSUM 3742 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 3743 #endif 3744 if_setcapenable(ifp, if_getcapabilities(ifp)); 3745 #ifdef DEVICE_POLLING 3746 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 3747 #endif 3748 3749 /* 3750 * 5700 B0 chips do not support checksumming correctly due 3751 * to hardware bugs. 3752 */ 3753 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3754 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3755 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3756 if_sethwassist(ifp, 0); 3757 } 3758 3759 /* 3760 * Figure out what sort of media we have by checking the 3761 * hardware config word in the first 32k of NIC internal memory, 3762 * or fall back to examining the EEPROM if necessary. 3763 * Note: on some BCM5700 cards, this value appears to be unset. 3764 * If that's the case, we have to rely on identifying the NIC 3765 * by its PCI subsystem ID, as we do below for the SysKonnect 3766 * SK-9D41. 3767 */ 3768 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3769 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3770 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3771 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3772 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3773 sizeof(hwcfg))) { 3774 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3775 error = ENXIO; 3776 goto fail; 3777 } 3778 hwcfg = ntohl(hwcfg); 3779 } 3780 3781 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3782 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3783 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3784 if (BGE_IS_5705_PLUS(sc)) { 3785 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3786 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3787 } else 3788 sc->bge_flags |= BGE_FLAG_TBI; 3789 } 3790 3791 /* Set various PHY bug flags. */ 3792 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3793 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3794 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3795 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3796 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3797 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3798 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3799 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3800 if (pci_get_subvendor(dev) == DELL_VENDORID) 3801 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3802 if ((BGE_IS_5705_PLUS(sc)) && 3803 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3804 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3805 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3806 !BGE_IS_5717_PLUS(sc)) { 3807 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3808 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3809 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3810 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3811 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3812 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3813 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3814 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3815 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3816 } else 3817 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3818 } 3819 3820 /* 3821 * Don't enable Ethernet@WireSpeed for the 5700 or the 3822 * 5705 A0 and A1 chips. 3823 */ 3824 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3825 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3826 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3827 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3828 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3829 3830 if (sc->bge_flags & BGE_FLAG_TBI) { 3831 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3832 bge_ifmedia_sts); 3833 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3834 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3835 0, NULL); 3836 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3837 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3838 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3839 } else { 3840 /* 3841 * Do transceiver setup and tell the firmware the 3842 * driver is down so we can try to get access the 3843 * probe if ASF is running. Retry a couple of times 3844 * if we get a conflict with the ASF firmware accessing 3845 * the PHY. 3846 */ 3847 trys = 0; 3848 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3849 again: 3850 bge_asf_driver_up(sc); 3851 3852 error = mii_attach(dev, &sc->bge_miibus, ifp, 3853 (ifm_change_cb_t)bge_ifmedia_upd, 3854 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3855 MII_OFFSET_ANY, MIIF_DOPAUSE); 3856 if (error != 0) { 3857 if (trys++ < 4) { 3858 device_printf(sc->bge_dev, "Try again\n"); 3859 bge_miibus_writereg(sc->bge_dev, 3860 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3861 goto again; 3862 } 3863 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3864 goto fail; 3865 } 3866 3867 /* 3868 * Now tell the firmware we are going up after probing the PHY 3869 */ 3870 if (sc->bge_asf_mode & ASF_STACKUP) 3871 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3872 } 3873 3874 /* 3875 * When using the BCM5701 in PCI-X mode, data corruption has 3876 * been observed in the first few bytes of some received packets. 3877 * Aligning the packet buffer in memory eliminates the corruption. 3878 * Unfortunately, this misaligns the packet payloads. On platforms 3879 * which do not support unaligned accesses, we will realign the 3880 * payloads by copying the received packets. 3881 */ 3882 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3883 sc->bge_flags & BGE_FLAG_PCIX) 3884 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3885 3886 /* 3887 * Call MI attach routine. 3888 */ 3889 ether_ifattach(ifp, eaddr); 3890 3891 /* Tell upper layer we support long frames. */ 3892 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 3893 3894 /* 3895 * Hookup IRQ last. 3896 */ 3897 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3898 /* Take advantage of single-shot MSI. */ 3899 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3900 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3901 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3902 taskqueue_thread_enqueue, &sc->bge_tq); 3903 if (sc->bge_tq == NULL) { 3904 device_printf(dev, "could not create taskqueue.\n"); 3905 ether_ifdetach(ifp); 3906 error = ENOMEM; 3907 goto fail; 3908 } 3909 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3910 "%s taskq", device_get_nameunit(sc->bge_dev)); 3911 if (error != 0) { 3912 device_printf(dev, "could not start threads.\n"); 3913 ether_ifdetach(ifp); 3914 goto fail; 3915 } 3916 error = bus_setup_intr(dev, sc->bge_irq, 3917 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3918 &sc->bge_intrhand); 3919 } else 3920 error = bus_setup_intr(dev, sc->bge_irq, 3921 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3922 &sc->bge_intrhand); 3923 3924 if (error) { 3925 ether_ifdetach(ifp); 3926 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3927 goto fail; 3928 } 3929 3930 /* Attach driver debugnet methods. */ 3931 DEBUGNET_SET(ifp, bge); 3932 3933 fail: 3934 if (error) 3935 bge_detach(dev); 3936 return (error); 3937 } 3938 3939 static int 3940 bge_detach(device_t dev) 3941 { 3942 struct bge_softc *sc; 3943 if_t ifp; 3944 3945 sc = device_get_softc(dev); 3946 ifp = sc->bge_ifp; 3947 3948 #ifdef DEVICE_POLLING 3949 if (if_getcapenable(ifp) & IFCAP_POLLING) 3950 ether_poll_deregister(ifp); 3951 #endif 3952 3953 if (device_is_attached(dev)) { 3954 ether_ifdetach(ifp); 3955 BGE_LOCK(sc); 3956 bge_stop(sc); 3957 BGE_UNLOCK(sc); 3958 callout_drain(&sc->bge_stat_ch); 3959 } 3960 3961 if (sc->bge_tq) 3962 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3963 3964 if (sc->bge_flags & BGE_FLAG_TBI) 3965 ifmedia_removeall(&sc->bge_ifmedia); 3966 else if (sc->bge_miibus != NULL) { 3967 bus_generic_detach(dev); 3968 device_delete_child(dev, sc->bge_miibus); 3969 } 3970 3971 bge_release_resources(sc); 3972 3973 return (0); 3974 } 3975 3976 static void 3977 bge_release_resources(struct bge_softc *sc) 3978 { 3979 device_t dev; 3980 3981 dev = sc->bge_dev; 3982 3983 if (sc->bge_tq != NULL) 3984 taskqueue_free(sc->bge_tq); 3985 3986 if (sc->bge_intrhand != NULL) 3987 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3988 3989 if (sc->bge_irq != NULL) { 3990 bus_release_resource(dev, SYS_RES_IRQ, 3991 rman_get_rid(sc->bge_irq), sc->bge_irq); 3992 pci_release_msi(dev); 3993 } 3994 3995 if (sc->bge_res != NULL) 3996 bus_release_resource(dev, SYS_RES_MEMORY, 3997 rman_get_rid(sc->bge_res), sc->bge_res); 3998 3999 if (sc->bge_res2 != NULL) 4000 bus_release_resource(dev, SYS_RES_MEMORY, 4001 rman_get_rid(sc->bge_res2), sc->bge_res2); 4002 4003 if (sc->bge_ifp != NULL) 4004 if_free(sc->bge_ifp); 4005 4006 bge_dma_free(sc); 4007 4008 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4009 BGE_LOCK_DESTROY(sc); 4010 } 4011 4012 static int 4013 bge_reset(struct bge_softc *sc) 4014 { 4015 device_t dev; 4016 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4017 void (*write_op)(struct bge_softc *, int, int); 4018 uint16_t devctl; 4019 int i; 4020 4021 dev = sc->bge_dev; 4022 4023 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4024 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4025 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4026 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4027 4028 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4029 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4030 if (sc->bge_flags & BGE_FLAG_PCIE) 4031 write_op = bge_writemem_direct; 4032 else 4033 write_op = bge_writemem_ind; 4034 } else 4035 write_op = bge_writereg_ind; 4036 4037 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4038 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4039 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4040 for (i = 0; i < 8000; i++) { 4041 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4042 BGE_NVRAMSWARB_GNT1) 4043 break; 4044 DELAY(20); 4045 } 4046 if (i == 8000) { 4047 if (bootverbose) 4048 device_printf(dev, "NVRAM lock timedout!\n"); 4049 } 4050 } 4051 /* Take APE lock when performing reset. */ 4052 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4053 4054 /* Save some important PCI state. */ 4055 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4056 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4057 4058 pci_write_config(dev, BGE_PCI_MISC_CTL, 4059 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4060 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4061 4062 /* Disable fastboot on controllers that support it. */ 4063 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4064 BGE_IS_5755_PLUS(sc)) { 4065 if (bootverbose) 4066 device_printf(dev, "Disabling fastboot\n"); 4067 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4068 } 4069 4070 /* 4071 * Write the magic number to SRAM at offset 0xB50. 4072 * When firmware finishes its initialization it will 4073 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4074 */ 4075 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4076 4077 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4078 4079 /* XXX: Broadcom Linux driver. */ 4080 if (sc->bge_flags & BGE_FLAG_PCIE) { 4081 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4082 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4083 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4084 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4085 } 4086 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4087 /* Prevent PCIE link training during global reset */ 4088 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4089 reset |= 1 << 29; 4090 } 4091 } 4092 4093 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4094 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4095 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4096 val | BGE_VCPU_STATUS_DRV_RESET); 4097 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4098 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4099 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4100 } 4101 4102 /* 4103 * Set GPHY Power Down Override to leave GPHY 4104 * powered up in D0 uninitialized. 4105 */ 4106 if (BGE_IS_5705_PLUS(sc) && 4107 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4108 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4109 4110 /* Issue global reset */ 4111 write_op(sc, BGE_MISC_CFG, reset); 4112 4113 if (sc->bge_flags & BGE_FLAG_PCIE) 4114 DELAY(100 * 1000); 4115 else 4116 DELAY(1000); 4117 4118 /* XXX: Broadcom Linux driver. */ 4119 if (sc->bge_flags & BGE_FLAG_PCIE) { 4120 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4121 DELAY(500000); /* wait for link training to complete */ 4122 val = pci_read_config(dev, 0xC4, 4); 4123 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4124 } 4125 devctl = pci_read_config(dev, 4126 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4127 /* Clear enable no snoop and disable relaxed ordering. */ 4128 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4129 PCIEM_CTL_NOSNOOP_ENABLE); 4130 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4131 devctl, 2); 4132 pci_set_max_read_req(dev, sc->bge_expmrq); 4133 /* Clear error status. */ 4134 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4135 PCIEM_STA_CORRECTABLE_ERROR | 4136 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4137 PCIEM_STA_UNSUPPORTED_REQ, 2); 4138 } 4139 4140 /* Reset some of the PCI state that got zapped by reset. */ 4141 pci_write_config(dev, BGE_PCI_MISC_CTL, 4142 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4143 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4144 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4145 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4146 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4147 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4148 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4149 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4150 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4151 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4152 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4153 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4154 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4155 /* 4156 * Disable PCI-X relaxed ordering to ensure status block update 4157 * comes first then packet buffer DMA. Otherwise driver may 4158 * read stale status block. 4159 */ 4160 if (sc->bge_flags & BGE_FLAG_PCIX) { 4161 devctl = pci_read_config(dev, 4162 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4163 devctl &= ~PCIXM_COMMAND_ERO; 4164 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4165 devctl &= ~PCIXM_COMMAND_MAX_READ; 4166 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4167 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4168 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4169 PCIXM_COMMAND_MAX_READ); 4170 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4171 } 4172 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4173 devctl, 2); 4174 } 4175 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4176 if (BGE_IS_5714_FAMILY(sc)) { 4177 /* This chip disables MSI on reset. */ 4178 if (sc->bge_flags & BGE_FLAG_MSI) { 4179 val = pci_read_config(dev, 4180 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4181 pci_write_config(dev, 4182 sc->bge_msicap + PCIR_MSI_CTRL, 4183 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4184 val = CSR_READ_4(sc, BGE_MSI_MODE); 4185 CSR_WRITE_4(sc, BGE_MSI_MODE, 4186 val | BGE_MSIMODE_ENABLE); 4187 } 4188 val = CSR_READ_4(sc, BGE_MARB_MODE); 4189 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4190 } else 4191 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4192 4193 /* Fix up byte swapping. */ 4194 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4195 4196 val = CSR_READ_4(sc, BGE_MAC_MODE); 4197 val = (val & ~mac_mode_mask) | mac_mode; 4198 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4199 DELAY(40); 4200 4201 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4202 4203 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4204 for (i = 0; i < BGE_TIMEOUT; i++) { 4205 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4206 if (val & BGE_VCPU_STATUS_INIT_DONE) 4207 break; 4208 DELAY(100); 4209 } 4210 if (i == BGE_TIMEOUT) { 4211 device_printf(dev, "reset timed out\n"); 4212 return (1); 4213 } 4214 } else { 4215 /* 4216 * Poll until we see the 1's complement of the magic number. 4217 * This indicates that the firmware initialization is complete. 4218 * We expect this to fail if no chip containing the Ethernet 4219 * address is fitted though. 4220 */ 4221 for (i = 0; i < BGE_TIMEOUT; i++) { 4222 DELAY(10); 4223 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4224 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4225 break; 4226 } 4227 4228 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4229 device_printf(dev, 4230 "firmware handshake timed out, found 0x%08x\n", 4231 val); 4232 /* BCM57765 A0 needs additional time before accessing. */ 4233 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4234 DELAY(10 * 1000); /* XXX */ 4235 } 4236 4237 /* 4238 * The 5704 in TBI mode apparently needs some special 4239 * adjustment to insure the SERDES drive level is set 4240 * to 1.2V. 4241 */ 4242 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4243 sc->bge_flags & BGE_FLAG_TBI) { 4244 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4245 val = (val & ~0xFFF) | 0x880; 4246 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4247 } 4248 4249 /* XXX: Broadcom Linux driver. */ 4250 if (sc->bge_flags & BGE_FLAG_PCIE && 4251 !BGE_IS_5717_PLUS(sc) && 4252 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4253 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4254 /* Enable Data FIFO protection. */ 4255 val = CSR_READ_4(sc, 0x7C00); 4256 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4257 } 4258 4259 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4260 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4261 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4262 4263 return (0); 4264 } 4265 4266 static __inline void 4267 bge_rxreuse_std(struct bge_softc *sc, int i) 4268 { 4269 struct bge_rx_bd *r; 4270 4271 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4272 r->bge_flags = BGE_RXBDFLAG_END; 4273 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4274 r->bge_idx = i; 4275 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4276 } 4277 4278 static __inline void 4279 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4280 { 4281 struct bge_extrx_bd *r; 4282 4283 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4284 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4285 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4286 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4287 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4288 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4289 r->bge_idx = i; 4290 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4291 } 4292 4293 /* 4294 * Frame reception handling. This is called if there's a frame 4295 * on the receive return list. 4296 * 4297 * Note: we have to be able to handle two possibilities here: 4298 * 1) the frame is from the jumbo receive ring 4299 * 2) the frame is from the standard receive ring 4300 */ 4301 4302 static int 4303 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4304 { 4305 if_t ifp; 4306 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4307 uint16_t rx_cons; 4308 4309 rx_cons = sc->bge_rx_saved_considx; 4310 4311 /* Nothing to do. */ 4312 if (rx_cons == rx_prod) 4313 return (rx_npkts); 4314 4315 ifp = sc->bge_ifp; 4316 4317 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4318 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4319 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4320 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4321 if (BGE_IS_JUMBO_CAPABLE(sc) && 4322 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4323 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4324 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4325 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4326 4327 while (rx_cons != rx_prod) { 4328 struct bge_rx_bd *cur_rx; 4329 uint32_t rxidx; 4330 struct mbuf *m = NULL; 4331 uint16_t vlan_tag = 0; 4332 int have_tag = 0; 4333 4334 #ifdef DEVICE_POLLING 4335 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4336 if (sc->rxcycles <= 0) 4337 break; 4338 sc->rxcycles--; 4339 } 4340 #endif 4341 4342 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4343 4344 rxidx = cur_rx->bge_idx; 4345 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4346 4347 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4348 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4349 have_tag = 1; 4350 vlan_tag = cur_rx->bge_vlan_tag; 4351 } 4352 4353 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4354 jumbocnt++; 4355 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4356 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4357 bge_rxreuse_jumbo(sc, rxidx); 4358 continue; 4359 } 4360 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4361 bge_rxreuse_jumbo(sc, rxidx); 4362 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4363 continue; 4364 } 4365 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4366 } else { 4367 stdcnt++; 4368 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4369 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4370 bge_rxreuse_std(sc, rxidx); 4371 continue; 4372 } 4373 if (bge_newbuf_std(sc, rxidx) != 0) { 4374 bge_rxreuse_std(sc, rxidx); 4375 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4376 continue; 4377 } 4378 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4379 } 4380 4381 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 4382 #ifndef __NO_STRICT_ALIGNMENT 4383 /* 4384 * For architectures with strict alignment we must make sure 4385 * the payload is aligned. 4386 */ 4387 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4388 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4389 cur_rx->bge_len); 4390 m->m_data += ETHER_ALIGN; 4391 } 4392 #endif 4393 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4394 m->m_pkthdr.rcvif = ifp; 4395 4396 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 4397 bge_rxcsum(sc, cur_rx, m); 4398 4399 /* 4400 * If we received a packet with a vlan tag, 4401 * attach that information to the packet. 4402 */ 4403 if (have_tag) { 4404 m->m_pkthdr.ether_vtag = vlan_tag; 4405 m->m_flags |= M_VLANTAG; 4406 } 4407 4408 if (holdlck != 0) { 4409 BGE_UNLOCK(sc); 4410 if_input(ifp, m); 4411 BGE_LOCK(sc); 4412 } else 4413 if_input(ifp, m); 4414 rx_npkts++; 4415 4416 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4417 return (rx_npkts); 4418 } 4419 4420 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4421 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4422 if (stdcnt > 0) 4423 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4424 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4425 4426 if (jumbocnt > 0) 4427 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4428 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4429 4430 sc->bge_rx_saved_considx = rx_cons; 4431 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4432 if (stdcnt) 4433 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4434 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4435 if (jumbocnt) 4436 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4437 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4438 #ifdef notyet 4439 /* 4440 * This register wraps very quickly under heavy packet drops. 4441 * If you need correct statistics, you can enable this check. 4442 */ 4443 if (BGE_IS_5705_PLUS(sc)) 4444 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4445 #endif 4446 return (rx_npkts); 4447 } 4448 4449 static void 4450 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4451 { 4452 4453 if (BGE_IS_5717_PLUS(sc)) { 4454 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4455 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4456 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4457 if ((cur_rx->bge_error_flag & 4458 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4459 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4460 } 4461 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4462 m->m_pkthdr.csum_data = 4463 cur_rx->bge_tcp_udp_csum; 4464 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4465 CSUM_PSEUDO_HDR; 4466 } 4467 } 4468 } else { 4469 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4470 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4471 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4472 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4473 } 4474 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4475 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4476 m->m_pkthdr.csum_data = 4477 cur_rx->bge_tcp_udp_csum; 4478 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4479 CSUM_PSEUDO_HDR; 4480 } 4481 } 4482 } 4483 4484 static void 4485 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4486 { 4487 struct bge_tx_bd *cur_tx; 4488 if_t ifp; 4489 4490 BGE_LOCK_ASSERT(sc); 4491 4492 /* Nothing to do. */ 4493 if (sc->bge_tx_saved_considx == tx_cons) 4494 return; 4495 4496 ifp = sc->bge_ifp; 4497 4498 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4499 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4500 /* 4501 * Go through our tx ring and free mbufs for those 4502 * frames that have been sent. 4503 */ 4504 while (sc->bge_tx_saved_considx != tx_cons) { 4505 uint32_t idx; 4506 4507 idx = sc->bge_tx_saved_considx; 4508 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4509 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4510 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 4511 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4512 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4513 sc->bge_cdata.bge_tx_dmamap[idx], 4514 BUS_DMASYNC_POSTWRITE); 4515 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4516 sc->bge_cdata.bge_tx_dmamap[idx]); 4517 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4518 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4519 } 4520 sc->bge_txcnt--; 4521 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4522 } 4523 4524 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4525 if (sc->bge_txcnt == 0) 4526 sc->bge_timer = 0; 4527 } 4528 4529 #ifdef DEVICE_POLLING 4530 static int 4531 bge_poll(if_t ifp, enum poll_cmd cmd, int count) 4532 { 4533 struct bge_softc *sc = if_getsoftc(ifp); 4534 uint16_t rx_prod, tx_cons; 4535 uint32_t statusword; 4536 int rx_npkts = 0; 4537 4538 BGE_LOCK(sc); 4539 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4540 BGE_UNLOCK(sc); 4541 return (rx_npkts); 4542 } 4543 4544 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4545 sc->bge_cdata.bge_status_map, 4546 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4547 /* Fetch updates from the status block. */ 4548 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4549 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4550 4551 statusword = sc->bge_ldata.bge_status_block->bge_status; 4552 /* Clear the status so the next pass only sees the changes. */ 4553 sc->bge_ldata.bge_status_block->bge_status = 0; 4554 4555 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4556 sc->bge_cdata.bge_status_map, 4557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4558 4559 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4560 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4561 sc->bge_link_evt++; 4562 4563 if (cmd == POLL_AND_CHECK_STATUS) 4564 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4565 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4566 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4567 bge_link_upd(sc); 4568 4569 sc->rxcycles = count; 4570 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4571 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4572 BGE_UNLOCK(sc); 4573 return (rx_npkts); 4574 } 4575 bge_txeof(sc, tx_cons); 4576 if (!if_sendq_empty(ifp)) 4577 bge_start_locked(ifp); 4578 4579 BGE_UNLOCK(sc); 4580 return (rx_npkts); 4581 } 4582 #endif /* DEVICE_POLLING */ 4583 4584 static int 4585 bge_msi_intr(void *arg) 4586 { 4587 struct bge_softc *sc; 4588 4589 sc = (struct bge_softc *)arg; 4590 /* 4591 * This interrupt is not shared and controller already 4592 * disabled further interrupt. 4593 */ 4594 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4595 return (FILTER_HANDLED); 4596 } 4597 4598 static void 4599 bge_intr_task(void *arg, int pending) 4600 { 4601 struct bge_softc *sc; 4602 if_t ifp; 4603 uint32_t status, status_tag; 4604 uint16_t rx_prod, tx_cons; 4605 4606 sc = (struct bge_softc *)arg; 4607 ifp = sc->bge_ifp; 4608 4609 BGE_LOCK(sc); 4610 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 4611 BGE_UNLOCK(sc); 4612 return; 4613 } 4614 4615 /* Get updated status block. */ 4616 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4617 sc->bge_cdata.bge_status_map, 4618 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4619 4620 /* Save producer/consumer indices. */ 4621 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4622 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4623 status = sc->bge_ldata.bge_status_block->bge_status; 4624 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4625 /* Dirty the status flag. */ 4626 sc->bge_ldata.bge_status_block->bge_status = 0; 4627 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4628 sc->bge_cdata.bge_status_map, 4629 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4630 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4631 status_tag = 0; 4632 4633 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4634 bge_link_upd(sc); 4635 4636 /* Let controller work. */ 4637 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4638 4639 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4640 sc->bge_rx_saved_considx != rx_prod) { 4641 /* Check RX return ring producer/consumer. */ 4642 BGE_UNLOCK(sc); 4643 bge_rxeof(sc, rx_prod, 0); 4644 BGE_LOCK(sc); 4645 } 4646 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4647 /* Check TX ring producer/consumer. */ 4648 bge_txeof(sc, tx_cons); 4649 if (!if_sendq_empty(ifp)) 4650 bge_start_locked(ifp); 4651 } 4652 BGE_UNLOCK(sc); 4653 } 4654 4655 static void 4656 bge_intr(void *xsc) 4657 { 4658 struct bge_softc *sc; 4659 if_t ifp; 4660 uint32_t statusword; 4661 uint16_t rx_prod, tx_cons; 4662 4663 sc = xsc; 4664 4665 BGE_LOCK(sc); 4666 4667 ifp = sc->bge_ifp; 4668 4669 #ifdef DEVICE_POLLING 4670 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4671 BGE_UNLOCK(sc); 4672 return; 4673 } 4674 #endif 4675 4676 /* 4677 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4678 * disable interrupts by writing nonzero like we used to, since with 4679 * our current organization this just gives complications and 4680 * pessimizations for re-enabling interrupts. We used to have races 4681 * instead of the necessary complications. Disabling interrupts 4682 * would just reduce the chance of a status update while we are 4683 * running (by switching to the interrupt-mode coalescence 4684 * parameters), but this chance is already very low so it is more 4685 * efficient to get another interrupt than prevent it. 4686 * 4687 * We do the ack first to ensure another interrupt if there is a 4688 * status update after the ack. We don't check for the status 4689 * changing later because it is more efficient to get another 4690 * interrupt than prevent it, not quite as above (not checking is 4691 * a smaller optimization than not toggling the interrupt enable, 4692 * since checking doesn't involve PCI accesses and toggling require 4693 * the status check). So toggling would probably be a pessimization 4694 * even with MSI. It would only be needed for using a task queue. 4695 */ 4696 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4697 4698 /* 4699 * Do the mandatory PCI flush as well as get the link status. 4700 */ 4701 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4702 4703 /* Make sure the descriptor ring indexes are coherent. */ 4704 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4705 sc->bge_cdata.bge_status_map, 4706 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4707 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4708 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4709 sc->bge_ldata.bge_status_block->bge_status = 0; 4710 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4711 sc->bge_cdata.bge_status_map, 4712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4713 4714 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4715 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4716 statusword || sc->bge_link_evt) 4717 bge_link_upd(sc); 4718 4719 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4720 /* Check RX return ring producer/consumer. */ 4721 bge_rxeof(sc, rx_prod, 1); 4722 } 4723 4724 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4725 /* Check TX ring producer/consumer. */ 4726 bge_txeof(sc, tx_cons); 4727 } 4728 4729 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4730 !if_sendq_empty(ifp)) 4731 bge_start_locked(ifp); 4732 4733 BGE_UNLOCK(sc); 4734 } 4735 4736 static void 4737 bge_asf_driver_up(struct bge_softc *sc) 4738 { 4739 if (sc->bge_asf_mode & ASF_STACKUP) { 4740 /* Send ASF heartbeat aprox. every 2s */ 4741 if (sc->bge_asf_count) 4742 sc->bge_asf_count --; 4743 else { 4744 sc->bge_asf_count = 2; 4745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4746 BGE_FW_CMD_DRV_ALIVE); 4747 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4748 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4749 BGE_FW_HB_TIMEOUT_SEC); 4750 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4751 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4752 BGE_RX_CPU_DRV_EVENT); 4753 } 4754 } 4755 } 4756 4757 static void 4758 bge_tick(void *xsc) 4759 { 4760 struct bge_softc *sc = xsc; 4761 struct mii_data *mii = NULL; 4762 4763 BGE_LOCK_ASSERT(sc); 4764 4765 /* Synchronize with possible callout reset/stop. */ 4766 if (callout_pending(&sc->bge_stat_ch) || 4767 !callout_active(&sc->bge_stat_ch)) 4768 return; 4769 4770 if (BGE_IS_5705_PLUS(sc)) 4771 bge_stats_update_regs(sc); 4772 else 4773 bge_stats_update(sc); 4774 4775 /* XXX Add APE heartbeat check here? */ 4776 4777 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4778 mii = device_get_softc(sc->bge_miibus); 4779 /* 4780 * Do not touch PHY if we have link up. This could break 4781 * IPMI/ASF mode or produce extra input errors 4782 * (extra errors was reported for bcm5701 & bcm5704). 4783 */ 4784 if (!sc->bge_link) 4785 mii_tick(mii); 4786 } else { 4787 /* 4788 * Since in TBI mode auto-polling can't be used we should poll 4789 * link status manually. Here we register pending link event 4790 * and trigger interrupt. 4791 */ 4792 #ifdef DEVICE_POLLING 4793 /* In polling mode we poll link state in bge_poll(). */ 4794 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 4795 #endif 4796 { 4797 sc->bge_link_evt++; 4798 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4799 sc->bge_flags & BGE_FLAG_5788) 4800 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4801 else 4802 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4803 } 4804 } 4805 4806 bge_asf_driver_up(sc); 4807 bge_watchdog(sc); 4808 4809 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4810 } 4811 4812 static void 4813 bge_stats_update_regs(struct bge_softc *sc) 4814 { 4815 if_t ifp; 4816 struct bge_mac_stats *stats; 4817 uint32_t val; 4818 4819 ifp = sc->bge_ifp; 4820 stats = &sc->bge_mac_stats; 4821 4822 stats->ifHCOutOctets += 4823 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4824 stats->etherStatsCollisions += 4825 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4826 stats->outXonSent += 4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4828 stats->outXoffSent += 4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4830 stats->dot3StatsInternalMacTransmitErrors += 4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4832 stats->dot3StatsSingleCollisionFrames += 4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4834 stats->dot3StatsMultipleCollisionFrames += 4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4836 stats->dot3StatsDeferredTransmissions += 4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4838 stats->dot3StatsExcessiveCollisions += 4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4840 stats->dot3StatsLateCollisions += 4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4842 stats->ifHCOutUcastPkts += 4843 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4844 stats->ifHCOutMulticastPkts += 4845 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4846 stats->ifHCOutBroadcastPkts += 4847 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4848 4849 stats->ifHCInOctets += 4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4851 stats->etherStatsFragments += 4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4853 stats->ifHCInUcastPkts += 4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4855 stats->ifHCInMulticastPkts += 4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4857 stats->ifHCInBroadcastPkts += 4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4859 stats->dot3StatsFCSErrors += 4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4861 stats->dot3StatsAlignmentErrors += 4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4863 stats->xonPauseFramesReceived += 4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4865 stats->xoffPauseFramesReceived += 4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4867 stats->macControlFramesReceived += 4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4869 stats->xoffStateEntered += 4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4871 stats->dot3StatsFramesTooLong += 4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4873 stats->etherStatsJabbers += 4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4875 stats->etherStatsUndersizePkts += 4876 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4877 4878 stats->FramesDroppedDueToFilters += 4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4880 stats->DmaWriteQueueFull += 4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4882 stats->DmaWriteHighPriQueueFull += 4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4884 stats->NoMoreRxBDs += 4885 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4886 /* 4887 * XXX 4888 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4889 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4890 * includes number of unwanted multicast frames. This comes 4891 * from silicon bug and known workaround to get rough(not 4892 * exact) counter is to enable interrupt on MBUF low water 4893 * attention. This can be accomplished by setting 4894 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4895 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4896 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4897 * However that change would generate more interrupts and 4898 * there are still possibilities of losing multiple frames 4899 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4900 * Given that the workaround still would not get correct 4901 * counter I don't think it's worth to implement it. So 4902 * ignore reading the counter on controllers that have the 4903 * silicon bug. 4904 */ 4905 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4906 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4907 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4908 stats->InputDiscards += 4909 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4910 stats->InputErrors += 4911 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4912 stats->RecvThresholdHit += 4913 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4914 4915 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4916 /* 4917 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4918 * frames, it's safe to disable workaround for DMA engine's 4919 * miscalculation of TXMBUF space. 4920 */ 4921 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4922 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4923 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4924 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4925 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4926 else 4927 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4928 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4929 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4930 } 4931 } 4932 } 4933 4934 static void 4935 bge_stats_clear_regs(struct bge_softc *sc) 4936 { 4937 4938 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4939 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4951 4952 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4966 4967 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4968 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4969 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4970 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4974 } 4975 4976 static void 4977 bge_stats_update(struct bge_softc *sc) 4978 { 4979 if_t ifp; 4980 bus_size_t stats; 4981 uint32_t cnt; /* current register value */ 4982 4983 ifp = sc->bge_ifp; 4984 4985 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4986 4987 #define READ_STAT(sc, stats, stat) \ 4988 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4989 4990 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4991 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions); 4992 sc->bge_tx_collisions = cnt; 4993 4994 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4995 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds); 4996 sc->bge_rx_nobds = cnt; 4997 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4998 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs); 4999 sc->bge_rx_inerrs = cnt; 5000 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5001 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards); 5002 sc->bge_rx_discards = cnt; 5003 5004 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5005 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards); 5006 sc->bge_tx_discards = cnt; 5007 5008 #undef READ_STAT 5009 } 5010 5011 /* 5012 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5013 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5014 * but when such padded frames employ the bge IP/TCP checksum offload, 5015 * the hardware checksum assist gives incorrect results (possibly 5016 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5017 * If we pad such runts with zeros, the onboard checksum comes out correct. 5018 */ 5019 static __inline int 5020 bge_cksum_pad(struct mbuf *m) 5021 { 5022 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5023 struct mbuf *last; 5024 5025 /* If there's only the packet-header and we can pad there, use it. */ 5026 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5027 M_TRAILINGSPACE(m) >= padlen) { 5028 last = m; 5029 } else { 5030 /* 5031 * Walk packet chain to find last mbuf. We will either 5032 * pad there, or append a new mbuf and pad it. 5033 */ 5034 for (last = m; last->m_next != NULL; last = last->m_next); 5035 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5036 /* Allocate new empty mbuf, pad it. Compact later. */ 5037 struct mbuf *n; 5038 5039 MGET(n, M_NOWAIT, MT_DATA); 5040 if (n == NULL) 5041 return (ENOBUFS); 5042 n->m_len = 0; 5043 last->m_next = n; 5044 last = n; 5045 } 5046 } 5047 5048 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5049 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5050 last->m_len += padlen; 5051 m->m_pkthdr.len += padlen; 5052 5053 return (0); 5054 } 5055 5056 static struct mbuf * 5057 bge_check_short_dma(struct mbuf *m) 5058 { 5059 struct mbuf *n; 5060 int found; 5061 5062 /* 5063 * If device receive two back-to-back send BDs with less than 5064 * or equal to 8 total bytes then the device may hang. The two 5065 * back-to-back send BDs must in the same frame for this failure 5066 * to occur. Scan mbuf chains and see whether two back-to-back 5067 * send BDs are there. If this is the case, allocate new mbuf 5068 * and copy the frame to workaround the silicon bug. 5069 */ 5070 for (n = m, found = 0; n != NULL; n = n->m_next) { 5071 if (n->m_len < 8) { 5072 found++; 5073 if (found > 1) 5074 break; 5075 continue; 5076 } 5077 found = 0; 5078 } 5079 5080 if (found > 1) { 5081 n = m_defrag(m, M_NOWAIT); 5082 if (n == NULL) 5083 m_freem(m); 5084 } else 5085 n = m; 5086 return (n); 5087 } 5088 5089 static struct mbuf * 5090 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5091 uint16_t *flags) 5092 { 5093 struct ip *ip; 5094 struct tcphdr *tcp; 5095 struct mbuf *n; 5096 uint16_t hlen; 5097 uint32_t poff; 5098 5099 if (M_WRITABLE(m) == 0) { 5100 /* Get a writable copy. */ 5101 n = m_dup(m, M_NOWAIT); 5102 m_freem(m); 5103 if (n == NULL) 5104 return (NULL); 5105 m = n; 5106 } 5107 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5108 if (m == NULL) 5109 return (NULL); 5110 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5111 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5112 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5113 if (m == NULL) 5114 return (NULL); 5115 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5116 m = m_pullup(m, poff + (tcp->th_off << 2)); 5117 if (m == NULL) 5118 return (NULL); 5119 /* 5120 * It seems controller doesn't modify IP length and TCP pseudo 5121 * checksum. These checksum computed by upper stack should be 0. 5122 */ 5123 *mss = m->m_pkthdr.tso_segsz; 5124 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5125 ip->ip_sum = 0; 5126 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5127 /* Clear pseudo checksum computed by TCP stack. */ 5128 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5129 tcp->th_sum = 0; 5130 /* 5131 * Broadcom controllers uses different descriptor format for 5132 * TSO depending on ASIC revision. Due to TSO-capable firmware 5133 * license issue and lower performance of firmware based TSO 5134 * we only support hardware based TSO. 5135 */ 5136 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5137 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5138 if (sc->bge_flags & BGE_FLAG_TSO3) { 5139 /* 5140 * For BCM5717 and newer controllers, hardware based TSO 5141 * uses the 14 lower bits of the bge_mss field to store the 5142 * MSS and the upper 2 bits to store the lowest 2 bits of 5143 * the IP/TCP header length. The upper 6 bits of the header 5144 * length are stored in the bge_flags[14:10,4] field. Jumbo 5145 * frames are supported. 5146 */ 5147 *mss |= ((hlen & 0x3) << 14); 5148 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5149 } else { 5150 /* 5151 * For BCM5755 and newer controllers, hardware based TSO uses 5152 * the lower 11 bits to store the MSS and the upper 5 bits to 5153 * store the IP/TCP header length. Jumbo frames are not 5154 * supported. 5155 */ 5156 *mss |= (hlen << 11); 5157 } 5158 return (m); 5159 } 5160 5161 /* 5162 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5163 * pointers to descriptors. 5164 */ 5165 static int 5166 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5167 { 5168 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5169 bus_dmamap_t map; 5170 struct bge_tx_bd *d; 5171 struct mbuf *m = *m_head; 5172 uint32_t idx = *txidx; 5173 uint16_t csum_flags, mss, vlan_tag; 5174 int nsegs, i, error; 5175 5176 csum_flags = 0; 5177 mss = 0; 5178 vlan_tag = 0; 5179 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5180 m->m_next != NULL) { 5181 *m_head = bge_check_short_dma(m); 5182 if (*m_head == NULL) 5183 return (ENOBUFS); 5184 m = *m_head; 5185 } 5186 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5187 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5188 if (*m_head == NULL) 5189 return (ENOBUFS); 5190 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5191 BGE_TXBDFLAG_CPU_POST_DMA; 5192 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5193 if (m->m_pkthdr.csum_flags & CSUM_IP) 5194 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5195 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5196 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5197 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5198 (error = bge_cksum_pad(m)) != 0) { 5199 m_freem(m); 5200 *m_head = NULL; 5201 return (error); 5202 } 5203 } 5204 } 5205 5206 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5207 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5208 m->m_pkthdr.len > ETHER_MAX_LEN) 5209 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5210 if (sc->bge_forced_collapse > 0 && 5211 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5212 /* 5213 * Forcedly collapse mbuf chains to overcome hardware 5214 * limitation which only support a single outstanding 5215 * DMA read operation. 5216 */ 5217 if (sc->bge_forced_collapse == 1) 5218 m = m_defrag(m, M_NOWAIT); 5219 else 5220 m = m_collapse(m, M_NOWAIT, 5221 sc->bge_forced_collapse); 5222 if (m == NULL) 5223 m = *m_head; 5224 *m_head = m; 5225 } 5226 } 5227 5228 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5229 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5230 &nsegs, BUS_DMA_NOWAIT); 5231 if (error == EFBIG) { 5232 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5233 if (m == NULL) { 5234 m_freem(*m_head); 5235 *m_head = NULL; 5236 return (ENOBUFS); 5237 } 5238 *m_head = m; 5239 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5240 m, segs, &nsegs, BUS_DMA_NOWAIT); 5241 if (error) { 5242 m_freem(m); 5243 *m_head = NULL; 5244 return (error); 5245 } 5246 } else if (error != 0) 5247 return (error); 5248 5249 /* Check if we have enough free send BDs. */ 5250 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5251 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5252 return (ENOBUFS); 5253 } 5254 5255 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5256 5257 if (m->m_flags & M_VLANTAG) { 5258 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5259 vlan_tag = m->m_pkthdr.ether_vtag; 5260 } 5261 5262 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5263 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5264 /* 5265 * 5725 family of devices corrupts TSO packets when TSO DMA 5266 * buffers cross into regions which are within MSS bytes of 5267 * a 4GB boundary. If we encounter the condition, drop the 5268 * packet. 5269 */ 5270 for (i = 0; ; i++) { 5271 d = &sc->bge_ldata.bge_tx_ring[idx]; 5272 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5273 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5274 d->bge_len = segs[i].ds_len; 5275 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5276 d->bge_addr.bge_addr_lo) 5277 break; 5278 d->bge_flags = csum_flags; 5279 d->bge_vlan_tag = vlan_tag; 5280 d->bge_mss = mss; 5281 if (i == nsegs - 1) 5282 break; 5283 BGE_INC(idx, BGE_TX_RING_CNT); 5284 } 5285 if (i != nsegs - 1) { 5286 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5287 BUS_DMASYNC_POSTWRITE); 5288 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5289 m_freem(*m_head); 5290 *m_head = NULL; 5291 return (EIO); 5292 } 5293 } else { 5294 for (i = 0; ; i++) { 5295 d = &sc->bge_ldata.bge_tx_ring[idx]; 5296 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5297 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5298 d->bge_len = segs[i].ds_len; 5299 d->bge_flags = csum_flags; 5300 d->bge_vlan_tag = vlan_tag; 5301 d->bge_mss = mss; 5302 if (i == nsegs - 1) 5303 break; 5304 BGE_INC(idx, BGE_TX_RING_CNT); 5305 } 5306 } 5307 5308 /* Mark the last segment as end of packet... */ 5309 d->bge_flags |= BGE_TXBDFLAG_END; 5310 5311 /* 5312 * Insure that the map for this transmission 5313 * is placed at the array index of the last descriptor 5314 * in this chain. 5315 */ 5316 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5317 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5318 sc->bge_cdata.bge_tx_chain[idx] = m; 5319 sc->bge_txcnt += nsegs; 5320 5321 BGE_INC(idx, BGE_TX_RING_CNT); 5322 *txidx = idx; 5323 5324 return (0); 5325 } 5326 5327 /* 5328 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5329 * to the mbuf data regions directly in the transmit descriptors. 5330 */ 5331 static void 5332 bge_start_locked(if_t ifp) 5333 { 5334 struct bge_softc *sc; 5335 struct mbuf *m_head; 5336 uint32_t prodidx; 5337 int count; 5338 5339 sc = if_getsoftc(ifp); 5340 BGE_LOCK_ASSERT(sc); 5341 5342 if (!sc->bge_link || 5343 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5344 IFF_DRV_RUNNING) 5345 return; 5346 5347 prodidx = sc->bge_tx_prodidx; 5348 5349 for (count = 0; !if_sendq_empty(ifp);) { 5350 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5351 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5352 break; 5353 } 5354 m_head = if_dequeue(ifp); 5355 if (m_head == NULL) 5356 break; 5357 5358 /* 5359 * Pack the data into the transmit ring. If we 5360 * don't have room, set the OACTIVE flag and wait 5361 * for the NIC to drain the ring. 5362 */ 5363 if (bge_encap(sc, &m_head, &prodidx)) { 5364 if (m_head == NULL) 5365 break; 5366 if_sendq_prepend(ifp, m_head); 5367 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5368 break; 5369 } 5370 ++count; 5371 5372 /* 5373 * If there's a BPF listener, bounce a copy of this frame 5374 * to him. 5375 */ 5376 if_bpfmtap(ifp, m_head); 5377 } 5378 5379 if (count > 0) 5380 bge_start_tx(sc, prodidx); 5381 } 5382 5383 static void 5384 bge_start_tx(struct bge_softc *sc, uint32_t prodidx) 5385 { 5386 5387 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5388 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5389 /* Transmit. */ 5390 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5391 /* 5700 b2 errata */ 5392 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5393 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5394 5395 sc->bge_tx_prodidx = prodidx; 5396 5397 /* Set a timeout in case the chip goes out to lunch. */ 5398 sc->bge_timer = BGE_TX_TIMEOUT; 5399 } 5400 5401 /* 5402 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5403 * to the mbuf data regions directly in the transmit descriptors. 5404 */ 5405 static void 5406 bge_start(if_t ifp) 5407 { 5408 struct bge_softc *sc; 5409 5410 sc = if_getsoftc(ifp); 5411 BGE_LOCK(sc); 5412 bge_start_locked(ifp); 5413 BGE_UNLOCK(sc); 5414 } 5415 5416 static void 5417 bge_init_locked(struct bge_softc *sc) 5418 { 5419 if_t ifp; 5420 uint16_t *m; 5421 uint32_t mode; 5422 5423 BGE_LOCK_ASSERT(sc); 5424 5425 ifp = sc->bge_ifp; 5426 5427 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5428 return; 5429 5430 /* Cancel pending I/O and flush buffers. */ 5431 bge_stop(sc); 5432 5433 bge_stop_fw(sc); 5434 bge_sig_pre_reset(sc, BGE_RESET_START); 5435 bge_reset(sc); 5436 bge_sig_legacy(sc, BGE_RESET_START); 5437 bge_sig_post_reset(sc, BGE_RESET_START); 5438 5439 bge_chipinit(sc); 5440 5441 /* 5442 * Init the various state machines, ring 5443 * control blocks and firmware. 5444 */ 5445 if (bge_blockinit(sc)) { 5446 device_printf(sc->bge_dev, "initialization failure\n"); 5447 return; 5448 } 5449 5450 ifp = sc->bge_ifp; 5451 5452 /* Specify MTU. */ 5453 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5454 ETHER_HDR_LEN + ETHER_CRC_LEN + 5455 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5456 5457 /* Load our MAC address. */ 5458 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5459 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5460 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5461 5462 /* Program promiscuous mode. */ 5463 bge_setpromisc(sc); 5464 5465 /* Program multicast filter. */ 5466 bge_setmulti(sc); 5467 5468 /* Program VLAN tag stripping. */ 5469 bge_setvlan(sc); 5470 5471 /* Override UDP checksum offloading. */ 5472 if (sc->bge_forced_udpcsum == 0) 5473 sc->bge_csum_features &= ~CSUM_UDP; 5474 else 5475 sc->bge_csum_features |= CSUM_UDP; 5476 if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5477 if_getcapenable(ifp) & IFCAP_TXCSUM) { 5478 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5479 if_sethwassistbits(ifp, sc->bge_csum_features, 0); 5480 } 5481 5482 /* Init RX ring. */ 5483 if (bge_init_rx_ring_std(sc) != 0) { 5484 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5485 bge_stop(sc); 5486 return; 5487 } 5488 5489 /* 5490 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5491 * memory to insure that the chip has in fact read the first 5492 * entry of the ring. 5493 */ 5494 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5495 uint32_t v, i; 5496 for (i = 0; i < 10; i++) { 5497 DELAY(20); 5498 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5499 if (v == (MCLBYTES - ETHER_ALIGN)) 5500 break; 5501 } 5502 if (i == 10) 5503 device_printf (sc->bge_dev, 5504 "5705 A0 chip failed to load RX ring\n"); 5505 } 5506 5507 /* Init jumbo RX ring. */ 5508 if (BGE_IS_JUMBO_CAPABLE(sc) && 5509 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5510 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 5511 if (bge_init_rx_ring_jumbo(sc) != 0) { 5512 device_printf(sc->bge_dev, 5513 "no memory for jumbo Rx buffers.\n"); 5514 bge_stop(sc); 5515 return; 5516 } 5517 } 5518 5519 /* Init our RX return ring index. */ 5520 sc->bge_rx_saved_considx = 0; 5521 5522 /* Init our RX/TX stat counters. */ 5523 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5524 5525 /* Init TX ring. */ 5526 bge_init_tx_ring(sc); 5527 5528 /* Enable TX MAC state machine lockup fix. */ 5529 mode = CSR_READ_4(sc, BGE_TX_MODE); 5530 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5531 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5532 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5533 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5534 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5535 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5536 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5537 } 5538 /* Turn on transmitter. */ 5539 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5540 DELAY(100); 5541 5542 /* Turn on receiver. */ 5543 mode = CSR_READ_4(sc, BGE_RX_MODE); 5544 if (BGE_IS_5755_PLUS(sc)) 5545 mode |= BGE_RXMODE_IPV6_ENABLE; 5546 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5547 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5548 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5549 DELAY(10); 5550 5551 /* 5552 * Set the number of good frames to receive after RX MBUF 5553 * Low Watermark has been reached. After the RX MAC receives 5554 * this number of frames, it will drop subsequent incoming 5555 * frames until the MBUF High Watermark is reached. 5556 */ 5557 if (BGE_IS_57765_PLUS(sc)) 5558 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5559 else 5560 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5561 5562 /* Clear MAC statistics. */ 5563 if (BGE_IS_5705_PLUS(sc)) 5564 bge_stats_clear_regs(sc); 5565 5566 /* Tell firmware we're alive. */ 5567 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5568 5569 #ifdef DEVICE_POLLING 5570 /* Disable interrupts if we are polling. */ 5571 if (if_getcapenable(ifp) & IFCAP_POLLING) { 5572 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5573 BGE_PCIMISCCTL_MASK_PCI_INTR); 5574 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5575 } else 5576 #endif 5577 5578 /* Enable host interrupts. */ 5579 { 5580 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5581 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5582 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5583 } 5584 5585 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5586 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 5587 5588 bge_ifmedia_upd_locked(ifp); 5589 5590 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5591 } 5592 5593 static void 5594 bge_init(void *xsc) 5595 { 5596 struct bge_softc *sc = xsc; 5597 5598 BGE_LOCK(sc); 5599 bge_init_locked(sc); 5600 BGE_UNLOCK(sc); 5601 } 5602 5603 /* 5604 * Set media options. 5605 */ 5606 static int 5607 bge_ifmedia_upd(if_t ifp) 5608 { 5609 struct bge_softc *sc = if_getsoftc(ifp); 5610 int res; 5611 5612 BGE_LOCK(sc); 5613 res = bge_ifmedia_upd_locked(ifp); 5614 BGE_UNLOCK(sc); 5615 5616 return (res); 5617 } 5618 5619 static int 5620 bge_ifmedia_upd_locked(if_t ifp) 5621 { 5622 struct bge_softc *sc = if_getsoftc(ifp); 5623 struct mii_data *mii; 5624 struct mii_softc *miisc; 5625 struct ifmedia *ifm; 5626 5627 BGE_LOCK_ASSERT(sc); 5628 5629 ifm = &sc->bge_ifmedia; 5630 5631 /* If this is a 1000baseX NIC, enable the TBI port. */ 5632 if (sc->bge_flags & BGE_FLAG_TBI) { 5633 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5634 return (EINVAL); 5635 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5636 case IFM_AUTO: 5637 /* 5638 * The BCM5704 ASIC appears to have a special 5639 * mechanism for programming the autoneg 5640 * advertisement registers in TBI mode. 5641 */ 5642 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5643 uint32_t sgdig; 5644 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5645 if (sgdig & BGE_SGDIGSTS_DONE) { 5646 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5647 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5648 sgdig |= BGE_SGDIGCFG_AUTO | 5649 BGE_SGDIGCFG_PAUSE_CAP | 5650 BGE_SGDIGCFG_ASYM_PAUSE; 5651 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5652 sgdig | BGE_SGDIGCFG_SEND); 5653 DELAY(5); 5654 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5655 } 5656 } 5657 break; 5658 case IFM_1000_SX: 5659 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5660 BGE_CLRBIT(sc, BGE_MAC_MODE, 5661 BGE_MACMODE_HALF_DUPLEX); 5662 } else { 5663 BGE_SETBIT(sc, BGE_MAC_MODE, 5664 BGE_MACMODE_HALF_DUPLEX); 5665 } 5666 DELAY(40); 5667 break; 5668 default: 5669 return (EINVAL); 5670 } 5671 return (0); 5672 } 5673 5674 sc->bge_link_evt++; 5675 mii = device_get_softc(sc->bge_miibus); 5676 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5677 PHY_RESET(miisc); 5678 mii_mediachg(mii); 5679 5680 /* 5681 * Force an interrupt so that we will call bge_link_upd 5682 * if needed and clear any pending link state attention. 5683 * Without this we are not getting any further interrupts 5684 * for link state changes and thus will not UP the link and 5685 * not be able to send in bge_start_locked. The only 5686 * way to get things working was to receive a packet and 5687 * get an RX intr. 5688 * bge_tick should help for fiber cards and we might not 5689 * need to do this here if BGE_FLAG_TBI is set but as 5690 * we poll for fiber anyway it should not harm. 5691 */ 5692 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5693 sc->bge_flags & BGE_FLAG_5788) 5694 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5695 else 5696 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5697 5698 return (0); 5699 } 5700 5701 /* 5702 * Report current media status. 5703 */ 5704 static void 5705 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 5706 { 5707 struct bge_softc *sc = if_getsoftc(ifp); 5708 struct mii_data *mii; 5709 5710 BGE_LOCK(sc); 5711 5712 if ((if_getflags(ifp) & IFF_UP) == 0) { 5713 BGE_UNLOCK(sc); 5714 return; 5715 } 5716 if (sc->bge_flags & BGE_FLAG_TBI) { 5717 ifmr->ifm_status = IFM_AVALID; 5718 ifmr->ifm_active = IFM_ETHER; 5719 if (CSR_READ_4(sc, BGE_MAC_STS) & 5720 BGE_MACSTAT_TBI_PCS_SYNCHED) 5721 ifmr->ifm_status |= IFM_ACTIVE; 5722 else { 5723 ifmr->ifm_active |= IFM_NONE; 5724 BGE_UNLOCK(sc); 5725 return; 5726 } 5727 ifmr->ifm_active |= IFM_1000_SX; 5728 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5729 ifmr->ifm_active |= IFM_HDX; 5730 else 5731 ifmr->ifm_active |= IFM_FDX; 5732 BGE_UNLOCK(sc); 5733 return; 5734 } 5735 5736 mii = device_get_softc(sc->bge_miibus); 5737 mii_pollstat(mii); 5738 ifmr->ifm_active = mii->mii_media_active; 5739 ifmr->ifm_status = mii->mii_media_status; 5740 5741 BGE_UNLOCK(sc); 5742 } 5743 5744 static int 5745 bge_ioctl(if_t ifp, u_long command, caddr_t data) 5746 { 5747 struct bge_softc *sc = if_getsoftc(ifp); 5748 struct ifreq *ifr = (struct ifreq *) data; 5749 struct mii_data *mii; 5750 int flags, mask, error = 0; 5751 5752 switch (command) { 5753 case SIOCSIFMTU: 5754 if (BGE_IS_JUMBO_CAPABLE(sc) || 5755 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5756 if (ifr->ifr_mtu < ETHERMIN || 5757 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5758 error = EINVAL; 5759 break; 5760 } 5761 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5762 error = EINVAL; 5763 break; 5764 } 5765 BGE_LOCK(sc); 5766 if (if_getmtu(ifp) != ifr->ifr_mtu) { 5767 if_setmtu(ifp, ifr->ifr_mtu); 5768 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5769 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5770 bge_init_locked(sc); 5771 } 5772 } 5773 BGE_UNLOCK(sc); 5774 break; 5775 case SIOCSIFFLAGS: 5776 BGE_LOCK(sc); 5777 if (if_getflags(ifp) & IFF_UP) { 5778 /* 5779 * If only the state of the PROMISC flag changed, 5780 * then just use the 'set promisc mode' command 5781 * instead of reinitializing the entire NIC. Doing 5782 * a full re-init means reloading the firmware and 5783 * waiting for it to start up, which may take a 5784 * second or two. Similarly for ALLMULTI. 5785 */ 5786 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5787 flags = if_getflags(ifp) ^ sc->bge_if_flags; 5788 if (flags & IFF_PROMISC) 5789 bge_setpromisc(sc); 5790 if (flags & IFF_ALLMULTI) 5791 bge_setmulti(sc); 5792 } else 5793 bge_init_locked(sc); 5794 } else { 5795 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5796 bge_stop(sc); 5797 } 5798 } 5799 sc->bge_if_flags = if_getflags(ifp); 5800 BGE_UNLOCK(sc); 5801 error = 0; 5802 break; 5803 case SIOCADDMULTI: 5804 case SIOCDELMULTI: 5805 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5806 BGE_LOCK(sc); 5807 bge_setmulti(sc); 5808 BGE_UNLOCK(sc); 5809 error = 0; 5810 } 5811 break; 5812 case SIOCSIFMEDIA: 5813 case SIOCGIFMEDIA: 5814 if (sc->bge_flags & BGE_FLAG_TBI) { 5815 error = ifmedia_ioctl(ifp, ifr, 5816 &sc->bge_ifmedia, command); 5817 } else { 5818 mii = device_get_softc(sc->bge_miibus); 5819 error = ifmedia_ioctl(ifp, ifr, 5820 &mii->mii_media, command); 5821 } 5822 break; 5823 case SIOCSIFCAP: 5824 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 5825 #ifdef DEVICE_POLLING 5826 if (mask & IFCAP_POLLING) { 5827 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5828 error = ether_poll_register(bge_poll, ifp); 5829 if (error) 5830 return (error); 5831 BGE_LOCK(sc); 5832 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5833 BGE_PCIMISCCTL_MASK_PCI_INTR); 5834 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5835 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 5836 BGE_UNLOCK(sc); 5837 } else { 5838 error = ether_poll_deregister(ifp); 5839 /* Enable interrupt even in error case */ 5840 BGE_LOCK(sc); 5841 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5842 BGE_PCIMISCCTL_MASK_PCI_INTR); 5843 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5844 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 5845 BGE_UNLOCK(sc); 5846 } 5847 } 5848 #endif 5849 if ((mask & IFCAP_TXCSUM) != 0 && 5850 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5851 if_togglecapenable(ifp, IFCAP_TXCSUM); 5852 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5853 if_sethwassistbits(ifp, 5854 sc->bge_csum_features, 0); 5855 else 5856 if_sethwassistbits(ifp, 0, 5857 sc->bge_csum_features); 5858 } 5859 5860 if ((mask & IFCAP_RXCSUM) != 0 && 5861 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5862 if_togglecapenable(ifp, IFCAP_RXCSUM); 5863 5864 if ((mask & IFCAP_TSO4) != 0 && 5865 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5866 if_togglecapenable(ifp, IFCAP_TSO4); 5867 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5868 if_sethwassistbits(ifp, CSUM_TSO, 0); 5869 else 5870 if_sethwassistbits(ifp, 0, CSUM_TSO); 5871 } 5872 5873 if (mask & IFCAP_VLAN_MTU) { 5874 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5875 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5876 bge_init(sc); 5877 } 5878 5879 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5880 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5881 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 5882 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5883 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5884 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5885 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5886 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5887 BGE_LOCK(sc); 5888 bge_setvlan(sc); 5889 BGE_UNLOCK(sc); 5890 } 5891 #ifdef VLAN_CAPABILITIES 5892 if_vlancap(ifp); 5893 #endif 5894 break; 5895 default: 5896 error = ether_ioctl(ifp, command, data); 5897 break; 5898 } 5899 5900 return (error); 5901 } 5902 5903 static void 5904 bge_watchdog(struct bge_softc *sc) 5905 { 5906 if_t ifp; 5907 uint32_t status; 5908 5909 BGE_LOCK_ASSERT(sc); 5910 5911 if (sc->bge_timer == 0 || --sc->bge_timer) 5912 return; 5913 5914 /* If pause frames are active then don't reset the hardware. */ 5915 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5916 status = CSR_READ_4(sc, BGE_RX_STS); 5917 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5918 /* 5919 * If link partner has us in XOFF state then wait for 5920 * the condition to clear. 5921 */ 5922 CSR_WRITE_4(sc, BGE_RX_STS, status); 5923 sc->bge_timer = BGE_TX_TIMEOUT; 5924 return; 5925 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5926 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5927 /* 5928 * If link partner has us in XOFF state then wait for 5929 * the condition to clear. 5930 */ 5931 CSR_WRITE_4(sc, BGE_RX_STS, status); 5932 sc->bge_timer = BGE_TX_TIMEOUT; 5933 return; 5934 } 5935 /* 5936 * Any other condition is unexpected and the controller 5937 * should be reset. 5938 */ 5939 } 5940 5941 ifp = sc->bge_ifp; 5942 5943 if_printf(ifp, "watchdog timeout -- resetting\n"); 5944 5945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5946 bge_init_locked(sc); 5947 5948 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 5949 } 5950 5951 static void 5952 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5953 { 5954 int i; 5955 5956 BGE_CLRBIT(sc, reg, bit); 5957 5958 for (i = 0; i < BGE_TIMEOUT; i++) { 5959 if ((CSR_READ_4(sc, reg) & bit) == 0) 5960 return; 5961 DELAY(100); 5962 } 5963 } 5964 5965 /* 5966 * Stop the adapter and free any mbufs allocated to the 5967 * RX and TX lists. 5968 */ 5969 static void 5970 bge_stop(struct bge_softc *sc) 5971 { 5972 if_t ifp; 5973 5974 BGE_LOCK_ASSERT(sc); 5975 5976 ifp = sc->bge_ifp; 5977 5978 callout_stop(&sc->bge_stat_ch); 5979 5980 /* Disable host interrupts. */ 5981 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5982 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5983 5984 /* 5985 * Tell firmware we're shutting down. 5986 */ 5987 bge_stop_fw(sc); 5988 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5989 5990 /* 5991 * Disable all of the receiver blocks. 5992 */ 5993 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5996 if (BGE_IS_5700_FAMILY(sc)) 5997 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5998 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6001 6002 /* 6003 * Disable all of the transmit blocks. 6004 */ 6005 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6006 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6008 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6009 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6010 if (BGE_IS_5700_FAMILY(sc)) 6011 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6012 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6013 6014 /* 6015 * Shut down all of the memory managers and related 6016 * state machines. 6017 */ 6018 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6019 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6020 if (BGE_IS_5700_FAMILY(sc)) 6021 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6022 6023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6024 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6025 if (!(BGE_IS_5705_PLUS(sc))) { 6026 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6027 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6028 } 6029 /* Update MAC statistics. */ 6030 if (BGE_IS_5705_PLUS(sc)) 6031 bge_stats_update_regs(sc); 6032 6033 bge_reset(sc); 6034 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6035 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6036 6037 /* 6038 * Keep the ASF firmware running if up. 6039 */ 6040 if (sc->bge_asf_mode & ASF_STACKUP) 6041 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6042 else 6043 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6044 6045 /* Free the RX lists. */ 6046 bge_free_rx_ring_std(sc); 6047 6048 /* Free jumbo RX list. */ 6049 if (BGE_IS_JUMBO_CAPABLE(sc)) 6050 bge_free_rx_ring_jumbo(sc); 6051 6052 /* Free TX buffers. */ 6053 bge_free_tx_ring(sc); 6054 6055 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6056 6057 /* Clear MAC's link state (PHY may still have link UP). */ 6058 if (bootverbose && sc->bge_link) 6059 if_printf(sc->bge_ifp, "link DOWN\n"); 6060 sc->bge_link = 0; 6061 6062 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 6063 } 6064 6065 /* 6066 * Stop all chip I/O so that the kernel's probe routines don't 6067 * get confused by errant DMAs when rebooting. 6068 */ 6069 static int 6070 bge_shutdown(device_t dev) 6071 { 6072 struct bge_softc *sc; 6073 6074 sc = device_get_softc(dev); 6075 BGE_LOCK(sc); 6076 bge_stop(sc); 6077 BGE_UNLOCK(sc); 6078 6079 return (0); 6080 } 6081 6082 static int 6083 bge_suspend(device_t dev) 6084 { 6085 struct bge_softc *sc; 6086 6087 sc = device_get_softc(dev); 6088 BGE_LOCK(sc); 6089 bge_stop(sc); 6090 BGE_UNLOCK(sc); 6091 6092 return (0); 6093 } 6094 6095 static int 6096 bge_resume(device_t dev) 6097 { 6098 struct bge_softc *sc; 6099 if_t ifp; 6100 6101 sc = device_get_softc(dev); 6102 BGE_LOCK(sc); 6103 ifp = sc->bge_ifp; 6104 if (if_getflags(ifp) & IFF_UP) { 6105 bge_init_locked(sc); 6106 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6107 bge_start_locked(ifp); 6108 } 6109 BGE_UNLOCK(sc); 6110 6111 return (0); 6112 } 6113 6114 static void 6115 bge_link_upd(struct bge_softc *sc) 6116 { 6117 struct mii_data *mii; 6118 uint32_t link, status; 6119 6120 BGE_LOCK_ASSERT(sc); 6121 6122 /* Clear 'pending link event' flag. */ 6123 sc->bge_link_evt = 0; 6124 6125 /* 6126 * Process link state changes. 6127 * Grrr. The link status word in the status block does 6128 * not work correctly on the BCM5700 rev AX and BX chips, 6129 * according to all available information. Hence, we have 6130 * to enable MII interrupts in order to properly obtain 6131 * async link changes. Unfortunately, this also means that 6132 * we have to read the MAC status register to detect link 6133 * changes, thereby adding an additional register access to 6134 * the interrupt handler. 6135 * 6136 * XXX: perhaps link state detection procedure used for 6137 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6138 */ 6139 6140 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6141 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6142 status = CSR_READ_4(sc, BGE_MAC_STS); 6143 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6144 mii = device_get_softc(sc->bge_miibus); 6145 mii_pollstat(mii); 6146 if (!sc->bge_link && 6147 mii->mii_media_status & IFM_ACTIVE && 6148 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6149 sc->bge_link++; 6150 if (bootverbose) 6151 if_printf(sc->bge_ifp, "link UP\n"); 6152 } else if (sc->bge_link && 6153 (!(mii->mii_media_status & IFM_ACTIVE) || 6154 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6155 sc->bge_link = 0; 6156 if (bootverbose) 6157 if_printf(sc->bge_ifp, "link DOWN\n"); 6158 } 6159 6160 /* Clear the interrupt. */ 6161 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6162 BGE_EVTENB_MI_INTERRUPT); 6163 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6164 BRGPHY_MII_ISR); 6165 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6166 BRGPHY_MII_IMR, BRGPHY_INTRS); 6167 } 6168 return; 6169 } 6170 6171 if (sc->bge_flags & BGE_FLAG_TBI) { 6172 status = CSR_READ_4(sc, BGE_MAC_STS); 6173 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6174 if (!sc->bge_link) { 6175 sc->bge_link++; 6176 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6177 BGE_CLRBIT(sc, BGE_MAC_MODE, 6178 BGE_MACMODE_TBI_SEND_CFGS); 6179 DELAY(40); 6180 } 6181 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6182 if (bootverbose) 6183 if_printf(sc->bge_ifp, "link UP\n"); 6184 if_link_state_change(sc->bge_ifp, 6185 LINK_STATE_UP); 6186 } 6187 } else if (sc->bge_link) { 6188 sc->bge_link = 0; 6189 if (bootverbose) 6190 if_printf(sc->bge_ifp, "link DOWN\n"); 6191 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6192 } 6193 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6194 /* 6195 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6196 * in status word always set. Workaround this bug by reading 6197 * PHY link status directly. 6198 */ 6199 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6200 6201 if (link != sc->bge_link || 6202 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6203 mii = device_get_softc(sc->bge_miibus); 6204 mii_pollstat(mii); 6205 if (!sc->bge_link && 6206 mii->mii_media_status & IFM_ACTIVE && 6207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6208 sc->bge_link++; 6209 if (bootverbose) 6210 if_printf(sc->bge_ifp, "link UP\n"); 6211 } else if (sc->bge_link && 6212 (!(mii->mii_media_status & IFM_ACTIVE) || 6213 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6214 sc->bge_link = 0; 6215 if (bootverbose) 6216 if_printf(sc->bge_ifp, "link DOWN\n"); 6217 } 6218 } 6219 } else { 6220 /* 6221 * For controllers that call mii_tick, we have to poll 6222 * link status. 6223 */ 6224 mii = device_get_softc(sc->bge_miibus); 6225 mii_pollstat(mii); 6226 bge_miibus_statchg(sc->bge_dev); 6227 } 6228 6229 /* Disable MAC attention when link is up. */ 6230 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6231 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6232 BGE_MACSTAT_LINK_CHANGED); 6233 } 6234 6235 static void 6236 bge_add_sysctls(struct bge_softc *sc) 6237 { 6238 struct sysctl_ctx_list *ctx; 6239 struct sysctl_oid_list *children; 6240 int unit; 6241 6242 ctx = device_get_sysctl_ctx(sc->bge_dev); 6243 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6244 6245 #ifdef BGE_REGISTER_DEBUG 6246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6247 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6248 bge_sysctl_debug_info, "I", "Debug Information"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6251 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6252 bge_sysctl_reg_read, "I", "MAC Register Read"); 6253 6254 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6255 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6256 bge_sysctl_ape_read, "I", "APE Register Read"); 6257 6258 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6259 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6260 bge_sysctl_mem_read, "I", "Memory Read"); 6261 6262 #endif 6263 6264 unit = device_get_unit(sc->bge_dev); 6265 /* 6266 * A common design characteristic for many Broadcom client controllers 6267 * is that they only support a single outstanding DMA read operation 6268 * on the PCIe bus. This means that it will take twice as long to fetch 6269 * a TX frame that is split into header and payload buffers as it does 6270 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6271 * these controllers, coalescing buffers to reduce the number of memory 6272 * reads is effective way to get maximum performance(about 940Mbps). 6273 * Without collapsing TX buffers the maximum TCP bulk transfer 6274 * performance is about 850Mbps. However forcing coalescing mbufs 6275 * consumes a lot of CPU cycles, so leave it off by default. 6276 */ 6277 sc->bge_forced_collapse = 0; 6278 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6279 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6280 "Number of fragmented TX buffers of a frame allowed before " 6281 "forced collapsing"); 6282 6283 sc->bge_msi = 1; 6284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6285 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 6286 6287 /* 6288 * It seems all Broadcom controllers have a bug that can generate UDP 6289 * datagrams with checksum value 0 when TX UDP checksum offloading is 6290 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6291 * Even though the probability of generating such UDP datagrams is 6292 * low, I don't want to see FreeBSD boxes to inject such datagrams 6293 * into network so disable UDP checksum offloading by default. Users 6294 * still override this behavior by setting a sysctl variable, 6295 * dev.bge.0.forced_udpcsum. 6296 */ 6297 sc->bge_forced_udpcsum = 0; 6298 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6299 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 6300 "Enable UDP checksum offloading even if controller can " 6301 "generate UDP checksum value 0"); 6302 6303 if (BGE_IS_5705_PLUS(sc)) 6304 bge_add_sysctl_stats_regs(sc, ctx, children); 6305 else 6306 bge_add_sysctl_stats(sc, ctx, children); 6307 } 6308 6309 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6310 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \ 6311 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \ 6312 offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc) 6313 6314 static void 6315 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6316 struct sysctl_oid_list *parent) 6317 { 6318 struct sysctl_oid *tree; 6319 struct sysctl_oid_list *children, *schildren; 6320 6321 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 6322 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics"); 6323 schildren = children = SYSCTL_CHILDREN(tree); 6324 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6325 children, COSFramesDroppedDueToFilters, 6326 "FramesDroppedDueToFilters"); 6327 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6328 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6329 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6330 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6331 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6332 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6333 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6334 children, ifInDiscards, "InputDiscards"); 6335 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6336 children, ifInErrors, "InputErrors"); 6337 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6338 children, nicRecvThresholdHit, "RecvThresholdHit"); 6339 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6340 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6341 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6342 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6343 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6344 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6345 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6346 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6347 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6348 children, nicRingStatusUpdate, "RingStatusUpdate"); 6349 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6350 children, nicInterrupts, "Interrupts"); 6351 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6352 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6353 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6354 children, nicSendThresholdHit, "SendThresholdHit"); 6355 6356 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", 6357 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics"); 6358 children = SYSCTL_CHILDREN(tree); 6359 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6360 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6361 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6362 children, rxstats.etherStatsFragments, "Fragments"); 6363 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6364 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6365 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6366 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6367 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6368 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6369 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6370 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6371 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6372 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6373 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6374 children, rxstats.xoffPauseFramesReceived, 6375 "xoffPauseFramesReceived"); 6376 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6377 children, rxstats.macControlFramesReceived, 6378 "ControlFramesReceived"); 6379 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6380 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6381 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6382 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6383 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6384 children, rxstats.etherStatsJabbers, "Jabbers"); 6385 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6386 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6387 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6388 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6390 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6391 6392 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", 6393 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics"); 6394 children = SYSCTL_CHILDREN(tree); 6395 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6396 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6397 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6398 children, txstats.etherStatsCollisions, "Collisions"); 6399 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6400 children, txstats.outXonSent, "XonSent"); 6401 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6402 children, txstats.outXoffSent, "XoffSent"); 6403 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6404 children, txstats.flowControlDone, "flowControlDone"); 6405 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6406 children, txstats.dot3StatsInternalMacTransmitErrors, 6407 "InternalMacTransmitErrors"); 6408 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6409 children, txstats.dot3StatsSingleCollisionFrames, 6410 "SingleCollisionFrames"); 6411 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6412 children, txstats.dot3StatsMultipleCollisionFrames, 6413 "MultipleCollisionFrames"); 6414 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6415 children, txstats.dot3StatsDeferredTransmissions, 6416 "DeferredTransmissions"); 6417 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6418 children, txstats.dot3StatsExcessiveCollisions, 6419 "ExcessiveCollisions"); 6420 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6421 children, txstats.dot3StatsLateCollisions, 6422 "LateCollisions"); 6423 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6424 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6426 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6427 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6428 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6429 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6430 children, txstats.dot3StatsCarrierSenseErrors, 6431 "CarrierSenseErrors"); 6432 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6433 children, txstats.ifOutDiscards, "Discards"); 6434 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6435 children, txstats.ifOutErrors, "Errors"); 6436 } 6437 6438 #undef BGE_SYSCTL_STAT 6439 6440 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6441 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6442 6443 static void 6444 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6445 struct sysctl_oid_list *parent) 6446 { 6447 struct sysctl_oid *tree; 6448 struct sysctl_oid_list *child, *schild; 6449 struct bge_mac_stats *stats; 6450 6451 stats = &sc->bge_mac_stats; 6452 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 6453 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics"); 6454 schild = child = SYSCTL_CHILDREN(tree); 6455 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6456 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6457 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6458 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6459 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6460 &stats->DmaWriteHighPriQueueFull, 6461 "NIC DMA Write High Priority Queue Full"); 6462 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6463 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6465 &stats->InputDiscards, "Discarded Input Frames"); 6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6467 &stats->InputErrors, "Input Errors"); 6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6469 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6470 6471 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 6472 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics"); 6473 child = SYSCTL_CHILDREN(tree); 6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6475 &stats->ifHCInOctets, "Inbound Octets"); 6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6477 &stats->etherStatsFragments, "Fragments"); 6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6479 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6481 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6483 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6485 &stats->dot3StatsFCSErrors, "FCS Errors"); 6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6487 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6489 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6491 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6493 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6495 &stats->xoffStateEntered, "XOFF State Entered"); 6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6497 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6499 &stats->etherStatsJabbers, "Jabbers"); 6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6501 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6502 6503 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 6504 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics"); 6505 child = SYSCTL_CHILDREN(tree); 6506 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6507 &stats->ifHCOutOctets, "Outbound Octets"); 6508 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6509 &stats->etherStatsCollisions, "TX Collisions"); 6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6511 &stats->outXonSent, "XON Sent"); 6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6513 &stats->outXoffSent, "XOFF Sent"); 6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6515 &stats->dot3StatsInternalMacTransmitErrors, 6516 "Internal MAC TX Errors"); 6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6518 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6520 &stats->dot3StatsMultipleCollisionFrames, 6521 "Multiple Collision Frames"); 6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6523 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6525 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6527 &stats->dot3StatsLateCollisions, "Late Collisions"); 6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6529 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6531 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6533 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6534 } 6535 6536 #undef BGE_SYSCTL_STAT_ADD64 6537 6538 static int 6539 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6540 { 6541 struct bge_softc *sc; 6542 uint32_t result; 6543 int offset; 6544 6545 sc = (struct bge_softc *)arg1; 6546 offset = arg2; 6547 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6548 offsetof(bge_hostaddr, bge_addr_lo)); 6549 return (sysctl_handle_int(oidp, &result, 0, req)); 6550 } 6551 6552 #ifdef BGE_REGISTER_DEBUG 6553 static int 6554 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6555 { 6556 struct bge_softc *sc; 6557 uint16_t *sbdata; 6558 int error, result, sbsz; 6559 int i, j; 6560 6561 result = -1; 6562 error = sysctl_handle_int(oidp, &result, 0, req); 6563 if (error || (req->newptr == NULL)) 6564 return (error); 6565 6566 if (result == 1) { 6567 sc = (struct bge_softc *)arg1; 6568 6569 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6570 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6571 sbsz = BGE_STATUS_BLK_SZ; 6572 else 6573 sbsz = 32; 6574 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6575 printf("Status Block:\n"); 6576 BGE_LOCK(sc); 6577 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6578 sc->bge_cdata.bge_status_map, 6579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6580 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6581 printf("%06x:", i); 6582 for (j = 0; j < 8; j++) 6583 printf(" %04x", sbdata[i++]); 6584 printf("\n"); 6585 } 6586 6587 printf("Registers:\n"); 6588 for (i = 0x800; i < 0xA00; ) { 6589 printf("%06x:", i); 6590 for (j = 0; j < 8; j++) { 6591 printf(" %08x", CSR_READ_4(sc, i)); 6592 i += 4; 6593 } 6594 printf("\n"); 6595 } 6596 BGE_UNLOCK(sc); 6597 6598 printf("Hardware Flags:\n"); 6599 if (BGE_IS_5717_PLUS(sc)) 6600 printf(" - 5717 Plus\n"); 6601 if (BGE_IS_5755_PLUS(sc)) 6602 printf(" - 5755 Plus\n"); 6603 if (BGE_IS_575X_PLUS(sc)) 6604 printf(" - 575X Plus\n"); 6605 if (BGE_IS_5705_PLUS(sc)) 6606 printf(" - 5705 Plus\n"); 6607 if (BGE_IS_5714_FAMILY(sc)) 6608 printf(" - 5714 Family\n"); 6609 if (BGE_IS_5700_FAMILY(sc)) 6610 printf(" - 5700 Family\n"); 6611 if (sc->bge_flags & BGE_FLAG_JUMBO) 6612 printf(" - Supports Jumbo Frames\n"); 6613 if (sc->bge_flags & BGE_FLAG_PCIX) 6614 printf(" - PCI-X Bus\n"); 6615 if (sc->bge_flags & BGE_FLAG_PCIE) 6616 printf(" - PCI Express Bus\n"); 6617 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6618 printf(" - No 3 LEDs\n"); 6619 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6620 printf(" - RX Alignment Bug\n"); 6621 } 6622 6623 return (error); 6624 } 6625 6626 static int 6627 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6628 { 6629 struct bge_softc *sc; 6630 int error; 6631 uint16_t result; 6632 uint32_t val; 6633 6634 result = -1; 6635 error = sysctl_handle_int(oidp, &result, 0, req); 6636 if (error || (req->newptr == NULL)) 6637 return (error); 6638 6639 if (result < 0x8000) { 6640 sc = (struct bge_softc *)arg1; 6641 val = CSR_READ_4(sc, result); 6642 printf("reg 0x%06X = 0x%08X\n", result, val); 6643 } 6644 6645 return (error); 6646 } 6647 6648 static int 6649 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6650 { 6651 struct bge_softc *sc; 6652 int error; 6653 uint16_t result; 6654 uint32_t val; 6655 6656 result = -1; 6657 error = sysctl_handle_int(oidp, &result, 0, req); 6658 if (error || (req->newptr == NULL)) 6659 return (error); 6660 6661 if (result < 0x8000) { 6662 sc = (struct bge_softc *)arg1; 6663 val = APE_READ_4(sc, result); 6664 printf("reg 0x%06X = 0x%08X\n", result, val); 6665 } 6666 6667 return (error); 6668 } 6669 6670 static int 6671 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6672 { 6673 struct bge_softc *sc; 6674 int error; 6675 uint16_t result; 6676 uint32_t val; 6677 6678 result = -1; 6679 error = sysctl_handle_int(oidp, &result, 0, req); 6680 if (error || (req->newptr == NULL)) 6681 return (error); 6682 6683 if (result < 0x8000) { 6684 sc = (struct bge_softc *)arg1; 6685 val = bge_readmem_ind(sc, result); 6686 printf("mem 0x%06X = 0x%08X\n", result, val); 6687 } 6688 6689 return (error); 6690 } 6691 #endif 6692 6693 static int 6694 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6695 { 6696 return (1); 6697 } 6698 6699 static int 6700 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6701 { 6702 uint32_t mac_addr; 6703 6704 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6705 if ((mac_addr >> 16) == 0x484b) { 6706 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6707 ether_addr[1] = (uint8_t)mac_addr; 6708 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6709 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6710 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6711 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6712 ether_addr[5] = (uint8_t)mac_addr; 6713 return (0); 6714 } 6715 return (1); 6716 } 6717 6718 static int 6719 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6720 { 6721 int mac_offset = BGE_EE_MAC_OFFSET; 6722 6723 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6724 mac_offset = BGE_EE_MAC_OFFSET_5906; 6725 6726 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6727 ETHER_ADDR_LEN)); 6728 } 6729 6730 static int 6731 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6732 { 6733 6734 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6735 return (1); 6736 6737 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6738 ETHER_ADDR_LEN)); 6739 } 6740 6741 static int 6742 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6743 { 6744 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6745 /* NOTE: Order is critical */ 6746 bge_get_eaddr_fw, 6747 bge_get_eaddr_mem, 6748 bge_get_eaddr_nvram, 6749 bge_get_eaddr_eeprom, 6750 NULL 6751 }; 6752 const bge_eaddr_fcn_t *func; 6753 6754 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6755 if ((*func)(sc, eaddr) == 0) 6756 break; 6757 } 6758 return (*func == NULL ? ENXIO : 0); 6759 } 6760 6761 static uint64_t 6762 bge_get_counter(if_t ifp, ift_counter cnt) 6763 { 6764 struct bge_softc *sc; 6765 struct bge_mac_stats *stats; 6766 6767 sc = if_getsoftc(ifp); 6768 if (!BGE_IS_5705_PLUS(sc)) 6769 return (if_get_counter_default(ifp, cnt)); 6770 stats = &sc->bge_mac_stats; 6771 6772 switch (cnt) { 6773 case IFCOUNTER_IERRORS: 6774 return (stats->NoMoreRxBDs + stats->InputDiscards + 6775 stats->InputErrors); 6776 case IFCOUNTER_COLLISIONS: 6777 return (stats->etherStatsCollisions); 6778 default: 6779 return (if_get_counter_default(ifp, cnt)); 6780 } 6781 } 6782 6783 #ifdef DEBUGNET 6784 static void 6785 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6786 { 6787 struct bge_softc *sc; 6788 6789 sc = if_getsoftc(ifp); 6790 BGE_LOCK(sc); 6791 *nrxr = sc->bge_return_ring_cnt; 6792 *ncl = DEBUGNET_MAX_IN_FLIGHT; 6793 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 && 6794 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 6795 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) 6796 *clsize = MJUM9BYTES; 6797 else 6798 *clsize = MCLBYTES; 6799 BGE_UNLOCK(sc); 6800 } 6801 6802 static void 6803 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 6804 { 6805 } 6806 6807 static int 6808 bge_debugnet_transmit(if_t ifp, struct mbuf *m) 6809 { 6810 struct bge_softc *sc; 6811 uint32_t prodidx; 6812 int error; 6813 6814 sc = if_getsoftc(ifp); 6815 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6816 IFF_DRV_RUNNING) 6817 return (1); 6818 6819 prodidx = sc->bge_tx_prodidx; 6820 error = bge_encap(sc, &m, &prodidx); 6821 if (error == 0) 6822 bge_start_tx(sc, prodidx); 6823 return (error); 6824 } 6825 6826 static int 6827 bge_debugnet_poll(if_t ifp, int count) 6828 { 6829 struct bge_softc *sc; 6830 uint32_t rx_prod, tx_cons; 6831 6832 sc = if_getsoftc(ifp); 6833 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6834 IFF_DRV_RUNNING) 6835 return (1); 6836 6837 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6838 sc->bge_cdata.bge_status_map, 6839 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6840 6841 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 6842 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 6843 6844 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6845 sc->bge_cdata.bge_status_map, 6846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6847 6848 (void)bge_rxeof(sc, rx_prod, 0); 6849 bge_txeof(sc, tx_cons); 6850 return (0); 6851 } 6852 #endif /* DEBUGNET */ 6853