1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_var.h> 87 #include <net/if_arp.h> 88 #include <net/ethernet.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #include <net/bpf.h> 93 94 #include <net/if_types.h> 95 #include <net/if_vlan_var.h> 96 97 #include <netinet/in_systm.h> 98 #include <netinet/in.h> 99 #include <netinet/ip.h> 100 #include <netinet/tcp.h> 101 102 #include <machine/bus.h> 103 #include <machine/resource.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include "miidevs.h" 110 #include <dev/mii/brgphyreg.h> 111 112 #ifdef __sparc64__ 113 #include <dev/ofw/ofw_bus.h> 114 #include <dev/ofw/openfirm.h> 115 #include <machine/ofw_machdep.h> 116 #include <machine/ver.h> 117 #endif 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 122 #include <dev/bge/if_bgereg.h> 123 124 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 126 127 MODULE_DEPEND(bge, pci, 1, 1, 1); 128 MODULE_DEPEND(bge, ether, 1, 1, 1); 129 MODULE_DEPEND(bge, miibus, 1, 1, 1); 130 131 /* "device miibus" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. Note: the 136 * spec seems to indicate that the hardware still has Alteon's vendor 137 * ID burned into it, though it will always be overriden by the vendor 138 * ID in the EEPROM. Just to be safe, we cover all possibilities. 139 */ 140 static const struct bge_type { 141 uint16_t bge_vid; 142 uint16_t bge_did; 143 } bge_devs[] = { 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 145 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 146 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 149 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 150 151 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 152 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 238 239 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 240 241 { TC_VENDORID, TC_DEVICEID_3C996 }, 242 243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 244 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 245 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 246 247 { 0, 0 } 248 }; 249 250 static const struct bge_vendor { 251 uint16_t v_id; 252 const char *v_name; 253 } bge_vendors[] = { 254 { ALTEON_VENDORID, "Alteon" }, 255 { ALTIMA_VENDORID, "Altima" }, 256 { APPLE_VENDORID, "Apple" }, 257 { BCOM_VENDORID, "Broadcom" }, 258 { SK_VENDORID, "SysKonnect" }, 259 { TC_VENDORID, "3Com" }, 260 { FJTSU_VENDORID, "Fujitsu" }, 261 262 { 0, NULL } 263 }; 264 265 static const struct bge_revision { 266 uint32_t br_chipid; 267 const char *br_name; 268 } bge_revisions[] = { 269 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 270 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 271 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 272 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 273 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 274 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 275 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 276 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 277 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 278 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 279 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 280 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 281 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 282 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 283 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 284 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 285 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 286 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 287 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 288 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 289 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 290 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 291 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 292 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 293 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 294 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 295 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 296 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 297 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 298 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 299 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 300 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 301 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 302 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 303 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 304 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 305 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 306 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 307 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 308 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 309 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 310 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 311 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 312 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 313 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 314 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 315 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 316 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 317 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 318 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 319 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 320 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 321 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 322 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 323 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 324 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 325 /* 5754 and 5787 share the same ASIC ID */ 326 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 327 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 328 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 329 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 330 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 331 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 332 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 333 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 334 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 335 336 { 0, NULL } 337 }; 338 339 /* 340 * Some defaults for major revisions, so that newer steppings 341 * that we don't know about have a shot at working. 342 */ 343 static const struct bge_revision bge_majorrevs[] = { 344 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 345 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 346 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 347 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 348 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 349 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 350 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 351 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 352 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 353 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 354 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 355 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 356 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 357 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 358 /* 5754 and 5787 share the same ASIC ID */ 359 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 360 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 361 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 362 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 363 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 364 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 365 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 366 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 367 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 368 369 { 0, NULL } 370 }; 371 372 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 373 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 374 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 375 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 376 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 377 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 378 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 379 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 380 381 static uint32_t bge_chipid(device_t); 382 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 383 static const struct bge_revision * bge_lookup_rev(uint32_t); 384 385 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 386 387 static int bge_probe(device_t); 388 static int bge_attach(device_t); 389 static int bge_detach(device_t); 390 static int bge_suspend(device_t); 391 static int bge_resume(device_t); 392 static void bge_release_resources(struct bge_softc *); 393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 394 static int bge_dma_alloc(struct bge_softc *); 395 static void bge_dma_free(struct bge_softc *); 396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 397 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 398 399 static void bge_devinfo(struct bge_softc *); 400 static int bge_mbox_reorder(struct bge_softc *); 401 402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 407 408 static void bge_txeof(struct bge_softc *, uint16_t); 409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 410 static int bge_rxeof(struct bge_softc *, uint16_t, int); 411 412 static void bge_asf_driver_up (struct bge_softc *); 413 static void bge_tick(void *); 414 static void bge_stats_clear_regs(struct bge_softc *); 415 static void bge_stats_update(struct bge_softc *); 416 static void bge_stats_update_regs(struct bge_softc *); 417 static struct mbuf *bge_check_short_dma(struct mbuf *); 418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 419 uint16_t *, uint16_t *); 420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 421 422 static void bge_intr(void *); 423 static int bge_msi_intr(void *); 424 static void bge_intr_task(void *, int); 425 static void bge_start_locked(if_t); 426 static void bge_start(if_t); 427 static int bge_ioctl(if_t, u_long, caddr_t); 428 static void bge_init_locked(struct bge_softc *); 429 static void bge_init(void *); 430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 431 static void bge_stop(struct bge_softc *); 432 static void bge_watchdog(struct bge_softc *); 433 static int bge_shutdown(device_t); 434 static int bge_ifmedia_upd_locked(if_t); 435 static int bge_ifmedia_upd(if_t); 436 static void bge_ifmedia_sts(if_t, struct ifmediareq *); 437 438 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 439 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 440 441 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 442 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 443 444 static void bge_setpromisc(struct bge_softc *); 445 static void bge_setmulti(struct bge_softc *); 446 static void bge_setvlan(struct bge_softc *); 447 448 static __inline void bge_rxreuse_std(struct bge_softc *, int); 449 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 450 static int bge_newbuf_std(struct bge_softc *, int); 451 static int bge_newbuf_jumbo(struct bge_softc *, int); 452 static int bge_init_rx_ring_std(struct bge_softc *); 453 static void bge_free_rx_ring_std(struct bge_softc *); 454 static int bge_init_rx_ring_jumbo(struct bge_softc *); 455 static void bge_free_rx_ring_jumbo(struct bge_softc *); 456 static void bge_free_tx_ring(struct bge_softc *); 457 static int bge_init_tx_ring(struct bge_softc *); 458 459 static int bge_chipinit(struct bge_softc *); 460 static int bge_blockinit(struct bge_softc *); 461 static uint32_t bge_dma_swap_options(struct bge_softc *); 462 463 static int bge_has_eaddr(struct bge_softc *); 464 static uint32_t bge_readmem_ind(struct bge_softc *, int); 465 static void bge_writemem_ind(struct bge_softc *, int, int); 466 static void bge_writembx(struct bge_softc *, int, int); 467 #ifdef notdef 468 static uint32_t bge_readreg_ind(struct bge_softc *, int); 469 #endif 470 static void bge_writemem_direct(struct bge_softc *, int, int); 471 static void bge_writereg_ind(struct bge_softc *, int, int); 472 473 static int bge_miibus_readreg(device_t, int, int); 474 static int bge_miibus_writereg(device_t, int, int, int); 475 static void bge_miibus_statchg(device_t); 476 #ifdef DEVICE_POLLING 477 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 478 #endif 479 480 #define BGE_RESET_SHUTDOWN 0 481 #define BGE_RESET_START 1 482 #define BGE_RESET_SUSPEND 2 483 static void bge_sig_post_reset(struct bge_softc *, int); 484 static void bge_sig_legacy(struct bge_softc *, int); 485 static void bge_sig_pre_reset(struct bge_softc *, int); 486 static void bge_stop_fw(struct bge_softc *); 487 static int bge_reset(struct bge_softc *); 488 static void bge_link_upd(struct bge_softc *); 489 490 static void bge_ape_lock_init(struct bge_softc *); 491 static void bge_ape_read_fw_ver(struct bge_softc *); 492 static int bge_ape_lock(struct bge_softc *, int); 493 static void bge_ape_unlock(struct bge_softc *, int); 494 static void bge_ape_send_event(struct bge_softc *, uint32_t); 495 static void bge_ape_driver_state_change(struct bge_softc *, int); 496 497 /* 498 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 499 * leak information to untrusted users. It is also known to cause alignment 500 * traps on certain architectures. 501 */ 502 #ifdef BGE_REGISTER_DEBUG 503 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 504 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 505 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 506 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 507 #endif 508 static void bge_add_sysctls(struct bge_softc *); 509 static void bge_add_sysctl_stats_regs(struct bge_softc *, 510 struct sysctl_ctx_list *, struct sysctl_oid_list *); 511 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 512 struct sysctl_oid_list *); 513 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 514 515 static device_method_t bge_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_probe, bge_probe), 518 DEVMETHOD(device_attach, bge_attach), 519 DEVMETHOD(device_detach, bge_detach), 520 DEVMETHOD(device_shutdown, bge_shutdown), 521 DEVMETHOD(device_suspend, bge_suspend), 522 DEVMETHOD(device_resume, bge_resume), 523 524 /* MII interface */ 525 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 526 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 527 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 528 529 DEVMETHOD_END 530 }; 531 532 static driver_t bge_driver = { 533 "bge", 534 bge_methods, 535 sizeof(struct bge_softc) 536 }; 537 538 static devclass_t bge_devclass; 539 540 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 541 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 542 543 static int bge_allow_asf = 1; 544 545 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 546 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 547 "Allow ASF mode if available"); 548 549 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 550 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 551 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 552 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 553 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 554 555 static int 556 bge_has_eaddr(struct bge_softc *sc) 557 { 558 #ifdef __sparc64__ 559 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 560 device_t dev; 561 uint32_t subvendor; 562 563 dev = sc->bge_dev; 564 565 /* 566 * The on-board BGEs found in sun4u machines aren't fitted with 567 * an EEPROM which means that we have to obtain the MAC address 568 * via OFW and that some tests will always fail. We distinguish 569 * such BGEs by the subvendor ID, which also has to be obtained 570 * from OFW instead of the PCI configuration space as the latter 571 * indicates Broadcom as the subvendor of the netboot interface. 572 * For early Blade 1500 and 2500 we even have to check the OFW 573 * device path as the subvendor ID always defaults to Broadcom 574 * there. 575 */ 576 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 577 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 578 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 579 return (0); 580 memset(buf, 0, sizeof(buf)); 581 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 582 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 583 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 584 return (0); 585 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 586 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 587 return (0); 588 } 589 #endif 590 return (1); 591 } 592 593 static uint32_t 594 bge_readmem_ind(struct bge_softc *sc, int off) 595 { 596 device_t dev; 597 uint32_t val; 598 599 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 600 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 601 return (0); 602 603 dev = sc->bge_dev; 604 605 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 606 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 607 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 608 return (val); 609 } 610 611 static void 612 bge_writemem_ind(struct bge_softc *sc, int off, int val) 613 { 614 device_t dev; 615 616 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 617 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 618 return; 619 620 dev = sc->bge_dev; 621 622 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 623 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 624 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 625 } 626 627 #ifdef notdef 628 static uint32_t 629 bge_readreg_ind(struct bge_softc *sc, int off) 630 { 631 device_t dev; 632 633 dev = sc->bge_dev; 634 635 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 636 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 637 } 638 #endif 639 640 static void 641 bge_writereg_ind(struct bge_softc *sc, int off, int val) 642 { 643 device_t dev; 644 645 dev = sc->bge_dev; 646 647 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 648 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 649 } 650 651 static void 652 bge_writemem_direct(struct bge_softc *sc, int off, int val) 653 { 654 CSR_WRITE_4(sc, off, val); 655 } 656 657 static void 658 bge_writembx(struct bge_softc *sc, int off, int val) 659 { 660 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 661 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 662 663 CSR_WRITE_4(sc, off, val); 664 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 665 CSR_READ_4(sc, off); 666 } 667 668 /* 669 * Clear all stale locks and select the lock for this driver instance. 670 */ 671 static void 672 bge_ape_lock_init(struct bge_softc *sc) 673 { 674 uint32_t bit, regbase; 675 int i; 676 677 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 678 regbase = BGE_APE_LOCK_GRANT; 679 else 680 regbase = BGE_APE_PER_LOCK_GRANT; 681 682 /* Clear any stale locks. */ 683 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 684 switch (i) { 685 case BGE_APE_LOCK_PHY0: 686 case BGE_APE_LOCK_PHY1: 687 case BGE_APE_LOCK_PHY2: 688 case BGE_APE_LOCK_PHY3: 689 bit = BGE_APE_LOCK_GRANT_DRIVER0; 690 break; 691 default: 692 if (sc->bge_func_addr == 0) 693 bit = BGE_APE_LOCK_GRANT_DRIVER0; 694 else 695 bit = (1 << sc->bge_func_addr); 696 } 697 APE_WRITE_4(sc, regbase + 4 * i, bit); 698 } 699 700 /* Select the PHY lock based on the device's function number. */ 701 switch (sc->bge_func_addr) { 702 case 0: 703 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 704 break; 705 case 1: 706 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 707 break; 708 case 2: 709 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 710 break; 711 case 3: 712 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 713 break; 714 default: 715 device_printf(sc->bge_dev, 716 "PHY lock not supported on this function\n"); 717 } 718 } 719 720 /* 721 * Check for APE firmware, set flags, and print version info. 722 */ 723 static void 724 bge_ape_read_fw_ver(struct bge_softc *sc) 725 { 726 const char *fwtype; 727 uint32_t apedata, features; 728 729 /* Check for a valid APE signature in shared memory. */ 730 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 731 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 732 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 733 return; 734 } 735 736 /* Check if APE firmware is running. */ 737 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 738 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 739 device_printf(sc->bge_dev, "APE signature found " 740 "but FW status not ready! 0x%08x\n", apedata); 741 return; 742 } 743 744 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 745 746 /* Fetch the APE firwmare type and version. */ 747 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 748 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 749 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 750 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 751 fwtype = "NCSI"; 752 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 753 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 754 fwtype = "DASH"; 755 } else 756 fwtype = "UNKN"; 757 758 /* Print the APE firmware version. */ 759 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 760 fwtype, 761 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 762 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 763 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 764 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 765 } 766 767 static int 768 bge_ape_lock(struct bge_softc *sc, int locknum) 769 { 770 uint32_t bit, gnt, req, status; 771 int i, off; 772 773 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 774 return (0); 775 776 /* Lock request/grant registers have different bases. */ 777 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 778 req = BGE_APE_LOCK_REQ; 779 gnt = BGE_APE_LOCK_GRANT; 780 } else { 781 req = BGE_APE_PER_LOCK_REQ; 782 gnt = BGE_APE_PER_LOCK_GRANT; 783 } 784 785 off = 4 * locknum; 786 787 switch (locknum) { 788 case BGE_APE_LOCK_GPIO: 789 /* Lock required when using GPIO. */ 790 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 791 return (0); 792 if (sc->bge_func_addr == 0) 793 bit = BGE_APE_LOCK_REQ_DRIVER0; 794 else 795 bit = (1 << sc->bge_func_addr); 796 break; 797 case BGE_APE_LOCK_GRC: 798 /* Lock required to reset the device. */ 799 if (sc->bge_func_addr == 0) 800 bit = BGE_APE_LOCK_REQ_DRIVER0; 801 else 802 bit = (1 << sc->bge_func_addr); 803 break; 804 case BGE_APE_LOCK_MEM: 805 /* Lock required when accessing certain APE memory. */ 806 if (sc->bge_func_addr == 0) 807 bit = BGE_APE_LOCK_REQ_DRIVER0; 808 else 809 bit = (1 << sc->bge_func_addr); 810 break; 811 case BGE_APE_LOCK_PHY0: 812 case BGE_APE_LOCK_PHY1: 813 case BGE_APE_LOCK_PHY2: 814 case BGE_APE_LOCK_PHY3: 815 /* Lock required when accessing PHYs. */ 816 bit = BGE_APE_LOCK_REQ_DRIVER0; 817 break; 818 default: 819 return (EINVAL); 820 } 821 822 /* Request a lock. */ 823 APE_WRITE_4(sc, req + off, bit); 824 825 /* Wait up to 1 second to acquire lock. */ 826 for (i = 0; i < 20000; i++) { 827 status = APE_READ_4(sc, gnt + off); 828 if (status == bit) 829 break; 830 DELAY(50); 831 } 832 833 /* Handle any errors. */ 834 if (status != bit) { 835 device_printf(sc->bge_dev, "APE lock %d request failed! " 836 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 837 locknum, req + off, bit & 0xFFFF, gnt + off, 838 status & 0xFFFF); 839 /* Revoke the lock request. */ 840 APE_WRITE_4(sc, gnt + off, bit); 841 return (EBUSY); 842 } 843 844 return (0); 845 } 846 847 static void 848 bge_ape_unlock(struct bge_softc *sc, int locknum) 849 { 850 uint32_t bit, gnt; 851 int off; 852 853 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 854 return; 855 856 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 857 gnt = BGE_APE_LOCK_GRANT; 858 else 859 gnt = BGE_APE_PER_LOCK_GRANT; 860 861 off = 4 * locknum; 862 863 switch (locknum) { 864 case BGE_APE_LOCK_GPIO: 865 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 866 return; 867 if (sc->bge_func_addr == 0) 868 bit = BGE_APE_LOCK_GRANT_DRIVER0; 869 else 870 bit = (1 << sc->bge_func_addr); 871 break; 872 case BGE_APE_LOCK_GRC: 873 if (sc->bge_func_addr == 0) 874 bit = BGE_APE_LOCK_GRANT_DRIVER0; 875 else 876 bit = (1 << sc->bge_func_addr); 877 break; 878 case BGE_APE_LOCK_MEM: 879 if (sc->bge_func_addr == 0) 880 bit = BGE_APE_LOCK_GRANT_DRIVER0; 881 else 882 bit = (1 << sc->bge_func_addr); 883 break; 884 case BGE_APE_LOCK_PHY0: 885 case BGE_APE_LOCK_PHY1: 886 case BGE_APE_LOCK_PHY2: 887 case BGE_APE_LOCK_PHY3: 888 bit = BGE_APE_LOCK_GRANT_DRIVER0; 889 break; 890 default: 891 return; 892 } 893 894 APE_WRITE_4(sc, gnt + off, bit); 895 } 896 897 /* 898 * Send an event to the APE firmware. 899 */ 900 static void 901 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 902 { 903 uint32_t apedata; 904 int i; 905 906 /* NCSI does not support APE events. */ 907 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 908 return; 909 910 /* Wait up to 1ms for APE to service previous event. */ 911 for (i = 10; i > 0; i--) { 912 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 913 break; 914 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 915 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 916 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 917 BGE_APE_EVENT_STATUS_EVENT_PENDING); 918 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 919 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 920 break; 921 } 922 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 923 DELAY(100); 924 } 925 if (i == 0) 926 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 927 event); 928 } 929 930 static void 931 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 932 { 933 uint32_t apedata, event; 934 935 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 936 return; 937 938 switch (kind) { 939 case BGE_RESET_START: 940 /* If this is the first load, clear the load counter. */ 941 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 942 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 943 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 944 else { 945 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 946 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 947 } 948 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 949 BGE_APE_HOST_SEG_SIG_MAGIC); 950 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 951 BGE_APE_HOST_SEG_LEN_MAGIC); 952 953 /* Add some version info if bge(4) supports it. */ 954 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 955 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 956 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 957 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 958 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 959 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 960 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 961 BGE_APE_HOST_DRVR_STATE_START); 962 event = BGE_APE_EVENT_STATUS_STATE_START; 963 break; 964 case BGE_RESET_SHUTDOWN: 965 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 966 BGE_APE_HOST_DRVR_STATE_UNLOAD); 967 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 968 break; 969 case BGE_RESET_SUSPEND: 970 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 971 break; 972 default: 973 return; 974 } 975 976 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 977 BGE_APE_EVENT_STATUS_STATE_CHNGE); 978 } 979 980 /* 981 * Map a single buffer address. 982 */ 983 984 static void 985 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986 { 987 struct bge_dmamap_arg *ctx; 988 989 if (error) 990 return; 991 992 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 993 994 ctx = arg; 995 ctx->bge_busaddr = segs->ds_addr; 996 } 997 998 static uint8_t 999 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1000 { 1001 uint32_t access, byte = 0; 1002 int i; 1003 1004 /* Lock. */ 1005 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1006 for (i = 0; i < 8000; i++) { 1007 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1008 break; 1009 DELAY(20); 1010 } 1011 if (i == 8000) 1012 return (1); 1013 1014 /* Enable access. */ 1015 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1016 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1017 1018 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1019 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1020 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1021 DELAY(10); 1022 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1023 DELAY(10); 1024 break; 1025 } 1026 } 1027 1028 if (i == BGE_TIMEOUT * 10) { 1029 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1030 return (1); 1031 } 1032 1033 /* Get result. */ 1034 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1035 1036 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1037 1038 /* Disable access. */ 1039 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1040 1041 /* Unlock. */ 1042 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1043 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1044 1045 return (0); 1046 } 1047 1048 /* 1049 * Read a sequence of bytes from NVRAM. 1050 */ 1051 static int 1052 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1053 { 1054 int err = 0, i; 1055 uint8_t byte = 0; 1056 1057 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1058 return (1); 1059 1060 for (i = 0; i < cnt; i++) { 1061 err = bge_nvram_getbyte(sc, off + i, &byte); 1062 if (err) 1063 break; 1064 *(dest + i) = byte; 1065 } 1066 1067 return (err ? 1 : 0); 1068 } 1069 1070 /* 1071 * Read a byte of data stored in the EEPROM at address 'addr.' The 1072 * BCM570x supports both the traditional bitbang interface and an 1073 * auto access interface for reading the EEPROM. We use the auto 1074 * access method. 1075 */ 1076 static uint8_t 1077 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1078 { 1079 int i; 1080 uint32_t byte = 0; 1081 1082 /* 1083 * Enable use of auto EEPROM access so we can avoid 1084 * having to use the bitbang method. 1085 */ 1086 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1087 1088 /* Reset the EEPROM, load the clock period. */ 1089 CSR_WRITE_4(sc, BGE_EE_ADDR, 1090 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1091 DELAY(20); 1092 1093 /* Issue the read EEPROM command. */ 1094 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1095 1096 /* Wait for completion */ 1097 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1098 DELAY(10); 1099 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1100 break; 1101 } 1102 1103 if (i == BGE_TIMEOUT * 10) { 1104 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1105 return (1); 1106 } 1107 1108 /* Get result. */ 1109 byte = CSR_READ_4(sc, BGE_EE_DATA); 1110 1111 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1112 1113 return (0); 1114 } 1115 1116 /* 1117 * Read a sequence of bytes from the EEPROM. 1118 */ 1119 static int 1120 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1121 { 1122 int i, error = 0; 1123 uint8_t byte = 0; 1124 1125 for (i = 0; i < cnt; i++) { 1126 error = bge_eeprom_getbyte(sc, off + i, &byte); 1127 if (error) 1128 break; 1129 *(dest + i) = byte; 1130 } 1131 1132 return (error ? 1 : 0); 1133 } 1134 1135 static int 1136 bge_miibus_readreg(device_t dev, int phy, int reg) 1137 { 1138 struct bge_softc *sc; 1139 uint32_t val; 1140 int i; 1141 1142 sc = device_get_softc(dev); 1143 1144 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1145 return (0); 1146 1147 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1148 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1149 CSR_WRITE_4(sc, BGE_MI_MODE, 1150 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1151 DELAY(80); 1152 } 1153 1154 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1155 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1156 1157 /* Poll for the PHY register access to complete. */ 1158 for (i = 0; i < BGE_TIMEOUT; i++) { 1159 DELAY(10); 1160 val = CSR_READ_4(sc, BGE_MI_COMM); 1161 if ((val & BGE_MICOMM_BUSY) == 0) { 1162 DELAY(5); 1163 val = CSR_READ_4(sc, BGE_MI_COMM); 1164 break; 1165 } 1166 } 1167 1168 if (i == BGE_TIMEOUT) { 1169 device_printf(sc->bge_dev, 1170 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1171 phy, reg, val); 1172 val = 0; 1173 } 1174 1175 /* Restore the autopoll bit if necessary. */ 1176 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1177 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1178 DELAY(80); 1179 } 1180 1181 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1182 1183 if (val & BGE_MICOMM_READFAIL) 1184 return (0); 1185 1186 return (val & 0xFFFF); 1187 } 1188 1189 static int 1190 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1191 { 1192 struct bge_softc *sc; 1193 int i; 1194 1195 sc = device_get_softc(dev); 1196 1197 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1198 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1199 return (0); 1200 1201 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1202 return (0); 1203 1204 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1205 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1206 CSR_WRITE_4(sc, BGE_MI_MODE, 1207 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1208 DELAY(80); 1209 } 1210 1211 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1212 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1213 1214 for (i = 0; i < BGE_TIMEOUT; i++) { 1215 DELAY(10); 1216 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1217 DELAY(5); 1218 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1219 break; 1220 } 1221 } 1222 1223 /* Restore the autopoll bit if necessary. */ 1224 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1225 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1226 DELAY(80); 1227 } 1228 1229 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1230 1231 if (i == BGE_TIMEOUT) 1232 device_printf(sc->bge_dev, 1233 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1234 phy, reg, val); 1235 1236 return (0); 1237 } 1238 1239 static void 1240 bge_miibus_statchg(device_t dev) 1241 { 1242 struct bge_softc *sc; 1243 struct mii_data *mii; 1244 uint32_t mac_mode, rx_mode, tx_mode; 1245 1246 sc = device_get_softc(dev); 1247 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1248 return; 1249 mii = device_get_softc(sc->bge_miibus); 1250 1251 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1252 (IFM_ACTIVE | IFM_AVALID)) { 1253 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1254 case IFM_10_T: 1255 case IFM_100_TX: 1256 sc->bge_link = 1; 1257 break; 1258 case IFM_1000_T: 1259 case IFM_1000_SX: 1260 case IFM_2500_SX: 1261 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1262 sc->bge_link = 1; 1263 else 1264 sc->bge_link = 0; 1265 break; 1266 default: 1267 sc->bge_link = 0; 1268 break; 1269 } 1270 } else 1271 sc->bge_link = 0; 1272 if (sc->bge_link == 0) 1273 return; 1274 1275 /* 1276 * APE firmware touches these registers to keep the MAC 1277 * connected to the outside world. Try to keep the 1278 * accesses atomic. 1279 */ 1280 1281 /* Set the port mode (MII/GMII) to match the link speed. */ 1282 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1283 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1284 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1285 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1286 1287 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1288 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1289 mac_mode |= BGE_PORTMODE_GMII; 1290 else 1291 mac_mode |= BGE_PORTMODE_MII; 1292 1293 /* Set MAC flow control behavior to match link flow control settings. */ 1294 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1295 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1296 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1298 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1299 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1300 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1301 } else 1302 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1303 1304 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1305 DELAY(40); 1306 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1307 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1308 } 1309 1310 /* 1311 * Intialize a standard receive ring descriptor. 1312 */ 1313 static int 1314 bge_newbuf_std(struct bge_softc *sc, int i) 1315 { 1316 struct mbuf *m; 1317 struct bge_rx_bd *r; 1318 bus_dma_segment_t segs[1]; 1319 bus_dmamap_t map; 1320 int error, nsegs; 1321 1322 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1323 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1324 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1325 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1326 if (m == NULL) 1327 return (ENOBUFS); 1328 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1329 } else { 1330 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1331 if (m == NULL) 1332 return (ENOBUFS); 1333 m->m_len = m->m_pkthdr.len = MCLBYTES; 1334 } 1335 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1336 m_adj(m, ETHER_ALIGN); 1337 1338 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1339 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1340 if (error != 0) { 1341 m_freem(m); 1342 return (error); 1343 } 1344 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1345 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1346 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1347 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1348 sc->bge_cdata.bge_rx_std_dmamap[i]); 1349 } 1350 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1351 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1352 sc->bge_cdata.bge_rx_std_sparemap = map; 1353 sc->bge_cdata.bge_rx_std_chain[i] = m; 1354 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1355 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1356 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1357 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1358 r->bge_flags = BGE_RXBDFLAG_END; 1359 r->bge_len = segs[0].ds_len; 1360 r->bge_idx = i; 1361 1362 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1363 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1364 1365 return (0); 1366 } 1367 1368 /* 1369 * Initialize a jumbo receive ring descriptor. This allocates 1370 * a jumbo buffer from the pool managed internally by the driver. 1371 */ 1372 static int 1373 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1374 { 1375 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1376 bus_dmamap_t map; 1377 struct bge_extrx_bd *r; 1378 struct mbuf *m; 1379 int error, nsegs; 1380 1381 MGETHDR(m, M_NOWAIT, MT_DATA); 1382 if (m == NULL) 1383 return (ENOBUFS); 1384 1385 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1386 if (!(m->m_flags & M_EXT)) { 1387 m_freem(m); 1388 return (ENOBUFS); 1389 } 1390 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1391 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1392 m_adj(m, ETHER_ALIGN); 1393 1394 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1395 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1396 if (error != 0) { 1397 m_freem(m); 1398 return (error); 1399 } 1400 1401 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1402 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1403 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1404 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1405 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1406 } 1407 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1409 sc->bge_cdata.bge_rx_jumbo_sparemap; 1410 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1411 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1412 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1413 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1416 1417 /* 1418 * Fill in the extended RX buffer descriptor. 1419 */ 1420 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1421 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1422 r->bge_idx = i; 1423 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1424 switch (nsegs) { 1425 case 4: 1426 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1427 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1428 r->bge_len3 = segs[3].ds_len; 1429 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1430 case 3: 1431 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1432 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1433 r->bge_len2 = segs[2].ds_len; 1434 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1435 case 2: 1436 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1437 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1438 r->bge_len1 = segs[1].ds_len; 1439 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1440 case 1: 1441 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1442 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1443 r->bge_len0 = segs[0].ds_len; 1444 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1445 break; 1446 default: 1447 panic("%s: %d segments\n", __func__, nsegs); 1448 } 1449 1450 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1451 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1452 1453 return (0); 1454 } 1455 1456 static int 1457 bge_init_rx_ring_std(struct bge_softc *sc) 1458 { 1459 int error, i; 1460 1461 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1462 sc->bge_std = 0; 1463 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1464 if ((error = bge_newbuf_std(sc, i)) != 0) 1465 return (error); 1466 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1467 } 1468 1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1470 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1471 1472 sc->bge_std = 0; 1473 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1474 1475 return (0); 1476 } 1477 1478 static void 1479 bge_free_rx_ring_std(struct bge_softc *sc) 1480 { 1481 int i; 1482 1483 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1484 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1485 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1486 sc->bge_cdata.bge_rx_std_dmamap[i], 1487 BUS_DMASYNC_POSTREAD); 1488 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1489 sc->bge_cdata.bge_rx_std_dmamap[i]); 1490 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1491 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1492 } 1493 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1494 sizeof(struct bge_rx_bd)); 1495 } 1496 } 1497 1498 static int 1499 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1500 { 1501 struct bge_rcb *rcb; 1502 int error, i; 1503 1504 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1505 sc->bge_jumbo = 0; 1506 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1507 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1508 return (error); 1509 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1510 } 1511 1512 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1513 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1514 1515 sc->bge_jumbo = 0; 1516 1517 /* Enable the jumbo receive producer ring. */ 1518 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1519 rcb->bge_maxlen_flags = 1520 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1522 1523 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1524 1525 return (0); 1526 } 1527 1528 static void 1529 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1530 { 1531 int i; 1532 1533 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1534 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1535 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1536 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1537 BUS_DMASYNC_POSTREAD); 1538 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1539 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1540 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1541 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1542 } 1543 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1544 sizeof(struct bge_extrx_bd)); 1545 } 1546 } 1547 1548 static void 1549 bge_free_tx_ring(struct bge_softc *sc) 1550 { 1551 int i; 1552 1553 if (sc->bge_ldata.bge_tx_ring == NULL) 1554 return; 1555 1556 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1557 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1558 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1559 sc->bge_cdata.bge_tx_dmamap[i], 1560 BUS_DMASYNC_POSTWRITE); 1561 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1562 sc->bge_cdata.bge_tx_dmamap[i]); 1563 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1564 sc->bge_cdata.bge_tx_chain[i] = NULL; 1565 } 1566 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1567 sizeof(struct bge_tx_bd)); 1568 } 1569 } 1570 1571 static int 1572 bge_init_tx_ring(struct bge_softc *sc) 1573 { 1574 sc->bge_txcnt = 0; 1575 sc->bge_tx_saved_considx = 0; 1576 1577 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1578 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1579 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1580 1581 /* Initialize transmit producer index for host-memory send ring. */ 1582 sc->bge_tx_prodidx = 0; 1583 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1584 1585 /* 5700 b2 errata */ 1586 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1587 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1588 1589 /* NIC-memory send ring not used; initialize to zero. */ 1590 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1591 /* 5700 b2 errata */ 1592 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1593 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1594 1595 return (0); 1596 } 1597 1598 static void 1599 bge_setpromisc(struct bge_softc *sc) 1600 { 1601 if_t ifp; 1602 1603 BGE_LOCK_ASSERT(sc); 1604 1605 ifp = sc->bge_ifp; 1606 1607 /* Enable or disable promiscuous mode as needed. */ 1608 if (if_getflags(ifp) & IFF_PROMISC) 1609 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1610 else 1611 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1612 } 1613 1614 static void 1615 bge_setmulti(struct bge_softc *sc) 1616 { 1617 if_t ifp; 1618 int mc_count = 0; 1619 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1620 int h, i, mcnt; 1621 unsigned char *mta; 1622 1623 BGE_LOCK_ASSERT(sc); 1624 1625 ifp = sc->bge_ifp; 1626 1627 mc_count = if_multiaddr_count(ifp, -1); 1628 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * 1629 mc_count, M_DEVBUF, M_NOWAIT); 1630 1631 if(mta == NULL) { 1632 device_printf(sc->bge_dev, 1633 "Failed to allocated temp mcast list\n"); 1634 return; 1635 } 1636 1637 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 1638 for (i = 0; i < 4; i++) 1639 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1640 return; 1641 } 1642 1643 /* First, zot all the existing filters. */ 1644 for (i = 0; i < 4; i++) 1645 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1646 1647 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 1648 for(i = 0; i < mcnt; i++) { 1649 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 1650 ETHER_ADDR_LEN) & 0x7F; 1651 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1652 } 1653 1654 for (i = 0; i < 4; i++) 1655 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1656 1657 free(mta, M_DEVBUF); 1658 } 1659 1660 static void 1661 bge_setvlan(struct bge_softc *sc) 1662 { 1663 if_t ifp; 1664 1665 BGE_LOCK_ASSERT(sc); 1666 1667 ifp = sc->bge_ifp; 1668 1669 /* Enable or disable VLAN tag stripping as needed. */ 1670 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1671 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1672 else 1673 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1674 } 1675 1676 static void 1677 bge_sig_pre_reset(struct bge_softc *sc, int type) 1678 { 1679 1680 /* 1681 * Some chips don't like this so only do this if ASF is enabled 1682 */ 1683 if (sc->bge_asf_mode) 1684 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1685 1686 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1687 switch (type) { 1688 case BGE_RESET_START: 1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1690 BGE_FW_DRV_STATE_START); 1691 break; 1692 case BGE_RESET_SHUTDOWN: 1693 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1694 BGE_FW_DRV_STATE_UNLOAD); 1695 break; 1696 case BGE_RESET_SUSPEND: 1697 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1698 BGE_FW_DRV_STATE_SUSPEND); 1699 break; 1700 } 1701 } 1702 1703 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1704 bge_ape_driver_state_change(sc, type); 1705 } 1706 1707 static void 1708 bge_sig_post_reset(struct bge_softc *sc, int type) 1709 { 1710 1711 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1712 switch (type) { 1713 case BGE_RESET_START: 1714 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1715 BGE_FW_DRV_STATE_START_DONE); 1716 /* START DONE */ 1717 break; 1718 case BGE_RESET_SHUTDOWN: 1719 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1720 BGE_FW_DRV_STATE_UNLOAD_DONE); 1721 break; 1722 } 1723 } 1724 if (type == BGE_RESET_SHUTDOWN) 1725 bge_ape_driver_state_change(sc, type); 1726 } 1727 1728 static void 1729 bge_sig_legacy(struct bge_softc *sc, int type) 1730 { 1731 1732 if (sc->bge_asf_mode) { 1733 switch (type) { 1734 case BGE_RESET_START: 1735 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1736 BGE_FW_DRV_STATE_START); 1737 break; 1738 case BGE_RESET_SHUTDOWN: 1739 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1740 BGE_FW_DRV_STATE_UNLOAD); 1741 break; 1742 } 1743 } 1744 } 1745 1746 static void 1747 bge_stop_fw(struct bge_softc *sc) 1748 { 1749 int i; 1750 1751 if (sc->bge_asf_mode) { 1752 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1753 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1754 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1755 1756 for (i = 0; i < 100; i++ ) { 1757 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1758 BGE_RX_CPU_DRV_EVENT)) 1759 break; 1760 DELAY(10); 1761 } 1762 } 1763 } 1764 1765 static uint32_t 1766 bge_dma_swap_options(struct bge_softc *sc) 1767 { 1768 uint32_t dma_options; 1769 1770 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1771 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1772 #if BYTE_ORDER == BIG_ENDIAN 1773 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1774 #endif 1775 return (dma_options); 1776 } 1777 1778 /* 1779 * Do endian, PCI and DMA initialization. 1780 */ 1781 static int 1782 bge_chipinit(struct bge_softc *sc) 1783 { 1784 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1785 uint16_t val; 1786 int i; 1787 1788 /* Set endianness before we access any non-PCI registers. */ 1789 misc_ctl = BGE_INIT; 1790 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1791 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1792 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1793 1794 /* 1795 * Clear the MAC statistics block in the NIC's 1796 * internal memory. 1797 */ 1798 for (i = BGE_STATS_BLOCK; 1799 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1800 BGE_MEMWIN_WRITE(sc, i, 0); 1801 1802 for (i = BGE_STATUS_BLOCK; 1803 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1804 BGE_MEMWIN_WRITE(sc, i, 0); 1805 1806 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1807 /* 1808 * Fix data corruption caused by non-qword write with WB. 1809 * Fix master abort in PCI mode. 1810 * Fix PCI latency timer. 1811 */ 1812 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1813 val |= (1 << 10) | (1 << 12) | (1 << 13); 1814 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1815 } 1816 1817 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1818 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1819 /* 1820 * For the 57766 and non Ax versions of 57765, bootcode 1821 * needs to setup the PCIE Fast Training Sequence (FTS) 1822 * value to prevent transmit hangs. 1823 */ 1824 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1825 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1826 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1827 BGE_CPMU_PADRNG_CTL_RDIV2); 1828 } 1829 } 1830 1831 /* 1832 * Set up the PCI DMA control register. 1833 */ 1834 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1835 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1836 if (sc->bge_flags & BGE_FLAG_PCIE) { 1837 if (sc->bge_mps >= 256) 1838 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1839 else 1840 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1841 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1842 if (BGE_IS_5714_FAMILY(sc)) { 1843 /* 256 bytes for read and write. */ 1844 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1845 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1846 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1847 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1848 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1849 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1850 /* 1851 * In the BCM5703, the DMA read watermark should 1852 * be set to less than or equal to the maximum 1853 * memory read byte count of the PCI-X command 1854 * register. 1855 */ 1856 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1857 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1858 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1859 /* 1536 bytes for read, 384 bytes for write. */ 1860 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1861 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1862 } else { 1863 /* 384 bytes for read and write. */ 1864 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1865 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1866 0x0F; 1867 } 1868 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1869 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1870 uint32_t tmp; 1871 1872 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1873 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1874 if (tmp == 6 || tmp == 7) 1875 dma_rw_ctl |= 1876 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1877 1878 /* Set PCI-X DMA write workaround. */ 1879 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1880 } 1881 } else { 1882 /* Conventional PCI bus: 256 bytes for read and write. */ 1883 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1884 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1885 1886 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1887 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1888 dma_rw_ctl |= 0x0F; 1889 } 1890 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1891 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1892 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1893 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1894 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1895 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1896 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1897 if (BGE_IS_5717_PLUS(sc)) { 1898 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1899 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1900 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1901 /* 1902 * Enable HW workaround for controllers that misinterpret 1903 * a status tag update and leave interrupts permanently 1904 * disabled. 1905 */ 1906 if (!BGE_IS_57765_PLUS(sc) && 1907 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1908 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1909 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1910 } 1911 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1912 1913 /* 1914 * Set up general mode register. 1915 */ 1916 mode_ctl = bge_dma_swap_options(sc); 1917 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1918 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1919 /* Retain Host-2-BMC settings written by APE firmware. */ 1920 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1921 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1922 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1923 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1924 } 1925 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1926 BGE_MODECTL_TX_NO_PHDR_CSUM; 1927 1928 /* 1929 * BCM5701 B5 have a bug causing data corruption when using 1930 * 64-bit DMA reads, which can be terminated early and then 1931 * completed later as 32-bit accesses, in combination with 1932 * certain bridges. 1933 */ 1934 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1935 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1936 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1937 1938 /* 1939 * Tell the firmware the driver is running 1940 */ 1941 if (sc->bge_asf_mode & ASF_STACKUP) 1942 mode_ctl |= BGE_MODECTL_STACKUP; 1943 1944 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1945 1946 /* 1947 * Disable memory write invalidate. Apparently it is not supported 1948 * properly by these devices. Also ensure that INTx isn't disabled, 1949 * as these chips need it even when using MSI. 1950 */ 1951 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1952 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1953 1954 /* Set the timer prescaler (always 66 MHz). */ 1955 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1956 1957 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1958 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1959 DELAY(40); /* XXX */ 1960 1961 /* Put PHY into ready state */ 1962 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1963 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1964 DELAY(40); 1965 } 1966 1967 return (0); 1968 } 1969 1970 static int 1971 bge_blockinit(struct bge_softc *sc) 1972 { 1973 struct bge_rcb *rcb; 1974 bus_size_t vrcb; 1975 bge_hostaddr taddr; 1976 uint32_t dmactl, rdmareg, val; 1977 int i, limit; 1978 1979 /* 1980 * Initialize the memory window pointer register so that 1981 * we can access the first 32K of internal NIC RAM. This will 1982 * allow us to set up the TX send ring RCBs and the RX return 1983 * ring RCBs, plus other things which live in NIC memory. 1984 */ 1985 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1986 1987 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1988 1989 if (!(BGE_IS_5705_PLUS(sc))) { 1990 /* Configure mbuf memory pool */ 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1992 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1993 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1994 else 1995 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1996 1997 /* Configure DMA resource pool */ 1998 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1999 BGE_DMA_DESCRIPTORS); 2000 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2001 } 2002 2003 /* Configure mbuf pool watermarks */ 2004 if (BGE_IS_5717_PLUS(sc)) { 2005 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2006 if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2009 } else { 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2012 } 2013 } else if (!BGE_IS_5705_PLUS(sc)) { 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2017 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2018 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2019 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2020 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2021 } else { 2022 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2023 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2024 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2025 } 2026 2027 /* Configure DMA resource watermarks */ 2028 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2029 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2030 2031 /* Enable buffer manager */ 2032 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2033 /* 2034 * Change the arbitration algorithm of TXMBUF read request to 2035 * round-robin instead of priority based for BCM5719. When 2036 * TXFIFO is almost empty, RDMA will hold its request until 2037 * TXFIFO is not almost empty. 2038 */ 2039 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2040 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2041 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2042 2043 /* Poll for buffer manager start indication */ 2044 for (i = 0; i < BGE_TIMEOUT; i++) { 2045 DELAY(10); 2046 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2047 break; 2048 } 2049 2050 if (i == BGE_TIMEOUT) { 2051 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2052 return (ENXIO); 2053 } 2054 2055 /* Enable flow-through queues */ 2056 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2057 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2058 2059 /* Wait until queue initialization is complete */ 2060 for (i = 0; i < BGE_TIMEOUT; i++) { 2061 DELAY(10); 2062 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2063 break; 2064 } 2065 2066 if (i == BGE_TIMEOUT) { 2067 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2068 return (ENXIO); 2069 } 2070 2071 /* 2072 * Summary of rings supported by the controller: 2073 * 2074 * Standard Receive Producer Ring 2075 * - This ring is used to feed receive buffers for "standard" 2076 * sized frames (typically 1536 bytes) to the controller. 2077 * 2078 * Jumbo Receive Producer Ring 2079 * - This ring is used to feed receive buffers for jumbo sized 2080 * frames (i.e. anything bigger than the "standard" frames) 2081 * to the controller. 2082 * 2083 * Mini Receive Producer Ring 2084 * - This ring is used to feed receive buffers for "mini" 2085 * sized frames to the controller. 2086 * - This feature required external memory for the controller 2087 * but was never used in a production system. Should always 2088 * be disabled. 2089 * 2090 * Receive Return Ring 2091 * - After the controller has placed an incoming frame into a 2092 * receive buffer that buffer is moved into a receive return 2093 * ring. The driver is then responsible to passing the 2094 * buffer up to the stack. Many versions of the controller 2095 * support multiple RR rings. 2096 * 2097 * Send Ring 2098 * - This ring is used for outgoing frames. Many versions of 2099 * the controller support multiple send rings. 2100 */ 2101 2102 /* Initialize the standard receive producer ring control block. */ 2103 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2104 rcb->bge_hostaddr.bge_addr_lo = 2105 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2106 rcb->bge_hostaddr.bge_addr_hi = 2107 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2108 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2109 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2110 if (BGE_IS_5717_PLUS(sc)) { 2111 /* 2112 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2113 * Bits 15-2 : Maximum RX frame size 2114 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2115 * Bit 0 : Reserved 2116 */ 2117 rcb->bge_maxlen_flags = 2118 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2119 } else if (BGE_IS_5705_PLUS(sc)) { 2120 /* 2121 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2122 * Bits 15-2 : Reserved (should be 0) 2123 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2124 * Bit 0 : Reserved 2125 */ 2126 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2127 } else { 2128 /* 2129 * Ring size is always XXX entries 2130 * Bits 31-16: Maximum RX frame size 2131 * Bits 15-2 : Reserved (should be 0) 2132 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2133 * Bit 0 : Reserved 2134 */ 2135 rcb->bge_maxlen_flags = 2136 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2137 } 2138 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2139 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2140 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2141 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2142 else 2143 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2144 /* Write the standard receive producer ring control block. */ 2145 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2146 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2147 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2148 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2149 2150 /* Reset the standard receive producer ring producer index. */ 2151 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2152 2153 /* 2154 * Initialize the jumbo RX producer ring control 2155 * block. We set the 'ring disabled' bit in the 2156 * flags field until we're actually ready to start 2157 * using this ring (i.e. once we set the MTU 2158 * high enough to require it). 2159 */ 2160 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2161 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2162 /* Get the jumbo receive producer ring RCB parameters. */ 2163 rcb->bge_hostaddr.bge_addr_lo = 2164 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2165 rcb->bge_hostaddr.bge_addr_hi = 2166 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2167 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2168 sc->bge_cdata.bge_rx_jumbo_ring_map, 2169 BUS_DMASYNC_PREREAD); 2170 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2171 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2172 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2173 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2174 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2175 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2176 else 2177 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2178 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2179 rcb->bge_hostaddr.bge_addr_hi); 2180 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2181 rcb->bge_hostaddr.bge_addr_lo); 2182 /* Program the jumbo receive producer ring RCB parameters. */ 2183 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2184 rcb->bge_maxlen_flags); 2185 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2186 /* Reset the jumbo receive producer ring producer index. */ 2187 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2188 } 2189 2190 /* Disable the mini receive producer ring RCB. */ 2191 if (BGE_IS_5700_FAMILY(sc)) { 2192 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2193 rcb->bge_maxlen_flags = 2194 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2195 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2196 rcb->bge_maxlen_flags); 2197 /* Reset the mini receive producer ring producer index. */ 2198 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2199 } 2200 2201 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2202 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2203 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2204 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2205 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2206 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2207 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2208 } 2209 /* 2210 * The BD ring replenish thresholds control how often the 2211 * hardware fetches new BD's from the producer rings in host 2212 * memory. Setting the value too low on a busy system can 2213 * starve the hardware and recue the throughpout. 2214 * 2215 * Set the BD ring replentish thresholds. The recommended 2216 * values are 1/8th the number of descriptors allocated to 2217 * each ring. 2218 * XXX The 5754 requires a lower threshold, so it might be a 2219 * requirement of all 575x family chips. The Linux driver sets 2220 * the lower threshold for all 5705 family chips as well, but there 2221 * are reports that it might not need to be so strict. 2222 * 2223 * XXX Linux does some extra fiddling here for the 5906 parts as 2224 * well. 2225 */ 2226 if (BGE_IS_5705_PLUS(sc)) 2227 val = 8; 2228 else 2229 val = BGE_STD_RX_RING_CNT / 8; 2230 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2231 if (BGE_IS_JUMBO_CAPABLE(sc)) 2232 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2233 BGE_JUMBO_RX_RING_CNT/8); 2234 if (BGE_IS_5717_PLUS(sc)) { 2235 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2236 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2237 } 2238 2239 /* 2240 * Disable all send rings by setting the 'ring disabled' bit 2241 * in the flags field of all the TX send ring control blocks, 2242 * located in NIC memory. 2243 */ 2244 if (!BGE_IS_5705_PLUS(sc)) 2245 /* 5700 to 5704 had 16 send rings. */ 2246 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2247 else if (BGE_IS_57765_PLUS(sc) || 2248 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2249 limit = 2; 2250 else if (BGE_IS_5717_PLUS(sc)) 2251 limit = 4; 2252 else 2253 limit = 1; 2254 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2255 for (i = 0; i < limit; i++) { 2256 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2257 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2258 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2259 vrcb += sizeof(struct bge_rcb); 2260 } 2261 2262 /* Configure send ring RCB 0 (we use only the first ring) */ 2263 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2264 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2266 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2267 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2268 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2269 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2270 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2271 else 2272 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2273 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2274 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2275 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2276 2277 /* 2278 * Disable all receive return rings by setting the 2279 * 'ring diabled' bit in the flags field of all the receive 2280 * return ring control blocks, located in NIC memory. 2281 */ 2282 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2283 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2284 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2285 /* Should be 17, use 16 until we get an SRAM map. */ 2286 limit = 16; 2287 } else if (!BGE_IS_5705_PLUS(sc)) 2288 limit = BGE_RX_RINGS_MAX; 2289 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2290 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2291 BGE_IS_57765_PLUS(sc)) 2292 limit = 4; 2293 else 2294 limit = 1; 2295 /* Disable all receive return rings. */ 2296 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2297 for (i = 0; i < limit; i++) { 2298 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2299 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2300 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2301 BGE_RCB_FLAG_RING_DISABLED); 2302 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2303 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2304 (i * (sizeof(uint64_t))), 0); 2305 vrcb += sizeof(struct bge_rcb); 2306 } 2307 2308 /* 2309 * Set up receive return ring 0. Note that the NIC address 2310 * for RX return rings is 0x0. The return rings live entirely 2311 * within the host, so the nicaddr field in the RCB isn't used. 2312 */ 2313 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2314 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2315 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2316 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2317 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2318 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2319 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2320 2321 /* Set random backoff seed for TX */ 2322 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2323 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2324 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2325 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2326 BGE_TX_BACKOFF_SEED_MASK); 2327 2328 /* Set inter-packet gap */ 2329 val = 0x2620; 2330 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2331 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2332 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2333 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2334 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2335 2336 /* 2337 * Specify which ring to use for packets that don't match 2338 * any RX rules. 2339 */ 2340 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2341 2342 /* 2343 * Configure number of RX lists. One interrupt distribution 2344 * list, sixteen active lists, one bad frames class. 2345 */ 2346 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2347 2348 /* Inialize RX list placement stats mask. */ 2349 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2350 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2351 2352 /* Disable host coalescing until we get it set up */ 2353 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2354 2355 /* Poll to make sure it's shut down. */ 2356 for (i = 0; i < BGE_TIMEOUT; i++) { 2357 DELAY(10); 2358 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2359 break; 2360 } 2361 2362 if (i == BGE_TIMEOUT) { 2363 device_printf(sc->bge_dev, 2364 "host coalescing engine failed to idle\n"); 2365 return (ENXIO); 2366 } 2367 2368 /* Set up host coalescing defaults */ 2369 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2370 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2371 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2372 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2373 if (!(BGE_IS_5705_PLUS(sc))) { 2374 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2375 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2376 } 2377 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2378 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2379 2380 /* Set up address of statistics block */ 2381 if (!(BGE_IS_5705_PLUS(sc))) { 2382 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2383 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2384 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2385 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2386 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2387 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2388 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2389 } 2390 2391 /* Set up address of status block */ 2392 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2393 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2394 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2395 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2396 2397 /* Set up status block size. */ 2398 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2399 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2400 val = BGE_STATBLKSZ_FULL; 2401 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2402 } else { 2403 val = BGE_STATBLKSZ_32BYTE; 2404 bzero(sc->bge_ldata.bge_status_block, 32); 2405 } 2406 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2407 sc->bge_cdata.bge_status_map, 2408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2409 2410 /* Turn on host coalescing state machine */ 2411 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2412 2413 /* Turn on RX BD completion state machine and enable attentions */ 2414 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2415 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2416 2417 /* Turn on RX list placement state machine */ 2418 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2419 2420 /* Turn on RX list selector state machine. */ 2421 if (!(BGE_IS_5705_PLUS(sc))) 2422 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2423 2424 /* Turn on DMA, clear stats. */ 2425 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2426 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2427 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2428 BGE_MACMODE_FRMHDR_DMA_ENB; 2429 2430 if (sc->bge_flags & BGE_FLAG_TBI) 2431 val |= BGE_PORTMODE_TBI; 2432 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2433 val |= BGE_PORTMODE_GMII; 2434 else 2435 val |= BGE_PORTMODE_MII; 2436 2437 /* Allow APE to send/receive frames. */ 2438 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2439 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2440 2441 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2442 DELAY(40); 2443 2444 /* Set misc. local control, enable interrupts on attentions */ 2445 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2446 2447 #ifdef notdef 2448 /* Assert GPIO pins for PHY reset */ 2449 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2450 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2451 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2452 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2453 #endif 2454 2455 /* Turn on DMA completion state machine */ 2456 if (!(BGE_IS_5705_PLUS(sc))) 2457 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2458 2459 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2460 2461 /* Enable host coalescing bug fix. */ 2462 if (BGE_IS_5755_PLUS(sc)) 2463 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2464 2465 /* Request larger DMA burst size to get better performance. */ 2466 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2467 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2468 2469 /* Turn on write DMA state machine */ 2470 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2471 DELAY(40); 2472 2473 /* Turn on read DMA state machine */ 2474 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2475 2476 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2477 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2478 2479 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2480 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2481 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2482 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2483 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2484 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2485 if (sc->bge_flags & BGE_FLAG_PCIE) 2486 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2487 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2488 val |= BGE_RDMAMODE_TSO4_ENABLE; 2489 if (sc->bge_flags & BGE_FLAG_TSO3 || 2490 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2491 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2492 val |= BGE_RDMAMODE_TSO6_ENABLE; 2493 } 2494 2495 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2496 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2497 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2498 BGE_RDMAMODE_H2BNC_VLAN_DET; 2499 /* 2500 * Allow multiple outstanding read requests from 2501 * non-LSO read DMA engine. 2502 */ 2503 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2504 } 2505 2506 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2507 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2508 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2509 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2510 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2511 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2512 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2513 else 2514 rdmareg = BGE_RDMA_RSRVCTRL; 2515 dmactl = CSR_READ_4(sc, rdmareg); 2516 /* 2517 * Adjust tx margin to prevent TX data corruption and 2518 * fix internal FIFO overflow. 2519 */ 2520 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2521 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2522 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2523 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2524 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2525 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2526 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2527 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2528 } 2529 /* 2530 * Enable fix for read DMA FIFO overruns. 2531 * The fix is to limit the number of RX BDs 2532 * the hardware would fetch at a fime. 2533 */ 2534 CSR_WRITE_4(sc, rdmareg, dmactl | 2535 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2536 } 2537 2538 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2539 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2540 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2541 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2542 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2543 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2544 /* 2545 * Allow 4KB burst length reads for non-LSO frames. 2546 * Enable 512B burst length reads for buffer descriptors. 2547 */ 2548 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2549 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2550 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2551 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2552 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2553 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2554 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2555 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2556 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2557 } 2558 2559 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2560 DELAY(40); 2561 2562 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2563 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2564 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2565 if ((val & 0xFFFF) > BGE_FRAMELEN) 2566 break; 2567 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2568 break; 2569 } 2570 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2571 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2572 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2573 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2574 else 2575 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2576 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2577 } 2578 } 2579 2580 /* Turn on RX data completion state machine */ 2581 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2582 2583 /* Turn on RX BD initiator state machine */ 2584 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2585 2586 /* Turn on RX data and RX BD initiator state machine */ 2587 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2588 2589 /* Turn on Mbuf cluster free state machine */ 2590 if (!(BGE_IS_5705_PLUS(sc))) 2591 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2592 2593 /* Turn on send BD completion state machine */ 2594 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2595 2596 /* Turn on send data completion state machine */ 2597 val = BGE_SDCMODE_ENABLE; 2598 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2599 val |= BGE_SDCMODE_CDELAY; 2600 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2601 2602 /* Turn on send data initiator state machine */ 2603 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2604 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2605 BGE_SDIMODE_HW_LSO_PRE_DMA); 2606 else 2607 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2608 2609 /* Turn on send BD initiator state machine */ 2610 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2611 2612 /* Turn on send BD selector state machine */ 2613 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2614 2615 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2616 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2617 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2618 2619 /* ack/clear link change events */ 2620 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2621 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2622 BGE_MACSTAT_LINK_CHANGED); 2623 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2624 2625 /* 2626 * Enable attention when the link has changed state for 2627 * devices that use auto polling. 2628 */ 2629 if (sc->bge_flags & BGE_FLAG_TBI) { 2630 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2631 } else { 2632 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2633 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2634 DELAY(80); 2635 } 2636 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2637 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2638 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2639 BGE_EVTENB_MI_INTERRUPT); 2640 } 2641 2642 /* 2643 * Clear any pending link state attention. 2644 * Otherwise some link state change events may be lost until attention 2645 * is cleared by bge_intr() -> bge_link_upd() sequence. 2646 * It's not necessary on newer BCM chips - perhaps enabling link 2647 * state change attentions implies clearing pending attention. 2648 */ 2649 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2650 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2651 BGE_MACSTAT_LINK_CHANGED); 2652 2653 /* Enable link state change attentions. */ 2654 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2655 2656 return (0); 2657 } 2658 2659 static const struct bge_revision * 2660 bge_lookup_rev(uint32_t chipid) 2661 { 2662 const struct bge_revision *br; 2663 2664 for (br = bge_revisions; br->br_name != NULL; br++) { 2665 if (br->br_chipid == chipid) 2666 return (br); 2667 } 2668 2669 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2670 if (br->br_chipid == BGE_ASICREV(chipid)) 2671 return (br); 2672 } 2673 2674 return (NULL); 2675 } 2676 2677 static const struct bge_vendor * 2678 bge_lookup_vendor(uint16_t vid) 2679 { 2680 const struct bge_vendor *v; 2681 2682 for (v = bge_vendors; v->v_name != NULL; v++) 2683 if (v->v_id == vid) 2684 return (v); 2685 2686 return (NULL); 2687 } 2688 2689 static uint32_t 2690 bge_chipid(device_t dev) 2691 { 2692 uint32_t id; 2693 2694 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2695 BGE_PCIMISCCTL_ASICREV_SHIFT; 2696 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2697 /* 2698 * Find the ASCI revision. Different chips use different 2699 * registers. 2700 */ 2701 switch (pci_get_device(dev)) { 2702 case BCOM_DEVICEID_BCM5717: 2703 case BCOM_DEVICEID_BCM5718: 2704 case BCOM_DEVICEID_BCM5719: 2705 case BCOM_DEVICEID_BCM5720: 2706 case BCOM_DEVICEID_BCM5725: 2707 case BCOM_DEVICEID_BCM5727: 2708 case BCOM_DEVICEID_BCM5762: 2709 case BCOM_DEVICEID_BCM57764: 2710 case BCOM_DEVICEID_BCM57767: 2711 case BCOM_DEVICEID_BCM57787: 2712 id = pci_read_config(dev, 2713 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2714 break; 2715 case BCOM_DEVICEID_BCM57761: 2716 case BCOM_DEVICEID_BCM57762: 2717 case BCOM_DEVICEID_BCM57765: 2718 case BCOM_DEVICEID_BCM57766: 2719 case BCOM_DEVICEID_BCM57781: 2720 case BCOM_DEVICEID_BCM57782: 2721 case BCOM_DEVICEID_BCM57785: 2722 case BCOM_DEVICEID_BCM57786: 2723 case BCOM_DEVICEID_BCM57791: 2724 case BCOM_DEVICEID_BCM57795: 2725 id = pci_read_config(dev, 2726 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2727 break; 2728 default: 2729 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2730 } 2731 } 2732 return (id); 2733 } 2734 2735 /* 2736 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2737 * against our list and return its name if we find a match. 2738 * 2739 * Note that since the Broadcom controller contains VPD support, we 2740 * try to get the device name string from the controller itself instead 2741 * of the compiled-in string. It guarantees we'll always announce the 2742 * right product name. We fall back to the compiled-in string when 2743 * VPD is unavailable or corrupt. 2744 */ 2745 static int 2746 bge_probe(device_t dev) 2747 { 2748 char buf[96]; 2749 char model[64]; 2750 const struct bge_revision *br; 2751 const char *pname; 2752 struct bge_softc *sc; 2753 const struct bge_type *t = bge_devs; 2754 const struct bge_vendor *v; 2755 uint32_t id; 2756 uint16_t did, vid; 2757 2758 sc = device_get_softc(dev); 2759 sc->bge_dev = dev; 2760 vid = pci_get_vendor(dev); 2761 did = pci_get_device(dev); 2762 while(t->bge_vid != 0) { 2763 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2764 id = bge_chipid(dev); 2765 br = bge_lookup_rev(id); 2766 if (bge_has_eaddr(sc) && 2767 pci_get_vpd_ident(dev, &pname) == 0) 2768 snprintf(model, sizeof(model), "%s", pname); 2769 else { 2770 v = bge_lookup_vendor(vid); 2771 snprintf(model, sizeof(model), "%s %s", 2772 v != NULL ? v->v_name : "Unknown", 2773 br != NULL ? br->br_name : 2774 "NetXtreme/NetLink Ethernet Controller"); 2775 } 2776 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2777 model, br != NULL ? "" : "unknown ", id); 2778 device_set_desc_copy(dev, buf); 2779 return (BUS_PROBE_DEFAULT); 2780 } 2781 t++; 2782 } 2783 2784 return (ENXIO); 2785 } 2786 2787 static void 2788 bge_dma_free(struct bge_softc *sc) 2789 { 2790 int i; 2791 2792 /* Destroy DMA maps for RX buffers. */ 2793 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2794 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2795 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2796 sc->bge_cdata.bge_rx_std_dmamap[i]); 2797 } 2798 if (sc->bge_cdata.bge_rx_std_sparemap) 2799 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2800 sc->bge_cdata.bge_rx_std_sparemap); 2801 2802 /* Destroy DMA maps for jumbo RX buffers. */ 2803 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2804 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2805 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2806 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2807 } 2808 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2809 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2810 sc->bge_cdata.bge_rx_jumbo_sparemap); 2811 2812 /* Destroy DMA maps for TX buffers. */ 2813 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2814 if (sc->bge_cdata.bge_tx_dmamap[i]) 2815 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2816 sc->bge_cdata.bge_tx_dmamap[i]); 2817 } 2818 2819 if (sc->bge_cdata.bge_rx_mtag) 2820 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2821 if (sc->bge_cdata.bge_mtag_jumbo) 2822 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2823 if (sc->bge_cdata.bge_tx_mtag) 2824 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2825 2826 /* Destroy standard RX ring. */ 2827 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2828 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2829 sc->bge_cdata.bge_rx_std_ring_map); 2830 if (sc->bge_ldata.bge_rx_std_ring) 2831 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2832 sc->bge_ldata.bge_rx_std_ring, 2833 sc->bge_cdata.bge_rx_std_ring_map); 2834 2835 if (sc->bge_cdata.bge_rx_std_ring_tag) 2836 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2837 2838 /* Destroy jumbo RX ring. */ 2839 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2840 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2841 sc->bge_cdata.bge_rx_jumbo_ring_map); 2842 2843 if (sc->bge_ldata.bge_rx_jumbo_ring) 2844 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2845 sc->bge_ldata.bge_rx_jumbo_ring, 2846 sc->bge_cdata.bge_rx_jumbo_ring_map); 2847 2848 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2849 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2850 2851 /* Destroy RX return ring. */ 2852 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2853 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2854 sc->bge_cdata.bge_rx_return_ring_map); 2855 2856 if (sc->bge_ldata.bge_rx_return_ring) 2857 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2858 sc->bge_ldata.bge_rx_return_ring, 2859 sc->bge_cdata.bge_rx_return_ring_map); 2860 2861 if (sc->bge_cdata.bge_rx_return_ring_tag) 2862 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2863 2864 /* Destroy TX ring. */ 2865 if (sc->bge_ldata.bge_tx_ring_paddr) 2866 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2867 sc->bge_cdata.bge_tx_ring_map); 2868 2869 if (sc->bge_ldata.bge_tx_ring) 2870 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2871 sc->bge_ldata.bge_tx_ring, 2872 sc->bge_cdata.bge_tx_ring_map); 2873 2874 if (sc->bge_cdata.bge_tx_ring_tag) 2875 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2876 2877 /* Destroy status block. */ 2878 if (sc->bge_ldata.bge_status_block_paddr) 2879 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2880 sc->bge_cdata.bge_status_map); 2881 2882 if (sc->bge_ldata.bge_status_block) 2883 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2884 sc->bge_ldata.bge_status_block, 2885 sc->bge_cdata.bge_status_map); 2886 2887 if (sc->bge_cdata.bge_status_tag) 2888 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2889 2890 /* Destroy statistics block. */ 2891 if (sc->bge_ldata.bge_stats_paddr) 2892 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2893 sc->bge_cdata.bge_stats_map); 2894 2895 if (sc->bge_ldata.bge_stats) 2896 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2897 sc->bge_ldata.bge_stats, 2898 sc->bge_cdata.bge_stats_map); 2899 2900 if (sc->bge_cdata.bge_stats_tag) 2901 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2902 2903 if (sc->bge_cdata.bge_buffer_tag) 2904 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2905 2906 /* Destroy the parent tag. */ 2907 if (sc->bge_cdata.bge_parent_tag) 2908 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2909 } 2910 2911 static int 2912 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2913 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2914 bus_addr_t *paddr, const char *msg) 2915 { 2916 struct bge_dmamap_arg ctx; 2917 int error; 2918 2919 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2920 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2921 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2922 if (error != 0) { 2923 device_printf(sc->bge_dev, 2924 "could not create %s dma tag\n", msg); 2925 return (ENOMEM); 2926 } 2927 /* Allocate DMA'able memory for ring. */ 2928 error = bus_dmamem_alloc(*tag, (void **)ring, 2929 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2930 if (error != 0) { 2931 device_printf(sc->bge_dev, 2932 "could not allocate DMA'able memory for %s\n", msg); 2933 return (ENOMEM); 2934 } 2935 /* Load the address of the ring. */ 2936 ctx.bge_busaddr = 0; 2937 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2938 &ctx, BUS_DMA_NOWAIT); 2939 if (error != 0) { 2940 device_printf(sc->bge_dev, 2941 "could not load DMA'able memory for %s\n", msg); 2942 return (ENOMEM); 2943 } 2944 *paddr = ctx.bge_busaddr; 2945 return (0); 2946 } 2947 2948 static int 2949 bge_dma_alloc(struct bge_softc *sc) 2950 { 2951 bus_addr_t lowaddr; 2952 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2953 int i, error; 2954 2955 lowaddr = BUS_SPACE_MAXADDR; 2956 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2957 lowaddr = BGE_DMA_MAXADDR; 2958 /* 2959 * Allocate the parent bus DMA tag appropriate for PCI. 2960 */ 2961 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2962 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2963 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2964 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2965 if (error != 0) { 2966 device_printf(sc->bge_dev, 2967 "could not allocate parent dma tag\n"); 2968 return (ENOMEM); 2969 } 2970 2971 /* Create tag for standard RX ring. */ 2972 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2973 &sc->bge_cdata.bge_rx_std_ring_tag, 2974 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2975 &sc->bge_cdata.bge_rx_std_ring_map, 2976 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2977 if (error) 2978 return (error); 2979 2980 /* Create tag for RX return ring. */ 2981 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2982 &sc->bge_cdata.bge_rx_return_ring_tag, 2983 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2984 &sc->bge_cdata.bge_rx_return_ring_map, 2985 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2986 if (error) 2987 return (error); 2988 2989 /* Create tag for TX ring. */ 2990 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2991 &sc->bge_cdata.bge_tx_ring_tag, 2992 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2993 &sc->bge_cdata.bge_tx_ring_map, 2994 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2995 if (error) 2996 return (error); 2997 2998 /* 2999 * Create tag for status block. 3000 * Because we only use single Tx/Rx/Rx return ring, use 3001 * minimum status block size except BCM5700 AX/BX which 3002 * seems to want to see full status block size regardless 3003 * of configured number of ring. 3004 */ 3005 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3006 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 3007 sbsz = BGE_STATUS_BLK_SZ; 3008 else 3009 sbsz = 32; 3010 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3011 &sc->bge_cdata.bge_status_tag, 3012 (uint8_t **)&sc->bge_ldata.bge_status_block, 3013 &sc->bge_cdata.bge_status_map, 3014 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3015 if (error) 3016 return (error); 3017 3018 /* Create tag for statistics block. */ 3019 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3020 &sc->bge_cdata.bge_stats_tag, 3021 (uint8_t **)&sc->bge_ldata.bge_stats, 3022 &sc->bge_cdata.bge_stats_map, 3023 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3024 if (error) 3025 return (error); 3026 3027 /* Create tag for jumbo RX ring. */ 3028 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3029 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3030 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3031 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3032 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3033 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3034 if (error) 3035 return (error); 3036 } 3037 3038 /* Create parent tag for buffers. */ 3039 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3040 /* 3041 * XXX 3042 * watchdog timeout issue was observed on BCM5704 which 3043 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3044 * Both limiting DMA address space to 32bits and flushing 3045 * mailbox write seem to address the issue. 3046 */ 3047 if (sc->bge_pcixcap != 0) 3048 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3049 } 3050 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3051 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3052 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3053 &sc->bge_cdata.bge_buffer_tag); 3054 if (error != 0) { 3055 device_printf(sc->bge_dev, 3056 "could not allocate buffer dma tag\n"); 3057 return (ENOMEM); 3058 } 3059 /* Create tag for Tx mbufs. */ 3060 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3061 txsegsz = BGE_TSOSEG_SZ; 3062 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3063 } else { 3064 txsegsz = MCLBYTES; 3065 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3066 } 3067 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3068 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3069 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3070 &sc->bge_cdata.bge_tx_mtag); 3071 3072 if (error) { 3073 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3074 return (ENOMEM); 3075 } 3076 3077 /* Create tag for Rx mbufs. */ 3078 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3079 rxmaxsegsz = MJUM9BYTES; 3080 else 3081 rxmaxsegsz = MCLBYTES; 3082 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3083 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3084 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3085 3086 if (error) { 3087 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3088 return (ENOMEM); 3089 } 3090 3091 /* Create DMA maps for RX buffers. */ 3092 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3093 &sc->bge_cdata.bge_rx_std_sparemap); 3094 if (error) { 3095 device_printf(sc->bge_dev, 3096 "can't create spare DMA map for RX\n"); 3097 return (ENOMEM); 3098 } 3099 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3100 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3101 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3102 if (error) { 3103 device_printf(sc->bge_dev, 3104 "can't create DMA map for RX\n"); 3105 return (ENOMEM); 3106 } 3107 } 3108 3109 /* Create DMA maps for TX buffers. */ 3110 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3111 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3112 &sc->bge_cdata.bge_tx_dmamap[i]); 3113 if (error) { 3114 device_printf(sc->bge_dev, 3115 "can't create DMA map for TX\n"); 3116 return (ENOMEM); 3117 } 3118 } 3119 3120 /* Create tags for jumbo RX buffers. */ 3121 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3122 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3123 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3124 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3125 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3126 if (error) { 3127 device_printf(sc->bge_dev, 3128 "could not allocate jumbo dma tag\n"); 3129 return (ENOMEM); 3130 } 3131 /* Create DMA maps for jumbo RX buffers. */ 3132 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3133 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3134 if (error) { 3135 device_printf(sc->bge_dev, 3136 "can't create spare DMA map for jumbo RX\n"); 3137 return (ENOMEM); 3138 } 3139 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3140 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3141 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3142 if (error) { 3143 device_printf(sc->bge_dev, 3144 "can't create DMA map for jumbo RX\n"); 3145 return (ENOMEM); 3146 } 3147 } 3148 } 3149 3150 return (0); 3151 } 3152 3153 /* 3154 * Return true if this device has more than one port. 3155 */ 3156 static int 3157 bge_has_multiple_ports(struct bge_softc *sc) 3158 { 3159 device_t dev = sc->bge_dev; 3160 u_int b, d, f, fscan, s; 3161 3162 d = pci_get_domain(dev); 3163 b = pci_get_bus(dev); 3164 s = pci_get_slot(dev); 3165 f = pci_get_function(dev); 3166 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3167 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3168 return (1); 3169 return (0); 3170 } 3171 3172 /* 3173 * Return true if MSI can be used with this device. 3174 */ 3175 static int 3176 bge_can_use_msi(struct bge_softc *sc) 3177 { 3178 int can_use_msi = 0; 3179 3180 if (sc->bge_msi == 0) 3181 return (0); 3182 3183 /* Disable MSI for polling(4). */ 3184 #ifdef DEVICE_POLLING 3185 return (0); 3186 #endif 3187 switch (sc->bge_asicrev) { 3188 case BGE_ASICREV_BCM5714_A0: 3189 case BGE_ASICREV_BCM5714: 3190 /* 3191 * Apparently, MSI doesn't work when these chips are 3192 * configured in single-port mode. 3193 */ 3194 if (bge_has_multiple_ports(sc)) 3195 can_use_msi = 1; 3196 break; 3197 case BGE_ASICREV_BCM5750: 3198 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3199 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3200 can_use_msi = 1; 3201 break; 3202 default: 3203 if (BGE_IS_575X_PLUS(sc)) 3204 can_use_msi = 1; 3205 } 3206 return (can_use_msi); 3207 } 3208 3209 static int 3210 bge_mbox_reorder(struct bge_softc *sc) 3211 { 3212 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3213 static const struct mbox_reorder { 3214 const uint16_t vendor; 3215 const uint16_t device; 3216 const char *desc; 3217 } mbox_reorder_lists[] = { 3218 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3219 }; 3220 devclass_t pci, pcib; 3221 device_t bus, dev; 3222 int i; 3223 3224 pci = devclass_find("pci"); 3225 pcib = devclass_find("pcib"); 3226 dev = sc->bge_dev; 3227 bus = device_get_parent(dev); 3228 for (;;) { 3229 dev = device_get_parent(bus); 3230 bus = device_get_parent(dev); 3231 if (device_get_devclass(dev) != pcib) 3232 break; 3233 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3234 if (pci_get_vendor(dev) == 3235 mbox_reorder_lists[i].vendor && 3236 pci_get_device(dev) == 3237 mbox_reorder_lists[i].device) { 3238 device_printf(sc->bge_dev, 3239 "enabling MBOX workaround for %s\n", 3240 mbox_reorder_lists[i].desc); 3241 return (1); 3242 } 3243 } 3244 if (device_get_devclass(bus) != pci) 3245 break; 3246 } 3247 return (0); 3248 } 3249 3250 static void 3251 bge_devinfo(struct bge_softc *sc) 3252 { 3253 uint32_t cfg, clk; 3254 3255 device_printf(sc->bge_dev, 3256 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3257 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3258 if (sc->bge_flags & BGE_FLAG_PCIE) 3259 printf("PCI-E\n"); 3260 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3261 printf("PCI-X "); 3262 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3263 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3264 clk = 133; 3265 else { 3266 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3267 switch (clk) { 3268 case 0: 3269 clk = 33; 3270 break; 3271 case 2: 3272 clk = 50; 3273 break; 3274 case 4: 3275 clk = 66; 3276 break; 3277 case 6: 3278 clk = 100; 3279 break; 3280 case 7: 3281 clk = 133; 3282 break; 3283 } 3284 } 3285 printf("%u MHz\n", clk); 3286 } else { 3287 if (sc->bge_pcixcap != 0) 3288 printf("PCI on PCI-X "); 3289 else 3290 printf("PCI "); 3291 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3292 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3293 clk = 66; 3294 else 3295 clk = 33; 3296 if (cfg & BGE_PCISTATE_32BIT_BUS) 3297 printf("%u MHz; 32bit\n", clk); 3298 else 3299 printf("%u MHz; 64bit\n", clk); 3300 } 3301 } 3302 3303 static int 3304 bge_attach(device_t dev) 3305 { 3306 if_t ifp; 3307 struct bge_softc *sc; 3308 uint32_t hwcfg = 0, misccfg, pcistate; 3309 u_char eaddr[ETHER_ADDR_LEN]; 3310 int capmask, error, reg, rid, trys; 3311 3312 sc = device_get_softc(dev); 3313 sc->bge_dev = dev; 3314 3315 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3316 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3317 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3318 3319 pci_enable_busmaster(dev); 3320 3321 /* 3322 * Allocate control/status registers. 3323 */ 3324 rid = PCIR_BAR(0); 3325 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3326 RF_ACTIVE); 3327 3328 if (sc->bge_res == NULL) { 3329 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3330 error = ENXIO; 3331 goto fail; 3332 } 3333 3334 /* Save various chip information. */ 3335 sc->bge_func_addr = pci_get_function(dev); 3336 sc->bge_chipid = bge_chipid(dev); 3337 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3338 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3339 3340 /* Set default PHY address. */ 3341 sc->bge_phy_addr = 1; 3342 /* 3343 * PHY address mapping for various devices. 3344 * 3345 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3346 * ---------+-------+-------+-------+-------+ 3347 * BCM57XX | 1 | X | X | X | 3348 * BCM5704 | 1 | X | 1 | X | 3349 * BCM5717 | 1 | 8 | 2 | 9 | 3350 * BCM5719 | 1 | 8 | 2 | 9 | 3351 * BCM5720 | 1 | 8 | 2 | 9 | 3352 * 3353 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3354 * ---------+-------+-------+-------+-------+ 3355 * BCM57XX | X | X | X | X | 3356 * BCM5704 | X | X | X | X | 3357 * BCM5717 | X | X | X | X | 3358 * BCM5719 | 3 | 10 | 4 | 11 | 3359 * BCM5720 | X | X | X | X | 3360 * 3361 * Other addresses may respond but they are not 3362 * IEEE compliant PHYs and should be ignored. 3363 */ 3364 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3365 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3366 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3367 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3368 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3369 BGE_SGDIGSTS_IS_SERDES) 3370 sc->bge_phy_addr = sc->bge_func_addr + 8; 3371 else 3372 sc->bge_phy_addr = sc->bge_func_addr + 1; 3373 } else { 3374 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3375 BGE_CPMU_PHY_STRAP_IS_SERDES) 3376 sc->bge_phy_addr = sc->bge_func_addr + 8; 3377 else 3378 sc->bge_phy_addr = sc->bge_func_addr + 1; 3379 } 3380 } 3381 3382 if (bge_has_eaddr(sc)) 3383 sc->bge_flags |= BGE_FLAG_EADDR; 3384 3385 /* Save chipset family. */ 3386 switch (sc->bge_asicrev) { 3387 case BGE_ASICREV_BCM5762: 3388 case BGE_ASICREV_BCM57765: 3389 case BGE_ASICREV_BCM57766: 3390 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3391 /* FALLTHROUGH */ 3392 case BGE_ASICREV_BCM5717: 3393 case BGE_ASICREV_BCM5719: 3394 case BGE_ASICREV_BCM5720: 3395 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3396 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3397 BGE_FLAG_JUMBO_FRAME; 3398 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3399 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3400 /* 3401 * Enable work around for DMA engine miscalculation 3402 * of TXMBUF available space. 3403 */ 3404 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3405 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3406 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3407 /* Jumbo frame on BCM5719 A0 does not work. */ 3408 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3409 } 3410 } 3411 break; 3412 case BGE_ASICREV_BCM5755: 3413 case BGE_ASICREV_BCM5761: 3414 case BGE_ASICREV_BCM5784: 3415 case BGE_ASICREV_BCM5785: 3416 case BGE_ASICREV_BCM5787: 3417 case BGE_ASICREV_BCM57780: 3418 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3419 BGE_FLAG_5705_PLUS; 3420 break; 3421 case BGE_ASICREV_BCM5700: 3422 case BGE_ASICREV_BCM5701: 3423 case BGE_ASICREV_BCM5703: 3424 case BGE_ASICREV_BCM5704: 3425 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3426 break; 3427 case BGE_ASICREV_BCM5714_A0: 3428 case BGE_ASICREV_BCM5780: 3429 case BGE_ASICREV_BCM5714: 3430 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3431 /* FALLTHROUGH */ 3432 case BGE_ASICREV_BCM5750: 3433 case BGE_ASICREV_BCM5752: 3434 case BGE_ASICREV_BCM5906: 3435 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3436 /* FALLTHROUGH */ 3437 case BGE_ASICREV_BCM5705: 3438 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3439 break; 3440 } 3441 3442 /* Identify chips with APE processor. */ 3443 switch (sc->bge_asicrev) { 3444 case BGE_ASICREV_BCM5717: 3445 case BGE_ASICREV_BCM5719: 3446 case BGE_ASICREV_BCM5720: 3447 case BGE_ASICREV_BCM5761: 3448 case BGE_ASICREV_BCM5762: 3449 sc->bge_flags |= BGE_FLAG_APE; 3450 break; 3451 } 3452 3453 /* Chips with APE need BAR2 access for APE registers/memory. */ 3454 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3455 rid = PCIR_BAR(2); 3456 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3457 RF_ACTIVE); 3458 if (sc->bge_res2 == NULL) { 3459 device_printf (sc->bge_dev, 3460 "couldn't map BAR2 memory\n"); 3461 error = ENXIO; 3462 goto fail; 3463 } 3464 3465 /* Enable APE register/memory access by host driver. */ 3466 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3467 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3468 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3469 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3470 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3471 3472 bge_ape_lock_init(sc); 3473 bge_ape_read_fw_ver(sc); 3474 } 3475 3476 /* Add SYSCTLs, requires the chipset family to be set. */ 3477 bge_add_sysctls(sc); 3478 3479 /* Identify the chips that use an CPMU. */ 3480 if (BGE_IS_5717_PLUS(sc) || 3481 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3482 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3483 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3484 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3485 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3486 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3487 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3488 else 3489 sc->bge_mi_mode = BGE_MIMODE_BASE; 3490 /* Enable auto polling for BCM570[0-5]. */ 3491 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3492 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3493 3494 /* 3495 * All Broadcom controllers have 4GB boundary DMA bug. 3496 * Whenever an address crosses a multiple of the 4GB boundary 3497 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3498 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3499 * state machine will lockup and cause the device to hang. 3500 */ 3501 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3502 3503 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3504 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3505 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3506 3507 /* 3508 * BCM5719 cannot handle DMA requests for DMA segments that 3509 * have larger than 4KB in size. However the maximum DMA 3510 * segment size created in DMA tag is 4KB for TSO, so we 3511 * wouldn't encounter the issue here. 3512 */ 3513 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3514 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3515 3516 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3517 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3518 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3519 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3520 sc->bge_flags |= BGE_FLAG_5788; 3521 } 3522 3523 capmask = BMSR_DEFCAPMASK; 3524 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3525 (misccfg == 0x4000 || misccfg == 0x8000)) || 3526 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3527 pci_get_vendor(dev) == BCOM_VENDORID && 3528 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3529 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3530 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3531 (pci_get_vendor(dev) == BCOM_VENDORID && 3532 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3533 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3534 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3535 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3536 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3537 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3538 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3539 /* These chips are 10/100 only. */ 3540 capmask &= ~BMSR_EXTSTAT; 3541 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3542 } 3543 3544 /* 3545 * Some controllers seem to require a special firmware to use 3546 * TSO. But the firmware is not available to FreeBSD and Linux 3547 * claims that the TSO performed by the firmware is slower than 3548 * hardware based TSO. Moreover the firmware based TSO has one 3549 * known bug which can't handle TSO if Ethernet header + IP/TCP 3550 * header is greater than 80 bytes. A workaround for the TSO 3551 * bug exist but it seems it's too expensive than not using 3552 * TSO at all. Some hardwares also have the TSO bug so limit 3553 * the TSO to the controllers that are not affected TSO issues 3554 * (e.g. 5755 or higher). 3555 */ 3556 if (BGE_IS_5717_PLUS(sc)) { 3557 /* BCM5717 requires different TSO configuration. */ 3558 sc->bge_flags |= BGE_FLAG_TSO3; 3559 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3560 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3561 /* TSO on BCM5719 A0 does not work. */ 3562 sc->bge_flags &= ~BGE_FLAG_TSO3; 3563 } 3564 } else if (BGE_IS_5755_PLUS(sc)) { 3565 /* 3566 * BCM5754 and BCM5787 shares the same ASIC id so 3567 * explicit device id check is required. 3568 * Due to unknown reason TSO does not work on BCM5755M. 3569 */ 3570 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3571 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3572 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3573 sc->bge_flags |= BGE_FLAG_TSO; 3574 } 3575 3576 /* 3577 * Check if this is a PCI-X or PCI Express device. 3578 */ 3579 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3580 /* 3581 * Found a PCI Express capabilities register, this 3582 * must be a PCI Express device. 3583 */ 3584 sc->bge_flags |= BGE_FLAG_PCIE; 3585 sc->bge_expcap = reg; 3586 /* Extract supported maximum payload size. */ 3587 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3588 PCIER_DEVICE_CAP, 2); 3589 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3590 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3591 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3592 sc->bge_expmrq = 2048; 3593 else 3594 sc->bge_expmrq = 4096; 3595 pci_set_max_read_req(dev, sc->bge_expmrq); 3596 } else { 3597 /* 3598 * Check if the device is in PCI-X Mode. 3599 * (This bit is not valid on PCI Express controllers.) 3600 */ 3601 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3602 sc->bge_pcixcap = reg; 3603 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3604 BGE_PCISTATE_PCI_BUSMODE) == 0) 3605 sc->bge_flags |= BGE_FLAG_PCIX; 3606 } 3607 3608 /* 3609 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3610 * not actually a MAC controller bug but an issue with the embedded 3611 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3612 */ 3613 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3614 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3615 /* 3616 * Some PCI-X bridges are known to trigger write reordering to 3617 * the mailbox registers. Typical phenomena is watchdog timeouts 3618 * caused by out-of-order TX completions. Enable workaround for 3619 * PCI-X devices that live behind these bridges. 3620 * Note, PCI-X controllers can run in PCI mode so we can't use 3621 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3622 */ 3623 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3624 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3625 /* 3626 * Allocate the interrupt, using MSI if possible. These devices 3627 * support 8 MSI messages, but only the first one is used in 3628 * normal operation. 3629 */ 3630 rid = 0; 3631 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3632 sc->bge_msicap = reg; 3633 reg = 1; 3634 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3635 rid = 1; 3636 sc->bge_flags |= BGE_FLAG_MSI; 3637 } 3638 } 3639 3640 /* 3641 * All controllers except BCM5700 supports tagged status but 3642 * we use tagged status only for MSI case on BCM5717. Otherwise 3643 * MSI on BCM5717 does not work. 3644 */ 3645 #ifndef DEVICE_POLLING 3646 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3647 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3648 #endif 3649 3650 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3651 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3652 3653 if (sc->bge_irq == NULL) { 3654 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3655 error = ENXIO; 3656 goto fail; 3657 } 3658 3659 bge_devinfo(sc); 3660 3661 sc->bge_asf_mode = 0; 3662 /* No ASF if APE present. */ 3663 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3664 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3665 BGE_SRAM_DATA_SIG_MAGIC)) { 3666 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3667 BGE_HWCFG_ASF) { 3668 sc->bge_asf_mode |= ASF_ENABLE; 3669 sc->bge_asf_mode |= ASF_STACKUP; 3670 if (BGE_IS_575X_PLUS(sc)) 3671 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3672 } 3673 } 3674 } 3675 3676 bge_stop_fw(sc); 3677 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3678 if (bge_reset(sc)) { 3679 device_printf(sc->bge_dev, "chip reset failed\n"); 3680 error = ENXIO; 3681 goto fail; 3682 } 3683 3684 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3685 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3686 3687 if (bge_chipinit(sc)) { 3688 device_printf(sc->bge_dev, "chip initialization failed\n"); 3689 error = ENXIO; 3690 goto fail; 3691 } 3692 3693 error = bge_get_eaddr(sc, eaddr); 3694 if (error) { 3695 device_printf(sc->bge_dev, 3696 "failed to read station address\n"); 3697 error = ENXIO; 3698 goto fail; 3699 } 3700 3701 /* 5705 limits RX return ring to 512 entries. */ 3702 if (BGE_IS_5717_PLUS(sc)) 3703 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3704 else if (BGE_IS_5705_PLUS(sc)) 3705 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3706 else 3707 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3708 3709 if (bge_dma_alloc(sc)) { 3710 device_printf(sc->bge_dev, 3711 "failed to allocate DMA resources\n"); 3712 error = ENXIO; 3713 goto fail; 3714 } 3715 3716 /* Set default tuneable values. */ 3717 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3718 sc->bge_rx_coal_ticks = 150; 3719 sc->bge_tx_coal_ticks = 150; 3720 sc->bge_rx_max_coal_bds = 10; 3721 sc->bge_tx_max_coal_bds = 10; 3722 3723 /* Initialize checksum features to use. */ 3724 sc->bge_csum_features = BGE_CSUM_FEATURES; 3725 if (sc->bge_forced_udpcsum != 0) 3726 sc->bge_csum_features |= CSUM_UDP; 3727 3728 /* Set up ifnet structure */ 3729 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3730 if (ifp == NULL) { 3731 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3732 error = ENXIO; 3733 goto fail; 3734 } 3735 if_setsoftc(ifp, sc); 3736 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3737 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3738 if_setioctlfn(ifp, bge_ioctl); 3739 if_setstartfn(ifp, bge_start); 3740 if_setinitfn(ifp, bge_init); 3741 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3742 if_setsendqready(ifp); 3743 if_sethwassist(ifp, sc->bge_csum_features); 3744 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3745 IFCAP_VLAN_MTU); 3746 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3747 if_sethwassistbits(ifp, CSUM_TSO, 0); 3748 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3749 } 3750 #ifdef IFCAP_VLAN_HWCSUM 3751 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 3752 #endif 3753 if_setcapenable(ifp, if_getcapabilities(ifp)); 3754 #ifdef DEVICE_POLLING 3755 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 3756 #endif 3757 3758 /* 3759 * 5700 B0 chips do not support checksumming correctly due 3760 * to hardware bugs. 3761 */ 3762 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3763 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3764 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3765 if_sethwassist(ifp, 0); 3766 } 3767 3768 /* 3769 * Figure out what sort of media we have by checking the 3770 * hardware config word in the first 32k of NIC internal memory, 3771 * or fall back to examining the EEPROM if necessary. 3772 * Note: on some BCM5700 cards, this value appears to be unset. 3773 * If that's the case, we have to rely on identifying the NIC 3774 * by its PCI subsystem ID, as we do below for the SysKonnect 3775 * SK-9D41. 3776 */ 3777 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3778 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3779 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3780 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3781 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3782 sizeof(hwcfg))) { 3783 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3784 error = ENXIO; 3785 goto fail; 3786 } 3787 hwcfg = ntohl(hwcfg); 3788 } 3789 3790 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3791 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3792 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3793 if (BGE_IS_5705_PLUS(sc)) { 3794 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3795 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3796 } else 3797 sc->bge_flags |= BGE_FLAG_TBI; 3798 } 3799 3800 /* Set various PHY bug flags. */ 3801 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3802 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3803 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3804 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3805 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3806 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3807 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3808 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3809 if (pci_get_subvendor(dev) == DELL_VENDORID) 3810 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3811 if ((BGE_IS_5705_PLUS(sc)) && 3812 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3813 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3814 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3815 !BGE_IS_5717_PLUS(sc)) { 3816 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3817 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3818 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3819 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3820 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3821 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3822 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3823 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3824 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3825 } else 3826 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3827 } 3828 3829 /* 3830 * Don't enable Ethernet@WireSpeed for the 5700 or the 3831 * 5705 A0 and A1 chips. 3832 */ 3833 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3834 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3835 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3836 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3837 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3838 3839 if (sc->bge_flags & BGE_FLAG_TBI) { 3840 ifmedia_init_drv(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3841 bge_ifmedia_sts); 3842 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3843 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3844 0, NULL); 3845 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3846 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3847 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3848 } else { 3849 /* 3850 * Do transceiver setup and tell the firmware the 3851 * driver is down so we can try to get access the 3852 * probe if ASF is running. Retry a couple of times 3853 * if we get a conflict with the ASF firmware accessing 3854 * the PHY. 3855 */ 3856 trys = 0; 3857 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3858 again: 3859 bge_asf_driver_up(sc); 3860 3861 error = mii_attach(dev, &sc->bge_miibus, ifp, 3862 (ifm_change_cb_t)bge_ifmedia_upd, 3863 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3864 MII_OFFSET_ANY, MIIF_DOPAUSE); 3865 if (error != 0) { 3866 if (trys++ < 4) { 3867 device_printf(sc->bge_dev, "Try again\n"); 3868 bge_miibus_writereg(sc->bge_dev, 3869 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3870 goto again; 3871 } 3872 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3873 goto fail; 3874 } 3875 3876 /* 3877 * Now tell the firmware we are going up after probing the PHY 3878 */ 3879 if (sc->bge_asf_mode & ASF_STACKUP) 3880 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3881 } 3882 3883 /* 3884 * When using the BCM5701 in PCI-X mode, data corruption has 3885 * been observed in the first few bytes of some received packets. 3886 * Aligning the packet buffer in memory eliminates the corruption. 3887 * Unfortunately, this misaligns the packet payloads. On platforms 3888 * which do not support unaligned accesses, we will realign the 3889 * payloads by copying the received packets. 3890 */ 3891 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3892 sc->bge_flags & BGE_FLAG_PCIX) 3893 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3894 3895 /* 3896 * Call MI attach routine. 3897 */ 3898 ether_ifattach(ifp, eaddr); 3899 3900 /* Tell upper layer we support long frames. */ 3901 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 3902 3903 /* 3904 * Hookup IRQ last. 3905 */ 3906 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3907 /* Take advantage of single-shot MSI. */ 3908 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3909 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3910 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3911 taskqueue_thread_enqueue, &sc->bge_tq); 3912 if (sc->bge_tq == NULL) { 3913 device_printf(dev, "could not create taskqueue.\n"); 3914 ether_ifdetach(ifp); 3915 error = ENOMEM; 3916 goto fail; 3917 } 3918 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3919 "%s taskq", device_get_nameunit(sc->bge_dev)); 3920 if (error != 0) { 3921 device_printf(dev, "could not start threads.\n"); 3922 ether_ifdetach(ifp); 3923 goto fail; 3924 } 3925 error = bus_setup_intr(dev, sc->bge_irq, 3926 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3927 &sc->bge_intrhand); 3928 } else 3929 error = bus_setup_intr(dev, sc->bge_irq, 3930 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3931 &sc->bge_intrhand); 3932 3933 if (error) { 3934 ether_ifdetach(ifp); 3935 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3936 } 3937 3938 fail: 3939 if (error) 3940 bge_detach(dev); 3941 return (error); 3942 } 3943 3944 static int 3945 bge_detach(device_t dev) 3946 { 3947 struct bge_softc *sc; 3948 if_t ifp; 3949 3950 sc = device_get_softc(dev); 3951 ifp = sc->bge_ifp; 3952 3953 #ifdef DEVICE_POLLING 3954 if (if_getcapenable(ifp) & IFCAP_POLLING) 3955 ether_poll_deregister(ifp); 3956 #endif 3957 3958 if (device_is_attached(dev)) { 3959 ether_ifdetach(ifp); 3960 BGE_LOCK(sc); 3961 bge_stop(sc); 3962 BGE_UNLOCK(sc); 3963 callout_drain(&sc->bge_stat_ch); 3964 } 3965 3966 if (sc->bge_tq) 3967 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3968 3969 if (sc->bge_flags & BGE_FLAG_TBI) 3970 ifmedia_removeall(&sc->bge_ifmedia); 3971 else if (sc->bge_miibus != NULL) { 3972 bus_generic_detach(dev); 3973 device_delete_child(dev, sc->bge_miibus); 3974 } 3975 3976 bge_release_resources(sc); 3977 3978 return (0); 3979 } 3980 3981 static void 3982 bge_release_resources(struct bge_softc *sc) 3983 { 3984 device_t dev; 3985 3986 dev = sc->bge_dev; 3987 3988 if (sc->bge_tq != NULL) 3989 taskqueue_free(sc->bge_tq); 3990 3991 if (sc->bge_intrhand != NULL) 3992 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3993 3994 if (sc->bge_irq != NULL) { 3995 bus_release_resource(dev, SYS_RES_IRQ, 3996 rman_get_rid(sc->bge_irq), sc->bge_irq); 3997 pci_release_msi(dev); 3998 } 3999 4000 if (sc->bge_res != NULL) 4001 bus_release_resource(dev, SYS_RES_MEMORY, 4002 rman_get_rid(sc->bge_res), sc->bge_res); 4003 4004 if (sc->bge_res2 != NULL) 4005 bus_release_resource(dev, SYS_RES_MEMORY, 4006 rman_get_rid(sc->bge_res2), sc->bge_res2); 4007 4008 if (sc->bge_ifp != NULL) 4009 if_free(sc->bge_ifp); 4010 4011 bge_dma_free(sc); 4012 4013 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4014 BGE_LOCK_DESTROY(sc); 4015 } 4016 4017 static int 4018 bge_reset(struct bge_softc *sc) 4019 { 4020 device_t dev; 4021 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4022 void (*write_op)(struct bge_softc *, int, int); 4023 uint16_t devctl; 4024 int i; 4025 4026 dev = sc->bge_dev; 4027 4028 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4029 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4030 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4031 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4032 4033 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4034 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4035 if (sc->bge_flags & BGE_FLAG_PCIE) 4036 write_op = bge_writemem_direct; 4037 else 4038 write_op = bge_writemem_ind; 4039 } else 4040 write_op = bge_writereg_ind; 4041 4042 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4043 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4044 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4045 for (i = 0; i < 8000; i++) { 4046 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4047 BGE_NVRAMSWARB_GNT1) 4048 break; 4049 DELAY(20); 4050 } 4051 if (i == 8000) { 4052 if (bootverbose) 4053 device_printf(dev, "NVRAM lock timedout!\n"); 4054 } 4055 } 4056 /* Take APE lock when performing reset. */ 4057 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4058 4059 /* Save some important PCI state. */ 4060 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4061 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4062 4063 pci_write_config(dev, BGE_PCI_MISC_CTL, 4064 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4065 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4066 4067 /* Disable fastboot on controllers that support it. */ 4068 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4069 BGE_IS_5755_PLUS(sc)) { 4070 if (bootverbose) 4071 device_printf(dev, "Disabling fastboot\n"); 4072 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4073 } 4074 4075 /* 4076 * Write the magic number to SRAM at offset 0xB50. 4077 * When firmware finishes its initialization it will 4078 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4079 */ 4080 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4081 4082 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4083 4084 /* XXX: Broadcom Linux driver. */ 4085 if (sc->bge_flags & BGE_FLAG_PCIE) { 4086 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4087 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4088 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4089 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4090 } 4091 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4092 /* Prevent PCIE link training during global reset */ 4093 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4094 reset |= 1 << 29; 4095 } 4096 } 4097 4098 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4099 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4100 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4101 val | BGE_VCPU_STATUS_DRV_RESET); 4102 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4103 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4104 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4105 } 4106 4107 /* 4108 * Set GPHY Power Down Override to leave GPHY 4109 * powered up in D0 uninitialized. 4110 */ 4111 if (BGE_IS_5705_PLUS(sc) && 4112 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4113 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4114 4115 /* Issue global reset */ 4116 write_op(sc, BGE_MISC_CFG, reset); 4117 4118 if (sc->bge_flags & BGE_FLAG_PCIE) 4119 DELAY(100 * 1000); 4120 else 4121 DELAY(1000); 4122 4123 /* XXX: Broadcom Linux driver. */ 4124 if (sc->bge_flags & BGE_FLAG_PCIE) { 4125 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4126 DELAY(500000); /* wait for link training to complete */ 4127 val = pci_read_config(dev, 0xC4, 4); 4128 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4129 } 4130 devctl = pci_read_config(dev, 4131 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4132 /* Clear enable no snoop and disable relaxed ordering. */ 4133 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4134 PCIEM_CTL_NOSNOOP_ENABLE); 4135 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4136 devctl, 2); 4137 pci_set_max_read_req(dev, sc->bge_expmrq); 4138 /* Clear error status. */ 4139 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4140 PCIEM_STA_CORRECTABLE_ERROR | 4141 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4142 PCIEM_STA_UNSUPPORTED_REQ, 2); 4143 } 4144 4145 /* Reset some of the PCI state that got zapped by reset. */ 4146 pci_write_config(dev, BGE_PCI_MISC_CTL, 4147 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4148 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4149 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4150 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4151 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4152 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4154 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4155 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4156 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4157 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4158 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4159 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4160 /* 4161 * Disable PCI-X relaxed ordering to ensure status block update 4162 * comes first then packet buffer DMA. Otherwise driver may 4163 * read stale status block. 4164 */ 4165 if (sc->bge_flags & BGE_FLAG_PCIX) { 4166 devctl = pci_read_config(dev, 4167 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4168 devctl &= ~PCIXM_COMMAND_ERO; 4169 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4170 devctl &= ~PCIXM_COMMAND_MAX_READ; 4171 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4172 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4173 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4174 PCIXM_COMMAND_MAX_READ); 4175 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4176 } 4177 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4178 devctl, 2); 4179 } 4180 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4181 if (BGE_IS_5714_FAMILY(sc)) { 4182 /* This chip disables MSI on reset. */ 4183 if (sc->bge_flags & BGE_FLAG_MSI) { 4184 val = pci_read_config(dev, 4185 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4186 pci_write_config(dev, 4187 sc->bge_msicap + PCIR_MSI_CTRL, 4188 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4189 val = CSR_READ_4(sc, BGE_MSI_MODE); 4190 CSR_WRITE_4(sc, BGE_MSI_MODE, 4191 val | BGE_MSIMODE_ENABLE); 4192 } 4193 val = CSR_READ_4(sc, BGE_MARB_MODE); 4194 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4195 } else 4196 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4197 4198 /* Fix up byte swapping. */ 4199 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4200 4201 val = CSR_READ_4(sc, BGE_MAC_MODE); 4202 val = (val & ~mac_mode_mask) | mac_mode; 4203 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4204 DELAY(40); 4205 4206 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4207 4208 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4209 for (i = 0; i < BGE_TIMEOUT; i++) { 4210 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4211 if (val & BGE_VCPU_STATUS_INIT_DONE) 4212 break; 4213 DELAY(100); 4214 } 4215 if (i == BGE_TIMEOUT) { 4216 device_printf(dev, "reset timed out\n"); 4217 return (1); 4218 } 4219 } else { 4220 /* 4221 * Poll until we see the 1's complement of the magic number. 4222 * This indicates that the firmware initialization is complete. 4223 * We expect this to fail if no chip containing the Ethernet 4224 * address is fitted though. 4225 */ 4226 for (i = 0; i < BGE_TIMEOUT; i++) { 4227 DELAY(10); 4228 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4229 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4230 break; 4231 } 4232 4233 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4234 device_printf(dev, 4235 "firmware handshake timed out, found 0x%08x\n", 4236 val); 4237 /* BCM57765 A0 needs additional time before accessing. */ 4238 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4239 DELAY(10 * 1000); /* XXX */ 4240 } 4241 4242 /* 4243 * The 5704 in TBI mode apparently needs some special 4244 * adjustment to insure the SERDES drive level is set 4245 * to 1.2V. 4246 */ 4247 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4248 sc->bge_flags & BGE_FLAG_TBI) { 4249 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4250 val = (val & ~0xFFF) | 0x880; 4251 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4252 } 4253 4254 /* XXX: Broadcom Linux driver. */ 4255 if (sc->bge_flags & BGE_FLAG_PCIE && 4256 !BGE_IS_5717_PLUS(sc) && 4257 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4258 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4259 /* Enable Data FIFO protection. */ 4260 val = CSR_READ_4(sc, 0x7C00); 4261 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4262 } 4263 4264 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4265 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4266 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4267 4268 return (0); 4269 } 4270 4271 static __inline void 4272 bge_rxreuse_std(struct bge_softc *sc, int i) 4273 { 4274 struct bge_rx_bd *r; 4275 4276 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4277 r->bge_flags = BGE_RXBDFLAG_END; 4278 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4279 r->bge_idx = i; 4280 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4281 } 4282 4283 static __inline void 4284 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4285 { 4286 struct bge_extrx_bd *r; 4287 4288 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4289 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4290 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4291 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4292 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4293 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4294 r->bge_idx = i; 4295 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4296 } 4297 4298 /* 4299 * Frame reception handling. This is called if there's a frame 4300 * on the receive return list. 4301 * 4302 * Note: we have to be able to handle two possibilities here: 4303 * 1) the frame is from the jumbo receive ring 4304 * 2) the frame is from the standard receive ring 4305 */ 4306 4307 static int 4308 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4309 { 4310 if_t ifp; 4311 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4312 uint16_t rx_cons; 4313 4314 rx_cons = sc->bge_rx_saved_considx; 4315 4316 /* Nothing to do. */ 4317 if (rx_cons == rx_prod) 4318 return (rx_npkts); 4319 4320 ifp = sc->bge_ifp; 4321 4322 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4323 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4324 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4325 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4326 if (BGE_IS_JUMBO_CAPABLE(sc) && 4327 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4328 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4329 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4330 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4331 4332 while (rx_cons != rx_prod) { 4333 struct bge_rx_bd *cur_rx; 4334 uint32_t rxidx; 4335 struct mbuf *m = NULL; 4336 uint16_t vlan_tag = 0; 4337 int have_tag = 0; 4338 4339 #ifdef DEVICE_POLLING 4340 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4341 if (sc->rxcycles <= 0) 4342 break; 4343 sc->rxcycles--; 4344 } 4345 #endif 4346 4347 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4348 4349 rxidx = cur_rx->bge_idx; 4350 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4351 4352 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4353 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4354 have_tag = 1; 4355 vlan_tag = cur_rx->bge_vlan_tag; 4356 } 4357 4358 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4359 jumbocnt++; 4360 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4361 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4362 bge_rxreuse_jumbo(sc, rxidx); 4363 continue; 4364 } 4365 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4366 bge_rxreuse_jumbo(sc, rxidx); 4367 if_inciqdrops(ifp, 1); 4368 continue; 4369 } 4370 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4371 } else { 4372 stdcnt++; 4373 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4374 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4375 bge_rxreuse_std(sc, rxidx); 4376 continue; 4377 } 4378 if (bge_newbuf_std(sc, rxidx) != 0) { 4379 bge_rxreuse_std(sc, rxidx); 4380 if_inciqdrops(ifp, 1); 4381 continue; 4382 } 4383 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4384 } 4385 4386 if_incipackets(ifp, 1); 4387 #ifndef __NO_STRICT_ALIGNMENT 4388 /* 4389 * For architectures with strict alignment we must make sure 4390 * the payload is aligned. 4391 */ 4392 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4393 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4394 cur_rx->bge_len); 4395 m->m_data += ETHER_ALIGN; 4396 } 4397 #endif 4398 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4399 m->m_pkthdr.rcvif = ifp; 4400 4401 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 4402 bge_rxcsum(sc, cur_rx, m); 4403 4404 /* 4405 * If we received a packet with a vlan tag, 4406 * attach that information to the packet. 4407 */ 4408 if (have_tag) { 4409 m->m_pkthdr.ether_vtag = vlan_tag; 4410 m->m_flags |= M_VLANTAG; 4411 } 4412 4413 if (holdlck != 0) { 4414 BGE_UNLOCK(sc); 4415 if_input(ifp, m); 4416 BGE_LOCK(sc); 4417 } else 4418 if_input(ifp, m); 4419 rx_npkts++; 4420 4421 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4422 return (rx_npkts); 4423 } 4424 4425 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4426 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4427 if (stdcnt > 0) 4428 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4429 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4430 4431 if (jumbocnt > 0) 4432 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4433 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4434 4435 sc->bge_rx_saved_considx = rx_cons; 4436 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4437 if (stdcnt) 4438 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4439 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4440 if (jumbocnt) 4441 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4442 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4443 #ifdef notyet 4444 /* 4445 * This register wraps very quickly under heavy packet drops. 4446 * If you need correct statistics, you can enable this check. 4447 */ 4448 if (BGE_IS_5705_PLUS(sc)) 4449 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4450 #endif 4451 return (rx_npkts); 4452 } 4453 4454 static void 4455 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4456 { 4457 4458 if (BGE_IS_5717_PLUS(sc)) { 4459 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4460 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4461 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4462 if ((cur_rx->bge_error_flag & 4463 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4464 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4465 } 4466 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4467 m->m_pkthdr.csum_data = 4468 cur_rx->bge_tcp_udp_csum; 4469 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4470 CSUM_PSEUDO_HDR; 4471 } 4472 } 4473 } else { 4474 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4475 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4476 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4477 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4478 } 4479 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4480 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4481 m->m_pkthdr.csum_data = 4482 cur_rx->bge_tcp_udp_csum; 4483 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4484 CSUM_PSEUDO_HDR; 4485 } 4486 } 4487 } 4488 4489 static void 4490 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4491 { 4492 struct bge_tx_bd *cur_tx; 4493 if_t ifp; 4494 4495 BGE_LOCK_ASSERT(sc); 4496 4497 /* Nothing to do. */ 4498 if (sc->bge_tx_saved_considx == tx_cons) 4499 return; 4500 4501 ifp = sc->bge_ifp; 4502 4503 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4504 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4505 /* 4506 * Go through our tx ring and free mbufs for those 4507 * frames that have been sent. 4508 */ 4509 while (sc->bge_tx_saved_considx != tx_cons) { 4510 uint32_t idx; 4511 4512 idx = sc->bge_tx_saved_considx; 4513 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4514 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4515 if_incopackets(ifp, 1); 4516 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4517 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4518 sc->bge_cdata.bge_tx_dmamap[idx], 4519 BUS_DMASYNC_POSTWRITE); 4520 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4521 sc->bge_cdata.bge_tx_dmamap[idx]); 4522 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4523 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4524 } 4525 sc->bge_txcnt--; 4526 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4527 } 4528 4529 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4530 if (sc->bge_txcnt == 0) 4531 sc->bge_timer = 0; 4532 } 4533 4534 #ifdef DEVICE_POLLING 4535 static int 4536 bge_poll(if_t ifp, enum poll_cmd cmd, int count) 4537 { 4538 struct bge_softc *sc = if_getsoftc(ifp); 4539 uint16_t rx_prod, tx_cons; 4540 uint32_t statusword; 4541 int rx_npkts = 0; 4542 4543 BGE_LOCK(sc); 4544 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4545 BGE_UNLOCK(sc); 4546 return (rx_npkts); 4547 } 4548 4549 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4550 sc->bge_cdata.bge_status_map, 4551 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4552 /* Fetch updates from the status block. */ 4553 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4554 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4555 4556 statusword = sc->bge_ldata.bge_status_block->bge_status; 4557 /* Clear the status so the next pass only sees the changes. */ 4558 sc->bge_ldata.bge_status_block->bge_status = 0; 4559 4560 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4561 sc->bge_cdata.bge_status_map, 4562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4563 4564 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4565 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4566 sc->bge_link_evt++; 4567 4568 if (cmd == POLL_AND_CHECK_STATUS) 4569 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4570 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4571 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4572 bge_link_upd(sc); 4573 4574 sc->rxcycles = count; 4575 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4576 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4577 BGE_UNLOCK(sc); 4578 return (rx_npkts); 4579 } 4580 bge_txeof(sc, tx_cons); 4581 if (!if_sendq_empty(ifp)) 4582 bge_start_locked(ifp); 4583 4584 BGE_UNLOCK(sc); 4585 return (rx_npkts); 4586 } 4587 #endif /* DEVICE_POLLING */ 4588 4589 static int 4590 bge_msi_intr(void *arg) 4591 { 4592 struct bge_softc *sc; 4593 4594 sc = (struct bge_softc *)arg; 4595 /* 4596 * This interrupt is not shared and controller already 4597 * disabled further interrupt. 4598 */ 4599 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4600 return (FILTER_HANDLED); 4601 } 4602 4603 static void 4604 bge_intr_task(void *arg, int pending) 4605 { 4606 struct bge_softc *sc; 4607 if_t ifp; 4608 uint32_t status, status_tag; 4609 uint16_t rx_prod, tx_cons; 4610 4611 sc = (struct bge_softc *)arg; 4612 ifp = sc->bge_ifp; 4613 4614 BGE_LOCK(sc); 4615 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 4616 BGE_UNLOCK(sc); 4617 return; 4618 } 4619 4620 /* Get updated status block. */ 4621 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4622 sc->bge_cdata.bge_status_map, 4623 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4624 4625 /* Save producer/consumer indices. */ 4626 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4627 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4628 status = sc->bge_ldata.bge_status_block->bge_status; 4629 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4630 /* Dirty the status flag. */ 4631 sc->bge_ldata.bge_status_block->bge_status = 0; 4632 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4633 sc->bge_cdata.bge_status_map, 4634 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4635 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4636 status_tag = 0; 4637 4638 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4639 bge_link_upd(sc); 4640 4641 /* Let controller work. */ 4642 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4643 4644 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4645 sc->bge_rx_saved_considx != rx_prod) { 4646 /* Check RX return ring producer/consumer. */ 4647 BGE_UNLOCK(sc); 4648 bge_rxeof(sc, rx_prod, 0); 4649 BGE_LOCK(sc); 4650 } 4651 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4652 /* Check TX ring producer/consumer. */ 4653 bge_txeof(sc, tx_cons); 4654 if (!if_sendq_empty(ifp)) 4655 bge_start_locked(ifp); 4656 } 4657 BGE_UNLOCK(sc); 4658 } 4659 4660 static void 4661 bge_intr(void *xsc) 4662 { 4663 struct bge_softc *sc; 4664 if_t ifp; 4665 uint32_t statusword; 4666 uint16_t rx_prod, tx_cons; 4667 4668 sc = xsc; 4669 4670 BGE_LOCK(sc); 4671 4672 ifp = sc->bge_ifp; 4673 4674 #ifdef DEVICE_POLLING 4675 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4676 BGE_UNLOCK(sc); 4677 return; 4678 } 4679 #endif 4680 4681 /* 4682 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4683 * disable interrupts by writing nonzero like we used to, since with 4684 * our current organization this just gives complications and 4685 * pessimizations for re-enabling interrupts. We used to have races 4686 * instead of the necessary complications. Disabling interrupts 4687 * would just reduce the chance of a status update while we are 4688 * running (by switching to the interrupt-mode coalescence 4689 * parameters), but this chance is already very low so it is more 4690 * efficient to get another interrupt than prevent it. 4691 * 4692 * We do the ack first to ensure another interrupt if there is a 4693 * status update after the ack. We don't check for the status 4694 * changing later because it is more efficient to get another 4695 * interrupt than prevent it, not quite as above (not checking is 4696 * a smaller optimization than not toggling the interrupt enable, 4697 * since checking doesn't involve PCI accesses and toggling require 4698 * the status check). So toggling would probably be a pessimization 4699 * even with MSI. It would only be needed for using a task queue. 4700 */ 4701 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4702 4703 /* 4704 * Do the mandatory PCI flush as well as get the link status. 4705 */ 4706 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4707 4708 /* Make sure the descriptor ring indexes are coherent. */ 4709 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4710 sc->bge_cdata.bge_status_map, 4711 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4712 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4713 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4714 sc->bge_ldata.bge_status_block->bge_status = 0; 4715 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4716 sc->bge_cdata.bge_status_map, 4717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4718 4719 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4720 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4721 statusword || sc->bge_link_evt) 4722 bge_link_upd(sc); 4723 4724 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4725 /* Check RX return ring producer/consumer. */ 4726 bge_rxeof(sc, rx_prod, 1); 4727 } 4728 4729 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4730 /* Check TX ring producer/consumer. */ 4731 bge_txeof(sc, tx_cons); 4732 } 4733 4734 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4735 !if_sendq_empty(ifp)) 4736 bge_start_locked(ifp); 4737 4738 BGE_UNLOCK(sc); 4739 } 4740 4741 static void 4742 bge_asf_driver_up(struct bge_softc *sc) 4743 { 4744 if (sc->bge_asf_mode & ASF_STACKUP) { 4745 /* Send ASF heartbeat aprox. every 2s */ 4746 if (sc->bge_asf_count) 4747 sc->bge_asf_count --; 4748 else { 4749 sc->bge_asf_count = 2; 4750 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4751 BGE_FW_CMD_DRV_ALIVE); 4752 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4753 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4754 BGE_FW_HB_TIMEOUT_SEC); 4755 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4756 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4757 BGE_RX_CPU_DRV_EVENT); 4758 } 4759 } 4760 } 4761 4762 static void 4763 bge_tick(void *xsc) 4764 { 4765 struct bge_softc *sc = xsc; 4766 struct mii_data *mii = NULL; 4767 4768 BGE_LOCK_ASSERT(sc); 4769 4770 /* Synchronize with possible callout reset/stop. */ 4771 if (callout_pending(&sc->bge_stat_ch) || 4772 !callout_active(&sc->bge_stat_ch)) 4773 return; 4774 4775 if (BGE_IS_5705_PLUS(sc)) 4776 bge_stats_update_regs(sc); 4777 else 4778 bge_stats_update(sc); 4779 4780 /* XXX Add APE heartbeat check here? */ 4781 4782 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4783 mii = device_get_softc(sc->bge_miibus); 4784 /* 4785 * Do not touch PHY if we have link up. This could break 4786 * IPMI/ASF mode or produce extra input errors 4787 * (extra errors was reported for bcm5701 & bcm5704). 4788 */ 4789 if (!sc->bge_link) 4790 mii_tick(mii); 4791 } else { 4792 /* 4793 * Since in TBI mode auto-polling can't be used we should poll 4794 * link status manually. Here we register pending link event 4795 * and trigger interrupt. 4796 */ 4797 #ifdef DEVICE_POLLING 4798 /* In polling mode we poll link state in bge_poll(). */ 4799 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 4800 #endif 4801 { 4802 sc->bge_link_evt++; 4803 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4804 sc->bge_flags & BGE_FLAG_5788) 4805 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4806 else 4807 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4808 } 4809 } 4810 4811 bge_asf_driver_up(sc); 4812 bge_watchdog(sc); 4813 4814 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4815 } 4816 4817 static void 4818 bge_stats_update_regs(struct bge_softc *sc) 4819 { 4820 if_t ifp; 4821 struct bge_mac_stats *stats; 4822 uint32_t val; 4823 4824 ifp = sc->bge_ifp; 4825 stats = &sc->bge_mac_stats; 4826 4827 stats->ifHCOutOctets += 4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4829 stats->etherStatsCollisions += 4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4831 stats->outXonSent += 4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4833 stats->outXoffSent += 4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4835 stats->dot3StatsInternalMacTransmitErrors += 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4837 stats->dot3StatsSingleCollisionFrames += 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4839 stats->dot3StatsMultipleCollisionFrames += 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4841 stats->dot3StatsDeferredTransmissions += 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4843 stats->dot3StatsExcessiveCollisions += 4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4845 stats->dot3StatsLateCollisions += 4846 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4847 stats->ifHCOutUcastPkts += 4848 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4849 stats->ifHCOutMulticastPkts += 4850 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4851 stats->ifHCOutBroadcastPkts += 4852 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4853 4854 stats->ifHCInOctets += 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4856 stats->etherStatsFragments += 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4858 stats->ifHCInUcastPkts += 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4860 stats->ifHCInMulticastPkts += 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4862 stats->ifHCInBroadcastPkts += 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4864 stats->dot3StatsFCSErrors += 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4866 stats->dot3StatsAlignmentErrors += 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4868 stats->xonPauseFramesReceived += 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4870 stats->xoffPauseFramesReceived += 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4872 stats->macControlFramesReceived += 4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4874 stats->xoffStateEntered += 4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4876 stats->dot3StatsFramesTooLong += 4877 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4878 stats->etherStatsJabbers += 4879 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4880 stats->etherStatsUndersizePkts += 4881 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4882 4883 stats->FramesDroppedDueToFilters += 4884 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4885 stats->DmaWriteQueueFull += 4886 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4887 stats->DmaWriteHighPriQueueFull += 4888 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4889 stats->NoMoreRxBDs += 4890 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4891 /* 4892 * XXX 4893 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4894 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4895 * includes number of unwanted multicast frames. This comes 4896 * from silicon bug and known workaround to get rough(not 4897 * exact) counter is to enable interrupt on MBUF low water 4898 * attention. This can be accomplished by setting 4899 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4900 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4901 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4902 * However that change would generate more interrupts and 4903 * there are still possibilities of losing multiple frames 4904 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4905 * Given that the workaround still would not get correct 4906 * counter I don't think it's worth to implement it. So 4907 * ignore reading the counter on controllers that have the 4908 * silicon bug. 4909 */ 4910 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4911 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4912 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4913 stats->InputDiscards += 4914 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4915 stats->InputErrors += 4916 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4917 stats->RecvThresholdHit += 4918 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4919 4920 if_setcollisions(ifp, (u_long)stats->etherStatsCollisions); 4921 if_setierrors(ifp, (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4922 stats->InputErrors)); 4923 4924 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4925 /* 4926 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4927 * frames, it's safe to disable workaround for DMA engine's 4928 * miscalculation of TXMBUF space. 4929 */ 4930 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4931 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4932 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4933 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4934 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4935 else 4936 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4937 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4938 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4939 } 4940 } 4941 } 4942 4943 static void 4944 bge_stats_clear_regs(struct bge_softc *sc) 4945 { 4946 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4953 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4954 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4955 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4956 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4957 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4958 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4959 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4960 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4968 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4969 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4970 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4971 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4972 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4973 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4974 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4975 4976 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4977 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4978 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4979 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4980 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4981 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4982 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4983 } 4984 4985 static void 4986 bge_stats_update(struct bge_softc *sc) 4987 { 4988 if_t ifp; 4989 bus_size_t stats; 4990 uint32_t cnt; /* current register value */ 4991 4992 ifp = sc->bge_ifp; 4993 4994 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4995 4996 #define READ_STAT(sc, stats, stat) \ 4997 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4998 4999 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 5000 if_inccollisions(ifp, (uint32_t)(cnt - sc->bge_tx_collisions)); 5001 sc->bge_tx_collisions = cnt; 5002 5003 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 5004 if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_nobds)); 5005 sc->bge_rx_nobds = cnt; 5006 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5007 if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_inerrs)); 5008 sc->bge_rx_inerrs = cnt; 5009 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5010 if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_discards)); 5011 sc->bge_rx_discards = cnt; 5012 5013 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5014 if_incoerrors(ifp, (uint32_t)(cnt - sc->bge_tx_discards)); 5015 sc->bge_tx_discards = cnt; 5016 5017 #undef READ_STAT 5018 } 5019 5020 /* 5021 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5022 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5023 * but when such padded frames employ the bge IP/TCP checksum offload, 5024 * the hardware checksum assist gives incorrect results (possibly 5025 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5026 * If we pad such runts with zeros, the onboard checksum comes out correct. 5027 */ 5028 static __inline int 5029 bge_cksum_pad(struct mbuf *m) 5030 { 5031 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5032 struct mbuf *last; 5033 5034 /* If there's only the packet-header and we can pad there, use it. */ 5035 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5036 M_TRAILINGSPACE(m) >= padlen) { 5037 last = m; 5038 } else { 5039 /* 5040 * Walk packet chain to find last mbuf. We will either 5041 * pad there, or append a new mbuf and pad it. 5042 */ 5043 for (last = m; last->m_next != NULL; last = last->m_next); 5044 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5045 /* Allocate new empty mbuf, pad it. Compact later. */ 5046 struct mbuf *n; 5047 5048 MGET(n, M_NOWAIT, MT_DATA); 5049 if (n == NULL) 5050 return (ENOBUFS); 5051 n->m_len = 0; 5052 last->m_next = n; 5053 last = n; 5054 } 5055 } 5056 5057 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5058 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5059 last->m_len += padlen; 5060 m->m_pkthdr.len += padlen; 5061 5062 return (0); 5063 } 5064 5065 static struct mbuf * 5066 bge_check_short_dma(struct mbuf *m) 5067 { 5068 struct mbuf *n; 5069 int found; 5070 5071 /* 5072 * If device receive two back-to-back send BDs with less than 5073 * or equal to 8 total bytes then the device may hang. The two 5074 * back-to-back send BDs must in the same frame for this failure 5075 * to occur. Scan mbuf chains and see whether two back-to-back 5076 * send BDs are there. If this is the case, allocate new mbuf 5077 * and copy the frame to workaround the silicon bug. 5078 */ 5079 for (n = m, found = 0; n != NULL; n = n->m_next) { 5080 if (n->m_len < 8) { 5081 found++; 5082 if (found > 1) 5083 break; 5084 continue; 5085 } 5086 found = 0; 5087 } 5088 5089 if (found > 1) { 5090 n = m_defrag(m, M_NOWAIT); 5091 if (n == NULL) 5092 m_freem(m); 5093 } else 5094 n = m; 5095 return (n); 5096 } 5097 5098 static struct mbuf * 5099 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5100 uint16_t *flags) 5101 { 5102 struct ip *ip; 5103 struct tcphdr *tcp; 5104 struct mbuf *n; 5105 uint16_t hlen; 5106 uint32_t poff; 5107 5108 if (M_WRITABLE(m) == 0) { 5109 /* Get a writable copy. */ 5110 n = m_dup(m, M_NOWAIT); 5111 m_freem(m); 5112 if (n == NULL) 5113 return (NULL); 5114 m = n; 5115 } 5116 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5117 if (m == NULL) 5118 return (NULL); 5119 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5120 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5121 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5122 if (m == NULL) 5123 return (NULL); 5124 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5125 m = m_pullup(m, poff + (tcp->th_off << 2)); 5126 if (m == NULL) 5127 return (NULL); 5128 /* 5129 * It seems controller doesn't modify IP length and TCP pseudo 5130 * checksum. These checksum computed by upper stack should be 0. 5131 */ 5132 *mss = m->m_pkthdr.tso_segsz; 5133 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5134 ip->ip_sum = 0; 5135 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5136 /* Clear pseudo checksum computed by TCP stack. */ 5137 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5138 tcp->th_sum = 0; 5139 /* 5140 * Broadcom controllers uses different descriptor format for 5141 * TSO depending on ASIC revision. Due to TSO-capable firmware 5142 * license issue and lower performance of firmware based TSO 5143 * we only support hardware based TSO. 5144 */ 5145 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5146 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5147 if (sc->bge_flags & BGE_FLAG_TSO3) { 5148 /* 5149 * For BCM5717 and newer controllers, hardware based TSO 5150 * uses the 14 lower bits of the bge_mss field to store the 5151 * MSS and the upper 2 bits to store the lowest 2 bits of 5152 * the IP/TCP header length. The upper 6 bits of the header 5153 * length are stored in the bge_flags[14:10,4] field. Jumbo 5154 * frames are supported. 5155 */ 5156 *mss |= ((hlen & 0x3) << 14); 5157 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5158 } else { 5159 /* 5160 * For BCM5755 and newer controllers, hardware based TSO uses 5161 * the lower 11 bits to store the MSS and the upper 5 bits to 5162 * store the IP/TCP header length. Jumbo frames are not 5163 * supported. 5164 */ 5165 *mss |= (hlen << 11); 5166 } 5167 return (m); 5168 } 5169 5170 /* 5171 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5172 * pointers to descriptors. 5173 */ 5174 static int 5175 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5176 { 5177 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5178 bus_dmamap_t map; 5179 struct bge_tx_bd *d; 5180 struct mbuf *m = *m_head; 5181 uint32_t idx = *txidx; 5182 uint16_t csum_flags, mss, vlan_tag; 5183 int nsegs, i, error; 5184 5185 csum_flags = 0; 5186 mss = 0; 5187 vlan_tag = 0; 5188 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5189 m->m_next != NULL) { 5190 *m_head = bge_check_short_dma(m); 5191 if (*m_head == NULL) 5192 return (ENOBUFS); 5193 m = *m_head; 5194 } 5195 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5196 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5197 if (*m_head == NULL) 5198 return (ENOBUFS); 5199 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5200 BGE_TXBDFLAG_CPU_POST_DMA; 5201 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5202 if (m->m_pkthdr.csum_flags & CSUM_IP) 5203 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5204 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5205 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5206 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5207 (error = bge_cksum_pad(m)) != 0) { 5208 m_freem(m); 5209 *m_head = NULL; 5210 return (error); 5211 } 5212 } 5213 } 5214 5215 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5216 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5217 m->m_pkthdr.len > ETHER_MAX_LEN) 5218 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5219 if (sc->bge_forced_collapse > 0 && 5220 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5221 /* 5222 * Forcedly collapse mbuf chains to overcome hardware 5223 * limitation which only support a single outstanding 5224 * DMA read operation. 5225 */ 5226 if (sc->bge_forced_collapse == 1) 5227 m = m_defrag(m, M_NOWAIT); 5228 else 5229 m = m_collapse(m, M_NOWAIT, 5230 sc->bge_forced_collapse); 5231 if (m == NULL) 5232 m = *m_head; 5233 *m_head = m; 5234 } 5235 } 5236 5237 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5238 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5239 &nsegs, BUS_DMA_NOWAIT); 5240 if (error == EFBIG) { 5241 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5242 if (m == NULL) { 5243 m_freem(*m_head); 5244 *m_head = NULL; 5245 return (ENOBUFS); 5246 } 5247 *m_head = m; 5248 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5249 m, segs, &nsegs, BUS_DMA_NOWAIT); 5250 if (error) { 5251 m_freem(m); 5252 *m_head = NULL; 5253 return (error); 5254 } 5255 } else if (error != 0) 5256 return (error); 5257 5258 /* Check if we have enough free send BDs. */ 5259 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5260 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5261 return (ENOBUFS); 5262 } 5263 5264 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5265 5266 if (m->m_flags & M_VLANTAG) { 5267 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5268 vlan_tag = m->m_pkthdr.ether_vtag; 5269 } 5270 5271 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5272 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5273 /* 5274 * 5725 family of devices corrupts TSO packets when TSO DMA 5275 * buffers cross into regions which are within MSS bytes of 5276 * a 4GB boundary. If we encounter the condition, drop the 5277 * packet. 5278 */ 5279 for (i = 0; ; i++) { 5280 d = &sc->bge_ldata.bge_tx_ring[idx]; 5281 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5282 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5283 d->bge_len = segs[i].ds_len; 5284 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5285 d->bge_addr.bge_addr_lo) 5286 break; 5287 d->bge_flags = csum_flags; 5288 d->bge_vlan_tag = vlan_tag; 5289 d->bge_mss = mss; 5290 if (i == nsegs - 1) 5291 break; 5292 BGE_INC(idx, BGE_TX_RING_CNT); 5293 } 5294 if (i != nsegs - 1) { 5295 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5296 BUS_DMASYNC_POSTWRITE); 5297 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5298 m_freem(*m_head); 5299 *m_head = NULL; 5300 return (EIO); 5301 } 5302 } else { 5303 for (i = 0; ; i++) { 5304 d = &sc->bge_ldata.bge_tx_ring[idx]; 5305 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5306 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5307 d->bge_len = segs[i].ds_len; 5308 d->bge_flags = csum_flags; 5309 d->bge_vlan_tag = vlan_tag; 5310 d->bge_mss = mss; 5311 if (i == nsegs - 1) 5312 break; 5313 BGE_INC(idx, BGE_TX_RING_CNT); 5314 } 5315 } 5316 5317 /* Mark the last segment as end of packet... */ 5318 d->bge_flags |= BGE_TXBDFLAG_END; 5319 5320 /* 5321 * Insure that the map for this transmission 5322 * is placed at the array index of the last descriptor 5323 * in this chain. 5324 */ 5325 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5326 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5327 sc->bge_cdata.bge_tx_chain[idx] = m; 5328 sc->bge_txcnt += nsegs; 5329 5330 BGE_INC(idx, BGE_TX_RING_CNT); 5331 *txidx = idx; 5332 5333 return (0); 5334 } 5335 5336 /* 5337 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5338 * to the mbuf data regions directly in the transmit descriptors. 5339 */ 5340 static void 5341 bge_start_locked(if_t ifp) 5342 { 5343 struct bge_softc *sc; 5344 struct mbuf *m_head; 5345 uint32_t prodidx; 5346 int count; 5347 5348 sc = if_getsoftc(ifp); 5349 BGE_LOCK_ASSERT(sc); 5350 5351 if (!sc->bge_link || 5352 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5353 IFF_DRV_RUNNING) 5354 return; 5355 5356 prodidx = sc->bge_tx_prodidx; 5357 5358 for (count = 0; !if_sendq_empty(ifp);) { 5359 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5360 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5361 break; 5362 } 5363 m_head = if_dequeue(ifp); 5364 if (m_head == NULL) 5365 break; 5366 5367 /* 5368 * Pack the data into the transmit ring. If we 5369 * don't have room, set the OACTIVE flag and wait 5370 * for the NIC to drain the ring. 5371 */ 5372 if (bge_encap(sc, &m_head, &prodidx)) { 5373 if (m_head == NULL) 5374 break; 5375 if_sendq_prepend(ifp, m_head); 5376 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5377 break; 5378 } 5379 ++count; 5380 5381 /* 5382 * If there's a BPF listener, bounce a copy of this frame 5383 * to him. 5384 */ 5385 if_bpfmtap(ifp, m_head); 5386 } 5387 5388 if (count > 0) { 5389 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5390 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5391 /* Transmit. */ 5392 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5393 /* 5700 b2 errata */ 5394 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5395 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5396 5397 sc->bge_tx_prodidx = prodidx; 5398 5399 /* 5400 * Set a timeout in case the chip goes out to lunch. 5401 */ 5402 sc->bge_timer = BGE_TX_TIMEOUT; 5403 } 5404 } 5405 5406 /* 5407 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5408 * to the mbuf data regions directly in the transmit descriptors. 5409 */ 5410 static void 5411 bge_start(if_t ifp) 5412 { 5413 struct bge_softc *sc; 5414 5415 sc = if_getsoftc(ifp); 5416 BGE_LOCK(sc); 5417 bge_start_locked(ifp); 5418 BGE_UNLOCK(sc); 5419 } 5420 5421 static void 5422 bge_init_locked(struct bge_softc *sc) 5423 { 5424 if_t ifp; 5425 uint16_t *m; 5426 uint32_t mode; 5427 5428 BGE_LOCK_ASSERT(sc); 5429 5430 ifp = sc->bge_ifp; 5431 5432 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5433 return; 5434 5435 /* Cancel pending I/O and flush buffers. */ 5436 bge_stop(sc); 5437 5438 bge_stop_fw(sc); 5439 bge_sig_pre_reset(sc, BGE_RESET_START); 5440 bge_reset(sc); 5441 bge_sig_legacy(sc, BGE_RESET_START); 5442 bge_sig_post_reset(sc, BGE_RESET_START); 5443 5444 bge_chipinit(sc); 5445 5446 /* 5447 * Init the various state machines, ring 5448 * control blocks and firmware. 5449 */ 5450 if (bge_blockinit(sc)) { 5451 device_printf(sc->bge_dev, "initialization failure\n"); 5452 return; 5453 } 5454 5455 ifp = sc->bge_ifp; 5456 5457 /* Specify MTU. */ 5458 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5459 ETHER_HDR_LEN + ETHER_CRC_LEN + 5460 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5461 5462 /* Load our MAC address. */ 5463 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5464 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5465 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5466 5467 /* Program promiscuous mode. */ 5468 bge_setpromisc(sc); 5469 5470 /* Program multicast filter. */ 5471 bge_setmulti(sc); 5472 5473 /* Program VLAN tag stripping. */ 5474 bge_setvlan(sc); 5475 5476 /* Override UDP checksum offloading. */ 5477 if (sc->bge_forced_udpcsum == 0) 5478 sc->bge_csum_features &= ~CSUM_UDP; 5479 else 5480 sc->bge_csum_features |= CSUM_UDP; 5481 if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5482 if_getcapenable(ifp) & IFCAP_TXCSUM) { 5483 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5484 if_sethwassistbits(ifp, sc->bge_csum_features, 0); 5485 } 5486 5487 /* Init RX ring. */ 5488 if (bge_init_rx_ring_std(sc) != 0) { 5489 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5490 bge_stop(sc); 5491 return; 5492 } 5493 5494 /* 5495 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5496 * memory to insure that the chip has in fact read the first 5497 * entry of the ring. 5498 */ 5499 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5500 uint32_t v, i; 5501 for (i = 0; i < 10; i++) { 5502 DELAY(20); 5503 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5504 if (v == (MCLBYTES - ETHER_ALIGN)) 5505 break; 5506 } 5507 if (i == 10) 5508 device_printf (sc->bge_dev, 5509 "5705 A0 chip failed to load RX ring\n"); 5510 } 5511 5512 /* Init jumbo RX ring. */ 5513 if (BGE_IS_JUMBO_CAPABLE(sc) && 5514 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5515 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 5516 if (bge_init_rx_ring_jumbo(sc) != 0) { 5517 device_printf(sc->bge_dev, 5518 "no memory for jumbo Rx buffers.\n"); 5519 bge_stop(sc); 5520 return; 5521 } 5522 } 5523 5524 /* Init our RX return ring index. */ 5525 sc->bge_rx_saved_considx = 0; 5526 5527 /* Init our RX/TX stat counters. */ 5528 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5529 5530 /* Init TX ring. */ 5531 bge_init_tx_ring(sc); 5532 5533 /* Enable TX MAC state machine lockup fix. */ 5534 mode = CSR_READ_4(sc, BGE_TX_MODE); 5535 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5536 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5537 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5538 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5539 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5540 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5541 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5542 } 5543 /* Turn on transmitter. */ 5544 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5545 DELAY(100); 5546 5547 /* Turn on receiver. */ 5548 mode = CSR_READ_4(sc, BGE_RX_MODE); 5549 if (BGE_IS_5755_PLUS(sc)) 5550 mode |= BGE_RXMODE_IPV6_ENABLE; 5551 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5552 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5553 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5554 DELAY(10); 5555 5556 /* 5557 * Set the number of good frames to receive after RX MBUF 5558 * Low Watermark has been reached. After the RX MAC receives 5559 * this number of frames, it will drop subsequent incoming 5560 * frames until the MBUF High Watermark is reached. 5561 */ 5562 if (BGE_IS_57765_PLUS(sc)) 5563 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5564 else 5565 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5566 5567 /* Clear MAC statistics. */ 5568 if (BGE_IS_5705_PLUS(sc)) 5569 bge_stats_clear_regs(sc); 5570 5571 /* Tell firmware we're alive. */ 5572 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5573 5574 #ifdef DEVICE_POLLING 5575 /* Disable interrupts if we are polling. */ 5576 if (if_getcapenable(ifp) & IFCAP_POLLING) { 5577 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5578 BGE_PCIMISCCTL_MASK_PCI_INTR); 5579 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5580 } else 5581 #endif 5582 5583 /* Enable host interrupts. */ 5584 { 5585 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5586 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5587 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5588 } 5589 5590 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5591 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 5592 5593 bge_ifmedia_upd_locked(ifp); 5594 5595 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5596 } 5597 5598 static void 5599 bge_init(void *xsc) 5600 { 5601 struct bge_softc *sc = xsc; 5602 5603 BGE_LOCK(sc); 5604 bge_init_locked(sc); 5605 BGE_UNLOCK(sc); 5606 } 5607 5608 /* 5609 * Set media options. 5610 */ 5611 static int 5612 bge_ifmedia_upd(if_t ifp) 5613 { 5614 struct bge_softc *sc = if_getsoftc(ifp); 5615 int res; 5616 5617 BGE_LOCK(sc); 5618 res = bge_ifmedia_upd_locked(ifp); 5619 BGE_UNLOCK(sc); 5620 5621 return (res); 5622 } 5623 5624 static int 5625 bge_ifmedia_upd_locked(if_t ifp) 5626 { 5627 struct bge_softc *sc = if_getsoftc(ifp); 5628 struct mii_data *mii; 5629 struct mii_softc *miisc; 5630 struct ifmedia *ifm; 5631 5632 BGE_LOCK_ASSERT(sc); 5633 5634 ifm = &sc->bge_ifmedia; 5635 5636 /* If this is a 1000baseX NIC, enable the TBI port. */ 5637 if (sc->bge_flags & BGE_FLAG_TBI) { 5638 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5639 return (EINVAL); 5640 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5641 case IFM_AUTO: 5642 /* 5643 * The BCM5704 ASIC appears to have a special 5644 * mechanism for programming the autoneg 5645 * advertisement registers in TBI mode. 5646 */ 5647 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5648 uint32_t sgdig; 5649 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5650 if (sgdig & BGE_SGDIGSTS_DONE) { 5651 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5652 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5653 sgdig |= BGE_SGDIGCFG_AUTO | 5654 BGE_SGDIGCFG_PAUSE_CAP | 5655 BGE_SGDIGCFG_ASYM_PAUSE; 5656 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5657 sgdig | BGE_SGDIGCFG_SEND); 5658 DELAY(5); 5659 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5660 } 5661 } 5662 break; 5663 case IFM_1000_SX: 5664 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5665 BGE_CLRBIT(sc, BGE_MAC_MODE, 5666 BGE_MACMODE_HALF_DUPLEX); 5667 } else { 5668 BGE_SETBIT(sc, BGE_MAC_MODE, 5669 BGE_MACMODE_HALF_DUPLEX); 5670 } 5671 DELAY(40); 5672 break; 5673 default: 5674 return (EINVAL); 5675 } 5676 return (0); 5677 } 5678 5679 sc->bge_link_evt++; 5680 mii = device_get_softc(sc->bge_miibus); 5681 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5682 PHY_RESET(miisc); 5683 mii_mediachg(mii); 5684 5685 /* 5686 * Force an interrupt so that we will call bge_link_upd 5687 * if needed and clear any pending link state attention. 5688 * Without this we are not getting any further interrupts 5689 * for link state changes and thus will not UP the link and 5690 * not be able to send in bge_start_locked. The only 5691 * way to get things working was to receive a packet and 5692 * get an RX intr. 5693 * bge_tick should help for fiber cards and we might not 5694 * need to do this here if BGE_FLAG_TBI is set but as 5695 * we poll for fiber anyway it should not harm. 5696 */ 5697 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5698 sc->bge_flags & BGE_FLAG_5788) 5699 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5700 else 5701 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5702 5703 return (0); 5704 } 5705 5706 /* 5707 * Report current media status. 5708 */ 5709 static void 5710 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 5711 { 5712 struct bge_softc *sc = if_getsoftc(ifp); 5713 struct mii_data *mii; 5714 5715 BGE_LOCK(sc); 5716 5717 if ((if_getflags(ifp) & IFF_UP) == 0) { 5718 BGE_UNLOCK(sc); 5719 return; 5720 } 5721 if (sc->bge_flags & BGE_FLAG_TBI) { 5722 ifmr->ifm_status = IFM_AVALID; 5723 ifmr->ifm_active = IFM_ETHER; 5724 if (CSR_READ_4(sc, BGE_MAC_STS) & 5725 BGE_MACSTAT_TBI_PCS_SYNCHED) 5726 ifmr->ifm_status |= IFM_ACTIVE; 5727 else { 5728 ifmr->ifm_active |= IFM_NONE; 5729 BGE_UNLOCK(sc); 5730 return; 5731 } 5732 ifmr->ifm_active |= IFM_1000_SX; 5733 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5734 ifmr->ifm_active |= IFM_HDX; 5735 else 5736 ifmr->ifm_active |= IFM_FDX; 5737 BGE_UNLOCK(sc); 5738 return; 5739 } 5740 5741 mii = device_get_softc(sc->bge_miibus); 5742 mii_pollstat(mii); 5743 ifmr->ifm_active = mii->mii_media_active; 5744 ifmr->ifm_status = mii->mii_media_status; 5745 5746 BGE_UNLOCK(sc); 5747 } 5748 5749 static int 5750 bge_ioctl(if_t ifp, u_long command, caddr_t data) 5751 { 5752 struct bge_softc *sc = if_getsoftc(ifp); 5753 struct ifreq *ifr = (struct ifreq *) data; 5754 struct mii_data *mii; 5755 int flags, mask, error = 0; 5756 5757 switch (command) { 5758 case SIOCSIFMTU: 5759 if (BGE_IS_JUMBO_CAPABLE(sc) || 5760 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5761 if (ifr->ifr_mtu < ETHERMIN || 5762 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5763 error = EINVAL; 5764 break; 5765 } 5766 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5767 error = EINVAL; 5768 break; 5769 } 5770 BGE_LOCK(sc); 5771 if (if_getmtu(ifp) != ifr->ifr_mtu) { 5772 if_setmtu(ifp, ifr->ifr_mtu); 5773 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5774 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5775 bge_init_locked(sc); 5776 } 5777 } 5778 BGE_UNLOCK(sc); 5779 break; 5780 case SIOCSIFFLAGS: 5781 BGE_LOCK(sc); 5782 if (if_getflags(ifp) & IFF_UP) { 5783 /* 5784 * If only the state of the PROMISC flag changed, 5785 * then just use the 'set promisc mode' command 5786 * instead of reinitializing the entire NIC. Doing 5787 * a full re-init means reloading the firmware and 5788 * waiting for it to start up, which may take a 5789 * second or two. Similarly for ALLMULTI. 5790 */ 5791 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5792 flags = if_getflags(ifp) ^ sc->bge_if_flags; 5793 if (flags & IFF_PROMISC) 5794 bge_setpromisc(sc); 5795 if (flags & IFF_ALLMULTI) 5796 bge_setmulti(sc); 5797 } else 5798 bge_init_locked(sc); 5799 } else { 5800 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5801 bge_stop(sc); 5802 } 5803 } 5804 sc->bge_if_flags = if_getflags(ifp); 5805 BGE_UNLOCK(sc); 5806 error = 0; 5807 break; 5808 case SIOCADDMULTI: 5809 case SIOCDELMULTI: 5810 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5811 BGE_LOCK(sc); 5812 bge_setmulti(sc); 5813 BGE_UNLOCK(sc); 5814 error = 0; 5815 } 5816 break; 5817 case SIOCSIFMEDIA: 5818 case SIOCGIFMEDIA: 5819 if (sc->bge_flags & BGE_FLAG_TBI) { 5820 error = ifmedia_ioctl(ifp, ifr, 5821 &sc->bge_ifmedia, command); 5822 } else { 5823 mii = device_get_softc(sc->bge_miibus); 5824 error = ifmedia_ioctl(ifp, ifr, 5825 &mii->mii_media, command); 5826 } 5827 break; 5828 case SIOCSIFCAP: 5829 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 5830 #ifdef DEVICE_POLLING 5831 if (mask & IFCAP_POLLING) { 5832 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5833 error = ether_poll_register_drv(bge_poll, ifp); 5834 if (error) 5835 return (error); 5836 BGE_LOCK(sc); 5837 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5838 BGE_PCIMISCCTL_MASK_PCI_INTR); 5839 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5840 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 5841 BGE_UNLOCK(sc); 5842 } else { 5843 error = ether_poll_deregister(ifp); 5844 /* Enable interrupt even in error case */ 5845 BGE_LOCK(sc); 5846 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5847 BGE_PCIMISCCTL_MASK_PCI_INTR); 5848 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5849 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 5850 BGE_UNLOCK(sc); 5851 } 5852 } 5853 #endif 5854 if ((mask & IFCAP_TXCSUM) != 0 && 5855 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5856 if_togglecapenable(ifp, IFCAP_TXCSUM); 5857 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5858 if_sethwassistbits(ifp, 5859 sc->bge_csum_features, 0); 5860 else 5861 if_sethwassistbits(ifp, 0, 5862 sc->bge_csum_features); 5863 } 5864 5865 if ((mask & IFCAP_RXCSUM) != 0 && 5866 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5867 if_togglecapenable(ifp, IFCAP_RXCSUM); 5868 5869 if ((mask & IFCAP_TSO4) != 0 && 5870 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5871 if_togglecapenable(ifp, IFCAP_TSO4); 5872 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5873 if_sethwassistbits(ifp, CSUM_TSO, 0); 5874 else 5875 if_sethwassistbits(ifp, 0, CSUM_TSO); 5876 } 5877 5878 if (mask & IFCAP_VLAN_MTU) { 5879 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5880 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5881 bge_init(sc); 5882 } 5883 5884 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5885 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5886 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 5887 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5888 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5889 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5890 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5891 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5892 BGE_LOCK(sc); 5893 bge_setvlan(sc); 5894 BGE_UNLOCK(sc); 5895 } 5896 #ifdef VLAN_CAPABILITIES 5897 if_vlancap(ifp); 5898 #endif 5899 break; 5900 default: 5901 error = ether_ioctl(ifp, command, data); 5902 break; 5903 } 5904 5905 return (error); 5906 } 5907 5908 static void 5909 bge_watchdog(struct bge_softc *sc) 5910 { 5911 if_t ifp; 5912 uint32_t status; 5913 5914 BGE_LOCK_ASSERT(sc); 5915 5916 if (sc->bge_timer == 0 || --sc->bge_timer) 5917 return; 5918 5919 /* If pause frames are active then don't reset the hardware. */ 5920 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5921 status = CSR_READ_4(sc, BGE_RX_STS); 5922 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5923 /* 5924 * If link partner has us in XOFF state then wait for 5925 * the condition to clear. 5926 */ 5927 CSR_WRITE_4(sc, BGE_RX_STS, status); 5928 sc->bge_timer = BGE_TX_TIMEOUT; 5929 return; 5930 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5931 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5932 /* 5933 * If link partner has us in XOFF state then wait for 5934 * the condition to clear. 5935 */ 5936 CSR_WRITE_4(sc, BGE_RX_STS, status); 5937 sc->bge_timer = BGE_TX_TIMEOUT; 5938 return; 5939 } 5940 /* 5941 * Any other condition is unexpected and the controller 5942 * should be reset. 5943 */ 5944 } 5945 5946 ifp = sc->bge_ifp; 5947 5948 if_printf(ifp, "watchdog timeout -- resetting\n"); 5949 5950 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5951 bge_init_locked(sc); 5952 5953 if_incoerrors(ifp, 1); 5954 } 5955 5956 static void 5957 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5958 { 5959 int i; 5960 5961 BGE_CLRBIT(sc, reg, bit); 5962 5963 for (i = 0; i < BGE_TIMEOUT; i++) { 5964 if ((CSR_READ_4(sc, reg) & bit) == 0) 5965 return; 5966 DELAY(100); 5967 } 5968 } 5969 5970 /* 5971 * Stop the adapter and free any mbufs allocated to the 5972 * RX and TX lists. 5973 */ 5974 static void 5975 bge_stop(struct bge_softc *sc) 5976 { 5977 if_t ifp; 5978 5979 BGE_LOCK_ASSERT(sc); 5980 5981 ifp = sc->bge_ifp; 5982 5983 callout_stop(&sc->bge_stat_ch); 5984 5985 /* Disable host interrupts. */ 5986 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5987 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5988 5989 /* 5990 * Tell firmware we're shutting down. 5991 */ 5992 bge_stop_fw(sc); 5993 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5994 5995 /* 5996 * Disable all of the receiver blocks. 5997 */ 5998 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6001 if (BGE_IS_5700_FAMILY(sc)) 6002 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6003 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6004 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6005 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6006 6007 /* 6008 * Disable all of the transmit blocks. 6009 */ 6010 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6011 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6012 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6013 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6014 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6015 if (BGE_IS_5700_FAMILY(sc)) 6016 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6017 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6018 6019 /* 6020 * Shut down all of the memory managers and related 6021 * state machines. 6022 */ 6023 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6024 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6025 if (BGE_IS_5700_FAMILY(sc)) 6026 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6027 6028 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6029 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6030 if (!(BGE_IS_5705_PLUS(sc))) { 6031 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6032 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6033 } 6034 /* Update MAC statistics. */ 6035 if (BGE_IS_5705_PLUS(sc)) 6036 bge_stats_update_regs(sc); 6037 6038 bge_reset(sc); 6039 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6040 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6041 6042 /* 6043 * Keep the ASF firmware running if up. 6044 */ 6045 if (sc->bge_asf_mode & ASF_STACKUP) 6046 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6047 else 6048 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6049 6050 /* Free the RX lists. */ 6051 bge_free_rx_ring_std(sc); 6052 6053 /* Free jumbo RX list. */ 6054 if (BGE_IS_JUMBO_CAPABLE(sc)) 6055 bge_free_rx_ring_jumbo(sc); 6056 6057 /* Free TX buffers. */ 6058 bge_free_tx_ring(sc); 6059 6060 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6061 6062 /* Clear MAC's link state (PHY may still have link UP). */ 6063 if (bootverbose && sc->bge_link) 6064 if_printf(sc->bge_ifp, "link DOWN\n"); 6065 sc->bge_link = 0; 6066 6067 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 6068 } 6069 6070 /* 6071 * Stop all chip I/O so that the kernel's probe routines don't 6072 * get confused by errant DMAs when rebooting. 6073 */ 6074 static int 6075 bge_shutdown(device_t dev) 6076 { 6077 struct bge_softc *sc; 6078 6079 sc = device_get_softc(dev); 6080 BGE_LOCK(sc); 6081 bge_stop(sc); 6082 BGE_UNLOCK(sc); 6083 6084 return (0); 6085 } 6086 6087 static int 6088 bge_suspend(device_t dev) 6089 { 6090 struct bge_softc *sc; 6091 6092 sc = device_get_softc(dev); 6093 BGE_LOCK(sc); 6094 bge_stop(sc); 6095 BGE_UNLOCK(sc); 6096 6097 return (0); 6098 } 6099 6100 static int 6101 bge_resume(device_t dev) 6102 { 6103 struct bge_softc *sc; 6104 if_t ifp; 6105 6106 sc = device_get_softc(dev); 6107 BGE_LOCK(sc); 6108 ifp = sc->bge_ifp; 6109 if (if_getflags(ifp) & IFF_UP) { 6110 bge_init_locked(sc); 6111 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6112 bge_start_locked(ifp); 6113 } 6114 BGE_UNLOCK(sc); 6115 6116 return (0); 6117 } 6118 6119 static void 6120 bge_link_upd(struct bge_softc *sc) 6121 { 6122 struct mii_data *mii; 6123 uint32_t link, status; 6124 6125 BGE_LOCK_ASSERT(sc); 6126 6127 /* Clear 'pending link event' flag. */ 6128 sc->bge_link_evt = 0; 6129 6130 /* 6131 * Process link state changes. 6132 * Grrr. The link status word in the status block does 6133 * not work correctly on the BCM5700 rev AX and BX chips, 6134 * according to all available information. Hence, we have 6135 * to enable MII interrupts in order to properly obtain 6136 * async link changes. Unfortunately, this also means that 6137 * we have to read the MAC status register to detect link 6138 * changes, thereby adding an additional register access to 6139 * the interrupt handler. 6140 * 6141 * XXX: perhaps link state detection procedure used for 6142 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6143 */ 6144 6145 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6146 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6147 status = CSR_READ_4(sc, BGE_MAC_STS); 6148 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6149 mii = device_get_softc(sc->bge_miibus); 6150 mii_pollstat(mii); 6151 if (!sc->bge_link && 6152 mii->mii_media_status & IFM_ACTIVE && 6153 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6154 sc->bge_link++; 6155 if (bootverbose) 6156 if_printf(sc->bge_ifp, "link UP\n"); 6157 } else if (sc->bge_link && 6158 (!(mii->mii_media_status & IFM_ACTIVE) || 6159 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6160 sc->bge_link = 0; 6161 if (bootverbose) 6162 if_printf(sc->bge_ifp, "link DOWN\n"); 6163 } 6164 6165 /* Clear the interrupt. */ 6166 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6167 BGE_EVTENB_MI_INTERRUPT); 6168 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6169 BRGPHY_MII_ISR); 6170 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6171 BRGPHY_MII_IMR, BRGPHY_INTRS); 6172 } 6173 return; 6174 } 6175 6176 if (sc->bge_flags & BGE_FLAG_TBI) { 6177 status = CSR_READ_4(sc, BGE_MAC_STS); 6178 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6179 if (!sc->bge_link) { 6180 sc->bge_link++; 6181 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6182 BGE_CLRBIT(sc, BGE_MAC_MODE, 6183 BGE_MACMODE_TBI_SEND_CFGS); 6184 DELAY(40); 6185 } 6186 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6187 if (bootverbose) 6188 if_printf(sc->bge_ifp, "link UP\n"); 6189 if_link_state_change(sc->bge_ifp, 6190 LINK_STATE_UP); 6191 } 6192 } else if (sc->bge_link) { 6193 sc->bge_link = 0; 6194 if (bootverbose) 6195 if_printf(sc->bge_ifp, "link DOWN\n"); 6196 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6197 } 6198 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6199 /* 6200 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6201 * in status word always set. Workaround this bug by reading 6202 * PHY link status directly. 6203 */ 6204 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6205 6206 if (link != sc->bge_link || 6207 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6208 mii = device_get_softc(sc->bge_miibus); 6209 mii_pollstat(mii); 6210 if (!sc->bge_link && 6211 mii->mii_media_status & IFM_ACTIVE && 6212 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6213 sc->bge_link++; 6214 if (bootverbose) 6215 if_printf(sc->bge_ifp, "link UP\n"); 6216 } else if (sc->bge_link && 6217 (!(mii->mii_media_status & IFM_ACTIVE) || 6218 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6219 sc->bge_link = 0; 6220 if (bootverbose) 6221 if_printf(sc->bge_ifp, "link DOWN\n"); 6222 } 6223 } 6224 } else { 6225 /* 6226 * For controllers that call mii_tick, we have to poll 6227 * link status. 6228 */ 6229 mii = device_get_softc(sc->bge_miibus); 6230 mii_pollstat(mii); 6231 bge_miibus_statchg(sc->bge_dev); 6232 } 6233 6234 /* Disable MAC attention when link is up. */ 6235 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6236 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6237 BGE_MACSTAT_LINK_CHANGED); 6238 } 6239 6240 static void 6241 bge_add_sysctls(struct bge_softc *sc) 6242 { 6243 struct sysctl_ctx_list *ctx; 6244 struct sysctl_oid_list *children; 6245 int unit; 6246 6247 ctx = device_get_sysctl_ctx(sc->bge_dev); 6248 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6249 6250 #ifdef BGE_REGISTER_DEBUG 6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6252 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6253 "Debug Information"); 6254 6255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6256 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6257 "MAC Register Read"); 6258 6259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6260 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6261 "APE Register Read"); 6262 6263 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6264 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6265 "Memory Read"); 6266 6267 #endif 6268 6269 unit = device_get_unit(sc->bge_dev); 6270 /* 6271 * A common design characteristic for many Broadcom client controllers 6272 * is that they only support a single outstanding DMA read operation 6273 * on the PCIe bus. This means that it will take twice as long to fetch 6274 * a TX frame that is split into header and payload buffers as it does 6275 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6276 * these controllers, coalescing buffers to reduce the number of memory 6277 * reads is effective way to get maximum performance(about 940Mbps). 6278 * Without collapsing TX buffers the maximum TCP bulk transfer 6279 * performance is about 850Mbps. However forcing coalescing mbufs 6280 * consumes a lot of CPU cycles, so leave it off by default. 6281 */ 6282 sc->bge_forced_collapse = 0; 6283 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6284 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6285 "Number of fragmented TX buffers of a frame allowed before " 6286 "forced collapsing"); 6287 6288 sc->bge_msi = 1; 6289 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6290 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 6291 6292 /* 6293 * It seems all Broadcom controllers have a bug that can generate UDP 6294 * datagrams with checksum value 0 when TX UDP checksum offloading is 6295 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6296 * Even though the probability of generating such UDP datagrams is 6297 * low, I don't want to see FreeBSD boxes to inject such datagrams 6298 * into network so disable UDP checksum offloading by default. Users 6299 * still override this behavior by setting a sysctl variable, 6300 * dev.bge.0.forced_udpcsum. 6301 */ 6302 sc->bge_forced_udpcsum = 0; 6303 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6304 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 6305 "Enable UDP checksum offloading even if controller can " 6306 "generate UDP checksum value 0"); 6307 6308 if (BGE_IS_5705_PLUS(sc)) 6309 bge_add_sysctl_stats_regs(sc, ctx, children); 6310 else 6311 bge_add_sysctl_stats(sc, ctx, children); 6312 } 6313 6314 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6315 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6316 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6317 desc) 6318 6319 static void 6320 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6321 struct sysctl_oid_list *parent) 6322 { 6323 struct sysctl_oid *tree; 6324 struct sysctl_oid_list *children, *schildren; 6325 6326 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6327 NULL, "BGE Statistics"); 6328 schildren = children = SYSCTL_CHILDREN(tree); 6329 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6330 children, COSFramesDroppedDueToFilters, 6331 "FramesDroppedDueToFilters"); 6332 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6333 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6334 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6335 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6336 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6337 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6338 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6339 children, ifInDiscards, "InputDiscards"); 6340 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6341 children, ifInErrors, "InputErrors"); 6342 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6343 children, nicRecvThresholdHit, "RecvThresholdHit"); 6344 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6345 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6346 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6347 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6348 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6349 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6350 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6351 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6352 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6353 children, nicRingStatusUpdate, "RingStatusUpdate"); 6354 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6355 children, nicInterrupts, "Interrupts"); 6356 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6357 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6358 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6359 children, nicSendThresholdHit, "SendThresholdHit"); 6360 6361 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6362 NULL, "BGE RX Statistics"); 6363 children = SYSCTL_CHILDREN(tree); 6364 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6365 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6366 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6367 children, rxstats.etherStatsFragments, "Fragments"); 6368 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6369 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6370 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6371 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6372 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6373 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6374 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6375 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6376 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6377 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6378 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6379 children, rxstats.xoffPauseFramesReceived, 6380 "xoffPauseFramesReceived"); 6381 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6382 children, rxstats.macControlFramesReceived, 6383 "ControlFramesReceived"); 6384 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6385 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6386 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6387 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6388 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6389 children, rxstats.etherStatsJabbers, "Jabbers"); 6390 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6391 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6392 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6393 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6394 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6395 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6396 6397 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6398 NULL, "BGE TX Statistics"); 6399 children = SYSCTL_CHILDREN(tree); 6400 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6401 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6402 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6403 children, txstats.etherStatsCollisions, "Collisions"); 6404 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6405 children, txstats.outXonSent, "XonSent"); 6406 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6407 children, txstats.outXoffSent, "XoffSent"); 6408 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6409 children, txstats.flowControlDone, "flowControlDone"); 6410 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6411 children, txstats.dot3StatsInternalMacTransmitErrors, 6412 "InternalMacTransmitErrors"); 6413 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6414 children, txstats.dot3StatsSingleCollisionFrames, 6415 "SingleCollisionFrames"); 6416 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6417 children, txstats.dot3StatsMultipleCollisionFrames, 6418 "MultipleCollisionFrames"); 6419 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6420 children, txstats.dot3StatsDeferredTransmissions, 6421 "DeferredTransmissions"); 6422 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6423 children, txstats.dot3StatsExcessiveCollisions, 6424 "ExcessiveCollisions"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6426 children, txstats.dot3StatsLateCollisions, 6427 "LateCollisions"); 6428 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6429 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6430 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6431 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6432 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6433 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6434 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6435 children, txstats.dot3StatsCarrierSenseErrors, 6436 "CarrierSenseErrors"); 6437 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6438 children, txstats.ifOutDiscards, "Discards"); 6439 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6440 children, txstats.ifOutErrors, "Errors"); 6441 } 6442 6443 #undef BGE_SYSCTL_STAT 6444 6445 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6446 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6447 6448 static void 6449 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6450 struct sysctl_oid_list *parent) 6451 { 6452 struct sysctl_oid *tree; 6453 struct sysctl_oid_list *child, *schild; 6454 struct bge_mac_stats *stats; 6455 6456 stats = &sc->bge_mac_stats; 6457 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6458 NULL, "BGE Statistics"); 6459 schild = child = SYSCTL_CHILDREN(tree); 6460 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6461 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6462 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6463 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6465 &stats->DmaWriteHighPriQueueFull, 6466 "NIC DMA Write High Priority Queue Full"); 6467 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6468 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6469 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6470 &stats->InputDiscards, "Discarded Input Frames"); 6471 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6472 &stats->InputErrors, "Input Errors"); 6473 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6474 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6475 6476 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6477 NULL, "BGE RX Statistics"); 6478 child = SYSCTL_CHILDREN(tree); 6479 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6480 &stats->ifHCInOctets, "Inbound Octets"); 6481 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6482 &stats->etherStatsFragments, "Fragments"); 6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6484 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6486 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6488 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6490 &stats->dot3StatsFCSErrors, "FCS Errors"); 6491 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6492 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6493 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6494 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6495 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6496 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6497 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6498 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6500 &stats->xoffStateEntered, "XOFF State Entered"); 6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6502 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6504 &stats->etherStatsJabbers, "Jabbers"); 6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6506 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6507 6508 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6509 NULL, "BGE TX Statistics"); 6510 child = SYSCTL_CHILDREN(tree); 6511 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6512 &stats->ifHCOutOctets, "Outbound Octets"); 6513 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6514 &stats->etherStatsCollisions, "TX Collisions"); 6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6516 &stats->outXonSent, "XON Sent"); 6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6518 &stats->outXoffSent, "XOFF Sent"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6520 &stats->dot3StatsInternalMacTransmitErrors, 6521 "Internal MAC TX Errors"); 6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6523 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6525 &stats->dot3StatsMultipleCollisionFrames, 6526 "Multiple Collision Frames"); 6527 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6528 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6529 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6530 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6531 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6532 &stats->dot3StatsLateCollisions, "Late Collisions"); 6533 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6534 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6535 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6536 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6537 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6538 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6539 } 6540 6541 #undef BGE_SYSCTL_STAT_ADD64 6542 6543 static int 6544 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6545 { 6546 struct bge_softc *sc; 6547 uint32_t result; 6548 int offset; 6549 6550 sc = (struct bge_softc *)arg1; 6551 offset = arg2; 6552 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6553 offsetof(bge_hostaddr, bge_addr_lo)); 6554 return (sysctl_handle_int(oidp, &result, 0, req)); 6555 } 6556 6557 #ifdef BGE_REGISTER_DEBUG 6558 static int 6559 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6560 { 6561 struct bge_softc *sc; 6562 uint16_t *sbdata; 6563 int error, result, sbsz; 6564 int i, j; 6565 6566 result = -1; 6567 error = sysctl_handle_int(oidp, &result, 0, req); 6568 if (error || (req->newptr == NULL)) 6569 return (error); 6570 6571 if (result == 1) { 6572 sc = (struct bge_softc *)arg1; 6573 6574 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6575 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6576 sbsz = BGE_STATUS_BLK_SZ; 6577 else 6578 sbsz = 32; 6579 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6580 printf("Status Block:\n"); 6581 BGE_LOCK(sc); 6582 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6583 sc->bge_cdata.bge_status_map, 6584 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6585 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6586 printf("%06x:", i); 6587 for (j = 0; j < 8; j++) 6588 printf(" %04x", sbdata[i++]); 6589 printf("\n"); 6590 } 6591 6592 printf("Registers:\n"); 6593 for (i = 0x800; i < 0xA00; ) { 6594 printf("%06x:", i); 6595 for (j = 0; j < 8; j++) { 6596 printf(" %08x", CSR_READ_4(sc, i)); 6597 i += 4; 6598 } 6599 printf("\n"); 6600 } 6601 BGE_UNLOCK(sc); 6602 6603 printf("Hardware Flags:\n"); 6604 if (BGE_IS_5717_PLUS(sc)) 6605 printf(" - 5717 Plus\n"); 6606 if (BGE_IS_5755_PLUS(sc)) 6607 printf(" - 5755 Plus\n"); 6608 if (BGE_IS_575X_PLUS(sc)) 6609 printf(" - 575X Plus\n"); 6610 if (BGE_IS_5705_PLUS(sc)) 6611 printf(" - 5705 Plus\n"); 6612 if (BGE_IS_5714_FAMILY(sc)) 6613 printf(" - 5714 Family\n"); 6614 if (BGE_IS_5700_FAMILY(sc)) 6615 printf(" - 5700 Family\n"); 6616 if (sc->bge_flags & BGE_FLAG_JUMBO) 6617 printf(" - Supports Jumbo Frames\n"); 6618 if (sc->bge_flags & BGE_FLAG_PCIX) 6619 printf(" - PCI-X Bus\n"); 6620 if (sc->bge_flags & BGE_FLAG_PCIE) 6621 printf(" - PCI Express Bus\n"); 6622 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6623 printf(" - No 3 LEDs\n"); 6624 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6625 printf(" - RX Alignment Bug\n"); 6626 } 6627 6628 return (error); 6629 } 6630 6631 static int 6632 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6633 { 6634 struct bge_softc *sc; 6635 int error; 6636 uint16_t result; 6637 uint32_t val; 6638 6639 result = -1; 6640 error = sysctl_handle_int(oidp, &result, 0, req); 6641 if (error || (req->newptr == NULL)) 6642 return (error); 6643 6644 if (result < 0x8000) { 6645 sc = (struct bge_softc *)arg1; 6646 val = CSR_READ_4(sc, result); 6647 printf("reg 0x%06X = 0x%08X\n", result, val); 6648 } 6649 6650 return (error); 6651 } 6652 6653 static int 6654 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6655 { 6656 struct bge_softc *sc; 6657 int error; 6658 uint16_t result; 6659 uint32_t val; 6660 6661 result = -1; 6662 error = sysctl_handle_int(oidp, &result, 0, req); 6663 if (error || (req->newptr == NULL)) 6664 return (error); 6665 6666 if (result < 0x8000) { 6667 sc = (struct bge_softc *)arg1; 6668 val = APE_READ_4(sc, result); 6669 printf("reg 0x%06X = 0x%08X\n", result, val); 6670 } 6671 6672 return (error); 6673 } 6674 6675 static int 6676 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6677 { 6678 struct bge_softc *sc; 6679 int error; 6680 uint16_t result; 6681 uint32_t val; 6682 6683 result = -1; 6684 error = sysctl_handle_int(oidp, &result, 0, req); 6685 if (error || (req->newptr == NULL)) 6686 return (error); 6687 6688 if (result < 0x8000) { 6689 sc = (struct bge_softc *)arg1; 6690 val = bge_readmem_ind(sc, result); 6691 printf("mem 0x%06X = 0x%08X\n", result, val); 6692 } 6693 6694 return (error); 6695 } 6696 #endif 6697 6698 static int 6699 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6700 { 6701 6702 if (sc->bge_flags & BGE_FLAG_EADDR) 6703 return (1); 6704 6705 #ifdef __sparc64__ 6706 OF_getetheraddr(sc->bge_dev, ether_addr); 6707 return (0); 6708 #endif 6709 return (1); 6710 } 6711 6712 static int 6713 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6714 { 6715 uint32_t mac_addr; 6716 6717 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6718 if ((mac_addr >> 16) == 0x484b) { 6719 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6720 ether_addr[1] = (uint8_t)mac_addr; 6721 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6722 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6723 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6724 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6725 ether_addr[5] = (uint8_t)mac_addr; 6726 return (0); 6727 } 6728 return (1); 6729 } 6730 6731 static int 6732 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6733 { 6734 int mac_offset = BGE_EE_MAC_OFFSET; 6735 6736 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6737 mac_offset = BGE_EE_MAC_OFFSET_5906; 6738 6739 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6740 ETHER_ADDR_LEN)); 6741 } 6742 6743 static int 6744 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6745 { 6746 6747 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6748 return (1); 6749 6750 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6751 ETHER_ADDR_LEN)); 6752 } 6753 6754 static int 6755 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6756 { 6757 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6758 /* NOTE: Order is critical */ 6759 bge_get_eaddr_fw, 6760 bge_get_eaddr_mem, 6761 bge_get_eaddr_nvram, 6762 bge_get_eaddr_eeprom, 6763 NULL 6764 }; 6765 const bge_eaddr_fcn_t *func; 6766 6767 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6768 if ((*func)(sc, eaddr) == 0) 6769 break; 6770 } 6771 return (*func == NULL ? ENXIO : 0); 6772 } 6773