1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/endian.h> 71 #include <sys/systm.h> 72 #include <sys/sockio.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/module.h> 77 #include <sys/socket.h> 78 #include <sys/queue.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <net/if_types.h> 89 #include <net/if_vlan_var.h> 90 91 #include <netinet/in_systm.h> 92 #include <netinet/in.h> 93 #include <netinet/ip.h> 94 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus.h> 97 #include <machine/resource.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include "miidevs.h" 104 #include <dev/mii/brgphyreg.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 109 #include <dev/bge/if_bgereg.h> 110 111 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 112 113 MODULE_DEPEND(bge, pci, 1, 1, 1); 114 MODULE_DEPEND(bge, ether, 1, 1, 1); 115 MODULE_DEPEND(bge, miibus, 1, 1, 1); 116 117 /* "controller miibus0" required. See GENERIC if you get errors here. */ 118 #include "miibus_if.h" 119 120 /* 121 * Various supported device vendors/types and their names. Note: the 122 * spec seems to indicate that the hardware still has Alteon's vendor 123 * ID burned into it, though it will always be overriden by the vendor 124 * ID in the EEPROM. Just to be safe, we cover all possibilities. 125 */ 126 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 127 128 static struct bge_type bge_devs[] = { 129 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 130 "Broadcom BCM5700 Gigabit Ethernet" }, 131 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 132 "Broadcom BCM5701 Gigabit Ethernet" }, 133 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 134 "Broadcom BCM5700 Gigabit Ethernet" }, 135 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 136 "Broadcom BCM5701 Gigabit Ethernet" }, 137 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 138 "Broadcom BCM5702 Gigabit Ethernet" }, 139 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 140 "Broadcom BCM5702X Gigabit Ethernet" }, 141 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 142 "Broadcom BCM5703 Gigabit Ethernet" }, 143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 144 "Broadcom BCM5703X Gigabit Ethernet" }, 145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 146 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 148 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 150 "Broadcom BCM5705 Gigabit Ethernet" }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K, 152 "Broadcom BCM5705K Gigabit Ethernet" }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 154 "Broadcom BCM5705M Gigabit Ethernet" }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 156 "Broadcom BCM5705M Gigabit Ethernet" }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C, 158 "Broadcom BCM5714C Gigabit Ethernet" }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721, 160 "Broadcom BCM5721 Gigabit Ethernet" }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750, 162 "Broadcom BCM5750 Gigabit Ethernet" }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M, 164 "Broadcom BCM5750M Gigabit Ethernet" }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751, 166 "Broadcom BCM5751 Gigabit Ethernet" }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M, 168 "Broadcom BCM5751M Gigabit Ethernet" }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 170 "Broadcom BCM5782 Gigabit Ethernet" }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788, 172 "Broadcom BCM5788 Gigabit Ethernet" }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789, 174 "Broadcom BCM5789 Gigabit Ethernet" }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 176 "Broadcom BCM5901 Fast Ethernet" }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 178 "Broadcom BCM5901A2 Fast Ethernet" }, 179 { SK_VENDORID, SK_DEVICEID_ALTIMA, 180 "SysKonnect Gigabit Ethernet" }, 181 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 182 "Altima AC1000 Gigabit Ethernet" }, 183 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002, 184 "Altima AC1002 Gigabit Ethernet" }, 185 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 186 "Altima AC9100 Gigabit Ethernet" }, 187 { 0, 0, NULL } 188 }; 189 190 static int bge_probe (device_t); 191 static int bge_attach (device_t); 192 static int bge_detach (device_t); 193 static void bge_release_resources 194 (struct bge_softc *); 195 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 196 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 197 bus_size_t, int); 198 static int bge_dma_alloc (device_t); 199 static void bge_dma_free (struct bge_softc *); 200 201 static void bge_txeof (struct bge_softc *); 202 static void bge_rxeof (struct bge_softc *); 203 204 static void bge_tick_locked (struct bge_softc *); 205 static void bge_tick (void *); 206 static void bge_stats_update (struct bge_softc *); 207 static void bge_stats_update_regs 208 (struct bge_softc *); 209 static int bge_encap (struct bge_softc *, struct mbuf *, 210 u_int32_t *); 211 212 static void bge_intr (void *); 213 static void bge_start_locked (struct ifnet *); 214 static void bge_start (struct ifnet *); 215 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 216 static void bge_init_locked (struct bge_softc *); 217 static void bge_init (void *); 218 static void bge_stop (struct bge_softc *); 219 static void bge_watchdog (struct ifnet *); 220 static void bge_shutdown (device_t); 221 static int bge_ifmedia_upd (struct ifnet *); 222 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 225 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 226 227 static void bge_setmulti (struct bge_softc *); 228 229 static void bge_handle_events (struct bge_softc *); 230 static int bge_alloc_jumbo_mem (struct bge_softc *); 231 static void bge_free_jumbo_mem (struct bge_softc *); 232 static void *bge_jalloc (struct bge_softc *); 233 static void bge_jfree (void *, void *); 234 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 235 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 236 static int bge_init_rx_ring_std (struct bge_softc *); 237 static void bge_free_rx_ring_std (struct bge_softc *); 238 static int bge_init_rx_ring_jumbo (struct bge_softc *); 239 static void bge_free_rx_ring_jumbo (struct bge_softc *); 240 static void bge_free_tx_ring (struct bge_softc *); 241 static int bge_init_tx_ring (struct bge_softc *); 242 243 static int bge_chipinit (struct bge_softc *); 244 static int bge_blockinit (struct bge_softc *); 245 246 #ifdef notdef 247 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 248 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 249 static void bge_vpd_read (struct bge_softc *); 250 #endif 251 252 static u_int32_t bge_readmem_ind 253 (struct bge_softc *, int); 254 static void bge_writemem_ind (struct bge_softc *, int, int); 255 #ifdef notdef 256 static u_int32_t bge_readreg_ind 257 (struct bge_softc *, int); 258 #endif 259 static void bge_writereg_ind (struct bge_softc *, int, int); 260 261 static int bge_miibus_readreg (device_t, int, int); 262 static int bge_miibus_writereg (device_t, int, int, int); 263 static void bge_miibus_statchg (device_t); 264 265 static void bge_reset (struct bge_softc *); 266 267 static device_method_t bge_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, bge_probe), 270 DEVMETHOD(device_attach, bge_attach), 271 DEVMETHOD(device_detach, bge_detach), 272 DEVMETHOD(device_shutdown, bge_shutdown), 273 274 /* bus interface */ 275 DEVMETHOD(bus_print_child, bus_generic_print_child), 276 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 280 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 281 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 282 283 { 0, 0 } 284 }; 285 286 static driver_t bge_driver = { 287 "bge", 288 bge_methods, 289 sizeof(struct bge_softc) 290 }; 291 292 static devclass_t bge_devclass; 293 294 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 295 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 296 297 static u_int32_t 298 bge_readmem_ind(sc, off) 299 struct bge_softc *sc; 300 int off; 301 { 302 device_t dev; 303 304 dev = sc->bge_dev; 305 306 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 307 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 308 } 309 310 static void 311 bge_writemem_ind(sc, off, val) 312 struct bge_softc *sc; 313 int off, val; 314 { 315 device_t dev; 316 317 dev = sc->bge_dev; 318 319 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 320 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 321 322 return; 323 } 324 325 #ifdef notdef 326 static u_int32_t 327 bge_readreg_ind(sc, off) 328 struct bge_softc *sc; 329 int off; 330 { 331 device_t dev; 332 333 dev = sc->bge_dev; 334 335 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 336 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 337 } 338 #endif 339 340 static void 341 bge_writereg_ind(sc, off, val) 342 struct bge_softc *sc; 343 int off, val; 344 { 345 device_t dev; 346 347 dev = sc->bge_dev; 348 349 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 350 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 351 352 return; 353 } 354 355 /* 356 * Map a single buffer address. 357 */ 358 359 static void 360 bge_dma_map_addr(arg, segs, nseg, error) 361 void *arg; 362 bus_dma_segment_t *segs; 363 int nseg; 364 int error; 365 { 366 struct bge_dmamap_arg *ctx; 367 368 if (error) 369 return; 370 371 ctx = arg; 372 373 if (nseg > ctx->bge_maxsegs) { 374 ctx->bge_maxsegs = 0; 375 return; 376 } 377 378 ctx->bge_busaddr = segs->ds_addr; 379 380 return; 381 } 382 383 /* 384 * Map an mbuf chain into an TX ring. 385 */ 386 387 static void 388 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 389 void *arg; 390 bus_dma_segment_t *segs; 391 int nseg; 392 bus_size_t mapsize; 393 int error; 394 { 395 struct bge_dmamap_arg *ctx; 396 struct bge_tx_bd *d = NULL; 397 int i = 0, idx; 398 399 if (error) 400 return; 401 402 ctx = arg; 403 404 /* Signal error to caller if there's too many segments */ 405 if (nseg > ctx->bge_maxsegs) { 406 ctx->bge_maxsegs = 0; 407 return; 408 } 409 410 idx = ctx->bge_idx; 411 while(1) { 412 d = &ctx->bge_ring[idx]; 413 d->bge_addr.bge_addr_lo = 414 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 415 d->bge_addr.bge_addr_hi = 416 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 417 d->bge_len = htole16(segs[i].ds_len); 418 d->bge_flags = htole16(ctx->bge_flags); 419 i++; 420 if (i == nseg) 421 break; 422 BGE_INC(idx, BGE_TX_RING_CNT); 423 } 424 425 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 426 ctx->bge_maxsegs = nseg; 427 ctx->bge_idx = idx; 428 429 return; 430 } 431 432 433 #ifdef notdef 434 static u_int8_t 435 bge_vpd_readbyte(sc, addr) 436 struct bge_softc *sc; 437 int addr; 438 { 439 int i; 440 device_t dev; 441 u_int32_t val; 442 443 dev = sc->bge_dev; 444 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 445 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 446 DELAY(10); 447 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 448 break; 449 } 450 451 if (i == BGE_TIMEOUT) { 452 printf("bge%d: VPD read timed out\n", sc->bge_unit); 453 return(0); 454 } 455 456 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 457 458 return((val >> ((addr % 4) * 8)) & 0xFF); 459 } 460 461 static void 462 bge_vpd_read_res(sc, res, addr) 463 struct bge_softc *sc; 464 struct vpd_res *res; 465 int addr; 466 { 467 int i; 468 u_int8_t *ptr; 469 470 ptr = (u_int8_t *)res; 471 for (i = 0; i < sizeof(struct vpd_res); i++) 472 ptr[i] = bge_vpd_readbyte(sc, i + addr); 473 474 return; 475 } 476 477 static void 478 bge_vpd_read(sc) 479 struct bge_softc *sc; 480 { 481 int pos = 0, i; 482 struct vpd_res res; 483 484 if (sc->bge_vpd_prodname != NULL) 485 free(sc->bge_vpd_prodname, M_DEVBUF); 486 if (sc->bge_vpd_readonly != NULL) 487 free(sc->bge_vpd_readonly, M_DEVBUF); 488 sc->bge_vpd_prodname = NULL; 489 sc->bge_vpd_readonly = NULL; 490 491 bge_vpd_read_res(sc, &res, pos); 492 493 if (res.vr_id != VPD_RES_ID) { 494 printf("bge%d: bad VPD resource id: expected %x got %x\n", 495 sc->bge_unit, VPD_RES_ID, res.vr_id); 496 return; 497 } 498 499 pos += sizeof(res); 500 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 501 for (i = 0; i < res.vr_len; i++) 502 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 503 sc->bge_vpd_prodname[i] = '\0'; 504 pos += i; 505 506 bge_vpd_read_res(sc, &res, pos); 507 508 if (res.vr_id != VPD_RES_READ) { 509 printf("bge%d: bad VPD resource id: expected %x got %x\n", 510 sc->bge_unit, VPD_RES_READ, res.vr_id); 511 return; 512 } 513 514 pos += sizeof(res); 515 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 516 for (i = 0; i < res.vr_len + 1; i++) 517 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 518 519 return; 520 } 521 #endif 522 523 /* 524 * Read a byte of data stored in the EEPROM at address 'addr.' The 525 * BCM570x supports both the traditional bitbang interface and an 526 * auto access interface for reading the EEPROM. We use the auto 527 * access method. 528 */ 529 static u_int8_t 530 bge_eeprom_getbyte(sc, addr, dest) 531 struct bge_softc *sc; 532 int addr; 533 u_int8_t *dest; 534 { 535 int i; 536 u_int32_t byte = 0; 537 538 /* 539 * Enable use of auto EEPROM access so we can avoid 540 * having to use the bitbang method. 541 */ 542 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 543 544 /* Reset the EEPROM, load the clock period. */ 545 CSR_WRITE_4(sc, BGE_EE_ADDR, 546 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 547 DELAY(20); 548 549 /* Issue the read EEPROM command. */ 550 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 551 552 /* Wait for completion */ 553 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 554 DELAY(10); 555 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 556 break; 557 } 558 559 if (i == BGE_TIMEOUT) { 560 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 561 return(0); 562 } 563 564 /* Get result. */ 565 byte = CSR_READ_4(sc, BGE_EE_DATA); 566 567 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 568 569 return(0); 570 } 571 572 /* 573 * Read a sequence of bytes from the EEPROM. 574 */ 575 static int 576 bge_read_eeprom(sc, dest, off, cnt) 577 struct bge_softc *sc; 578 caddr_t dest; 579 int off; 580 int cnt; 581 { 582 int err = 0, i; 583 u_int8_t byte = 0; 584 585 for (i = 0; i < cnt; i++) { 586 err = bge_eeprom_getbyte(sc, off + i, &byte); 587 if (err) 588 break; 589 *(dest + i) = byte; 590 } 591 592 return(err ? 1 : 0); 593 } 594 595 static int 596 bge_miibus_readreg(dev, phy, reg) 597 device_t dev; 598 int phy, reg; 599 { 600 struct bge_softc *sc; 601 u_int32_t val, autopoll; 602 int i; 603 604 sc = device_get_softc(dev); 605 606 /* 607 * Broadcom's own driver always assumes the internal 608 * PHY is at GMII address 1. On some chips, the PHY responds 609 * to accesses at all addresses, which could cause us to 610 * bogusly attach the PHY 32 times at probe type. Always 611 * restricting the lookup to address 1 is simpler than 612 * trying to figure out which chips revisions should be 613 * special-cased. 614 */ 615 if (phy != 1) 616 return(0); 617 618 /* Reading with autopolling on may trigger PCI errors */ 619 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 620 if (autopoll & BGE_MIMODE_AUTOPOLL) { 621 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 622 DELAY(40); 623 } 624 625 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 626 BGE_MIPHY(phy)|BGE_MIREG(reg)); 627 628 for (i = 0; i < BGE_TIMEOUT; i++) { 629 val = CSR_READ_4(sc, BGE_MI_COMM); 630 if (!(val & BGE_MICOMM_BUSY)) 631 break; 632 } 633 634 if (i == BGE_TIMEOUT) { 635 printf("bge%d: PHY read timed out\n", sc->bge_unit); 636 val = 0; 637 goto done; 638 } 639 640 val = CSR_READ_4(sc, BGE_MI_COMM); 641 642 done: 643 if (autopoll & BGE_MIMODE_AUTOPOLL) { 644 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 645 DELAY(40); 646 } 647 648 if (val & BGE_MICOMM_READFAIL) 649 return(0); 650 651 return(val & 0xFFFF); 652 } 653 654 static int 655 bge_miibus_writereg(dev, phy, reg, val) 656 device_t dev; 657 int phy, reg, val; 658 { 659 struct bge_softc *sc; 660 u_int32_t autopoll; 661 int i; 662 663 sc = device_get_softc(dev); 664 665 /* Reading with autopolling on may trigger PCI errors */ 666 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 667 if (autopoll & BGE_MIMODE_AUTOPOLL) { 668 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 669 DELAY(40); 670 } 671 672 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 673 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 674 675 for (i = 0; i < BGE_TIMEOUT; i++) { 676 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 677 break; 678 } 679 680 if (autopoll & BGE_MIMODE_AUTOPOLL) { 681 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 682 DELAY(40); 683 } 684 685 if (i == BGE_TIMEOUT) { 686 printf("bge%d: PHY read timed out\n", sc->bge_unit); 687 return(0); 688 } 689 690 return(0); 691 } 692 693 static void 694 bge_miibus_statchg(dev) 695 device_t dev; 696 { 697 struct bge_softc *sc; 698 struct mii_data *mii; 699 700 sc = device_get_softc(dev); 701 mii = device_get_softc(sc->bge_miibus); 702 703 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 704 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 705 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 706 } else { 707 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 708 } 709 710 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 711 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 712 } else { 713 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 714 } 715 716 return; 717 } 718 719 /* 720 * Handle events that have triggered interrupts. 721 */ 722 static void 723 bge_handle_events(sc) 724 struct bge_softc *sc; 725 { 726 727 return; 728 } 729 730 /* 731 * Memory management for jumbo frames. 732 */ 733 734 static int 735 bge_alloc_jumbo_mem(sc) 736 struct bge_softc *sc; 737 { 738 caddr_t ptr; 739 register int i, error; 740 struct bge_jpool_entry *entry; 741 742 /* Create tag for jumbo buffer block */ 743 744 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 745 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 746 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 747 &sc->bge_cdata.bge_jumbo_tag); 748 749 if (error) { 750 printf("bge%d: could not allocate jumbo dma tag\n", 751 sc->bge_unit); 752 return (ENOMEM); 753 } 754 755 /* Allocate DMA'able memory for jumbo buffer block */ 756 757 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 758 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 759 &sc->bge_cdata.bge_jumbo_map); 760 761 if (error) 762 return (ENOMEM); 763 764 SLIST_INIT(&sc->bge_jfree_listhead); 765 SLIST_INIT(&sc->bge_jinuse_listhead); 766 767 /* 768 * Now divide it up into 9K pieces and save the addresses 769 * in an array. 770 */ 771 ptr = sc->bge_ldata.bge_jumbo_buf; 772 for (i = 0; i < BGE_JSLOTS; i++) { 773 sc->bge_cdata.bge_jslots[i] = ptr; 774 ptr += BGE_JLEN; 775 entry = malloc(sizeof(struct bge_jpool_entry), 776 M_DEVBUF, M_NOWAIT); 777 if (entry == NULL) { 778 bge_free_jumbo_mem(sc); 779 sc->bge_ldata.bge_jumbo_buf = NULL; 780 printf("bge%d: no memory for jumbo " 781 "buffer queue!\n", sc->bge_unit); 782 return(ENOBUFS); 783 } 784 entry->slot = i; 785 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 786 entry, jpool_entries); 787 } 788 789 return(0); 790 } 791 792 static void 793 bge_free_jumbo_mem(sc) 794 struct bge_softc *sc; 795 { 796 int i; 797 struct bge_jpool_entry *entry; 798 799 for (i = 0; i < BGE_JSLOTS; i++) { 800 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 801 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 802 free(entry, M_DEVBUF); 803 } 804 805 /* Destroy jumbo buffer block */ 806 807 if (sc->bge_ldata.bge_rx_jumbo_ring) 808 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 809 sc->bge_ldata.bge_jumbo_buf, 810 sc->bge_cdata.bge_jumbo_map); 811 812 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 813 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 814 sc->bge_cdata.bge_jumbo_map); 815 816 if (sc->bge_cdata.bge_jumbo_tag) 817 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 818 819 return; 820 } 821 822 /* 823 * Allocate a jumbo buffer. 824 */ 825 static void * 826 bge_jalloc(sc) 827 struct bge_softc *sc; 828 { 829 struct bge_jpool_entry *entry; 830 831 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 832 833 if (entry == NULL) { 834 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 835 return(NULL); 836 } 837 838 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 839 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 840 return(sc->bge_cdata.bge_jslots[entry->slot]); 841 } 842 843 /* 844 * Release a jumbo buffer. 845 */ 846 static void 847 bge_jfree(buf, args) 848 void *buf; 849 void *args; 850 { 851 struct bge_jpool_entry *entry; 852 struct bge_softc *sc; 853 int i; 854 855 /* Extract the softc struct pointer. */ 856 sc = (struct bge_softc *)args; 857 858 if (sc == NULL) 859 panic("bge_jfree: can't find softc pointer!"); 860 861 /* calculate the slot this buffer belongs to */ 862 863 i = ((vm_offset_t)buf 864 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 865 866 if ((i < 0) || (i >= BGE_JSLOTS)) 867 panic("bge_jfree: asked to free buffer that we don't manage!"); 868 869 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 870 if (entry == NULL) 871 panic("bge_jfree: buffer not in use!"); 872 entry->slot = i; 873 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 874 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 875 876 return; 877 } 878 879 880 /* 881 * Intialize a standard receive ring descriptor. 882 */ 883 static int 884 bge_newbuf_std(sc, i, m) 885 struct bge_softc *sc; 886 int i; 887 struct mbuf *m; 888 { 889 struct mbuf *m_new = NULL; 890 struct bge_rx_bd *r; 891 struct bge_dmamap_arg ctx; 892 int error; 893 894 if (m == NULL) { 895 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 896 if (m_new == NULL) { 897 return(ENOBUFS); 898 } 899 900 MCLGET(m_new, M_DONTWAIT); 901 if (!(m_new->m_flags & M_EXT)) { 902 m_freem(m_new); 903 return(ENOBUFS); 904 } 905 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 906 } else { 907 m_new = m; 908 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 909 m_new->m_data = m_new->m_ext.ext_buf; 910 } 911 912 if (!sc->bge_rx_alignment_bug) 913 m_adj(m_new, ETHER_ALIGN); 914 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 915 r = &sc->bge_ldata.bge_rx_std_ring[i]; 916 ctx.bge_maxsegs = 1; 917 ctx.sc = sc; 918 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 919 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 920 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 921 if (error || ctx.bge_maxsegs == 0) { 922 if (m == NULL) 923 m_freem(m_new); 924 return(ENOMEM); 925 } 926 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 927 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 928 r->bge_flags = htole16(BGE_RXBDFLAG_END); 929 r->bge_len = htole16(m_new->m_len); 930 r->bge_idx = htole16(i); 931 932 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 933 sc->bge_cdata.bge_rx_std_dmamap[i], 934 BUS_DMASYNC_PREREAD); 935 936 return(0); 937 } 938 939 /* 940 * Initialize a jumbo receive ring descriptor. This allocates 941 * a jumbo buffer from the pool managed internally by the driver. 942 */ 943 static int 944 bge_newbuf_jumbo(sc, i, m) 945 struct bge_softc *sc; 946 int i; 947 struct mbuf *m; 948 { 949 struct mbuf *m_new = NULL; 950 struct bge_rx_bd *r; 951 struct bge_dmamap_arg ctx; 952 int error; 953 954 if (m == NULL) { 955 caddr_t *buf = NULL; 956 957 /* Allocate the mbuf. */ 958 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 959 if (m_new == NULL) { 960 return(ENOBUFS); 961 } 962 963 /* Allocate the jumbo buffer */ 964 buf = bge_jalloc(sc); 965 if (buf == NULL) { 966 m_freem(m_new); 967 printf("bge%d: jumbo allocation failed " 968 "-- packet dropped!\n", sc->bge_unit); 969 return(ENOBUFS); 970 } 971 972 /* Attach the buffer to the mbuf. */ 973 m_new->m_data = (void *) buf; 974 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 975 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 976 (struct bge_softc *)sc, 0, EXT_NET_DRV); 977 } else { 978 m_new = m; 979 m_new->m_data = m_new->m_ext.ext_buf; 980 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 981 } 982 983 if (!sc->bge_rx_alignment_bug) 984 m_adj(m_new, ETHER_ALIGN); 985 /* Set up the descriptor. */ 986 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 987 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 988 ctx.bge_maxsegs = 1; 989 ctx.sc = sc; 990 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 991 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 992 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 993 if (error || ctx.bge_maxsegs == 0) { 994 if (m == NULL) 995 m_freem(m_new); 996 return(ENOMEM); 997 } 998 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 999 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 1000 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 1001 r->bge_len = htole16(m_new->m_len); 1002 r->bge_idx = htole16(i); 1003 1004 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1005 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1006 BUS_DMASYNC_PREREAD); 1007 1008 return(0); 1009 } 1010 1011 /* 1012 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1013 * that's 1MB or memory, which is a lot. For now, we fill only the first 1014 * 256 ring entries and hope that our CPU is fast enough to keep up with 1015 * the NIC. 1016 */ 1017 static int 1018 bge_init_rx_ring_std(sc) 1019 struct bge_softc *sc; 1020 { 1021 int i; 1022 1023 for (i = 0; i < BGE_SSLOTS; i++) { 1024 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1025 return(ENOBUFS); 1026 }; 1027 1028 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1029 sc->bge_cdata.bge_rx_std_ring_map, 1030 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1031 1032 sc->bge_std = i - 1; 1033 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1034 1035 return(0); 1036 } 1037 1038 static void 1039 bge_free_rx_ring_std(sc) 1040 struct bge_softc *sc; 1041 { 1042 int i; 1043 1044 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1045 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1046 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1047 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1048 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1049 sc->bge_cdata.bge_rx_std_dmamap[i]); 1050 } 1051 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1052 sizeof(struct bge_rx_bd)); 1053 } 1054 1055 return; 1056 } 1057 1058 static int 1059 bge_init_rx_ring_jumbo(sc) 1060 struct bge_softc *sc; 1061 { 1062 int i; 1063 struct bge_rcb *rcb; 1064 1065 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1066 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1067 return(ENOBUFS); 1068 }; 1069 1070 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1071 sc->bge_cdata.bge_rx_jumbo_ring_map, 1072 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1073 1074 sc->bge_jumbo = i - 1; 1075 1076 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1077 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1078 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1079 1080 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1081 1082 return(0); 1083 } 1084 1085 static void 1086 bge_free_rx_ring_jumbo(sc) 1087 struct bge_softc *sc; 1088 { 1089 int i; 1090 1091 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1092 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1093 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1094 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1095 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1096 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1097 } 1098 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1099 sizeof(struct bge_rx_bd)); 1100 } 1101 1102 return; 1103 } 1104 1105 static void 1106 bge_free_tx_ring(sc) 1107 struct bge_softc *sc; 1108 { 1109 int i; 1110 1111 if (sc->bge_ldata.bge_tx_ring == NULL) 1112 return; 1113 1114 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1115 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1116 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1117 sc->bge_cdata.bge_tx_chain[i] = NULL; 1118 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1119 sc->bge_cdata.bge_tx_dmamap[i]); 1120 } 1121 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1122 sizeof(struct bge_tx_bd)); 1123 } 1124 1125 return; 1126 } 1127 1128 static int 1129 bge_init_tx_ring(sc) 1130 struct bge_softc *sc; 1131 { 1132 sc->bge_txcnt = 0; 1133 sc->bge_tx_saved_considx = 0; 1134 1135 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1136 /* 5700 b2 errata */ 1137 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1138 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1139 1140 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1141 /* 5700 b2 errata */ 1142 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1143 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1144 1145 return(0); 1146 } 1147 1148 static void 1149 bge_setmulti(sc) 1150 struct bge_softc *sc; 1151 { 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1155 int h, i; 1156 1157 BGE_LOCK_ASSERT(sc); 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1162 for (i = 0; i < 4; i++) 1163 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1164 return; 1165 } 1166 1167 /* First, zot all the existing filters. */ 1168 for (i = 0; i < 4; i++) 1169 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1170 1171 /* Now program new ones. */ 1172 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1173 if (ifma->ifma_addr->sa_family != AF_LINK) 1174 continue; 1175 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1176 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1177 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1178 } 1179 1180 for (i = 0; i < 4; i++) 1181 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1182 1183 return; 1184 } 1185 1186 /* 1187 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1188 * self-test results. 1189 */ 1190 static int 1191 bge_chipinit(sc) 1192 struct bge_softc *sc; 1193 { 1194 int i; 1195 u_int32_t dma_rw_ctl; 1196 1197 /* Set endianness before we access any non-PCI registers. */ 1198 #if BYTE_ORDER == BIG_ENDIAN 1199 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1200 BGE_BIGENDIAN_INIT, 4); 1201 #else 1202 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1203 BGE_LITTLEENDIAN_INIT, 4); 1204 #endif 1205 1206 /* 1207 * Check the 'ROM failed' bit on the RX CPU to see if 1208 * self-tests passed. 1209 */ 1210 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1211 printf("bge%d: RX CPU self-diagnostics failed!\n", 1212 sc->bge_unit); 1213 return(ENODEV); 1214 } 1215 1216 /* Clear the MAC control register */ 1217 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1218 1219 /* 1220 * Clear the MAC statistics block in the NIC's 1221 * internal memory. 1222 */ 1223 for (i = BGE_STATS_BLOCK; 1224 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1225 BGE_MEMWIN_WRITE(sc, i, 0); 1226 1227 for (i = BGE_STATUS_BLOCK; 1228 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1229 BGE_MEMWIN_WRITE(sc, i, 0); 1230 1231 /* Set up the PCI DMA control register. */ 1232 if (sc->bge_pcie) { 1233 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1234 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1235 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1236 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1237 BGE_PCISTATE_PCI_BUSMODE) { 1238 /* Conventional PCI bus */ 1239 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1240 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1241 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1242 (0x0F); 1243 } else { 1244 /* PCI-X bus */ 1245 /* 1246 * The 5704 uses a different encoding of read/write 1247 * watermarks. 1248 */ 1249 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1250 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1251 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1252 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1253 else 1254 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1255 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1256 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1257 (0x0F); 1258 1259 /* 1260 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1261 * for hardware bugs. 1262 */ 1263 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1264 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1265 u_int32_t tmp; 1266 1267 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1268 if (tmp == 0x6 || tmp == 0x7) 1269 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1270 } 1271 } 1272 1273 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1274 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1275 sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1276 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1277 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1278 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1279 1280 /* 1281 * Set up general mode register. 1282 */ 1283 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1284 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1285 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1286 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1287 1288 /* 1289 * Disable memory write invalidate. Apparently it is not supported 1290 * properly by these devices. 1291 */ 1292 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1293 1294 #ifdef __brokenalpha__ 1295 /* 1296 * Must insure that we do not cross an 8K (bytes) boundary 1297 * for DMA reads. Our highest limit is 1K bytes. This is a 1298 * restriction on some ALPHA platforms with early revision 1299 * 21174 PCI chipsets, such as the AlphaPC 164lx 1300 */ 1301 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1302 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1303 #endif 1304 1305 /* Set the timer prescaler (always 66Mhz) */ 1306 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1307 1308 return(0); 1309 } 1310 1311 static int 1312 bge_blockinit(sc) 1313 struct bge_softc *sc; 1314 { 1315 struct bge_rcb *rcb; 1316 volatile struct bge_rcb *vrcb; 1317 int i; 1318 1319 /* 1320 * Initialize the memory window pointer register so that 1321 * we can access the first 32K of internal NIC RAM. This will 1322 * allow us to set up the TX send ring RCBs and the RX return 1323 * ring RCBs, plus other things which live in NIC memory. 1324 */ 1325 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1326 1327 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1328 1329 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1330 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1331 /* Configure mbuf memory pool */ 1332 if (sc->bge_extram) { 1333 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1334 BGE_EXT_SSRAM); 1335 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1336 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1337 else 1338 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1339 } else { 1340 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1341 BGE_BUFFPOOL_1); 1342 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1344 else 1345 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1346 } 1347 1348 /* Configure DMA resource pool */ 1349 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1350 BGE_DMA_DESCRIPTORS); 1351 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1352 } 1353 1354 /* Configure mbuf pool watermarks */ 1355 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1356 sc->bge_asicrev == BGE_ASICREV_BCM5750) { 1357 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1359 } else { 1360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1362 } 1363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1364 1365 /* Configure DMA resource watermarks */ 1366 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1367 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1368 1369 /* Enable buffer manager */ 1370 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1371 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1372 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1373 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1374 1375 /* Poll for buffer manager start indication */ 1376 for (i = 0; i < BGE_TIMEOUT; i++) { 1377 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1378 break; 1379 DELAY(10); 1380 } 1381 1382 if (i == BGE_TIMEOUT) { 1383 printf("bge%d: buffer manager failed to start\n", 1384 sc->bge_unit); 1385 return(ENXIO); 1386 } 1387 } 1388 1389 /* Enable flow-through queues */ 1390 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1391 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1392 1393 /* Wait until queue initialization is complete */ 1394 for (i = 0; i < BGE_TIMEOUT; i++) { 1395 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1396 break; 1397 DELAY(10); 1398 } 1399 1400 if (i == BGE_TIMEOUT) { 1401 printf("bge%d: flow-through queue init failed\n", 1402 sc->bge_unit); 1403 return(ENXIO); 1404 } 1405 1406 /* Initialize the standard RX ring control block */ 1407 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1408 rcb->bge_hostaddr.bge_addr_lo = 1409 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1410 rcb->bge_hostaddr.bge_addr_hi = 1411 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1412 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1413 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1414 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 1415 sc->bge_asicrev == BGE_ASICREV_BCM5750) 1416 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1417 else 1418 rcb->bge_maxlen_flags = 1419 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1420 if (sc->bge_extram) 1421 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1422 else 1423 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1424 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1425 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1426 1427 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1428 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1429 1430 /* 1431 * Initialize the jumbo RX ring control block 1432 * We set the 'ring disabled' bit in the flags 1433 * field until we're actually ready to start 1434 * using this ring (i.e. once we set the MTU 1435 * high enough to require it). 1436 */ 1437 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1438 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1439 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1440 1441 rcb->bge_hostaddr.bge_addr_lo = 1442 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1443 rcb->bge_hostaddr.bge_addr_hi = 1444 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1445 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1446 sc->bge_cdata.bge_rx_jumbo_ring_map, 1447 BUS_DMASYNC_PREREAD); 1448 rcb->bge_maxlen_flags = 1449 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1450 BGE_RCB_FLAG_RING_DISABLED); 1451 if (sc->bge_extram) 1452 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1453 else 1454 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1455 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1456 rcb->bge_hostaddr.bge_addr_hi); 1457 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1458 rcb->bge_hostaddr.bge_addr_lo); 1459 1460 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1461 rcb->bge_maxlen_flags); 1462 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1463 1464 /* Set up dummy disabled mini ring RCB */ 1465 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1466 rcb->bge_maxlen_flags = 1467 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1468 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1469 rcb->bge_maxlen_flags); 1470 } 1471 1472 /* 1473 * Set the BD ring replentish thresholds. The recommended 1474 * values are 1/8th the number of descriptors allocated to 1475 * each ring. 1476 */ 1477 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1478 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1479 1480 /* 1481 * Disable all unused send rings by setting the 'ring disabled' 1482 * bit in the flags field of all the TX send ring control blocks. 1483 * These are located in NIC memory. 1484 */ 1485 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1486 BGE_SEND_RING_RCB); 1487 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1488 vrcb->bge_maxlen_flags = 1489 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1490 vrcb->bge_nicaddr = 0; 1491 vrcb++; 1492 } 1493 1494 /* Configure TX RCB 0 (we use only the first ring) */ 1495 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1496 BGE_SEND_RING_RCB); 1497 vrcb->bge_hostaddr.bge_addr_lo = 1498 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1499 vrcb->bge_hostaddr.bge_addr_hi = 1500 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1501 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1502 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1503 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1504 vrcb->bge_maxlen_flags = 1505 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1506 1507 /* Disable all unused RX return rings */ 1508 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1509 BGE_RX_RETURN_RING_RCB); 1510 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1511 vrcb->bge_hostaddr.bge_addr_hi = 0; 1512 vrcb->bge_hostaddr.bge_addr_lo = 0; 1513 vrcb->bge_maxlen_flags = 1514 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1515 BGE_RCB_FLAG_RING_DISABLED); 1516 vrcb->bge_nicaddr = 0; 1517 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1518 (i * (sizeof(u_int64_t))), 0); 1519 vrcb++; 1520 } 1521 1522 /* Initialize RX ring indexes */ 1523 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1524 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1525 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1526 1527 /* 1528 * Set up RX return ring 0 1529 * Note that the NIC address for RX return rings is 0x00000000. 1530 * The return rings live entirely within the host, so the 1531 * nicaddr field in the RCB isn't used. 1532 */ 1533 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1534 BGE_RX_RETURN_RING_RCB); 1535 vrcb->bge_hostaddr.bge_addr_lo = 1536 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1537 vrcb->bge_hostaddr.bge_addr_hi = 1538 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1539 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1540 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1541 vrcb->bge_nicaddr = 0x00000000; 1542 vrcb->bge_maxlen_flags = 1543 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1544 1545 /* Set random backoff seed for TX */ 1546 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1547 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1548 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1549 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1550 BGE_TX_BACKOFF_SEED_MASK); 1551 1552 /* Set inter-packet gap */ 1553 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1554 1555 /* 1556 * Specify which ring to use for packets that don't match 1557 * any RX rules. 1558 */ 1559 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1560 1561 /* 1562 * Configure number of RX lists. One interrupt distribution 1563 * list, sixteen active lists, one bad frames class. 1564 */ 1565 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1566 1567 /* Inialize RX list placement stats mask. */ 1568 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1569 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1570 1571 /* Disable host coalescing until we get it set up */ 1572 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1573 1574 /* Poll to make sure it's shut down. */ 1575 for (i = 0; i < BGE_TIMEOUT; i++) { 1576 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1577 break; 1578 DELAY(10); 1579 } 1580 1581 if (i == BGE_TIMEOUT) { 1582 printf("bge%d: host coalescing engine failed to idle\n", 1583 sc->bge_unit); 1584 return(ENXIO); 1585 } 1586 1587 /* Set up host coalescing defaults */ 1588 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1589 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1590 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1591 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1592 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1593 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1594 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1595 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1596 } 1597 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1598 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1599 1600 /* Set up address of statistics block */ 1601 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1602 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 1603 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1604 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1605 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1606 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1607 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1608 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1609 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1610 } 1611 1612 /* Set up address of status block */ 1613 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1614 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1615 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1616 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1617 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1618 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1619 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1620 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1621 1622 /* Turn on host coalescing state machine */ 1623 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1624 1625 /* Turn on RX BD completion state machine and enable attentions */ 1626 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1627 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1628 1629 /* Turn on RX list placement state machine */ 1630 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1631 1632 /* Turn on RX list selector state machine. */ 1633 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1634 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1635 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1636 1637 /* Turn on DMA, clear stats */ 1638 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1639 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1640 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1641 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1642 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1643 1644 /* Set misc. local control, enable interrupts on attentions */ 1645 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1646 1647 #ifdef notdef 1648 /* Assert GPIO pins for PHY reset */ 1649 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1650 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1651 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1652 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1653 #endif 1654 1655 /* Turn on DMA completion state machine */ 1656 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1657 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1658 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1659 1660 /* Turn on write DMA state machine */ 1661 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1662 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1663 1664 /* Turn on read DMA state machine */ 1665 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1666 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1667 1668 /* Turn on RX data completion state machine */ 1669 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1670 1671 /* Turn on RX BD initiator state machine */ 1672 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1673 1674 /* Turn on RX data and RX BD initiator state machine */ 1675 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1676 1677 /* Turn on Mbuf cluster free state machine */ 1678 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1679 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1680 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1681 1682 /* Turn on send BD completion state machine */ 1683 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1684 1685 /* Turn on send data completion state machine */ 1686 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1687 1688 /* Turn on send data initiator state machine */ 1689 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1690 1691 /* Turn on send BD initiator state machine */ 1692 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1693 1694 /* Turn on send BD selector state machine */ 1695 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1696 1697 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1698 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1699 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1700 1701 /* ack/clear link change events */ 1702 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1703 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1704 BGE_MACSTAT_LINK_CHANGED); 1705 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1706 1707 /* Enable PHY auto polling (for MII/GMII only) */ 1708 if (sc->bge_tbi) { 1709 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1710 } else { 1711 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1712 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1713 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1714 BGE_EVTENB_MI_INTERRUPT); 1715 } 1716 1717 /* Enable link state change attentions. */ 1718 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1719 1720 return(0); 1721 } 1722 1723 /* 1724 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1725 * against our list and return its name if we find a match. Note 1726 * that since the Broadcom controller contains VPD support, we 1727 * can get the device name string from the controller itself instead 1728 * of the compiled-in string. This is a little slow, but it guarantees 1729 * we'll always announce the right product name. 1730 */ 1731 static int 1732 bge_probe(dev) 1733 device_t dev; 1734 { 1735 struct bge_type *t; 1736 struct bge_softc *sc; 1737 char *descbuf; 1738 1739 t = bge_devs; 1740 1741 sc = device_get_softc(dev); 1742 bzero(sc, sizeof(struct bge_softc)); 1743 sc->bge_unit = device_get_unit(dev); 1744 sc->bge_dev = dev; 1745 1746 while(t->bge_name != NULL) { 1747 if ((pci_get_vendor(dev) == t->bge_vid) && 1748 (pci_get_device(dev) == t->bge_did)) { 1749 #ifdef notdef 1750 bge_vpd_read(sc); 1751 device_set_desc(dev, sc->bge_vpd_prodname); 1752 #endif 1753 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1754 if (descbuf == NULL) 1755 return(ENOMEM); 1756 snprintf(descbuf, BGE_DEVDESC_MAX, 1757 "%s, ASIC rev. %#04x", t->bge_name, 1758 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1759 device_set_desc_copy(dev, descbuf); 1760 if (pci_get_subvendor(dev) == DELL_VENDORID) 1761 sc->bge_no_3_led = 1; 1762 free(descbuf, M_TEMP); 1763 return(0); 1764 } 1765 t++; 1766 } 1767 1768 return(ENXIO); 1769 } 1770 1771 static void 1772 bge_dma_free(sc) 1773 struct bge_softc *sc; 1774 { 1775 int i; 1776 1777 1778 /* Destroy DMA maps for RX buffers */ 1779 1780 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1781 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1782 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1783 sc->bge_cdata.bge_rx_std_dmamap[i]); 1784 } 1785 1786 /* Destroy DMA maps for jumbo RX buffers */ 1787 1788 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1789 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1790 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1791 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1792 } 1793 1794 /* Destroy DMA maps for TX buffers */ 1795 1796 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1797 if (sc->bge_cdata.bge_tx_dmamap[i]) 1798 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1799 sc->bge_cdata.bge_tx_dmamap[i]); 1800 } 1801 1802 if (sc->bge_cdata.bge_mtag) 1803 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1804 1805 1806 /* Destroy standard RX ring */ 1807 1808 if (sc->bge_ldata.bge_rx_std_ring) 1809 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1810 sc->bge_ldata.bge_rx_std_ring, 1811 sc->bge_cdata.bge_rx_std_ring_map); 1812 1813 if (sc->bge_cdata.bge_rx_std_ring_map) { 1814 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1815 sc->bge_cdata.bge_rx_std_ring_map); 1816 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1817 sc->bge_cdata.bge_rx_std_ring_map); 1818 } 1819 1820 if (sc->bge_cdata.bge_rx_std_ring_tag) 1821 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1822 1823 /* Destroy jumbo RX ring */ 1824 1825 if (sc->bge_ldata.bge_rx_jumbo_ring) 1826 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1827 sc->bge_ldata.bge_rx_jumbo_ring, 1828 sc->bge_cdata.bge_rx_jumbo_ring_map); 1829 1830 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1831 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1832 sc->bge_cdata.bge_rx_jumbo_ring_map); 1833 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1834 sc->bge_cdata.bge_rx_jumbo_ring_map); 1835 } 1836 1837 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1838 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1839 1840 /* Destroy RX return ring */ 1841 1842 if (sc->bge_ldata.bge_rx_return_ring) 1843 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1844 sc->bge_ldata.bge_rx_return_ring, 1845 sc->bge_cdata.bge_rx_return_ring_map); 1846 1847 if (sc->bge_cdata.bge_rx_return_ring_map) { 1848 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1849 sc->bge_cdata.bge_rx_return_ring_map); 1850 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1851 sc->bge_cdata.bge_rx_return_ring_map); 1852 } 1853 1854 if (sc->bge_cdata.bge_rx_return_ring_tag) 1855 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1856 1857 /* Destroy TX ring */ 1858 1859 if (sc->bge_ldata.bge_tx_ring) 1860 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1861 sc->bge_ldata.bge_tx_ring, 1862 sc->bge_cdata.bge_tx_ring_map); 1863 1864 if (sc->bge_cdata.bge_tx_ring_map) { 1865 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1866 sc->bge_cdata.bge_tx_ring_map); 1867 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1868 sc->bge_cdata.bge_tx_ring_map); 1869 } 1870 1871 if (sc->bge_cdata.bge_tx_ring_tag) 1872 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1873 1874 /* Destroy status block */ 1875 1876 if (sc->bge_ldata.bge_status_block) 1877 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1878 sc->bge_ldata.bge_status_block, 1879 sc->bge_cdata.bge_status_map); 1880 1881 if (sc->bge_cdata.bge_status_map) { 1882 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1883 sc->bge_cdata.bge_status_map); 1884 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1885 sc->bge_cdata.bge_status_map); 1886 } 1887 1888 if (sc->bge_cdata.bge_status_tag) 1889 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1890 1891 /* Destroy statistics block */ 1892 1893 if (sc->bge_ldata.bge_stats) 1894 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1895 sc->bge_ldata.bge_stats, 1896 sc->bge_cdata.bge_stats_map); 1897 1898 if (sc->bge_cdata.bge_stats_map) { 1899 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1900 sc->bge_cdata.bge_stats_map); 1901 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1902 sc->bge_cdata.bge_stats_map); 1903 } 1904 1905 if (sc->bge_cdata.bge_stats_tag) 1906 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1907 1908 /* Destroy the parent tag */ 1909 1910 if (sc->bge_cdata.bge_parent_tag) 1911 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1912 1913 return; 1914 } 1915 1916 static int 1917 bge_dma_alloc(dev) 1918 device_t dev; 1919 { 1920 struct bge_softc *sc; 1921 int nseg, i, error; 1922 struct bge_dmamap_arg ctx; 1923 1924 sc = device_get_softc(dev); 1925 1926 /* 1927 * Allocate the parent bus DMA tag appropriate for PCI. 1928 */ 1929 #define BGE_NSEG_NEW 32 1930 error = bus_dma_tag_create(NULL, /* parent */ 1931 PAGE_SIZE, 0, /* alignment, boundary */ 1932 BUS_SPACE_MAXADDR, /* lowaddr */ 1933 BUS_SPACE_MAXADDR, /* highaddr */ 1934 NULL, NULL, /* filter, filterarg */ 1935 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1936 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1937 0, /* flags */ 1938 NULL, NULL, /* lockfunc, lockarg */ 1939 &sc->bge_cdata.bge_parent_tag); 1940 1941 /* 1942 * Create tag for RX mbufs. 1943 */ 1944 nseg = 32; 1945 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1946 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1947 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, 1948 &sc->bge_cdata.bge_mtag); 1949 1950 if (error) { 1951 device_printf(dev, "could not allocate dma tag\n"); 1952 return (ENOMEM); 1953 } 1954 1955 /* Create DMA maps for RX buffers */ 1956 1957 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1958 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1959 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1960 if (error) { 1961 device_printf(dev, "can't create DMA map for RX\n"); 1962 return(ENOMEM); 1963 } 1964 } 1965 1966 /* Create DMA maps for TX buffers */ 1967 1968 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1969 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1970 &sc->bge_cdata.bge_tx_dmamap[i]); 1971 if (error) { 1972 device_printf(dev, "can't create DMA map for RX\n"); 1973 return(ENOMEM); 1974 } 1975 } 1976 1977 /* Create tag for standard RX ring */ 1978 1979 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1980 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1981 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1982 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1983 1984 if (error) { 1985 device_printf(dev, "could not allocate dma tag\n"); 1986 return (ENOMEM); 1987 } 1988 1989 /* Allocate DMA'able memory for standard RX ring */ 1990 1991 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1992 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1993 &sc->bge_cdata.bge_rx_std_ring_map); 1994 if (error) 1995 return (ENOMEM); 1996 1997 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1998 1999 /* Load the address of the standard RX ring */ 2000 2001 ctx.bge_maxsegs = 1; 2002 ctx.sc = sc; 2003 2004 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2005 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2006 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2007 2008 if (error) 2009 return (ENOMEM); 2010 2011 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2012 2013 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2014 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2015 2016 /* 2017 * Create tag for jumbo mbufs. 2018 * This is really a bit of a kludge. We allocate a special 2019 * jumbo buffer pool which (thanks to the way our DMA 2020 * memory allocation works) will consist of contiguous 2021 * pages. This means that even though a jumbo buffer might 2022 * be larger than a page size, we don't really need to 2023 * map it into more than one DMA segment. However, the 2024 * default mbuf tag will result in multi-segment mappings, 2025 * so we have to create a special jumbo mbuf tag that 2026 * lets us get away with mapping the jumbo buffers as 2027 * a single segment. I think eventually the driver should 2028 * be changed so that it uses ordinary mbufs and cluster 2029 * buffers, i.e. jumbo frames can span multiple DMA 2030 * descriptors. But that's a project for another day. 2031 */ 2032 2033 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2034 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2035 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2036 &sc->bge_cdata.bge_mtag_jumbo); 2037 2038 if (error) { 2039 device_printf(dev, "could not allocate dma tag\n"); 2040 return (ENOMEM); 2041 } 2042 2043 /* Create tag for jumbo RX ring */ 2044 2045 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2046 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2047 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2048 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2049 2050 if (error) { 2051 device_printf(dev, "could not allocate dma tag\n"); 2052 return (ENOMEM); 2053 } 2054 2055 /* Allocate DMA'able memory for jumbo RX ring */ 2056 2057 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2058 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2059 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2060 if (error) 2061 return (ENOMEM); 2062 2063 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2064 BGE_JUMBO_RX_RING_SZ); 2065 2066 /* Load the address of the jumbo RX ring */ 2067 2068 ctx.bge_maxsegs = 1; 2069 ctx.sc = sc; 2070 2071 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2072 sc->bge_cdata.bge_rx_jumbo_ring_map, 2073 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2074 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2075 2076 if (error) 2077 return (ENOMEM); 2078 2079 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2080 2081 /* Create DMA maps for jumbo RX buffers */ 2082 2083 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2084 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2085 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2086 if (error) { 2087 device_printf(dev, 2088 "can't create DMA map for RX\n"); 2089 return(ENOMEM); 2090 } 2091 } 2092 2093 } 2094 2095 /* Create tag for RX return ring */ 2096 2097 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2098 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2099 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2100 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2101 2102 if (error) { 2103 device_printf(dev, "could not allocate dma tag\n"); 2104 return (ENOMEM); 2105 } 2106 2107 /* Allocate DMA'able memory for RX return ring */ 2108 2109 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2110 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2111 &sc->bge_cdata.bge_rx_return_ring_map); 2112 if (error) 2113 return (ENOMEM); 2114 2115 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2116 BGE_RX_RTN_RING_SZ(sc)); 2117 2118 /* Load the address of the RX return ring */ 2119 2120 ctx.bge_maxsegs = 1; 2121 ctx.sc = sc; 2122 2123 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2124 sc->bge_cdata.bge_rx_return_ring_map, 2125 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2126 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2127 2128 if (error) 2129 return (ENOMEM); 2130 2131 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2132 2133 /* Create tag for TX ring */ 2134 2135 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2136 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2137 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2138 &sc->bge_cdata.bge_tx_ring_tag); 2139 2140 if (error) { 2141 device_printf(dev, "could not allocate dma tag\n"); 2142 return (ENOMEM); 2143 } 2144 2145 /* Allocate DMA'able memory for TX ring */ 2146 2147 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2148 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2149 &sc->bge_cdata.bge_tx_ring_map); 2150 if (error) 2151 return (ENOMEM); 2152 2153 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2154 2155 /* Load the address of the TX ring */ 2156 2157 ctx.bge_maxsegs = 1; 2158 ctx.sc = sc; 2159 2160 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2161 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2162 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2163 2164 if (error) 2165 return (ENOMEM); 2166 2167 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2168 2169 /* Create tag for status block */ 2170 2171 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2172 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2173 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2174 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2175 2176 if (error) { 2177 device_printf(dev, "could not allocate dma tag\n"); 2178 return (ENOMEM); 2179 } 2180 2181 /* Allocate DMA'able memory for status block */ 2182 2183 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2184 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2185 &sc->bge_cdata.bge_status_map); 2186 if (error) 2187 return (ENOMEM); 2188 2189 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2190 2191 /* Load the address of the status block */ 2192 2193 ctx.sc = sc; 2194 ctx.bge_maxsegs = 1; 2195 2196 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2197 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2198 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2199 2200 if (error) 2201 return (ENOMEM); 2202 2203 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2204 2205 /* Create tag for statistics block */ 2206 2207 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2208 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2209 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2210 &sc->bge_cdata.bge_stats_tag); 2211 2212 if (error) { 2213 device_printf(dev, "could not allocate dma tag\n"); 2214 return (ENOMEM); 2215 } 2216 2217 /* Allocate DMA'able memory for statistics block */ 2218 2219 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2220 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2221 &sc->bge_cdata.bge_stats_map); 2222 if (error) 2223 return (ENOMEM); 2224 2225 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2226 2227 /* Load the address of the statstics block */ 2228 2229 ctx.sc = sc; 2230 ctx.bge_maxsegs = 1; 2231 2232 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2233 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2234 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2235 2236 if (error) 2237 return (ENOMEM); 2238 2239 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2240 2241 return(0); 2242 } 2243 2244 static int 2245 bge_attach(dev) 2246 device_t dev; 2247 { 2248 struct ifnet *ifp; 2249 struct bge_softc *sc; 2250 u_int32_t hwcfg = 0; 2251 u_int32_t mac_addr = 0; 2252 int unit, error = 0, rid; 2253 2254 sc = device_get_softc(dev); 2255 unit = device_get_unit(dev); 2256 sc->bge_dev = dev; 2257 sc->bge_unit = unit; 2258 2259 /* 2260 * Map control/status registers. 2261 */ 2262 pci_enable_busmaster(dev); 2263 2264 rid = BGE_PCI_BAR0; 2265 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2266 RF_ACTIVE|PCI_RF_DENSE); 2267 2268 if (sc->bge_res == NULL) { 2269 printf ("bge%d: couldn't map memory\n", unit); 2270 error = ENXIO; 2271 goto fail; 2272 } 2273 2274 sc->bge_btag = rman_get_bustag(sc->bge_res); 2275 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2276 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2277 2278 /* Allocate interrupt */ 2279 rid = 0; 2280 2281 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2282 RF_SHAREABLE | RF_ACTIVE); 2283 2284 if (sc->bge_irq == NULL) { 2285 printf("bge%d: couldn't map interrupt\n", unit); 2286 error = ENXIO; 2287 goto fail; 2288 } 2289 2290 sc->bge_unit = unit; 2291 2292 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2293 2294 /* Save ASIC rev. */ 2295 2296 sc->bge_chipid = 2297 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2298 BGE_PCIMISCCTL_ASICREV; 2299 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2300 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2301 2302 /* 2303 * Treat the 5714 like the 5750 until we have more info 2304 * on this chip. 2305 */ 2306 if (sc->bge_asicrev == BGE_ASICREV_BCM5714) 2307 sc->bge_asicrev = BGE_ASICREV_BCM5750; 2308 2309 /* 2310 * XXX: Broadcom Linux driver. Not in specs or eratta. 2311 * PCI-Express? 2312 */ 2313 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2314 u_int32_t v; 2315 2316 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4); 2317 if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) { 2318 v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2319 if ((v & 0xff) == BGE_PCIE_CAPID) 2320 sc->bge_pcie = 1; 2321 } 2322 } 2323 2324 /* Try to reset the chip. */ 2325 bge_reset(sc); 2326 2327 if (bge_chipinit(sc)) { 2328 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2329 bge_release_resources(sc); 2330 error = ENXIO; 2331 goto fail; 2332 } 2333 2334 /* 2335 * Get station address from the EEPROM. 2336 */ 2337 mac_addr = bge_readmem_ind(sc, 0x0c14); 2338 if ((mac_addr >> 16) == 0x484b) { 2339 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2340 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2341 mac_addr = bge_readmem_ind(sc, 0x0c18); 2342 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2343 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2344 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2345 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2346 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2347 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2348 printf("bge%d: failed to read station address\n", unit); 2349 bge_release_resources(sc); 2350 error = ENXIO; 2351 goto fail; 2352 } 2353 2354 /* 5705 limits RX return ring to 512 entries. */ 2355 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 2356 sc->bge_asicrev == BGE_ASICREV_BCM5750) 2357 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2358 else 2359 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2360 2361 if (bge_dma_alloc(dev)) { 2362 printf ("bge%d: failed to allocate DMA resources\n", 2363 sc->bge_unit); 2364 bge_release_resources(sc); 2365 error = ENXIO; 2366 goto fail; 2367 } 2368 2369 /* 2370 * Try to allocate memory for jumbo buffers. 2371 * The 5705 does not appear to support jumbo frames. 2372 */ 2373 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2374 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2375 if (bge_alloc_jumbo_mem(sc)) { 2376 printf("bge%d: jumbo buffer allocation " 2377 "failed\n", sc->bge_unit); 2378 bge_release_resources(sc); 2379 error = ENXIO; 2380 goto fail; 2381 } 2382 } 2383 2384 /* Set default tuneable values. */ 2385 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2386 sc->bge_rx_coal_ticks = 150; 2387 sc->bge_tx_coal_ticks = 150; 2388 sc->bge_rx_max_coal_bds = 64; 2389 sc->bge_tx_max_coal_bds = 128; 2390 2391 /* Set up ifnet structure */ 2392 ifp = &sc->arpcom.ac_if; 2393 ifp->if_softc = sc; 2394 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2396 ifp->if_ioctl = bge_ioctl; 2397 ifp->if_start = bge_start; 2398 ifp->if_watchdog = bge_watchdog; 2399 ifp->if_init = bge_init; 2400 ifp->if_mtu = ETHERMTU; 2401 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2402 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2403 IFQ_SET_READY(&ifp->if_snd); 2404 ifp->if_hwassist = BGE_CSUM_FEATURES; 2405 /* NB: the code for RX csum offload is disabled for now */ 2406 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING | 2407 IFCAP_VLAN_MTU; 2408 ifp->if_capenable = ifp->if_capabilities; 2409 2410 /* 2411 * Figure out what sort of media we have by checking the 2412 * hardware config word in the first 32k of NIC internal memory, 2413 * or fall back to examining the EEPROM if necessary. 2414 * Note: on some BCM5700 cards, this value appears to be unset. 2415 * If that's the case, we have to rely on identifying the NIC 2416 * by its PCI subsystem ID, as we do below for the SysKonnect 2417 * SK-9D41. 2418 */ 2419 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2420 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2421 else { 2422 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2423 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2424 hwcfg = ntohl(hwcfg); 2425 } 2426 2427 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2428 sc->bge_tbi = 1; 2429 2430 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2431 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2432 sc->bge_tbi = 1; 2433 2434 if (sc->bge_tbi) { 2435 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2436 bge_ifmedia_upd, bge_ifmedia_sts); 2437 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2438 ifmedia_add(&sc->bge_ifmedia, 2439 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2440 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2441 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2442 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2443 } else { 2444 /* 2445 * Do transceiver setup. 2446 */ 2447 if (mii_phy_probe(dev, &sc->bge_miibus, 2448 bge_ifmedia_upd, bge_ifmedia_sts)) { 2449 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2450 bge_release_resources(sc); 2451 bge_free_jumbo_mem(sc); 2452 error = ENXIO; 2453 goto fail; 2454 } 2455 } 2456 2457 /* 2458 * When using the BCM5701 in PCI-X mode, data corruption has 2459 * been observed in the first few bytes of some received packets. 2460 * Aligning the packet buffer in memory eliminates the corruption. 2461 * Unfortunately, this misaligns the packet payloads. On platforms 2462 * which do not support unaligned accesses, we will realign the 2463 * payloads by copying the received packets. 2464 */ 2465 switch (sc->bge_chipid) { 2466 case BGE_CHIPID_BCM5701_A0: 2467 case BGE_CHIPID_BCM5701_B0: 2468 case BGE_CHIPID_BCM5701_B2: 2469 case BGE_CHIPID_BCM5701_B5: 2470 /* If in PCI-X mode, work around the alignment bug. */ 2471 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2472 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2473 BGE_PCISTATE_PCI_BUSSPEED) 2474 sc->bge_rx_alignment_bug = 1; 2475 break; 2476 } 2477 2478 /* 2479 * Call MI attach routine. 2480 */ 2481 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2482 callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE); 2483 2484 /* 2485 * Hookup IRQ last. 2486 */ 2487 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2488 bge_intr, sc, &sc->bge_intrhand); 2489 2490 if (error) { 2491 bge_release_resources(sc); 2492 printf("bge%d: couldn't set up irq\n", unit); 2493 } 2494 2495 fail: 2496 return(error); 2497 } 2498 2499 static int 2500 bge_detach(dev) 2501 device_t dev; 2502 { 2503 struct bge_softc *sc; 2504 struct ifnet *ifp; 2505 2506 sc = device_get_softc(dev); 2507 ifp = &sc->arpcom.ac_if; 2508 2509 BGE_LOCK(sc); 2510 bge_stop(sc); 2511 bge_reset(sc); 2512 BGE_UNLOCK(sc); 2513 2514 ether_ifdetach(ifp); 2515 2516 if (sc->bge_tbi) { 2517 ifmedia_removeall(&sc->bge_ifmedia); 2518 } else { 2519 bus_generic_detach(dev); 2520 device_delete_child(dev, sc->bge_miibus); 2521 } 2522 2523 bge_release_resources(sc); 2524 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2525 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2526 bge_free_jumbo_mem(sc); 2527 2528 return(0); 2529 } 2530 2531 static void 2532 bge_release_resources(sc) 2533 struct bge_softc *sc; 2534 { 2535 device_t dev; 2536 2537 dev = sc->bge_dev; 2538 2539 if (sc->bge_vpd_prodname != NULL) 2540 free(sc->bge_vpd_prodname, M_DEVBUF); 2541 2542 if (sc->bge_vpd_readonly != NULL) 2543 free(sc->bge_vpd_readonly, M_DEVBUF); 2544 2545 if (sc->bge_intrhand != NULL) 2546 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2547 2548 if (sc->bge_irq != NULL) 2549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2550 2551 if (sc->bge_res != NULL) 2552 bus_release_resource(dev, SYS_RES_MEMORY, 2553 BGE_PCI_BAR0, sc->bge_res); 2554 2555 bge_dma_free(sc); 2556 2557 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2558 BGE_LOCK_DESTROY(sc); 2559 2560 return; 2561 } 2562 2563 static void 2564 bge_reset(sc) 2565 struct bge_softc *sc; 2566 { 2567 device_t dev; 2568 u_int32_t cachesize, command, pcistate, reset; 2569 int i, val = 0; 2570 2571 dev = sc->bge_dev; 2572 2573 /* Save some important PCI state. */ 2574 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2575 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2576 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2577 2578 pci_write_config(dev, BGE_PCI_MISC_CTL, 2579 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2580 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2581 2582 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2583 2584 /* XXX: Broadcom Linux driver. */ 2585 if (sc->bge_pcie) { 2586 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */ 2587 CSR_WRITE_4(sc, 0x7e2c, 0x20); 2588 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2589 /* Prevent PCIE link training during global reset */ 2590 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2591 reset |= (1<<29); 2592 } 2593 } 2594 2595 /* Issue global reset */ 2596 bge_writereg_ind(sc, BGE_MISC_CFG, reset); 2597 2598 DELAY(1000); 2599 2600 /* XXX: Broadcom Linux driver. */ 2601 if (sc->bge_pcie) { 2602 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2603 uint32_t v; 2604 2605 DELAY(500000); /* wait for link training to complete */ 2606 v = pci_read_config(dev, 0xc4, 4); 2607 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2608 } 2609 /* Set PCIE max payload size and clear error status. */ 2610 pci_write_config(dev, 0xd8, 0xf5000, 4); 2611 } 2612 2613 /* Reset some of the PCI state that got zapped by reset */ 2614 pci_write_config(dev, BGE_PCI_MISC_CTL, 2615 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2616 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2617 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2618 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2619 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2620 2621 /* Enable memory arbiter. */ 2622 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2623 sc->bge_asicrev != BGE_ASICREV_BCM5750) 2624 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2625 2626 /* 2627 * Prevent PXE restart: write a magic number to the 2628 * general communications memory at 0xB50. 2629 */ 2630 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2631 /* 2632 * Poll the value location we just wrote until 2633 * we see the 1's complement of the magic number. 2634 * This indicates that the firmware initialization 2635 * is complete. 2636 */ 2637 for (i = 0; i < BGE_TIMEOUT; i++) { 2638 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2639 if (val == ~BGE_MAGIC_NUMBER) 2640 break; 2641 DELAY(10); 2642 } 2643 2644 if (i == BGE_TIMEOUT) { 2645 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2646 return; 2647 } 2648 2649 /* 2650 * XXX Wait for the value of the PCISTATE register to 2651 * return to its original pre-reset state. This is a 2652 * fairly good indicator of reset completion. If we don't 2653 * wait for the reset to fully complete, trying to read 2654 * from the device's non-PCI registers may yield garbage 2655 * results. 2656 */ 2657 for (i = 0; i < BGE_TIMEOUT; i++) { 2658 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2659 break; 2660 DELAY(10); 2661 } 2662 2663 /* Fix up byte swapping */ 2664 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2665 BGE_MODECTL_BYTESWAP_DATA); 2666 2667 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2668 2669 /* 2670 * The 5704 in TBI mode apparently needs some special 2671 * adjustment to insure the SERDES drive level is set 2672 * to 1.2V. 2673 */ 2674 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) { 2675 uint32_t serdescfg; 2676 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2677 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2678 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2679 } 2680 2681 /* XXX: Broadcom Linux driver. */ 2682 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2683 uint32_t v; 2684 2685 v = CSR_READ_4(sc, 0x7c00); 2686 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 2687 } 2688 DELAY(10000); 2689 2690 return; 2691 } 2692 2693 /* 2694 * Frame reception handling. This is called if there's a frame 2695 * on the receive return list. 2696 * 2697 * Note: we have to be able to handle two possibilities here: 2698 * 1) the frame is from the jumbo recieve ring 2699 * 2) the frame is from the standard receive ring 2700 */ 2701 2702 static void 2703 bge_rxeof(sc) 2704 struct bge_softc *sc; 2705 { 2706 struct ifnet *ifp; 2707 int stdcnt = 0, jumbocnt = 0; 2708 2709 BGE_LOCK_ASSERT(sc); 2710 2711 ifp = &sc->arpcom.ac_if; 2712 2713 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2714 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2715 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2716 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2717 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2718 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2719 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2720 sc->bge_cdata.bge_rx_jumbo_ring_map, 2721 BUS_DMASYNC_POSTREAD); 2722 } 2723 2724 while(sc->bge_rx_saved_considx != 2725 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2726 struct bge_rx_bd *cur_rx; 2727 u_int32_t rxidx; 2728 struct ether_header *eh; 2729 struct mbuf *m = NULL; 2730 u_int16_t vlan_tag = 0; 2731 int have_tag = 0; 2732 2733 cur_rx = 2734 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2735 2736 rxidx = cur_rx->bge_idx; 2737 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2738 2739 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2740 have_tag = 1; 2741 vlan_tag = cur_rx->bge_vlan_tag; 2742 } 2743 2744 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2745 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2746 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2747 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2748 BUS_DMASYNC_POSTREAD); 2749 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2750 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2751 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2752 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2753 jumbocnt++; 2754 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2755 ifp->if_ierrors++; 2756 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2757 continue; 2758 } 2759 if (bge_newbuf_jumbo(sc, 2760 sc->bge_jumbo, NULL) == ENOBUFS) { 2761 ifp->if_ierrors++; 2762 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2763 continue; 2764 } 2765 } else { 2766 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2767 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2768 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2769 BUS_DMASYNC_POSTREAD); 2770 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2771 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2772 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2773 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2774 stdcnt++; 2775 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2776 ifp->if_ierrors++; 2777 bge_newbuf_std(sc, sc->bge_std, m); 2778 continue; 2779 } 2780 if (bge_newbuf_std(sc, sc->bge_std, 2781 NULL) == ENOBUFS) { 2782 ifp->if_ierrors++; 2783 bge_newbuf_std(sc, sc->bge_std, m); 2784 continue; 2785 } 2786 } 2787 2788 ifp->if_ipackets++; 2789 #ifndef __i386__ 2790 /* 2791 * The i386 allows unaligned accesses, but for other 2792 * platforms we must make sure the payload is aligned. 2793 */ 2794 if (sc->bge_rx_alignment_bug) { 2795 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2796 cur_rx->bge_len); 2797 m->m_data += ETHER_ALIGN; 2798 } 2799 #endif 2800 eh = mtod(m, struct ether_header *); 2801 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2802 m->m_pkthdr.rcvif = ifp; 2803 2804 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2805 if (ifp->if_capenable & IFCAP_RXCSUM) { 2806 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2807 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2808 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2809 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2810 m->m_pkthdr.csum_data = 2811 cur_rx->bge_tcp_udp_csum; 2812 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2813 } 2814 } 2815 #endif 2816 2817 /* 2818 * If we received a packet with a vlan tag, 2819 * attach that information to the packet. 2820 */ 2821 if (have_tag) 2822 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2823 2824 BGE_UNLOCK(sc); 2825 (*ifp->if_input)(ifp, m); 2826 BGE_LOCK(sc); 2827 } 2828 2829 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2830 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2831 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2832 sc->bge_cdata.bge_rx_std_ring_map, 2833 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2834 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 2835 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 2836 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2837 sc->bge_cdata.bge_rx_jumbo_ring_map, 2838 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2839 } 2840 2841 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2842 if (stdcnt) 2843 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2844 if (jumbocnt) 2845 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2846 2847 return; 2848 } 2849 2850 static void 2851 bge_txeof(sc) 2852 struct bge_softc *sc; 2853 { 2854 struct bge_tx_bd *cur_tx = NULL; 2855 struct ifnet *ifp; 2856 2857 BGE_LOCK_ASSERT(sc); 2858 2859 ifp = &sc->arpcom.ac_if; 2860 2861 /* 2862 * Go through our tx ring and free mbufs for those 2863 * frames that have been sent. 2864 */ 2865 while (sc->bge_tx_saved_considx != 2866 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2867 u_int32_t idx = 0; 2868 2869 idx = sc->bge_tx_saved_considx; 2870 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2871 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2872 ifp->if_opackets++; 2873 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2874 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2875 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2876 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2877 sc->bge_cdata.bge_tx_dmamap[idx]); 2878 } 2879 sc->bge_txcnt--; 2880 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2881 ifp->if_timer = 0; 2882 } 2883 2884 if (cur_tx != NULL) 2885 ifp->if_flags &= ~IFF_OACTIVE; 2886 2887 return; 2888 } 2889 2890 static void 2891 bge_intr(xsc) 2892 void *xsc; 2893 { 2894 struct bge_softc *sc; 2895 struct ifnet *ifp; 2896 u_int32_t statusword; 2897 u_int32_t status, mimode; 2898 2899 sc = xsc; 2900 ifp = &sc->arpcom.ac_if; 2901 2902 BGE_LOCK(sc); 2903 2904 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2905 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2906 2907 statusword = 2908 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2909 2910 #ifdef notdef 2911 /* Avoid this for now -- checking this register is expensive. */ 2912 /* Make sure this is really our interrupt. */ 2913 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2914 return; 2915 #endif 2916 /* Ack interrupt and stop others from occuring. */ 2917 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2918 2919 /* 2920 * Process link state changes. 2921 * Grrr. The link status word in the status block does 2922 * not work correctly on the BCM5700 rev AX and BX chips, 2923 * according to all available information. Hence, we have 2924 * to enable MII interrupts in order to properly obtain 2925 * async link changes. Unfortunately, this also means that 2926 * we have to read the MAC status register to detect link 2927 * changes, thereby adding an additional register access to 2928 * the interrupt handler. 2929 */ 2930 2931 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2932 2933 status = CSR_READ_4(sc, BGE_MAC_STS); 2934 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2935 sc->bge_link = 0; 2936 callout_stop(&sc->bge_stat_ch); 2937 bge_tick_locked(sc); 2938 /* Clear the interrupt */ 2939 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2940 BGE_EVTENB_MI_INTERRUPT); 2941 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2942 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2943 BRGPHY_INTRS); 2944 } 2945 } else { 2946 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2947 /* 2948 * Sometimes PCS encoding errors are detected in 2949 * TBI mode (on fiber NICs), and for some reason 2950 * the chip will signal them as link changes. 2951 * If we get a link change event, but the 'PCS 2952 * encoding error' bit in the MAC status register 2953 * is set, don't bother doing a link check. 2954 * This avoids spurious "gigabit link up" messages 2955 * that sometimes appear on fiber NICs during 2956 * periods of heavy traffic. (There should be no 2957 * effect on copper NICs.) 2958 * 2959 * If we do have a copper NIC (bge_tbi == 0) then 2960 * check that the AUTOPOLL bit is set before 2961 * processing the event as a real link change. 2962 * Turning AUTOPOLL on and off in the MII read/write 2963 * functions will often trigger a link status 2964 * interrupt for no reason. 2965 */ 2966 status = CSR_READ_4(sc, BGE_MAC_STS); 2967 mimode = CSR_READ_4(sc, BGE_MI_MODE); 2968 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2969 BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi && 2970 (mimode & BGE_MIMODE_AUTOPOLL))) { 2971 sc->bge_link = 0; 2972 callout_stop(&sc->bge_stat_ch); 2973 bge_tick_locked(sc); 2974 } 2975 /* Clear the interrupt */ 2976 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2977 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2978 BGE_MACSTAT_LINK_CHANGED); 2979 2980 /* Force flush the status block cached by PCI bridge */ 2981 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2982 } 2983 } 2984 2985 if (ifp->if_flags & IFF_RUNNING) { 2986 /* Check RX return ring producer/consumer */ 2987 bge_rxeof(sc); 2988 2989 /* Check TX ring producer/consumer */ 2990 bge_txeof(sc); 2991 } 2992 2993 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2994 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2995 2996 bge_handle_events(sc); 2997 2998 /* Re-enable interrupts. */ 2999 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3000 3001 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3002 bge_start_locked(ifp); 3003 3004 BGE_UNLOCK(sc); 3005 3006 return; 3007 } 3008 3009 static void 3010 bge_tick_locked(sc) 3011 struct bge_softc *sc; 3012 { 3013 struct mii_data *mii = NULL; 3014 struct ifmedia *ifm = NULL; 3015 struct ifnet *ifp; 3016 3017 ifp = &sc->arpcom.ac_if; 3018 3019 BGE_LOCK_ASSERT(sc); 3020 3021 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 || 3022 sc->bge_asicrev == BGE_ASICREV_BCM5750) 3023 bge_stats_update_regs(sc); 3024 else 3025 bge_stats_update(sc); 3026 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3027 if (sc->bge_link) 3028 return; 3029 3030 if (sc->bge_tbi) { 3031 ifm = &sc->bge_ifmedia; 3032 if (CSR_READ_4(sc, BGE_MAC_STS) & 3033 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3034 sc->bge_link++; 3035 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 3036 BGE_CLRBIT(sc, BGE_MAC_MODE, 3037 BGE_MACMODE_TBI_SEND_CFGS); 3038 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3039 if (bootverbose) 3040 printf("bge%d: gigabit link up\n", 3041 sc->bge_unit); 3042 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3043 bge_start_locked(ifp); 3044 } 3045 return; 3046 } 3047 3048 mii = device_get_softc(sc->bge_miibus); 3049 mii_tick(mii); 3050 3051 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3052 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3053 sc->bge_link++; 3054 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 3055 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 3056 bootverbose) 3057 printf("bge%d: gigabit link up\n", sc->bge_unit); 3058 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3059 bge_start_locked(ifp); 3060 } 3061 3062 return; 3063 } 3064 3065 static void 3066 bge_tick(xsc) 3067 void *xsc; 3068 { 3069 struct bge_softc *sc; 3070 3071 sc = xsc; 3072 3073 BGE_LOCK(sc); 3074 bge_tick_locked(sc); 3075 BGE_UNLOCK(sc); 3076 } 3077 3078 static void 3079 bge_stats_update_regs(sc) 3080 struct bge_softc *sc; 3081 { 3082 struct ifnet *ifp; 3083 struct bge_mac_stats_regs stats; 3084 u_int32_t *s; 3085 int i; 3086 3087 ifp = &sc->arpcom.ac_if; 3088 3089 s = (u_int32_t *)&stats; 3090 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3091 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3092 s++; 3093 } 3094 3095 ifp->if_collisions += 3096 (stats.dot3StatsSingleCollisionFrames + 3097 stats.dot3StatsMultipleCollisionFrames + 3098 stats.dot3StatsExcessiveCollisions + 3099 stats.dot3StatsLateCollisions) - 3100 ifp->if_collisions; 3101 3102 return; 3103 } 3104 3105 static void 3106 bge_stats_update(sc) 3107 struct bge_softc *sc; 3108 { 3109 struct ifnet *ifp; 3110 struct bge_stats *stats; 3111 3112 ifp = &sc->arpcom.ac_if; 3113 3114 stats = (struct bge_stats *)(sc->bge_vhandle + 3115 BGE_MEMWIN_START + BGE_STATS_BLOCK); 3116 3117 ifp->if_collisions += 3118 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3119 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3120 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3121 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3122 ifp->if_collisions; 3123 3124 #ifdef notdef 3125 ifp->if_collisions += 3126 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3127 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3128 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3129 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3130 ifp->if_collisions; 3131 #endif 3132 3133 return; 3134 } 3135 3136 /* 3137 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3138 * pointers to descriptors. 3139 */ 3140 static int 3141 bge_encap(sc, m_head, txidx) 3142 struct bge_softc *sc; 3143 struct mbuf *m_head; 3144 u_int32_t *txidx; 3145 { 3146 struct bge_tx_bd *f = NULL; 3147 u_int16_t csum_flags = 0; 3148 struct m_tag *mtag; 3149 struct bge_dmamap_arg ctx; 3150 bus_dmamap_t map; 3151 int error; 3152 3153 3154 if (m_head->m_pkthdr.csum_flags) { 3155 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3156 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3157 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3158 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3159 if (m_head->m_flags & M_LASTFRAG) 3160 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3161 else if (m_head->m_flags & M_FRAG) 3162 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3163 } 3164 3165 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3166 3167 ctx.sc = sc; 3168 ctx.bge_idx = *txidx; 3169 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3170 ctx.bge_flags = csum_flags; 3171 /* 3172 * Sanity check: avoid coming within 16 descriptors 3173 * of the end of the ring. 3174 */ 3175 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3176 3177 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3178 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3179 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3180 3181 if (error || ctx.bge_maxsegs == 0 /*|| 3182 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3183 return (ENOBUFS); 3184 3185 /* 3186 * Insure that the map for this transmission 3187 * is placed at the array index of the last descriptor 3188 * in this chain. 3189 */ 3190 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3191 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3192 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3193 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3194 sc->bge_txcnt += ctx.bge_maxsegs; 3195 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3196 if (mtag != NULL) { 3197 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3198 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3199 } else { 3200 f->bge_vlan_tag = 0; 3201 } 3202 3203 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3204 *txidx = ctx.bge_idx; 3205 3206 return(0); 3207 } 3208 3209 /* 3210 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3211 * to the mbuf data regions directly in the transmit descriptors. 3212 */ 3213 static void 3214 bge_start_locked(ifp) 3215 struct ifnet *ifp; 3216 { 3217 struct bge_softc *sc; 3218 struct mbuf *m_head = NULL; 3219 u_int32_t prodidx = 0; 3220 int count = 0; 3221 3222 sc = ifp->if_softc; 3223 3224 if (!sc->bge_link && IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3225 return; 3226 3227 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3228 3229 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3230 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3231 if (m_head == NULL) 3232 break; 3233 3234 /* 3235 * XXX 3236 * The code inside the if() block is never reached since we 3237 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3238 * requests to checksum TCP/UDP in a fragmented packet. 3239 * 3240 * XXX 3241 * safety overkill. If this is a fragmented packet chain 3242 * with delayed TCP/UDP checksums, then only encapsulate 3243 * it if we have enough descriptors to handle the entire 3244 * chain at once. 3245 * (paranoia -- may not actually be needed) 3246 */ 3247 if (m_head->m_flags & M_FIRSTFRAG && 3248 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3249 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3250 m_head->m_pkthdr.csum_data + 16) { 3251 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3252 ifp->if_flags |= IFF_OACTIVE; 3253 break; 3254 } 3255 } 3256 3257 /* 3258 * Pack the data into the transmit ring. If we 3259 * don't have room, set the OACTIVE flag and wait 3260 * for the NIC to drain the ring. 3261 */ 3262 if (bge_encap(sc, m_head, &prodidx)) { 3263 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3264 ifp->if_flags |= IFF_OACTIVE; 3265 break; 3266 } 3267 ++count; 3268 3269 /* 3270 * If there's a BPF listener, bounce a copy of this frame 3271 * to him. 3272 */ 3273 BPF_MTAP(ifp, m_head); 3274 } 3275 3276 if (count == 0) { 3277 /* no packets were dequeued */ 3278 return; 3279 } 3280 3281 /* Transmit */ 3282 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3283 /* 5700 b2 errata */ 3284 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3285 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3286 3287 /* 3288 * Set a timeout in case the chip goes out to lunch. 3289 */ 3290 ifp->if_timer = 5; 3291 3292 return; 3293 } 3294 3295 /* 3296 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3297 * to the mbuf data regions directly in the transmit descriptors. 3298 */ 3299 static void 3300 bge_start(ifp) 3301 struct ifnet *ifp; 3302 { 3303 struct bge_softc *sc; 3304 3305 sc = ifp->if_softc; 3306 BGE_LOCK(sc); 3307 bge_start_locked(ifp); 3308 BGE_UNLOCK(sc); 3309 } 3310 3311 static void 3312 bge_init_locked(sc) 3313 struct bge_softc *sc; 3314 { 3315 struct ifnet *ifp; 3316 u_int16_t *m; 3317 3318 BGE_LOCK_ASSERT(sc); 3319 3320 ifp = &sc->arpcom.ac_if; 3321 3322 if (ifp->if_flags & IFF_RUNNING) 3323 return; 3324 3325 /* Cancel pending I/O and flush buffers. */ 3326 bge_stop(sc); 3327 bge_reset(sc); 3328 bge_chipinit(sc); 3329 3330 /* 3331 * Init the various state machines, ring 3332 * control blocks and firmware. 3333 */ 3334 if (bge_blockinit(sc)) { 3335 printf("bge%d: initialization failure\n", sc->bge_unit); 3336 return; 3337 } 3338 3339 ifp = &sc->arpcom.ac_if; 3340 3341 /* Specify MTU. */ 3342 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3343 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3344 3345 /* Load our MAC address. */ 3346 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3347 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3348 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3349 3350 /* Enable or disable promiscuous mode as needed. */ 3351 if (ifp->if_flags & IFF_PROMISC) { 3352 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3353 } else { 3354 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3355 } 3356 3357 /* Program multicast filter. */ 3358 bge_setmulti(sc); 3359 3360 /* Init RX ring. */ 3361 bge_init_rx_ring_std(sc); 3362 3363 /* 3364 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3365 * memory to insure that the chip has in fact read the first 3366 * entry of the ring. 3367 */ 3368 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3369 u_int32_t v, i; 3370 for (i = 0; i < 10; i++) { 3371 DELAY(20); 3372 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3373 if (v == (MCLBYTES - ETHER_ALIGN)) 3374 break; 3375 } 3376 if (i == 10) 3377 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3378 sc->bge_unit); 3379 } 3380 3381 /* Init jumbo RX ring. */ 3382 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3383 bge_init_rx_ring_jumbo(sc); 3384 3385 /* Init our RX return ring index */ 3386 sc->bge_rx_saved_considx = 0; 3387 3388 /* Init TX ring. */ 3389 bge_init_tx_ring(sc); 3390 3391 /* Turn on transmitter */ 3392 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3393 3394 /* Turn on receiver */ 3395 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3396 3397 /* Tell firmware we're alive. */ 3398 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3399 3400 /* Enable host interrupts. */ 3401 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3402 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3403 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3404 3405 bge_ifmedia_upd(ifp); 3406 3407 ifp->if_flags |= IFF_RUNNING; 3408 ifp->if_flags &= ~IFF_OACTIVE; 3409 3410 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3411 3412 return; 3413 } 3414 3415 static void 3416 bge_init(xsc) 3417 void *xsc; 3418 { 3419 struct bge_softc *sc = xsc; 3420 3421 BGE_LOCK(sc); 3422 bge_init_locked(sc); 3423 BGE_UNLOCK(sc); 3424 3425 return; 3426 } 3427 3428 /* 3429 * Set media options. 3430 */ 3431 static int 3432 bge_ifmedia_upd(ifp) 3433 struct ifnet *ifp; 3434 { 3435 struct bge_softc *sc; 3436 struct mii_data *mii; 3437 struct ifmedia *ifm; 3438 3439 sc = ifp->if_softc; 3440 ifm = &sc->bge_ifmedia; 3441 3442 /* If this is a 1000baseX NIC, enable the TBI port. */ 3443 if (sc->bge_tbi) { 3444 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3445 return(EINVAL); 3446 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3447 case IFM_AUTO: 3448 break; 3449 case IFM_1000_SX: 3450 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3451 BGE_CLRBIT(sc, BGE_MAC_MODE, 3452 BGE_MACMODE_HALF_DUPLEX); 3453 } else { 3454 BGE_SETBIT(sc, BGE_MAC_MODE, 3455 BGE_MACMODE_HALF_DUPLEX); 3456 } 3457 break; 3458 default: 3459 return(EINVAL); 3460 } 3461 return(0); 3462 } 3463 3464 mii = device_get_softc(sc->bge_miibus); 3465 sc->bge_link = 0; 3466 if (mii->mii_instance) { 3467 struct mii_softc *miisc; 3468 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3469 miisc = LIST_NEXT(miisc, mii_list)) 3470 mii_phy_reset(miisc); 3471 } 3472 mii_mediachg(mii); 3473 3474 return(0); 3475 } 3476 3477 /* 3478 * Report current media status. 3479 */ 3480 static void 3481 bge_ifmedia_sts(ifp, ifmr) 3482 struct ifnet *ifp; 3483 struct ifmediareq *ifmr; 3484 { 3485 struct bge_softc *sc; 3486 struct mii_data *mii; 3487 3488 sc = ifp->if_softc; 3489 3490 if (sc->bge_tbi) { 3491 ifmr->ifm_status = IFM_AVALID; 3492 ifmr->ifm_active = IFM_ETHER; 3493 if (CSR_READ_4(sc, BGE_MAC_STS) & 3494 BGE_MACSTAT_TBI_PCS_SYNCHED) 3495 ifmr->ifm_status |= IFM_ACTIVE; 3496 ifmr->ifm_active |= IFM_1000_SX; 3497 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3498 ifmr->ifm_active |= IFM_HDX; 3499 else 3500 ifmr->ifm_active |= IFM_FDX; 3501 return; 3502 } 3503 3504 mii = device_get_softc(sc->bge_miibus); 3505 mii_pollstat(mii); 3506 ifmr->ifm_active = mii->mii_media_active; 3507 ifmr->ifm_status = mii->mii_media_status; 3508 3509 return; 3510 } 3511 3512 static int 3513 bge_ioctl(ifp, command, data) 3514 struct ifnet *ifp; 3515 u_long command; 3516 caddr_t data; 3517 { 3518 struct bge_softc *sc = ifp->if_softc; 3519 struct ifreq *ifr = (struct ifreq *) data; 3520 int mask, error = 0; 3521 struct mii_data *mii; 3522 3523 switch(command) { 3524 case SIOCSIFMTU: 3525 /* Disallow jumbo frames on 5705. */ 3526 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 || 3527 sc->bge_asicrev == BGE_ASICREV_BCM5750) && 3528 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3529 error = EINVAL; 3530 else { 3531 ifp->if_mtu = ifr->ifr_mtu; 3532 ifp->if_flags &= ~IFF_RUNNING; 3533 bge_init(sc); 3534 } 3535 break; 3536 case SIOCSIFFLAGS: 3537 BGE_LOCK(sc); 3538 if (ifp->if_flags & IFF_UP) { 3539 /* 3540 * If only the state of the PROMISC flag changed, 3541 * then just use the 'set promisc mode' command 3542 * instead of reinitializing the entire NIC. Doing 3543 * a full re-init means reloading the firmware and 3544 * waiting for it to start up, which may take a 3545 * second or two. 3546 */ 3547 if (ifp->if_flags & IFF_RUNNING && 3548 ifp->if_flags & IFF_PROMISC && 3549 !(sc->bge_if_flags & IFF_PROMISC)) { 3550 BGE_SETBIT(sc, BGE_RX_MODE, 3551 BGE_RXMODE_RX_PROMISC); 3552 } else if (ifp->if_flags & IFF_RUNNING && 3553 !(ifp->if_flags & IFF_PROMISC) && 3554 sc->bge_if_flags & IFF_PROMISC) { 3555 BGE_CLRBIT(sc, BGE_RX_MODE, 3556 BGE_RXMODE_RX_PROMISC); 3557 } else 3558 bge_init_locked(sc); 3559 } else { 3560 if (ifp->if_flags & IFF_RUNNING) { 3561 bge_stop(sc); 3562 } 3563 } 3564 sc->bge_if_flags = ifp->if_flags; 3565 BGE_UNLOCK(sc); 3566 error = 0; 3567 break; 3568 case SIOCADDMULTI: 3569 case SIOCDELMULTI: 3570 if (ifp->if_flags & IFF_RUNNING) { 3571 BGE_LOCK(sc); 3572 bge_setmulti(sc); 3573 BGE_UNLOCK(sc); 3574 error = 0; 3575 } 3576 break; 3577 case SIOCSIFMEDIA: 3578 case SIOCGIFMEDIA: 3579 if (sc->bge_tbi) { 3580 error = ifmedia_ioctl(ifp, ifr, 3581 &sc->bge_ifmedia, command); 3582 } else { 3583 mii = device_get_softc(sc->bge_miibus); 3584 error = ifmedia_ioctl(ifp, ifr, 3585 &mii->mii_media, command); 3586 } 3587 break; 3588 case SIOCSIFCAP: 3589 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3590 /* NB: the code for RX csum offload is disabled for now */ 3591 if (mask & IFCAP_TXCSUM) { 3592 ifp->if_capenable ^= IFCAP_TXCSUM; 3593 if (IFCAP_TXCSUM & ifp->if_capenable) 3594 ifp->if_hwassist = BGE_CSUM_FEATURES; 3595 else 3596 ifp->if_hwassist = 0; 3597 } 3598 error = 0; 3599 break; 3600 default: 3601 error = ether_ioctl(ifp, command, data); 3602 break; 3603 } 3604 3605 return(error); 3606 } 3607 3608 static void 3609 bge_watchdog(ifp) 3610 struct ifnet *ifp; 3611 { 3612 struct bge_softc *sc; 3613 3614 sc = ifp->if_softc; 3615 3616 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3617 3618 ifp->if_flags &= ~IFF_RUNNING; 3619 bge_init(sc); 3620 3621 ifp->if_oerrors++; 3622 3623 return; 3624 } 3625 3626 /* 3627 * Stop the adapter and free any mbufs allocated to the 3628 * RX and TX lists. 3629 */ 3630 static void 3631 bge_stop(sc) 3632 struct bge_softc *sc; 3633 { 3634 struct ifnet *ifp; 3635 struct ifmedia_entry *ifm; 3636 struct mii_data *mii = NULL; 3637 int mtmp, itmp; 3638 3639 BGE_LOCK_ASSERT(sc); 3640 3641 ifp = &sc->arpcom.ac_if; 3642 3643 if (!sc->bge_tbi) 3644 mii = device_get_softc(sc->bge_miibus); 3645 3646 callout_stop(&sc->bge_stat_ch); 3647 3648 /* 3649 * Disable all of the receiver blocks 3650 */ 3651 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3652 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3653 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3654 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 3655 sc->bge_asicrev != BGE_ASICREV_BCM5750) 3656 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3657 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3658 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3659 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3660 3661 /* 3662 * Disable all of the transmit blocks 3663 */ 3664 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3665 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3666 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3667 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3668 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3669 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 3670 sc->bge_asicrev != BGE_ASICREV_BCM5750) 3671 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3672 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3673 3674 /* 3675 * Shut down all of the memory managers and related 3676 * state machines. 3677 */ 3678 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3679 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3680 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 3681 sc->bge_asicrev != BGE_ASICREV_BCM5750) 3682 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3683 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3684 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3685 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 3686 sc->bge_asicrev != BGE_ASICREV_BCM5750) { 3687 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3688 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3689 } 3690 3691 /* Disable host interrupts. */ 3692 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3693 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3694 3695 /* 3696 * Tell firmware we're shutting down. 3697 */ 3698 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3699 3700 /* Free the RX lists. */ 3701 bge_free_rx_ring_std(sc); 3702 3703 /* Free jumbo RX list. */ 3704 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 3705 sc->bge_asicrev != BGE_ASICREV_BCM5750) 3706 bge_free_rx_ring_jumbo(sc); 3707 3708 /* Free TX buffers. */ 3709 bge_free_tx_ring(sc); 3710 3711 /* 3712 * Isolate/power down the PHY, but leave the media selection 3713 * unchanged so that things will be put back to normal when 3714 * we bring the interface back up. 3715 */ 3716 if (!sc->bge_tbi) { 3717 itmp = ifp->if_flags; 3718 ifp->if_flags |= IFF_UP; 3719 ifm = mii->mii_media.ifm_cur; 3720 mtmp = ifm->ifm_media; 3721 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3722 mii_mediachg(mii); 3723 ifm->ifm_media = mtmp; 3724 ifp->if_flags = itmp; 3725 } 3726 3727 sc->bge_link = 0; 3728 3729 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3730 3731 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3732 3733 return; 3734 } 3735 3736 /* 3737 * Stop all chip I/O so that the kernel's probe routines don't 3738 * get confused by errant DMAs when rebooting. 3739 */ 3740 static void 3741 bge_shutdown(dev) 3742 device_t dev; 3743 { 3744 struct bge_softc *sc; 3745 3746 sc = device_get_softc(dev); 3747 3748 BGE_LOCK(sc); 3749 bge_stop(sc); 3750 bge_reset(sc); 3751 BGE_UNLOCK(sc); 3752 3753 return; 3754 } 3755