1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/cdefs.h> 70 __FBSDID("$FreeBSD$"); 71 72 #include <sys/param.h> 73 #include <sys/endian.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <machine/clock.h> /* for DELAY */ 98 #include <machine/bus_memio.h> 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 112 #include <dev/bge/if_bgereg.h> 113 114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 115 116 MODULE_DEPEND(bge, pci, 1, 1, 1); 117 MODULE_DEPEND(bge, ether, 1, 1, 1); 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Various supported device vendors/types and their names. Note: the 125 * spec seems to indicate that the hardware still has Alteon's vendor 126 * ID burned into it, though it will always be overriden by the vendor 127 * ID in the EEPROM. Just to be safe, we cover all possibilities. 128 */ 129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 130 131 static struct bge_type bge_devs[] = { 132 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 141 "Broadcom BCM5702 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 145 "Broadcom BCM5703 Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 149 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 151 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 153 "Broadcom BCM5705 Gigabit Ethernet" }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 155 "Broadcom BCM5705M Gigabit Ethernet" }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 157 "Broadcom BCM5705M Gigabit Ethernet" }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 159 "Broadcom BCM5782 Gigabit Ethernet" }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788, 161 "Broadcom BCM5788 Gigabit Ethernet" }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 163 "Broadcom BCM5901 Fast Ethernet" }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 165 "Broadcom BCM5901A2 Fast Ethernet" }, 166 { SK_VENDORID, SK_DEVICEID_ALTIMA, 167 "SysKonnect Gigabit Ethernet" }, 168 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 169 "Altima AC1000 Gigabit Ethernet" }, 170 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 171 "Altima AC9100 Gigabit Ethernet" }, 172 { 0, 0, NULL } 173 }; 174 175 static int bge_probe (device_t); 176 static int bge_attach (device_t); 177 static int bge_detach (device_t); 178 static void bge_release_resources 179 (struct bge_softc *); 180 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 181 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 182 bus_size_t, int); 183 static int bge_dma_alloc (device_t); 184 static void bge_dma_free (struct bge_softc *); 185 186 static void bge_txeof (struct bge_softc *); 187 static void bge_rxeof (struct bge_softc *); 188 189 static void bge_tick (void *); 190 static void bge_stats_update (struct bge_softc *); 191 static void bge_stats_update_regs 192 (struct bge_softc *); 193 static int bge_encap (struct bge_softc *, struct mbuf *, 194 u_int32_t *); 195 196 static void bge_intr (void *); 197 static void bge_start (struct ifnet *); 198 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 199 static void bge_init (void *); 200 static void bge_stop (struct bge_softc *); 201 static void bge_watchdog (struct ifnet *); 202 static void bge_shutdown (device_t); 203 static int bge_ifmedia_upd (struct ifnet *); 204 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 205 206 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 207 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 208 209 static u_int32_t bge_crc (caddr_t); 210 static void bge_setmulti (struct bge_softc *); 211 212 static void bge_handle_events (struct bge_softc *); 213 static int bge_alloc_jumbo_mem (struct bge_softc *); 214 static void bge_free_jumbo_mem (struct bge_softc *); 215 static void *bge_jalloc (struct bge_softc *); 216 static void bge_jfree (void *, void *); 217 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 218 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 219 static int bge_init_rx_ring_std (struct bge_softc *); 220 static void bge_free_rx_ring_std (struct bge_softc *); 221 static int bge_init_rx_ring_jumbo (struct bge_softc *); 222 static void bge_free_rx_ring_jumbo (struct bge_softc *); 223 static void bge_free_tx_ring (struct bge_softc *); 224 static int bge_init_tx_ring (struct bge_softc *); 225 226 static int bge_chipinit (struct bge_softc *); 227 static int bge_blockinit (struct bge_softc *); 228 229 #ifdef notdef 230 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 231 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 232 static void bge_vpd_read (struct bge_softc *); 233 #endif 234 235 static u_int32_t bge_readmem_ind 236 (struct bge_softc *, int); 237 static void bge_writemem_ind (struct bge_softc *, int, int); 238 #ifdef notdef 239 static u_int32_t bge_readreg_ind 240 (struct bge_softc *, int); 241 #endif 242 static void bge_writereg_ind (struct bge_softc *, int, int); 243 244 static int bge_miibus_readreg (device_t, int, int); 245 static int bge_miibus_writereg (device_t, int, int, int); 246 static void bge_miibus_statchg (device_t); 247 248 static void bge_reset (struct bge_softc *); 249 250 static device_method_t bge_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, bge_probe), 253 DEVMETHOD(device_attach, bge_attach), 254 DEVMETHOD(device_detach, bge_detach), 255 DEVMETHOD(device_shutdown, bge_shutdown), 256 257 /* bus interface */ 258 DEVMETHOD(bus_print_child, bus_generic_print_child), 259 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 260 261 /* MII interface */ 262 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 263 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 264 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 265 266 { 0, 0 } 267 }; 268 269 static driver_t bge_driver = { 270 "bge", 271 bge_methods, 272 sizeof(struct bge_softc) 273 }; 274 275 static devclass_t bge_devclass; 276 277 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 278 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 279 280 static u_int32_t 281 bge_readmem_ind(sc, off) 282 struct bge_softc *sc; 283 int off; 284 { 285 device_t dev; 286 287 dev = sc->bge_dev; 288 289 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 290 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 291 } 292 293 static void 294 bge_writemem_ind(sc, off, val) 295 struct bge_softc *sc; 296 int off, val; 297 { 298 device_t dev; 299 300 dev = sc->bge_dev; 301 302 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 303 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 304 305 return; 306 } 307 308 #ifdef notdef 309 static u_int32_t 310 bge_readreg_ind(sc, off) 311 struct bge_softc *sc; 312 int off; 313 { 314 device_t dev; 315 316 dev = sc->bge_dev; 317 318 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 319 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 320 } 321 #endif 322 323 static void 324 bge_writereg_ind(sc, off, val) 325 struct bge_softc *sc; 326 int off, val; 327 { 328 device_t dev; 329 330 dev = sc->bge_dev; 331 332 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 333 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 334 335 return; 336 } 337 338 /* 339 * Map a single buffer address. 340 */ 341 342 static void 343 bge_dma_map_addr(arg, segs, nseg, error) 344 void *arg; 345 bus_dma_segment_t *segs; 346 int nseg; 347 int error; 348 { 349 struct bge_dmamap_arg *ctx; 350 351 if (error) 352 return; 353 354 ctx = arg; 355 356 if (nseg > ctx->bge_maxsegs) { 357 ctx->bge_maxsegs = 0; 358 return; 359 } 360 361 ctx->bge_busaddr = segs->ds_addr; 362 363 return; 364 } 365 366 /* 367 * Map an mbuf chain into an TX ring. 368 */ 369 370 static void 371 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 372 void *arg; 373 bus_dma_segment_t *segs; 374 int nseg; 375 bus_size_t mapsize; 376 int error; 377 { 378 struct bge_dmamap_arg *ctx; 379 struct bge_tx_bd *d = NULL; 380 int i = 0, idx; 381 382 if (error) 383 return; 384 385 ctx = arg; 386 387 /* Signal error to caller if there's too many segments */ 388 if (nseg > ctx->bge_maxsegs) { 389 ctx->bge_maxsegs = 0; 390 return; 391 } 392 393 idx = ctx->bge_idx; 394 while(1) { 395 d = &ctx->bge_ring[idx]; 396 d->bge_addr.bge_addr_lo = 397 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 398 d->bge_addr.bge_addr_hi = 399 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 400 d->bge_len = htole16(segs[i].ds_len); 401 d->bge_flags = htole16(ctx->bge_flags); 402 i++; 403 if (i == nseg) 404 break; 405 BGE_INC(idx, BGE_TX_RING_CNT); 406 } 407 408 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 409 ctx->bge_maxsegs = nseg; 410 ctx->bge_idx = idx; 411 412 return; 413 } 414 415 416 #ifdef notdef 417 static u_int8_t 418 bge_vpd_readbyte(sc, addr) 419 struct bge_softc *sc; 420 int addr; 421 { 422 int i; 423 device_t dev; 424 u_int32_t val; 425 426 dev = sc->bge_dev; 427 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 428 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 429 DELAY(10); 430 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 431 break; 432 } 433 434 if (i == BGE_TIMEOUT) { 435 printf("bge%d: VPD read timed out\n", sc->bge_unit); 436 return(0); 437 } 438 439 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 440 441 return((val >> ((addr % 4) * 8)) & 0xFF); 442 } 443 444 static void 445 bge_vpd_read_res(sc, res, addr) 446 struct bge_softc *sc; 447 struct vpd_res *res; 448 int addr; 449 { 450 int i; 451 u_int8_t *ptr; 452 453 ptr = (u_int8_t *)res; 454 for (i = 0; i < sizeof(struct vpd_res); i++) 455 ptr[i] = bge_vpd_readbyte(sc, i + addr); 456 457 return; 458 } 459 460 static void 461 bge_vpd_read(sc) 462 struct bge_softc *sc; 463 { 464 int pos = 0, i; 465 struct vpd_res res; 466 467 if (sc->bge_vpd_prodname != NULL) 468 free(sc->bge_vpd_prodname, M_DEVBUF); 469 if (sc->bge_vpd_readonly != NULL) 470 free(sc->bge_vpd_readonly, M_DEVBUF); 471 sc->bge_vpd_prodname = NULL; 472 sc->bge_vpd_readonly = NULL; 473 474 bge_vpd_read_res(sc, &res, pos); 475 476 if (res.vr_id != VPD_RES_ID) { 477 printf("bge%d: bad VPD resource id: expected %x got %x\n", 478 sc->bge_unit, VPD_RES_ID, res.vr_id); 479 return; 480 } 481 482 pos += sizeof(res); 483 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 484 for (i = 0; i < res.vr_len; i++) 485 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 486 sc->bge_vpd_prodname[i] = '\0'; 487 pos += i; 488 489 bge_vpd_read_res(sc, &res, pos); 490 491 if (res.vr_id != VPD_RES_READ) { 492 printf("bge%d: bad VPD resource id: expected %x got %x\n", 493 sc->bge_unit, VPD_RES_READ, res.vr_id); 494 return; 495 } 496 497 pos += sizeof(res); 498 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 499 for (i = 0; i < res.vr_len + 1; i++) 500 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 501 502 return; 503 } 504 #endif 505 506 /* 507 * Read a byte of data stored in the EEPROM at address 'addr.' The 508 * BCM570x supports both the traditional bitbang interface and an 509 * auto access interface for reading the EEPROM. We use the auto 510 * access method. 511 */ 512 static u_int8_t 513 bge_eeprom_getbyte(sc, addr, dest) 514 struct bge_softc *sc; 515 int addr; 516 u_int8_t *dest; 517 { 518 int i; 519 u_int32_t byte = 0; 520 521 /* 522 * Enable use of auto EEPROM access so we can avoid 523 * having to use the bitbang method. 524 */ 525 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 526 527 /* Reset the EEPROM, load the clock period. */ 528 CSR_WRITE_4(sc, BGE_EE_ADDR, 529 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 530 DELAY(20); 531 532 /* Issue the read EEPROM command. */ 533 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 534 535 /* Wait for completion */ 536 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 537 DELAY(10); 538 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 539 break; 540 } 541 542 if (i == BGE_TIMEOUT) { 543 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 544 return(0); 545 } 546 547 /* Get result. */ 548 byte = CSR_READ_4(sc, BGE_EE_DATA); 549 550 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 551 552 return(0); 553 } 554 555 /* 556 * Read a sequence of bytes from the EEPROM. 557 */ 558 static int 559 bge_read_eeprom(sc, dest, off, cnt) 560 struct bge_softc *sc; 561 caddr_t dest; 562 int off; 563 int cnt; 564 { 565 int err = 0, i; 566 u_int8_t byte = 0; 567 568 for (i = 0; i < cnt; i++) { 569 err = bge_eeprom_getbyte(sc, off + i, &byte); 570 if (err) 571 break; 572 *(dest + i) = byte; 573 } 574 575 return(err ? 1 : 0); 576 } 577 578 static int 579 bge_miibus_readreg(dev, phy, reg) 580 device_t dev; 581 int phy, reg; 582 { 583 struct bge_softc *sc; 584 u_int32_t val, autopoll; 585 int i; 586 587 sc = device_get_softc(dev); 588 589 /* 590 * Broadcom's own driver always assumes the internal 591 * PHY is at GMII address 1. On some chips, the PHY responds 592 * to accesses at all addresses, which could cause us to 593 * bogusly attach the PHY 32 times at probe type. Always 594 * restricting the lookup to address 1 is simpler than 595 * trying to figure out which chips revisions should be 596 * special-cased. 597 */ 598 if (phy != 1) 599 return(0); 600 601 /* Reading with autopolling on may trigger PCI errors */ 602 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 603 if (autopoll & BGE_MIMODE_AUTOPOLL) { 604 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 605 DELAY(40); 606 } 607 608 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 609 BGE_MIPHY(phy)|BGE_MIREG(reg)); 610 611 for (i = 0; i < BGE_TIMEOUT; i++) { 612 val = CSR_READ_4(sc, BGE_MI_COMM); 613 if (!(val & BGE_MICOMM_BUSY)) 614 break; 615 } 616 617 if (i == BGE_TIMEOUT) { 618 printf("bge%d: PHY read timed out\n", sc->bge_unit); 619 val = 0; 620 goto done; 621 } 622 623 val = CSR_READ_4(sc, BGE_MI_COMM); 624 625 done: 626 if (autopoll & BGE_MIMODE_AUTOPOLL) { 627 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 628 DELAY(40); 629 } 630 631 if (val & BGE_MICOMM_READFAIL) 632 return(0); 633 634 return(val & 0xFFFF); 635 } 636 637 static int 638 bge_miibus_writereg(dev, phy, reg, val) 639 device_t dev; 640 int phy, reg, val; 641 { 642 struct bge_softc *sc; 643 u_int32_t autopoll; 644 int i; 645 646 sc = device_get_softc(dev); 647 648 /* Reading with autopolling on may trigger PCI errors */ 649 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 650 if (autopoll & BGE_MIMODE_AUTOPOLL) { 651 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 652 DELAY(40); 653 } 654 655 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 656 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 657 658 for (i = 0; i < BGE_TIMEOUT; i++) { 659 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 660 break; 661 } 662 663 if (autopoll & BGE_MIMODE_AUTOPOLL) { 664 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 665 DELAY(40); 666 } 667 668 if (i == BGE_TIMEOUT) { 669 printf("bge%d: PHY read timed out\n", sc->bge_unit); 670 return(0); 671 } 672 673 return(0); 674 } 675 676 static void 677 bge_miibus_statchg(dev) 678 device_t dev; 679 { 680 struct bge_softc *sc; 681 struct mii_data *mii; 682 683 sc = device_get_softc(dev); 684 mii = device_get_softc(sc->bge_miibus); 685 686 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 687 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 688 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 689 } else { 690 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 691 } 692 693 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 694 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 695 } else { 696 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 697 } 698 699 return; 700 } 701 702 /* 703 * Handle events that have triggered interrupts. 704 */ 705 static void 706 bge_handle_events(sc) 707 struct bge_softc *sc; 708 { 709 710 return; 711 } 712 713 /* 714 * Memory management for jumbo frames. 715 */ 716 717 static int 718 bge_alloc_jumbo_mem(sc) 719 struct bge_softc *sc; 720 { 721 caddr_t ptr; 722 register int i, error; 723 struct bge_jpool_entry *entry; 724 725 /* Create tag for jumbo buffer block */ 726 727 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 728 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 729 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 730 &sc->bge_cdata.bge_jumbo_tag); 731 732 if (error) { 733 printf("bge%d: could not allocate jumbo dma tag\n", 734 sc->bge_unit); 735 return (ENOMEM); 736 } 737 738 /* Allocate DMA'able memory for jumbo buffer block */ 739 740 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 741 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 742 &sc->bge_cdata.bge_jumbo_map); 743 744 if (error) 745 return (ENOMEM); 746 747 SLIST_INIT(&sc->bge_jfree_listhead); 748 SLIST_INIT(&sc->bge_jinuse_listhead); 749 750 /* 751 * Now divide it up into 9K pieces and save the addresses 752 * in an array. 753 */ 754 ptr = sc->bge_ldata.bge_jumbo_buf; 755 for (i = 0; i < BGE_JSLOTS; i++) { 756 sc->bge_cdata.bge_jslots[i] = ptr; 757 ptr += BGE_JLEN; 758 entry = malloc(sizeof(struct bge_jpool_entry), 759 M_DEVBUF, M_NOWAIT); 760 if (entry == NULL) { 761 bge_free_jumbo_mem(sc); 762 sc->bge_ldata.bge_jumbo_buf = NULL; 763 printf("bge%d: no memory for jumbo " 764 "buffer queue!\n", sc->bge_unit); 765 return(ENOBUFS); 766 } 767 entry->slot = i; 768 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 769 entry, jpool_entries); 770 } 771 772 return(0); 773 } 774 775 static void 776 bge_free_jumbo_mem(sc) 777 struct bge_softc *sc; 778 { 779 int i; 780 struct bge_jpool_entry *entry; 781 782 for (i = 0; i < BGE_JSLOTS; i++) { 783 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 784 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 785 free(entry, M_DEVBUF); 786 } 787 788 /* Destroy jumbo buffer block */ 789 790 if (sc->bge_ldata.bge_rx_jumbo_ring) 791 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 792 sc->bge_ldata.bge_jumbo_buf, 793 sc->bge_cdata.bge_jumbo_map); 794 795 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 796 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 797 sc->bge_cdata.bge_jumbo_map); 798 799 if (sc->bge_cdata.bge_jumbo_tag) 800 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 801 802 return; 803 } 804 805 /* 806 * Allocate a jumbo buffer. 807 */ 808 static void * 809 bge_jalloc(sc) 810 struct bge_softc *sc; 811 { 812 struct bge_jpool_entry *entry; 813 814 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 815 816 if (entry == NULL) { 817 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 818 return(NULL); 819 } 820 821 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 822 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 823 return(sc->bge_cdata.bge_jslots[entry->slot]); 824 } 825 826 /* 827 * Release a jumbo buffer. 828 */ 829 static void 830 bge_jfree(buf, args) 831 void *buf; 832 void *args; 833 { 834 struct bge_jpool_entry *entry; 835 struct bge_softc *sc; 836 int i; 837 838 /* Extract the softc struct pointer. */ 839 sc = (struct bge_softc *)args; 840 841 if (sc == NULL) 842 panic("bge_jfree: can't find softc pointer!"); 843 844 /* calculate the slot this buffer belongs to */ 845 846 i = ((vm_offset_t)buf 847 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 848 849 if ((i < 0) || (i >= BGE_JSLOTS)) 850 panic("bge_jfree: asked to free buffer that we don't manage!"); 851 852 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 853 if (entry == NULL) 854 panic("bge_jfree: buffer not in use!"); 855 entry->slot = i; 856 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 857 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 858 859 return; 860 } 861 862 863 /* 864 * Intialize a standard receive ring descriptor. 865 */ 866 static int 867 bge_newbuf_std(sc, i, m) 868 struct bge_softc *sc; 869 int i; 870 struct mbuf *m; 871 { 872 struct mbuf *m_new = NULL; 873 struct bge_rx_bd *r; 874 struct bge_dmamap_arg ctx; 875 int error; 876 877 if (m == NULL) { 878 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 879 if (m_new == NULL) { 880 return(ENOBUFS); 881 } 882 883 MCLGET(m_new, M_DONTWAIT); 884 if (!(m_new->m_flags & M_EXT)) { 885 m_freem(m_new); 886 return(ENOBUFS); 887 } 888 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 889 } else { 890 m_new = m; 891 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 892 m_new->m_data = m_new->m_ext.ext_buf; 893 } 894 895 if (!sc->bge_rx_alignment_bug) 896 m_adj(m_new, ETHER_ALIGN); 897 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 898 r = &sc->bge_ldata.bge_rx_std_ring[i]; 899 ctx.bge_maxsegs = 1; 900 ctx.sc = sc; 901 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 902 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 903 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 904 if (error || ctx.bge_maxsegs == 0) { 905 if (m == NULL) 906 m_freem(m_new); 907 return(ENOMEM); 908 } 909 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 910 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 911 r->bge_flags = htole16(BGE_RXBDFLAG_END); 912 r->bge_len = htole16(m_new->m_len); 913 r->bge_idx = htole16(i); 914 915 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 916 sc->bge_cdata.bge_rx_std_dmamap[i], 917 BUS_DMASYNC_PREREAD); 918 919 return(0); 920 } 921 922 /* 923 * Initialize a jumbo receive ring descriptor. This allocates 924 * a jumbo buffer from the pool managed internally by the driver. 925 */ 926 static int 927 bge_newbuf_jumbo(sc, i, m) 928 struct bge_softc *sc; 929 int i; 930 struct mbuf *m; 931 { 932 struct mbuf *m_new = NULL; 933 struct bge_rx_bd *r; 934 struct bge_dmamap_arg ctx; 935 int error; 936 937 if (m == NULL) { 938 caddr_t *buf = NULL; 939 940 /* Allocate the mbuf. */ 941 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 942 if (m_new == NULL) { 943 return(ENOBUFS); 944 } 945 946 /* Allocate the jumbo buffer */ 947 buf = bge_jalloc(sc); 948 if (buf == NULL) { 949 m_freem(m_new); 950 printf("bge%d: jumbo allocation failed " 951 "-- packet dropped!\n", sc->bge_unit); 952 return(ENOBUFS); 953 } 954 955 /* Attach the buffer to the mbuf. */ 956 m_new->m_data = (void *) buf; 957 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 958 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 959 (struct bge_softc *)sc, 0, EXT_NET_DRV); 960 } else { 961 m_new = m; 962 m_new->m_data = m_new->m_ext.ext_buf; 963 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 964 } 965 966 if (!sc->bge_rx_alignment_bug) 967 m_adj(m_new, ETHER_ALIGN); 968 /* Set up the descriptor. */ 969 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 970 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 971 ctx.bge_maxsegs = 1; 972 ctx.sc = sc; 973 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 974 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 975 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 976 if (error || ctx.bge_maxsegs == 0) { 977 if (m == NULL) 978 m_freem(m_new); 979 return(ENOMEM); 980 } 981 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 982 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 983 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 984 r->bge_len = htole16(m_new->m_len); 985 r->bge_idx = htole16(i); 986 987 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 988 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 989 BUS_DMASYNC_PREREAD); 990 991 return(0); 992 } 993 994 /* 995 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 996 * that's 1MB or memory, which is a lot. For now, we fill only the first 997 * 256 ring entries and hope that our CPU is fast enough to keep up with 998 * the NIC. 999 */ 1000 static int 1001 bge_init_rx_ring_std(sc) 1002 struct bge_softc *sc; 1003 { 1004 int i; 1005 1006 for (i = 0; i < BGE_SSLOTS; i++) { 1007 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1008 return(ENOBUFS); 1009 }; 1010 1011 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1012 sc->bge_cdata.bge_rx_std_ring_map, 1013 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1014 1015 sc->bge_std = i - 1; 1016 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1017 1018 return(0); 1019 } 1020 1021 static void 1022 bge_free_rx_ring_std(sc) 1023 struct bge_softc *sc; 1024 { 1025 int i; 1026 1027 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1028 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1029 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1030 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1031 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1032 sc->bge_cdata.bge_rx_std_dmamap[i]); 1033 } 1034 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1035 sizeof(struct bge_rx_bd)); 1036 } 1037 1038 return; 1039 } 1040 1041 static int 1042 bge_init_rx_ring_jumbo(sc) 1043 struct bge_softc *sc; 1044 { 1045 int i; 1046 struct bge_rcb *rcb; 1047 1048 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1049 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1050 return(ENOBUFS); 1051 }; 1052 1053 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1054 sc->bge_cdata.bge_rx_jumbo_ring_map, 1055 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1056 1057 sc->bge_jumbo = i - 1; 1058 1059 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1060 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1061 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1062 1063 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1064 1065 return(0); 1066 } 1067 1068 static void 1069 bge_free_rx_ring_jumbo(sc) 1070 struct bge_softc *sc; 1071 { 1072 int i; 1073 1074 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1075 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1076 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1077 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1078 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1079 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1080 } 1081 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1082 sizeof(struct bge_rx_bd)); 1083 } 1084 1085 return; 1086 } 1087 1088 static void 1089 bge_free_tx_ring(sc) 1090 struct bge_softc *sc; 1091 { 1092 int i; 1093 1094 if (sc->bge_ldata.bge_tx_ring == NULL) 1095 return; 1096 1097 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1098 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1099 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1100 sc->bge_cdata.bge_tx_chain[i] = NULL; 1101 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1102 sc->bge_cdata.bge_tx_dmamap[i]); 1103 } 1104 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1105 sizeof(struct bge_tx_bd)); 1106 } 1107 1108 return; 1109 } 1110 1111 static int 1112 bge_init_tx_ring(sc) 1113 struct bge_softc *sc; 1114 { 1115 sc->bge_txcnt = 0; 1116 sc->bge_tx_saved_considx = 0; 1117 1118 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1119 /* 5700 b2 errata */ 1120 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1121 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1122 1123 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1124 /* 5700 b2 errata */ 1125 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1126 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1127 1128 return(0); 1129 } 1130 1131 #define BGE_POLY 0xEDB88320 1132 1133 static u_int32_t 1134 bge_crc(addr) 1135 caddr_t addr; 1136 { 1137 u_int32_t idx, bit, data, crc; 1138 1139 /* Compute CRC for the address value. */ 1140 crc = 0xFFFFFFFF; /* initial value */ 1141 1142 for (idx = 0; idx < 6; idx++) { 1143 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1144 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1145 } 1146 1147 return(crc & 0x7F); 1148 } 1149 1150 static void 1151 bge_setmulti(sc) 1152 struct bge_softc *sc; 1153 { 1154 struct ifnet *ifp; 1155 struct ifmultiaddr *ifma; 1156 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1157 int h, i; 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1162 for (i = 0; i < 4; i++) 1163 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1164 return; 1165 } 1166 1167 /* First, zot all the existing filters. */ 1168 for (i = 0; i < 4; i++) 1169 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1170 1171 /* Now program new ones. */ 1172 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1173 if (ifma->ifma_addr->sa_family != AF_LINK) 1174 continue; 1175 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1176 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1177 } 1178 1179 for (i = 0; i < 4; i++) 1180 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1181 1182 return; 1183 } 1184 1185 /* 1186 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1187 * self-test results. 1188 */ 1189 static int 1190 bge_chipinit(sc) 1191 struct bge_softc *sc; 1192 { 1193 int i; 1194 u_int32_t dma_rw_ctl; 1195 1196 /* Set endianness before we access any non-PCI registers. */ 1197 #if BYTE_ORDER == BIG_ENDIAN 1198 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1199 BGE_BIGENDIAN_INIT, 4); 1200 #else 1201 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1202 BGE_LITTLEENDIAN_INIT, 4); 1203 #endif 1204 1205 /* 1206 * Check the 'ROM failed' bit on the RX CPU to see if 1207 * self-tests passed. 1208 */ 1209 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1210 printf("bge%d: RX CPU self-diagnostics failed!\n", 1211 sc->bge_unit); 1212 return(ENODEV); 1213 } 1214 1215 /* Clear the MAC control register */ 1216 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1217 1218 /* 1219 * Clear the MAC statistics block in the NIC's 1220 * internal memory. 1221 */ 1222 for (i = BGE_STATS_BLOCK; 1223 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1224 BGE_MEMWIN_WRITE(sc, i, 0); 1225 1226 for (i = BGE_STATUS_BLOCK; 1227 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1228 BGE_MEMWIN_WRITE(sc, i, 0); 1229 1230 /* Set up the PCI DMA control register. */ 1231 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1232 BGE_PCISTATE_PCI_BUSMODE) { 1233 /* Conventional PCI bus */ 1234 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1235 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1236 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1237 (0x0F); 1238 } else { 1239 /* PCI-X bus */ 1240 /* 1241 * The 5704 uses a different encoding of read/write 1242 * watermarks. 1243 */ 1244 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1245 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1246 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1247 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1248 else 1249 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1250 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1251 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1252 (0x0F); 1253 1254 /* 1255 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1256 * for hardware bugs. 1257 */ 1258 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1259 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1260 u_int32_t tmp; 1261 1262 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1263 if (tmp == 0x6 || tmp == 0x7) 1264 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1265 } 1266 } 1267 1268 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1269 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1270 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1271 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1272 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1273 1274 /* 1275 * Set up general mode register. 1276 */ 1277 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1278 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1279 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1280 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1281 1282 /* 1283 * Disable memory write invalidate. Apparently it is not supported 1284 * properly by these devices. 1285 */ 1286 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1287 1288 #ifdef __brokenalpha__ 1289 /* 1290 * Must insure that we do not cross an 8K (bytes) boundary 1291 * for DMA reads. Our highest limit is 1K bytes. This is a 1292 * restriction on some ALPHA platforms with early revision 1293 * 21174 PCI chipsets, such as the AlphaPC 164lx 1294 */ 1295 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1296 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1297 #endif 1298 1299 /* Set the timer prescaler (always 66Mhz) */ 1300 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1301 1302 return(0); 1303 } 1304 1305 static int 1306 bge_blockinit(sc) 1307 struct bge_softc *sc; 1308 { 1309 struct bge_rcb *rcb; 1310 volatile struct bge_rcb *vrcb; 1311 int i; 1312 1313 /* 1314 * Initialize the memory window pointer register so that 1315 * we can access the first 32K of internal NIC RAM. This will 1316 * allow us to set up the TX send ring RCBs and the RX return 1317 * ring RCBs, plus other things which live in NIC memory. 1318 */ 1319 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1320 1321 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1322 1323 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1324 /* Configure mbuf memory pool */ 1325 if (sc->bge_extram) { 1326 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1327 BGE_EXT_SSRAM); 1328 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1329 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1330 else 1331 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1332 } else { 1333 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1334 BGE_BUFFPOOL_1); 1335 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1336 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1337 else 1338 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1339 } 1340 1341 /* Configure DMA resource pool */ 1342 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1343 BGE_DMA_DESCRIPTORS); 1344 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1345 } 1346 1347 /* Configure mbuf pool watermarks */ 1348 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1351 } else { 1352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1354 } 1355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1356 1357 /* Configure DMA resource watermarks */ 1358 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1359 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1360 1361 /* Enable buffer manager */ 1362 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1363 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1364 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1365 1366 /* Poll for buffer manager start indication */ 1367 for (i = 0; i < BGE_TIMEOUT; i++) { 1368 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1369 break; 1370 DELAY(10); 1371 } 1372 1373 if (i == BGE_TIMEOUT) { 1374 printf("bge%d: buffer manager failed to start\n", 1375 sc->bge_unit); 1376 return(ENXIO); 1377 } 1378 } 1379 1380 /* Enable flow-through queues */ 1381 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1382 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1383 1384 /* Wait until queue initialization is complete */ 1385 for (i = 0; i < BGE_TIMEOUT; i++) { 1386 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1387 break; 1388 DELAY(10); 1389 } 1390 1391 if (i == BGE_TIMEOUT) { 1392 printf("bge%d: flow-through queue init failed\n", 1393 sc->bge_unit); 1394 return(ENXIO); 1395 } 1396 1397 /* Initialize the standard RX ring control block */ 1398 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1399 rcb->bge_hostaddr.bge_addr_lo = 1400 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1401 rcb->bge_hostaddr.bge_addr_hi = 1402 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1403 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1404 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1405 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1406 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1407 else 1408 rcb->bge_maxlen_flags = 1409 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1410 if (sc->bge_extram) 1411 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1412 else 1413 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1414 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1415 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1416 1417 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1418 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1419 1420 /* 1421 * Initialize the jumbo RX ring control block 1422 * We set the 'ring disabled' bit in the flags 1423 * field until we're actually ready to start 1424 * using this ring (i.e. once we set the MTU 1425 * high enough to require it). 1426 */ 1427 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1428 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1429 1430 rcb->bge_hostaddr.bge_addr_lo = 1431 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1432 rcb->bge_hostaddr.bge_addr_hi = 1433 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1434 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1435 sc->bge_cdata.bge_rx_jumbo_ring_map, 1436 BUS_DMASYNC_PREREAD); 1437 rcb->bge_maxlen_flags = 1438 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1439 BGE_RCB_FLAG_RING_DISABLED); 1440 if (sc->bge_extram) 1441 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1442 else 1443 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1444 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1445 rcb->bge_hostaddr.bge_addr_hi); 1446 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1447 rcb->bge_hostaddr.bge_addr_lo); 1448 1449 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1450 rcb->bge_maxlen_flags); 1451 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1452 1453 /* Set up dummy disabled mini ring RCB */ 1454 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1455 rcb->bge_maxlen_flags = 1456 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1457 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1458 rcb->bge_maxlen_flags); 1459 } 1460 1461 /* 1462 * Set the BD ring replentish thresholds. The recommended 1463 * values are 1/8th the number of descriptors allocated to 1464 * each ring. 1465 */ 1466 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1467 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1468 1469 /* 1470 * Disable all unused send rings by setting the 'ring disabled' 1471 * bit in the flags field of all the TX send ring control blocks. 1472 * These are located in NIC memory. 1473 */ 1474 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1475 BGE_SEND_RING_RCB); 1476 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1477 vrcb->bge_maxlen_flags = 1478 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1479 vrcb->bge_nicaddr = 0; 1480 vrcb++; 1481 } 1482 1483 /* Configure TX RCB 0 (we use only the first ring) */ 1484 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1485 BGE_SEND_RING_RCB); 1486 vrcb->bge_hostaddr.bge_addr_lo = 1487 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1488 vrcb->bge_hostaddr.bge_addr_hi = 1489 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1490 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1491 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1492 vrcb->bge_maxlen_flags = 1493 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1494 1495 /* Disable all unused RX return rings */ 1496 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1497 BGE_RX_RETURN_RING_RCB); 1498 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1499 vrcb->bge_hostaddr.bge_addr_hi = 0; 1500 vrcb->bge_hostaddr.bge_addr_lo = 0; 1501 vrcb->bge_maxlen_flags = 1502 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1503 BGE_RCB_FLAG_RING_DISABLED); 1504 vrcb->bge_nicaddr = 0; 1505 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1506 (i * (sizeof(u_int64_t))), 0); 1507 vrcb++; 1508 } 1509 1510 /* Initialize RX ring indexes */ 1511 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1512 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1513 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1514 1515 /* 1516 * Set up RX return ring 0 1517 * Note that the NIC address for RX return rings is 0x00000000. 1518 * The return rings live entirely within the host, so the 1519 * nicaddr field in the RCB isn't used. 1520 */ 1521 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1522 BGE_RX_RETURN_RING_RCB); 1523 vrcb->bge_hostaddr.bge_addr_lo = 1524 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1525 vrcb->bge_hostaddr.bge_addr_hi = 1526 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1527 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1528 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1529 vrcb->bge_nicaddr = 0x00000000; 1530 vrcb->bge_maxlen_flags = 1531 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1532 1533 /* Set random backoff seed for TX */ 1534 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1535 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1536 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1537 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1538 BGE_TX_BACKOFF_SEED_MASK); 1539 1540 /* Set inter-packet gap */ 1541 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1542 1543 /* 1544 * Specify which ring to use for packets that don't match 1545 * any RX rules. 1546 */ 1547 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1548 1549 /* 1550 * Configure number of RX lists. One interrupt distribution 1551 * list, sixteen active lists, one bad frames class. 1552 */ 1553 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1554 1555 /* Inialize RX list placement stats mask. */ 1556 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1557 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1558 1559 /* Disable host coalescing until we get it set up */ 1560 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1561 1562 /* Poll to make sure it's shut down. */ 1563 for (i = 0; i < BGE_TIMEOUT; i++) { 1564 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1565 break; 1566 DELAY(10); 1567 } 1568 1569 if (i == BGE_TIMEOUT) { 1570 printf("bge%d: host coalescing engine failed to idle\n", 1571 sc->bge_unit); 1572 return(ENXIO); 1573 } 1574 1575 /* Set up host coalescing defaults */ 1576 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1577 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1578 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1579 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1580 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1581 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1582 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1583 } 1584 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1585 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1586 1587 /* Set up address of statistics block */ 1588 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1589 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1590 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1591 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1592 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1593 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1594 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1595 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1596 } 1597 1598 /* Set up address of status block */ 1599 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1600 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1601 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1602 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1603 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1604 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1605 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1606 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1607 1608 /* Turn on host coalescing state machine */ 1609 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1610 1611 /* Turn on RX BD completion state machine and enable attentions */ 1612 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1613 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1614 1615 /* Turn on RX list placement state machine */ 1616 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1617 1618 /* Turn on RX list selector state machine. */ 1619 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1620 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1621 1622 /* Turn on DMA, clear stats */ 1623 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1624 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1625 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1626 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1627 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1628 1629 /* Set misc. local control, enable interrupts on attentions */ 1630 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1631 1632 #ifdef notdef 1633 /* Assert GPIO pins for PHY reset */ 1634 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1635 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1636 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1637 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1638 #endif 1639 1640 /* Turn on DMA completion state machine */ 1641 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1642 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1643 1644 /* Turn on write DMA state machine */ 1645 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1646 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1647 1648 /* Turn on read DMA state machine */ 1649 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1650 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1651 1652 /* Turn on RX data completion state machine */ 1653 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1654 1655 /* Turn on RX BD initiator state machine */ 1656 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1657 1658 /* Turn on RX data and RX BD initiator state machine */ 1659 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1660 1661 /* Turn on Mbuf cluster free state machine */ 1662 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1663 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1664 1665 /* Turn on send BD completion state machine */ 1666 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1667 1668 /* Turn on send data completion state machine */ 1669 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1670 1671 /* Turn on send data initiator state machine */ 1672 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1673 1674 /* Turn on send BD initiator state machine */ 1675 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1676 1677 /* Turn on send BD selector state machine */ 1678 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1679 1680 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1681 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1682 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1683 1684 /* ack/clear link change events */ 1685 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1686 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1687 BGE_MACSTAT_LINK_CHANGED); 1688 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1689 1690 /* Enable PHY auto polling (for MII/GMII only) */ 1691 if (sc->bge_tbi) { 1692 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1693 } else { 1694 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1695 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1696 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1697 BGE_EVTENB_MI_INTERRUPT); 1698 } 1699 1700 /* Enable link state change attentions. */ 1701 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1702 1703 return(0); 1704 } 1705 1706 /* 1707 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1708 * against our list and return its name if we find a match. Note 1709 * that since the Broadcom controller contains VPD support, we 1710 * can get the device name string from the controller itself instead 1711 * of the compiled-in string. This is a little slow, but it guarantees 1712 * we'll always announce the right product name. 1713 */ 1714 static int 1715 bge_probe(dev) 1716 device_t dev; 1717 { 1718 struct bge_type *t; 1719 struct bge_softc *sc; 1720 char *descbuf; 1721 1722 t = bge_devs; 1723 1724 sc = device_get_softc(dev); 1725 bzero(sc, sizeof(struct bge_softc)); 1726 sc->bge_unit = device_get_unit(dev); 1727 sc->bge_dev = dev; 1728 1729 while(t->bge_name != NULL) { 1730 if ((pci_get_vendor(dev) == t->bge_vid) && 1731 (pci_get_device(dev) == t->bge_did)) { 1732 #ifdef notdef 1733 bge_vpd_read(sc); 1734 device_set_desc(dev, sc->bge_vpd_prodname); 1735 #endif 1736 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1737 if (descbuf == NULL) 1738 return(ENOMEM); 1739 snprintf(descbuf, BGE_DEVDESC_MAX, 1740 "%s, ASIC rev. %#04x", t->bge_name, 1741 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1742 device_set_desc_copy(dev, descbuf); 1743 if (pci_get_subvendor(dev) == DELL_VENDORID) 1744 sc->bge_no_3_led = 1; 1745 free(descbuf, M_TEMP); 1746 return(0); 1747 } 1748 t++; 1749 } 1750 1751 return(ENXIO); 1752 } 1753 1754 static void 1755 bge_dma_free(sc) 1756 struct bge_softc *sc; 1757 { 1758 int i; 1759 1760 1761 /* Destroy DMA maps for RX buffers */ 1762 1763 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1764 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1765 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1766 sc->bge_cdata.bge_rx_std_dmamap[i]); 1767 } 1768 1769 /* Destroy DMA maps for jumbo RX buffers */ 1770 1771 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1772 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1773 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1774 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1775 } 1776 1777 /* Destroy DMA maps for TX buffers */ 1778 1779 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1780 if (sc->bge_cdata.bge_tx_dmamap[i]) 1781 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1782 sc->bge_cdata.bge_tx_dmamap[i]); 1783 } 1784 1785 if (sc->bge_cdata.bge_mtag) 1786 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1787 1788 1789 /* Destroy standard RX ring */ 1790 1791 if (sc->bge_ldata.bge_rx_std_ring) 1792 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1793 sc->bge_ldata.bge_rx_std_ring, 1794 sc->bge_cdata.bge_rx_std_ring_map); 1795 1796 if (sc->bge_cdata.bge_rx_std_ring_map) { 1797 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1798 sc->bge_cdata.bge_rx_std_ring_map); 1799 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1800 sc->bge_cdata.bge_rx_std_ring_map); 1801 } 1802 1803 if (sc->bge_cdata.bge_rx_std_ring_tag) 1804 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1805 1806 /* Destroy jumbo RX ring */ 1807 1808 if (sc->bge_ldata.bge_rx_jumbo_ring) 1809 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1810 sc->bge_ldata.bge_rx_jumbo_ring, 1811 sc->bge_cdata.bge_rx_jumbo_ring_map); 1812 1813 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1814 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1815 sc->bge_cdata.bge_rx_jumbo_ring_map); 1816 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1817 sc->bge_cdata.bge_rx_jumbo_ring_map); 1818 } 1819 1820 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1821 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1822 1823 /* Destroy RX return ring */ 1824 1825 if (sc->bge_ldata.bge_rx_return_ring) 1826 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1827 sc->bge_ldata.bge_rx_return_ring, 1828 sc->bge_cdata.bge_rx_return_ring_map); 1829 1830 if (sc->bge_cdata.bge_rx_return_ring_map) { 1831 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1832 sc->bge_cdata.bge_rx_return_ring_map); 1833 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1834 sc->bge_cdata.bge_rx_return_ring_map); 1835 } 1836 1837 if (sc->bge_cdata.bge_rx_return_ring_tag) 1838 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1839 1840 /* Destroy TX ring */ 1841 1842 if (sc->bge_ldata.bge_tx_ring) 1843 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1844 sc->bge_ldata.bge_tx_ring, 1845 sc->bge_cdata.bge_tx_ring_map); 1846 1847 if (sc->bge_cdata.bge_tx_ring_map) { 1848 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1849 sc->bge_cdata.bge_tx_ring_map); 1850 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1851 sc->bge_cdata.bge_tx_ring_map); 1852 } 1853 1854 if (sc->bge_cdata.bge_tx_ring_tag) 1855 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1856 1857 /* Destroy status block */ 1858 1859 if (sc->bge_ldata.bge_status_block) 1860 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1861 sc->bge_ldata.bge_status_block, 1862 sc->bge_cdata.bge_status_map); 1863 1864 if (sc->bge_cdata.bge_status_map) { 1865 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1866 sc->bge_cdata.bge_status_map); 1867 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1868 sc->bge_cdata.bge_status_map); 1869 } 1870 1871 if (sc->bge_cdata.bge_status_tag) 1872 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1873 1874 /* Destroy statistics block */ 1875 1876 if (sc->bge_ldata.bge_stats) 1877 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1878 sc->bge_ldata.bge_stats, 1879 sc->bge_cdata.bge_stats_map); 1880 1881 if (sc->bge_cdata.bge_stats_map) { 1882 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1883 sc->bge_cdata.bge_stats_map); 1884 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1885 sc->bge_cdata.bge_stats_map); 1886 } 1887 1888 if (sc->bge_cdata.bge_stats_tag) 1889 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1890 1891 /* Destroy the parent tag */ 1892 1893 if (sc->bge_cdata.bge_parent_tag) 1894 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1895 1896 return; 1897 } 1898 1899 static int 1900 bge_dma_alloc(dev) 1901 device_t dev; 1902 { 1903 struct bge_softc *sc; 1904 int nseg, i, error; 1905 struct bge_dmamap_arg ctx; 1906 1907 sc = device_get_softc(dev); 1908 1909 /* 1910 * Allocate the parent bus DMA tag appropriate for PCI. 1911 */ 1912 #define BGE_NSEG_NEW 32 1913 error = bus_dma_tag_create(NULL, /* parent */ 1914 PAGE_SIZE, 0, /* alignment, boundary */ 1915 BUS_SPACE_MAXADDR, /* lowaddr */ 1916 BUS_SPACE_MAXADDR_32BIT,/* highaddr */ 1917 NULL, NULL, /* filter, filterarg */ 1918 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1919 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1920 BUS_DMA_ALLOCNOW, /* flags */ 1921 NULL, NULL, /* lockfunc, lockarg */ 1922 &sc->bge_cdata.bge_parent_tag); 1923 1924 /* 1925 * Create tag for RX mbufs. 1926 */ 1927 nseg = 32; 1928 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, ETHER_ALIGN, 1929 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1930 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1931 &sc->bge_cdata.bge_mtag); 1932 1933 if (error) { 1934 device_printf(dev, "could not allocate dma tag\n"); 1935 return (ENOMEM); 1936 } 1937 1938 /* Create DMA maps for RX buffers */ 1939 1940 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1941 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1942 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1943 if (error) { 1944 device_printf(dev, "can't create DMA map for RX\n"); 1945 return(ENOMEM); 1946 } 1947 } 1948 1949 /* Create DMA maps for TX buffers */ 1950 1951 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1952 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1953 &sc->bge_cdata.bge_tx_dmamap[i]); 1954 if (error) { 1955 device_printf(dev, "can't create DMA map for RX\n"); 1956 return(ENOMEM); 1957 } 1958 } 1959 1960 /* Create tag for standard RX ring */ 1961 1962 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1963 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1964 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1965 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1966 1967 if (error) { 1968 device_printf(dev, "could not allocate dma tag\n"); 1969 return (ENOMEM); 1970 } 1971 1972 /* Allocate DMA'able memory for standard RX ring */ 1973 1974 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1975 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1976 &sc->bge_cdata.bge_rx_std_ring_map); 1977 if (error) 1978 return (ENOMEM); 1979 1980 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1981 1982 /* Load the address of the standard RX ring */ 1983 1984 ctx.bge_maxsegs = 1; 1985 ctx.sc = sc; 1986 1987 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1988 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1989 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1990 1991 if (error) 1992 return (ENOMEM); 1993 1994 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1995 1996 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1997 1998 /* 1999 * Create tag for jumbo mbufs. 2000 * This is really a bit of a kludge. We allocate a special 2001 * jumbo buffer pool which (thanks to the way our DMA 2002 * memory allocation works) will consist of contiguous 2003 * pages. This means that even though a jumbo buffer might 2004 * be larger than a page size, we don't really need to 2005 * map it into more than one DMA segment. However, the 2006 * default mbuf tag will result in multi-segment mappings, 2007 * so we have to create a special jumbo mbuf tag that 2008 * lets us get away with mapping the jumbo buffers as 2009 * a single segment. I think eventually the driver should 2010 * be changed so that it uses ordinary mbufs and cluster 2011 * buffers, i.e. jumbo frames can span multiple DMA 2012 * descriptors. But that's a project for another day. 2013 */ 2014 2015 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2016 ETHER_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2017 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2018 &sc->bge_cdata.bge_mtag_jumbo); 2019 2020 if (error) { 2021 device_printf(dev, "could not allocate dma tag\n"); 2022 return (ENOMEM); 2023 } 2024 2025 /* Create tag for jumbo RX ring */ 2026 2027 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2028 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2029 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2030 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2031 2032 if (error) { 2033 device_printf(dev, "could not allocate dma tag\n"); 2034 return (ENOMEM); 2035 } 2036 2037 /* Allocate DMA'able memory for jumbo RX ring */ 2038 2039 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2040 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2041 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2042 if (error) 2043 return (ENOMEM); 2044 2045 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2046 BGE_JUMBO_RX_RING_SZ); 2047 2048 /* Load the address of the jumbo RX ring */ 2049 2050 ctx.bge_maxsegs = 1; 2051 ctx.sc = sc; 2052 2053 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2054 sc->bge_cdata.bge_rx_jumbo_ring_map, 2055 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2056 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2057 2058 if (error) 2059 return (ENOMEM); 2060 2061 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2062 2063 /* Create DMA maps for jumbo RX buffers */ 2064 2065 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2066 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2067 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2068 if (error) { 2069 device_printf(dev, 2070 "can't create DMA map for RX\n"); 2071 return(ENOMEM); 2072 } 2073 } 2074 2075 } 2076 2077 /* Create tag for RX return ring */ 2078 2079 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2080 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2081 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2082 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2083 2084 if (error) { 2085 device_printf(dev, "could not allocate dma tag\n"); 2086 return (ENOMEM); 2087 } 2088 2089 /* Allocate DMA'able memory for RX return ring */ 2090 2091 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2092 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2093 &sc->bge_cdata.bge_rx_return_ring_map); 2094 if (error) 2095 return (ENOMEM); 2096 2097 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2098 BGE_RX_RTN_RING_SZ(sc)); 2099 2100 /* Load the address of the RX return ring */ 2101 2102 ctx.bge_maxsegs = 1; 2103 ctx.sc = sc; 2104 2105 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2106 sc->bge_cdata.bge_rx_return_ring_map, 2107 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2108 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2109 2110 if (error) 2111 return (ENOMEM); 2112 2113 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2114 2115 /* Create tag for TX ring */ 2116 2117 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2118 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2119 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2120 &sc->bge_cdata.bge_tx_ring_tag); 2121 2122 if (error) { 2123 device_printf(dev, "could not allocate dma tag\n"); 2124 return (ENOMEM); 2125 } 2126 2127 /* Allocate DMA'able memory for TX ring */ 2128 2129 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2130 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2131 &sc->bge_cdata.bge_tx_ring_map); 2132 if (error) 2133 return (ENOMEM); 2134 2135 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2136 2137 /* Load the address of the TX ring */ 2138 2139 ctx.bge_maxsegs = 1; 2140 ctx.sc = sc; 2141 2142 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2143 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2144 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2145 2146 if (error) 2147 return (ENOMEM); 2148 2149 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2150 2151 /* Create tag for status block */ 2152 2153 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2154 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2155 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2156 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2157 2158 if (error) { 2159 device_printf(dev, "could not allocate dma tag\n"); 2160 return (ENOMEM); 2161 } 2162 2163 /* Allocate DMA'able memory for status block */ 2164 2165 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2166 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2167 &sc->bge_cdata.bge_status_map); 2168 if (error) 2169 return (ENOMEM); 2170 2171 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2172 2173 /* Load the address of the status block */ 2174 2175 ctx.sc = sc; 2176 ctx.bge_maxsegs = 1; 2177 2178 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2179 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2180 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2181 2182 if (error) 2183 return (ENOMEM); 2184 2185 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2186 2187 /* Create tag for statistics block */ 2188 2189 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2190 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2191 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2192 &sc->bge_cdata.bge_stats_tag); 2193 2194 if (error) { 2195 device_printf(dev, "could not allocate dma tag\n"); 2196 return (ENOMEM); 2197 } 2198 2199 /* Allocate DMA'able memory for statistics block */ 2200 2201 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2202 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2203 &sc->bge_cdata.bge_stats_map); 2204 if (error) 2205 return (ENOMEM); 2206 2207 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2208 2209 /* Load the address of the statstics block */ 2210 2211 ctx.sc = sc; 2212 ctx.bge_maxsegs = 1; 2213 2214 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2215 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2216 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2217 2218 if (error) 2219 return (ENOMEM); 2220 2221 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2222 2223 return(0); 2224 } 2225 2226 static int 2227 bge_attach(dev) 2228 device_t dev; 2229 { 2230 int s; 2231 struct ifnet *ifp; 2232 struct bge_softc *sc; 2233 u_int32_t hwcfg = 0; 2234 u_int32_t mac_addr = 0; 2235 int unit, error = 0, rid; 2236 2237 s = splimp(); 2238 2239 sc = device_get_softc(dev); 2240 unit = device_get_unit(dev); 2241 sc->bge_dev = dev; 2242 sc->bge_unit = unit; 2243 2244 /* 2245 * Map control/status registers. 2246 */ 2247 pci_enable_busmaster(dev); 2248 2249 rid = BGE_PCI_BAR0; 2250 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2251 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2252 2253 if (sc->bge_res == NULL) { 2254 printf ("bge%d: couldn't map memory\n", unit); 2255 error = ENXIO; 2256 goto fail; 2257 } 2258 2259 sc->bge_btag = rman_get_bustag(sc->bge_res); 2260 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2261 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2262 2263 /* Allocate interrupt */ 2264 rid = 0; 2265 2266 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2267 RF_SHAREABLE | RF_ACTIVE); 2268 2269 if (sc->bge_irq == NULL) { 2270 printf("bge%d: couldn't map interrupt\n", unit); 2271 error = ENXIO; 2272 goto fail; 2273 } 2274 2275 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 2276 bge_intr, sc, &sc->bge_intrhand); 2277 2278 if (error) { 2279 bge_release_resources(sc); 2280 printf("bge%d: couldn't set up irq\n", unit); 2281 goto fail; 2282 } 2283 2284 sc->bge_unit = unit; 2285 2286 /* Try to reset the chip. */ 2287 bge_reset(sc); 2288 2289 if (bge_chipinit(sc)) { 2290 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2291 bge_release_resources(sc); 2292 error = ENXIO; 2293 goto fail; 2294 } 2295 2296 /* 2297 * Get station address from the EEPROM. 2298 */ 2299 mac_addr = bge_readmem_ind(sc, 0x0c14); 2300 if ((mac_addr >> 16) == 0x484b) { 2301 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2302 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2303 mac_addr = bge_readmem_ind(sc, 0x0c18); 2304 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2305 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2306 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2307 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2308 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2309 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2310 printf("bge%d: failed to read station address\n", unit); 2311 bge_release_resources(sc); 2312 error = ENXIO; 2313 goto fail; 2314 } 2315 2316 /* 2317 * A Broadcom chip was detected. Inform the world. 2318 */ 2319 printf("bge%d: Ethernet address: %6D\n", unit, 2320 sc->arpcom.ac_enaddr, ":"); 2321 2322 /* Save ASIC rev. */ 2323 2324 sc->bge_chipid = 2325 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2326 BGE_PCIMISCCTL_ASICREV; 2327 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2328 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2329 2330 /* 5705 limits RX return ring to 512 entries. */ 2331 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2332 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2333 else 2334 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2335 2336 if (bge_dma_alloc(dev)) { 2337 printf ("bge%d: failed to allocate DMA resources\n", 2338 sc->bge_unit); 2339 bge_release_resources(sc); 2340 error = ENXIO; 2341 goto fail; 2342 } 2343 2344 /* 2345 * Try to allocate memory for jumbo buffers. 2346 * The 5705 does not appear to support jumbo frames. 2347 */ 2348 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2349 if (bge_alloc_jumbo_mem(sc)) { 2350 printf("bge%d: jumbo buffer allocation " 2351 "failed\n", sc->bge_unit); 2352 bge_release_resources(sc); 2353 error = ENXIO; 2354 goto fail; 2355 } 2356 } 2357 2358 /* Set default tuneable values. */ 2359 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2360 sc->bge_rx_coal_ticks = 150; 2361 sc->bge_tx_coal_ticks = 150; 2362 sc->bge_rx_max_coal_bds = 64; 2363 sc->bge_tx_max_coal_bds = 128; 2364 2365 /* Set up ifnet structure */ 2366 ifp = &sc->arpcom.ac_if; 2367 ifp->if_softc = sc; 2368 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2370 ifp->if_ioctl = bge_ioctl; 2371 ifp->if_output = ether_output; 2372 ifp->if_start = bge_start; 2373 ifp->if_watchdog = bge_watchdog; 2374 ifp->if_init = bge_init; 2375 ifp->if_mtu = ETHERMTU; 2376 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 2377 ifp->if_hwassist = BGE_CSUM_FEATURES; 2378 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2379 IFCAP_VLAN_MTU; 2380 ifp->if_capenable = ifp->if_capabilities; 2381 2382 /* 2383 * Figure out what sort of media we have by checking the 2384 * hardware config word in the first 32k of NIC internal memory, 2385 * or fall back to examining the EEPROM if necessary. 2386 * Note: on some BCM5700 cards, this value appears to be unset. 2387 * If that's the case, we have to rely on identifying the NIC 2388 * by its PCI subsystem ID, as we do below for the SysKonnect 2389 * SK-9D41. 2390 */ 2391 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2392 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2393 else { 2394 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2395 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2396 hwcfg = ntohl(hwcfg); 2397 } 2398 2399 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2400 sc->bge_tbi = 1; 2401 2402 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2403 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2404 sc->bge_tbi = 1; 2405 2406 if (sc->bge_tbi) { 2407 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2408 bge_ifmedia_upd, bge_ifmedia_sts); 2409 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2410 ifmedia_add(&sc->bge_ifmedia, 2411 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2412 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2413 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2414 } else { 2415 /* 2416 * Do transceiver setup. 2417 */ 2418 if (mii_phy_probe(dev, &sc->bge_miibus, 2419 bge_ifmedia_upd, bge_ifmedia_sts)) { 2420 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2421 bge_release_resources(sc); 2422 bge_free_jumbo_mem(sc); 2423 error = ENXIO; 2424 goto fail; 2425 } 2426 } 2427 2428 /* 2429 * When using the BCM5701 in PCI-X mode, data corruption has 2430 * been observed in the first few bytes of some received packets. 2431 * Aligning the packet buffer in memory eliminates the corruption. 2432 * Unfortunately, this misaligns the packet payloads. On platforms 2433 * which do not support unaligned accesses, we will realign the 2434 * payloads by copying the received packets. 2435 */ 2436 switch (sc->bge_chipid) { 2437 case BGE_CHIPID_BCM5701_A0: 2438 case BGE_CHIPID_BCM5701_B0: 2439 case BGE_CHIPID_BCM5701_B2: 2440 case BGE_CHIPID_BCM5701_B5: 2441 /* If in PCI-X mode, work around the alignment bug. */ 2442 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2443 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2444 BGE_PCISTATE_PCI_BUSSPEED) 2445 sc->bge_rx_alignment_bug = 1; 2446 break; 2447 } 2448 2449 /* 2450 * Call MI attach routine. 2451 */ 2452 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2453 callout_handle_init(&sc->bge_stat_ch); 2454 2455 fail: 2456 splx(s); 2457 2458 return(error); 2459 } 2460 2461 static int 2462 bge_detach(dev) 2463 device_t dev; 2464 { 2465 struct bge_softc *sc; 2466 struct ifnet *ifp; 2467 int s; 2468 2469 s = splimp(); 2470 2471 sc = device_get_softc(dev); 2472 ifp = &sc->arpcom.ac_if; 2473 2474 ether_ifdetach(ifp); 2475 bge_stop(sc); 2476 bge_reset(sc); 2477 2478 if (sc->bge_tbi) { 2479 ifmedia_removeall(&sc->bge_ifmedia); 2480 } else { 2481 bus_generic_detach(dev); 2482 device_delete_child(dev, sc->bge_miibus); 2483 } 2484 2485 bge_release_resources(sc); 2486 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2487 bge_free_jumbo_mem(sc); 2488 2489 splx(s); 2490 2491 return(0); 2492 } 2493 2494 static void 2495 bge_release_resources(sc) 2496 struct bge_softc *sc; 2497 { 2498 device_t dev; 2499 2500 dev = sc->bge_dev; 2501 2502 if (sc->bge_vpd_prodname != NULL) 2503 free(sc->bge_vpd_prodname, M_DEVBUF); 2504 2505 if (sc->bge_vpd_readonly != NULL) 2506 free(sc->bge_vpd_readonly, M_DEVBUF); 2507 2508 if (sc->bge_intrhand != NULL) 2509 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2510 2511 if (sc->bge_irq != NULL) 2512 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2513 2514 if (sc->bge_res != NULL) 2515 bus_release_resource(dev, SYS_RES_MEMORY, 2516 BGE_PCI_BAR0, sc->bge_res); 2517 2518 bge_dma_free(sc); 2519 2520 return; 2521 } 2522 2523 static void 2524 bge_reset(sc) 2525 struct bge_softc *sc; 2526 { 2527 device_t dev; 2528 u_int32_t cachesize, command, pcistate; 2529 int i, val = 0; 2530 2531 dev = sc->bge_dev; 2532 2533 /* Save some important PCI state. */ 2534 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2535 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2536 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2537 2538 pci_write_config(dev, BGE_PCI_MISC_CTL, 2539 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2540 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2541 2542 /* Issue global reset */ 2543 bge_writereg_ind(sc, BGE_MISC_CFG, 2544 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2545 2546 DELAY(1000); 2547 2548 /* Reset some of the PCI state that got zapped by reset */ 2549 pci_write_config(dev, BGE_PCI_MISC_CTL, 2550 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2551 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2552 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2553 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2554 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2555 2556 /* 2557 * Prevent PXE restart: write a magic number to the 2558 * general communications memory at 0xB50. 2559 */ 2560 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2561 /* 2562 * Poll the value location we just wrote until 2563 * we see the 1's complement of the magic number. 2564 * This indicates that the firmware initialization 2565 * is complete. 2566 */ 2567 for (i = 0; i < BGE_TIMEOUT; i++) { 2568 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2569 if (val == ~BGE_MAGIC_NUMBER) 2570 break; 2571 DELAY(10); 2572 } 2573 2574 if (i == BGE_TIMEOUT) { 2575 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2576 return; 2577 } 2578 2579 /* 2580 * XXX Wait for the value of the PCISTATE register to 2581 * return to its original pre-reset state. This is a 2582 * fairly good indicator of reset completion. If we don't 2583 * wait for the reset to fully complete, trying to read 2584 * from the device's non-PCI registers may yield garbage 2585 * results. 2586 */ 2587 for (i = 0; i < BGE_TIMEOUT; i++) { 2588 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2589 break; 2590 DELAY(10); 2591 } 2592 2593 /* Enable memory arbiter. */ 2594 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2595 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2596 2597 /* Fix up byte swapping */ 2598 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2599 BGE_MODECTL_BYTESWAP_DATA); 2600 2601 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2602 2603 DELAY(10000); 2604 2605 return; 2606 } 2607 2608 /* 2609 * Frame reception handling. This is called if there's a frame 2610 * on the receive return list. 2611 * 2612 * Note: we have to be able to handle two possibilities here: 2613 * 1) the frame is from the jumbo recieve ring 2614 * 2) the frame is from the standard receive ring 2615 */ 2616 2617 static void 2618 bge_rxeof(sc) 2619 struct bge_softc *sc; 2620 { 2621 struct ifnet *ifp; 2622 int stdcnt = 0, jumbocnt = 0; 2623 2624 ifp = &sc->arpcom.ac_if; 2625 2626 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2627 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2628 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2629 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2630 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2631 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2632 sc->bge_cdata.bge_rx_jumbo_ring_map, 2633 BUS_DMASYNC_POSTREAD); 2634 } 2635 2636 while(sc->bge_rx_saved_considx != 2637 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2638 struct bge_rx_bd *cur_rx; 2639 u_int32_t rxidx; 2640 struct ether_header *eh; 2641 struct mbuf *m = NULL; 2642 u_int16_t vlan_tag = 0; 2643 int have_tag = 0; 2644 2645 cur_rx = 2646 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2647 2648 rxidx = cur_rx->bge_idx; 2649 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2650 2651 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2652 have_tag = 1; 2653 vlan_tag = cur_rx->bge_vlan_tag; 2654 } 2655 2656 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2657 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2658 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2659 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2660 BUS_DMASYNC_POSTREAD); 2661 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2662 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2663 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2664 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2665 jumbocnt++; 2666 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2667 ifp->if_ierrors++; 2668 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2669 continue; 2670 } 2671 if (bge_newbuf_jumbo(sc, 2672 sc->bge_jumbo, NULL) == ENOBUFS) { 2673 ifp->if_ierrors++; 2674 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2675 continue; 2676 } 2677 } else { 2678 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2679 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2680 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2681 BUS_DMASYNC_POSTREAD); 2682 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2683 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2684 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2685 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2686 stdcnt++; 2687 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2688 ifp->if_ierrors++; 2689 bge_newbuf_std(sc, sc->bge_std, m); 2690 continue; 2691 } 2692 if (bge_newbuf_std(sc, sc->bge_std, 2693 NULL) == ENOBUFS) { 2694 ifp->if_ierrors++; 2695 bge_newbuf_std(sc, sc->bge_std, m); 2696 continue; 2697 } 2698 } 2699 2700 ifp->if_ipackets++; 2701 #ifndef __i386__ 2702 /* 2703 * The i386 allows unaligned accesses, but for other 2704 * platforms we must make sure the payload is aligned. 2705 */ 2706 if (sc->bge_rx_alignment_bug) { 2707 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2708 cur_rx->bge_len); 2709 m->m_data += ETHER_ALIGN; 2710 } 2711 #endif 2712 eh = mtod(m, struct ether_header *); 2713 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2714 m->m_pkthdr.rcvif = ifp; 2715 2716 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2717 if (ifp->if_hwassist) { 2718 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2719 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2720 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2721 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2722 m->m_pkthdr.csum_data = 2723 cur_rx->bge_tcp_udp_csum; 2724 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2725 } 2726 } 2727 #endif 2728 2729 /* 2730 * If we received a packet with a vlan tag, 2731 * attach that information to the packet. 2732 */ 2733 if (have_tag) 2734 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2735 2736 (*ifp->if_input)(ifp, m); 2737 } 2738 2739 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2740 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2741 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2742 sc->bge_cdata.bge_rx_std_ring_map, 2743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2744 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2745 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2746 sc->bge_cdata.bge_rx_jumbo_ring_map, 2747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2748 } 2749 2750 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2751 if (stdcnt) 2752 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2753 if (jumbocnt) 2754 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2755 2756 return; 2757 } 2758 2759 static void 2760 bge_txeof(sc) 2761 struct bge_softc *sc; 2762 { 2763 struct bge_tx_bd *cur_tx = NULL; 2764 struct ifnet *ifp; 2765 2766 ifp = &sc->arpcom.ac_if; 2767 2768 /* 2769 * Go through our tx ring and free mbufs for those 2770 * frames that have been sent. 2771 */ 2772 while (sc->bge_tx_saved_considx != 2773 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2774 u_int32_t idx = 0; 2775 2776 idx = sc->bge_tx_saved_considx; 2777 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2778 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2779 ifp->if_opackets++; 2780 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2781 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2782 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2783 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2784 sc->bge_cdata.bge_tx_dmamap[idx]); 2785 } 2786 sc->bge_txcnt--; 2787 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2788 ifp->if_timer = 0; 2789 } 2790 2791 if (cur_tx != NULL) 2792 ifp->if_flags &= ~IFF_OACTIVE; 2793 2794 return; 2795 } 2796 2797 static void 2798 bge_intr(xsc) 2799 void *xsc; 2800 { 2801 struct bge_softc *sc; 2802 struct ifnet *ifp; 2803 u_int32_t statusword; 2804 u_int32_t status; 2805 2806 sc = xsc; 2807 ifp = &sc->arpcom.ac_if; 2808 2809 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2810 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2811 2812 statusword = 2813 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2814 2815 #ifdef notdef 2816 /* Avoid this for now -- checking this register is expensive. */ 2817 /* Make sure this is really our interrupt. */ 2818 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2819 return; 2820 #endif 2821 /* Ack interrupt and stop others from occuring. */ 2822 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2823 2824 /* 2825 * Process link state changes. 2826 * Grrr. The link status word in the status block does 2827 * not work correctly on the BCM5700 rev AX and BX chips, 2828 * according to all avaibable information. Hence, we have 2829 * to enable MII interrupts in order to properly obtain 2830 * async link changes. Unfortunately, this also means that 2831 * we have to read the MAC status register to detect link 2832 * changes, thereby adding an additional register access to 2833 * the interrupt handler. 2834 */ 2835 2836 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2837 2838 status = CSR_READ_4(sc, BGE_MAC_STS); 2839 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2840 sc->bge_link = 0; 2841 untimeout(bge_tick, sc, sc->bge_stat_ch); 2842 bge_tick(sc); 2843 /* Clear the interrupt */ 2844 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2845 BGE_EVTENB_MI_INTERRUPT); 2846 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2847 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2848 BRGPHY_INTRS); 2849 } 2850 } else { 2851 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2852 /* 2853 * Sometimes PCS encoding errors are detected in 2854 * TBI mode (on fiber NICs), and for some reason 2855 * the chip will signal them as link changes. 2856 * If we get a link change event, but the 'PCS 2857 * encoding error' bit in the MAC status register 2858 * is set, don't bother doing a link check. 2859 * This avoids spurious "gigabit link up" messages 2860 * that sometimes appear on fiber NICs during 2861 * periods of heavy traffic. (There should be no 2862 * effect on copper NICs.) 2863 */ 2864 status = CSR_READ_4(sc, BGE_MAC_STS); 2865 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2866 BGE_MACSTAT_MI_COMPLETE))) { 2867 sc->bge_link = 0; 2868 untimeout(bge_tick, sc, sc->bge_stat_ch); 2869 bge_tick(sc); 2870 } 2871 /* Clear the interrupt */ 2872 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2873 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2874 BGE_MACSTAT_LINK_CHANGED); 2875 2876 /* Force flush the status block cached by PCI bridge */ 2877 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2878 } 2879 } 2880 2881 if (ifp->if_flags & IFF_RUNNING) { 2882 /* Check RX return ring producer/consumer */ 2883 bge_rxeof(sc); 2884 2885 /* Check TX ring producer/consumer */ 2886 bge_txeof(sc); 2887 } 2888 2889 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2890 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2891 2892 bge_handle_events(sc); 2893 2894 /* Re-enable interrupts. */ 2895 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2896 2897 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2898 bge_start(ifp); 2899 2900 return; 2901 } 2902 2903 static void 2904 bge_tick(xsc) 2905 void *xsc; 2906 { 2907 struct bge_softc *sc; 2908 struct mii_data *mii = NULL; 2909 struct ifmedia *ifm = NULL; 2910 struct ifnet *ifp; 2911 int s; 2912 2913 sc = xsc; 2914 ifp = &sc->arpcom.ac_if; 2915 2916 s = splimp(); 2917 2918 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2919 bge_stats_update_regs(sc); 2920 else 2921 bge_stats_update(sc); 2922 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2923 if (sc->bge_link) { 2924 splx(s); 2925 return; 2926 } 2927 2928 if (sc->bge_tbi) { 2929 ifm = &sc->bge_ifmedia; 2930 if (CSR_READ_4(sc, BGE_MAC_STS) & 2931 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2932 sc->bge_link++; 2933 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2934 printf("bge%d: gigabit link up\n", sc->bge_unit); 2935 if (ifp->if_snd.ifq_head != NULL) 2936 bge_start(ifp); 2937 } 2938 splx(s); 2939 return; 2940 } 2941 2942 mii = device_get_softc(sc->bge_miibus); 2943 mii_tick(mii); 2944 2945 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2946 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2947 sc->bge_link++; 2948 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2949 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2950 printf("bge%d: gigabit link up\n", 2951 sc->bge_unit); 2952 if (ifp->if_snd.ifq_head != NULL) 2953 bge_start(ifp); 2954 } 2955 2956 splx(s); 2957 2958 return; 2959 } 2960 2961 static void 2962 bge_stats_update_regs(sc) 2963 struct bge_softc *sc; 2964 { 2965 struct ifnet *ifp; 2966 struct bge_mac_stats_regs stats; 2967 u_int32_t *s; 2968 int i; 2969 2970 ifp = &sc->arpcom.ac_if; 2971 2972 s = (u_int32_t *)&stats; 2973 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2974 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2975 s++; 2976 } 2977 2978 ifp->if_collisions += 2979 (stats.dot3StatsSingleCollisionFrames + 2980 stats.dot3StatsMultipleCollisionFrames + 2981 stats.dot3StatsExcessiveCollisions + 2982 stats.dot3StatsLateCollisions) - 2983 ifp->if_collisions; 2984 2985 return; 2986 } 2987 2988 static void 2989 bge_stats_update(sc) 2990 struct bge_softc *sc; 2991 { 2992 struct ifnet *ifp; 2993 struct bge_stats *stats; 2994 2995 ifp = &sc->arpcom.ac_if; 2996 2997 stats = (struct bge_stats *)(sc->bge_vhandle + 2998 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2999 3000 ifp->if_collisions += 3001 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3002 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3003 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3004 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3005 ifp->if_collisions; 3006 3007 #ifdef notdef 3008 ifp->if_collisions += 3009 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3010 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3011 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3012 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3013 ifp->if_collisions; 3014 #endif 3015 3016 return; 3017 } 3018 3019 /* 3020 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3021 * pointers to descriptors. 3022 */ 3023 static int 3024 bge_encap(sc, m_head, txidx) 3025 struct bge_softc *sc; 3026 struct mbuf *m_head; 3027 u_int32_t *txidx; 3028 { 3029 struct bge_tx_bd *f = NULL; 3030 u_int16_t csum_flags = 0; 3031 struct m_tag *mtag; 3032 struct bge_dmamap_arg ctx; 3033 bus_dmamap_t map; 3034 int error; 3035 3036 3037 if (m_head->m_pkthdr.csum_flags) { 3038 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3039 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3040 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3041 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3042 if (m_head->m_flags & M_LASTFRAG) 3043 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3044 else if (m_head->m_flags & M_FRAG) 3045 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3046 } 3047 3048 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3049 3050 ctx.sc = sc; 3051 ctx.bge_idx = *txidx; 3052 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3053 ctx.bge_flags = csum_flags; 3054 /* 3055 * Sanity check: avoid coming within 16 descriptors 3056 * of the end of the ring. 3057 */ 3058 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3059 3060 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3061 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3062 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3063 3064 if (error || ctx.bge_maxsegs == 0 /*|| 3065 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3066 return (ENOBUFS); 3067 3068 /* 3069 * Insure that the map for this transmission 3070 * is placed at the array index of the last descriptor 3071 * in this chain. 3072 */ 3073 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3074 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3075 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3076 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3077 sc->bge_txcnt += ctx.bge_maxsegs; 3078 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3079 if (mtag != NULL) { 3080 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3081 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3082 } else { 3083 f->bge_vlan_tag = 0; 3084 } 3085 3086 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3087 *txidx = ctx.bge_idx; 3088 3089 return(0); 3090 } 3091 3092 /* 3093 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3094 * to the mbuf data regions directly in the transmit descriptors. 3095 */ 3096 static void 3097 bge_start(ifp) 3098 struct ifnet *ifp; 3099 { 3100 struct bge_softc *sc; 3101 struct mbuf *m_head = NULL; 3102 u_int32_t prodidx = 0; 3103 3104 sc = ifp->if_softc; 3105 3106 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3107 return; 3108 3109 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3110 3111 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3112 IF_DEQUEUE(&ifp->if_snd, m_head); 3113 if (m_head == NULL) 3114 break; 3115 3116 /* 3117 * XXX 3118 * safety overkill. If this is a fragmented packet chain 3119 * with delayed TCP/UDP checksums, then only encapsulate 3120 * it if we have enough descriptors to handle the entire 3121 * chain at once. 3122 * (paranoia -- may not actually be needed) 3123 */ 3124 if (m_head->m_flags & M_FIRSTFRAG && 3125 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3126 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3127 m_head->m_pkthdr.csum_data + 16) { 3128 IF_PREPEND(&ifp->if_snd, m_head); 3129 ifp->if_flags |= IFF_OACTIVE; 3130 break; 3131 } 3132 } 3133 3134 /* 3135 * Pack the data into the transmit ring. If we 3136 * don't have room, set the OACTIVE flag and wait 3137 * for the NIC to drain the ring. 3138 */ 3139 if (bge_encap(sc, m_head, &prodidx)) { 3140 IF_PREPEND(&ifp->if_snd, m_head); 3141 ifp->if_flags |= IFF_OACTIVE; 3142 break; 3143 } 3144 3145 /* 3146 * If there's a BPF listener, bounce a copy of this frame 3147 * to him. 3148 */ 3149 BPF_MTAP(ifp, m_head); 3150 } 3151 3152 /* Transmit */ 3153 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3154 /* 5700 b2 errata */ 3155 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3156 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3157 3158 /* 3159 * Set a timeout in case the chip goes out to lunch. 3160 */ 3161 ifp->if_timer = 5; 3162 3163 return; 3164 } 3165 3166 static void 3167 bge_init(xsc) 3168 void *xsc; 3169 { 3170 struct bge_softc *sc = xsc; 3171 struct ifnet *ifp; 3172 u_int16_t *m; 3173 int s; 3174 3175 s = splimp(); 3176 3177 ifp = &sc->arpcom.ac_if; 3178 3179 if (ifp->if_flags & IFF_RUNNING) { 3180 splx(s); 3181 return; 3182 } 3183 3184 /* Cancel pending I/O and flush buffers. */ 3185 bge_stop(sc); 3186 bge_reset(sc); 3187 bge_chipinit(sc); 3188 3189 /* 3190 * Init the various state machines, ring 3191 * control blocks and firmware. 3192 */ 3193 if (bge_blockinit(sc)) { 3194 printf("bge%d: initialization failure\n", sc->bge_unit); 3195 splx(s); 3196 return; 3197 } 3198 3199 ifp = &sc->arpcom.ac_if; 3200 3201 /* Specify MTU. */ 3202 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3203 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3204 3205 /* Load our MAC address. */ 3206 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3207 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3208 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3209 3210 /* Enable or disable promiscuous mode as needed. */ 3211 if (ifp->if_flags & IFF_PROMISC) { 3212 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3213 } else { 3214 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3215 } 3216 3217 /* Program multicast filter. */ 3218 bge_setmulti(sc); 3219 3220 /* Init RX ring. */ 3221 bge_init_rx_ring_std(sc); 3222 3223 /* 3224 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3225 * memory to insure that the chip has in fact read the first 3226 * entry of the ring. 3227 */ 3228 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3229 u_int32_t v, i; 3230 for (i = 0; i < 10; i++) { 3231 DELAY(20); 3232 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3233 if (v == (MCLBYTES - ETHER_ALIGN)) 3234 break; 3235 } 3236 if (i == 10) 3237 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3238 sc->bge_unit); 3239 } 3240 3241 /* Init jumbo RX ring. */ 3242 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3243 bge_init_rx_ring_jumbo(sc); 3244 3245 /* Init our RX return ring index */ 3246 sc->bge_rx_saved_considx = 0; 3247 3248 /* Init TX ring. */ 3249 bge_init_tx_ring(sc); 3250 3251 /* Turn on transmitter */ 3252 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3253 3254 /* Turn on receiver */ 3255 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3256 3257 /* Tell firmware we're alive. */ 3258 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3259 3260 /* Enable host interrupts. */ 3261 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3262 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3263 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3264 3265 bge_ifmedia_upd(ifp); 3266 3267 ifp->if_flags |= IFF_RUNNING; 3268 ifp->if_flags &= ~IFF_OACTIVE; 3269 3270 splx(s); 3271 3272 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 3273 3274 return; 3275 } 3276 3277 /* 3278 * Set media options. 3279 */ 3280 static int 3281 bge_ifmedia_upd(ifp) 3282 struct ifnet *ifp; 3283 { 3284 struct bge_softc *sc; 3285 struct mii_data *mii; 3286 struct ifmedia *ifm; 3287 3288 sc = ifp->if_softc; 3289 ifm = &sc->bge_ifmedia; 3290 3291 /* If this is a 1000baseX NIC, enable the TBI port. */ 3292 if (sc->bge_tbi) { 3293 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3294 return(EINVAL); 3295 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3296 case IFM_AUTO: 3297 break; 3298 case IFM_1000_SX: 3299 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3300 BGE_CLRBIT(sc, BGE_MAC_MODE, 3301 BGE_MACMODE_HALF_DUPLEX); 3302 } else { 3303 BGE_SETBIT(sc, BGE_MAC_MODE, 3304 BGE_MACMODE_HALF_DUPLEX); 3305 } 3306 break; 3307 default: 3308 return(EINVAL); 3309 } 3310 return(0); 3311 } 3312 3313 mii = device_get_softc(sc->bge_miibus); 3314 sc->bge_link = 0; 3315 if (mii->mii_instance) { 3316 struct mii_softc *miisc; 3317 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3318 miisc = LIST_NEXT(miisc, mii_list)) 3319 mii_phy_reset(miisc); 3320 } 3321 mii_mediachg(mii); 3322 3323 return(0); 3324 } 3325 3326 /* 3327 * Report current media status. 3328 */ 3329 static void 3330 bge_ifmedia_sts(ifp, ifmr) 3331 struct ifnet *ifp; 3332 struct ifmediareq *ifmr; 3333 { 3334 struct bge_softc *sc; 3335 struct mii_data *mii; 3336 3337 sc = ifp->if_softc; 3338 3339 if (sc->bge_tbi) { 3340 ifmr->ifm_status = IFM_AVALID; 3341 ifmr->ifm_active = IFM_ETHER; 3342 if (CSR_READ_4(sc, BGE_MAC_STS) & 3343 BGE_MACSTAT_TBI_PCS_SYNCHED) 3344 ifmr->ifm_status |= IFM_ACTIVE; 3345 ifmr->ifm_active |= IFM_1000_SX; 3346 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3347 ifmr->ifm_active |= IFM_HDX; 3348 else 3349 ifmr->ifm_active |= IFM_FDX; 3350 return; 3351 } 3352 3353 mii = device_get_softc(sc->bge_miibus); 3354 mii_pollstat(mii); 3355 ifmr->ifm_active = mii->mii_media_active; 3356 ifmr->ifm_status = mii->mii_media_status; 3357 3358 return; 3359 } 3360 3361 static int 3362 bge_ioctl(ifp, command, data) 3363 struct ifnet *ifp; 3364 u_long command; 3365 caddr_t data; 3366 { 3367 struct bge_softc *sc = ifp->if_softc; 3368 struct ifreq *ifr = (struct ifreq *) data; 3369 int s, mask, error = 0; 3370 struct mii_data *mii; 3371 3372 s = splimp(); 3373 3374 switch(command) { 3375 case SIOCSIFMTU: 3376 /* Disallow jumbo frames on 5705. */ 3377 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3378 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3379 error = EINVAL; 3380 else { 3381 ifp->if_mtu = ifr->ifr_mtu; 3382 ifp->if_flags &= ~IFF_RUNNING; 3383 bge_init(sc); 3384 } 3385 break; 3386 case SIOCSIFFLAGS: 3387 if (ifp->if_flags & IFF_UP) { 3388 /* 3389 * If only the state of the PROMISC flag changed, 3390 * then just use the 'set promisc mode' command 3391 * instead of reinitializing the entire NIC. Doing 3392 * a full re-init means reloading the firmware and 3393 * waiting for it to start up, which may take a 3394 * second or two. 3395 */ 3396 if (ifp->if_flags & IFF_RUNNING && 3397 ifp->if_flags & IFF_PROMISC && 3398 !(sc->bge_if_flags & IFF_PROMISC)) { 3399 BGE_SETBIT(sc, BGE_RX_MODE, 3400 BGE_RXMODE_RX_PROMISC); 3401 } else if (ifp->if_flags & IFF_RUNNING && 3402 !(ifp->if_flags & IFF_PROMISC) && 3403 sc->bge_if_flags & IFF_PROMISC) { 3404 BGE_CLRBIT(sc, BGE_RX_MODE, 3405 BGE_RXMODE_RX_PROMISC); 3406 } else 3407 bge_init(sc); 3408 } else { 3409 if (ifp->if_flags & IFF_RUNNING) { 3410 bge_stop(sc); 3411 } 3412 } 3413 sc->bge_if_flags = ifp->if_flags; 3414 error = 0; 3415 break; 3416 case SIOCADDMULTI: 3417 case SIOCDELMULTI: 3418 if (ifp->if_flags & IFF_RUNNING) { 3419 bge_setmulti(sc); 3420 error = 0; 3421 } 3422 break; 3423 case SIOCSIFMEDIA: 3424 case SIOCGIFMEDIA: 3425 if (sc->bge_tbi) { 3426 error = ifmedia_ioctl(ifp, ifr, 3427 &sc->bge_ifmedia, command); 3428 } else { 3429 mii = device_get_softc(sc->bge_miibus); 3430 error = ifmedia_ioctl(ifp, ifr, 3431 &mii->mii_media, command); 3432 } 3433 break; 3434 case SIOCSIFCAP: 3435 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3436 if (mask & IFCAP_HWCSUM) { 3437 if (IFCAP_HWCSUM & ifp->if_capenable) 3438 ifp->if_capenable &= ~IFCAP_HWCSUM; 3439 else 3440 ifp->if_capenable |= IFCAP_HWCSUM; 3441 } 3442 error = 0; 3443 break; 3444 default: 3445 error = ether_ioctl(ifp, command, data); 3446 break; 3447 } 3448 3449 (void)splx(s); 3450 3451 return(error); 3452 } 3453 3454 static void 3455 bge_watchdog(ifp) 3456 struct ifnet *ifp; 3457 { 3458 struct bge_softc *sc; 3459 3460 sc = ifp->if_softc; 3461 3462 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3463 3464 ifp->if_flags &= ~IFF_RUNNING; 3465 bge_init(sc); 3466 3467 ifp->if_oerrors++; 3468 3469 return; 3470 } 3471 3472 /* 3473 * Stop the adapter and free any mbufs allocated to the 3474 * RX and TX lists. 3475 */ 3476 static void 3477 bge_stop(sc) 3478 struct bge_softc *sc; 3479 { 3480 struct ifnet *ifp; 3481 struct ifmedia_entry *ifm; 3482 struct mii_data *mii = NULL; 3483 int mtmp, itmp; 3484 3485 ifp = &sc->arpcom.ac_if; 3486 3487 if (!sc->bge_tbi) 3488 mii = device_get_softc(sc->bge_miibus); 3489 3490 untimeout(bge_tick, sc, sc->bge_stat_ch); 3491 3492 /* 3493 * Disable all of the receiver blocks 3494 */ 3495 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3496 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3497 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3498 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3499 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3500 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3501 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3502 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3503 3504 /* 3505 * Disable all of the transmit blocks 3506 */ 3507 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3508 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3509 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3510 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3511 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3512 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3513 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3514 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3515 3516 /* 3517 * Shut down all of the memory managers and related 3518 * state machines. 3519 */ 3520 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3521 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3522 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3523 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3524 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3525 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3526 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 3527 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3528 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3529 } 3530 3531 /* Disable host interrupts. */ 3532 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3533 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3534 3535 /* 3536 * Tell firmware we're shutting down. 3537 */ 3538 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3539 3540 /* Free the RX lists. */ 3541 bge_free_rx_ring_std(sc); 3542 3543 /* Free jumbo RX list. */ 3544 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3545 bge_free_rx_ring_jumbo(sc); 3546 3547 /* Free TX buffers. */ 3548 bge_free_tx_ring(sc); 3549 3550 /* 3551 * Isolate/power down the PHY, but leave the media selection 3552 * unchanged so that things will be put back to normal when 3553 * we bring the interface back up. 3554 */ 3555 if (!sc->bge_tbi) { 3556 itmp = ifp->if_flags; 3557 ifp->if_flags |= IFF_UP; 3558 ifm = mii->mii_media.ifm_cur; 3559 mtmp = ifm->ifm_media; 3560 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3561 mii_mediachg(mii); 3562 ifm->ifm_media = mtmp; 3563 ifp->if_flags = itmp; 3564 } 3565 3566 sc->bge_link = 0; 3567 3568 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3569 3570 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3571 3572 return; 3573 } 3574 3575 /* 3576 * Stop all chip I/O so that the kernel's probe routines don't 3577 * get confused by errant DMAs when rebooting. 3578 */ 3579 static void 3580 bge_shutdown(dev) 3581 device_t dev; 3582 { 3583 struct bge_softc *sc; 3584 3585 sc = device_get_softc(dev); 3586 3587 bge_stop(sc); 3588 bge_reset(sc); 3589 3590 return; 3591 } 3592