1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/cdefs.h> 70 __FBSDID("$FreeBSD$"); 71 72 #include <sys/param.h> 73 #include <sys/endian.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <machine/clock.h> /* for DELAY */ 98 #include <machine/bus_memio.h> 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 112 #include <dev/bge/if_bgereg.h> 113 114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 115 116 MODULE_DEPEND(bge, pci, 1, 1, 1); 117 MODULE_DEPEND(bge, ether, 1, 1, 1); 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Various supported device vendors/types and their names. Note: the 125 * spec seems to indicate that the hardware still has Alteon's vendor 126 * ID burned into it, though it will always be overriden by the vendor 127 * ID in the EEPROM. Just to be safe, we cover all possibilities. 128 */ 129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 130 131 static struct bge_type bge_devs[] = { 132 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 141 "Broadcom BCM5702 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 145 "Broadcom BCM5703 Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 149 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 151 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 153 "Broadcom BCM5705 Gigabit Ethernet" }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 155 "Broadcom BCM5705M Gigabit Ethernet" }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 157 "Broadcom BCM5705M Gigabit Ethernet" }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 159 "Broadcom BCM5782 Gigabit Ethernet" }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 161 "Broadcom BCM5901 Fast Ethernet" }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 163 "Broadcom BCM5901A2 Fast Ethernet" }, 164 { SK_VENDORID, SK_DEVICEID_ALTIMA, 165 "SysKonnect Gigabit Ethernet" }, 166 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 167 "Altima AC1000 Gigabit Ethernet" }, 168 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 169 "Altima AC9100 Gigabit Ethernet" }, 170 { 0, 0, NULL } 171 }; 172 173 static int bge_probe (device_t); 174 static int bge_attach (device_t); 175 static int bge_detach (device_t); 176 static void bge_release_resources 177 (struct bge_softc *); 178 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 179 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 180 bus_size_t, int); 181 static int bge_dma_alloc (device_t); 182 static void bge_dma_free (struct bge_softc *); 183 184 static void bge_txeof (struct bge_softc *); 185 static void bge_rxeof (struct bge_softc *); 186 187 static void bge_tick (void *); 188 static void bge_stats_update (struct bge_softc *); 189 static void bge_stats_update_regs 190 (struct bge_softc *); 191 static int bge_encap (struct bge_softc *, struct mbuf *, 192 u_int32_t *); 193 194 static void bge_intr (void *); 195 static void bge_start (struct ifnet *); 196 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 197 static void bge_init (void *); 198 static void bge_stop (struct bge_softc *); 199 static void bge_watchdog (struct ifnet *); 200 static void bge_shutdown (device_t); 201 static int bge_ifmedia_upd (struct ifnet *); 202 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 203 204 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 205 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 206 207 static u_int32_t bge_crc (caddr_t); 208 static void bge_setmulti (struct bge_softc *); 209 210 static void bge_handle_events (struct bge_softc *); 211 static int bge_alloc_jumbo_mem (struct bge_softc *); 212 static void bge_free_jumbo_mem (struct bge_softc *); 213 static void *bge_jalloc (struct bge_softc *); 214 static void bge_jfree (void *, void *); 215 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 216 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 217 static int bge_init_rx_ring_std (struct bge_softc *); 218 static void bge_free_rx_ring_std (struct bge_softc *); 219 static int bge_init_rx_ring_jumbo (struct bge_softc *); 220 static void bge_free_rx_ring_jumbo (struct bge_softc *); 221 static void bge_free_tx_ring (struct bge_softc *); 222 static int bge_init_tx_ring (struct bge_softc *); 223 224 static int bge_chipinit (struct bge_softc *); 225 static int bge_blockinit (struct bge_softc *); 226 227 #ifdef notdef 228 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 229 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 230 static void bge_vpd_read (struct bge_softc *); 231 #endif 232 233 static u_int32_t bge_readmem_ind 234 (struct bge_softc *, int); 235 static void bge_writemem_ind (struct bge_softc *, int, int); 236 #ifdef notdef 237 static u_int32_t bge_readreg_ind 238 (struct bge_softc *, int); 239 #endif 240 static void bge_writereg_ind (struct bge_softc *, int, int); 241 242 static int bge_miibus_readreg (device_t, int, int); 243 static int bge_miibus_writereg (device_t, int, int, int); 244 static void bge_miibus_statchg (device_t); 245 246 static void bge_reset (struct bge_softc *); 247 248 static device_method_t bge_methods[] = { 249 /* Device interface */ 250 DEVMETHOD(device_probe, bge_probe), 251 DEVMETHOD(device_attach, bge_attach), 252 DEVMETHOD(device_detach, bge_detach), 253 DEVMETHOD(device_shutdown, bge_shutdown), 254 255 /* bus interface */ 256 DEVMETHOD(bus_print_child, bus_generic_print_child), 257 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 258 259 /* MII interface */ 260 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 261 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 262 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 263 264 { 0, 0 } 265 }; 266 267 static driver_t bge_driver = { 268 "bge", 269 bge_methods, 270 sizeof(struct bge_softc) 271 }; 272 273 static devclass_t bge_devclass; 274 275 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 276 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 277 278 static u_int32_t 279 bge_readmem_ind(sc, off) 280 struct bge_softc *sc; 281 int off; 282 { 283 device_t dev; 284 285 dev = sc->bge_dev; 286 287 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 288 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 289 } 290 291 static void 292 bge_writemem_ind(sc, off, val) 293 struct bge_softc *sc; 294 int off, val; 295 { 296 device_t dev; 297 298 dev = sc->bge_dev; 299 300 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 301 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 302 303 return; 304 } 305 306 #ifdef notdef 307 static u_int32_t 308 bge_readreg_ind(sc, off) 309 struct bge_softc *sc; 310 int off; 311 { 312 device_t dev; 313 314 dev = sc->bge_dev; 315 316 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 317 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 318 } 319 #endif 320 321 static void 322 bge_writereg_ind(sc, off, val) 323 struct bge_softc *sc; 324 int off, val; 325 { 326 device_t dev; 327 328 dev = sc->bge_dev; 329 330 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 331 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 332 333 return; 334 } 335 336 /* 337 * Map a single buffer address. 338 */ 339 340 static void 341 bge_dma_map_addr(arg, segs, nseg, error) 342 void *arg; 343 bus_dma_segment_t *segs; 344 int nseg; 345 int error; 346 { 347 struct bge_dmamap_arg *ctx; 348 349 if (error) 350 return; 351 352 ctx = arg; 353 354 if (nseg > ctx->bge_maxsegs) { 355 ctx->bge_maxsegs = 0; 356 return; 357 } 358 359 ctx->bge_busaddr = segs->ds_addr; 360 361 return; 362 } 363 364 /* 365 * Map an mbuf chain into an TX ring. 366 */ 367 368 static void 369 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 370 void *arg; 371 bus_dma_segment_t *segs; 372 int nseg; 373 bus_size_t mapsize; 374 int error; 375 { 376 struct bge_dmamap_arg *ctx; 377 struct bge_tx_bd *d = NULL; 378 int i = 0, idx; 379 380 if (error) 381 return; 382 383 ctx = arg; 384 385 /* Signal error to caller if there's too many segments */ 386 if (nseg > ctx->bge_maxsegs) { 387 ctx->bge_maxsegs = 0; 388 return; 389 } 390 391 idx = ctx->bge_idx; 392 while(1) { 393 d = &ctx->bge_ring[idx]; 394 d->bge_addr.bge_addr_lo = 395 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 396 d->bge_addr.bge_addr_hi = 397 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 398 d->bge_len = htole16(segs[i].ds_len); 399 d->bge_flags = htole16(ctx->bge_flags); 400 i++; 401 if (i == nseg) 402 break; 403 BGE_INC(idx, BGE_TX_RING_CNT); 404 } 405 406 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 407 ctx->bge_maxsegs = nseg; 408 ctx->bge_idx = idx; 409 410 return; 411 } 412 413 414 #ifdef notdef 415 static u_int8_t 416 bge_vpd_readbyte(sc, addr) 417 struct bge_softc *sc; 418 int addr; 419 { 420 int i; 421 device_t dev; 422 u_int32_t val; 423 424 dev = sc->bge_dev; 425 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 426 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 427 DELAY(10); 428 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 429 break; 430 } 431 432 if (i == BGE_TIMEOUT) { 433 printf("bge%d: VPD read timed out\n", sc->bge_unit); 434 return(0); 435 } 436 437 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 438 439 return((val >> ((addr % 4) * 8)) & 0xFF); 440 } 441 442 static void 443 bge_vpd_read_res(sc, res, addr) 444 struct bge_softc *sc; 445 struct vpd_res *res; 446 int addr; 447 { 448 int i; 449 u_int8_t *ptr; 450 451 ptr = (u_int8_t *)res; 452 for (i = 0; i < sizeof(struct vpd_res); i++) 453 ptr[i] = bge_vpd_readbyte(sc, i + addr); 454 455 return; 456 } 457 458 static void 459 bge_vpd_read(sc) 460 struct bge_softc *sc; 461 { 462 int pos = 0, i; 463 struct vpd_res res; 464 465 if (sc->bge_vpd_prodname != NULL) 466 free(sc->bge_vpd_prodname, M_DEVBUF); 467 if (sc->bge_vpd_readonly != NULL) 468 free(sc->bge_vpd_readonly, M_DEVBUF); 469 sc->bge_vpd_prodname = NULL; 470 sc->bge_vpd_readonly = NULL; 471 472 bge_vpd_read_res(sc, &res, pos); 473 474 if (res.vr_id != VPD_RES_ID) { 475 printf("bge%d: bad VPD resource id: expected %x got %x\n", 476 sc->bge_unit, VPD_RES_ID, res.vr_id); 477 return; 478 } 479 480 pos += sizeof(res); 481 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 482 for (i = 0; i < res.vr_len; i++) 483 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 484 sc->bge_vpd_prodname[i] = '\0'; 485 pos += i; 486 487 bge_vpd_read_res(sc, &res, pos); 488 489 if (res.vr_id != VPD_RES_READ) { 490 printf("bge%d: bad VPD resource id: expected %x got %x\n", 491 sc->bge_unit, VPD_RES_READ, res.vr_id); 492 return; 493 } 494 495 pos += sizeof(res); 496 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 497 for (i = 0; i < res.vr_len + 1; i++) 498 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 499 500 return; 501 } 502 #endif 503 504 /* 505 * Read a byte of data stored in the EEPROM at address 'addr.' The 506 * BCM570x supports both the traditional bitbang interface and an 507 * auto access interface for reading the EEPROM. We use the auto 508 * access method. 509 */ 510 static u_int8_t 511 bge_eeprom_getbyte(sc, addr, dest) 512 struct bge_softc *sc; 513 int addr; 514 u_int8_t *dest; 515 { 516 int i; 517 u_int32_t byte = 0; 518 519 /* 520 * Enable use of auto EEPROM access so we can avoid 521 * having to use the bitbang method. 522 */ 523 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 524 525 /* Reset the EEPROM, load the clock period. */ 526 CSR_WRITE_4(sc, BGE_EE_ADDR, 527 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 528 DELAY(20); 529 530 /* Issue the read EEPROM command. */ 531 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 532 533 /* Wait for completion */ 534 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 535 DELAY(10); 536 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 537 break; 538 } 539 540 if (i == BGE_TIMEOUT) { 541 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 542 return(0); 543 } 544 545 /* Get result. */ 546 byte = CSR_READ_4(sc, BGE_EE_DATA); 547 548 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 549 550 return(0); 551 } 552 553 /* 554 * Read a sequence of bytes from the EEPROM. 555 */ 556 static int 557 bge_read_eeprom(sc, dest, off, cnt) 558 struct bge_softc *sc; 559 caddr_t dest; 560 int off; 561 int cnt; 562 { 563 int err = 0, i; 564 u_int8_t byte = 0; 565 566 for (i = 0; i < cnt; i++) { 567 err = bge_eeprom_getbyte(sc, off + i, &byte); 568 if (err) 569 break; 570 *(dest + i) = byte; 571 } 572 573 return(err ? 1 : 0); 574 } 575 576 static int 577 bge_miibus_readreg(dev, phy, reg) 578 device_t dev; 579 int phy, reg; 580 { 581 struct bge_softc *sc; 582 u_int32_t val, autopoll; 583 int i; 584 585 sc = device_get_softc(dev); 586 587 /* 588 * Broadcom's own driver always assumes the internal 589 * PHY is at GMII address 1. On some chips, the PHY responds 590 * to accesses at all addresses, which could cause us to 591 * bogusly attach the PHY 32 times at probe type. Always 592 * restricting the lookup to address 1 is simpler than 593 * trying to figure out which chips revisions should be 594 * special-cased. 595 */ 596 if (phy != 1) 597 return(0); 598 599 /* Reading with autopolling on may trigger PCI errors */ 600 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 601 if (autopoll & BGE_MIMODE_AUTOPOLL) { 602 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 603 DELAY(40); 604 } 605 606 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 607 BGE_MIPHY(phy)|BGE_MIREG(reg)); 608 609 for (i = 0; i < BGE_TIMEOUT; i++) { 610 val = CSR_READ_4(sc, BGE_MI_COMM); 611 if (!(val & BGE_MICOMM_BUSY)) 612 break; 613 } 614 615 if (i == BGE_TIMEOUT) { 616 printf("bge%d: PHY read timed out\n", sc->bge_unit); 617 val = 0; 618 goto done; 619 } 620 621 val = CSR_READ_4(sc, BGE_MI_COMM); 622 623 done: 624 if (autopoll & BGE_MIMODE_AUTOPOLL) { 625 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 626 DELAY(40); 627 } 628 629 if (val & BGE_MICOMM_READFAIL) 630 return(0); 631 632 return(val & 0xFFFF); 633 } 634 635 static int 636 bge_miibus_writereg(dev, phy, reg, val) 637 device_t dev; 638 int phy, reg, val; 639 { 640 struct bge_softc *sc; 641 u_int32_t autopoll; 642 int i; 643 644 sc = device_get_softc(dev); 645 646 /* Reading with autopolling on may trigger PCI errors */ 647 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 648 if (autopoll & BGE_MIMODE_AUTOPOLL) { 649 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 650 DELAY(40); 651 } 652 653 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 654 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 655 656 for (i = 0; i < BGE_TIMEOUT; i++) { 657 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 658 break; 659 } 660 661 if (autopoll & BGE_MIMODE_AUTOPOLL) { 662 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 663 DELAY(40); 664 } 665 666 if (i == BGE_TIMEOUT) { 667 printf("bge%d: PHY read timed out\n", sc->bge_unit); 668 return(0); 669 } 670 671 return(0); 672 } 673 674 static void 675 bge_miibus_statchg(dev) 676 device_t dev; 677 { 678 struct bge_softc *sc; 679 struct mii_data *mii; 680 681 sc = device_get_softc(dev); 682 mii = device_get_softc(sc->bge_miibus); 683 684 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 685 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 686 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 687 } else { 688 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 689 } 690 691 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 692 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 693 } else { 694 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 695 } 696 697 return; 698 } 699 700 /* 701 * Handle events that have triggered interrupts. 702 */ 703 static void 704 bge_handle_events(sc) 705 struct bge_softc *sc; 706 { 707 708 return; 709 } 710 711 /* 712 * Memory management for jumbo frames. 713 */ 714 715 static int 716 bge_alloc_jumbo_mem(sc) 717 struct bge_softc *sc; 718 { 719 caddr_t ptr; 720 register int i, error; 721 struct bge_jpool_entry *entry; 722 723 /* Create tag for jumbo buffer block */ 724 725 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 726 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 727 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 728 &sc->bge_cdata.bge_jumbo_tag); 729 730 if (error) { 731 printf("bge%d: could not allocate jumbo dma tag\n", 732 sc->bge_unit); 733 return (ENOMEM); 734 } 735 736 /* Allocate DMA'able memory for jumbo buffer block */ 737 738 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 739 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 740 &sc->bge_cdata.bge_jumbo_map); 741 742 if (error) 743 return (ENOMEM); 744 745 SLIST_INIT(&sc->bge_jfree_listhead); 746 SLIST_INIT(&sc->bge_jinuse_listhead); 747 748 /* 749 * Now divide it up into 9K pieces and save the addresses 750 * in an array. 751 */ 752 ptr = sc->bge_ldata.bge_jumbo_buf; 753 for (i = 0; i < BGE_JSLOTS; i++) { 754 sc->bge_cdata.bge_jslots[i] = ptr; 755 ptr += BGE_JLEN; 756 entry = malloc(sizeof(struct bge_jpool_entry), 757 M_DEVBUF, M_NOWAIT); 758 if (entry == NULL) { 759 bge_free_jumbo_mem(sc); 760 sc->bge_ldata.bge_jumbo_buf = NULL; 761 printf("bge%d: no memory for jumbo " 762 "buffer queue!\n", sc->bge_unit); 763 return(ENOBUFS); 764 } 765 entry->slot = i; 766 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 767 entry, jpool_entries); 768 } 769 770 return(0); 771 } 772 773 static void 774 bge_free_jumbo_mem(sc) 775 struct bge_softc *sc; 776 { 777 int i; 778 struct bge_jpool_entry *entry; 779 780 for (i = 0; i < BGE_JSLOTS; i++) { 781 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 782 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 783 free(entry, M_DEVBUF); 784 } 785 786 /* Destroy jumbo buffer block */ 787 788 if (sc->bge_ldata.bge_rx_jumbo_ring) 789 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 790 sc->bge_ldata.bge_jumbo_buf, 791 sc->bge_cdata.bge_jumbo_map); 792 793 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 794 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 795 sc->bge_cdata.bge_jumbo_map); 796 797 if (sc->bge_cdata.bge_jumbo_tag) 798 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 799 800 return; 801 } 802 803 /* 804 * Allocate a jumbo buffer. 805 */ 806 static void * 807 bge_jalloc(sc) 808 struct bge_softc *sc; 809 { 810 struct bge_jpool_entry *entry; 811 812 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 813 814 if (entry == NULL) { 815 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 816 return(NULL); 817 } 818 819 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 820 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 821 return(sc->bge_cdata.bge_jslots[entry->slot]); 822 } 823 824 /* 825 * Release a jumbo buffer. 826 */ 827 static void 828 bge_jfree(buf, args) 829 void *buf; 830 void *args; 831 { 832 struct bge_jpool_entry *entry; 833 struct bge_softc *sc; 834 int i; 835 836 /* Extract the softc struct pointer. */ 837 sc = (struct bge_softc *)args; 838 839 if (sc == NULL) 840 panic("bge_jfree: can't find softc pointer!"); 841 842 /* calculate the slot this buffer belongs to */ 843 844 i = ((vm_offset_t)buf 845 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 846 847 if ((i < 0) || (i >= BGE_JSLOTS)) 848 panic("bge_jfree: asked to free buffer that we don't manage!"); 849 850 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 851 if (entry == NULL) 852 panic("bge_jfree: buffer not in use!"); 853 entry->slot = i; 854 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 855 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 856 857 return; 858 } 859 860 861 /* 862 * Intialize a standard receive ring descriptor. 863 */ 864 static int 865 bge_newbuf_std(sc, i, m) 866 struct bge_softc *sc; 867 int i; 868 struct mbuf *m; 869 { 870 struct mbuf *m_new = NULL; 871 struct bge_rx_bd *r; 872 struct bge_dmamap_arg ctx; 873 int error; 874 875 if (m == NULL) { 876 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 877 if (m_new == NULL) { 878 return(ENOBUFS); 879 } 880 881 MCLGET(m_new, M_DONTWAIT); 882 if (!(m_new->m_flags & M_EXT)) { 883 m_freem(m_new); 884 return(ENOBUFS); 885 } 886 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 887 } else { 888 m_new = m; 889 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 890 m_new->m_data = m_new->m_ext.ext_buf; 891 } 892 893 if (!sc->bge_rx_alignment_bug) 894 m_adj(m_new, ETHER_ALIGN); 895 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 896 r = &sc->bge_ldata.bge_rx_std_ring[i]; 897 ctx.bge_maxsegs = 1; 898 ctx.sc = sc; 899 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 900 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 901 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 902 if (error || ctx.bge_maxsegs == 0) { 903 if (m == NULL) 904 m_freem(m_new); 905 return(ENOMEM); 906 } 907 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 908 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 909 r->bge_flags = htole16(BGE_RXBDFLAG_END); 910 r->bge_len = htole16(m_new->m_len); 911 r->bge_idx = htole16(i); 912 913 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 914 sc->bge_cdata.bge_rx_std_dmamap[i], 915 BUS_DMASYNC_PREREAD); 916 917 return(0); 918 } 919 920 /* 921 * Initialize a jumbo receive ring descriptor. This allocates 922 * a jumbo buffer from the pool managed internally by the driver. 923 */ 924 static int 925 bge_newbuf_jumbo(sc, i, m) 926 struct bge_softc *sc; 927 int i; 928 struct mbuf *m; 929 { 930 struct mbuf *m_new = NULL; 931 struct bge_rx_bd *r; 932 struct bge_dmamap_arg ctx; 933 int error; 934 935 if (m == NULL) { 936 caddr_t *buf = NULL; 937 938 /* Allocate the mbuf. */ 939 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 940 if (m_new == NULL) { 941 return(ENOBUFS); 942 } 943 944 /* Allocate the jumbo buffer */ 945 buf = bge_jalloc(sc); 946 if (buf == NULL) { 947 m_freem(m_new); 948 printf("bge%d: jumbo allocation failed " 949 "-- packet dropped!\n", sc->bge_unit); 950 return(ENOBUFS); 951 } 952 953 /* Attach the buffer to the mbuf. */ 954 m_new->m_data = (void *) buf; 955 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 956 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 957 (struct bge_softc *)sc, 0, EXT_NET_DRV); 958 } else { 959 m_new = m; 960 m_new->m_data = m_new->m_ext.ext_buf; 961 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 962 } 963 964 if (!sc->bge_rx_alignment_bug) 965 m_adj(m_new, ETHER_ALIGN); 966 /* Set up the descriptor. */ 967 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 968 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 969 ctx.bge_maxsegs = 1; 970 ctx.sc = sc; 971 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 972 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 973 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 974 if (error || ctx.bge_maxsegs == 0) { 975 if (m == NULL) 976 m_freem(m_new); 977 return(ENOMEM); 978 } 979 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 980 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 981 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 982 r->bge_len = htole16(m_new->m_len); 983 r->bge_idx = htole16(i); 984 985 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 986 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 987 BUS_DMASYNC_PREREAD); 988 989 return(0); 990 } 991 992 /* 993 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 994 * that's 1MB or memory, which is a lot. For now, we fill only the first 995 * 256 ring entries and hope that our CPU is fast enough to keep up with 996 * the NIC. 997 */ 998 static int 999 bge_init_rx_ring_std(sc) 1000 struct bge_softc *sc; 1001 { 1002 int i; 1003 1004 for (i = 0; i < BGE_SSLOTS; i++) { 1005 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1006 return(ENOBUFS); 1007 }; 1008 1009 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1010 sc->bge_cdata.bge_rx_std_ring_map, 1011 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1012 1013 sc->bge_std = i - 1; 1014 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1015 1016 return(0); 1017 } 1018 1019 static void 1020 bge_free_rx_ring_std(sc) 1021 struct bge_softc *sc; 1022 { 1023 int i; 1024 1025 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1026 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1027 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1028 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1029 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1030 sc->bge_cdata.bge_rx_std_dmamap[i]); 1031 } 1032 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1033 sizeof(struct bge_rx_bd)); 1034 } 1035 1036 return; 1037 } 1038 1039 static int 1040 bge_init_rx_ring_jumbo(sc) 1041 struct bge_softc *sc; 1042 { 1043 int i; 1044 struct bge_rcb *rcb; 1045 1046 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1047 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1048 return(ENOBUFS); 1049 }; 1050 1051 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1052 sc->bge_cdata.bge_rx_jumbo_ring_map, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 1055 sc->bge_jumbo = i - 1; 1056 1057 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1058 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1059 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1060 1061 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1062 1063 return(0); 1064 } 1065 1066 static void 1067 bge_free_rx_ring_jumbo(sc) 1068 struct bge_softc *sc; 1069 { 1070 int i; 1071 1072 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1073 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1074 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1075 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1076 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1077 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1078 } 1079 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1080 sizeof(struct bge_rx_bd)); 1081 } 1082 1083 return; 1084 } 1085 1086 static void 1087 bge_free_tx_ring(sc) 1088 struct bge_softc *sc; 1089 { 1090 int i; 1091 1092 if (sc->bge_ldata.bge_tx_ring == NULL) 1093 return; 1094 1095 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1096 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1097 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1098 sc->bge_cdata.bge_tx_chain[i] = NULL; 1099 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1100 sc->bge_cdata.bge_tx_dmamap[i]); 1101 } 1102 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1103 sizeof(struct bge_tx_bd)); 1104 } 1105 1106 return; 1107 } 1108 1109 static int 1110 bge_init_tx_ring(sc) 1111 struct bge_softc *sc; 1112 { 1113 sc->bge_txcnt = 0; 1114 sc->bge_tx_saved_considx = 0; 1115 1116 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1117 /* 5700 b2 errata */ 1118 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1119 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1120 1121 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1122 /* 5700 b2 errata */ 1123 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1124 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1125 1126 return(0); 1127 } 1128 1129 #define BGE_POLY 0xEDB88320 1130 1131 static u_int32_t 1132 bge_crc(addr) 1133 caddr_t addr; 1134 { 1135 u_int32_t idx, bit, data, crc; 1136 1137 /* Compute CRC for the address value. */ 1138 crc = 0xFFFFFFFF; /* initial value */ 1139 1140 for (idx = 0; idx < 6; idx++) { 1141 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1142 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1143 } 1144 1145 return(crc & 0x7F); 1146 } 1147 1148 static void 1149 bge_setmulti(sc) 1150 struct bge_softc *sc; 1151 { 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1155 int h, i; 1156 1157 ifp = &sc->arpcom.ac_if; 1158 1159 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1160 for (i = 0; i < 4; i++) 1161 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1162 return; 1163 } 1164 1165 /* First, zot all the existing filters. */ 1166 for (i = 0; i < 4; i++) 1167 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1168 1169 /* Now program new ones. */ 1170 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1171 if (ifma->ifma_addr->sa_family != AF_LINK) 1172 continue; 1173 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1175 } 1176 1177 for (i = 0; i < 4; i++) 1178 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1179 1180 return; 1181 } 1182 1183 /* 1184 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1185 * self-test results. 1186 */ 1187 static int 1188 bge_chipinit(sc) 1189 struct bge_softc *sc; 1190 { 1191 int i; 1192 u_int32_t dma_rw_ctl; 1193 1194 /* Set endianness before we access any non-PCI registers. */ 1195 #if BYTE_ORDER == BIG_ENDIAN 1196 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1197 BGE_BIGENDIAN_INIT, 4); 1198 #else 1199 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1200 BGE_LITTLEENDIAN_INIT, 4); 1201 #endif 1202 1203 /* 1204 * Check the 'ROM failed' bit on the RX CPU to see if 1205 * self-tests passed. 1206 */ 1207 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1208 printf("bge%d: RX CPU self-diagnostics failed!\n", 1209 sc->bge_unit); 1210 return(ENODEV); 1211 } 1212 1213 /* Clear the MAC control register */ 1214 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1215 1216 /* 1217 * Clear the MAC statistics block in the NIC's 1218 * internal memory. 1219 */ 1220 for (i = BGE_STATS_BLOCK; 1221 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1222 BGE_MEMWIN_WRITE(sc, i, 0); 1223 1224 for (i = BGE_STATUS_BLOCK; 1225 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1226 BGE_MEMWIN_WRITE(sc, i, 0); 1227 1228 /* Set up the PCI DMA control register. */ 1229 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1230 BGE_PCISTATE_PCI_BUSMODE) { 1231 /* Conventional PCI bus */ 1232 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1233 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1234 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1235 (0x0F); 1236 } else { 1237 /* PCI-X bus */ 1238 /* 1239 * The 5704 uses a different encoding of read/write 1240 * watermarks. 1241 */ 1242 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1243 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1244 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1245 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1246 else 1247 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1248 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1249 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1250 (0x0F); 1251 1252 /* 1253 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1254 * for hardware bugs. 1255 */ 1256 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1257 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1258 u_int32_t tmp; 1259 1260 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1261 if (tmp == 0x6 || tmp == 0x7) 1262 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1263 } 1264 } 1265 1266 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1267 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1268 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1269 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1270 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1271 1272 /* 1273 * Set up general mode register. 1274 */ 1275 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1276 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1277 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1278 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1279 BGE_MODECTL_RX_NO_PHDR_CSUM); 1280 1281 /* 1282 * Disable memory write invalidate. Apparently it is not supported 1283 * properly by these devices. 1284 */ 1285 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1286 1287 #ifdef __brokenalpha__ 1288 /* 1289 * Must insure that we do not cross an 8K (bytes) boundary 1290 * for DMA reads. Our highest limit is 1K bytes. This is a 1291 * restriction on some ALPHA platforms with early revision 1292 * 21174 PCI chipsets, such as the AlphaPC 164lx 1293 */ 1294 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1295 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1296 #endif 1297 1298 /* Set the timer prescaler (always 66Mhz) */ 1299 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1300 1301 return(0); 1302 } 1303 1304 static int 1305 bge_blockinit(sc) 1306 struct bge_softc *sc; 1307 { 1308 struct bge_rcb *rcb; 1309 volatile struct bge_rcb *vrcb; 1310 int i; 1311 1312 /* 1313 * Initialize the memory window pointer register so that 1314 * we can access the first 32K of internal NIC RAM. This will 1315 * allow us to set up the TX send ring RCBs and the RX return 1316 * ring RCBs, plus other things which live in NIC memory. 1317 */ 1318 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1319 1320 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1321 1322 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1323 /* Configure mbuf memory pool */ 1324 if (sc->bge_extram) { 1325 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1326 BGE_EXT_SSRAM); 1327 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1328 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1329 else 1330 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1331 } else { 1332 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1333 BGE_BUFFPOOL_1); 1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1335 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1336 else 1337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1338 } 1339 1340 /* Configure DMA resource pool */ 1341 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1342 BGE_DMA_DESCRIPTORS); 1343 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1344 } 1345 1346 /* Configure mbuf pool watermarks */ 1347 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1348 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1350 } else { 1351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1353 } 1354 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1355 1356 /* Configure DMA resource watermarks */ 1357 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1358 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1359 1360 /* Enable buffer manager */ 1361 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1362 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1363 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1364 1365 /* Poll for buffer manager start indication */ 1366 for (i = 0; i < BGE_TIMEOUT; i++) { 1367 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1368 break; 1369 DELAY(10); 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 printf("bge%d: buffer manager failed to start\n", 1374 sc->bge_unit); 1375 return(ENXIO); 1376 } 1377 } 1378 1379 /* Enable flow-through queues */ 1380 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1381 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1382 1383 /* Wait until queue initialization is complete */ 1384 for (i = 0; i < BGE_TIMEOUT; i++) { 1385 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1386 break; 1387 DELAY(10); 1388 } 1389 1390 if (i == BGE_TIMEOUT) { 1391 printf("bge%d: flow-through queue init failed\n", 1392 sc->bge_unit); 1393 return(ENXIO); 1394 } 1395 1396 /* Initialize the standard RX ring control block */ 1397 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1398 rcb->bge_hostaddr.bge_addr_lo = 1399 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1400 rcb->bge_hostaddr.bge_addr_hi = 1401 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1402 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1403 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1404 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1405 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1406 else 1407 rcb->bge_maxlen_flags = 1408 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1409 if (sc->bge_extram) 1410 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1411 else 1412 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1413 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1414 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1415 1416 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1417 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1418 1419 /* 1420 * Initialize the jumbo RX ring control block 1421 * We set the 'ring disabled' bit in the flags 1422 * field until we're actually ready to start 1423 * using this ring (i.e. once we set the MTU 1424 * high enough to require it). 1425 */ 1426 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1427 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1428 1429 rcb->bge_hostaddr.bge_addr_lo = 1430 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1431 rcb->bge_hostaddr.bge_addr_hi = 1432 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1433 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1434 sc->bge_cdata.bge_rx_jumbo_ring_map, 1435 BUS_DMASYNC_PREREAD); 1436 rcb->bge_maxlen_flags = 1437 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1438 BGE_RCB_FLAG_RING_DISABLED); 1439 if (sc->bge_extram) 1440 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1441 else 1442 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1443 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1444 rcb->bge_hostaddr.bge_addr_hi); 1445 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1446 rcb->bge_hostaddr.bge_addr_lo); 1447 1448 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1449 rcb->bge_maxlen_flags); 1450 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1451 1452 /* Set up dummy disabled mini ring RCB */ 1453 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1454 rcb->bge_maxlen_flags = 1455 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1456 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1457 rcb->bge_maxlen_flags); 1458 } 1459 1460 /* 1461 * Set the BD ring replentish thresholds. The recommended 1462 * values are 1/8th the number of descriptors allocated to 1463 * each ring. 1464 */ 1465 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1466 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1467 1468 /* 1469 * Disable all unused send rings by setting the 'ring disabled' 1470 * bit in the flags field of all the TX send ring control blocks. 1471 * These are located in NIC memory. 1472 */ 1473 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1474 BGE_SEND_RING_RCB); 1475 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1476 vrcb->bge_maxlen_flags = 1477 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1478 vrcb->bge_nicaddr = 0; 1479 vrcb++; 1480 } 1481 1482 /* Configure TX RCB 0 (we use only the first ring) */ 1483 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1484 BGE_SEND_RING_RCB); 1485 vrcb->bge_hostaddr.bge_addr_lo = 1486 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1487 vrcb->bge_hostaddr.bge_addr_hi = 1488 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1489 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1490 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1491 vrcb->bge_maxlen_flags = 1492 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1493 1494 /* Disable all unused RX return rings */ 1495 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1496 BGE_RX_RETURN_RING_RCB); 1497 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1498 vrcb->bge_hostaddr.bge_addr_hi = 0; 1499 vrcb->bge_hostaddr.bge_addr_lo = 0; 1500 vrcb->bge_maxlen_flags = 1501 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1502 BGE_RCB_FLAG_RING_DISABLED); 1503 vrcb->bge_nicaddr = 0; 1504 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1505 (i * (sizeof(u_int64_t))), 0); 1506 vrcb++; 1507 } 1508 1509 /* Initialize RX ring indexes */ 1510 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1511 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1512 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1513 1514 /* 1515 * Set up RX return ring 0 1516 * Note that the NIC address for RX return rings is 0x00000000. 1517 * The return rings live entirely within the host, so the 1518 * nicaddr field in the RCB isn't used. 1519 */ 1520 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1521 BGE_RX_RETURN_RING_RCB); 1522 vrcb->bge_hostaddr.bge_addr_lo = 1523 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1524 vrcb->bge_hostaddr.bge_addr_hi = 1525 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1526 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1527 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1528 vrcb->bge_nicaddr = 0x00000000; 1529 vrcb->bge_maxlen_flags = 1530 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1531 1532 /* Set random backoff seed for TX */ 1533 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1534 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1535 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1536 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1537 BGE_TX_BACKOFF_SEED_MASK); 1538 1539 /* Set inter-packet gap */ 1540 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1541 1542 /* 1543 * Specify which ring to use for packets that don't match 1544 * any RX rules. 1545 */ 1546 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1547 1548 /* 1549 * Configure number of RX lists. One interrupt distribution 1550 * list, sixteen active lists, one bad frames class. 1551 */ 1552 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1553 1554 /* Inialize RX list placement stats mask. */ 1555 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1556 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1557 1558 /* Disable host coalescing until we get it set up */ 1559 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1560 1561 /* Poll to make sure it's shut down. */ 1562 for (i = 0; i < BGE_TIMEOUT; i++) { 1563 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1564 break; 1565 DELAY(10); 1566 } 1567 1568 if (i == BGE_TIMEOUT) { 1569 printf("bge%d: host coalescing engine failed to idle\n", 1570 sc->bge_unit); 1571 return(ENXIO); 1572 } 1573 1574 /* Set up host coalescing defaults */ 1575 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1576 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1577 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1578 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1579 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1580 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1581 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1582 } 1583 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1584 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1585 1586 /* Set up address of statistics block */ 1587 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1588 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1589 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1590 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1591 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1592 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1593 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1594 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1595 } 1596 1597 /* Set up address of status block */ 1598 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1599 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1600 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1601 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1602 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1603 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1604 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1605 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1606 1607 /* Turn on host coalescing state machine */ 1608 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1609 1610 /* Turn on RX BD completion state machine and enable attentions */ 1611 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1612 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1613 1614 /* Turn on RX list placement state machine */ 1615 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1616 1617 /* Turn on RX list selector state machine. */ 1618 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1619 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1620 1621 /* Turn on DMA, clear stats */ 1622 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1623 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1624 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1625 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1626 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1627 1628 /* Set misc. local control, enable interrupts on attentions */ 1629 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1630 1631 #ifdef notdef 1632 /* Assert GPIO pins for PHY reset */ 1633 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1634 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1635 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1636 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1637 #endif 1638 1639 /* Turn on DMA completion state machine */ 1640 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1641 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1642 1643 /* Turn on write DMA state machine */ 1644 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1645 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1646 1647 /* Turn on read DMA state machine */ 1648 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1649 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1650 1651 /* Turn on RX data completion state machine */ 1652 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1653 1654 /* Turn on RX BD initiator state machine */ 1655 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1656 1657 /* Turn on RX data and RX BD initiator state machine */ 1658 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1659 1660 /* Turn on Mbuf cluster free state machine */ 1661 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1662 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1663 1664 /* Turn on send BD completion state machine */ 1665 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1666 1667 /* Turn on send data completion state machine */ 1668 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1669 1670 /* Turn on send data initiator state machine */ 1671 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1672 1673 /* Turn on send BD initiator state machine */ 1674 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1675 1676 /* Turn on send BD selector state machine */ 1677 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1678 1679 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1680 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1681 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1682 1683 /* ack/clear link change events */ 1684 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1685 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1686 BGE_MACSTAT_LINK_CHANGED); 1687 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1688 1689 /* Enable PHY auto polling (for MII/GMII only) */ 1690 if (sc->bge_tbi) { 1691 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1692 } else { 1693 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1694 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1695 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1696 BGE_EVTENB_MI_INTERRUPT); 1697 } 1698 1699 /* Enable link state change attentions. */ 1700 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1701 1702 return(0); 1703 } 1704 1705 /* 1706 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1707 * against our list and return its name if we find a match. Note 1708 * that since the Broadcom controller contains VPD support, we 1709 * can get the device name string from the controller itself instead 1710 * of the compiled-in string. This is a little slow, but it guarantees 1711 * we'll always announce the right product name. 1712 */ 1713 static int 1714 bge_probe(dev) 1715 device_t dev; 1716 { 1717 struct bge_type *t; 1718 struct bge_softc *sc; 1719 char *descbuf; 1720 1721 t = bge_devs; 1722 1723 sc = device_get_softc(dev); 1724 bzero(sc, sizeof(struct bge_softc)); 1725 sc->bge_unit = device_get_unit(dev); 1726 sc->bge_dev = dev; 1727 1728 while(t->bge_name != NULL) { 1729 if ((pci_get_vendor(dev) == t->bge_vid) && 1730 (pci_get_device(dev) == t->bge_did)) { 1731 #ifdef notdef 1732 bge_vpd_read(sc); 1733 device_set_desc(dev, sc->bge_vpd_prodname); 1734 #endif 1735 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1736 if (descbuf == NULL) 1737 return(ENOMEM); 1738 snprintf(descbuf, BGE_DEVDESC_MAX, 1739 "%s, ASIC rev. %#04x", t->bge_name, 1740 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1741 device_set_desc_copy(dev, descbuf); 1742 if (pci_get_subvendor(dev) == DELL_VENDORID) 1743 sc->bge_no_3_led = 1; 1744 free(descbuf, M_TEMP); 1745 return(0); 1746 } 1747 t++; 1748 } 1749 1750 return(ENXIO); 1751 } 1752 1753 static void 1754 bge_dma_free(sc) 1755 struct bge_softc *sc; 1756 { 1757 int i; 1758 1759 1760 /* Destroy DMA maps for RX buffers */ 1761 1762 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1763 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1764 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1765 sc->bge_cdata.bge_rx_std_dmamap[i]); 1766 } 1767 1768 /* Destroy DMA maps for jumbo RX buffers */ 1769 1770 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1771 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1772 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1773 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1774 } 1775 1776 /* Destroy DMA maps for TX buffers */ 1777 1778 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1779 if (sc->bge_cdata.bge_tx_dmamap[i]) 1780 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1781 sc->bge_cdata.bge_tx_dmamap[i]); 1782 } 1783 1784 if (sc->bge_cdata.bge_mtag) 1785 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1786 1787 1788 /* Destroy standard RX ring */ 1789 1790 if (sc->bge_ldata.bge_rx_std_ring) 1791 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1792 sc->bge_ldata.bge_rx_std_ring, 1793 sc->bge_cdata.bge_rx_std_ring_map); 1794 1795 if (sc->bge_cdata.bge_rx_std_ring_map) { 1796 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1797 sc->bge_cdata.bge_rx_std_ring_map); 1798 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1799 sc->bge_cdata.bge_rx_std_ring_map); 1800 } 1801 1802 if (sc->bge_cdata.bge_rx_std_ring_tag) 1803 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1804 1805 /* Destroy jumbo RX ring */ 1806 1807 if (sc->bge_ldata.bge_rx_jumbo_ring) 1808 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1809 sc->bge_ldata.bge_rx_jumbo_ring, 1810 sc->bge_cdata.bge_rx_jumbo_ring_map); 1811 1812 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1813 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1814 sc->bge_cdata.bge_rx_jumbo_ring_map); 1815 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1816 sc->bge_cdata.bge_rx_jumbo_ring_map); 1817 } 1818 1819 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1820 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1821 1822 /* Destroy RX return ring */ 1823 1824 if (sc->bge_ldata.bge_rx_return_ring) 1825 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1826 sc->bge_ldata.bge_rx_return_ring, 1827 sc->bge_cdata.bge_rx_return_ring_map); 1828 1829 if (sc->bge_cdata.bge_rx_return_ring_map) { 1830 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1831 sc->bge_cdata.bge_rx_return_ring_map); 1832 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1833 sc->bge_cdata.bge_rx_return_ring_map); 1834 } 1835 1836 if (sc->bge_cdata.bge_rx_return_ring_tag) 1837 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1838 1839 /* Destroy TX ring */ 1840 1841 if (sc->bge_ldata.bge_tx_ring) 1842 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1843 sc->bge_ldata.bge_tx_ring, 1844 sc->bge_cdata.bge_tx_ring_map); 1845 1846 if (sc->bge_cdata.bge_tx_ring_map) { 1847 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1848 sc->bge_cdata.bge_tx_ring_map); 1849 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1850 sc->bge_cdata.bge_tx_ring_map); 1851 } 1852 1853 if (sc->bge_cdata.bge_tx_ring_tag) 1854 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1855 1856 /* Destroy status block */ 1857 1858 if (sc->bge_ldata.bge_status_block) 1859 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1860 sc->bge_ldata.bge_status_block, 1861 sc->bge_cdata.bge_status_map); 1862 1863 if (sc->bge_cdata.bge_status_map) { 1864 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1865 sc->bge_cdata.bge_status_map); 1866 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1867 sc->bge_cdata.bge_status_map); 1868 } 1869 1870 if (sc->bge_cdata.bge_status_tag) 1871 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1872 1873 /* Destroy statistics block */ 1874 1875 if (sc->bge_ldata.bge_stats) 1876 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1877 sc->bge_ldata.bge_stats, 1878 sc->bge_cdata.bge_stats_map); 1879 1880 if (sc->bge_cdata.bge_stats_map) { 1881 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1882 sc->bge_cdata.bge_stats_map); 1883 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1884 sc->bge_cdata.bge_stats_map); 1885 } 1886 1887 if (sc->bge_cdata.bge_stats_tag) 1888 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1889 1890 /* Destroy the parent tag */ 1891 1892 if (sc->bge_cdata.bge_parent_tag) 1893 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1894 1895 return; 1896 } 1897 1898 static int 1899 bge_dma_alloc(dev) 1900 device_t dev; 1901 { 1902 struct bge_softc *sc; 1903 int nseg, i, error; 1904 struct bge_dmamap_arg ctx; 1905 1906 sc = device_get_softc(dev); 1907 1908 /* 1909 * Allocate the parent bus DMA tag appropriate for PCI. 1910 */ 1911 #define BGE_NSEG_NEW 32 1912 error = bus_dma_tag_create(NULL, /* parent */ 1913 PAGE_SIZE, 0, /* alignment, boundary */ 1914 BUS_SPACE_MAXADDR, /* lowaddr */ 1915 BUS_SPACE_MAXADDR_32BIT,/* highaddr */ 1916 NULL, NULL, /* filter, filterarg */ 1917 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1918 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1919 BUS_DMA_ALLOCNOW, /* flags */ 1920 NULL, NULL, /* lockfunc, lockarg */ 1921 &sc->bge_cdata.bge_parent_tag); 1922 1923 /* 1924 * Create tag for RX mbufs. 1925 */ 1926 nseg = 32; 1927 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, ETHER_ALIGN, 1928 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1929 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1930 &sc->bge_cdata.bge_mtag); 1931 1932 if (error) { 1933 device_printf(dev, "could not allocate dma tag\n"); 1934 return (ENOMEM); 1935 } 1936 1937 /* Create DMA maps for RX buffers */ 1938 1939 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1940 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1941 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1942 if (error) { 1943 device_printf(dev, "can't create DMA map for RX\n"); 1944 return(ENOMEM); 1945 } 1946 } 1947 1948 /* Create DMA maps for TX buffers */ 1949 1950 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1951 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1952 &sc->bge_cdata.bge_tx_dmamap[i]); 1953 if (error) { 1954 device_printf(dev, "can't create DMA map for RX\n"); 1955 return(ENOMEM); 1956 } 1957 } 1958 1959 /* Create tag for standard RX ring */ 1960 1961 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1962 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1963 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1964 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1965 1966 if (error) { 1967 device_printf(dev, "could not allocate dma tag\n"); 1968 return (ENOMEM); 1969 } 1970 1971 /* Allocate DMA'able memory for standard RX ring */ 1972 1973 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1974 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1975 &sc->bge_cdata.bge_rx_std_ring_map); 1976 if (error) 1977 return (ENOMEM); 1978 1979 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1980 1981 /* Load the address of the standard RX ring */ 1982 1983 ctx.bge_maxsegs = 1; 1984 ctx.sc = sc; 1985 1986 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1987 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1988 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1989 1990 if (error) 1991 return (ENOMEM); 1992 1993 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1994 1995 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1996 1997 /* 1998 * Create tag for jumbo mbufs. 1999 * This is really a bit of a kludge. We allocate a special 2000 * jumbo buffer pool which (thanks to the way our DMA 2001 * memory allocation works) will consist of contiguous 2002 * pages. This means that even though a jumbo buffer might 2003 * be larger than a page size, we don't really need to 2004 * map it into more than one DMA segment. However, the 2005 * default mbuf tag will result in multi-segment mappings, 2006 * so we have to create a special jumbo mbuf tag that 2007 * lets us get away with mapping the jumbo buffers as 2008 * a single segment. I think eventually the driver should 2009 * be changed so that it uses ordinary mbufs and cluster 2010 * buffers, i.e. jumbo frames can span multiple DMA 2011 * descriptors. But that's a project for another day. 2012 */ 2013 2014 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2015 ETHER_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2016 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2017 &sc->bge_cdata.bge_mtag_jumbo); 2018 2019 if (error) { 2020 device_printf(dev, "could not allocate dma tag\n"); 2021 return (ENOMEM); 2022 } 2023 2024 /* Create tag for jumbo RX ring */ 2025 2026 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2027 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2028 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2029 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2030 2031 if (error) { 2032 device_printf(dev, "could not allocate dma tag\n"); 2033 return (ENOMEM); 2034 } 2035 2036 /* Allocate DMA'able memory for jumbo RX ring */ 2037 2038 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2039 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2040 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2041 if (error) 2042 return (ENOMEM); 2043 2044 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2045 BGE_JUMBO_RX_RING_SZ); 2046 2047 /* Load the address of the jumbo RX ring */ 2048 2049 ctx.bge_maxsegs = 1; 2050 ctx.sc = sc; 2051 2052 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2053 sc->bge_cdata.bge_rx_jumbo_ring_map, 2054 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2055 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2056 2057 if (error) 2058 return (ENOMEM); 2059 2060 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2061 2062 /* Create DMA maps for jumbo RX buffers */ 2063 2064 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2065 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2066 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2067 if (error) { 2068 device_printf(dev, 2069 "can't create DMA map for RX\n"); 2070 return(ENOMEM); 2071 } 2072 } 2073 2074 } 2075 2076 /* Create tag for RX return ring */ 2077 2078 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2079 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2080 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2081 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2082 2083 if (error) { 2084 device_printf(dev, "could not allocate dma tag\n"); 2085 return (ENOMEM); 2086 } 2087 2088 /* Allocate DMA'able memory for RX return ring */ 2089 2090 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2091 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2092 &sc->bge_cdata.bge_rx_return_ring_map); 2093 if (error) 2094 return (ENOMEM); 2095 2096 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2097 BGE_RX_RTN_RING_SZ(sc)); 2098 2099 /* Load the address of the RX return ring */ 2100 2101 ctx.bge_maxsegs = 1; 2102 ctx.sc = sc; 2103 2104 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2105 sc->bge_cdata.bge_rx_return_ring_map, 2106 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2107 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2108 2109 if (error) 2110 return (ENOMEM); 2111 2112 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2113 2114 /* Create tag for TX ring */ 2115 2116 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2117 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2118 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2119 &sc->bge_cdata.bge_tx_ring_tag); 2120 2121 if (error) { 2122 device_printf(dev, "could not allocate dma tag\n"); 2123 return (ENOMEM); 2124 } 2125 2126 /* Allocate DMA'able memory for TX ring */ 2127 2128 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2129 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2130 &sc->bge_cdata.bge_tx_ring_map); 2131 if (error) 2132 return (ENOMEM); 2133 2134 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2135 2136 /* Load the address of the TX ring */ 2137 2138 ctx.bge_maxsegs = 1; 2139 ctx.sc = sc; 2140 2141 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2142 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2143 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2144 2145 if (error) 2146 return (ENOMEM); 2147 2148 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2149 2150 /* Create tag for status block */ 2151 2152 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2153 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2154 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2155 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2156 2157 if (error) { 2158 device_printf(dev, "could not allocate dma tag\n"); 2159 return (ENOMEM); 2160 } 2161 2162 /* Allocate DMA'able memory for status block */ 2163 2164 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2165 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2166 &sc->bge_cdata.bge_status_map); 2167 if (error) 2168 return (ENOMEM); 2169 2170 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2171 2172 /* Load the address of the status block */ 2173 2174 ctx.sc = sc; 2175 ctx.bge_maxsegs = 1; 2176 2177 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2178 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2179 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2180 2181 if (error) 2182 return (ENOMEM); 2183 2184 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2185 2186 /* Create tag for statistics block */ 2187 2188 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2189 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2190 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2191 &sc->bge_cdata.bge_stats_tag); 2192 2193 if (error) { 2194 device_printf(dev, "could not allocate dma tag\n"); 2195 return (ENOMEM); 2196 } 2197 2198 /* Allocate DMA'able memory for statistics block */ 2199 2200 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2201 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2202 &sc->bge_cdata.bge_stats_map); 2203 if (error) 2204 return (ENOMEM); 2205 2206 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2207 2208 /* Load the address of the statstics block */ 2209 2210 ctx.sc = sc; 2211 ctx.bge_maxsegs = 1; 2212 2213 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2214 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2215 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2216 2217 if (error) 2218 return (ENOMEM); 2219 2220 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2221 2222 return(0); 2223 } 2224 2225 static int 2226 bge_attach(dev) 2227 device_t dev; 2228 { 2229 int s; 2230 struct ifnet *ifp; 2231 struct bge_softc *sc; 2232 u_int32_t hwcfg = 0; 2233 u_int32_t mac_addr = 0; 2234 int unit, error = 0, rid; 2235 2236 s = splimp(); 2237 2238 sc = device_get_softc(dev); 2239 unit = device_get_unit(dev); 2240 sc->bge_dev = dev; 2241 sc->bge_unit = unit; 2242 2243 /* 2244 * Map control/status registers. 2245 */ 2246 pci_enable_busmaster(dev); 2247 2248 rid = BGE_PCI_BAR0; 2249 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2250 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2251 2252 if (sc->bge_res == NULL) { 2253 printf ("bge%d: couldn't map memory\n", unit); 2254 error = ENXIO; 2255 goto fail; 2256 } 2257 2258 sc->bge_btag = rman_get_bustag(sc->bge_res); 2259 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2260 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2261 2262 /* Allocate interrupt */ 2263 rid = 0; 2264 2265 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2266 RF_SHAREABLE | RF_ACTIVE); 2267 2268 if (sc->bge_irq == NULL) { 2269 printf("bge%d: couldn't map interrupt\n", unit); 2270 error = ENXIO; 2271 goto fail; 2272 } 2273 2274 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 2275 bge_intr, sc, &sc->bge_intrhand); 2276 2277 if (error) { 2278 bge_release_resources(sc); 2279 printf("bge%d: couldn't set up irq\n", unit); 2280 goto fail; 2281 } 2282 2283 sc->bge_unit = unit; 2284 2285 /* Try to reset the chip. */ 2286 bge_reset(sc); 2287 2288 if (bge_chipinit(sc)) { 2289 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2290 bge_release_resources(sc); 2291 error = ENXIO; 2292 goto fail; 2293 } 2294 2295 /* 2296 * Get station address from the EEPROM. 2297 */ 2298 mac_addr = bge_readmem_ind(sc, 0x0c14); 2299 if ((mac_addr >> 16) == 0x484b) { 2300 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2301 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2302 mac_addr = bge_readmem_ind(sc, 0x0c18); 2303 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2304 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2305 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2306 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2307 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2308 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2309 printf("bge%d: failed to read station address\n", unit); 2310 bge_release_resources(sc); 2311 error = ENXIO; 2312 goto fail; 2313 } 2314 2315 /* 2316 * A Broadcom chip was detected. Inform the world. 2317 */ 2318 printf("bge%d: Ethernet address: %6D\n", unit, 2319 sc->arpcom.ac_enaddr, ":"); 2320 2321 /* Save ASIC rev. */ 2322 2323 sc->bge_chipid = 2324 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2325 BGE_PCIMISCCTL_ASICREV; 2326 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2327 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2328 2329 /* 5705 limits RX return ring to 512 entries. */ 2330 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2331 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2332 else 2333 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2334 2335 if (bge_dma_alloc(dev)) { 2336 printf ("bge%d: failed to allocate DMA resources\n", 2337 sc->bge_unit); 2338 bge_release_resources(sc); 2339 error = ENXIO; 2340 goto fail; 2341 } 2342 2343 /* 2344 * Try to allocate memory for jumbo buffers. 2345 * The 5705 does not appear to support jumbo frames. 2346 */ 2347 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2348 if (bge_alloc_jumbo_mem(sc)) { 2349 printf("bge%d: jumbo buffer allocation " 2350 "failed\n", sc->bge_unit); 2351 bge_release_resources(sc); 2352 error = ENXIO; 2353 goto fail; 2354 } 2355 } 2356 2357 /* Set default tuneable values. */ 2358 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2359 sc->bge_rx_coal_ticks = 150; 2360 sc->bge_tx_coal_ticks = 150; 2361 sc->bge_rx_max_coal_bds = 64; 2362 sc->bge_tx_max_coal_bds = 128; 2363 2364 /* Set up ifnet structure */ 2365 ifp = &sc->arpcom.ac_if; 2366 ifp->if_softc = sc; 2367 ifp->if_unit = sc->bge_unit; 2368 ifp->if_name = "bge"; 2369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2370 ifp->if_ioctl = bge_ioctl; 2371 ifp->if_output = ether_output; 2372 ifp->if_start = bge_start; 2373 ifp->if_watchdog = bge_watchdog; 2374 ifp->if_init = bge_init; 2375 ifp->if_mtu = ETHERMTU; 2376 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 2377 ifp->if_hwassist = BGE_CSUM_FEATURES; 2378 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2379 IFCAP_VLAN_MTU; 2380 ifp->if_capenable = ifp->if_capabilities; 2381 2382 /* 2383 * Figure out what sort of media we have by checking the 2384 * hardware config word in the first 32k of NIC internal memory, 2385 * or fall back to examining the EEPROM if necessary. 2386 * Note: on some BCM5700 cards, this value appears to be unset. 2387 * If that's the case, we have to rely on identifying the NIC 2388 * by its PCI subsystem ID, as we do below for the SysKonnect 2389 * SK-9D41. 2390 */ 2391 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2392 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2393 else { 2394 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2395 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2396 hwcfg = ntohl(hwcfg); 2397 } 2398 2399 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2400 sc->bge_tbi = 1; 2401 2402 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2403 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2404 sc->bge_tbi = 1; 2405 2406 if (sc->bge_tbi) { 2407 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2408 bge_ifmedia_upd, bge_ifmedia_sts); 2409 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2410 ifmedia_add(&sc->bge_ifmedia, 2411 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2412 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2413 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2414 } else { 2415 /* 2416 * Do transceiver setup. 2417 */ 2418 if (mii_phy_probe(dev, &sc->bge_miibus, 2419 bge_ifmedia_upd, bge_ifmedia_sts)) { 2420 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2421 bge_release_resources(sc); 2422 bge_free_jumbo_mem(sc); 2423 error = ENXIO; 2424 goto fail; 2425 } 2426 } 2427 2428 /* 2429 * When using the BCM5701 in PCI-X mode, data corruption has 2430 * been observed in the first few bytes of some received packets. 2431 * Aligning the packet buffer in memory eliminates the corruption. 2432 * Unfortunately, this misaligns the packet payloads. On platforms 2433 * which do not support unaligned accesses, we will realign the 2434 * payloads by copying the received packets. 2435 */ 2436 switch (sc->bge_chipid) { 2437 case BGE_CHIPID_BCM5701_A0: 2438 case BGE_CHIPID_BCM5701_B0: 2439 case BGE_CHIPID_BCM5701_B2: 2440 case BGE_CHIPID_BCM5701_B5: 2441 /* If in PCI-X mode, work around the alignment bug. */ 2442 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2443 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2444 BGE_PCISTATE_PCI_BUSSPEED) 2445 sc->bge_rx_alignment_bug = 1; 2446 break; 2447 } 2448 2449 /* 2450 * Call MI attach routine. 2451 */ 2452 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2453 callout_handle_init(&sc->bge_stat_ch); 2454 2455 fail: 2456 splx(s); 2457 2458 return(error); 2459 } 2460 2461 static int 2462 bge_detach(dev) 2463 device_t dev; 2464 { 2465 struct bge_softc *sc; 2466 struct ifnet *ifp; 2467 int s; 2468 2469 s = splimp(); 2470 2471 sc = device_get_softc(dev); 2472 ifp = &sc->arpcom.ac_if; 2473 2474 ether_ifdetach(ifp); 2475 bge_stop(sc); 2476 bge_reset(sc); 2477 2478 if (sc->bge_tbi) { 2479 ifmedia_removeall(&sc->bge_ifmedia); 2480 } else { 2481 bus_generic_detach(dev); 2482 device_delete_child(dev, sc->bge_miibus); 2483 } 2484 2485 bge_release_resources(sc); 2486 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2487 bge_free_jumbo_mem(sc); 2488 2489 splx(s); 2490 2491 return(0); 2492 } 2493 2494 static void 2495 bge_release_resources(sc) 2496 struct bge_softc *sc; 2497 { 2498 device_t dev; 2499 2500 dev = sc->bge_dev; 2501 2502 if (sc->bge_vpd_prodname != NULL) 2503 free(sc->bge_vpd_prodname, M_DEVBUF); 2504 2505 if (sc->bge_vpd_readonly != NULL) 2506 free(sc->bge_vpd_readonly, M_DEVBUF); 2507 2508 if (sc->bge_intrhand != NULL) 2509 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2510 2511 if (sc->bge_irq != NULL) 2512 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2513 2514 if (sc->bge_res != NULL) 2515 bus_release_resource(dev, SYS_RES_MEMORY, 2516 BGE_PCI_BAR0, sc->bge_res); 2517 2518 bge_dma_free(sc); 2519 2520 return; 2521 } 2522 2523 static void 2524 bge_reset(sc) 2525 struct bge_softc *sc; 2526 { 2527 device_t dev; 2528 u_int32_t cachesize, command, pcistate; 2529 int i, val = 0; 2530 2531 dev = sc->bge_dev; 2532 2533 /* Save some important PCI state. */ 2534 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2535 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2536 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2537 2538 pci_write_config(dev, BGE_PCI_MISC_CTL, 2539 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2540 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2541 2542 /* Issue global reset */ 2543 bge_writereg_ind(sc, BGE_MISC_CFG, 2544 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2545 2546 DELAY(1000); 2547 2548 /* Reset some of the PCI state that got zapped by reset */ 2549 pci_write_config(dev, BGE_PCI_MISC_CTL, 2550 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2551 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2552 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2553 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2554 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2555 2556 /* 2557 * Prevent PXE restart: write a magic number to the 2558 * general communications memory at 0xB50. 2559 */ 2560 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2561 /* 2562 * Poll the value location we just wrote until 2563 * we see the 1's complement of the magic number. 2564 * This indicates that the firmware initialization 2565 * is complete. 2566 */ 2567 for (i = 0; i < BGE_TIMEOUT; i++) { 2568 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2569 if (val == ~BGE_MAGIC_NUMBER) 2570 break; 2571 DELAY(10); 2572 } 2573 2574 if (i == BGE_TIMEOUT) { 2575 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2576 return; 2577 } 2578 2579 /* 2580 * XXX Wait for the value of the PCISTATE register to 2581 * return to its original pre-reset state. This is a 2582 * fairly good indicator of reset completion. If we don't 2583 * wait for the reset to fully complete, trying to read 2584 * from the device's non-PCI registers may yield garbage 2585 * results. 2586 */ 2587 for (i = 0; i < BGE_TIMEOUT; i++) { 2588 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2589 break; 2590 DELAY(10); 2591 } 2592 2593 /* Enable memory arbiter. */ 2594 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2595 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2596 2597 /* Fix up byte swapping */ 2598 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2599 BGE_MODECTL_BYTESWAP_DATA); 2600 2601 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2602 2603 DELAY(10000); 2604 2605 return; 2606 } 2607 2608 /* 2609 * Frame reception handling. This is called if there's a frame 2610 * on the receive return list. 2611 * 2612 * Note: we have to be able to handle two possibilities here: 2613 * 1) the frame is from the jumbo recieve ring 2614 * 2) the frame is from the standard receive ring 2615 */ 2616 2617 static void 2618 bge_rxeof(sc) 2619 struct bge_softc *sc; 2620 { 2621 struct ifnet *ifp; 2622 int stdcnt = 0, jumbocnt = 0; 2623 2624 ifp = &sc->arpcom.ac_if; 2625 2626 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2627 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2628 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2629 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2630 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2631 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2632 sc->bge_cdata.bge_rx_jumbo_ring_map, 2633 BUS_DMASYNC_POSTREAD); 2634 } 2635 2636 while(sc->bge_rx_saved_considx != 2637 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2638 struct bge_rx_bd *cur_rx; 2639 u_int32_t rxidx; 2640 struct ether_header *eh; 2641 struct mbuf *m = NULL; 2642 u_int16_t vlan_tag = 0; 2643 int have_tag = 0; 2644 2645 cur_rx = 2646 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2647 2648 rxidx = cur_rx->bge_idx; 2649 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2650 2651 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2652 have_tag = 1; 2653 vlan_tag = cur_rx->bge_vlan_tag; 2654 } 2655 2656 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2657 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2658 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2659 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2660 BUS_DMASYNC_POSTREAD); 2661 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2662 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2663 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2664 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2665 jumbocnt++; 2666 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2667 ifp->if_ierrors++; 2668 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2669 continue; 2670 } 2671 if (bge_newbuf_jumbo(sc, 2672 sc->bge_jumbo, NULL) == ENOBUFS) { 2673 ifp->if_ierrors++; 2674 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2675 continue; 2676 } 2677 } else { 2678 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2679 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2680 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2681 BUS_DMASYNC_POSTREAD); 2682 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2683 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2684 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2685 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2686 stdcnt++; 2687 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2688 ifp->if_ierrors++; 2689 bge_newbuf_std(sc, sc->bge_std, m); 2690 continue; 2691 } 2692 if (bge_newbuf_std(sc, sc->bge_std, 2693 NULL) == ENOBUFS) { 2694 ifp->if_ierrors++; 2695 bge_newbuf_std(sc, sc->bge_std, m); 2696 continue; 2697 } 2698 } 2699 2700 ifp->if_ipackets++; 2701 #ifndef __i386__ 2702 /* 2703 * The i386 allows unaligned accesses, but for other 2704 * platforms we must make sure the payload is aligned. 2705 */ 2706 if (sc->bge_rx_alignment_bug) { 2707 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2708 cur_rx->bge_len); 2709 m->m_data += ETHER_ALIGN; 2710 } 2711 #endif 2712 eh = mtod(m, struct ether_header *); 2713 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2714 m->m_pkthdr.rcvif = ifp; 2715 2716 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2717 if (ifp->if_hwassist) { 2718 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2719 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2720 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2721 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2722 m->m_pkthdr.csum_data = 2723 cur_rx->bge_tcp_udp_csum; 2724 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2725 } 2726 } 2727 #endif 2728 2729 /* 2730 * If we received a packet with a vlan tag, 2731 * attach that information to the packet. 2732 */ 2733 if (have_tag) 2734 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2735 2736 (*ifp->if_input)(ifp, m); 2737 } 2738 2739 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2740 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2741 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2742 sc->bge_cdata.bge_rx_std_ring_map, 2743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2744 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2745 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2746 sc->bge_cdata.bge_rx_jumbo_ring_map, 2747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2748 } 2749 2750 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2751 if (stdcnt) 2752 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2753 if (jumbocnt) 2754 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2755 2756 return; 2757 } 2758 2759 static void 2760 bge_txeof(sc) 2761 struct bge_softc *sc; 2762 { 2763 struct bge_tx_bd *cur_tx = NULL; 2764 struct ifnet *ifp; 2765 2766 ifp = &sc->arpcom.ac_if; 2767 2768 /* 2769 * Go through our tx ring and free mbufs for those 2770 * frames that have been sent. 2771 */ 2772 while (sc->bge_tx_saved_considx != 2773 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2774 u_int32_t idx = 0; 2775 2776 idx = sc->bge_tx_saved_considx; 2777 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2778 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2779 ifp->if_opackets++; 2780 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2781 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2782 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2783 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2784 sc->bge_cdata.bge_tx_dmamap[idx]); 2785 } 2786 sc->bge_txcnt--; 2787 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2788 ifp->if_timer = 0; 2789 } 2790 2791 if (cur_tx != NULL) 2792 ifp->if_flags &= ~IFF_OACTIVE; 2793 2794 return; 2795 } 2796 2797 static void 2798 bge_intr(xsc) 2799 void *xsc; 2800 { 2801 struct bge_softc *sc; 2802 struct ifnet *ifp; 2803 u_int32_t statusword; 2804 u_int32_t status; 2805 2806 sc = xsc; 2807 ifp = &sc->arpcom.ac_if; 2808 2809 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2810 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2811 2812 statusword = 2813 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2814 2815 #ifdef notdef 2816 /* Avoid this for now -- checking this register is expensive. */ 2817 /* Make sure this is really our interrupt. */ 2818 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2819 return; 2820 #endif 2821 /* Ack interrupt and stop others from occuring. */ 2822 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2823 2824 /* 2825 * Process link state changes. 2826 * Grrr. The link status word in the status block does 2827 * not work correctly on the BCM5700 rev AX and BX chips, 2828 * according to all avaibable information. Hence, we have 2829 * to enable MII interrupts in order to properly obtain 2830 * async link changes. Unfortunately, this also means that 2831 * we have to read the MAC status register to detect link 2832 * changes, thereby adding an additional register access to 2833 * the interrupt handler. 2834 */ 2835 2836 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2837 2838 status = CSR_READ_4(sc, BGE_MAC_STS); 2839 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2840 sc->bge_link = 0; 2841 untimeout(bge_tick, sc, sc->bge_stat_ch); 2842 bge_tick(sc); 2843 /* Clear the interrupt */ 2844 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2845 BGE_EVTENB_MI_INTERRUPT); 2846 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2847 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2848 BRGPHY_INTRS); 2849 } 2850 } else { 2851 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2852 /* 2853 * Sometimes PCS encoding errors are detected in 2854 * TBI mode (on fiber NICs), and for some reason 2855 * the chip will signal them as link changes. 2856 * If we get a link change event, but the 'PCS 2857 * encoding error' bit in the MAC status register 2858 * is set, don't bother doing a link check. 2859 * This avoids spurious "gigabit link up" messages 2860 * that sometimes appear on fiber NICs during 2861 * periods of heavy traffic. (There should be no 2862 * effect on copper NICs.) 2863 */ 2864 status = CSR_READ_4(sc, BGE_MAC_STS); 2865 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2866 BGE_MACSTAT_MI_COMPLETE))) { 2867 sc->bge_link = 0; 2868 untimeout(bge_tick, sc, sc->bge_stat_ch); 2869 bge_tick(sc); 2870 } 2871 /* Clear the interrupt */ 2872 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2873 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2874 BGE_MACSTAT_LINK_CHANGED); 2875 2876 /* Force flush the status block cached by PCI bridge */ 2877 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2878 } 2879 } 2880 2881 if (ifp->if_flags & IFF_RUNNING) { 2882 /* Check RX return ring producer/consumer */ 2883 bge_rxeof(sc); 2884 2885 /* Check TX ring producer/consumer */ 2886 bge_txeof(sc); 2887 } 2888 2889 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2890 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2891 2892 bge_handle_events(sc); 2893 2894 /* Re-enable interrupts. */ 2895 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2896 2897 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2898 bge_start(ifp); 2899 2900 return; 2901 } 2902 2903 static void 2904 bge_tick(xsc) 2905 void *xsc; 2906 { 2907 struct bge_softc *sc; 2908 struct mii_data *mii = NULL; 2909 struct ifmedia *ifm = NULL; 2910 struct ifnet *ifp; 2911 int s; 2912 2913 sc = xsc; 2914 ifp = &sc->arpcom.ac_if; 2915 2916 s = splimp(); 2917 2918 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2919 bge_stats_update_regs(sc); 2920 else 2921 bge_stats_update(sc); 2922 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2923 if (sc->bge_link) { 2924 splx(s); 2925 return; 2926 } 2927 2928 if (sc->bge_tbi) { 2929 ifm = &sc->bge_ifmedia; 2930 if (CSR_READ_4(sc, BGE_MAC_STS) & 2931 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2932 sc->bge_link++; 2933 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2934 printf("bge%d: gigabit link up\n", sc->bge_unit); 2935 if (ifp->if_snd.ifq_head != NULL) 2936 bge_start(ifp); 2937 } 2938 splx(s); 2939 return; 2940 } 2941 2942 mii = device_get_softc(sc->bge_miibus); 2943 mii_tick(mii); 2944 2945 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2946 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2947 sc->bge_link++; 2948 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2949 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2950 printf("bge%d: gigabit link up\n", 2951 sc->bge_unit); 2952 if (ifp->if_snd.ifq_head != NULL) 2953 bge_start(ifp); 2954 } 2955 2956 splx(s); 2957 2958 return; 2959 } 2960 2961 static void 2962 bge_stats_update_regs(sc) 2963 struct bge_softc *sc; 2964 { 2965 struct ifnet *ifp; 2966 struct bge_mac_stats_regs stats; 2967 u_int32_t *s; 2968 int i; 2969 2970 ifp = &sc->arpcom.ac_if; 2971 2972 s = (u_int32_t *)&stats; 2973 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2974 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2975 s++; 2976 } 2977 2978 ifp->if_collisions += 2979 (stats.dot3StatsSingleCollisionFrames + 2980 stats.dot3StatsMultipleCollisionFrames + 2981 stats.dot3StatsExcessiveCollisions + 2982 stats.dot3StatsLateCollisions) - 2983 ifp->if_collisions; 2984 2985 return; 2986 } 2987 2988 static void 2989 bge_stats_update(sc) 2990 struct bge_softc *sc; 2991 { 2992 struct ifnet *ifp; 2993 struct bge_stats *stats; 2994 2995 ifp = &sc->arpcom.ac_if; 2996 2997 stats = (struct bge_stats *)(sc->bge_vhandle + 2998 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2999 3000 ifp->if_collisions += 3001 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3002 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3003 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3004 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3005 ifp->if_collisions; 3006 3007 #ifdef notdef 3008 ifp->if_collisions += 3009 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3010 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3011 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3012 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3013 ifp->if_collisions; 3014 #endif 3015 3016 return; 3017 } 3018 3019 /* 3020 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3021 * pointers to descriptors. 3022 */ 3023 static int 3024 bge_encap(sc, m_head, txidx) 3025 struct bge_softc *sc; 3026 struct mbuf *m_head; 3027 u_int32_t *txidx; 3028 { 3029 struct bge_tx_bd *f = NULL; 3030 u_int16_t csum_flags = 0; 3031 struct m_tag *mtag; 3032 struct bge_dmamap_arg ctx; 3033 bus_dmamap_t map; 3034 int error; 3035 3036 3037 if (m_head->m_pkthdr.csum_flags) { 3038 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3039 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3040 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3041 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3042 if (m_head->m_flags & M_LASTFRAG) 3043 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3044 else if (m_head->m_flags & M_FRAG) 3045 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3046 } 3047 3048 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3049 3050 ctx.sc = sc; 3051 ctx.bge_idx = *txidx; 3052 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3053 ctx.bge_flags = csum_flags; 3054 /* 3055 * Sanity check: avoid coming within 16 descriptors 3056 * of the end of the ring. 3057 */ 3058 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3059 3060 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3061 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3062 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3063 3064 if (error || ctx.bge_maxsegs == 0 /*|| 3065 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3066 return (ENOBUFS); 3067 3068 /* 3069 * Insure that the map for this transmission 3070 * is placed at the array index of the last descriptor 3071 * in this chain. 3072 */ 3073 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3074 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3075 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3076 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3077 sc->bge_txcnt += ctx.bge_maxsegs; 3078 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3079 if (mtag != NULL) { 3080 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3081 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3082 } else { 3083 f->bge_vlan_tag = 0; 3084 } 3085 3086 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3087 *txidx = ctx.bge_idx; 3088 3089 return(0); 3090 } 3091 3092 /* 3093 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3094 * to the mbuf data regions directly in the transmit descriptors. 3095 */ 3096 static void 3097 bge_start(ifp) 3098 struct ifnet *ifp; 3099 { 3100 struct bge_softc *sc; 3101 struct mbuf *m_head = NULL; 3102 u_int32_t prodidx = 0; 3103 3104 sc = ifp->if_softc; 3105 3106 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3107 return; 3108 3109 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3110 3111 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3112 IF_DEQUEUE(&ifp->if_snd, m_head); 3113 if (m_head == NULL) 3114 break; 3115 3116 /* 3117 * XXX 3118 * safety overkill. If this is a fragmented packet chain 3119 * with delayed TCP/UDP checksums, then only encapsulate 3120 * it if we have enough descriptors to handle the entire 3121 * chain at once. 3122 * (paranoia -- may not actually be needed) 3123 */ 3124 if (m_head->m_flags & M_FIRSTFRAG && 3125 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3126 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3127 m_head->m_pkthdr.csum_data + 16) { 3128 IF_PREPEND(&ifp->if_snd, m_head); 3129 ifp->if_flags |= IFF_OACTIVE; 3130 break; 3131 } 3132 } 3133 3134 /* 3135 * Pack the data into the transmit ring. If we 3136 * don't have room, set the OACTIVE flag and wait 3137 * for the NIC to drain the ring. 3138 */ 3139 if (bge_encap(sc, m_head, &prodidx)) { 3140 IF_PREPEND(&ifp->if_snd, m_head); 3141 ifp->if_flags |= IFF_OACTIVE; 3142 break; 3143 } 3144 3145 /* 3146 * If there's a BPF listener, bounce a copy of this frame 3147 * to him. 3148 */ 3149 BPF_MTAP(ifp, m_head); 3150 } 3151 3152 /* Transmit */ 3153 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3154 /* 5700 b2 errata */ 3155 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3156 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3157 3158 /* 3159 * Set a timeout in case the chip goes out to lunch. 3160 */ 3161 ifp->if_timer = 5; 3162 3163 return; 3164 } 3165 3166 static void 3167 bge_init(xsc) 3168 void *xsc; 3169 { 3170 struct bge_softc *sc = xsc; 3171 struct ifnet *ifp; 3172 u_int16_t *m; 3173 int s; 3174 3175 s = splimp(); 3176 3177 ifp = &sc->arpcom.ac_if; 3178 3179 if (ifp->if_flags & IFF_RUNNING) { 3180 splx(s); 3181 return; 3182 } 3183 3184 /* Cancel pending I/O and flush buffers. */ 3185 bge_stop(sc); 3186 bge_reset(sc); 3187 bge_chipinit(sc); 3188 3189 /* 3190 * Init the various state machines, ring 3191 * control blocks and firmware. 3192 */ 3193 if (bge_blockinit(sc)) { 3194 printf("bge%d: initialization failure\n", sc->bge_unit); 3195 splx(s); 3196 return; 3197 } 3198 3199 ifp = &sc->arpcom.ac_if; 3200 3201 /* Specify MTU. */ 3202 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3203 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3204 3205 /* Load our MAC address. */ 3206 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3207 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3208 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3209 3210 /* Enable or disable promiscuous mode as needed. */ 3211 if (ifp->if_flags & IFF_PROMISC) { 3212 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3213 } else { 3214 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3215 } 3216 3217 /* Program multicast filter. */ 3218 bge_setmulti(sc); 3219 3220 /* Init RX ring. */ 3221 bge_init_rx_ring_std(sc); 3222 3223 /* 3224 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3225 * memory to insure that the chip has in fact read the first 3226 * entry of the ring. 3227 */ 3228 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3229 u_int32_t v, i; 3230 for (i = 0; i < 10; i++) { 3231 DELAY(20); 3232 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3233 if (v == (MCLBYTES - ETHER_ALIGN)) 3234 break; 3235 } 3236 if (i == 10) 3237 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3238 sc->bge_unit); 3239 } 3240 3241 /* Init jumbo RX ring. */ 3242 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3243 bge_init_rx_ring_jumbo(sc); 3244 3245 /* Init our RX return ring index */ 3246 sc->bge_rx_saved_considx = 0; 3247 3248 /* Init TX ring. */ 3249 bge_init_tx_ring(sc); 3250 3251 /* Turn on transmitter */ 3252 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3253 3254 /* Turn on receiver */ 3255 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3256 3257 /* Tell firmware we're alive. */ 3258 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3259 3260 /* Enable host interrupts. */ 3261 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3262 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3263 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3264 3265 bge_ifmedia_upd(ifp); 3266 3267 ifp->if_flags |= IFF_RUNNING; 3268 ifp->if_flags &= ~IFF_OACTIVE; 3269 3270 splx(s); 3271 3272 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 3273 3274 return; 3275 } 3276 3277 /* 3278 * Set media options. 3279 */ 3280 static int 3281 bge_ifmedia_upd(ifp) 3282 struct ifnet *ifp; 3283 { 3284 struct bge_softc *sc; 3285 struct mii_data *mii; 3286 struct ifmedia *ifm; 3287 3288 sc = ifp->if_softc; 3289 ifm = &sc->bge_ifmedia; 3290 3291 /* If this is a 1000baseX NIC, enable the TBI port. */ 3292 if (sc->bge_tbi) { 3293 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3294 return(EINVAL); 3295 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3296 case IFM_AUTO: 3297 break; 3298 case IFM_1000_SX: 3299 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3300 BGE_CLRBIT(sc, BGE_MAC_MODE, 3301 BGE_MACMODE_HALF_DUPLEX); 3302 } else { 3303 BGE_SETBIT(sc, BGE_MAC_MODE, 3304 BGE_MACMODE_HALF_DUPLEX); 3305 } 3306 break; 3307 default: 3308 return(EINVAL); 3309 } 3310 return(0); 3311 } 3312 3313 mii = device_get_softc(sc->bge_miibus); 3314 sc->bge_link = 0; 3315 if (mii->mii_instance) { 3316 struct mii_softc *miisc; 3317 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3318 miisc = LIST_NEXT(miisc, mii_list)) 3319 mii_phy_reset(miisc); 3320 } 3321 mii_mediachg(mii); 3322 3323 return(0); 3324 } 3325 3326 /* 3327 * Report current media status. 3328 */ 3329 static void 3330 bge_ifmedia_sts(ifp, ifmr) 3331 struct ifnet *ifp; 3332 struct ifmediareq *ifmr; 3333 { 3334 struct bge_softc *sc; 3335 struct mii_data *mii; 3336 3337 sc = ifp->if_softc; 3338 3339 if (sc->bge_tbi) { 3340 ifmr->ifm_status = IFM_AVALID; 3341 ifmr->ifm_active = IFM_ETHER; 3342 if (CSR_READ_4(sc, BGE_MAC_STS) & 3343 BGE_MACSTAT_TBI_PCS_SYNCHED) 3344 ifmr->ifm_status |= IFM_ACTIVE; 3345 ifmr->ifm_active |= IFM_1000_SX; 3346 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3347 ifmr->ifm_active |= IFM_HDX; 3348 else 3349 ifmr->ifm_active |= IFM_FDX; 3350 return; 3351 } 3352 3353 mii = device_get_softc(sc->bge_miibus); 3354 mii_pollstat(mii); 3355 ifmr->ifm_active = mii->mii_media_active; 3356 ifmr->ifm_status = mii->mii_media_status; 3357 3358 return; 3359 } 3360 3361 static int 3362 bge_ioctl(ifp, command, data) 3363 struct ifnet *ifp; 3364 u_long command; 3365 caddr_t data; 3366 { 3367 struct bge_softc *sc = ifp->if_softc; 3368 struct ifreq *ifr = (struct ifreq *) data; 3369 int s, mask, error = 0; 3370 struct mii_data *mii; 3371 3372 s = splimp(); 3373 3374 switch(command) { 3375 case SIOCSIFMTU: 3376 /* Disallow jumbo frames on 5705. */ 3377 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3378 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3379 error = EINVAL; 3380 else { 3381 ifp->if_mtu = ifr->ifr_mtu; 3382 ifp->if_flags &= ~IFF_RUNNING; 3383 bge_init(sc); 3384 } 3385 break; 3386 case SIOCSIFFLAGS: 3387 if (ifp->if_flags & IFF_UP) { 3388 /* 3389 * If only the state of the PROMISC flag changed, 3390 * then just use the 'set promisc mode' command 3391 * instead of reinitializing the entire NIC. Doing 3392 * a full re-init means reloading the firmware and 3393 * waiting for it to start up, which may take a 3394 * second or two. 3395 */ 3396 if (ifp->if_flags & IFF_RUNNING && 3397 ifp->if_flags & IFF_PROMISC && 3398 !(sc->bge_if_flags & IFF_PROMISC)) { 3399 BGE_SETBIT(sc, BGE_RX_MODE, 3400 BGE_RXMODE_RX_PROMISC); 3401 } else if (ifp->if_flags & IFF_RUNNING && 3402 !(ifp->if_flags & IFF_PROMISC) && 3403 sc->bge_if_flags & IFF_PROMISC) { 3404 BGE_CLRBIT(sc, BGE_RX_MODE, 3405 BGE_RXMODE_RX_PROMISC); 3406 } else 3407 bge_init(sc); 3408 } else { 3409 if (ifp->if_flags & IFF_RUNNING) { 3410 bge_stop(sc); 3411 } 3412 } 3413 sc->bge_if_flags = ifp->if_flags; 3414 error = 0; 3415 break; 3416 case SIOCADDMULTI: 3417 case SIOCDELMULTI: 3418 if (ifp->if_flags & IFF_RUNNING) { 3419 bge_setmulti(sc); 3420 error = 0; 3421 } 3422 break; 3423 case SIOCSIFMEDIA: 3424 case SIOCGIFMEDIA: 3425 if (sc->bge_tbi) { 3426 error = ifmedia_ioctl(ifp, ifr, 3427 &sc->bge_ifmedia, command); 3428 } else { 3429 mii = device_get_softc(sc->bge_miibus); 3430 error = ifmedia_ioctl(ifp, ifr, 3431 &mii->mii_media, command); 3432 } 3433 break; 3434 case SIOCSIFCAP: 3435 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3436 if (mask & IFCAP_HWCSUM) { 3437 if (IFCAP_HWCSUM & ifp->if_capenable) 3438 ifp->if_capenable &= ~IFCAP_HWCSUM; 3439 else 3440 ifp->if_capenable |= IFCAP_HWCSUM; 3441 } 3442 error = 0; 3443 break; 3444 default: 3445 error = ether_ioctl(ifp, command, data); 3446 break; 3447 } 3448 3449 (void)splx(s); 3450 3451 return(error); 3452 } 3453 3454 static void 3455 bge_watchdog(ifp) 3456 struct ifnet *ifp; 3457 { 3458 struct bge_softc *sc; 3459 3460 sc = ifp->if_softc; 3461 3462 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3463 3464 ifp->if_flags &= ~IFF_RUNNING; 3465 bge_init(sc); 3466 3467 ifp->if_oerrors++; 3468 3469 return; 3470 } 3471 3472 /* 3473 * Stop the adapter and free any mbufs allocated to the 3474 * RX and TX lists. 3475 */ 3476 static void 3477 bge_stop(sc) 3478 struct bge_softc *sc; 3479 { 3480 struct ifnet *ifp; 3481 struct ifmedia_entry *ifm; 3482 struct mii_data *mii = NULL; 3483 int mtmp, itmp; 3484 3485 ifp = &sc->arpcom.ac_if; 3486 3487 if (!sc->bge_tbi) 3488 mii = device_get_softc(sc->bge_miibus); 3489 3490 untimeout(bge_tick, sc, sc->bge_stat_ch); 3491 3492 /* 3493 * Disable all of the receiver blocks 3494 */ 3495 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3496 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3497 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3498 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3499 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3500 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3501 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3502 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3503 3504 /* 3505 * Disable all of the transmit blocks 3506 */ 3507 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3508 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3509 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3510 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3511 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3512 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3513 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3514 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3515 3516 /* 3517 * Shut down all of the memory managers and related 3518 * state machines. 3519 */ 3520 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3521 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3522 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3523 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3524 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3525 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3526 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 3527 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3528 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3529 } 3530 3531 /* Disable host interrupts. */ 3532 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3533 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3534 3535 /* 3536 * Tell firmware we're shutting down. 3537 */ 3538 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3539 3540 /* Free the RX lists. */ 3541 bge_free_rx_ring_std(sc); 3542 3543 /* Free jumbo RX list. */ 3544 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3545 bge_free_rx_ring_jumbo(sc); 3546 3547 /* Free TX buffers. */ 3548 bge_free_tx_ring(sc); 3549 3550 /* 3551 * Isolate/power down the PHY, but leave the media selection 3552 * unchanged so that things will be put back to normal when 3553 * we bring the interface back up. 3554 */ 3555 if (!sc->bge_tbi) { 3556 itmp = ifp->if_flags; 3557 ifp->if_flags |= IFF_UP; 3558 ifm = mii->mii_media.ifm_cur; 3559 mtmp = ifm->ifm_media; 3560 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3561 mii_mediachg(mii); 3562 ifm->ifm_media = mtmp; 3563 ifp->if_flags = itmp; 3564 } 3565 3566 sc->bge_link = 0; 3567 3568 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3569 3570 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3571 3572 return; 3573 } 3574 3575 /* 3576 * Stop all chip I/O so that the kernel's probe routines don't 3577 * get confused by errant DMAs when rebooting. 3578 */ 3579 static void 3580 bge_shutdown(dev) 3581 device_t dev; 3582 { 3583 struct bge_softc *sc; 3584 3585 sc = device_get_softc(dev); 3586 3587 bge_stop(sc); 3588 bge_reset(sc); 3589 3590 return; 3591 } 3592