1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 218 219 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 220 221 { TC_VENDORID, TC_DEVICEID_3C996 }, 222 223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 224 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 225 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 226 227 { 0, 0 } 228 }; 229 230 static const struct bge_vendor { 231 uint16_t v_id; 232 const char *v_name; 233 } bge_vendors[] = { 234 { ALTEON_VENDORID, "Alteon" }, 235 { ALTIMA_VENDORID, "Altima" }, 236 { APPLE_VENDORID, "Apple" }, 237 { BCOM_VENDORID, "Broadcom" }, 238 { SK_VENDORID, "SysKonnect" }, 239 { TC_VENDORID, "3Com" }, 240 { FJTSU_VENDORID, "Fujitsu" }, 241 242 { 0, NULL } 243 }; 244 245 static const struct bge_revision { 246 uint32_t br_chipid; 247 const char *br_name; 248 } bge_revisions[] = { 249 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 250 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 251 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 252 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 253 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 254 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 255 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 256 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 257 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 258 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 259 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 260 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 261 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 262 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 263 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 264 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 265 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 266 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 267 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 268 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 269 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 270 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 271 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 272 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 273 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 274 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 275 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 276 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 277 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 278 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 279 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 280 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 281 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 282 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 283 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 284 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 285 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 286 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 287 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 288 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 289 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 290 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 291 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 292 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 293 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 294 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 295 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 296 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 297 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 298 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 299 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 302 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 303 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 304 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 305 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 306 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 307 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 308 309 { 0, NULL } 310 }; 311 312 /* 313 * Some defaults for major revisions, so that newer steppings 314 * that we don't know about have a shot at working. 315 */ 316 static const struct bge_revision bge_majorrevs[] = { 317 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 318 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 319 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 320 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 321 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 322 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 323 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 324 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 325 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 326 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 327 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 328 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 329 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 330 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 331 /* 5754 and 5787 share the same ASIC ID */ 332 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 333 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 334 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 335 336 { 0, NULL } 337 }; 338 339 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 340 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 341 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 342 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 343 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 344 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 345 346 const struct bge_revision * bge_lookup_rev(uint32_t); 347 const struct bge_vendor * bge_lookup_vendor(uint16_t); 348 349 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 350 351 static int bge_probe(device_t); 352 static int bge_attach(device_t); 353 static int bge_detach(device_t); 354 static int bge_suspend(device_t); 355 static int bge_resume(device_t); 356 static void bge_release_resources(struct bge_softc *); 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 358 static int bge_dma_alloc(struct bge_softc *); 359 static void bge_dma_free(struct bge_softc *); 360 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 361 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 362 363 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 364 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 365 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 366 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 367 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 368 369 static void bge_txeof(struct bge_softc *, uint16_t); 370 static int bge_rxeof(struct bge_softc *, uint16_t, int); 371 372 static void bge_asf_driver_up (struct bge_softc *); 373 static void bge_tick(void *); 374 static void bge_stats_update(struct bge_softc *); 375 static void bge_stats_update_regs(struct bge_softc *); 376 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 377 uint16_t *); 378 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 379 380 static void bge_intr(void *); 381 static int bge_msi_intr(void *); 382 static void bge_intr_task(void *, int); 383 static void bge_start_locked(struct ifnet *); 384 static void bge_start(struct ifnet *); 385 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 386 static void bge_init_locked(struct bge_softc *); 387 static void bge_init(void *); 388 static void bge_stop(struct bge_softc *); 389 static void bge_watchdog(struct bge_softc *); 390 static int bge_shutdown(device_t); 391 static int bge_ifmedia_upd_locked(struct ifnet *); 392 static int bge_ifmedia_upd(struct ifnet *); 393 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 394 395 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 396 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 397 398 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 399 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 400 401 static void bge_setpromisc(struct bge_softc *); 402 static void bge_setmulti(struct bge_softc *); 403 static void bge_setvlan(struct bge_softc *); 404 405 static __inline void bge_rxreuse_std(struct bge_softc *, int); 406 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 407 static int bge_newbuf_std(struct bge_softc *, int); 408 static int bge_newbuf_jumbo(struct bge_softc *, int); 409 static int bge_init_rx_ring_std(struct bge_softc *); 410 static void bge_free_rx_ring_std(struct bge_softc *); 411 static int bge_init_rx_ring_jumbo(struct bge_softc *); 412 static void bge_free_rx_ring_jumbo(struct bge_softc *); 413 static void bge_free_tx_ring(struct bge_softc *); 414 static int bge_init_tx_ring(struct bge_softc *); 415 416 static int bge_chipinit(struct bge_softc *); 417 static int bge_blockinit(struct bge_softc *); 418 419 static int bge_has_eaddr(struct bge_softc *); 420 static uint32_t bge_readmem_ind(struct bge_softc *, int); 421 static void bge_writemem_ind(struct bge_softc *, int, int); 422 static void bge_writembx(struct bge_softc *, int, int); 423 #ifdef notdef 424 static uint32_t bge_readreg_ind(struct bge_softc *, int); 425 #endif 426 static void bge_writemem_direct(struct bge_softc *, int, int); 427 static void bge_writereg_ind(struct bge_softc *, int, int); 428 429 static int bge_miibus_readreg(device_t, int, int); 430 static int bge_miibus_writereg(device_t, int, int, int); 431 static void bge_miibus_statchg(device_t); 432 #ifdef DEVICE_POLLING 433 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 434 #endif 435 436 #define BGE_RESET_START 1 437 #define BGE_RESET_STOP 2 438 static void bge_sig_post_reset(struct bge_softc *, int); 439 static void bge_sig_legacy(struct bge_softc *, int); 440 static void bge_sig_pre_reset(struct bge_softc *, int); 441 static void bge_stop_fw(struct bge_softc *); 442 static int bge_reset(struct bge_softc *); 443 static void bge_link_upd(struct bge_softc *); 444 445 /* 446 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 447 * leak information to untrusted users. It is also known to cause alignment 448 * traps on certain architectures. 449 */ 450 #ifdef BGE_REGISTER_DEBUG 451 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 452 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 453 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 454 #endif 455 static void bge_add_sysctls(struct bge_softc *); 456 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 457 458 static device_method_t bge_methods[] = { 459 /* Device interface */ 460 DEVMETHOD(device_probe, bge_probe), 461 DEVMETHOD(device_attach, bge_attach), 462 DEVMETHOD(device_detach, bge_detach), 463 DEVMETHOD(device_shutdown, bge_shutdown), 464 DEVMETHOD(device_suspend, bge_suspend), 465 DEVMETHOD(device_resume, bge_resume), 466 467 /* bus interface */ 468 DEVMETHOD(bus_print_child, bus_generic_print_child), 469 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 470 471 /* MII interface */ 472 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 473 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 474 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 475 476 { 0, 0 } 477 }; 478 479 static driver_t bge_driver = { 480 "bge", 481 bge_methods, 482 sizeof(struct bge_softc) 483 }; 484 485 static devclass_t bge_devclass; 486 487 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 488 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 489 490 static int bge_allow_asf = 1; 491 492 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 493 494 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 495 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 496 "Allow ASF mode if available"); 497 498 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 499 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 500 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 501 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 502 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 503 504 static int 505 bge_has_eaddr(struct bge_softc *sc) 506 { 507 #ifdef __sparc64__ 508 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 509 device_t dev; 510 uint32_t subvendor; 511 512 dev = sc->bge_dev; 513 514 /* 515 * The on-board BGEs found in sun4u machines aren't fitted with 516 * an EEPROM which means that we have to obtain the MAC address 517 * via OFW and that some tests will always fail. We distinguish 518 * such BGEs by the subvendor ID, which also has to be obtained 519 * from OFW instead of the PCI configuration space as the latter 520 * indicates Broadcom as the subvendor of the netboot interface. 521 * For early Blade 1500 and 2500 we even have to check the OFW 522 * device path as the subvendor ID always defaults to Broadcom 523 * there. 524 */ 525 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 526 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 527 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 528 return (0); 529 memset(buf, 0, sizeof(buf)); 530 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 531 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 532 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 533 return (0); 534 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 535 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 536 return (0); 537 } 538 #endif 539 return (1); 540 } 541 542 static uint32_t 543 bge_readmem_ind(struct bge_softc *sc, int off) 544 { 545 device_t dev; 546 uint32_t val; 547 548 dev = sc->bge_dev; 549 550 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 551 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 552 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 553 return (val); 554 } 555 556 static void 557 bge_writemem_ind(struct bge_softc *sc, int off, int val) 558 { 559 device_t dev; 560 561 dev = sc->bge_dev; 562 563 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 564 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 565 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 566 } 567 568 #ifdef notdef 569 static uint32_t 570 bge_readreg_ind(struct bge_softc *sc, int off) 571 { 572 device_t dev; 573 574 dev = sc->bge_dev; 575 576 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 577 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 578 } 579 #endif 580 581 static void 582 bge_writereg_ind(struct bge_softc *sc, int off, int val) 583 { 584 device_t dev; 585 586 dev = sc->bge_dev; 587 588 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 589 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 590 } 591 592 static void 593 bge_writemem_direct(struct bge_softc *sc, int off, int val) 594 { 595 CSR_WRITE_4(sc, off, val); 596 } 597 598 static void 599 bge_writembx(struct bge_softc *sc, int off, int val) 600 { 601 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 602 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 603 604 CSR_WRITE_4(sc, off, val); 605 } 606 607 /* 608 * Map a single buffer address. 609 */ 610 611 static void 612 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 613 { 614 struct bge_dmamap_arg *ctx; 615 616 if (error) 617 return; 618 619 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 620 621 ctx = arg; 622 ctx->bge_busaddr = segs->ds_addr; 623 } 624 625 static uint8_t 626 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 627 { 628 uint32_t access, byte = 0; 629 int i; 630 631 /* Lock. */ 632 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 633 for (i = 0; i < 8000; i++) { 634 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 635 break; 636 DELAY(20); 637 } 638 if (i == 8000) 639 return (1); 640 641 /* Enable access. */ 642 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 643 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 644 645 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 646 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 647 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 648 DELAY(10); 649 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 650 DELAY(10); 651 break; 652 } 653 } 654 655 if (i == BGE_TIMEOUT * 10) { 656 if_printf(sc->bge_ifp, "nvram read timed out\n"); 657 return (1); 658 } 659 660 /* Get result. */ 661 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 662 663 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 664 665 /* Disable access. */ 666 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 667 668 /* Unlock. */ 669 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 670 CSR_READ_4(sc, BGE_NVRAM_SWARB); 671 672 return (0); 673 } 674 675 /* 676 * Read a sequence of bytes from NVRAM. 677 */ 678 static int 679 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 680 { 681 int err = 0, i; 682 uint8_t byte = 0; 683 684 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 685 return (1); 686 687 for (i = 0; i < cnt; i++) { 688 err = bge_nvram_getbyte(sc, off + i, &byte); 689 if (err) 690 break; 691 *(dest + i) = byte; 692 } 693 694 return (err ? 1 : 0); 695 } 696 697 /* 698 * Read a byte of data stored in the EEPROM at address 'addr.' The 699 * BCM570x supports both the traditional bitbang interface and an 700 * auto access interface for reading the EEPROM. We use the auto 701 * access method. 702 */ 703 static uint8_t 704 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 705 { 706 int i; 707 uint32_t byte = 0; 708 709 /* 710 * Enable use of auto EEPROM access so we can avoid 711 * having to use the bitbang method. 712 */ 713 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 714 715 /* Reset the EEPROM, load the clock period. */ 716 CSR_WRITE_4(sc, BGE_EE_ADDR, 717 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 718 DELAY(20); 719 720 /* Issue the read EEPROM command. */ 721 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 722 723 /* Wait for completion */ 724 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 725 DELAY(10); 726 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 727 break; 728 } 729 730 if (i == BGE_TIMEOUT * 10) { 731 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 732 return (1); 733 } 734 735 /* Get result. */ 736 byte = CSR_READ_4(sc, BGE_EE_DATA); 737 738 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 739 740 return (0); 741 } 742 743 /* 744 * Read a sequence of bytes from the EEPROM. 745 */ 746 static int 747 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 748 { 749 int i, error = 0; 750 uint8_t byte = 0; 751 752 for (i = 0; i < cnt; i++) { 753 error = bge_eeprom_getbyte(sc, off + i, &byte); 754 if (error) 755 break; 756 *(dest + i) = byte; 757 } 758 759 return (error ? 1 : 0); 760 } 761 762 static int 763 bge_miibus_readreg(device_t dev, int phy, int reg) 764 { 765 struct bge_softc *sc; 766 uint32_t val, autopoll; 767 int i; 768 769 sc = device_get_softc(dev); 770 771 /* 772 * Broadcom's own driver always assumes the internal 773 * PHY is at GMII address 1. On some chips, the PHY responds 774 * to accesses at all addresses, which could cause us to 775 * bogusly attach the PHY 32 times at probe type. Always 776 * restricting the lookup to address 1 is simpler than 777 * trying to figure out which chips revisions should be 778 * special-cased. 779 */ 780 if (phy != 1) 781 return (0); 782 783 /* Reading with autopolling on may trigger PCI errors */ 784 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 785 if (autopoll & BGE_MIMODE_AUTOPOLL) { 786 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 787 DELAY(40); 788 } 789 790 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 791 BGE_MIPHY(phy) | BGE_MIREG(reg)); 792 793 for (i = 0; i < BGE_TIMEOUT; i++) { 794 DELAY(10); 795 val = CSR_READ_4(sc, BGE_MI_COMM); 796 if (!(val & BGE_MICOMM_BUSY)) 797 break; 798 } 799 800 if (i == BGE_TIMEOUT) { 801 device_printf(sc->bge_dev, 802 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 803 phy, reg, val); 804 val = 0; 805 goto done; 806 } 807 808 DELAY(5); 809 val = CSR_READ_4(sc, BGE_MI_COMM); 810 811 done: 812 if (autopoll & BGE_MIMODE_AUTOPOLL) { 813 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 814 DELAY(40); 815 } 816 817 if (val & BGE_MICOMM_READFAIL) 818 return (0); 819 820 return (val & 0xFFFF); 821 } 822 823 static int 824 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 825 { 826 struct bge_softc *sc; 827 uint32_t autopoll; 828 int i; 829 830 sc = device_get_softc(dev); 831 832 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 833 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 834 return (0); 835 836 /* Reading with autopolling on may trigger PCI errors */ 837 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 838 if (autopoll & BGE_MIMODE_AUTOPOLL) { 839 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 840 DELAY(40); 841 } 842 843 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 844 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 845 846 for (i = 0; i < BGE_TIMEOUT; i++) { 847 DELAY(10); 848 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 849 DELAY(5); 850 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 851 break; 852 } 853 } 854 855 if (i == BGE_TIMEOUT) { 856 device_printf(sc->bge_dev, 857 "PHY write timed out (phy %d, reg %d, val %d)\n", 858 phy, reg, val); 859 return (0); 860 } 861 862 if (autopoll & BGE_MIMODE_AUTOPOLL) { 863 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 864 DELAY(40); 865 } 866 867 return (0); 868 } 869 870 static void 871 bge_miibus_statchg(device_t dev) 872 { 873 struct bge_softc *sc; 874 struct mii_data *mii; 875 sc = device_get_softc(dev); 876 mii = device_get_softc(sc->bge_miibus); 877 878 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 879 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 880 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 881 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 882 else 883 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 884 885 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 886 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 887 else 888 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 889 } 890 891 /* 892 * Intialize a standard receive ring descriptor. 893 */ 894 static int 895 bge_newbuf_std(struct bge_softc *sc, int i) 896 { 897 struct mbuf *m; 898 struct bge_rx_bd *r; 899 bus_dma_segment_t segs[1]; 900 bus_dmamap_t map; 901 int error, nsegs; 902 903 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 904 if (m == NULL) 905 return (ENOBUFS); 906 m->m_len = m->m_pkthdr.len = MCLBYTES; 907 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 908 m_adj(m, ETHER_ALIGN); 909 910 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 911 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 912 if (error != 0) { 913 m_freem(m); 914 return (error); 915 } 916 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 917 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 918 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 919 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 920 sc->bge_cdata.bge_rx_std_dmamap[i]); 921 } 922 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 923 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 924 sc->bge_cdata.bge_rx_std_sparemap = map; 925 sc->bge_cdata.bge_rx_std_chain[i] = m; 926 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 927 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 928 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 929 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 930 r->bge_flags = BGE_RXBDFLAG_END; 931 r->bge_len = segs[0].ds_len; 932 r->bge_idx = i; 933 934 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 935 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 936 937 return (0); 938 } 939 940 /* 941 * Initialize a jumbo receive ring descriptor. This allocates 942 * a jumbo buffer from the pool managed internally by the driver. 943 */ 944 static int 945 bge_newbuf_jumbo(struct bge_softc *sc, int i) 946 { 947 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 948 bus_dmamap_t map; 949 struct bge_extrx_bd *r; 950 struct mbuf *m; 951 int error, nsegs; 952 953 MGETHDR(m, M_DONTWAIT, MT_DATA); 954 if (m == NULL) 955 return (ENOBUFS); 956 957 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 958 if (!(m->m_flags & M_EXT)) { 959 m_freem(m); 960 return (ENOBUFS); 961 } 962 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 963 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 964 m_adj(m, ETHER_ALIGN); 965 966 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 967 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 968 if (error != 0) { 969 m_freem(m); 970 return (error); 971 } 972 973 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 974 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 975 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 976 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 977 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 978 } 979 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 980 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 981 sc->bge_cdata.bge_rx_jumbo_sparemap; 982 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 983 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 984 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 985 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 986 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 987 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 988 989 /* 990 * Fill in the extended RX buffer descriptor. 991 */ 992 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 993 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 994 r->bge_idx = i; 995 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 996 switch (nsegs) { 997 case 4: 998 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 999 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1000 r->bge_len3 = segs[3].ds_len; 1001 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1002 case 3: 1003 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1004 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1005 r->bge_len2 = segs[2].ds_len; 1006 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1007 case 2: 1008 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1009 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1010 r->bge_len1 = segs[1].ds_len; 1011 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1012 case 1: 1013 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1014 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1015 r->bge_len0 = segs[0].ds_len; 1016 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1017 break; 1018 default: 1019 panic("%s: %d segments\n", __func__, nsegs); 1020 } 1021 1022 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1023 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1024 1025 return (0); 1026 } 1027 1028 static int 1029 bge_init_rx_ring_std(struct bge_softc *sc) 1030 { 1031 int error, i; 1032 1033 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1034 sc->bge_std = 0; 1035 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1036 if ((error = bge_newbuf_std(sc, i)) != 0) 1037 return (error); 1038 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1039 }; 1040 1041 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1042 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1043 1044 sc->bge_std = 0; 1045 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1046 1047 return (0); 1048 } 1049 1050 static void 1051 bge_free_rx_ring_std(struct bge_softc *sc) 1052 { 1053 int i; 1054 1055 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1056 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1057 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1058 sc->bge_cdata.bge_rx_std_dmamap[i], 1059 BUS_DMASYNC_POSTREAD); 1060 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1061 sc->bge_cdata.bge_rx_std_dmamap[i]); 1062 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1063 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1064 } 1065 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1066 sizeof(struct bge_rx_bd)); 1067 } 1068 } 1069 1070 static int 1071 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1072 { 1073 struct bge_rcb *rcb; 1074 int error, i; 1075 1076 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1077 sc->bge_jumbo = 0; 1078 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1079 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1080 return (error); 1081 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1082 }; 1083 1084 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1085 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1086 1087 sc->bge_jumbo = 0; 1088 1089 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1090 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1091 BGE_RCB_FLAG_USE_EXT_RX_BD); 1092 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1093 1094 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1095 1096 return (0); 1097 } 1098 1099 static void 1100 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1101 { 1102 int i; 1103 1104 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1105 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1106 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1107 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1108 BUS_DMASYNC_POSTREAD); 1109 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1110 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1111 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1112 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1113 } 1114 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1115 sizeof(struct bge_extrx_bd)); 1116 } 1117 } 1118 1119 static void 1120 bge_free_tx_ring(struct bge_softc *sc) 1121 { 1122 int i; 1123 1124 if (sc->bge_ldata.bge_tx_ring == NULL) 1125 return; 1126 1127 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1128 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1129 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1130 sc->bge_cdata.bge_tx_dmamap[i], 1131 BUS_DMASYNC_POSTWRITE); 1132 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1133 sc->bge_cdata.bge_tx_dmamap[i]); 1134 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1135 sc->bge_cdata.bge_tx_chain[i] = NULL; 1136 } 1137 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1138 sizeof(struct bge_tx_bd)); 1139 } 1140 } 1141 1142 static int 1143 bge_init_tx_ring(struct bge_softc *sc) 1144 { 1145 sc->bge_txcnt = 0; 1146 sc->bge_tx_saved_considx = 0; 1147 1148 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1149 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1150 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1151 1152 /* Initialize transmit producer index for host-memory send ring. */ 1153 sc->bge_tx_prodidx = 0; 1154 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1155 1156 /* 5700 b2 errata */ 1157 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1158 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1159 1160 /* NIC-memory send ring not used; initialize to zero. */ 1161 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1162 /* 5700 b2 errata */ 1163 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1164 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1165 1166 return (0); 1167 } 1168 1169 static void 1170 bge_setpromisc(struct bge_softc *sc) 1171 { 1172 struct ifnet *ifp; 1173 1174 BGE_LOCK_ASSERT(sc); 1175 1176 ifp = sc->bge_ifp; 1177 1178 /* Enable or disable promiscuous mode as needed. */ 1179 if (ifp->if_flags & IFF_PROMISC) 1180 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1181 else 1182 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1183 } 1184 1185 static void 1186 bge_setmulti(struct bge_softc *sc) 1187 { 1188 struct ifnet *ifp; 1189 struct ifmultiaddr *ifma; 1190 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1191 int h, i; 1192 1193 BGE_LOCK_ASSERT(sc); 1194 1195 ifp = sc->bge_ifp; 1196 1197 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1198 for (i = 0; i < 4; i++) 1199 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1200 return; 1201 } 1202 1203 /* First, zot all the existing filters. */ 1204 for (i = 0; i < 4; i++) 1205 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1206 1207 /* Now program new ones. */ 1208 if_maddr_rlock(ifp); 1209 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1210 if (ifma->ifma_addr->sa_family != AF_LINK) 1211 continue; 1212 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1213 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1214 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1215 } 1216 if_maddr_runlock(ifp); 1217 1218 for (i = 0; i < 4; i++) 1219 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1220 } 1221 1222 static void 1223 bge_setvlan(struct bge_softc *sc) 1224 { 1225 struct ifnet *ifp; 1226 1227 BGE_LOCK_ASSERT(sc); 1228 1229 ifp = sc->bge_ifp; 1230 1231 /* Enable or disable VLAN tag stripping as needed. */ 1232 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1233 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1234 else 1235 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1236 } 1237 1238 static void 1239 bge_sig_pre_reset(struct bge_softc *sc, int type) 1240 { 1241 1242 /* 1243 * Some chips don't like this so only do this if ASF is enabled 1244 */ 1245 if (sc->bge_asf_mode) 1246 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1247 1248 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1249 switch (type) { 1250 case BGE_RESET_START: 1251 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1252 break; 1253 case BGE_RESET_STOP: 1254 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1255 break; 1256 } 1257 } 1258 } 1259 1260 static void 1261 bge_sig_post_reset(struct bge_softc *sc, int type) 1262 { 1263 1264 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1265 switch (type) { 1266 case BGE_RESET_START: 1267 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1268 /* START DONE */ 1269 break; 1270 case BGE_RESET_STOP: 1271 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1272 break; 1273 } 1274 } 1275 } 1276 1277 static void 1278 bge_sig_legacy(struct bge_softc *sc, int type) 1279 { 1280 1281 if (sc->bge_asf_mode) { 1282 switch (type) { 1283 case BGE_RESET_START: 1284 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1285 break; 1286 case BGE_RESET_STOP: 1287 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1288 break; 1289 } 1290 } 1291 } 1292 1293 static void 1294 bge_stop_fw(struct bge_softc *sc) 1295 { 1296 int i; 1297 1298 if (sc->bge_asf_mode) { 1299 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1300 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1301 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1302 1303 for (i = 0; i < 100; i++ ) { 1304 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1305 break; 1306 DELAY(10); 1307 } 1308 } 1309 } 1310 1311 /* 1312 * Do endian, PCI and DMA initialization. 1313 */ 1314 static int 1315 bge_chipinit(struct bge_softc *sc) 1316 { 1317 uint32_t dma_rw_ctl; 1318 uint16_t val; 1319 int i; 1320 1321 /* Set endianness before we access any non-PCI registers. */ 1322 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1323 1324 /* Clear the MAC control register */ 1325 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1326 1327 /* 1328 * Clear the MAC statistics block in the NIC's 1329 * internal memory. 1330 */ 1331 for (i = BGE_STATS_BLOCK; 1332 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1333 BGE_MEMWIN_WRITE(sc, i, 0); 1334 1335 for (i = BGE_STATUS_BLOCK; 1336 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1337 BGE_MEMWIN_WRITE(sc, i, 0); 1338 1339 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1340 /* 1341 * Fix data corruption caused by non-qword write with WB. 1342 * Fix master abort in PCI mode. 1343 * Fix PCI latency timer. 1344 */ 1345 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1346 val |= (1 << 10) | (1 << 12) | (1 << 13); 1347 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1348 } 1349 1350 /* 1351 * Set up the PCI DMA control register. 1352 */ 1353 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1354 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1355 if (sc->bge_flags & BGE_FLAG_PCIE) { 1356 /* Read watermark not used, 128 bytes for write. */ 1357 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1358 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1359 if (BGE_IS_5714_FAMILY(sc)) { 1360 /* 256 bytes for read and write. */ 1361 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1362 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1363 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1364 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1365 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1366 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1367 /* 1368 * In the BCM5703, the DMA read watermark should 1369 * be set to less than or equal to the maximum 1370 * memory read byte count of the PCI-X command 1371 * register. 1372 */ 1373 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1374 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1375 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1376 /* 1536 bytes for read, 384 bytes for write. */ 1377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1379 } else { 1380 /* 384 bytes for read and write. */ 1381 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1382 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1383 0x0F; 1384 } 1385 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1386 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1387 uint32_t tmp; 1388 1389 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1390 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1391 if (tmp == 6 || tmp == 7) 1392 dma_rw_ctl |= 1393 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1394 1395 /* Set PCI-X DMA write workaround. */ 1396 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1397 } 1398 } else { 1399 /* Conventional PCI bus: 256 bytes for read and write. */ 1400 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1401 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1402 1403 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1404 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1405 dma_rw_ctl |= 0x0F; 1406 } 1407 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1408 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1409 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1410 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1412 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1413 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1414 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1415 1416 /* 1417 * Set up general mode register. 1418 */ 1419 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1420 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1421 BGE_MODECTL_TX_NO_PHDR_CSUM); 1422 1423 /* 1424 * BCM5701 B5 have a bug causing data corruption when using 1425 * 64-bit DMA reads, which can be terminated early and then 1426 * completed later as 32-bit accesses, in combination with 1427 * certain bridges. 1428 */ 1429 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1430 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1431 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1432 1433 /* 1434 * Tell the firmware the driver is running 1435 */ 1436 if (sc->bge_asf_mode & ASF_STACKUP) 1437 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1438 1439 /* 1440 * Disable memory write invalidate. Apparently it is not supported 1441 * properly by these devices. Also ensure that INTx isn't disabled, 1442 * as these chips need it even when using MSI. 1443 */ 1444 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1445 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1446 1447 /* Set the timer prescaler (always 66Mhz) */ 1448 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1449 1450 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1451 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1452 DELAY(40); /* XXX */ 1453 1454 /* Put PHY into ready state */ 1455 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1456 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1457 DELAY(40); 1458 } 1459 1460 return (0); 1461 } 1462 1463 static int 1464 bge_blockinit(struct bge_softc *sc) 1465 { 1466 struct bge_rcb *rcb; 1467 bus_size_t vrcb; 1468 bge_hostaddr taddr; 1469 uint32_t val; 1470 int i; 1471 1472 /* 1473 * Initialize the memory window pointer register so that 1474 * we can access the first 32K of internal NIC RAM. This will 1475 * allow us to set up the TX send ring RCBs and the RX return 1476 * ring RCBs, plus other things which live in NIC memory. 1477 */ 1478 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1479 1480 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1481 1482 if (!(BGE_IS_5705_PLUS(sc))) { 1483 /* Configure mbuf memory pool */ 1484 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1485 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1486 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1487 else 1488 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1489 1490 /* Configure DMA resource pool */ 1491 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1492 BGE_DMA_DESCRIPTORS); 1493 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1494 } 1495 1496 /* Configure mbuf pool watermarks */ 1497 if (!BGE_IS_5705_PLUS(sc)) { 1498 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1501 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1503 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1505 } else { 1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1507 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1509 } 1510 1511 /* Configure DMA resource watermarks */ 1512 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1513 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1514 1515 /* Enable buffer manager */ 1516 if (!(BGE_IS_5705_PLUS(sc))) { 1517 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1518 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1519 1520 /* Poll for buffer manager start indication */ 1521 for (i = 0; i < BGE_TIMEOUT; i++) { 1522 DELAY(10); 1523 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1524 break; 1525 } 1526 1527 if (i == BGE_TIMEOUT) { 1528 device_printf(sc->bge_dev, 1529 "buffer manager failed to start\n"); 1530 return (ENXIO); 1531 } 1532 } 1533 1534 /* Enable flow-through queues */ 1535 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1536 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1537 1538 /* Wait until queue initialization is complete */ 1539 for (i = 0; i < BGE_TIMEOUT; i++) { 1540 DELAY(10); 1541 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1542 break; 1543 } 1544 1545 if (i == BGE_TIMEOUT) { 1546 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1547 return (ENXIO); 1548 } 1549 1550 /* Initialize the standard RX ring control block */ 1551 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1552 rcb->bge_hostaddr.bge_addr_lo = 1553 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1554 rcb->bge_hostaddr.bge_addr_hi = 1555 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1556 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1557 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1558 if (BGE_IS_5705_PLUS(sc)) 1559 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1560 else 1561 rcb->bge_maxlen_flags = 1562 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1563 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1564 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1565 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1566 1567 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1568 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1569 1570 /* 1571 * Initialize the jumbo RX ring control block 1572 * We set the 'ring disabled' bit in the flags 1573 * field until we're actually ready to start 1574 * using this ring (i.e. once we set the MTU 1575 * high enough to require it). 1576 */ 1577 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1578 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1579 1580 rcb->bge_hostaddr.bge_addr_lo = 1581 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1582 rcb->bge_hostaddr.bge_addr_hi = 1583 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1584 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1585 sc->bge_cdata.bge_rx_jumbo_ring_map, 1586 BUS_DMASYNC_PREREAD); 1587 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1588 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1589 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1590 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1591 rcb->bge_hostaddr.bge_addr_hi); 1592 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1593 rcb->bge_hostaddr.bge_addr_lo); 1594 1595 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1596 rcb->bge_maxlen_flags); 1597 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1598 1599 /* Set up dummy disabled mini ring RCB */ 1600 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1601 rcb->bge_maxlen_flags = 1602 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1603 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1604 rcb->bge_maxlen_flags); 1605 } 1606 1607 /* 1608 * Set the BD ring replentish thresholds. The recommended 1609 * values are 1/8th the number of descriptors allocated to 1610 * each ring. 1611 * XXX The 5754 requires a lower threshold, so it might be a 1612 * requirement of all 575x family chips. The Linux driver sets 1613 * the lower threshold for all 5705 family chips as well, but there 1614 * are reports that it might not need to be so strict. 1615 * 1616 * XXX Linux does some extra fiddling here for the 5906 parts as 1617 * well. 1618 */ 1619 if (BGE_IS_5705_PLUS(sc)) 1620 val = 8; 1621 else 1622 val = BGE_STD_RX_RING_CNT / 8; 1623 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1624 if (BGE_IS_JUMBO_CAPABLE(sc)) 1625 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1626 BGE_JUMBO_RX_RING_CNT/8); 1627 1628 /* 1629 * Disable all unused send rings by setting the 'ring disabled' 1630 * bit in the flags field of all the TX send ring control blocks. 1631 * These are located in NIC memory. 1632 */ 1633 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1634 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1635 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1636 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1637 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1638 vrcb += sizeof(struct bge_rcb); 1639 } 1640 1641 /* Configure TX RCB 0 (we use only the first ring) */ 1642 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1643 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1644 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1645 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1646 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1647 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1648 if (!(BGE_IS_5705_PLUS(sc))) 1649 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1650 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1651 1652 /* Disable all unused RX return rings */ 1653 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1654 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1655 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1656 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1657 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1658 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1659 BGE_RCB_FLAG_RING_DISABLED)); 1660 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1661 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1662 (i * (sizeof(uint64_t))), 0); 1663 vrcb += sizeof(struct bge_rcb); 1664 } 1665 1666 /* Initialize RX ring indexes */ 1667 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1668 if (BGE_IS_JUMBO_CAPABLE(sc)) 1669 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1670 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1671 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1672 1673 /* 1674 * Set up RX return ring 0 1675 * Note that the NIC address for RX return rings is 0x00000000. 1676 * The return rings live entirely within the host, so the 1677 * nicaddr field in the RCB isn't used. 1678 */ 1679 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1680 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1681 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1682 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1683 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1684 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1685 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1686 1687 /* Set random backoff seed for TX */ 1688 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1689 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1690 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1691 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1692 BGE_TX_BACKOFF_SEED_MASK); 1693 1694 /* Set inter-packet gap */ 1695 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1696 1697 /* 1698 * Specify which ring to use for packets that don't match 1699 * any RX rules. 1700 */ 1701 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1702 1703 /* 1704 * Configure number of RX lists. One interrupt distribution 1705 * list, sixteen active lists, one bad frames class. 1706 */ 1707 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1708 1709 /* Inialize RX list placement stats mask. */ 1710 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1711 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1712 1713 /* Disable host coalescing until we get it set up */ 1714 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1715 1716 /* Poll to make sure it's shut down. */ 1717 for (i = 0; i < BGE_TIMEOUT; i++) { 1718 DELAY(10); 1719 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1720 break; 1721 } 1722 1723 if (i == BGE_TIMEOUT) { 1724 device_printf(sc->bge_dev, 1725 "host coalescing engine failed to idle\n"); 1726 return (ENXIO); 1727 } 1728 1729 /* Set up host coalescing defaults */ 1730 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1731 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1732 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1733 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1734 if (!(BGE_IS_5705_PLUS(sc))) { 1735 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1736 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1737 } 1738 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1739 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1740 1741 /* Set up address of statistics block */ 1742 if (!(BGE_IS_5705_PLUS(sc))) { 1743 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1744 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1745 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1746 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1747 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1748 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1749 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1750 } 1751 1752 /* Set up address of status block */ 1753 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1754 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1755 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1756 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1757 1758 /* Set up status block size. */ 1759 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1760 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1761 val = BGE_STATBLKSZ_FULL; 1762 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1763 } else { 1764 val = BGE_STATBLKSZ_32BYTE; 1765 bzero(sc->bge_ldata.bge_status_block, 32); 1766 } 1767 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1768 sc->bge_cdata.bge_status_map, 1769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1770 1771 /* Turn on host coalescing state machine */ 1772 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1773 1774 /* Turn on RX BD completion state machine and enable attentions */ 1775 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1776 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1777 1778 /* Turn on RX list placement state machine */ 1779 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1780 1781 /* Turn on RX list selector state machine. */ 1782 if (!(BGE_IS_5705_PLUS(sc))) 1783 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1784 1785 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1786 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1787 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1788 BGE_MACMODE_FRMHDR_DMA_ENB; 1789 1790 if (sc->bge_flags & BGE_FLAG_TBI) 1791 val |= BGE_PORTMODE_TBI; 1792 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1793 val |= BGE_PORTMODE_GMII; 1794 else 1795 val |= BGE_PORTMODE_MII; 1796 1797 /* Turn on DMA, clear stats */ 1798 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1799 1800 /* Set misc. local control, enable interrupts on attentions */ 1801 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1802 1803 #ifdef notdef 1804 /* Assert GPIO pins for PHY reset */ 1805 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1806 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1807 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1808 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1809 #endif 1810 1811 /* Turn on DMA completion state machine */ 1812 if (!(BGE_IS_5705_PLUS(sc))) 1813 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1814 1815 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1816 1817 /* Enable host coalescing bug fix. */ 1818 if (BGE_IS_5755_PLUS(sc)) 1819 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1820 1821 /* Turn on write DMA state machine */ 1822 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1823 DELAY(40); 1824 1825 /* Turn on read DMA state machine */ 1826 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1827 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1828 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1829 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1830 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1831 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1832 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1833 if (sc->bge_flags & BGE_FLAG_PCIE) 1834 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1835 if (sc->bge_flags & BGE_FLAG_TSO) { 1836 val |= BGE_RDMAMODE_TSO4_ENABLE; 1837 if (sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1838 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1839 val |= BGE_RDMAMODE_TSO6_ENABLE; 1840 } 1841 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1842 DELAY(40); 1843 1844 /* Turn on RX data completion state machine */ 1845 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1846 1847 /* Turn on RX BD initiator state machine */ 1848 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1849 1850 /* Turn on RX data and RX BD initiator state machine */ 1851 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1852 1853 /* Turn on Mbuf cluster free state machine */ 1854 if (!(BGE_IS_5705_PLUS(sc))) 1855 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1856 1857 /* Turn on send BD completion state machine */ 1858 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1859 1860 /* Turn on send data completion state machine */ 1861 val = BGE_SDCMODE_ENABLE; 1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1863 val |= BGE_SDCMODE_CDELAY; 1864 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1865 1866 /* Turn on send data initiator state machine */ 1867 if (sc->bge_flags & BGE_FLAG_TSO) 1868 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1869 else 1870 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1871 1872 /* Turn on send BD initiator state machine */ 1873 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1874 1875 /* Turn on send BD selector state machine */ 1876 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1877 1878 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1879 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1880 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1881 1882 /* ack/clear link change events */ 1883 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1884 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1885 BGE_MACSTAT_LINK_CHANGED); 1886 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1887 1888 /* Enable PHY auto polling (for MII/GMII only) */ 1889 if (sc->bge_flags & BGE_FLAG_TBI) { 1890 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1891 } else { 1892 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1893 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1894 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1895 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1896 BGE_EVTENB_MI_INTERRUPT); 1897 } 1898 1899 /* 1900 * Clear any pending link state attention. 1901 * Otherwise some link state change events may be lost until attention 1902 * is cleared by bge_intr() -> bge_link_upd() sequence. 1903 * It's not necessary on newer BCM chips - perhaps enabling link 1904 * state change attentions implies clearing pending attention. 1905 */ 1906 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1907 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1908 BGE_MACSTAT_LINK_CHANGED); 1909 1910 /* Enable link state change attentions. */ 1911 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1912 1913 return (0); 1914 } 1915 1916 const struct bge_revision * 1917 bge_lookup_rev(uint32_t chipid) 1918 { 1919 const struct bge_revision *br; 1920 1921 for (br = bge_revisions; br->br_name != NULL; br++) { 1922 if (br->br_chipid == chipid) 1923 return (br); 1924 } 1925 1926 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1927 if (br->br_chipid == BGE_ASICREV(chipid)) 1928 return (br); 1929 } 1930 1931 return (NULL); 1932 } 1933 1934 const struct bge_vendor * 1935 bge_lookup_vendor(uint16_t vid) 1936 { 1937 const struct bge_vendor *v; 1938 1939 for (v = bge_vendors; v->v_name != NULL; v++) 1940 if (v->v_id == vid) 1941 return (v); 1942 1943 panic("%s: unknown vendor %d", __func__, vid); 1944 return (NULL); 1945 } 1946 1947 /* 1948 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1949 * against our list and return its name if we find a match. 1950 * 1951 * Note that since the Broadcom controller contains VPD support, we 1952 * try to get the device name string from the controller itself instead 1953 * of the compiled-in string. It guarantees we'll always announce the 1954 * right product name. We fall back to the compiled-in string when 1955 * VPD is unavailable or corrupt. 1956 */ 1957 static int 1958 bge_probe(device_t dev) 1959 { 1960 const struct bge_type *t = bge_devs; 1961 struct bge_softc *sc = device_get_softc(dev); 1962 uint16_t vid, did; 1963 1964 sc->bge_dev = dev; 1965 vid = pci_get_vendor(dev); 1966 did = pci_get_device(dev); 1967 while(t->bge_vid != 0) { 1968 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1969 char model[64], buf[96]; 1970 const struct bge_revision *br; 1971 const struct bge_vendor *v; 1972 uint32_t id; 1973 1974 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1975 BGE_PCIMISCCTL_ASICREV_SHIFT; 1976 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 1977 id = pci_read_config(dev, 1978 BGE_PCI_PRODID_ASICREV, 4); 1979 br = bge_lookup_rev(id); 1980 v = bge_lookup_vendor(vid); 1981 { 1982 #if __FreeBSD_version > 700024 1983 const char *pname; 1984 1985 if (bge_has_eaddr(sc) && 1986 pci_get_vpd_ident(dev, &pname) == 0) 1987 snprintf(model, 64, "%s", pname); 1988 else 1989 #endif 1990 snprintf(model, 64, "%s %s", 1991 v->v_name, 1992 br != NULL ? br->br_name : 1993 "NetXtreme Ethernet Controller"); 1994 } 1995 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 1996 br != NULL ? "" : "unknown ", id); 1997 device_set_desc_copy(dev, buf); 1998 return (0); 1999 } 2000 t++; 2001 } 2002 2003 return (ENXIO); 2004 } 2005 2006 static void 2007 bge_dma_free(struct bge_softc *sc) 2008 { 2009 int i; 2010 2011 /* Destroy DMA maps for RX buffers. */ 2012 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2013 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2014 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2015 sc->bge_cdata.bge_rx_std_dmamap[i]); 2016 } 2017 if (sc->bge_cdata.bge_rx_std_sparemap) 2018 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2019 sc->bge_cdata.bge_rx_std_sparemap); 2020 2021 /* Destroy DMA maps for jumbo RX buffers. */ 2022 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2023 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2024 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2025 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2026 } 2027 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2028 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2029 sc->bge_cdata.bge_rx_jumbo_sparemap); 2030 2031 /* Destroy DMA maps for TX buffers. */ 2032 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2033 if (sc->bge_cdata.bge_tx_dmamap[i]) 2034 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2035 sc->bge_cdata.bge_tx_dmamap[i]); 2036 } 2037 2038 if (sc->bge_cdata.bge_rx_mtag) 2039 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2040 if (sc->bge_cdata.bge_tx_mtag) 2041 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2042 2043 2044 /* Destroy standard RX ring. */ 2045 if (sc->bge_cdata.bge_rx_std_ring_map) 2046 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2047 sc->bge_cdata.bge_rx_std_ring_map); 2048 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2049 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2050 sc->bge_ldata.bge_rx_std_ring, 2051 sc->bge_cdata.bge_rx_std_ring_map); 2052 2053 if (sc->bge_cdata.bge_rx_std_ring_tag) 2054 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2055 2056 /* Destroy jumbo RX ring. */ 2057 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2058 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2059 sc->bge_cdata.bge_rx_jumbo_ring_map); 2060 2061 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2062 sc->bge_ldata.bge_rx_jumbo_ring) 2063 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2064 sc->bge_ldata.bge_rx_jumbo_ring, 2065 sc->bge_cdata.bge_rx_jumbo_ring_map); 2066 2067 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2068 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2069 2070 /* Destroy RX return ring. */ 2071 if (sc->bge_cdata.bge_rx_return_ring_map) 2072 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2073 sc->bge_cdata.bge_rx_return_ring_map); 2074 2075 if (sc->bge_cdata.bge_rx_return_ring_map && 2076 sc->bge_ldata.bge_rx_return_ring) 2077 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2078 sc->bge_ldata.bge_rx_return_ring, 2079 sc->bge_cdata.bge_rx_return_ring_map); 2080 2081 if (sc->bge_cdata.bge_rx_return_ring_tag) 2082 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2083 2084 /* Destroy TX ring. */ 2085 if (sc->bge_cdata.bge_tx_ring_map) 2086 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2087 sc->bge_cdata.bge_tx_ring_map); 2088 2089 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2090 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2091 sc->bge_ldata.bge_tx_ring, 2092 sc->bge_cdata.bge_tx_ring_map); 2093 2094 if (sc->bge_cdata.bge_tx_ring_tag) 2095 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2096 2097 /* Destroy status block. */ 2098 if (sc->bge_cdata.bge_status_map) 2099 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2100 sc->bge_cdata.bge_status_map); 2101 2102 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2103 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2104 sc->bge_ldata.bge_status_block, 2105 sc->bge_cdata.bge_status_map); 2106 2107 if (sc->bge_cdata.bge_status_tag) 2108 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2109 2110 /* Destroy statistics block. */ 2111 if (sc->bge_cdata.bge_stats_map) 2112 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2113 sc->bge_cdata.bge_stats_map); 2114 2115 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2116 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2117 sc->bge_ldata.bge_stats, 2118 sc->bge_cdata.bge_stats_map); 2119 2120 if (sc->bge_cdata.bge_stats_tag) 2121 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2122 2123 if (sc->bge_cdata.bge_buffer_tag) 2124 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2125 2126 /* Destroy the parent tag. */ 2127 if (sc->bge_cdata.bge_parent_tag) 2128 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2129 } 2130 2131 static int 2132 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2133 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2134 bus_addr_t *paddr, const char *msg) 2135 { 2136 struct bge_dmamap_arg ctx; 2137 bus_addr_t lowaddr; 2138 bus_size_t ring_end; 2139 int error; 2140 2141 lowaddr = BUS_SPACE_MAXADDR; 2142 again: 2143 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2144 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2145 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2146 if (error != 0) { 2147 device_printf(sc->bge_dev, 2148 "could not create %s dma tag\n", msg); 2149 return (ENOMEM); 2150 } 2151 /* Allocate DMA'able memory for ring. */ 2152 error = bus_dmamem_alloc(*tag, (void **)ring, 2153 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2154 if (error != 0) { 2155 device_printf(sc->bge_dev, 2156 "could not allocate DMA'able memory for %s\n", msg); 2157 return (ENOMEM); 2158 } 2159 /* Load the address of the ring. */ 2160 ctx.bge_busaddr = 0; 2161 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2162 &ctx, BUS_DMA_NOWAIT); 2163 if (error != 0) { 2164 device_printf(sc->bge_dev, 2165 "could not load DMA'able memory for %s\n", msg); 2166 return (ENOMEM); 2167 } 2168 *paddr = ctx.bge_busaddr; 2169 ring_end = *paddr + maxsize; 2170 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2171 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2172 /* 2173 * 4GB boundary crossed. Limit maximum allowable DMA 2174 * address space to 32bit and try again. 2175 */ 2176 bus_dmamap_unload(*tag, *map); 2177 bus_dmamem_free(*tag, *ring, *map); 2178 bus_dma_tag_destroy(*tag); 2179 if (bootverbose) 2180 device_printf(sc->bge_dev, "4GB boundary crossed, " 2181 "limit DMA address space to 32bit for %s\n", msg); 2182 *ring = NULL; 2183 *tag = NULL; 2184 *map = NULL; 2185 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2186 goto again; 2187 } 2188 return (0); 2189 } 2190 2191 static int 2192 bge_dma_alloc(struct bge_softc *sc) 2193 { 2194 bus_addr_t lowaddr; 2195 bus_size_t boundary, sbsz, txsegsz, txmaxsegsz; 2196 int i, error; 2197 2198 lowaddr = BUS_SPACE_MAXADDR; 2199 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2200 lowaddr = BGE_DMA_MAXADDR; 2201 /* 2202 * Allocate the parent bus DMA tag appropriate for PCI. 2203 */ 2204 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2205 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2206 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2207 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2208 if (error != 0) { 2209 device_printf(sc->bge_dev, 2210 "could not allocate parent dma tag\n"); 2211 return (ENOMEM); 2212 } 2213 2214 /* Create tag for standard RX ring. */ 2215 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2216 &sc->bge_cdata.bge_rx_std_ring_tag, 2217 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2218 &sc->bge_cdata.bge_rx_std_ring_map, 2219 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2220 if (error) 2221 return (error); 2222 2223 /* Create tag for RX return ring. */ 2224 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2225 &sc->bge_cdata.bge_rx_return_ring_tag, 2226 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2227 &sc->bge_cdata.bge_rx_return_ring_map, 2228 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2229 if (error) 2230 return (error); 2231 2232 /* Create tag for TX ring. */ 2233 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2234 &sc->bge_cdata.bge_tx_ring_tag, 2235 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2236 &sc->bge_cdata.bge_tx_ring_map, 2237 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2238 if (error) 2239 return (error); 2240 2241 /* 2242 * Create tag for status block. 2243 * Because we only use single Tx/Rx/Rx return ring, use 2244 * minimum status block size except BCM5700 AX/BX which 2245 * seems to want to see full status block size regardless 2246 * of configured number of ring. 2247 */ 2248 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2249 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2250 sbsz = BGE_STATUS_BLK_SZ; 2251 else 2252 sbsz = 32; 2253 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2254 &sc->bge_cdata.bge_status_tag, 2255 (uint8_t **)&sc->bge_ldata.bge_status_block, 2256 &sc->bge_cdata.bge_status_map, 2257 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2258 if (error) 2259 return (error); 2260 2261 /* Create tag for statistics block. */ 2262 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2263 &sc->bge_cdata.bge_stats_tag, 2264 (uint8_t **)&sc->bge_ldata.bge_stats, 2265 &sc->bge_cdata.bge_stats_map, 2266 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2267 if (error) 2268 return (error); 2269 2270 /* Create tag for jumbo RX ring. */ 2271 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2272 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2273 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2274 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2275 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2276 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2277 if (error) 2278 return (error); 2279 } 2280 2281 /* Create parent tag for buffers. */ 2282 boundary = 0; 2283 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2284 boundary = BGE_DMA_BNDRY; 2285 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2286 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 2287 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2288 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 2289 if (error != 0) { 2290 device_printf(sc->bge_dev, 2291 "could not allocate buffer dma tag\n"); 2292 return (ENOMEM); 2293 } 2294 /* Create tag for Tx mbufs. */ 2295 if (sc->bge_flags & BGE_FLAG_TSO) { 2296 txsegsz = BGE_TSOSEG_SZ; 2297 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2298 } else { 2299 txsegsz = MCLBYTES; 2300 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2301 } 2302 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2303 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2304 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2305 &sc->bge_cdata.bge_tx_mtag); 2306 2307 if (error) { 2308 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2309 return (ENOMEM); 2310 } 2311 2312 /* Create tag for Rx mbufs. */ 2313 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2314 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2315 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2316 2317 if (error) { 2318 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2319 return (ENOMEM); 2320 } 2321 2322 /* Create DMA maps for RX buffers. */ 2323 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2324 &sc->bge_cdata.bge_rx_std_sparemap); 2325 if (error) { 2326 device_printf(sc->bge_dev, 2327 "can't create spare DMA map for RX\n"); 2328 return (ENOMEM); 2329 } 2330 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2331 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2332 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2333 if (error) { 2334 device_printf(sc->bge_dev, 2335 "can't create DMA map for RX\n"); 2336 return (ENOMEM); 2337 } 2338 } 2339 2340 /* Create DMA maps for TX buffers. */ 2341 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2342 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2343 &sc->bge_cdata.bge_tx_dmamap[i]); 2344 if (error) { 2345 device_printf(sc->bge_dev, 2346 "can't create DMA map for TX\n"); 2347 return (ENOMEM); 2348 } 2349 } 2350 2351 /* Create tags for jumbo RX buffers. */ 2352 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2353 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2354 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2355 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2356 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2357 if (error) { 2358 device_printf(sc->bge_dev, 2359 "could not allocate jumbo dma tag\n"); 2360 return (ENOMEM); 2361 } 2362 /* Create DMA maps for jumbo RX buffers. */ 2363 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2364 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2365 if (error) { 2366 device_printf(sc->bge_dev, 2367 "can't create spare DMA map for jumbo RX\n"); 2368 return (ENOMEM); 2369 } 2370 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2371 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2372 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2373 if (error) { 2374 device_printf(sc->bge_dev, 2375 "can't create DMA map for jumbo RX\n"); 2376 return (ENOMEM); 2377 } 2378 } 2379 } 2380 2381 return (0); 2382 } 2383 2384 /* 2385 * Return true if this device has more than one port. 2386 */ 2387 static int 2388 bge_has_multiple_ports(struct bge_softc *sc) 2389 { 2390 device_t dev = sc->bge_dev; 2391 u_int b, d, f, fscan, s; 2392 2393 d = pci_get_domain(dev); 2394 b = pci_get_bus(dev); 2395 s = pci_get_slot(dev); 2396 f = pci_get_function(dev); 2397 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2398 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2399 return (1); 2400 return (0); 2401 } 2402 2403 /* 2404 * Return true if MSI can be used with this device. 2405 */ 2406 static int 2407 bge_can_use_msi(struct bge_softc *sc) 2408 { 2409 int can_use_msi = 0; 2410 2411 switch (sc->bge_asicrev) { 2412 case BGE_ASICREV_BCM5714_A0: 2413 case BGE_ASICREV_BCM5714: 2414 /* 2415 * Apparently, MSI doesn't work when these chips are 2416 * configured in single-port mode. 2417 */ 2418 if (bge_has_multiple_ports(sc)) 2419 can_use_msi = 1; 2420 break; 2421 case BGE_ASICREV_BCM5750: 2422 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2423 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2424 can_use_msi = 1; 2425 break; 2426 default: 2427 if (BGE_IS_575X_PLUS(sc)) 2428 can_use_msi = 1; 2429 } 2430 return (can_use_msi); 2431 } 2432 2433 static int 2434 bge_attach(device_t dev) 2435 { 2436 struct ifnet *ifp; 2437 struct bge_softc *sc; 2438 uint32_t hwcfg = 0, misccfg; 2439 u_char eaddr[ETHER_ADDR_LEN]; 2440 int error, msicount, reg, rid, trys; 2441 2442 sc = device_get_softc(dev); 2443 sc->bge_dev = dev; 2444 2445 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2446 2447 /* 2448 * Map control/status registers. 2449 */ 2450 pci_enable_busmaster(dev); 2451 2452 rid = PCIR_BAR(0); 2453 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2454 RF_ACTIVE); 2455 2456 if (sc->bge_res == NULL) { 2457 device_printf (sc->bge_dev, "couldn't map memory\n"); 2458 error = ENXIO; 2459 goto fail; 2460 } 2461 2462 /* Save various chip information. */ 2463 sc->bge_chipid = 2464 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2465 BGE_PCIMISCCTL_ASICREV_SHIFT; 2466 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2467 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2468 4); 2469 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2470 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2471 2472 /* 2473 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2474 * 5705 A0 and A1 chips. 2475 */ 2476 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2477 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2478 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2479 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2480 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2481 2482 if (bge_has_eaddr(sc)) 2483 sc->bge_flags |= BGE_FLAG_EADDR; 2484 2485 /* Save chipset family. */ 2486 switch (sc->bge_asicrev) { 2487 case BGE_ASICREV_BCM5755: 2488 case BGE_ASICREV_BCM5761: 2489 case BGE_ASICREV_BCM5784: 2490 case BGE_ASICREV_BCM5785: 2491 case BGE_ASICREV_BCM5787: 2492 case BGE_ASICREV_BCM57780: 2493 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2494 BGE_FLAG_5705_PLUS; 2495 break; 2496 case BGE_ASICREV_BCM5700: 2497 case BGE_ASICREV_BCM5701: 2498 case BGE_ASICREV_BCM5703: 2499 case BGE_ASICREV_BCM5704: 2500 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2501 break; 2502 case BGE_ASICREV_BCM5714_A0: 2503 case BGE_ASICREV_BCM5780: 2504 case BGE_ASICREV_BCM5714: 2505 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2506 /* FALLTHROUGH */ 2507 case BGE_ASICREV_BCM5750: 2508 case BGE_ASICREV_BCM5752: 2509 case BGE_ASICREV_BCM5906: 2510 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2511 /* FALLTHROUGH */ 2512 case BGE_ASICREV_BCM5705: 2513 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2514 break; 2515 } 2516 2517 /* Set various bug flags. */ 2518 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2519 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2520 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2521 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2522 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2523 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2524 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2525 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2526 if (pci_get_subvendor(dev) == DELL_VENDORID) 2527 sc->bge_flags |= BGE_FLAG_NO_3LED; 2528 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 2529 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 2530 if (BGE_IS_5705_PLUS(sc) && 2531 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2532 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2533 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2534 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2535 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2536 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2537 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 2538 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2539 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2540 sc->bge_flags |= BGE_FLAG_BER_BUG; 2541 } 2542 2543 /* 2544 * All controllers that are not 5755 or higher have 4GB 2545 * boundary DMA bug. 2546 * Whenever an address crosses a multiple of the 4GB boundary 2547 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2548 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2549 * state machine will lockup and cause the device to hang. 2550 */ 2551 if (BGE_IS_5755_PLUS(sc) == 0) 2552 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2553 2554 /* 2555 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2556 * but I do not know the DEVICEID for the 5788M. 2557 */ 2558 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2559 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2560 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2561 sc->bge_flags |= BGE_FLAG_5788; 2562 2563 /* 2564 * Some controllers seem to require a special firmware to use 2565 * TSO. But the firmware is not available to FreeBSD and Linux 2566 * claims that the TSO performed by the firmware is slower than 2567 * hardware based TSO. Moreover the firmware based TSO has one 2568 * known bug which can't handle TSO if ethernet header + IP/TCP 2569 * header is greater than 80 bytes. The workaround for the TSO 2570 * bug exist but it seems it's too expensive than not using 2571 * TSO at all. Some hardwares also have the TSO bug so limit 2572 * the TSO to the controllers that are not affected TSO issues 2573 * (e.g. 5755 or higher). 2574 */ 2575 if (BGE_IS_5755_PLUS(sc)) { 2576 /* 2577 * BCM5754 and BCM5787 shares the same ASIC id so 2578 * explicit device id check is required. 2579 * Due to unknown reason TSO does not work on BCM5755M. 2580 */ 2581 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2582 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 2583 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 2584 sc->bge_flags |= BGE_FLAG_TSO; 2585 } 2586 2587 /* 2588 * Check if this is a PCI-X or PCI Express device. 2589 */ 2590 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2591 /* 2592 * Found a PCI Express capabilities register, this 2593 * must be a PCI Express device. 2594 */ 2595 sc->bge_flags |= BGE_FLAG_PCIE; 2596 sc->bge_expcap = reg; 2597 if (pci_get_max_read_req(dev) != 4096) 2598 pci_set_max_read_req(dev, 4096); 2599 } else { 2600 /* 2601 * Check if the device is in PCI-X Mode. 2602 * (This bit is not valid on PCI Express controllers.) 2603 */ 2604 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 2605 sc->bge_pcixcap = reg; 2606 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2607 BGE_PCISTATE_PCI_BUSMODE) == 0) 2608 sc->bge_flags |= BGE_FLAG_PCIX; 2609 } 2610 2611 /* 2612 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2613 * not actually a MAC controller bug but an issue with the embedded 2614 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2615 */ 2616 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2617 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2618 /* 2619 * Allocate the interrupt, using MSI if possible. These devices 2620 * support 8 MSI messages, but only the first one is used in 2621 * normal operation. 2622 */ 2623 rid = 0; 2624 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { 2625 sc->bge_msicap = reg; 2626 if (bge_can_use_msi(sc)) { 2627 msicount = pci_msi_count(dev); 2628 if (msicount > 1) 2629 msicount = 1; 2630 } else 2631 msicount = 0; 2632 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2633 rid = 1; 2634 sc->bge_flags |= BGE_FLAG_MSI; 2635 } 2636 } 2637 2638 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2639 RF_SHAREABLE | RF_ACTIVE); 2640 2641 if (sc->bge_irq == NULL) { 2642 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2643 error = ENXIO; 2644 goto fail; 2645 } 2646 2647 if (bootverbose) 2648 device_printf(dev, 2649 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2650 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2651 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2652 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2653 2654 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2655 2656 /* Try to reset the chip. */ 2657 if (bge_reset(sc)) { 2658 device_printf(sc->bge_dev, "chip reset failed\n"); 2659 error = ENXIO; 2660 goto fail; 2661 } 2662 2663 sc->bge_asf_mode = 0; 2664 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2665 == BGE_MAGIC_NUMBER)) { 2666 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2667 & BGE_HWCFG_ASF) { 2668 sc->bge_asf_mode |= ASF_ENABLE; 2669 sc->bge_asf_mode |= ASF_STACKUP; 2670 if (BGE_IS_575X_PLUS(sc)) 2671 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2672 } 2673 } 2674 2675 /* Try to reset the chip again the nice way. */ 2676 bge_stop_fw(sc); 2677 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2678 if (bge_reset(sc)) { 2679 device_printf(sc->bge_dev, "chip reset failed\n"); 2680 error = ENXIO; 2681 goto fail; 2682 } 2683 2684 bge_sig_legacy(sc, BGE_RESET_STOP); 2685 bge_sig_post_reset(sc, BGE_RESET_STOP); 2686 2687 if (bge_chipinit(sc)) { 2688 device_printf(sc->bge_dev, "chip initialization failed\n"); 2689 error = ENXIO; 2690 goto fail; 2691 } 2692 2693 error = bge_get_eaddr(sc, eaddr); 2694 if (error) { 2695 device_printf(sc->bge_dev, 2696 "failed to read station address\n"); 2697 error = ENXIO; 2698 goto fail; 2699 } 2700 2701 /* 5705 limits RX return ring to 512 entries. */ 2702 if (BGE_IS_5705_PLUS(sc)) 2703 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2704 else 2705 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2706 2707 if (bge_dma_alloc(sc)) { 2708 device_printf(sc->bge_dev, 2709 "failed to allocate DMA resources\n"); 2710 error = ENXIO; 2711 goto fail; 2712 } 2713 2714 bge_add_sysctls(sc); 2715 2716 /* Set default tuneable values. */ 2717 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2718 sc->bge_rx_coal_ticks = 150; 2719 sc->bge_tx_coal_ticks = 150; 2720 sc->bge_rx_max_coal_bds = 10; 2721 sc->bge_tx_max_coal_bds = 10; 2722 2723 /* Initialize checksum features to use. */ 2724 sc->bge_csum_features = BGE_CSUM_FEATURES; 2725 if (sc->bge_forced_udpcsum != 0) 2726 sc->bge_csum_features |= CSUM_UDP; 2727 2728 /* Set up ifnet structure */ 2729 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2730 if (ifp == NULL) { 2731 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2732 error = ENXIO; 2733 goto fail; 2734 } 2735 ifp->if_softc = sc; 2736 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2738 ifp->if_ioctl = bge_ioctl; 2739 ifp->if_start = bge_start; 2740 ifp->if_init = bge_init; 2741 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2742 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2743 IFQ_SET_READY(&ifp->if_snd); 2744 ifp->if_hwassist = sc->bge_csum_features; 2745 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2746 IFCAP_VLAN_MTU; 2747 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2748 ifp->if_hwassist |= CSUM_TSO; 2749 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 2750 } 2751 #ifdef IFCAP_VLAN_HWCSUM 2752 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2753 #endif 2754 ifp->if_capenable = ifp->if_capabilities; 2755 #ifdef DEVICE_POLLING 2756 ifp->if_capabilities |= IFCAP_POLLING; 2757 #endif 2758 2759 /* 2760 * 5700 B0 chips do not support checksumming correctly due 2761 * to hardware bugs. 2762 */ 2763 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2764 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2765 ifp->if_capenable &= ~IFCAP_HWCSUM; 2766 ifp->if_hwassist = 0; 2767 } 2768 2769 /* 2770 * Figure out what sort of media we have by checking the 2771 * hardware config word in the first 32k of NIC internal memory, 2772 * or fall back to examining the EEPROM if necessary. 2773 * Note: on some BCM5700 cards, this value appears to be unset. 2774 * If that's the case, we have to rely on identifying the NIC 2775 * by its PCI subsystem ID, as we do below for the SysKonnect 2776 * SK-9D41. 2777 */ 2778 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2779 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2780 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2781 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2782 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2783 sizeof(hwcfg))) { 2784 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2785 error = ENXIO; 2786 goto fail; 2787 } 2788 hwcfg = ntohl(hwcfg); 2789 } 2790 2791 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2792 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 2793 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2794 if (BGE_IS_5714_FAMILY(sc)) 2795 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2796 else 2797 sc->bge_flags |= BGE_FLAG_TBI; 2798 } 2799 2800 if (sc->bge_flags & BGE_FLAG_TBI) { 2801 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2802 bge_ifmedia_sts); 2803 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2804 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2805 0, NULL); 2806 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2807 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2808 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2809 } else { 2810 /* 2811 * Do transceiver setup and tell the firmware the 2812 * driver is down so we can try to get access the 2813 * probe if ASF is running. Retry a couple of times 2814 * if we get a conflict with the ASF firmware accessing 2815 * the PHY. 2816 */ 2817 trys = 0; 2818 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2819 again: 2820 bge_asf_driver_up(sc); 2821 2822 if (mii_phy_probe(dev, &sc->bge_miibus, 2823 bge_ifmedia_upd, bge_ifmedia_sts)) { 2824 if (trys++ < 4) { 2825 device_printf(sc->bge_dev, "Try again\n"); 2826 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2827 BMCR_RESET); 2828 goto again; 2829 } 2830 2831 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2832 error = ENXIO; 2833 goto fail; 2834 } 2835 2836 /* 2837 * Now tell the firmware we are going up after probing the PHY 2838 */ 2839 if (sc->bge_asf_mode & ASF_STACKUP) 2840 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2841 } 2842 2843 /* 2844 * When using the BCM5701 in PCI-X mode, data corruption has 2845 * been observed in the first few bytes of some received packets. 2846 * Aligning the packet buffer in memory eliminates the corruption. 2847 * Unfortunately, this misaligns the packet payloads. On platforms 2848 * which do not support unaligned accesses, we will realign the 2849 * payloads by copying the received packets. 2850 */ 2851 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2852 sc->bge_flags & BGE_FLAG_PCIX) 2853 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2854 2855 /* 2856 * Call MI attach routine. 2857 */ 2858 ether_ifattach(ifp, eaddr); 2859 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2860 2861 /* Tell upper layer we support long frames. */ 2862 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2863 2864 /* 2865 * Hookup IRQ last. 2866 */ 2867 #if __FreeBSD_version > 700030 2868 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 2869 /* Take advantage of single-shot MSI. */ 2870 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 2871 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 2872 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 2873 taskqueue_thread_enqueue, &sc->bge_tq); 2874 if (sc->bge_tq == NULL) { 2875 device_printf(dev, "could not create taskqueue.\n"); 2876 ether_ifdetach(ifp); 2877 error = ENXIO; 2878 goto fail; 2879 } 2880 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 2881 device_get_nameunit(sc->bge_dev)); 2882 error = bus_setup_intr(dev, sc->bge_irq, 2883 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 2884 &sc->bge_intrhand); 2885 if (error) 2886 ether_ifdetach(ifp); 2887 } else 2888 error = bus_setup_intr(dev, sc->bge_irq, 2889 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 2890 &sc->bge_intrhand); 2891 #else 2892 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2893 bge_intr, sc, &sc->bge_intrhand); 2894 #endif 2895 2896 if (error) { 2897 bge_detach(dev); 2898 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2899 } 2900 2901 return (0); 2902 2903 fail: 2904 bge_release_resources(sc); 2905 2906 return (error); 2907 } 2908 2909 static int 2910 bge_detach(device_t dev) 2911 { 2912 struct bge_softc *sc; 2913 struct ifnet *ifp; 2914 2915 sc = device_get_softc(dev); 2916 ifp = sc->bge_ifp; 2917 2918 #ifdef DEVICE_POLLING 2919 if (ifp->if_capenable & IFCAP_POLLING) 2920 ether_poll_deregister(ifp); 2921 #endif 2922 2923 BGE_LOCK(sc); 2924 bge_stop(sc); 2925 bge_reset(sc); 2926 BGE_UNLOCK(sc); 2927 2928 callout_drain(&sc->bge_stat_ch); 2929 2930 if (sc->bge_tq) 2931 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 2932 ether_ifdetach(ifp); 2933 2934 if (sc->bge_flags & BGE_FLAG_TBI) { 2935 ifmedia_removeall(&sc->bge_ifmedia); 2936 } else { 2937 bus_generic_detach(dev); 2938 device_delete_child(dev, sc->bge_miibus); 2939 } 2940 2941 bge_release_resources(sc); 2942 2943 return (0); 2944 } 2945 2946 static void 2947 bge_release_resources(struct bge_softc *sc) 2948 { 2949 device_t dev; 2950 2951 dev = sc->bge_dev; 2952 2953 if (sc->bge_tq != NULL) 2954 taskqueue_free(sc->bge_tq); 2955 2956 if (sc->bge_intrhand != NULL) 2957 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2958 2959 if (sc->bge_irq != NULL) 2960 bus_release_resource(dev, SYS_RES_IRQ, 2961 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2962 2963 if (sc->bge_flags & BGE_FLAG_MSI) 2964 pci_release_msi(dev); 2965 2966 if (sc->bge_res != NULL) 2967 bus_release_resource(dev, SYS_RES_MEMORY, 2968 PCIR_BAR(0), sc->bge_res); 2969 2970 if (sc->bge_ifp != NULL) 2971 if_free(sc->bge_ifp); 2972 2973 bge_dma_free(sc); 2974 2975 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2976 BGE_LOCK_DESTROY(sc); 2977 } 2978 2979 static int 2980 bge_reset(struct bge_softc *sc) 2981 { 2982 device_t dev; 2983 uint32_t cachesize, command, pcistate, reset, val; 2984 void (*write_op)(struct bge_softc *, int, int); 2985 uint16_t devctl; 2986 int i; 2987 2988 dev = sc->bge_dev; 2989 2990 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2991 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2992 if (sc->bge_flags & BGE_FLAG_PCIE) 2993 write_op = bge_writemem_direct; 2994 else 2995 write_op = bge_writemem_ind; 2996 } else 2997 write_op = bge_writereg_ind; 2998 2999 /* Save some important PCI state. */ 3000 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3001 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3002 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3003 3004 pci_write_config(dev, BGE_PCI_MISC_CTL, 3005 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3006 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3007 3008 /* Disable fastboot on controllers that support it. */ 3009 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3010 BGE_IS_5755_PLUS(sc)) { 3011 if (bootverbose) 3012 device_printf(dev, "Disabling fastboot\n"); 3013 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3014 } 3015 3016 /* 3017 * Write the magic number to SRAM at offset 0xB50. 3018 * When firmware finishes its initialization it will 3019 * write ~BGE_MAGIC_NUMBER to the same location. 3020 */ 3021 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3022 3023 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3024 3025 /* XXX: Broadcom Linux driver. */ 3026 if (sc->bge_flags & BGE_FLAG_PCIE) { 3027 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3028 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3029 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3030 /* Prevent PCIE link training during global reset */ 3031 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3032 reset |= 1 << 29; 3033 } 3034 } 3035 3036 /* 3037 * Set GPHY Power Down Override to leave GPHY 3038 * powered up in D0 uninitialized. 3039 */ 3040 if (BGE_IS_5705_PLUS(sc)) 3041 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3042 3043 /* Issue global reset */ 3044 write_op(sc, BGE_MISC_CFG, reset); 3045 3046 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3047 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3048 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3049 val | BGE_VCPU_STATUS_DRV_RESET); 3050 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3051 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3052 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3053 } 3054 3055 DELAY(1000); 3056 3057 /* XXX: Broadcom Linux driver. */ 3058 if (sc->bge_flags & BGE_FLAG_PCIE) { 3059 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3060 DELAY(500000); /* wait for link training to complete */ 3061 val = pci_read_config(dev, 0xC4, 4); 3062 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3063 } 3064 devctl = pci_read_config(dev, 3065 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3066 /* Clear enable no snoop and disable relaxed ordering. */ 3067 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3068 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3069 /* Set PCIE max payload size to 128. */ 3070 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3071 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3072 devctl, 2); 3073 /* Clear error status. */ 3074 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3075 PCIM_EXP_STA_CORRECTABLE_ERROR | 3076 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3077 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3078 } 3079 3080 /* Reset some of the PCI state that got zapped by reset. */ 3081 pci_write_config(dev, BGE_PCI_MISC_CTL, 3082 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3083 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3084 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3085 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3086 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3087 /* 3088 * Disable PCI-X relaxed ordering to ensure status block update 3089 * comes first then packet buffer DMA. Otherwise driver may 3090 * read stale status block. 3091 */ 3092 if (sc->bge_flags & BGE_FLAG_PCIX) { 3093 devctl = pci_read_config(dev, 3094 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3095 devctl &= ~PCIXM_COMMAND_ERO; 3096 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3097 devctl &= ~PCIXM_COMMAND_MAX_READ; 3098 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3099 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3100 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3101 PCIXM_COMMAND_MAX_READ); 3102 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3103 } 3104 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3105 devctl, 2); 3106 } 3107 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 3108 if (BGE_IS_5714_FAMILY(sc)) { 3109 /* This chip disables MSI on reset. */ 3110 if (sc->bge_flags & BGE_FLAG_MSI) { 3111 val = pci_read_config(dev, 3112 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3113 pci_write_config(dev, 3114 sc->bge_msicap + PCIR_MSI_CTRL, 3115 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3116 val = CSR_READ_4(sc, BGE_MSI_MODE); 3117 CSR_WRITE_4(sc, BGE_MSI_MODE, 3118 val | BGE_MSIMODE_ENABLE); 3119 } 3120 val = CSR_READ_4(sc, BGE_MARB_MODE); 3121 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3122 } else 3123 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3124 3125 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3126 for (i = 0; i < BGE_TIMEOUT; i++) { 3127 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3128 if (val & BGE_VCPU_STATUS_INIT_DONE) 3129 break; 3130 DELAY(100); 3131 } 3132 if (i == BGE_TIMEOUT) { 3133 device_printf(dev, "reset timed out\n"); 3134 return (1); 3135 } 3136 } else { 3137 /* 3138 * Poll until we see the 1's complement of the magic number. 3139 * This indicates that the firmware initialization is complete. 3140 * We expect this to fail if no chip containing the Ethernet 3141 * address is fitted though. 3142 */ 3143 for (i = 0; i < BGE_TIMEOUT; i++) { 3144 DELAY(10); 3145 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3146 if (val == ~BGE_MAGIC_NUMBER) 3147 break; 3148 } 3149 3150 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3151 device_printf(dev, 3152 "firmware handshake timed out, found 0x%08x\n", 3153 val); 3154 } 3155 3156 /* 3157 * XXX Wait for the value of the PCISTATE register to 3158 * return to its original pre-reset state. This is a 3159 * fairly good indicator of reset completion. If we don't 3160 * wait for the reset to fully complete, trying to read 3161 * from the device's non-PCI registers may yield garbage 3162 * results. 3163 */ 3164 for (i = 0; i < BGE_TIMEOUT; i++) { 3165 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3166 break; 3167 DELAY(10); 3168 } 3169 3170 /* Fix up byte swapping. */ 3171 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3172 BGE_MODECTL_BYTESWAP_DATA); 3173 3174 /* Tell the ASF firmware we are up */ 3175 if (sc->bge_asf_mode & ASF_STACKUP) 3176 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3177 3178 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3179 3180 /* 3181 * The 5704 in TBI mode apparently needs some special 3182 * adjustment to insure the SERDES drive level is set 3183 * to 1.2V. 3184 */ 3185 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3186 sc->bge_flags & BGE_FLAG_TBI) { 3187 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3188 val = (val & ~0xFFF) | 0x880; 3189 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3190 } 3191 3192 /* XXX: Broadcom Linux driver. */ 3193 if (sc->bge_flags & BGE_FLAG_PCIE && 3194 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3195 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3196 /* Enable Data FIFO protection. */ 3197 val = CSR_READ_4(sc, 0x7C00); 3198 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3199 } 3200 DELAY(10000); 3201 3202 return (0); 3203 } 3204 3205 static __inline void 3206 bge_rxreuse_std(struct bge_softc *sc, int i) 3207 { 3208 struct bge_rx_bd *r; 3209 3210 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3211 r->bge_flags = BGE_RXBDFLAG_END; 3212 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3213 r->bge_idx = i; 3214 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3215 } 3216 3217 static __inline void 3218 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3219 { 3220 struct bge_extrx_bd *r; 3221 3222 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3223 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3224 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3225 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3226 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3227 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3228 r->bge_idx = i; 3229 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3230 } 3231 3232 /* 3233 * Frame reception handling. This is called if there's a frame 3234 * on the receive return list. 3235 * 3236 * Note: we have to be able to handle two possibilities here: 3237 * 1) the frame is from the jumbo receive ring 3238 * 2) the frame is from the standard receive ring 3239 */ 3240 3241 static int 3242 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3243 { 3244 struct ifnet *ifp; 3245 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3246 uint16_t rx_cons; 3247 3248 rx_cons = sc->bge_rx_saved_considx; 3249 3250 /* Nothing to do. */ 3251 if (rx_cons == rx_prod) 3252 return (rx_npkts); 3253 3254 ifp = sc->bge_ifp; 3255 3256 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3257 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3258 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3259 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3260 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3261 (MCLBYTES - ETHER_ALIGN)) 3262 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3263 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3264 3265 while (rx_cons != rx_prod) { 3266 struct bge_rx_bd *cur_rx; 3267 uint32_t rxidx; 3268 struct mbuf *m = NULL; 3269 uint16_t vlan_tag = 0; 3270 int have_tag = 0; 3271 3272 #ifdef DEVICE_POLLING 3273 if (ifp->if_capenable & IFCAP_POLLING) { 3274 if (sc->rxcycles <= 0) 3275 break; 3276 sc->rxcycles--; 3277 } 3278 #endif 3279 3280 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3281 3282 rxidx = cur_rx->bge_idx; 3283 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3284 3285 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3286 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3287 have_tag = 1; 3288 vlan_tag = cur_rx->bge_vlan_tag; 3289 } 3290 3291 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3292 jumbocnt++; 3293 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3294 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3295 bge_rxreuse_jumbo(sc, rxidx); 3296 continue; 3297 } 3298 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3299 bge_rxreuse_jumbo(sc, rxidx); 3300 ifp->if_iqdrops++; 3301 continue; 3302 } 3303 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3304 } else { 3305 stdcnt++; 3306 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3307 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3308 bge_rxreuse_std(sc, rxidx); 3309 continue; 3310 } 3311 if (bge_newbuf_std(sc, rxidx) != 0) { 3312 bge_rxreuse_std(sc, rxidx); 3313 ifp->if_iqdrops++; 3314 continue; 3315 } 3316 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3317 } 3318 3319 ifp->if_ipackets++; 3320 #ifndef __NO_STRICT_ALIGNMENT 3321 /* 3322 * For architectures with strict alignment we must make sure 3323 * the payload is aligned. 3324 */ 3325 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3326 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3327 cur_rx->bge_len); 3328 m->m_data += ETHER_ALIGN; 3329 } 3330 #endif 3331 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3332 m->m_pkthdr.rcvif = ifp; 3333 3334 if (ifp->if_capenable & IFCAP_RXCSUM) { 3335 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3336 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3337 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3338 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3339 } 3340 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3341 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3342 m->m_pkthdr.csum_data = 3343 cur_rx->bge_tcp_udp_csum; 3344 m->m_pkthdr.csum_flags |= 3345 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3346 } 3347 } 3348 3349 /* 3350 * If we received a packet with a vlan tag, 3351 * attach that information to the packet. 3352 */ 3353 if (have_tag) { 3354 #if __FreeBSD_version > 700022 3355 m->m_pkthdr.ether_vtag = vlan_tag; 3356 m->m_flags |= M_VLANTAG; 3357 #else 3358 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3359 if (m == NULL) 3360 continue; 3361 #endif 3362 } 3363 3364 if (holdlck != 0) { 3365 BGE_UNLOCK(sc); 3366 (*ifp->if_input)(ifp, m); 3367 BGE_LOCK(sc); 3368 } else 3369 (*ifp->if_input)(ifp, m); 3370 rx_npkts++; 3371 3372 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3373 return (rx_npkts); 3374 } 3375 3376 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3377 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3378 if (stdcnt > 0) 3379 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3380 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3381 3382 if (jumbocnt > 0) 3383 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3384 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3385 3386 sc->bge_rx_saved_considx = rx_cons; 3387 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3388 if (stdcnt) 3389 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3390 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3391 if (jumbocnt) 3392 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3393 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3394 #ifdef notyet 3395 /* 3396 * This register wraps very quickly under heavy packet drops. 3397 * If you need correct statistics, you can enable this check. 3398 */ 3399 if (BGE_IS_5705_PLUS(sc)) 3400 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3401 #endif 3402 return (rx_npkts); 3403 } 3404 3405 static void 3406 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3407 { 3408 struct bge_tx_bd *cur_tx; 3409 struct ifnet *ifp; 3410 3411 BGE_LOCK_ASSERT(sc); 3412 3413 /* Nothing to do. */ 3414 if (sc->bge_tx_saved_considx == tx_cons) 3415 return; 3416 3417 ifp = sc->bge_ifp; 3418 3419 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3420 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3421 /* 3422 * Go through our tx ring and free mbufs for those 3423 * frames that have been sent. 3424 */ 3425 while (sc->bge_tx_saved_considx != tx_cons) { 3426 uint32_t idx; 3427 3428 idx = sc->bge_tx_saved_considx; 3429 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3430 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3431 ifp->if_opackets++; 3432 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3433 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3434 sc->bge_cdata.bge_tx_dmamap[idx], 3435 BUS_DMASYNC_POSTWRITE); 3436 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3437 sc->bge_cdata.bge_tx_dmamap[idx]); 3438 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3439 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3440 } 3441 sc->bge_txcnt--; 3442 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3443 } 3444 3445 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3446 if (sc->bge_txcnt == 0) 3447 sc->bge_timer = 0; 3448 } 3449 3450 #ifdef DEVICE_POLLING 3451 static int 3452 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3453 { 3454 struct bge_softc *sc = ifp->if_softc; 3455 uint16_t rx_prod, tx_cons; 3456 uint32_t statusword; 3457 int rx_npkts = 0; 3458 3459 BGE_LOCK(sc); 3460 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3461 BGE_UNLOCK(sc); 3462 return (rx_npkts); 3463 } 3464 3465 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3466 sc->bge_cdata.bge_status_map, 3467 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3468 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3469 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3470 3471 statusword = sc->bge_ldata.bge_status_block->bge_status; 3472 sc->bge_ldata.bge_status_block->bge_status = 0; 3473 3474 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3475 sc->bge_cdata.bge_status_map, 3476 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3477 3478 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3479 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3480 sc->bge_link_evt++; 3481 3482 if (cmd == POLL_AND_CHECK_STATUS) 3483 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3484 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3485 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3486 bge_link_upd(sc); 3487 3488 sc->rxcycles = count; 3489 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3490 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3491 BGE_UNLOCK(sc); 3492 return (rx_npkts); 3493 } 3494 bge_txeof(sc, tx_cons); 3495 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3496 bge_start_locked(ifp); 3497 3498 BGE_UNLOCK(sc); 3499 return (rx_npkts); 3500 } 3501 #endif /* DEVICE_POLLING */ 3502 3503 static int 3504 bge_msi_intr(void *arg) 3505 { 3506 struct bge_softc *sc; 3507 3508 sc = (struct bge_softc *)arg; 3509 /* 3510 * This interrupt is not shared and controller already 3511 * disabled further interrupt. 3512 */ 3513 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3514 return (FILTER_HANDLED); 3515 } 3516 3517 static void 3518 bge_intr_task(void *arg, int pending) 3519 { 3520 struct bge_softc *sc; 3521 struct ifnet *ifp; 3522 uint32_t status; 3523 uint16_t rx_prod, tx_cons; 3524 3525 sc = (struct bge_softc *)arg; 3526 ifp = sc->bge_ifp; 3527 3528 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3529 return; 3530 3531 /* Get updated status block. */ 3532 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3533 sc->bge_cdata.bge_status_map, 3534 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3535 3536 /* Save producer/consumer indexess. */ 3537 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3538 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3539 status = sc->bge_ldata.bge_status_block->bge_status; 3540 sc->bge_ldata.bge_status_block->bge_status = 0; 3541 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3542 sc->bge_cdata.bge_status_map, 3543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3544 /* Let controller work. */ 3545 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3546 3547 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) { 3548 BGE_LOCK(sc); 3549 bge_link_upd(sc); 3550 BGE_UNLOCK(sc); 3551 } 3552 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3553 /* Check RX return ring producer/consumer. */ 3554 bge_rxeof(sc, rx_prod, 0); 3555 } 3556 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3557 BGE_LOCK(sc); 3558 /* Check TX ring producer/consumer. */ 3559 bge_txeof(sc, tx_cons); 3560 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3561 bge_start_locked(ifp); 3562 BGE_UNLOCK(sc); 3563 } 3564 } 3565 3566 static void 3567 bge_intr(void *xsc) 3568 { 3569 struct bge_softc *sc; 3570 struct ifnet *ifp; 3571 uint32_t statusword; 3572 uint16_t rx_prod, tx_cons; 3573 3574 sc = xsc; 3575 3576 BGE_LOCK(sc); 3577 3578 ifp = sc->bge_ifp; 3579 3580 #ifdef DEVICE_POLLING 3581 if (ifp->if_capenable & IFCAP_POLLING) { 3582 BGE_UNLOCK(sc); 3583 return; 3584 } 3585 #endif 3586 3587 /* 3588 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3589 * disable interrupts by writing nonzero like we used to, since with 3590 * our current organization this just gives complications and 3591 * pessimizations for re-enabling interrupts. We used to have races 3592 * instead of the necessary complications. Disabling interrupts 3593 * would just reduce the chance of a status update while we are 3594 * running (by switching to the interrupt-mode coalescence 3595 * parameters), but this chance is already very low so it is more 3596 * efficient to get another interrupt than prevent it. 3597 * 3598 * We do the ack first to ensure another interrupt if there is a 3599 * status update after the ack. We don't check for the status 3600 * changing later because it is more efficient to get another 3601 * interrupt than prevent it, not quite as above (not checking is 3602 * a smaller optimization than not toggling the interrupt enable, 3603 * since checking doesn't involve PCI accesses and toggling require 3604 * the status check). So toggling would probably be a pessimization 3605 * even with MSI. It would only be needed for using a task queue. 3606 */ 3607 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3608 3609 /* 3610 * Do the mandatory PCI flush as well as get the link status. 3611 */ 3612 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3613 3614 /* Make sure the descriptor ring indexes are coherent. */ 3615 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3616 sc->bge_cdata.bge_status_map, 3617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3618 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3619 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3620 sc->bge_ldata.bge_status_block->bge_status = 0; 3621 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3622 sc->bge_cdata.bge_status_map, 3623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3624 3625 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3626 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3627 statusword || sc->bge_link_evt) 3628 bge_link_upd(sc); 3629 3630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3631 /* Check RX return ring producer/consumer. */ 3632 bge_rxeof(sc, rx_prod, 1); 3633 } 3634 3635 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3636 /* Check TX ring producer/consumer. */ 3637 bge_txeof(sc, tx_cons); 3638 } 3639 3640 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3641 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3642 bge_start_locked(ifp); 3643 3644 BGE_UNLOCK(sc); 3645 } 3646 3647 static void 3648 bge_asf_driver_up(struct bge_softc *sc) 3649 { 3650 if (sc->bge_asf_mode & ASF_STACKUP) { 3651 /* Send ASF heartbeat aprox. every 2s */ 3652 if (sc->bge_asf_count) 3653 sc->bge_asf_count --; 3654 else { 3655 sc->bge_asf_count = 2; 3656 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3657 BGE_FW_DRV_ALIVE); 3658 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3659 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3660 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3661 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3662 } 3663 } 3664 } 3665 3666 static void 3667 bge_tick(void *xsc) 3668 { 3669 struct bge_softc *sc = xsc; 3670 struct mii_data *mii = NULL; 3671 3672 BGE_LOCK_ASSERT(sc); 3673 3674 /* Synchronize with possible callout reset/stop. */ 3675 if (callout_pending(&sc->bge_stat_ch) || 3676 !callout_active(&sc->bge_stat_ch)) 3677 return; 3678 3679 if (BGE_IS_5705_PLUS(sc)) 3680 bge_stats_update_regs(sc); 3681 else 3682 bge_stats_update(sc); 3683 3684 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3685 mii = device_get_softc(sc->bge_miibus); 3686 /* 3687 * Do not touch PHY if we have link up. This could break 3688 * IPMI/ASF mode or produce extra input errors 3689 * (extra errors was reported for bcm5701 & bcm5704). 3690 */ 3691 if (!sc->bge_link) 3692 mii_tick(mii); 3693 } else { 3694 /* 3695 * Since in TBI mode auto-polling can't be used we should poll 3696 * link status manually. Here we register pending link event 3697 * and trigger interrupt. 3698 */ 3699 #ifdef DEVICE_POLLING 3700 /* In polling mode we poll link state in bge_poll(). */ 3701 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3702 #endif 3703 { 3704 sc->bge_link_evt++; 3705 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3706 sc->bge_flags & BGE_FLAG_5788) 3707 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3708 else 3709 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3710 } 3711 } 3712 3713 bge_asf_driver_up(sc); 3714 bge_watchdog(sc); 3715 3716 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3717 } 3718 3719 static void 3720 bge_stats_update_regs(struct bge_softc *sc) 3721 { 3722 struct ifnet *ifp; 3723 3724 ifp = sc->bge_ifp; 3725 3726 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3727 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3728 3729 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3730 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3731 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3732 } 3733 3734 static void 3735 bge_stats_update(struct bge_softc *sc) 3736 { 3737 struct ifnet *ifp; 3738 bus_size_t stats; 3739 uint32_t cnt; /* current register value */ 3740 3741 ifp = sc->bge_ifp; 3742 3743 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3744 3745 #define READ_STAT(sc, stats, stat) \ 3746 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3747 3748 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3749 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3750 sc->bge_tx_collisions = cnt; 3751 3752 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3753 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3754 sc->bge_rx_discards = cnt; 3755 3756 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3757 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3758 sc->bge_tx_discards = cnt; 3759 3760 #undef READ_STAT 3761 } 3762 3763 /* 3764 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3765 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3766 * but when such padded frames employ the bge IP/TCP checksum offload, 3767 * the hardware checksum assist gives incorrect results (possibly 3768 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3769 * If we pad such runts with zeros, the onboard checksum comes out correct. 3770 */ 3771 static __inline int 3772 bge_cksum_pad(struct mbuf *m) 3773 { 3774 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3775 struct mbuf *last; 3776 3777 /* If there's only the packet-header and we can pad there, use it. */ 3778 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3779 M_TRAILINGSPACE(m) >= padlen) { 3780 last = m; 3781 } else { 3782 /* 3783 * Walk packet chain to find last mbuf. We will either 3784 * pad there, or append a new mbuf and pad it. 3785 */ 3786 for (last = m; last->m_next != NULL; last = last->m_next); 3787 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3788 /* Allocate new empty mbuf, pad it. Compact later. */ 3789 struct mbuf *n; 3790 3791 MGET(n, M_DONTWAIT, MT_DATA); 3792 if (n == NULL) 3793 return (ENOBUFS); 3794 n->m_len = 0; 3795 last->m_next = n; 3796 last = n; 3797 } 3798 } 3799 3800 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3801 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3802 last->m_len += padlen; 3803 m->m_pkthdr.len += padlen; 3804 3805 return (0); 3806 } 3807 3808 static struct mbuf * 3809 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 3810 { 3811 struct ip *ip; 3812 struct tcphdr *tcp; 3813 struct mbuf *n; 3814 uint16_t hlen; 3815 uint32_t poff; 3816 3817 if (M_WRITABLE(m) == 0) { 3818 /* Get a writable copy. */ 3819 n = m_dup(m, M_DONTWAIT); 3820 m_freem(m); 3821 if (n == NULL) 3822 return (NULL); 3823 m = n; 3824 } 3825 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 3826 if (m == NULL) 3827 return (NULL); 3828 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 3829 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 3830 m = m_pullup(m, poff + sizeof(struct tcphdr)); 3831 if (m == NULL) 3832 return (NULL); 3833 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 3834 m = m_pullup(m, poff + (tcp->th_off << 2)); 3835 if (m == NULL) 3836 return (NULL); 3837 /* 3838 * It seems controller doesn't modify IP length and TCP pseudo 3839 * checksum. These checksum computed by upper stack should be 0. 3840 */ 3841 *mss = m->m_pkthdr.tso_segsz; 3842 ip->ip_sum = 0; 3843 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 3844 /* Clear pseudo checksum computed by TCP stack. */ 3845 tcp->th_sum = 0; 3846 /* 3847 * Broadcom controllers uses different descriptor format for 3848 * TSO depending on ASIC revision. Due to TSO-capable firmware 3849 * license issue and lower performance of firmware based TSO 3850 * we only support hardware based TSO which is applicable for 3851 * BCM5755 or newer controllers. Hardware based TSO uses 11 3852 * bits to store MSS and upper 5 bits are used to store IP/TCP 3853 * header length(including IP/TCP options). The header length 3854 * is expressed as 32 bits unit. 3855 */ 3856 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 3857 *mss |= (hlen << 11); 3858 return (m); 3859 } 3860 3861 /* 3862 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3863 * pointers to descriptors. 3864 */ 3865 static int 3866 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3867 { 3868 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3869 bus_dmamap_t map; 3870 struct bge_tx_bd *d; 3871 struct mbuf *m = *m_head; 3872 uint32_t idx = *txidx; 3873 uint16_t csum_flags, mss, vlan_tag; 3874 int nsegs, i, error; 3875 3876 csum_flags = 0; 3877 mss = 0; 3878 vlan_tag = 0; 3879 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 3880 *m_head = m = bge_setup_tso(sc, m, &mss); 3881 if (*m_head == NULL) 3882 return (ENOBUFS); 3883 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 3884 BGE_TXBDFLAG_CPU_POST_DMA; 3885 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 3886 if (m->m_pkthdr.csum_flags & CSUM_IP) 3887 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3888 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3889 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3890 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3891 (error = bge_cksum_pad(m)) != 0) { 3892 m_freem(m); 3893 *m_head = NULL; 3894 return (error); 3895 } 3896 } 3897 if (m->m_flags & M_LASTFRAG) 3898 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3899 else if (m->m_flags & M_FRAG) 3900 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3901 } 3902 3903 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3904 sc->bge_forced_collapse > 0 && 3905 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 3906 /* 3907 * Forcedly collapse mbuf chains to overcome hardware 3908 * limitation which only support a single outstanding 3909 * DMA read operation. 3910 */ 3911 if (sc->bge_forced_collapse == 1) 3912 m = m_defrag(m, M_DONTWAIT); 3913 else 3914 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse); 3915 if (m == NULL) 3916 m = *m_head; 3917 *m_head = m; 3918 } 3919 3920 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3921 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 3922 &nsegs, BUS_DMA_NOWAIT); 3923 if (error == EFBIG) { 3924 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3925 if (m == NULL) { 3926 m_freem(*m_head); 3927 *m_head = NULL; 3928 return (ENOBUFS); 3929 } 3930 *m_head = m; 3931 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 3932 m, segs, &nsegs, BUS_DMA_NOWAIT); 3933 if (error) { 3934 m_freem(m); 3935 *m_head = NULL; 3936 return (error); 3937 } 3938 } else if (error != 0) 3939 return (error); 3940 3941 /* Check if we have enough free send BDs. */ 3942 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 3943 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 3944 return (ENOBUFS); 3945 } 3946 3947 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3948 3949 #if __FreeBSD_version > 700022 3950 if (m->m_flags & M_VLANTAG) { 3951 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3952 vlan_tag = m->m_pkthdr.ether_vtag; 3953 } 3954 #else 3955 { 3956 struct m_tag *mtag; 3957 3958 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3959 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3960 vlan_tag = VLAN_TAG_VALUE(mtag); 3961 } 3962 } 3963 #endif 3964 for (i = 0; ; i++) { 3965 d = &sc->bge_ldata.bge_tx_ring[idx]; 3966 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3967 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3968 d->bge_len = segs[i].ds_len; 3969 d->bge_flags = csum_flags; 3970 d->bge_vlan_tag = vlan_tag; 3971 d->bge_mss = mss; 3972 if (i == nsegs - 1) 3973 break; 3974 BGE_INC(idx, BGE_TX_RING_CNT); 3975 } 3976 3977 /* Mark the last segment as end of packet... */ 3978 d->bge_flags |= BGE_TXBDFLAG_END; 3979 3980 /* 3981 * Insure that the map for this transmission 3982 * is placed at the array index of the last descriptor 3983 * in this chain. 3984 */ 3985 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3986 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3987 sc->bge_cdata.bge_tx_chain[idx] = m; 3988 sc->bge_txcnt += nsegs; 3989 3990 BGE_INC(idx, BGE_TX_RING_CNT); 3991 *txidx = idx; 3992 3993 return (0); 3994 } 3995 3996 /* 3997 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3998 * to the mbuf data regions directly in the transmit descriptors. 3999 */ 4000 static void 4001 bge_start_locked(struct ifnet *ifp) 4002 { 4003 struct bge_softc *sc; 4004 struct mbuf *m_head; 4005 uint32_t prodidx; 4006 int count; 4007 4008 sc = ifp->if_softc; 4009 BGE_LOCK_ASSERT(sc); 4010 4011 if (!sc->bge_link || 4012 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4013 IFF_DRV_RUNNING) 4014 return; 4015 4016 prodidx = sc->bge_tx_prodidx; 4017 4018 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4019 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4020 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4021 break; 4022 } 4023 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4024 if (m_head == NULL) 4025 break; 4026 4027 /* 4028 * XXX 4029 * The code inside the if() block is never reached since we 4030 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4031 * requests to checksum TCP/UDP in a fragmented packet. 4032 * 4033 * XXX 4034 * safety overkill. If this is a fragmented packet chain 4035 * with delayed TCP/UDP checksums, then only encapsulate 4036 * it if we have enough descriptors to handle the entire 4037 * chain at once. 4038 * (paranoia -- may not actually be needed) 4039 */ 4040 if (m_head->m_flags & M_FIRSTFRAG && 4041 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4042 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4043 m_head->m_pkthdr.csum_data + 16) { 4044 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4045 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4046 break; 4047 } 4048 } 4049 4050 /* 4051 * Pack the data into the transmit ring. If we 4052 * don't have room, set the OACTIVE flag and wait 4053 * for the NIC to drain the ring. 4054 */ 4055 if (bge_encap(sc, &m_head, &prodidx)) { 4056 if (m_head == NULL) 4057 break; 4058 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4059 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4060 break; 4061 } 4062 ++count; 4063 4064 /* 4065 * If there's a BPF listener, bounce a copy of this frame 4066 * to him. 4067 */ 4068 #ifdef ETHER_BPF_MTAP 4069 ETHER_BPF_MTAP(ifp, m_head); 4070 #else 4071 BPF_MTAP(ifp, m_head); 4072 #endif 4073 } 4074 4075 if (count > 0) { 4076 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4077 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4078 /* Transmit. */ 4079 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4080 /* 5700 b2 errata */ 4081 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4082 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4083 4084 sc->bge_tx_prodidx = prodidx; 4085 4086 /* 4087 * Set a timeout in case the chip goes out to lunch. 4088 */ 4089 sc->bge_timer = 5; 4090 } 4091 } 4092 4093 /* 4094 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4095 * to the mbuf data regions directly in the transmit descriptors. 4096 */ 4097 static void 4098 bge_start(struct ifnet *ifp) 4099 { 4100 struct bge_softc *sc; 4101 4102 sc = ifp->if_softc; 4103 BGE_LOCK(sc); 4104 bge_start_locked(ifp); 4105 BGE_UNLOCK(sc); 4106 } 4107 4108 static void 4109 bge_init_locked(struct bge_softc *sc) 4110 { 4111 struct ifnet *ifp; 4112 uint16_t *m; 4113 4114 BGE_LOCK_ASSERT(sc); 4115 4116 ifp = sc->bge_ifp; 4117 4118 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4119 return; 4120 4121 /* Cancel pending I/O and flush buffers. */ 4122 bge_stop(sc); 4123 4124 bge_stop_fw(sc); 4125 bge_sig_pre_reset(sc, BGE_RESET_START); 4126 bge_reset(sc); 4127 bge_sig_legacy(sc, BGE_RESET_START); 4128 bge_sig_post_reset(sc, BGE_RESET_START); 4129 4130 bge_chipinit(sc); 4131 4132 /* 4133 * Init the various state machines, ring 4134 * control blocks and firmware. 4135 */ 4136 if (bge_blockinit(sc)) { 4137 device_printf(sc->bge_dev, "initialization failure\n"); 4138 return; 4139 } 4140 4141 ifp = sc->bge_ifp; 4142 4143 /* Specify MTU. */ 4144 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4145 ETHER_HDR_LEN + ETHER_CRC_LEN + 4146 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4147 4148 /* Load our MAC address. */ 4149 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4150 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4151 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4152 4153 /* Program promiscuous mode. */ 4154 bge_setpromisc(sc); 4155 4156 /* Program multicast filter. */ 4157 bge_setmulti(sc); 4158 4159 /* Program VLAN tag stripping. */ 4160 bge_setvlan(sc); 4161 4162 /* Override UDP checksum offloading. */ 4163 if (sc->bge_forced_udpcsum == 0) 4164 sc->bge_csum_features &= ~CSUM_UDP; 4165 else 4166 sc->bge_csum_features |= CSUM_UDP; 4167 if (ifp->if_capabilities & IFCAP_TXCSUM && 4168 ifp->if_capenable & IFCAP_TXCSUM) { 4169 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4170 ifp->if_hwassist |= sc->bge_csum_features; 4171 } 4172 4173 /* Init RX ring. */ 4174 if (bge_init_rx_ring_std(sc) != 0) { 4175 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4176 bge_stop(sc); 4177 return; 4178 } 4179 4180 /* 4181 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4182 * memory to insure that the chip has in fact read the first 4183 * entry of the ring. 4184 */ 4185 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4186 uint32_t v, i; 4187 for (i = 0; i < 10; i++) { 4188 DELAY(20); 4189 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4190 if (v == (MCLBYTES - ETHER_ALIGN)) 4191 break; 4192 } 4193 if (i == 10) 4194 device_printf (sc->bge_dev, 4195 "5705 A0 chip failed to load RX ring\n"); 4196 } 4197 4198 /* Init jumbo RX ring. */ 4199 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4200 (MCLBYTES - ETHER_ALIGN)) { 4201 if (bge_init_rx_ring_jumbo(sc) != 0) { 4202 device_printf(sc->bge_dev, 4203 "no memory for jumbo Rx buffers.\n"); 4204 bge_stop(sc); 4205 return; 4206 } 4207 } 4208 4209 /* Init our RX return ring index. */ 4210 sc->bge_rx_saved_considx = 0; 4211 4212 /* Init our RX/TX stat counters. */ 4213 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4214 4215 /* Init TX ring. */ 4216 bge_init_tx_ring(sc); 4217 4218 /* Turn on transmitter. */ 4219 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4220 4221 /* Turn on receiver. */ 4222 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4223 4224 /* Tell firmware we're alive. */ 4225 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4226 4227 #ifdef DEVICE_POLLING 4228 /* Disable interrupts if we are polling. */ 4229 if (ifp->if_capenable & IFCAP_POLLING) { 4230 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4231 BGE_PCIMISCCTL_MASK_PCI_INTR); 4232 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4233 } else 4234 #endif 4235 4236 /* Enable host interrupts. */ 4237 { 4238 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4239 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4240 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4241 } 4242 4243 bge_ifmedia_upd_locked(ifp); 4244 4245 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4247 4248 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4249 } 4250 4251 static void 4252 bge_init(void *xsc) 4253 { 4254 struct bge_softc *sc = xsc; 4255 4256 BGE_LOCK(sc); 4257 bge_init_locked(sc); 4258 BGE_UNLOCK(sc); 4259 } 4260 4261 /* 4262 * Set media options. 4263 */ 4264 static int 4265 bge_ifmedia_upd(struct ifnet *ifp) 4266 { 4267 struct bge_softc *sc = ifp->if_softc; 4268 int res; 4269 4270 BGE_LOCK(sc); 4271 res = bge_ifmedia_upd_locked(ifp); 4272 BGE_UNLOCK(sc); 4273 4274 return (res); 4275 } 4276 4277 static int 4278 bge_ifmedia_upd_locked(struct ifnet *ifp) 4279 { 4280 struct bge_softc *sc = ifp->if_softc; 4281 struct mii_data *mii; 4282 struct mii_softc *miisc; 4283 struct ifmedia *ifm; 4284 4285 BGE_LOCK_ASSERT(sc); 4286 4287 ifm = &sc->bge_ifmedia; 4288 4289 /* If this is a 1000baseX NIC, enable the TBI port. */ 4290 if (sc->bge_flags & BGE_FLAG_TBI) { 4291 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4292 return (EINVAL); 4293 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4294 case IFM_AUTO: 4295 /* 4296 * The BCM5704 ASIC appears to have a special 4297 * mechanism for programming the autoneg 4298 * advertisement registers in TBI mode. 4299 */ 4300 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4301 uint32_t sgdig; 4302 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4303 if (sgdig & BGE_SGDIGSTS_DONE) { 4304 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4305 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4306 sgdig |= BGE_SGDIGCFG_AUTO | 4307 BGE_SGDIGCFG_PAUSE_CAP | 4308 BGE_SGDIGCFG_ASYM_PAUSE; 4309 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4310 sgdig | BGE_SGDIGCFG_SEND); 4311 DELAY(5); 4312 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4313 } 4314 } 4315 break; 4316 case IFM_1000_SX: 4317 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4318 BGE_CLRBIT(sc, BGE_MAC_MODE, 4319 BGE_MACMODE_HALF_DUPLEX); 4320 } else { 4321 BGE_SETBIT(sc, BGE_MAC_MODE, 4322 BGE_MACMODE_HALF_DUPLEX); 4323 } 4324 break; 4325 default: 4326 return (EINVAL); 4327 } 4328 return (0); 4329 } 4330 4331 sc->bge_link_evt++; 4332 mii = device_get_softc(sc->bge_miibus); 4333 if (mii->mii_instance) 4334 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4335 mii_phy_reset(miisc); 4336 mii_mediachg(mii); 4337 4338 /* 4339 * Force an interrupt so that we will call bge_link_upd 4340 * if needed and clear any pending link state attention. 4341 * Without this we are not getting any further interrupts 4342 * for link state changes and thus will not UP the link and 4343 * not be able to send in bge_start_locked. The only 4344 * way to get things working was to receive a packet and 4345 * get an RX intr. 4346 * bge_tick should help for fiber cards and we might not 4347 * need to do this here if BGE_FLAG_TBI is set but as 4348 * we poll for fiber anyway it should not harm. 4349 */ 4350 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4351 sc->bge_flags & BGE_FLAG_5788) 4352 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4353 else 4354 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4355 4356 return (0); 4357 } 4358 4359 /* 4360 * Report current media status. 4361 */ 4362 static void 4363 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4364 { 4365 struct bge_softc *sc = ifp->if_softc; 4366 struct mii_data *mii; 4367 4368 BGE_LOCK(sc); 4369 4370 if (sc->bge_flags & BGE_FLAG_TBI) { 4371 ifmr->ifm_status = IFM_AVALID; 4372 ifmr->ifm_active = IFM_ETHER; 4373 if (CSR_READ_4(sc, BGE_MAC_STS) & 4374 BGE_MACSTAT_TBI_PCS_SYNCHED) 4375 ifmr->ifm_status |= IFM_ACTIVE; 4376 else { 4377 ifmr->ifm_active |= IFM_NONE; 4378 BGE_UNLOCK(sc); 4379 return; 4380 } 4381 ifmr->ifm_active |= IFM_1000_SX; 4382 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4383 ifmr->ifm_active |= IFM_HDX; 4384 else 4385 ifmr->ifm_active |= IFM_FDX; 4386 BGE_UNLOCK(sc); 4387 return; 4388 } 4389 4390 mii = device_get_softc(sc->bge_miibus); 4391 mii_pollstat(mii); 4392 ifmr->ifm_active = mii->mii_media_active; 4393 ifmr->ifm_status = mii->mii_media_status; 4394 4395 BGE_UNLOCK(sc); 4396 } 4397 4398 static int 4399 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4400 { 4401 struct bge_softc *sc = ifp->if_softc; 4402 struct ifreq *ifr = (struct ifreq *) data; 4403 struct mii_data *mii; 4404 int flags, mask, error = 0; 4405 4406 switch (command) { 4407 case SIOCSIFMTU: 4408 if (ifr->ifr_mtu < ETHERMIN || 4409 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4410 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4411 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4412 ifr->ifr_mtu > ETHERMTU)) 4413 error = EINVAL; 4414 else if (ifp->if_mtu != ifr->ifr_mtu) { 4415 ifp->if_mtu = ifr->ifr_mtu; 4416 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4417 bge_init(sc); 4418 } 4419 break; 4420 case SIOCSIFFLAGS: 4421 BGE_LOCK(sc); 4422 if (ifp->if_flags & IFF_UP) { 4423 /* 4424 * If only the state of the PROMISC flag changed, 4425 * then just use the 'set promisc mode' command 4426 * instead of reinitializing the entire NIC. Doing 4427 * a full re-init means reloading the firmware and 4428 * waiting for it to start up, which may take a 4429 * second or two. Similarly for ALLMULTI. 4430 */ 4431 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4432 flags = ifp->if_flags ^ sc->bge_if_flags; 4433 if (flags & IFF_PROMISC) 4434 bge_setpromisc(sc); 4435 if (flags & IFF_ALLMULTI) 4436 bge_setmulti(sc); 4437 } else 4438 bge_init_locked(sc); 4439 } else { 4440 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4441 bge_stop(sc); 4442 } 4443 } 4444 sc->bge_if_flags = ifp->if_flags; 4445 BGE_UNLOCK(sc); 4446 error = 0; 4447 break; 4448 case SIOCADDMULTI: 4449 case SIOCDELMULTI: 4450 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4451 BGE_LOCK(sc); 4452 bge_setmulti(sc); 4453 BGE_UNLOCK(sc); 4454 error = 0; 4455 } 4456 break; 4457 case SIOCSIFMEDIA: 4458 case SIOCGIFMEDIA: 4459 if (sc->bge_flags & BGE_FLAG_TBI) { 4460 error = ifmedia_ioctl(ifp, ifr, 4461 &sc->bge_ifmedia, command); 4462 } else { 4463 mii = device_get_softc(sc->bge_miibus); 4464 error = ifmedia_ioctl(ifp, ifr, 4465 &mii->mii_media, command); 4466 } 4467 break; 4468 case SIOCSIFCAP: 4469 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4470 #ifdef DEVICE_POLLING 4471 if (mask & IFCAP_POLLING) { 4472 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4473 error = ether_poll_register(bge_poll, ifp); 4474 if (error) 4475 return (error); 4476 BGE_LOCK(sc); 4477 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4478 BGE_PCIMISCCTL_MASK_PCI_INTR); 4479 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4480 ifp->if_capenable |= IFCAP_POLLING; 4481 BGE_UNLOCK(sc); 4482 } else { 4483 error = ether_poll_deregister(ifp); 4484 /* Enable interrupt even in error case */ 4485 BGE_LOCK(sc); 4486 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4487 BGE_PCIMISCCTL_MASK_PCI_INTR); 4488 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4489 ifp->if_capenable &= ~IFCAP_POLLING; 4490 BGE_UNLOCK(sc); 4491 } 4492 } 4493 #endif 4494 if (mask & IFCAP_HWCSUM) { 4495 ifp->if_capenable ^= IFCAP_HWCSUM; 4496 if (IFCAP_HWCSUM & ifp->if_capenable && 4497 IFCAP_HWCSUM & ifp->if_capabilities) 4498 ifp->if_hwassist |= sc->bge_csum_features; 4499 else 4500 ifp->if_hwassist &= ~sc->bge_csum_features; 4501 } 4502 4503 if ((mask & IFCAP_TSO4) != 0 && 4504 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4505 ifp->if_capenable ^= IFCAP_TSO4; 4506 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4507 ifp->if_hwassist |= CSUM_TSO; 4508 else 4509 ifp->if_hwassist &= ~CSUM_TSO; 4510 } 4511 4512 if (mask & IFCAP_VLAN_MTU) { 4513 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4514 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4515 bge_init(sc); 4516 } 4517 4518 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 4519 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 4520 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 4521 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 4522 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 4523 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4524 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 4525 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 4526 BGE_LOCK(sc); 4527 bge_setvlan(sc); 4528 BGE_UNLOCK(sc); 4529 } 4530 #ifdef VLAN_CAPABILITIES 4531 VLAN_CAPABILITIES(ifp); 4532 #endif 4533 break; 4534 default: 4535 error = ether_ioctl(ifp, command, data); 4536 break; 4537 } 4538 4539 return (error); 4540 } 4541 4542 static void 4543 bge_watchdog(struct bge_softc *sc) 4544 { 4545 struct ifnet *ifp; 4546 4547 BGE_LOCK_ASSERT(sc); 4548 4549 if (sc->bge_timer == 0 || --sc->bge_timer) 4550 return; 4551 4552 ifp = sc->bge_ifp; 4553 4554 if_printf(ifp, "watchdog timeout -- resetting\n"); 4555 4556 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4557 bge_init_locked(sc); 4558 4559 ifp->if_oerrors++; 4560 } 4561 4562 /* 4563 * Stop the adapter and free any mbufs allocated to the 4564 * RX and TX lists. 4565 */ 4566 static void 4567 bge_stop(struct bge_softc *sc) 4568 { 4569 struct ifnet *ifp; 4570 4571 BGE_LOCK_ASSERT(sc); 4572 4573 ifp = sc->bge_ifp; 4574 4575 callout_stop(&sc->bge_stat_ch); 4576 4577 /* Disable host interrupts. */ 4578 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4579 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4580 4581 /* 4582 * Tell firmware we're shutting down. 4583 */ 4584 bge_stop_fw(sc); 4585 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4586 4587 /* 4588 * Disable all of the receiver blocks. 4589 */ 4590 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4591 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4592 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4593 if (!(BGE_IS_5705_PLUS(sc))) 4594 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4595 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4596 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4597 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4598 4599 /* 4600 * Disable all of the transmit blocks. 4601 */ 4602 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4603 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4604 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4605 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4606 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4607 if (!(BGE_IS_5705_PLUS(sc))) 4608 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4609 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4610 4611 /* 4612 * Shut down all of the memory managers and related 4613 * state machines. 4614 */ 4615 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4616 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4617 if (!(BGE_IS_5705_PLUS(sc))) 4618 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4619 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4620 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4621 if (!(BGE_IS_5705_PLUS(sc))) { 4622 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4623 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4624 } 4625 4626 bge_reset(sc); 4627 bge_sig_legacy(sc, BGE_RESET_STOP); 4628 bge_sig_post_reset(sc, BGE_RESET_STOP); 4629 4630 /* 4631 * Keep the ASF firmware running if up. 4632 */ 4633 if (sc->bge_asf_mode & ASF_STACKUP) 4634 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4635 else 4636 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4637 4638 /* Free the RX lists. */ 4639 bge_free_rx_ring_std(sc); 4640 4641 /* Free jumbo RX list. */ 4642 if (BGE_IS_JUMBO_CAPABLE(sc)) 4643 bge_free_rx_ring_jumbo(sc); 4644 4645 /* Free TX buffers. */ 4646 bge_free_tx_ring(sc); 4647 4648 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4649 4650 /* Clear MAC's link state (PHY may still have link UP). */ 4651 if (bootverbose && sc->bge_link) 4652 if_printf(sc->bge_ifp, "link DOWN\n"); 4653 sc->bge_link = 0; 4654 4655 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4656 } 4657 4658 /* 4659 * Stop all chip I/O so that the kernel's probe routines don't 4660 * get confused by errant DMAs when rebooting. 4661 */ 4662 static int 4663 bge_shutdown(device_t dev) 4664 { 4665 struct bge_softc *sc; 4666 4667 sc = device_get_softc(dev); 4668 BGE_LOCK(sc); 4669 bge_stop(sc); 4670 bge_reset(sc); 4671 BGE_UNLOCK(sc); 4672 4673 return (0); 4674 } 4675 4676 static int 4677 bge_suspend(device_t dev) 4678 { 4679 struct bge_softc *sc; 4680 4681 sc = device_get_softc(dev); 4682 BGE_LOCK(sc); 4683 bge_stop(sc); 4684 BGE_UNLOCK(sc); 4685 4686 return (0); 4687 } 4688 4689 static int 4690 bge_resume(device_t dev) 4691 { 4692 struct bge_softc *sc; 4693 struct ifnet *ifp; 4694 4695 sc = device_get_softc(dev); 4696 BGE_LOCK(sc); 4697 ifp = sc->bge_ifp; 4698 if (ifp->if_flags & IFF_UP) { 4699 bge_init_locked(sc); 4700 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4701 bge_start_locked(ifp); 4702 } 4703 BGE_UNLOCK(sc); 4704 4705 return (0); 4706 } 4707 4708 static void 4709 bge_link_upd(struct bge_softc *sc) 4710 { 4711 struct mii_data *mii; 4712 uint32_t link, status; 4713 4714 BGE_LOCK_ASSERT(sc); 4715 4716 /* Clear 'pending link event' flag. */ 4717 sc->bge_link_evt = 0; 4718 4719 /* 4720 * Process link state changes. 4721 * Grrr. The link status word in the status block does 4722 * not work correctly on the BCM5700 rev AX and BX chips, 4723 * according to all available information. Hence, we have 4724 * to enable MII interrupts in order to properly obtain 4725 * async link changes. Unfortunately, this also means that 4726 * we have to read the MAC status register to detect link 4727 * changes, thereby adding an additional register access to 4728 * the interrupt handler. 4729 * 4730 * XXX: perhaps link state detection procedure used for 4731 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4732 */ 4733 4734 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4735 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4736 status = CSR_READ_4(sc, BGE_MAC_STS); 4737 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4738 mii = device_get_softc(sc->bge_miibus); 4739 mii_pollstat(mii); 4740 if (!sc->bge_link && 4741 mii->mii_media_status & IFM_ACTIVE && 4742 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4743 sc->bge_link++; 4744 if (bootverbose) 4745 if_printf(sc->bge_ifp, "link UP\n"); 4746 } else if (sc->bge_link && 4747 (!(mii->mii_media_status & IFM_ACTIVE) || 4748 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4749 sc->bge_link = 0; 4750 if (bootverbose) 4751 if_printf(sc->bge_ifp, "link DOWN\n"); 4752 } 4753 4754 /* Clear the interrupt. */ 4755 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4756 BGE_EVTENB_MI_INTERRUPT); 4757 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4758 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4759 BRGPHY_INTRS); 4760 } 4761 return; 4762 } 4763 4764 if (sc->bge_flags & BGE_FLAG_TBI) { 4765 status = CSR_READ_4(sc, BGE_MAC_STS); 4766 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4767 if (!sc->bge_link) { 4768 sc->bge_link++; 4769 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4770 BGE_CLRBIT(sc, BGE_MAC_MODE, 4771 BGE_MACMODE_TBI_SEND_CFGS); 4772 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4773 if (bootverbose) 4774 if_printf(sc->bge_ifp, "link UP\n"); 4775 if_link_state_change(sc->bge_ifp, 4776 LINK_STATE_UP); 4777 } 4778 } else if (sc->bge_link) { 4779 sc->bge_link = 0; 4780 if (bootverbose) 4781 if_printf(sc->bge_ifp, "link DOWN\n"); 4782 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4783 } 4784 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4785 /* 4786 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4787 * in status word always set. Workaround this bug by reading 4788 * PHY link status directly. 4789 */ 4790 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4791 4792 if (link != sc->bge_link || 4793 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4794 mii = device_get_softc(sc->bge_miibus); 4795 mii_pollstat(mii); 4796 if (!sc->bge_link && 4797 mii->mii_media_status & IFM_ACTIVE && 4798 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4799 sc->bge_link++; 4800 if (bootverbose) 4801 if_printf(sc->bge_ifp, "link UP\n"); 4802 } else if (sc->bge_link && 4803 (!(mii->mii_media_status & IFM_ACTIVE) || 4804 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4805 sc->bge_link = 0; 4806 if (bootverbose) 4807 if_printf(sc->bge_ifp, "link DOWN\n"); 4808 } 4809 } 4810 } else { 4811 /* 4812 * Discard link events for MII/GMII controllers 4813 * if MI auto-polling is disabled. 4814 */ 4815 } 4816 4817 /* Clear the attention. */ 4818 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4819 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4820 BGE_MACSTAT_LINK_CHANGED); 4821 } 4822 4823 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4824 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4825 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4826 desc) 4827 4828 static void 4829 bge_add_sysctls(struct bge_softc *sc) 4830 { 4831 struct sysctl_ctx_list *ctx; 4832 struct sysctl_oid_list *children, *schildren; 4833 struct sysctl_oid *tree; 4834 char tn[32]; 4835 int unit; 4836 4837 ctx = device_get_sysctl_ctx(sc->bge_dev); 4838 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4839 4840 #ifdef BGE_REGISTER_DEBUG 4841 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4842 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4843 "Debug Information"); 4844 4845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4846 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4847 "Register Read"); 4848 4849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4850 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4851 "Memory Read"); 4852 4853 #endif 4854 4855 unit = device_get_unit(sc->bge_dev); 4856 /* 4857 * A common design characteristic for many Broadcom client controllers 4858 * is that they only support a single outstanding DMA read operation 4859 * on the PCIe bus. This means that it will take twice as long to fetch 4860 * a TX frame that is split into header and payload buffers as it does 4861 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 4862 * these controllers, coalescing buffers to reduce the number of memory 4863 * reads is effective way to get maximum performance(about 940Mbps). 4864 * Without collapsing TX buffers the maximum TCP bulk transfer 4865 * performance is about 850Mbps. However forcing coalescing mbufs 4866 * consumes a lot of CPU cycles, so leave it off by default. 4867 */ 4868 sc->bge_forced_collapse = 0; 4869 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 4870 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 4871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 4872 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 4873 "Number of fragmented TX buffers of a frame allowed before " 4874 "forced collapsing"); 4875 4876 /* 4877 * It seems all Broadcom controllers have a bug that can generate UDP 4878 * datagrams with checksum value 0 when TX UDP checksum offloading is 4879 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 4880 * Even though the probability of generating such UDP datagrams is 4881 * low, I don't want to see FreeBSD boxes to inject such datagrams 4882 * into network so disable UDP checksum offloading by default. Users 4883 * still override this behavior by setting a sysctl variable, 4884 * dev.bge.0.forced_udpcsum. 4885 */ 4886 sc->bge_forced_udpcsum = 0; 4887 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 4888 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 4889 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 4890 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 4891 "Enable UDP checksum offloading even if controller can " 4892 "generate UDP checksum value 0"); 4893 4894 if (BGE_IS_5705_PLUS(sc)) 4895 return; 4896 4897 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4898 NULL, "BGE Statistics"); 4899 schildren = children = SYSCTL_CHILDREN(tree); 4900 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4901 children, COSFramesDroppedDueToFilters, 4902 "FramesDroppedDueToFilters"); 4903 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4904 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4905 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4906 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4907 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4908 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4909 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4910 children, ifInDiscards, "InputDiscards"); 4911 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4912 children, ifInErrors, "InputErrors"); 4913 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4914 children, nicRecvThresholdHit, "RecvThresholdHit"); 4915 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4916 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4917 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4918 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4919 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4920 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4921 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4922 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4923 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4924 children, nicRingStatusUpdate, "RingStatusUpdate"); 4925 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4926 children, nicInterrupts, "Interrupts"); 4927 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4928 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4929 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4930 children, nicSendThresholdHit, "SendThresholdHit"); 4931 4932 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4933 NULL, "BGE RX Statistics"); 4934 children = SYSCTL_CHILDREN(tree); 4935 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4936 children, rxstats.ifHCInOctets, "Octets"); 4937 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4938 children, rxstats.etherStatsFragments, "Fragments"); 4939 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4940 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4941 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4942 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4943 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4944 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4945 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4946 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4947 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4948 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4949 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4950 children, rxstats.xoffPauseFramesReceived, 4951 "xoffPauseFramesReceived"); 4952 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4953 children, rxstats.macControlFramesReceived, 4954 "ControlFramesReceived"); 4955 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4956 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4957 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4958 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4959 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4960 children, rxstats.etherStatsJabbers, "Jabbers"); 4961 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4962 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4963 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4964 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4965 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4966 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4967 4968 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4969 NULL, "BGE TX Statistics"); 4970 children = SYSCTL_CHILDREN(tree); 4971 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4972 children, txstats.ifHCOutOctets, "Octets"); 4973 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4974 children, txstats.etherStatsCollisions, "Collisions"); 4975 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4976 children, txstats.outXonSent, "XonSent"); 4977 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4978 children, txstats.outXoffSent, "XoffSent"); 4979 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4980 children, txstats.flowControlDone, "flowControlDone"); 4981 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4982 children, txstats.dot3StatsInternalMacTransmitErrors, 4983 "InternalMacTransmitErrors"); 4984 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4985 children, txstats.dot3StatsSingleCollisionFrames, 4986 "SingleCollisionFrames"); 4987 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4988 children, txstats.dot3StatsMultipleCollisionFrames, 4989 "MultipleCollisionFrames"); 4990 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4991 children, txstats.dot3StatsDeferredTransmissions, 4992 "DeferredTransmissions"); 4993 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4994 children, txstats.dot3StatsExcessiveCollisions, 4995 "ExcessiveCollisions"); 4996 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4997 children, txstats.dot3StatsLateCollisions, 4998 "LateCollisions"); 4999 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5000 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 5001 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5002 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5003 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5004 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5005 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5006 children, txstats.dot3StatsCarrierSenseErrors, 5007 "CarrierSenseErrors"); 5008 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5009 children, txstats.ifOutDiscards, "Discards"); 5010 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5011 children, txstats.ifOutErrors, "Errors"); 5012 } 5013 5014 static int 5015 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5016 { 5017 struct bge_softc *sc; 5018 uint32_t result; 5019 int offset; 5020 5021 sc = (struct bge_softc *)arg1; 5022 offset = arg2; 5023 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5024 offsetof(bge_hostaddr, bge_addr_lo)); 5025 return (sysctl_handle_int(oidp, &result, 0, req)); 5026 } 5027 5028 #ifdef BGE_REGISTER_DEBUG 5029 static int 5030 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5031 { 5032 struct bge_softc *sc; 5033 uint16_t *sbdata; 5034 int error; 5035 int result; 5036 int i, j; 5037 5038 result = -1; 5039 error = sysctl_handle_int(oidp, &result, 0, req); 5040 if (error || (req->newptr == NULL)) 5041 return (error); 5042 5043 if (result == 1) { 5044 sc = (struct bge_softc *)arg1; 5045 5046 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5047 printf("Status Block:\n"); 5048 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5049 printf("%06x:", i); 5050 for (j = 0; j < 8; j++) { 5051 printf(" %04x", sbdata[i]); 5052 i += 4; 5053 } 5054 printf("\n"); 5055 } 5056 5057 printf("Registers:\n"); 5058 for (i = 0x800; i < 0xA00; ) { 5059 printf("%06x:", i); 5060 for (j = 0; j < 8; j++) { 5061 printf(" %08x", CSR_READ_4(sc, i)); 5062 i += 4; 5063 } 5064 printf("\n"); 5065 } 5066 5067 printf("Hardware Flags:\n"); 5068 if (BGE_IS_5755_PLUS(sc)) 5069 printf(" - 5755 Plus\n"); 5070 if (BGE_IS_575X_PLUS(sc)) 5071 printf(" - 575X Plus\n"); 5072 if (BGE_IS_5705_PLUS(sc)) 5073 printf(" - 5705 Plus\n"); 5074 if (BGE_IS_5714_FAMILY(sc)) 5075 printf(" - 5714 Family\n"); 5076 if (BGE_IS_5700_FAMILY(sc)) 5077 printf(" - 5700 Family\n"); 5078 if (sc->bge_flags & BGE_FLAG_JUMBO) 5079 printf(" - Supports Jumbo Frames\n"); 5080 if (sc->bge_flags & BGE_FLAG_PCIX) 5081 printf(" - PCI-X Bus\n"); 5082 if (sc->bge_flags & BGE_FLAG_PCIE) 5083 printf(" - PCI Express Bus\n"); 5084 if (sc->bge_flags & BGE_FLAG_NO_3LED) 5085 printf(" - No 3 LEDs\n"); 5086 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5087 printf(" - RX Alignment Bug\n"); 5088 } 5089 5090 return (error); 5091 } 5092 5093 static int 5094 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5095 { 5096 struct bge_softc *sc; 5097 int error; 5098 uint16_t result; 5099 uint32_t val; 5100 5101 result = -1; 5102 error = sysctl_handle_int(oidp, &result, 0, req); 5103 if (error || (req->newptr == NULL)) 5104 return (error); 5105 5106 if (result < 0x8000) { 5107 sc = (struct bge_softc *)arg1; 5108 val = CSR_READ_4(sc, result); 5109 printf("reg 0x%06X = 0x%08X\n", result, val); 5110 } 5111 5112 return (error); 5113 } 5114 5115 static int 5116 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5117 { 5118 struct bge_softc *sc; 5119 int error; 5120 uint16_t result; 5121 uint32_t val; 5122 5123 result = -1; 5124 error = sysctl_handle_int(oidp, &result, 0, req); 5125 if (error || (req->newptr == NULL)) 5126 return (error); 5127 5128 if (result < 0x8000) { 5129 sc = (struct bge_softc *)arg1; 5130 val = bge_readmem_ind(sc, result); 5131 printf("mem 0x%06X = 0x%08X\n", result, val); 5132 } 5133 5134 return (error); 5135 } 5136 #endif 5137 5138 static int 5139 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5140 { 5141 5142 if (sc->bge_flags & BGE_FLAG_EADDR) 5143 return (1); 5144 5145 #ifdef __sparc64__ 5146 OF_getetheraddr(sc->bge_dev, ether_addr); 5147 return (0); 5148 #endif 5149 return (1); 5150 } 5151 5152 static int 5153 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5154 { 5155 uint32_t mac_addr; 5156 5157 mac_addr = bge_readmem_ind(sc, 0x0c14); 5158 if ((mac_addr >> 16) == 0x484b) { 5159 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5160 ether_addr[1] = (uint8_t)mac_addr; 5161 mac_addr = bge_readmem_ind(sc, 0x0c18); 5162 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5163 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5164 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5165 ether_addr[5] = (uint8_t)mac_addr; 5166 return (0); 5167 } 5168 return (1); 5169 } 5170 5171 static int 5172 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5173 { 5174 int mac_offset = BGE_EE_MAC_OFFSET; 5175 5176 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5177 mac_offset = BGE_EE_MAC_OFFSET_5906; 5178 5179 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5180 ETHER_ADDR_LEN)); 5181 } 5182 5183 static int 5184 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5185 { 5186 5187 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5188 return (1); 5189 5190 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5191 ETHER_ADDR_LEN)); 5192 } 5193 5194 static int 5195 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5196 { 5197 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5198 /* NOTE: Order is critical */ 5199 bge_get_eaddr_fw, 5200 bge_get_eaddr_mem, 5201 bge_get_eaddr_nvram, 5202 bge_get_eaddr_eeprom, 5203 NULL 5204 }; 5205 const bge_eaddr_fcn_t *func; 5206 5207 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5208 if ((*func)(sc, eaddr) == 0) 5209 break; 5210 } 5211 return (*func == NULL ? ENXIO : 0); 5212 } 5213