1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 36 * 37 * The Broadcom BCM5700 is based on technology originally developed by 38 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 39 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 40 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 41 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 42 * frames, highly configurable RX filtering, and 16 RX and TX queues 43 * (which, along with RX filter rules, can be used for QOS applications). 44 * Other features, such as TCP segmentation, may be available as part 45 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 46 * firmware images can be stored in hardware and need not be compiled 47 * into the driver. 48 * 49 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 50 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 51 * 52 * The BCM5701 is a single-chip solution incorporating both the BCM5700 53 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 54 * does not support external SSRAM. 55 * 56 * Broadcom also produces a variation of the BCM5700 under the "Altima" 57 * brand name, which is functionally similar but lacks PCI-X support. 58 * 59 * Without external SSRAM, you can only have at most 4 TX rings, 60 * and the use of the mini RX ring is disabled. This seems to imply 61 * that these features are simply not available on the BCM5701. As a 62 * result, this driver does not implement any support for the mini RX 63 * ring. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD$"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <netinet/in_systm.h> 90 #include <netinet/in.h> 91 #include <netinet/ip.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 #include "miidevs.h" 105 #include <dev/mii/brgphyreg.h> 106 107 #include <pci/pcireg.h> 108 #include <pci/pcivar.h> 109 110 #include <dev/bge/if_bgereg.h> 111 112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 113 114 MODULE_DEPEND(bge, miibus, 1, 1, 1); 115 116 /* "controller miibus0" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 /* 120 * Various supported device vendors/types and their names. Note: the 121 * spec seems to indicate that the hardware still has Alteon's vendor 122 * ID burned into it, though it will always be overriden by the vendor 123 * ID in the EEPROM. Just to be safe, we cover all possibilities. 124 */ 125 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 126 127 static struct bge_type bge_devs[] = { 128 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 129 "Broadcom BCM5700 Gigabit Ethernet" }, 130 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 131 "Broadcom BCM5701 Gigabit Ethernet" }, 132 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 137 "Broadcom BCM5702X Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 139 "Broadcom BCM5703X Gigabit Ethernet" }, 140 { SK_VENDORID, SK_DEVICEID_ALTIMA, 141 "SysKonnect Gigabit Ethernet" }, 142 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 143 "Altima AC1000 Gigabit Ethernet" }, 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 145 "Altima AC9100 Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int bge_probe (device_t); 150 static int bge_attach (device_t); 151 static int bge_detach (device_t); 152 static void bge_release_resources 153 (struct bge_softc *); 154 static void bge_txeof (struct bge_softc *); 155 static void bge_rxeof (struct bge_softc *); 156 157 static void bge_tick (void *); 158 static void bge_stats_update (struct bge_softc *); 159 static int bge_encap (struct bge_softc *, struct mbuf *, 160 u_int32_t *); 161 162 static void bge_intr (void *); 163 static void bge_start (struct ifnet *); 164 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 165 static void bge_init (void *); 166 static void bge_stop (struct bge_softc *); 167 static void bge_watchdog (struct ifnet *); 168 static void bge_shutdown (device_t); 169 static int bge_ifmedia_upd (struct ifnet *); 170 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 171 172 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 173 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 174 175 static u_int32_t bge_crc (caddr_t); 176 static void bge_setmulti (struct bge_softc *); 177 178 static void bge_handle_events (struct bge_softc *); 179 static int bge_alloc_jumbo_mem (struct bge_softc *); 180 static void bge_free_jumbo_mem (struct bge_softc *); 181 static void *bge_jalloc (struct bge_softc *); 182 static void bge_jfree (void *, void *); 183 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 184 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 185 static int bge_init_rx_ring_std (struct bge_softc *); 186 static void bge_free_rx_ring_std (struct bge_softc *); 187 static int bge_init_rx_ring_jumbo (struct bge_softc *); 188 static void bge_free_rx_ring_jumbo (struct bge_softc *); 189 static void bge_free_tx_ring (struct bge_softc *); 190 static int bge_init_tx_ring (struct bge_softc *); 191 192 static int bge_chipinit (struct bge_softc *); 193 static int bge_blockinit (struct bge_softc *); 194 195 #ifdef notdef 196 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 197 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 198 static void bge_vpd_read (struct bge_softc *); 199 #endif 200 201 static u_int32_t bge_readmem_ind 202 (struct bge_softc *, int); 203 static void bge_writemem_ind (struct bge_softc *, int, int); 204 #ifdef notdef 205 static u_int32_t bge_readreg_ind 206 (struct bge_softc *, int); 207 #endif 208 static void bge_writereg_ind (struct bge_softc *, int, int); 209 210 static int bge_miibus_readreg (device_t, int, int); 211 static int bge_miibus_writereg (device_t, int, int, int); 212 static void bge_miibus_statchg (device_t); 213 214 static void bge_reset (struct bge_softc *); 215 static void bge_phy_hack (struct bge_softc *); 216 217 static device_method_t bge_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, bge_probe), 220 DEVMETHOD(device_attach, bge_attach), 221 DEVMETHOD(device_detach, bge_detach), 222 DEVMETHOD(device_shutdown, bge_shutdown), 223 224 /* bus interface */ 225 DEVMETHOD(bus_print_child, bus_generic_print_child), 226 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 227 228 /* MII interface */ 229 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 230 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 231 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 232 233 { 0, 0 } 234 }; 235 236 static driver_t bge_driver = { 237 "bge", 238 bge_methods, 239 sizeof(struct bge_softc) 240 }; 241 242 static devclass_t bge_devclass; 243 244 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 245 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 246 247 static u_int32_t 248 bge_readmem_ind(sc, off) 249 struct bge_softc *sc; 250 int off; 251 { 252 device_t dev; 253 254 dev = sc->bge_dev; 255 256 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 257 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 258 } 259 260 static void 261 bge_writemem_ind(sc, off, val) 262 struct bge_softc *sc; 263 int off, val; 264 { 265 device_t dev; 266 267 dev = sc->bge_dev; 268 269 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 270 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 271 272 return; 273 } 274 275 #ifdef notdef 276 static u_int32_t 277 bge_readreg_ind(sc, off) 278 struct bge_softc *sc; 279 int off; 280 { 281 device_t dev; 282 283 dev = sc->bge_dev; 284 285 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 286 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 287 } 288 #endif 289 290 static void 291 bge_writereg_ind(sc, off, val) 292 struct bge_softc *sc; 293 int off, val; 294 { 295 device_t dev; 296 297 dev = sc->bge_dev; 298 299 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 300 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 301 302 return; 303 } 304 305 #ifdef notdef 306 static u_int8_t 307 bge_vpd_readbyte(sc, addr) 308 struct bge_softc *sc; 309 int addr; 310 { 311 int i; 312 device_t dev; 313 u_int32_t val; 314 315 dev = sc->bge_dev; 316 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 317 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 318 DELAY(10); 319 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 320 break; 321 } 322 323 if (i == BGE_TIMEOUT) { 324 printf("bge%d: VPD read timed out\n", sc->bge_unit); 325 return(0); 326 } 327 328 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 329 330 return((val >> ((addr % 4) * 8)) & 0xFF); 331 } 332 333 static void 334 bge_vpd_read_res(sc, res, addr) 335 struct bge_softc *sc; 336 struct vpd_res *res; 337 int addr; 338 { 339 int i; 340 u_int8_t *ptr; 341 342 ptr = (u_int8_t *)res; 343 for (i = 0; i < sizeof(struct vpd_res); i++) 344 ptr[i] = bge_vpd_readbyte(sc, i + addr); 345 346 return; 347 } 348 349 static void 350 bge_vpd_read(sc) 351 struct bge_softc *sc; 352 { 353 int pos = 0, i; 354 struct vpd_res res; 355 356 if (sc->bge_vpd_prodname != NULL) 357 free(sc->bge_vpd_prodname, M_DEVBUF); 358 if (sc->bge_vpd_readonly != NULL) 359 free(sc->bge_vpd_readonly, M_DEVBUF); 360 sc->bge_vpd_prodname = NULL; 361 sc->bge_vpd_readonly = NULL; 362 363 bge_vpd_read_res(sc, &res, pos); 364 365 if (res.vr_id != VPD_RES_ID) { 366 printf("bge%d: bad VPD resource id: expected %x got %x\n", 367 sc->bge_unit, VPD_RES_ID, res.vr_id); 368 return; 369 } 370 371 pos += sizeof(res); 372 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 373 for (i = 0; i < res.vr_len; i++) 374 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 375 sc->bge_vpd_prodname[i] = '\0'; 376 pos += i; 377 378 bge_vpd_read_res(sc, &res, pos); 379 380 if (res.vr_id != VPD_RES_READ) { 381 printf("bge%d: bad VPD resource id: expected %x got %x\n", 382 sc->bge_unit, VPD_RES_READ, res.vr_id); 383 return; 384 } 385 386 pos += sizeof(res); 387 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 388 for (i = 0; i < res.vr_len + 1; i++) 389 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 390 391 return; 392 } 393 #endif 394 395 /* 396 * Read a byte of data stored in the EEPROM at address 'addr.' The 397 * BCM570x supports both the traditional bitbang interface and an 398 * auto access interface for reading the EEPROM. We use the auto 399 * access method. 400 */ 401 static u_int8_t 402 bge_eeprom_getbyte(sc, addr, dest) 403 struct bge_softc *sc; 404 int addr; 405 u_int8_t *dest; 406 { 407 int i; 408 u_int32_t byte = 0; 409 410 /* 411 * Enable use of auto EEPROM access so we can avoid 412 * having to use the bitbang method. 413 */ 414 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 415 416 /* Reset the EEPROM, load the clock period. */ 417 CSR_WRITE_4(sc, BGE_EE_ADDR, 418 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 419 DELAY(20); 420 421 /* Issue the read EEPROM command. */ 422 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 423 424 /* Wait for completion */ 425 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 426 DELAY(10); 427 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 428 break; 429 } 430 431 if (i == BGE_TIMEOUT) { 432 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 433 return(0); 434 } 435 436 /* Get result. */ 437 byte = CSR_READ_4(sc, BGE_EE_DATA); 438 439 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 440 441 return(0); 442 } 443 444 /* 445 * Read a sequence of bytes from the EEPROM. 446 */ 447 static int 448 bge_read_eeprom(sc, dest, off, cnt) 449 struct bge_softc *sc; 450 caddr_t dest; 451 int off; 452 int cnt; 453 { 454 int err = 0, i; 455 u_int8_t byte = 0; 456 457 for (i = 0; i < cnt; i++) { 458 err = bge_eeprom_getbyte(sc, off + i, &byte); 459 if (err) 460 break; 461 *(dest + i) = byte; 462 } 463 464 return(err ? 1 : 0); 465 } 466 467 static int 468 bge_miibus_readreg(dev, phy, reg) 469 device_t dev; 470 int phy, reg; 471 { 472 struct bge_softc *sc; 473 struct ifnet *ifp; 474 u_int32_t val; 475 int i; 476 477 sc = device_get_softc(dev); 478 ifp = &sc->arpcom.ac_if; 479 480 if (phy != 1) 481 switch(sc->bge_asicrev) { 482 case BGE_ASICREV_BCM5701_B5: 483 case BGE_ASICREV_BCM5703_A2: 484 return(0); 485 } 486 487 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 488 BGE_MIPHY(phy)|BGE_MIREG(reg)); 489 490 for (i = 0; i < BGE_TIMEOUT; i++) { 491 val = CSR_READ_4(sc, BGE_MI_COMM); 492 if (!(val & BGE_MICOMM_BUSY)) 493 break; 494 } 495 496 if (i == BGE_TIMEOUT) { 497 printf("bge%d: PHY read timed out\n", sc->bge_unit); 498 return(0); 499 } 500 501 val = CSR_READ_4(sc, BGE_MI_COMM); 502 503 if (val & BGE_MICOMM_READFAIL) 504 return(0); 505 506 return(val & 0xFFFF); 507 } 508 509 static int 510 bge_miibus_writereg(dev, phy, reg, val) 511 device_t dev; 512 int phy, reg, val; 513 { 514 struct bge_softc *sc; 515 int i; 516 517 sc = device_get_softc(dev); 518 519 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 520 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 521 522 for (i = 0; i < BGE_TIMEOUT; i++) { 523 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 524 break; 525 } 526 527 if (i == BGE_TIMEOUT) { 528 printf("bge%d: PHY read timed out\n", sc->bge_unit); 529 return(0); 530 } 531 532 return(0); 533 } 534 535 static void 536 bge_miibus_statchg(dev) 537 device_t dev; 538 { 539 struct bge_softc *sc; 540 struct mii_data *mii; 541 542 sc = device_get_softc(dev); 543 mii = device_get_softc(sc->bge_miibus); 544 545 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 546 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 547 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 548 } else { 549 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 550 } 551 552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 553 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 554 } else { 555 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 556 } 557 558 bge_phy_hack(sc); 559 560 return; 561 } 562 563 /* 564 * Handle events that have triggered interrupts. 565 */ 566 static void 567 bge_handle_events(sc) 568 struct bge_softc *sc; 569 { 570 571 return; 572 } 573 574 /* 575 * Memory management for jumbo frames. 576 */ 577 578 static int 579 bge_alloc_jumbo_mem(sc) 580 struct bge_softc *sc; 581 { 582 caddr_t ptr; 583 register int i; 584 struct bge_jpool_entry *entry; 585 586 /* Grab a big chunk o' storage. */ 587 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 589 590 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 591 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 592 return(ENOBUFS); 593 } 594 595 SLIST_INIT(&sc->bge_jfree_listhead); 596 SLIST_INIT(&sc->bge_jinuse_listhead); 597 598 /* 599 * Now divide it up into 9K pieces and save the addresses 600 * in an array. 601 */ 602 ptr = sc->bge_cdata.bge_jumbo_buf; 603 for (i = 0; i < BGE_JSLOTS; i++) { 604 sc->bge_cdata.bge_jslots[i] = ptr; 605 ptr += BGE_JLEN; 606 entry = malloc(sizeof(struct bge_jpool_entry), 607 M_DEVBUF, M_NOWAIT); 608 if (entry == NULL) { 609 contigfree(sc->bge_cdata.bge_jumbo_buf, 610 BGE_JMEM, M_DEVBUF); 611 sc->bge_cdata.bge_jumbo_buf = NULL; 612 printf("bge%d: no memory for jumbo " 613 "buffer queue!\n", sc->bge_unit); 614 return(ENOBUFS); 615 } 616 entry->slot = i; 617 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 618 entry, jpool_entries); 619 } 620 621 return(0); 622 } 623 624 static void 625 bge_free_jumbo_mem(sc) 626 struct bge_softc *sc; 627 { 628 int i; 629 struct bge_jpool_entry *entry; 630 631 for (i = 0; i < BGE_JSLOTS; i++) { 632 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 633 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 634 free(entry, M_DEVBUF); 635 } 636 637 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 638 639 return; 640 } 641 642 /* 643 * Allocate a jumbo buffer. 644 */ 645 static void * 646 bge_jalloc(sc) 647 struct bge_softc *sc; 648 { 649 struct bge_jpool_entry *entry; 650 651 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 652 653 if (entry == NULL) { 654 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 655 return(NULL); 656 } 657 658 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 659 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 660 return(sc->bge_cdata.bge_jslots[entry->slot]); 661 } 662 663 /* 664 * Release a jumbo buffer. 665 */ 666 static void 667 bge_jfree(buf, args) 668 void *buf; 669 void *args; 670 { 671 struct bge_jpool_entry *entry; 672 struct bge_softc *sc; 673 int i; 674 675 /* Extract the softc struct pointer. */ 676 sc = (struct bge_softc *)args; 677 678 if (sc == NULL) 679 panic("bge_jfree: can't find softc pointer!"); 680 681 /* calculate the slot this buffer belongs to */ 682 683 i = ((vm_offset_t)buf 684 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 685 686 if ((i < 0) || (i >= BGE_JSLOTS)) 687 panic("bge_jfree: asked to free buffer that we don't manage!"); 688 689 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 690 if (entry == NULL) 691 panic("bge_jfree: buffer not in use!"); 692 entry->slot = i; 693 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 694 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 695 696 return; 697 } 698 699 700 /* 701 * Intialize a standard receive ring descriptor. 702 */ 703 static int 704 bge_newbuf_std(sc, i, m) 705 struct bge_softc *sc; 706 int i; 707 struct mbuf *m; 708 { 709 struct mbuf *m_new = NULL; 710 struct bge_rx_bd *r; 711 712 if (m == NULL) { 713 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 714 if (m_new == NULL) { 715 return(ENOBUFS); 716 } 717 718 MCLGET(m_new, M_DONTWAIT); 719 if (!(m_new->m_flags & M_EXT)) { 720 m_freem(m_new); 721 return(ENOBUFS); 722 } 723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 724 } else { 725 m_new = m; 726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 727 m_new->m_data = m_new->m_ext.ext_buf; 728 } 729 730 if (!sc->bge_rx_alignment_bug) 731 m_adj(m_new, ETHER_ALIGN); 732 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 733 r = &sc->bge_rdata->bge_rx_std_ring[i]; 734 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 735 r->bge_flags = BGE_RXBDFLAG_END; 736 r->bge_len = m_new->m_len; 737 r->bge_idx = i; 738 739 return(0); 740 } 741 742 /* 743 * Initialize a jumbo receive ring descriptor. This allocates 744 * a jumbo buffer from the pool managed internally by the driver. 745 */ 746 static int 747 bge_newbuf_jumbo(sc, i, m) 748 struct bge_softc *sc; 749 int i; 750 struct mbuf *m; 751 { 752 struct mbuf *m_new = NULL; 753 struct bge_rx_bd *r; 754 755 if (m == NULL) { 756 caddr_t *buf = NULL; 757 758 /* Allocate the mbuf. */ 759 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 760 if (m_new == NULL) { 761 return(ENOBUFS); 762 } 763 764 /* Allocate the jumbo buffer */ 765 buf = bge_jalloc(sc); 766 if (buf == NULL) { 767 m_freem(m_new); 768 printf("bge%d: jumbo allocation failed " 769 "-- packet dropped!\n", sc->bge_unit); 770 return(ENOBUFS); 771 } 772 773 /* Attach the buffer to the mbuf. */ 774 m_new->m_data = (void *) buf; 775 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 776 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 777 (struct bge_softc *)sc, 0, EXT_NET_DRV); 778 } else { 779 m_new = m; 780 m_new->m_data = m_new->m_ext.ext_buf; 781 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 782 } 783 784 if (!sc->bge_rx_alignment_bug) 785 m_adj(m_new, ETHER_ALIGN); 786 /* Set up the descriptor. */ 787 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 788 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 789 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 790 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 791 r->bge_len = m_new->m_len; 792 r->bge_idx = i; 793 794 return(0); 795 } 796 797 /* 798 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 799 * that's 1MB or memory, which is a lot. For now, we fill only the first 800 * 256 ring entries and hope that our CPU is fast enough to keep up with 801 * the NIC. 802 */ 803 static int 804 bge_init_rx_ring_std(sc) 805 struct bge_softc *sc; 806 { 807 int i; 808 809 for (i = 0; i < BGE_SSLOTS; i++) { 810 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 811 return(ENOBUFS); 812 }; 813 814 sc->bge_std = i - 1; 815 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 816 817 return(0); 818 } 819 820 static void 821 bge_free_rx_ring_std(sc) 822 struct bge_softc *sc; 823 { 824 int i; 825 826 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 827 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 828 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 829 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 830 } 831 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 832 sizeof(struct bge_rx_bd)); 833 } 834 835 return; 836 } 837 838 static int 839 bge_init_rx_ring_jumbo(sc) 840 struct bge_softc *sc; 841 { 842 int i; 843 struct bge_rcb *rcb; 844 845 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 846 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 847 return(ENOBUFS); 848 }; 849 850 sc->bge_jumbo = i - 1; 851 852 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 853 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 854 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 855 856 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 857 858 return(0); 859 } 860 861 static void 862 bge_free_rx_ring_jumbo(sc) 863 struct bge_softc *sc; 864 { 865 int i; 866 867 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 868 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 869 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 870 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 871 } 872 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 873 sizeof(struct bge_rx_bd)); 874 } 875 876 return; 877 } 878 879 static void 880 bge_free_tx_ring(sc) 881 struct bge_softc *sc; 882 { 883 int i; 884 885 if (sc->bge_rdata->bge_tx_ring == NULL) 886 return; 887 888 for (i = 0; i < BGE_TX_RING_CNT; i++) { 889 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 890 m_freem(sc->bge_cdata.bge_tx_chain[i]); 891 sc->bge_cdata.bge_tx_chain[i] = NULL; 892 } 893 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 894 sizeof(struct bge_tx_bd)); 895 } 896 897 return; 898 } 899 900 static int 901 bge_init_tx_ring(sc) 902 struct bge_softc *sc; 903 { 904 sc->bge_txcnt = 0; 905 sc->bge_tx_saved_considx = 0; 906 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 907 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 908 909 return(0); 910 } 911 912 #define BGE_POLY 0xEDB88320 913 914 static u_int32_t 915 bge_crc(addr) 916 caddr_t addr; 917 { 918 u_int32_t idx, bit, data, crc; 919 920 /* Compute CRC for the address value. */ 921 crc = 0xFFFFFFFF; /* initial value */ 922 923 for (idx = 0; idx < 6; idx++) { 924 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 925 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 926 } 927 928 return(crc & 0x7F); 929 } 930 931 static void 932 bge_setmulti(sc) 933 struct bge_softc *sc; 934 { 935 struct ifnet *ifp; 936 struct ifmultiaddr *ifma; 937 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 938 int h, i; 939 940 ifp = &sc->arpcom.ac_if; 941 942 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 943 for (i = 0; i < 4; i++) 944 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 945 return; 946 } 947 948 /* First, zot all the existing filters. */ 949 for (i = 0; i < 4; i++) 950 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 951 952 /* Now program new ones. */ 953 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 954 if (ifma->ifma_addr->sa_family != AF_LINK) 955 continue; 956 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 957 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 958 } 959 960 for (i = 0; i < 4; i++) 961 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 962 963 return; 964 } 965 966 /* 967 * Do endian, PCI and DMA initialization. Also check the on-board ROM 968 * self-test results. 969 */ 970 static int 971 bge_chipinit(sc) 972 struct bge_softc *sc; 973 { 974 int i; 975 976 /* Set endianness before we access any non-PCI registers. */ 977 #if BYTE_ORDER == BIG_ENDIAN 978 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 979 BGE_BIGENDIAN_INIT, 4); 980 #else 981 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 982 BGE_LITTLEENDIAN_INIT, 4); 983 #endif 984 985 /* 986 * Check the 'ROM failed' bit on the RX CPU to see if 987 * self-tests passed. 988 */ 989 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 990 printf("bge%d: RX CPU self-diagnostics failed!\n", 991 sc->bge_unit); 992 return(ENODEV); 993 } 994 995 /* Clear the MAC control register */ 996 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 997 998 /* 999 * Clear the MAC statistics block in the NIC's 1000 * internal memory. 1001 */ 1002 for (i = BGE_STATS_BLOCK; 1003 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1004 BGE_MEMWIN_WRITE(sc, i, 0); 1005 1006 for (i = BGE_STATUS_BLOCK; 1007 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1008 BGE_MEMWIN_WRITE(sc, i, 0); 1009 1010 /* Set up the PCI DMA control register. */ 1011 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1012 BGE_PCISTATE_PCI_BUSMODE) { 1013 /* Conventional PCI bus */ 1014 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1015 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4); 1016 } else { 1017 /* PCI-X bus */ 1018 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1019 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4); 1020 } 1021 1022 /* 1023 * Set up general mode register. 1024 */ 1025 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1026 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1027 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1028 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1029 BGE_MODECTL_RX_NO_PHDR_CSUM); 1030 1031 /* 1032 * Disable memory write invalidate. Apparently it is not supported 1033 * properly by these devices. 1034 */ 1035 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1036 1037 #ifdef __brokenalpha__ 1038 /* 1039 * Must insure that we do not cross an 8K (bytes) boundary 1040 * for DMA reads. Our highest limit is 1K bytes. This is a 1041 * restriction on some ALPHA platforms with early revision 1042 * 21174 PCI chipsets, such as the AlphaPC 164lx 1043 */ 1044 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1045 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1046 #endif 1047 1048 /* Set the timer prescaler (always 66Mhz) */ 1049 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1050 1051 return(0); 1052 } 1053 1054 static int 1055 bge_blockinit(sc) 1056 struct bge_softc *sc; 1057 { 1058 struct bge_rcb *rcb; 1059 volatile struct bge_rcb *vrcb; 1060 int i; 1061 1062 /* 1063 * Initialize the memory window pointer register so that 1064 * we can access the first 32K of internal NIC RAM. This will 1065 * allow us to set up the TX send ring RCBs and the RX return 1066 * ring RCBs, plus other things which live in NIC memory. 1067 */ 1068 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1069 1070 /* Configure mbuf memory pool */ 1071 if (sc->bge_extram) { 1072 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1073 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1074 } else { 1075 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1076 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1077 } 1078 1079 /* Configure DMA resource pool */ 1080 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1081 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1082 1083 /* Configure mbuf pool watermarks */ 1084 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1086 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1087 1088 /* Configure DMA resource watermarks */ 1089 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1090 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1091 1092 /* Enable buffer manager */ 1093 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1094 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1095 1096 /* Poll for buffer manager start indication */ 1097 for (i = 0; i < BGE_TIMEOUT; i++) { 1098 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1099 break; 1100 DELAY(10); 1101 } 1102 1103 if (i == BGE_TIMEOUT) { 1104 printf("bge%d: buffer manager failed to start\n", 1105 sc->bge_unit); 1106 return(ENXIO); 1107 } 1108 1109 /* Enable flow-through queues */ 1110 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1111 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1112 1113 /* Wait until queue initialization is complete */ 1114 for (i = 0; i < BGE_TIMEOUT; i++) { 1115 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1116 break; 1117 DELAY(10); 1118 } 1119 1120 if (i == BGE_TIMEOUT) { 1121 printf("bge%d: flow-through queue init failed\n", 1122 sc->bge_unit); 1123 return(ENXIO); 1124 } 1125 1126 /* Initialize the standard RX ring control block */ 1127 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1128 BGE_HOSTADDR(rcb->bge_hostaddr) = 1129 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1130 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1131 if (sc->bge_extram) 1132 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1133 else 1134 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1135 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1136 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1137 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1139 1140 /* 1141 * Initialize the jumbo RX ring control block 1142 * We set the 'ring disabled' bit in the flags 1143 * field until we're actually ready to start 1144 * using this ring (i.e. once we set the MTU 1145 * high enough to require it). 1146 */ 1147 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1148 BGE_HOSTADDR(rcb->bge_hostaddr) = 1149 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1150 rcb->bge_maxlen_flags = 1151 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1152 if (sc->bge_extram) 1153 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1154 else 1155 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1156 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1157 rcb->bge_hostaddr.bge_addr_hi); 1158 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1159 rcb->bge_hostaddr.bge_addr_lo); 1160 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1161 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1162 1163 /* Set up dummy disabled mini ring RCB */ 1164 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1165 rcb->bge_maxlen_flags = 1166 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1167 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1168 1169 /* 1170 * Set the BD ring replentish thresholds. The recommended 1171 * values are 1/8th the number of descriptors allocated to 1172 * each ring. 1173 */ 1174 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1175 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1176 1177 /* 1178 * Disable all unused send rings by setting the 'ring disabled' 1179 * bit in the flags field of all the TX send ring control blocks. 1180 * These are located in NIC memory. 1181 */ 1182 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1183 BGE_SEND_RING_RCB); 1184 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1185 vrcb->bge_maxlen_flags = 1186 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1187 vrcb->bge_nicaddr = 0; 1188 vrcb++; 1189 } 1190 1191 /* Configure TX RCB 0 (we use only the first ring) */ 1192 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1193 BGE_SEND_RING_RCB); 1194 vrcb->bge_hostaddr.bge_addr_hi = 0; 1195 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1196 vtophys(&sc->bge_rdata->bge_tx_ring); 1197 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1198 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1199 1200 /* Disable all unused RX return rings */ 1201 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1202 BGE_RX_RETURN_RING_RCB); 1203 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1204 vrcb->bge_hostaddr.bge_addr_hi = 0; 1205 vrcb->bge_hostaddr.bge_addr_lo = 0; 1206 vrcb->bge_maxlen_flags = 1207 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1208 BGE_RCB_FLAG_RING_DISABLED); 1209 vrcb->bge_nicaddr = 0; 1210 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1211 (i * (sizeof(u_int64_t))), 0); 1212 vrcb++; 1213 } 1214 1215 /* Initialize RX ring indexes */ 1216 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1217 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1218 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1219 1220 /* 1221 * Set up RX return ring 0 1222 * Note that the NIC address for RX return rings is 0x00000000. 1223 * The return rings live entirely within the host, so the 1224 * nicaddr field in the RCB isn't used. 1225 */ 1226 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1227 BGE_RX_RETURN_RING_RCB); 1228 vrcb->bge_hostaddr.bge_addr_hi = 0; 1229 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1230 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1231 vrcb->bge_nicaddr = 0x00000000; 1232 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1233 1234 /* Set random backoff seed for TX */ 1235 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1236 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1237 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1238 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1239 BGE_TX_BACKOFF_SEED_MASK); 1240 1241 /* Set inter-packet gap */ 1242 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1243 1244 /* 1245 * Specify which ring to use for packets that don't match 1246 * any RX rules. 1247 */ 1248 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1249 1250 /* 1251 * Configure number of RX lists. One interrupt distribution 1252 * list, sixteen active lists, one bad frames class. 1253 */ 1254 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1255 1256 /* Inialize RX list placement stats mask. */ 1257 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1258 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1259 1260 /* Disable host coalescing until we get it set up */ 1261 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1262 1263 /* Poll to make sure it's shut down. */ 1264 for (i = 0; i < BGE_TIMEOUT; i++) { 1265 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1266 break; 1267 DELAY(10); 1268 } 1269 1270 if (i == BGE_TIMEOUT) { 1271 printf("bge%d: host coalescing engine failed to idle\n", 1272 sc->bge_unit); 1273 return(ENXIO); 1274 } 1275 1276 /* Set up host coalescing defaults */ 1277 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1278 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1279 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1280 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1281 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1282 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1283 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1284 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1285 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1286 1287 /* Set up address of statistics block */ 1288 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1289 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1290 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1291 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1292 1293 /* Set up address of status block */ 1294 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1295 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1296 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1297 vtophys(&sc->bge_rdata->bge_status_block)); 1298 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1299 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1300 1301 /* Turn on host coalescing state machine */ 1302 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1303 1304 /* Turn on RX BD completion state machine and enable attentions */ 1305 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1306 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1307 1308 /* Turn on RX list placement state machine */ 1309 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1310 1311 /* Turn on RX list selector state machine. */ 1312 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1313 1314 /* Turn on DMA, clear stats */ 1315 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1316 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1317 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1318 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1319 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1320 1321 /* Set misc. local control, enable interrupts on attentions */ 1322 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1323 1324 #ifdef notdef 1325 /* Assert GPIO pins for PHY reset */ 1326 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1327 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1328 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1329 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1330 #endif 1331 1332 /* Turn on DMA completion state machine */ 1333 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1334 1335 /* Turn on write DMA state machine */ 1336 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1337 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1338 1339 /* Turn on read DMA state machine */ 1340 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1341 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1342 1343 /* Turn on RX data completion state machine */ 1344 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1345 1346 /* Turn on RX BD initiator state machine */ 1347 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1348 1349 /* Turn on RX data and RX BD initiator state machine */ 1350 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1351 1352 /* Turn on Mbuf cluster free state machine */ 1353 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1354 1355 /* Turn on send BD completion state machine */ 1356 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1357 1358 /* Turn on send data completion state machine */ 1359 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1360 1361 /* Turn on send data initiator state machine */ 1362 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1363 1364 /* Turn on send BD initiator state machine */ 1365 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1366 1367 /* Turn on send BD selector state machine */ 1368 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1369 1370 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1371 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1372 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1373 1374 /* init LED register */ 1375 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1376 1377 /* ack/clear link change events */ 1378 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1379 BGE_MACSTAT_CFG_CHANGED); 1380 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1381 1382 /* Enable PHY auto polling (for MII/GMII only) */ 1383 if (sc->bge_tbi) { 1384 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1385 } else { 1386 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1387 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1388 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1389 BGE_EVTENB_MI_INTERRUPT); 1390 } 1391 1392 /* Enable link state change attentions. */ 1393 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1394 1395 return(0); 1396 } 1397 1398 /* 1399 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1400 * against our list and return its name if we find a match. Note 1401 * that since the Broadcom controller contains VPD support, we 1402 * can get the device name string from the controller itself instead 1403 * of the compiled-in string. This is a little slow, but it guarantees 1404 * we'll always announce the right product name. 1405 */ 1406 static int 1407 bge_probe(dev) 1408 device_t dev; 1409 { 1410 struct bge_type *t; 1411 struct bge_softc *sc; 1412 char *descbuf; 1413 1414 t = bge_devs; 1415 1416 sc = device_get_softc(dev); 1417 bzero(sc, sizeof(struct bge_softc)); 1418 sc->bge_unit = device_get_unit(dev); 1419 sc->bge_dev = dev; 1420 1421 while(t->bge_name != NULL) { 1422 if ((pci_get_vendor(dev) == t->bge_vid) && 1423 (pci_get_device(dev) == t->bge_did)) { 1424 #ifdef notdef 1425 bge_vpd_read(sc); 1426 device_set_desc(dev, sc->bge_vpd_prodname); 1427 #endif 1428 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1429 if (descbuf == NULL) 1430 return(ENOMEM); 1431 snprintf(descbuf, BGE_DEVDESC_MAX, 1432 "%s, ASIC rev. %#04x", t->bge_name, 1433 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1434 device_set_desc_copy(dev, descbuf); 1435 free(descbuf, M_TEMP); 1436 return(0); 1437 } 1438 t++; 1439 } 1440 1441 return(ENXIO); 1442 } 1443 1444 static int 1445 bge_attach(dev) 1446 device_t dev; 1447 { 1448 int s; 1449 u_int32_t command; 1450 struct ifnet *ifp; 1451 struct bge_softc *sc; 1452 u_int32_t hwcfg = 0; 1453 u_int32_t mac_addr = 0; 1454 int unit, error = 0, rid; 1455 1456 s = splimp(); 1457 1458 sc = device_get_softc(dev); 1459 unit = device_get_unit(dev); 1460 sc->bge_dev = dev; 1461 sc->bge_unit = unit; 1462 1463 /* 1464 * Map control/status registers. 1465 */ 1466 pci_enable_busmaster(dev); 1467 pci_enable_io(dev, SYS_RES_MEMORY); 1468 command = pci_read_config(dev, PCIR_COMMAND, 4); 1469 1470 if (!(command & PCIM_CMD_MEMEN)) { 1471 printf("bge%d: failed to enable memory mapping!\n", unit); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 1476 rid = BGE_PCI_BAR0; 1477 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1478 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1479 1480 if (sc->bge_res == NULL) { 1481 printf ("bge%d: couldn't map memory\n", unit); 1482 error = ENXIO; 1483 goto fail; 1484 } 1485 1486 sc->bge_btag = rman_get_bustag(sc->bge_res); 1487 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1488 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1489 1490 /* Allocate interrupt */ 1491 rid = 0; 1492 1493 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1494 RF_SHAREABLE | RF_ACTIVE); 1495 1496 if (sc->bge_irq == NULL) { 1497 printf("bge%d: couldn't map interrupt\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1503 bge_intr, sc, &sc->bge_intrhand); 1504 1505 if (error) { 1506 bge_release_resources(sc); 1507 printf("bge%d: couldn't set up irq\n", unit); 1508 goto fail; 1509 } 1510 1511 sc->bge_unit = unit; 1512 1513 /* Try to reset the chip. */ 1514 bge_reset(sc); 1515 1516 if (bge_chipinit(sc)) { 1517 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1518 bge_release_resources(sc); 1519 error = ENXIO; 1520 goto fail; 1521 } 1522 1523 /* 1524 * Get station address from the EEPROM. 1525 */ 1526 mac_addr = bge_readmem_ind(sc, 0x0c14); 1527 if ((mac_addr >> 16) == 0x484b) { 1528 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1529 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1530 mac_addr = bge_readmem_ind(sc, 0x0c18); 1531 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1532 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1533 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1534 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1535 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1536 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1537 printf("bge%d: failed to read station address\n", unit); 1538 bge_release_resources(sc); 1539 error = ENXIO; 1540 goto fail; 1541 } 1542 1543 /* 1544 * A Broadcom chip was detected. Inform the world. 1545 */ 1546 printf("bge%d: Ethernet address: %6D\n", unit, 1547 sc->arpcom.ac_enaddr, ":"); 1548 1549 /* Allocate the general information block and ring buffers. */ 1550 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1551 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1552 1553 if (sc->bge_rdata == NULL) { 1554 bge_release_resources(sc); 1555 error = ENXIO; 1556 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1557 goto fail; 1558 } 1559 1560 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1561 1562 /* Try to allocate memory for jumbo buffers. */ 1563 if (bge_alloc_jumbo_mem(sc)) { 1564 printf("bge%d: jumbo buffer allocation " 1565 "failed\n", sc->bge_unit); 1566 bge_release_resources(sc); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 /* Set default tuneable values. */ 1572 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1573 sc->bge_rx_coal_ticks = 150; 1574 sc->bge_tx_coal_ticks = 150; 1575 sc->bge_rx_max_coal_bds = 64; 1576 sc->bge_tx_max_coal_bds = 128; 1577 1578 /* Set up ifnet structure */ 1579 ifp = &sc->arpcom.ac_if; 1580 ifp->if_softc = sc; 1581 ifp->if_unit = sc->bge_unit; 1582 ifp->if_name = "bge"; 1583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1584 ifp->if_ioctl = bge_ioctl; 1585 ifp->if_output = ether_output; 1586 ifp->if_start = bge_start; 1587 ifp->if_watchdog = bge_watchdog; 1588 ifp->if_init = bge_init; 1589 ifp->if_mtu = ETHERMTU; 1590 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1591 ifp->if_hwassist = BGE_CSUM_FEATURES; 1592 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1593 ifp->if_capenable = ifp->if_capabilities; 1594 1595 /* Save ASIC rev. */ 1596 1597 sc->bge_asicrev = 1598 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1599 BGE_PCIMISCCTL_ASICREV; 1600 1601 /* Pretend all 5700s are the same */ 1602 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1603 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1604 1605 /* 1606 * Figure out what sort of media we have by checking the 1607 * hardware config word in the first 32k of NIC internal memory, 1608 * or fall back to examining the EEPROM if necessary. 1609 * Note: on some BCM5700 cards, this value appears to be unset. 1610 * If that's the case, we have to rely on identifying the NIC 1611 * by its PCI subsystem ID, as we do below for the SysKonnect 1612 * SK-9D41. 1613 */ 1614 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1615 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1616 else { 1617 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1618 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1619 hwcfg = ntohl(hwcfg); 1620 } 1621 1622 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1623 sc->bge_tbi = 1; 1624 1625 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1626 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1627 sc->bge_tbi = 1; 1628 1629 if (sc->bge_tbi) { 1630 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1631 bge_ifmedia_upd, bge_ifmedia_sts); 1632 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1633 ifmedia_add(&sc->bge_ifmedia, 1634 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1635 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1636 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1637 } else { 1638 /* 1639 * Do transceiver setup. 1640 */ 1641 if (mii_phy_probe(dev, &sc->bge_miibus, 1642 bge_ifmedia_upd, bge_ifmedia_sts)) { 1643 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1644 bge_release_resources(sc); 1645 bge_free_jumbo_mem(sc); 1646 error = ENXIO; 1647 goto fail; 1648 } 1649 } 1650 1651 /* 1652 * When using the BCM5701 in PCI-X mode, data corruption has 1653 * been observed in the first few bytes of some received packets. 1654 * Aligning the packet buffer in memory eliminates the corruption. 1655 * Unfortunately, this misaligns the packet payloads. On platforms 1656 * which do not support unaligned accesses, we will realign the 1657 * payloads by copying the received packets. 1658 */ 1659 switch (sc->bge_asicrev) { 1660 case BGE_ASICREV_BCM5701_A0: 1661 case BGE_ASICREV_BCM5701_B0: 1662 case BGE_ASICREV_BCM5701_B2: 1663 case BGE_ASICREV_BCM5701_B5: 1664 /* If in PCI-X mode, work around the alignment bug. */ 1665 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1666 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1667 BGE_PCISTATE_PCI_BUSSPEED) 1668 sc->bge_rx_alignment_bug = 1; 1669 break; 1670 } 1671 1672 /* 1673 * Call MI attach routine. 1674 */ 1675 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1676 callout_handle_init(&sc->bge_stat_ch); 1677 1678 fail: 1679 splx(s); 1680 1681 return(error); 1682 } 1683 1684 static int 1685 bge_detach(dev) 1686 device_t dev; 1687 { 1688 struct bge_softc *sc; 1689 struct ifnet *ifp; 1690 int s; 1691 1692 s = splimp(); 1693 1694 sc = device_get_softc(dev); 1695 ifp = &sc->arpcom.ac_if; 1696 1697 ether_ifdetach(ifp); 1698 bge_stop(sc); 1699 bge_reset(sc); 1700 1701 if (sc->bge_tbi) { 1702 ifmedia_removeall(&sc->bge_ifmedia); 1703 } else { 1704 bus_generic_detach(dev); 1705 device_delete_child(dev, sc->bge_miibus); 1706 } 1707 1708 bge_release_resources(sc); 1709 bge_free_jumbo_mem(sc); 1710 1711 splx(s); 1712 1713 return(0); 1714 } 1715 1716 static void 1717 bge_release_resources(sc) 1718 struct bge_softc *sc; 1719 { 1720 device_t dev; 1721 1722 dev = sc->bge_dev; 1723 1724 if (sc->bge_vpd_prodname != NULL) 1725 free(sc->bge_vpd_prodname, M_DEVBUF); 1726 1727 if (sc->bge_vpd_readonly != NULL) 1728 free(sc->bge_vpd_readonly, M_DEVBUF); 1729 1730 if (sc->bge_intrhand != NULL) 1731 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1732 1733 if (sc->bge_irq != NULL) 1734 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1735 1736 if (sc->bge_res != NULL) 1737 bus_release_resource(dev, SYS_RES_MEMORY, 1738 BGE_PCI_BAR0, sc->bge_res); 1739 1740 if (sc->bge_rdata != NULL) 1741 contigfree(sc->bge_rdata, 1742 sizeof(struct bge_ring_data), M_DEVBUF); 1743 1744 return; 1745 } 1746 1747 static void 1748 bge_reset(sc) 1749 struct bge_softc *sc; 1750 { 1751 device_t dev; 1752 u_int32_t cachesize, command, pcistate; 1753 int i, val = 0; 1754 1755 dev = sc->bge_dev; 1756 1757 /* Save some important PCI state. */ 1758 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1759 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1760 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1761 1762 pci_write_config(dev, BGE_PCI_MISC_CTL, 1763 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1764 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1765 1766 /* Issue global reset */ 1767 bge_writereg_ind(sc, BGE_MISC_CFG, 1768 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1769 1770 DELAY(1000); 1771 1772 /* Reset some of the PCI state that got zapped by reset */ 1773 pci_write_config(dev, BGE_PCI_MISC_CTL, 1774 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1775 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1776 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1777 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1778 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1779 1780 /* 1781 * Prevent PXE restart: write a magic number to the 1782 * general communications memory at 0xB50. 1783 */ 1784 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1785 /* 1786 * Poll the value location we just wrote until 1787 * we see the 1's complement of the magic number. 1788 * This indicates that the firmware initialization 1789 * is complete. 1790 */ 1791 for (i = 0; i < BGE_TIMEOUT; i++) { 1792 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1793 if (val == ~BGE_MAGIC_NUMBER) 1794 break; 1795 DELAY(10); 1796 } 1797 1798 if (i == BGE_TIMEOUT) { 1799 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1800 return; 1801 } 1802 1803 /* 1804 * XXX Wait for the value of the PCISTATE register to 1805 * return to its original pre-reset state. This is a 1806 * fairly good indicator of reset completion. If we don't 1807 * wait for the reset to fully complete, trying to read 1808 * from the device's non-PCI registers may yield garbage 1809 * results. 1810 */ 1811 for (i = 0; i < BGE_TIMEOUT; i++) { 1812 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1813 break; 1814 DELAY(10); 1815 } 1816 1817 /* Enable memory arbiter. */ 1818 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1819 1820 /* Fix up byte swapping */ 1821 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1822 BGE_MODECTL_BYTESWAP_DATA); 1823 1824 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1825 1826 DELAY(10000); 1827 1828 return; 1829 } 1830 1831 /* 1832 * Frame reception handling. This is called if there's a frame 1833 * on the receive return list. 1834 * 1835 * Note: we have to be able to handle two possibilities here: 1836 * 1) the frame is from the jumbo recieve ring 1837 * 2) the frame is from the standard receive ring 1838 */ 1839 1840 static void 1841 bge_rxeof(sc) 1842 struct bge_softc *sc; 1843 { 1844 struct ifnet *ifp; 1845 int stdcnt = 0, jumbocnt = 0; 1846 1847 ifp = &sc->arpcom.ac_if; 1848 1849 while(sc->bge_rx_saved_considx != 1850 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1851 struct bge_rx_bd *cur_rx; 1852 u_int32_t rxidx; 1853 struct ether_header *eh; 1854 struct mbuf *m = NULL; 1855 u_int16_t vlan_tag = 0; 1856 int have_tag = 0; 1857 1858 cur_rx = 1859 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1860 1861 rxidx = cur_rx->bge_idx; 1862 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1863 1864 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1865 have_tag = 1; 1866 vlan_tag = cur_rx->bge_vlan_tag; 1867 } 1868 1869 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1870 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1871 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1872 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1873 jumbocnt++; 1874 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1875 ifp->if_ierrors++; 1876 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1877 continue; 1878 } 1879 if (bge_newbuf_jumbo(sc, 1880 sc->bge_jumbo, NULL) == ENOBUFS) { 1881 ifp->if_ierrors++; 1882 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1883 continue; 1884 } 1885 } else { 1886 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1887 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1888 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1889 stdcnt++; 1890 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1891 ifp->if_ierrors++; 1892 bge_newbuf_std(sc, sc->bge_std, m); 1893 continue; 1894 } 1895 if (bge_newbuf_std(sc, sc->bge_std, 1896 NULL) == ENOBUFS) { 1897 ifp->if_ierrors++; 1898 bge_newbuf_std(sc, sc->bge_std, m); 1899 continue; 1900 } 1901 } 1902 1903 ifp->if_ipackets++; 1904 #ifndef __i386__ 1905 /* 1906 * The i386 allows unaligned accesses, but for other 1907 * platforms we must make sure the payload is aligned. 1908 */ 1909 if (sc->bge_rx_alignment_bug) { 1910 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1911 cur_rx->bge_len); 1912 m->m_data += ETHER_ALIGN; 1913 } 1914 #endif 1915 eh = mtod(m, struct ether_header *); 1916 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1917 m->m_pkthdr.rcvif = ifp; 1918 1919 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1920 if (ifp->if_hwassist) { 1921 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1922 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1923 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1924 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1925 m->m_pkthdr.csum_data = 1926 cur_rx->bge_tcp_udp_csum; 1927 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1928 } 1929 } 1930 #endif 1931 1932 /* 1933 * If we received a packet with a vlan tag, 1934 * attach that information to the packet. 1935 */ 1936 if (have_tag) 1937 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1938 1939 (*ifp->if_input)(ifp, m); 1940 } 1941 1942 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1943 if (stdcnt) 1944 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1945 if (jumbocnt) 1946 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1947 1948 return; 1949 } 1950 1951 static void 1952 bge_txeof(sc) 1953 struct bge_softc *sc; 1954 { 1955 struct bge_tx_bd *cur_tx = NULL; 1956 struct ifnet *ifp; 1957 1958 ifp = &sc->arpcom.ac_if; 1959 1960 /* 1961 * Go through our tx ring and free mbufs for those 1962 * frames that have been sent. 1963 */ 1964 while (sc->bge_tx_saved_considx != 1965 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1966 u_int32_t idx = 0; 1967 1968 idx = sc->bge_tx_saved_considx; 1969 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1970 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1971 ifp->if_opackets++; 1972 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1973 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1974 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1975 } 1976 sc->bge_txcnt--; 1977 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1978 ifp->if_timer = 0; 1979 } 1980 1981 if (cur_tx != NULL) 1982 ifp->if_flags &= ~IFF_OACTIVE; 1983 1984 return; 1985 } 1986 1987 static void 1988 bge_intr(xsc) 1989 void *xsc; 1990 { 1991 struct bge_softc *sc; 1992 struct ifnet *ifp; 1993 1994 sc = xsc; 1995 ifp = &sc->arpcom.ac_if; 1996 1997 #ifdef notdef 1998 /* Avoid this for now -- checking this register is expensive. */ 1999 /* Make sure this is really our interrupt. */ 2000 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2001 return; 2002 #endif 2003 /* Ack interrupt and stop others from occuring. */ 2004 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2005 2006 /* 2007 * Process link state changes. 2008 * Grrr. The link status word in the status block does 2009 * not work correctly on the BCM5700 rev AX and BX chips, 2010 * according to all avaibable information. Hence, we have 2011 * to enable MII interrupts in order to properly obtain 2012 * async link changes. Unfortunately, this also means that 2013 * we have to read the MAC status register to detect link 2014 * changes, thereby adding an additional register access to 2015 * the interrupt handler. 2016 */ 2017 2018 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2019 u_int32_t status; 2020 2021 status = CSR_READ_4(sc, BGE_MAC_STS); 2022 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2023 sc->bge_link = 0; 2024 untimeout(bge_tick, sc, sc->bge_stat_ch); 2025 bge_tick(sc); 2026 /* Clear the interrupt */ 2027 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2028 BGE_EVTENB_MI_INTERRUPT); 2029 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2030 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2031 BRGPHY_INTRS); 2032 } 2033 } else { 2034 if (sc->bge_rdata->bge_status_block.bge_status & 2035 BGE_STATFLAG_LINKSTATE_CHANGED) { 2036 sc->bge_link = 0; 2037 untimeout(bge_tick, sc, sc->bge_stat_ch); 2038 bge_tick(sc); 2039 /* Clear the interrupt */ 2040 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2041 BGE_MACSTAT_CFG_CHANGED); 2042 } 2043 } 2044 2045 if (ifp->if_flags & IFF_RUNNING) { 2046 /* Check RX return ring producer/consumer */ 2047 bge_rxeof(sc); 2048 2049 /* Check TX ring producer/consumer */ 2050 bge_txeof(sc); 2051 } 2052 2053 bge_handle_events(sc); 2054 2055 /* Re-enable interrupts. */ 2056 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2057 2058 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2059 bge_start(ifp); 2060 2061 return; 2062 } 2063 2064 static void 2065 bge_tick(xsc) 2066 void *xsc; 2067 { 2068 struct bge_softc *sc; 2069 struct mii_data *mii = NULL; 2070 struct ifmedia *ifm = NULL; 2071 struct ifnet *ifp; 2072 int s; 2073 2074 sc = xsc; 2075 ifp = &sc->arpcom.ac_if; 2076 2077 s = splimp(); 2078 2079 bge_stats_update(sc); 2080 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2081 if (sc->bge_link) { 2082 splx(s); 2083 return; 2084 } 2085 2086 if (sc->bge_tbi) { 2087 ifm = &sc->bge_ifmedia; 2088 if (CSR_READ_4(sc, BGE_MAC_STS) & 2089 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2090 sc->bge_link++; 2091 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2092 printf("bge%d: gigabit link up\n", sc->bge_unit); 2093 if (ifp->if_snd.ifq_head != NULL) 2094 bge_start(ifp); 2095 } 2096 splx(s); 2097 return; 2098 } 2099 2100 mii = device_get_softc(sc->bge_miibus); 2101 mii_tick(mii); 2102 2103 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2104 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2105 sc->bge_link++; 2106 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2107 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2108 printf("bge%d: gigabit link up\n", 2109 sc->bge_unit); 2110 if (ifp->if_snd.ifq_head != NULL) 2111 bge_start(ifp); 2112 } 2113 2114 splx(s); 2115 2116 return; 2117 } 2118 2119 static void 2120 bge_stats_update(sc) 2121 struct bge_softc *sc; 2122 { 2123 struct ifnet *ifp; 2124 struct bge_stats *stats; 2125 2126 ifp = &sc->arpcom.ac_if; 2127 2128 stats = (struct bge_stats *)(sc->bge_vhandle + 2129 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2130 2131 ifp->if_collisions += 2132 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2133 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2134 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2135 stats->dot3StatsLateCollisions.bge_addr_lo) - 2136 ifp->if_collisions; 2137 2138 #ifdef notdef 2139 ifp->if_collisions += 2140 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2141 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2142 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2143 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2144 ifp->if_collisions; 2145 #endif 2146 2147 return; 2148 } 2149 2150 /* 2151 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2152 * pointers to descriptors. 2153 */ 2154 static int 2155 bge_encap(sc, m_head, txidx) 2156 struct bge_softc *sc; 2157 struct mbuf *m_head; 2158 u_int32_t *txidx; 2159 { 2160 struct bge_tx_bd *f = NULL; 2161 struct mbuf *m; 2162 u_int32_t frag, cur, cnt = 0; 2163 u_int16_t csum_flags = 0; 2164 struct m_tag *mtag; 2165 2166 m = m_head; 2167 cur = frag = *txidx; 2168 2169 if (m_head->m_pkthdr.csum_flags) { 2170 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2171 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2172 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2173 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2174 if (m_head->m_flags & M_LASTFRAG) 2175 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2176 else if (m_head->m_flags & M_FRAG) 2177 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2178 } 2179 2180 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2181 2182 /* 2183 * Start packing the mbufs in this chain into 2184 * the fragment pointers. Stop when we run out 2185 * of fragments or hit the end of the mbuf chain. 2186 */ 2187 for (m = m_head; m != NULL; m = m->m_next) { 2188 if (m->m_len != 0) { 2189 f = &sc->bge_rdata->bge_tx_ring[frag]; 2190 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2191 break; 2192 BGE_HOSTADDR(f->bge_addr) = 2193 vtophys(mtod(m, vm_offset_t)); 2194 f->bge_len = m->m_len; 2195 f->bge_flags = csum_flags; 2196 if (mtag != NULL) { 2197 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2198 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2199 } else { 2200 f->bge_vlan_tag = 0; 2201 } 2202 /* 2203 * Sanity check: avoid coming within 16 descriptors 2204 * of the end of the ring. 2205 */ 2206 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2207 return(ENOBUFS); 2208 cur = frag; 2209 BGE_INC(frag, BGE_TX_RING_CNT); 2210 cnt++; 2211 } 2212 } 2213 2214 if (m != NULL) 2215 return(ENOBUFS); 2216 2217 if (frag == sc->bge_tx_saved_considx) 2218 return(ENOBUFS); 2219 2220 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2221 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2222 sc->bge_txcnt += cnt; 2223 2224 *txidx = frag; 2225 2226 return(0); 2227 } 2228 2229 /* 2230 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2231 * to the mbuf data regions directly in the transmit descriptors. 2232 */ 2233 static void 2234 bge_start(ifp) 2235 struct ifnet *ifp; 2236 { 2237 struct bge_softc *sc; 2238 struct mbuf *m_head = NULL; 2239 u_int32_t prodidx = 0; 2240 2241 sc = ifp->if_softc; 2242 2243 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2244 return; 2245 2246 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2247 2248 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2249 IF_DEQUEUE(&ifp->if_snd, m_head); 2250 if (m_head == NULL) 2251 break; 2252 2253 /* 2254 * XXX 2255 * safety overkill. If this is a fragmented packet chain 2256 * with delayed TCP/UDP checksums, then only encapsulate 2257 * it if we have enough descriptors to handle the entire 2258 * chain at once. 2259 * (paranoia -- may not actually be needed) 2260 */ 2261 if (m_head->m_flags & M_FIRSTFRAG && 2262 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2263 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2264 m_head->m_pkthdr.csum_data + 16) { 2265 IF_PREPEND(&ifp->if_snd, m_head); 2266 ifp->if_flags |= IFF_OACTIVE; 2267 break; 2268 } 2269 } 2270 2271 /* 2272 * Pack the data into the transmit ring. If we 2273 * don't have room, set the OACTIVE flag and wait 2274 * for the NIC to drain the ring. 2275 */ 2276 if (bge_encap(sc, m_head, &prodidx)) { 2277 IF_PREPEND(&ifp->if_snd, m_head); 2278 ifp->if_flags |= IFF_OACTIVE; 2279 break; 2280 } 2281 2282 /* 2283 * If there's a BPF listener, bounce a copy of this frame 2284 * to him. 2285 */ 2286 BPF_MTAP(ifp, m_head); 2287 } 2288 2289 /* Transmit */ 2290 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2291 2292 /* 2293 * Set a timeout in case the chip goes out to lunch. 2294 */ 2295 ifp->if_timer = 5; 2296 2297 return; 2298 } 2299 2300 /* 2301 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2302 * program its internal DSP. Failing to do this can result in 2303 * massive packet loss at 1Gb speeds. 2304 */ 2305 static void 2306 bge_phy_hack(sc) 2307 struct bge_softc *sc; 2308 { 2309 struct bge_bcom_hack bhack[] = { 2310 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2311 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2312 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2313 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2314 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2315 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2316 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2317 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2318 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2319 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2320 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2321 { 0, 0 } }; 2322 u_int16_t vid, did; 2323 int i; 2324 2325 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2326 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2327 2328 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2329 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2330 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2331 i = 0; 2332 while(bhack[i].reg) { 2333 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2334 bhack[i].val); 2335 i++; 2336 } 2337 } 2338 2339 return; 2340 } 2341 2342 static void 2343 bge_init(xsc) 2344 void *xsc; 2345 { 2346 struct bge_softc *sc = xsc; 2347 struct ifnet *ifp; 2348 u_int16_t *m; 2349 int s; 2350 2351 s = splimp(); 2352 2353 ifp = &sc->arpcom.ac_if; 2354 2355 if (ifp->if_flags & IFF_RUNNING) { 2356 splx(s); 2357 return; 2358 } 2359 2360 /* Cancel pending I/O and flush buffers. */ 2361 bge_stop(sc); 2362 bge_reset(sc); 2363 bge_chipinit(sc); 2364 2365 /* 2366 * Init the various state machines, ring 2367 * control blocks and firmware. 2368 */ 2369 if (bge_blockinit(sc)) { 2370 printf("bge%d: initialization failure\n", sc->bge_unit); 2371 splx(s); 2372 return; 2373 } 2374 2375 ifp = &sc->arpcom.ac_if; 2376 2377 /* Specify MTU. */ 2378 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2379 ETHER_HDR_LEN + ETHER_CRC_LEN); 2380 2381 /* Load our MAC address. */ 2382 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2383 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2384 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2385 2386 /* Enable or disable promiscuous mode as needed. */ 2387 if (ifp->if_flags & IFF_PROMISC) { 2388 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2389 } else { 2390 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2391 } 2392 2393 /* Program multicast filter. */ 2394 bge_setmulti(sc); 2395 2396 /* Init RX ring. */ 2397 bge_init_rx_ring_std(sc); 2398 2399 /* Init jumbo RX ring. */ 2400 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2401 bge_init_rx_ring_jumbo(sc); 2402 2403 /* Init our RX return ring index */ 2404 sc->bge_rx_saved_considx = 0; 2405 2406 /* Init TX ring. */ 2407 bge_init_tx_ring(sc); 2408 2409 /* Turn on transmitter */ 2410 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2411 2412 /* Turn on receiver */ 2413 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2414 2415 /* Tell firmware we're alive. */ 2416 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2417 2418 /* Enable host interrupts. */ 2419 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2420 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2421 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2422 2423 bge_ifmedia_upd(ifp); 2424 2425 ifp->if_flags |= IFF_RUNNING; 2426 ifp->if_flags &= ~IFF_OACTIVE; 2427 2428 splx(s); 2429 2430 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2431 2432 return; 2433 } 2434 2435 /* 2436 * Set media options. 2437 */ 2438 static int 2439 bge_ifmedia_upd(ifp) 2440 struct ifnet *ifp; 2441 { 2442 struct bge_softc *sc; 2443 struct mii_data *mii; 2444 struct ifmedia *ifm; 2445 2446 sc = ifp->if_softc; 2447 ifm = &sc->bge_ifmedia; 2448 2449 /* If this is a 1000baseX NIC, enable the TBI port. */ 2450 if (sc->bge_tbi) { 2451 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2452 return(EINVAL); 2453 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2454 case IFM_AUTO: 2455 break; 2456 case IFM_1000_SX: 2457 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2458 BGE_CLRBIT(sc, BGE_MAC_MODE, 2459 BGE_MACMODE_HALF_DUPLEX); 2460 } else { 2461 BGE_SETBIT(sc, BGE_MAC_MODE, 2462 BGE_MACMODE_HALF_DUPLEX); 2463 } 2464 break; 2465 default: 2466 return(EINVAL); 2467 } 2468 return(0); 2469 } 2470 2471 mii = device_get_softc(sc->bge_miibus); 2472 sc->bge_link = 0; 2473 if (mii->mii_instance) { 2474 struct mii_softc *miisc; 2475 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2476 miisc = LIST_NEXT(miisc, mii_list)) 2477 mii_phy_reset(miisc); 2478 } 2479 bge_phy_hack(sc); 2480 mii_mediachg(mii); 2481 2482 return(0); 2483 } 2484 2485 /* 2486 * Report current media status. 2487 */ 2488 static void 2489 bge_ifmedia_sts(ifp, ifmr) 2490 struct ifnet *ifp; 2491 struct ifmediareq *ifmr; 2492 { 2493 struct bge_softc *sc; 2494 struct mii_data *mii; 2495 2496 sc = ifp->if_softc; 2497 2498 if (sc->bge_tbi) { 2499 ifmr->ifm_status = IFM_AVALID; 2500 ifmr->ifm_active = IFM_ETHER; 2501 if (CSR_READ_4(sc, BGE_MAC_STS) & 2502 BGE_MACSTAT_TBI_PCS_SYNCHED) 2503 ifmr->ifm_status |= IFM_ACTIVE; 2504 ifmr->ifm_active |= IFM_1000_SX; 2505 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2506 ifmr->ifm_active |= IFM_HDX; 2507 else 2508 ifmr->ifm_active |= IFM_FDX; 2509 return; 2510 } 2511 2512 mii = device_get_softc(sc->bge_miibus); 2513 mii_pollstat(mii); 2514 ifmr->ifm_active = mii->mii_media_active; 2515 ifmr->ifm_status = mii->mii_media_status; 2516 2517 return; 2518 } 2519 2520 static int 2521 bge_ioctl(ifp, command, data) 2522 struct ifnet *ifp; 2523 u_long command; 2524 caddr_t data; 2525 { 2526 struct bge_softc *sc = ifp->if_softc; 2527 struct ifreq *ifr = (struct ifreq *) data; 2528 int s, mask, error = 0; 2529 struct mii_data *mii; 2530 2531 s = splimp(); 2532 2533 switch(command) { 2534 case SIOCSIFMTU: 2535 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2536 error = EINVAL; 2537 else { 2538 ifp->if_mtu = ifr->ifr_mtu; 2539 ifp->if_flags &= ~IFF_RUNNING; 2540 bge_init(sc); 2541 } 2542 break; 2543 case SIOCSIFFLAGS: 2544 if (ifp->if_flags & IFF_UP) { 2545 /* 2546 * If only the state of the PROMISC flag changed, 2547 * then just use the 'set promisc mode' command 2548 * instead of reinitializing the entire NIC. Doing 2549 * a full re-init means reloading the firmware and 2550 * waiting for it to start up, which may take a 2551 * second or two. 2552 */ 2553 if (ifp->if_flags & IFF_RUNNING && 2554 ifp->if_flags & IFF_PROMISC && 2555 !(sc->bge_if_flags & IFF_PROMISC)) { 2556 BGE_SETBIT(sc, BGE_RX_MODE, 2557 BGE_RXMODE_RX_PROMISC); 2558 } else if (ifp->if_flags & IFF_RUNNING && 2559 !(ifp->if_flags & IFF_PROMISC) && 2560 sc->bge_if_flags & IFF_PROMISC) { 2561 BGE_CLRBIT(sc, BGE_RX_MODE, 2562 BGE_RXMODE_RX_PROMISC); 2563 } else 2564 bge_init(sc); 2565 } else { 2566 if (ifp->if_flags & IFF_RUNNING) { 2567 bge_stop(sc); 2568 } 2569 } 2570 sc->bge_if_flags = ifp->if_flags; 2571 error = 0; 2572 break; 2573 case SIOCADDMULTI: 2574 case SIOCDELMULTI: 2575 if (ifp->if_flags & IFF_RUNNING) { 2576 bge_setmulti(sc); 2577 error = 0; 2578 } 2579 break; 2580 case SIOCSIFMEDIA: 2581 case SIOCGIFMEDIA: 2582 if (sc->bge_tbi) { 2583 error = ifmedia_ioctl(ifp, ifr, 2584 &sc->bge_ifmedia, command); 2585 } else { 2586 mii = device_get_softc(sc->bge_miibus); 2587 error = ifmedia_ioctl(ifp, ifr, 2588 &mii->mii_media, command); 2589 } 2590 break; 2591 case SIOCSIFCAP: 2592 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2593 if (mask & IFCAP_HWCSUM) { 2594 if (IFCAP_HWCSUM & ifp->if_capenable) 2595 ifp->if_capenable &= ~IFCAP_HWCSUM; 2596 else 2597 ifp->if_capenable |= IFCAP_HWCSUM; 2598 } 2599 error = 0; 2600 break; 2601 default: 2602 error = ether_ioctl(ifp, command, data); 2603 break; 2604 } 2605 2606 (void)splx(s); 2607 2608 return(error); 2609 } 2610 2611 static void 2612 bge_watchdog(ifp) 2613 struct ifnet *ifp; 2614 { 2615 struct bge_softc *sc; 2616 2617 sc = ifp->if_softc; 2618 2619 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2620 2621 ifp->if_flags &= ~IFF_RUNNING; 2622 bge_init(sc); 2623 2624 ifp->if_oerrors++; 2625 2626 return; 2627 } 2628 2629 /* 2630 * Stop the adapter and free any mbufs allocated to the 2631 * RX and TX lists. 2632 */ 2633 static void 2634 bge_stop(sc) 2635 struct bge_softc *sc; 2636 { 2637 struct ifnet *ifp; 2638 struct ifmedia_entry *ifm; 2639 struct mii_data *mii = NULL; 2640 int mtmp, itmp; 2641 2642 ifp = &sc->arpcom.ac_if; 2643 2644 if (!sc->bge_tbi) 2645 mii = device_get_softc(sc->bge_miibus); 2646 2647 untimeout(bge_tick, sc, sc->bge_stat_ch); 2648 2649 /* 2650 * Disable all of the receiver blocks 2651 */ 2652 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2653 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2654 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2655 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2656 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2657 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2658 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2659 2660 /* 2661 * Disable all of the transmit blocks 2662 */ 2663 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2664 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2665 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2666 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2667 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2668 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2669 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2670 2671 /* 2672 * Shut down all of the memory managers and related 2673 * state machines. 2674 */ 2675 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2676 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2677 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2678 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2679 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2680 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2681 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2682 2683 /* Disable host interrupts. */ 2684 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2685 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2686 2687 /* 2688 * Tell firmware we're shutting down. 2689 */ 2690 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2691 2692 /* Free the RX lists. */ 2693 bge_free_rx_ring_std(sc); 2694 2695 /* Free jumbo RX list. */ 2696 bge_free_rx_ring_jumbo(sc); 2697 2698 /* Free TX buffers. */ 2699 bge_free_tx_ring(sc); 2700 2701 /* 2702 * Isolate/power down the PHY, but leave the media selection 2703 * unchanged so that things will be put back to normal when 2704 * we bring the interface back up. 2705 */ 2706 if (!sc->bge_tbi) { 2707 itmp = ifp->if_flags; 2708 ifp->if_flags |= IFF_UP; 2709 ifm = mii->mii_media.ifm_cur; 2710 mtmp = ifm->ifm_media; 2711 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2712 mii_mediachg(mii); 2713 ifm->ifm_media = mtmp; 2714 ifp->if_flags = itmp; 2715 } 2716 2717 sc->bge_link = 0; 2718 2719 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2720 2721 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2722 2723 return; 2724 } 2725 2726 /* 2727 * Stop all chip I/O so that the kernel's probe routines don't 2728 * get confused by errant DMAs when rebooting. 2729 */ 2730 static void 2731 bge_shutdown(dev) 2732 device_t dev; 2733 { 2734 struct bge_softc *sc; 2735 2736 sc = device_get_softc(dev); 2737 2738 bge_stop(sc); 2739 bge_reset(sc); 2740 2741 return; 2742 } 2743