1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } const bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 227 228 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 229 230 { TC_VENDORID, TC_DEVICEID_3C996 }, 231 232 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 233 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 234 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 235 236 { 0, 0 } 237 }; 238 239 static const struct bge_vendor { 240 uint16_t v_id; 241 const char *v_name; 242 } const bge_vendors[] = { 243 { ALTEON_VENDORID, "Alteon" }, 244 { ALTIMA_VENDORID, "Altima" }, 245 { APPLE_VENDORID, "Apple" }, 246 { BCOM_VENDORID, "Broadcom" }, 247 { SK_VENDORID, "SysKonnect" }, 248 { TC_VENDORID, "3Com" }, 249 { FJTSU_VENDORID, "Fujitsu" }, 250 251 { 0, NULL } 252 }; 253 254 static const struct bge_revision { 255 uint32_t br_chipid; 256 const char *br_name; 257 } const bge_revisions[] = { 258 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 259 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 260 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 261 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 262 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 263 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 264 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 265 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 266 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 267 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 268 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 269 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 270 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 271 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 272 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 273 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 274 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 275 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 276 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 277 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 278 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 279 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 280 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 281 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 282 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 283 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 284 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 285 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 286 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 287 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 288 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 289 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 290 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 291 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 292 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 293 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 294 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 295 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 304 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 305 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 306 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 307 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 308 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 309 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 310 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 311 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 312 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 313 /* 5754 and 5787 share the same ASIC ID */ 314 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 315 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 316 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 317 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 318 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 319 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 320 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 321 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 322 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 323 324 { 0, NULL } 325 }; 326 327 /* 328 * Some defaults for major revisions, so that newer steppings 329 * that we don't know about have a shot at working. 330 */ 331 static const struct bge_revision const bge_majorrevs[] = { 332 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 333 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 334 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 335 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 336 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 337 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 338 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 339 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 340 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 341 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 342 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 343 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 344 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 345 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 346 /* 5754 and 5787 share the same ASIC ID */ 347 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 348 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 349 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 350 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 351 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 352 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 353 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 354 355 { 0, NULL } 356 }; 357 358 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 359 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 360 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 361 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 362 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 363 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 364 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 365 366 const struct bge_revision * bge_lookup_rev(uint32_t); 367 const struct bge_vendor * bge_lookup_vendor(uint16_t); 368 369 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 370 371 static int bge_probe(device_t); 372 static int bge_attach(device_t); 373 static int bge_detach(device_t); 374 static int bge_suspend(device_t); 375 static int bge_resume(device_t); 376 static void bge_release_resources(struct bge_softc *); 377 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 378 static int bge_dma_alloc(struct bge_softc *); 379 static void bge_dma_free(struct bge_softc *); 380 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 381 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 382 383 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 384 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 385 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 386 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 387 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 388 389 static void bge_txeof(struct bge_softc *, uint16_t); 390 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 391 static int bge_rxeof(struct bge_softc *, uint16_t, int); 392 393 static void bge_asf_driver_up (struct bge_softc *); 394 static void bge_tick(void *); 395 static void bge_stats_clear_regs(struct bge_softc *); 396 static void bge_stats_update(struct bge_softc *); 397 static void bge_stats_update_regs(struct bge_softc *); 398 static struct mbuf *bge_check_short_dma(struct mbuf *); 399 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 400 uint16_t *, uint16_t *); 401 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 402 403 static void bge_intr(void *); 404 static int bge_msi_intr(void *); 405 static void bge_intr_task(void *, int); 406 static void bge_start_locked(struct ifnet *); 407 static void bge_start(struct ifnet *); 408 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 409 static void bge_init_locked(struct bge_softc *); 410 static void bge_init(void *); 411 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 412 static void bge_stop(struct bge_softc *); 413 static void bge_watchdog(struct bge_softc *); 414 static int bge_shutdown(device_t); 415 static int bge_ifmedia_upd_locked(struct ifnet *); 416 static int bge_ifmedia_upd(struct ifnet *); 417 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 418 419 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 420 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 421 422 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 423 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 424 425 static void bge_setpromisc(struct bge_softc *); 426 static void bge_setmulti(struct bge_softc *); 427 static void bge_setvlan(struct bge_softc *); 428 429 static __inline void bge_rxreuse_std(struct bge_softc *, int); 430 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 431 static int bge_newbuf_std(struct bge_softc *, int); 432 static int bge_newbuf_jumbo(struct bge_softc *, int); 433 static int bge_init_rx_ring_std(struct bge_softc *); 434 static void bge_free_rx_ring_std(struct bge_softc *); 435 static int bge_init_rx_ring_jumbo(struct bge_softc *); 436 static void bge_free_rx_ring_jumbo(struct bge_softc *); 437 static void bge_free_tx_ring(struct bge_softc *); 438 static int bge_init_tx_ring(struct bge_softc *); 439 440 static int bge_chipinit(struct bge_softc *); 441 static int bge_blockinit(struct bge_softc *); 442 static uint32_t bge_dma_swap_options(struct bge_softc *); 443 444 static int bge_has_eaddr(struct bge_softc *); 445 static uint32_t bge_readmem_ind(struct bge_softc *, int); 446 static void bge_writemem_ind(struct bge_softc *, int, int); 447 static void bge_writembx(struct bge_softc *, int, int); 448 #ifdef notdef 449 static uint32_t bge_readreg_ind(struct bge_softc *, int); 450 #endif 451 static void bge_writemem_direct(struct bge_softc *, int, int); 452 static void bge_writereg_ind(struct bge_softc *, int, int); 453 454 static int bge_miibus_readreg(device_t, int, int); 455 static int bge_miibus_writereg(device_t, int, int, int); 456 static void bge_miibus_statchg(device_t); 457 #ifdef DEVICE_POLLING 458 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 459 #endif 460 461 #define BGE_RESET_START 1 462 #define BGE_RESET_STOP 2 463 static void bge_sig_post_reset(struct bge_softc *, int); 464 static void bge_sig_legacy(struct bge_softc *, int); 465 static void bge_sig_pre_reset(struct bge_softc *, int); 466 static void bge_stop_fw(struct bge_softc *); 467 static int bge_reset(struct bge_softc *); 468 static void bge_link_upd(struct bge_softc *); 469 470 /* 471 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 472 * leak information to untrusted users. It is also known to cause alignment 473 * traps on certain architectures. 474 */ 475 #ifdef BGE_REGISTER_DEBUG 476 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 477 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 478 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 479 #endif 480 static void bge_add_sysctls(struct bge_softc *); 481 static void bge_add_sysctl_stats_regs(struct bge_softc *, 482 struct sysctl_ctx_list *, struct sysctl_oid_list *); 483 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 484 struct sysctl_oid_list *); 485 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 486 487 static device_method_t bge_methods[] = { 488 /* Device interface */ 489 DEVMETHOD(device_probe, bge_probe), 490 DEVMETHOD(device_attach, bge_attach), 491 DEVMETHOD(device_detach, bge_detach), 492 DEVMETHOD(device_shutdown, bge_shutdown), 493 DEVMETHOD(device_suspend, bge_suspend), 494 DEVMETHOD(device_resume, bge_resume), 495 496 /* MII interface */ 497 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 498 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 499 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 500 501 DEVMETHOD_END 502 }; 503 504 static driver_t bge_driver = { 505 "bge", 506 bge_methods, 507 sizeof(struct bge_softc) 508 }; 509 510 static devclass_t bge_devclass; 511 512 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 513 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 514 515 static int bge_allow_asf = 1; 516 517 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 518 519 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 520 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 521 "Allow ASF mode if available"); 522 523 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 524 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 525 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 526 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 527 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 528 529 static int 530 bge_has_eaddr(struct bge_softc *sc) 531 { 532 #ifdef __sparc64__ 533 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 534 device_t dev; 535 uint32_t subvendor; 536 537 dev = sc->bge_dev; 538 539 /* 540 * The on-board BGEs found in sun4u machines aren't fitted with 541 * an EEPROM which means that we have to obtain the MAC address 542 * via OFW and that some tests will always fail. We distinguish 543 * such BGEs by the subvendor ID, which also has to be obtained 544 * from OFW instead of the PCI configuration space as the latter 545 * indicates Broadcom as the subvendor of the netboot interface. 546 * For early Blade 1500 and 2500 we even have to check the OFW 547 * device path as the subvendor ID always defaults to Broadcom 548 * there. 549 */ 550 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 551 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 552 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 553 return (0); 554 memset(buf, 0, sizeof(buf)); 555 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 556 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 557 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 558 return (0); 559 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 560 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 561 return (0); 562 } 563 #endif 564 return (1); 565 } 566 567 static uint32_t 568 bge_readmem_ind(struct bge_softc *sc, int off) 569 { 570 device_t dev; 571 uint32_t val; 572 573 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 574 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 575 return (0); 576 577 dev = sc->bge_dev; 578 579 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 580 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 581 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 582 return (val); 583 } 584 585 static void 586 bge_writemem_ind(struct bge_softc *sc, int off, int val) 587 { 588 device_t dev; 589 590 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 591 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 592 return; 593 594 dev = sc->bge_dev; 595 596 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 597 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 598 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 599 } 600 601 #ifdef notdef 602 static uint32_t 603 bge_readreg_ind(struct bge_softc *sc, int off) 604 { 605 device_t dev; 606 607 dev = sc->bge_dev; 608 609 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 610 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 611 } 612 #endif 613 614 static void 615 bge_writereg_ind(struct bge_softc *sc, int off, int val) 616 { 617 device_t dev; 618 619 dev = sc->bge_dev; 620 621 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 622 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 623 } 624 625 static void 626 bge_writemem_direct(struct bge_softc *sc, int off, int val) 627 { 628 CSR_WRITE_4(sc, off, val); 629 } 630 631 static void 632 bge_writembx(struct bge_softc *sc, int off, int val) 633 { 634 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 635 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 636 637 CSR_WRITE_4(sc, off, val); 638 } 639 640 /* 641 * Map a single buffer address. 642 */ 643 644 static void 645 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 646 { 647 struct bge_dmamap_arg *ctx; 648 649 if (error) 650 return; 651 652 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 653 654 ctx = arg; 655 ctx->bge_busaddr = segs->ds_addr; 656 } 657 658 static uint8_t 659 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 660 { 661 uint32_t access, byte = 0; 662 int i; 663 664 /* Lock. */ 665 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 666 for (i = 0; i < 8000; i++) { 667 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 668 break; 669 DELAY(20); 670 } 671 if (i == 8000) 672 return (1); 673 674 /* Enable access. */ 675 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 676 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 677 678 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 679 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 680 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 681 DELAY(10); 682 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 683 DELAY(10); 684 break; 685 } 686 } 687 688 if (i == BGE_TIMEOUT * 10) { 689 if_printf(sc->bge_ifp, "nvram read timed out\n"); 690 return (1); 691 } 692 693 /* Get result. */ 694 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 695 696 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 697 698 /* Disable access. */ 699 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 700 701 /* Unlock. */ 702 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 703 CSR_READ_4(sc, BGE_NVRAM_SWARB); 704 705 return (0); 706 } 707 708 /* 709 * Read a sequence of bytes from NVRAM. 710 */ 711 static int 712 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 713 { 714 int err = 0, i; 715 uint8_t byte = 0; 716 717 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 718 return (1); 719 720 for (i = 0; i < cnt; i++) { 721 err = bge_nvram_getbyte(sc, off + i, &byte); 722 if (err) 723 break; 724 *(dest + i) = byte; 725 } 726 727 return (err ? 1 : 0); 728 } 729 730 /* 731 * Read a byte of data stored in the EEPROM at address 'addr.' The 732 * BCM570x supports both the traditional bitbang interface and an 733 * auto access interface for reading the EEPROM. We use the auto 734 * access method. 735 */ 736 static uint8_t 737 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 738 { 739 int i; 740 uint32_t byte = 0; 741 742 /* 743 * Enable use of auto EEPROM access so we can avoid 744 * having to use the bitbang method. 745 */ 746 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 747 748 /* Reset the EEPROM, load the clock period. */ 749 CSR_WRITE_4(sc, BGE_EE_ADDR, 750 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 751 DELAY(20); 752 753 /* Issue the read EEPROM command. */ 754 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 755 756 /* Wait for completion */ 757 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 758 DELAY(10); 759 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 760 break; 761 } 762 763 if (i == BGE_TIMEOUT * 10) { 764 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 765 return (1); 766 } 767 768 /* Get result. */ 769 byte = CSR_READ_4(sc, BGE_EE_DATA); 770 771 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 772 773 return (0); 774 } 775 776 /* 777 * Read a sequence of bytes from the EEPROM. 778 */ 779 static int 780 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 781 { 782 int i, error = 0; 783 uint8_t byte = 0; 784 785 for (i = 0; i < cnt; i++) { 786 error = bge_eeprom_getbyte(sc, off + i, &byte); 787 if (error) 788 break; 789 *(dest + i) = byte; 790 } 791 792 return (error ? 1 : 0); 793 } 794 795 static int 796 bge_miibus_readreg(device_t dev, int phy, int reg) 797 { 798 struct bge_softc *sc; 799 uint32_t val; 800 int i; 801 802 sc = device_get_softc(dev); 803 804 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 805 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 806 CSR_WRITE_4(sc, BGE_MI_MODE, 807 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 808 DELAY(80); 809 } 810 811 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 812 BGE_MIPHY(phy) | BGE_MIREG(reg)); 813 814 /* Poll for the PHY register access to complete. */ 815 for (i = 0; i < BGE_TIMEOUT; i++) { 816 DELAY(10); 817 val = CSR_READ_4(sc, BGE_MI_COMM); 818 if ((val & BGE_MICOMM_BUSY) == 0) { 819 DELAY(5); 820 val = CSR_READ_4(sc, BGE_MI_COMM); 821 break; 822 } 823 } 824 825 if (i == BGE_TIMEOUT) { 826 device_printf(sc->bge_dev, 827 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 828 phy, reg, val); 829 val = 0; 830 } 831 832 /* Restore the autopoll bit if necessary. */ 833 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 834 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 835 DELAY(80); 836 } 837 838 if (val & BGE_MICOMM_READFAIL) 839 return (0); 840 841 return (val & 0xFFFF); 842 } 843 844 static int 845 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 846 { 847 struct bge_softc *sc; 848 int i; 849 850 sc = device_get_softc(dev); 851 852 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 853 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 854 return (0); 855 856 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 857 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 858 CSR_WRITE_4(sc, BGE_MI_MODE, 859 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 860 DELAY(80); 861 } 862 863 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 864 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 865 866 for (i = 0; i < BGE_TIMEOUT; i++) { 867 DELAY(10); 868 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 869 DELAY(5); 870 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 871 break; 872 } 873 } 874 875 /* Restore the autopoll bit if necessary. */ 876 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 877 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 878 DELAY(80); 879 } 880 881 if (i == BGE_TIMEOUT) 882 device_printf(sc->bge_dev, 883 "PHY write timed out (phy %d, reg %d, val %d)\n", 884 phy, reg, val); 885 886 return (0); 887 } 888 889 static void 890 bge_miibus_statchg(device_t dev) 891 { 892 struct bge_softc *sc; 893 struct mii_data *mii; 894 sc = device_get_softc(dev); 895 mii = device_get_softc(sc->bge_miibus); 896 897 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 898 (IFM_ACTIVE | IFM_AVALID)) { 899 switch (IFM_SUBTYPE(mii->mii_media_active)) { 900 case IFM_10_T: 901 case IFM_100_TX: 902 sc->bge_link = 1; 903 break; 904 case IFM_1000_T: 905 case IFM_1000_SX: 906 case IFM_2500_SX: 907 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 908 sc->bge_link = 1; 909 else 910 sc->bge_link = 0; 911 break; 912 default: 913 sc->bge_link = 0; 914 break; 915 } 916 } else 917 sc->bge_link = 0; 918 if (sc->bge_link == 0) 919 return; 920 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 921 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 922 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 923 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 924 else 925 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 926 927 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 928 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 929 if ((IFM_OPTIONS(mii->mii_media_active) & 930 IFM_ETH_TXPAUSE) != 0) 931 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 932 else 933 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 934 if ((IFM_OPTIONS(mii->mii_media_active) & 935 IFM_ETH_RXPAUSE) != 0) 936 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 937 else 938 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 939 } else { 940 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 941 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 942 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 943 } 944 } 945 946 /* 947 * Intialize a standard receive ring descriptor. 948 */ 949 static int 950 bge_newbuf_std(struct bge_softc *sc, int i) 951 { 952 struct mbuf *m; 953 struct bge_rx_bd *r; 954 bus_dma_segment_t segs[1]; 955 bus_dmamap_t map; 956 int error, nsegs; 957 958 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 959 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 960 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 961 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 962 if (m == NULL) 963 return (ENOBUFS); 964 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 965 } else { 966 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 967 if (m == NULL) 968 return (ENOBUFS); 969 m->m_len = m->m_pkthdr.len = MCLBYTES; 970 } 971 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 972 m_adj(m, ETHER_ALIGN); 973 974 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 975 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 976 if (error != 0) { 977 m_freem(m); 978 return (error); 979 } 980 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 981 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 982 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 983 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 984 sc->bge_cdata.bge_rx_std_dmamap[i]); 985 } 986 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 987 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 988 sc->bge_cdata.bge_rx_std_sparemap = map; 989 sc->bge_cdata.bge_rx_std_chain[i] = m; 990 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 991 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 992 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 993 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 994 r->bge_flags = BGE_RXBDFLAG_END; 995 r->bge_len = segs[0].ds_len; 996 r->bge_idx = i; 997 998 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 999 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1000 1001 return (0); 1002 } 1003 1004 /* 1005 * Initialize a jumbo receive ring descriptor. This allocates 1006 * a jumbo buffer from the pool managed internally by the driver. 1007 */ 1008 static int 1009 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1010 { 1011 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1012 bus_dmamap_t map; 1013 struct bge_extrx_bd *r; 1014 struct mbuf *m; 1015 int error, nsegs; 1016 1017 MGETHDR(m, M_DONTWAIT, MT_DATA); 1018 if (m == NULL) 1019 return (ENOBUFS); 1020 1021 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 1022 if (!(m->m_flags & M_EXT)) { 1023 m_freem(m); 1024 return (ENOBUFS); 1025 } 1026 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1027 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1028 m_adj(m, ETHER_ALIGN); 1029 1030 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1031 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1032 if (error != 0) { 1033 m_freem(m); 1034 return (error); 1035 } 1036 1037 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1038 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1039 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1040 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1041 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1042 } 1043 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1044 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1045 sc->bge_cdata.bge_rx_jumbo_sparemap; 1046 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1047 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1048 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1049 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1050 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1051 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1052 1053 /* 1054 * Fill in the extended RX buffer descriptor. 1055 */ 1056 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1057 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1058 r->bge_idx = i; 1059 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1060 switch (nsegs) { 1061 case 4: 1062 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1063 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1064 r->bge_len3 = segs[3].ds_len; 1065 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1066 case 3: 1067 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1068 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1069 r->bge_len2 = segs[2].ds_len; 1070 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1071 case 2: 1072 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1073 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1074 r->bge_len1 = segs[1].ds_len; 1075 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1076 case 1: 1077 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1078 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1079 r->bge_len0 = segs[0].ds_len; 1080 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1081 break; 1082 default: 1083 panic("%s: %d segments\n", __func__, nsegs); 1084 } 1085 1086 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1087 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1088 1089 return (0); 1090 } 1091 1092 static int 1093 bge_init_rx_ring_std(struct bge_softc *sc) 1094 { 1095 int error, i; 1096 1097 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1098 sc->bge_std = 0; 1099 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1100 if ((error = bge_newbuf_std(sc, i)) != 0) 1101 return (error); 1102 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1103 } 1104 1105 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1106 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1107 1108 sc->bge_std = 0; 1109 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1110 1111 return (0); 1112 } 1113 1114 static void 1115 bge_free_rx_ring_std(struct bge_softc *sc) 1116 { 1117 int i; 1118 1119 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1120 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1121 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1122 sc->bge_cdata.bge_rx_std_dmamap[i], 1123 BUS_DMASYNC_POSTREAD); 1124 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1125 sc->bge_cdata.bge_rx_std_dmamap[i]); 1126 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1127 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1128 } 1129 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1130 sizeof(struct bge_rx_bd)); 1131 } 1132 } 1133 1134 static int 1135 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1136 { 1137 struct bge_rcb *rcb; 1138 int error, i; 1139 1140 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1141 sc->bge_jumbo = 0; 1142 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1143 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1144 return (error); 1145 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1146 } 1147 1148 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1149 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1150 1151 sc->bge_jumbo = 0; 1152 1153 /* Enable the jumbo receive producer ring. */ 1154 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1155 rcb->bge_maxlen_flags = 1156 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1157 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1158 1159 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1160 1161 return (0); 1162 } 1163 1164 static void 1165 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1166 { 1167 int i; 1168 1169 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1170 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1171 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1172 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1173 BUS_DMASYNC_POSTREAD); 1174 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1175 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1176 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1177 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1178 } 1179 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1180 sizeof(struct bge_extrx_bd)); 1181 } 1182 } 1183 1184 static void 1185 bge_free_tx_ring(struct bge_softc *sc) 1186 { 1187 int i; 1188 1189 if (sc->bge_ldata.bge_tx_ring == NULL) 1190 return; 1191 1192 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1193 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1194 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1195 sc->bge_cdata.bge_tx_dmamap[i], 1196 BUS_DMASYNC_POSTWRITE); 1197 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1198 sc->bge_cdata.bge_tx_dmamap[i]); 1199 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1200 sc->bge_cdata.bge_tx_chain[i] = NULL; 1201 } 1202 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1203 sizeof(struct bge_tx_bd)); 1204 } 1205 } 1206 1207 static int 1208 bge_init_tx_ring(struct bge_softc *sc) 1209 { 1210 sc->bge_txcnt = 0; 1211 sc->bge_tx_saved_considx = 0; 1212 1213 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1214 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1215 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1216 1217 /* Initialize transmit producer index for host-memory send ring. */ 1218 sc->bge_tx_prodidx = 0; 1219 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1220 1221 /* 5700 b2 errata */ 1222 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1223 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1224 1225 /* NIC-memory send ring not used; initialize to zero. */ 1226 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1227 /* 5700 b2 errata */ 1228 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1229 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1230 1231 return (0); 1232 } 1233 1234 static void 1235 bge_setpromisc(struct bge_softc *sc) 1236 { 1237 struct ifnet *ifp; 1238 1239 BGE_LOCK_ASSERT(sc); 1240 1241 ifp = sc->bge_ifp; 1242 1243 /* Enable or disable promiscuous mode as needed. */ 1244 if (ifp->if_flags & IFF_PROMISC) 1245 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1246 else 1247 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1248 } 1249 1250 static void 1251 bge_setmulti(struct bge_softc *sc) 1252 { 1253 struct ifnet *ifp; 1254 struct ifmultiaddr *ifma; 1255 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1256 int h, i; 1257 1258 BGE_LOCK_ASSERT(sc); 1259 1260 ifp = sc->bge_ifp; 1261 1262 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1263 for (i = 0; i < 4; i++) 1264 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1265 return; 1266 } 1267 1268 /* First, zot all the existing filters. */ 1269 for (i = 0; i < 4; i++) 1270 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1271 1272 /* Now program new ones. */ 1273 if_maddr_rlock(ifp); 1274 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1275 if (ifma->ifma_addr->sa_family != AF_LINK) 1276 continue; 1277 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1278 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1279 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1280 } 1281 if_maddr_runlock(ifp); 1282 1283 for (i = 0; i < 4; i++) 1284 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1285 } 1286 1287 static void 1288 bge_setvlan(struct bge_softc *sc) 1289 { 1290 struct ifnet *ifp; 1291 1292 BGE_LOCK_ASSERT(sc); 1293 1294 ifp = sc->bge_ifp; 1295 1296 /* Enable or disable VLAN tag stripping as needed. */ 1297 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1298 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1299 else 1300 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1301 } 1302 1303 static void 1304 bge_sig_pre_reset(struct bge_softc *sc, int type) 1305 { 1306 1307 /* 1308 * Some chips don't like this so only do this if ASF is enabled 1309 */ 1310 if (sc->bge_asf_mode) 1311 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1312 1313 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1314 switch (type) { 1315 case BGE_RESET_START: 1316 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1317 BGE_FW_DRV_STATE_START); 1318 break; 1319 case BGE_RESET_STOP: 1320 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1321 BGE_FW_DRV_STATE_UNLOAD); 1322 break; 1323 } 1324 } 1325 } 1326 1327 static void 1328 bge_sig_post_reset(struct bge_softc *sc, int type) 1329 { 1330 1331 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1332 switch (type) { 1333 case BGE_RESET_START: 1334 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1335 BGE_FW_DRV_STATE_START_DONE); 1336 /* START DONE */ 1337 break; 1338 case BGE_RESET_STOP: 1339 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1340 BGE_FW_DRV_STATE_UNLOAD_DONE); 1341 break; 1342 } 1343 } 1344 } 1345 1346 static void 1347 bge_sig_legacy(struct bge_softc *sc, int type) 1348 { 1349 1350 if (sc->bge_asf_mode) { 1351 switch (type) { 1352 case BGE_RESET_START: 1353 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1354 BGE_FW_DRV_STATE_START); 1355 break; 1356 case BGE_RESET_STOP: 1357 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1358 BGE_FW_DRV_STATE_UNLOAD); 1359 break; 1360 } 1361 } 1362 } 1363 1364 static void 1365 bge_stop_fw(struct bge_softc *sc) 1366 { 1367 int i; 1368 1369 if (sc->bge_asf_mode) { 1370 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1371 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1372 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1373 1374 for (i = 0; i < 100; i++ ) { 1375 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1376 BGE_RX_CPU_DRV_EVENT)) 1377 break; 1378 DELAY(10); 1379 } 1380 } 1381 } 1382 1383 static uint32_t 1384 bge_dma_swap_options(struct bge_softc *sc) 1385 { 1386 uint32_t dma_options; 1387 1388 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1389 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1390 #if BYTE_ORDER == BIG_ENDIAN 1391 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1392 #endif 1393 if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720) 1394 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1395 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE | 1396 BGE_MODECTL_HTX2B_ENABLE; 1397 1398 return (dma_options); 1399 } 1400 1401 /* 1402 * Do endian, PCI and DMA initialization. 1403 */ 1404 static int 1405 bge_chipinit(struct bge_softc *sc) 1406 { 1407 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1408 uint16_t val; 1409 int i; 1410 1411 /* Set endianness before we access any non-PCI registers. */ 1412 misc_ctl = BGE_INIT; 1413 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1414 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1415 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1416 1417 /* Clear the MAC control register */ 1418 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1419 1420 /* 1421 * Clear the MAC statistics block in the NIC's 1422 * internal memory. 1423 */ 1424 for (i = BGE_STATS_BLOCK; 1425 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1426 BGE_MEMWIN_WRITE(sc, i, 0); 1427 1428 for (i = BGE_STATUS_BLOCK; 1429 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1430 BGE_MEMWIN_WRITE(sc, i, 0); 1431 1432 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1433 /* 1434 * Fix data corruption caused by non-qword write with WB. 1435 * Fix master abort in PCI mode. 1436 * Fix PCI latency timer. 1437 */ 1438 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1439 val |= (1 << 10) | (1 << 12) | (1 << 13); 1440 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1441 } 1442 1443 /* 1444 * Set up the PCI DMA control register. 1445 */ 1446 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1447 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1448 if (sc->bge_flags & BGE_FLAG_PCIE) { 1449 /* Read watermark not used, 128 bytes for write. */ 1450 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1451 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1452 if (BGE_IS_5714_FAMILY(sc)) { 1453 /* 256 bytes for read and write. */ 1454 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1455 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1456 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1457 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1458 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1459 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1460 /* 1461 * In the BCM5703, the DMA read watermark should 1462 * be set to less than or equal to the maximum 1463 * memory read byte count of the PCI-X command 1464 * register. 1465 */ 1466 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1467 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1468 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1469 /* 1536 bytes for read, 384 bytes for write. */ 1470 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1471 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1472 } else { 1473 /* 384 bytes for read and write. */ 1474 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1475 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1476 0x0F; 1477 } 1478 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1479 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1480 uint32_t tmp; 1481 1482 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1483 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1484 if (tmp == 6 || tmp == 7) 1485 dma_rw_ctl |= 1486 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1487 1488 /* Set PCI-X DMA write workaround. */ 1489 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1490 } 1491 } else { 1492 /* Conventional PCI bus: 256 bytes for read and write. */ 1493 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1494 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1495 1496 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1497 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1498 dma_rw_ctl |= 0x0F; 1499 } 1500 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1501 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1502 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1503 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1504 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1505 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1506 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1507 if (BGE_IS_5717_PLUS(sc)) { 1508 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1509 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1510 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1511 /* 1512 * Enable HW workaround for controllers that misinterpret 1513 * a status tag update and leave interrupts permanently 1514 * disabled. 1515 */ 1516 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1517 sc->bge_asicrev != BGE_ASICREV_BCM57765) 1518 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1519 } 1520 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1521 1522 /* 1523 * Set up general mode register. 1524 */ 1525 mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR | 1526 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; 1527 1528 /* 1529 * BCM5701 B5 have a bug causing data corruption when using 1530 * 64-bit DMA reads, which can be terminated early and then 1531 * completed later as 32-bit accesses, in combination with 1532 * certain bridges. 1533 */ 1534 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1535 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1536 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1537 1538 /* 1539 * Tell the firmware the driver is running 1540 */ 1541 if (sc->bge_asf_mode & ASF_STACKUP) 1542 mode_ctl |= BGE_MODECTL_STACKUP; 1543 1544 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1545 1546 /* 1547 * Disable memory write invalidate. Apparently it is not supported 1548 * properly by these devices. Also ensure that INTx isn't disabled, 1549 * as these chips need it even when using MSI. 1550 */ 1551 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1552 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1553 1554 /* Set the timer prescaler (always 66Mhz) */ 1555 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1556 1557 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1558 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1559 DELAY(40); /* XXX */ 1560 1561 /* Put PHY into ready state */ 1562 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1563 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1564 DELAY(40); 1565 } 1566 1567 return (0); 1568 } 1569 1570 static int 1571 bge_blockinit(struct bge_softc *sc) 1572 { 1573 struct bge_rcb *rcb; 1574 bus_size_t vrcb; 1575 bge_hostaddr taddr; 1576 uint32_t dmactl, val; 1577 int i, limit; 1578 1579 /* 1580 * Initialize the memory window pointer register so that 1581 * we can access the first 32K of internal NIC RAM. This will 1582 * allow us to set up the TX send ring RCBs and the RX return 1583 * ring RCBs, plus other things which live in NIC memory. 1584 */ 1585 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1586 1587 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1588 1589 if (!(BGE_IS_5705_PLUS(sc))) { 1590 /* Configure mbuf memory pool */ 1591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1592 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1593 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1594 else 1595 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1596 1597 /* Configure DMA resource pool */ 1598 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1599 BGE_DMA_DESCRIPTORS); 1600 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1601 } 1602 1603 /* Configure mbuf pool watermarks */ 1604 if (BGE_IS_5717_PLUS(sc)) { 1605 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1606 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1607 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1608 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1609 } else { 1610 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1611 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1612 } 1613 } else if (!BGE_IS_5705_PLUS(sc)) { 1614 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1615 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1616 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1617 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1618 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1619 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1620 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1621 } else { 1622 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1623 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1624 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1625 } 1626 1627 /* Configure DMA resource watermarks */ 1628 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1629 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1630 1631 /* Enable buffer manager */ 1632 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1633 /* 1634 * Change the arbitration algorithm of TXMBUF read request to 1635 * round-robin instead of priority based for BCM5719. When 1636 * TXFIFO is almost empty, RDMA will hold its request until 1637 * TXFIFO is not almost empty. 1638 */ 1639 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 1640 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1641 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1642 1643 /* Poll for buffer manager start indication */ 1644 for (i = 0; i < BGE_TIMEOUT; i++) { 1645 DELAY(10); 1646 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1647 break; 1648 } 1649 1650 if (i == BGE_TIMEOUT) { 1651 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 1652 return (ENXIO); 1653 } 1654 1655 /* Enable flow-through queues */ 1656 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1657 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1658 1659 /* Wait until queue initialization is complete */ 1660 for (i = 0; i < BGE_TIMEOUT; i++) { 1661 DELAY(10); 1662 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1663 break; 1664 } 1665 1666 if (i == BGE_TIMEOUT) { 1667 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1668 return (ENXIO); 1669 } 1670 1671 /* 1672 * Summary of rings supported by the controller: 1673 * 1674 * Standard Receive Producer Ring 1675 * - This ring is used to feed receive buffers for "standard" 1676 * sized frames (typically 1536 bytes) to the controller. 1677 * 1678 * Jumbo Receive Producer Ring 1679 * - This ring is used to feed receive buffers for jumbo sized 1680 * frames (i.e. anything bigger than the "standard" frames) 1681 * to the controller. 1682 * 1683 * Mini Receive Producer Ring 1684 * - This ring is used to feed receive buffers for "mini" 1685 * sized frames to the controller. 1686 * - This feature required external memory for the controller 1687 * but was never used in a production system. Should always 1688 * be disabled. 1689 * 1690 * Receive Return Ring 1691 * - After the controller has placed an incoming frame into a 1692 * receive buffer that buffer is moved into a receive return 1693 * ring. The driver is then responsible to passing the 1694 * buffer up to the stack. Many versions of the controller 1695 * support multiple RR rings. 1696 * 1697 * Send Ring 1698 * - This ring is used for outgoing frames. Many versions of 1699 * the controller support multiple send rings. 1700 */ 1701 1702 /* Initialize the standard receive producer ring control block. */ 1703 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1704 rcb->bge_hostaddr.bge_addr_lo = 1705 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1706 rcb->bge_hostaddr.bge_addr_hi = 1707 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1708 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1709 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1710 if (BGE_IS_5717_PLUS(sc)) { 1711 /* 1712 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1713 * Bits 15-2 : Maximum RX frame size 1714 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1715 * Bit 0 : Reserved 1716 */ 1717 rcb->bge_maxlen_flags = 1718 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 1719 } else if (BGE_IS_5705_PLUS(sc)) { 1720 /* 1721 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1722 * Bits 15-2 : Reserved (should be 0) 1723 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1724 * Bit 0 : Reserved 1725 */ 1726 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1727 } else { 1728 /* 1729 * Ring size is always XXX entries 1730 * Bits 31-16: Maximum RX frame size 1731 * Bits 15-2 : Reserved (should be 0) 1732 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1733 * Bit 0 : Reserved 1734 */ 1735 rcb->bge_maxlen_flags = 1736 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1737 } 1738 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1739 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1740 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1741 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1742 else 1743 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1744 /* Write the standard receive producer ring control block. */ 1745 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1746 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1747 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1748 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1749 1750 /* Reset the standard receive producer ring producer index. */ 1751 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1752 1753 /* 1754 * Initialize the jumbo RX producer ring control 1755 * block. We set the 'ring disabled' bit in the 1756 * flags field until we're actually ready to start 1757 * using this ring (i.e. once we set the MTU 1758 * high enough to require it). 1759 */ 1760 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1761 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1762 /* Get the jumbo receive producer ring RCB parameters. */ 1763 rcb->bge_hostaddr.bge_addr_lo = 1764 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1765 rcb->bge_hostaddr.bge_addr_hi = 1766 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1767 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1768 sc->bge_cdata.bge_rx_jumbo_ring_map, 1769 BUS_DMASYNC_PREREAD); 1770 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1771 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1772 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1773 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1774 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1775 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1776 else 1777 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1778 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1779 rcb->bge_hostaddr.bge_addr_hi); 1780 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1781 rcb->bge_hostaddr.bge_addr_lo); 1782 /* Program the jumbo receive producer ring RCB parameters. */ 1783 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1784 rcb->bge_maxlen_flags); 1785 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1786 /* Reset the jumbo receive producer ring producer index. */ 1787 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1788 } 1789 1790 /* Disable the mini receive producer ring RCB. */ 1791 if (BGE_IS_5700_FAMILY(sc)) { 1792 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1793 rcb->bge_maxlen_flags = 1794 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1795 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1796 rcb->bge_maxlen_flags); 1797 /* Reset the mini receive producer ring producer index. */ 1798 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1799 } 1800 1801 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1802 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1803 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1804 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1805 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 1806 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1807 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1808 } 1809 /* 1810 * The BD ring replenish thresholds control how often the 1811 * hardware fetches new BD's from the producer rings in host 1812 * memory. Setting the value too low on a busy system can 1813 * starve the hardware and recue the throughpout. 1814 * 1815 * Set the BD ring replentish thresholds. The recommended 1816 * values are 1/8th the number of descriptors allocated to 1817 * each ring. 1818 * XXX The 5754 requires a lower threshold, so it might be a 1819 * requirement of all 575x family chips. The Linux driver sets 1820 * the lower threshold for all 5705 family chips as well, but there 1821 * are reports that it might not need to be so strict. 1822 * 1823 * XXX Linux does some extra fiddling here for the 5906 parts as 1824 * well. 1825 */ 1826 if (BGE_IS_5705_PLUS(sc)) 1827 val = 8; 1828 else 1829 val = BGE_STD_RX_RING_CNT / 8; 1830 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1831 if (BGE_IS_JUMBO_CAPABLE(sc)) 1832 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1833 BGE_JUMBO_RX_RING_CNT/8); 1834 if (BGE_IS_5717_PLUS(sc)) { 1835 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1836 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1837 } 1838 1839 /* 1840 * Disable all send rings by setting the 'ring disabled' bit 1841 * in the flags field of all the TX send ring control blocks, 1842 * located in NIC memory. 1843 */ 1844 if (!BGE_IS_5705_PLUS(sc)) 1845 /* 5700 to 5704 had 16 send rings. */ 1846 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1847 else 1848 limit = 1; 1849 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1850 for (i = 0; i < limit; i++) { 1851 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1852 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1853 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1854 vrcb += sizeof(struct bge_rcb); 1855 } 1856 1857 /* Configure send ring RCB 0 (we use only the first ring) */ 1858 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1859 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1860 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1861 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1863 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1864 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1865 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 1866 else 1867 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1868 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1869 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1870 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1871 1872 /* 1873 * Disable all receive return rings by setting the 1874 * 'ring diabled' bit in the flags field of all the receive 1875 * return ring control blocks, located in NIC memory. 1876 */ 1877 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1878 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1879 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 1880 /* Should be 17, use 16 until we get an SRAM map. */ 1881 limit = 16; 1882 } else if (!BGE_IS_5705_PLUS(sc)) 1883 limit = BGE_RX_RINGS_MAX; 1884 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1885 sc->bge_asicrev == BGE_ASICREV_BCM57765) 1886 limit = 4; 1887 else 1888 limit = 1; 1889 /* Disable all receive return rings. */ 1890 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1891 for (i = 0; i < limit; i++) { 1892 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1893 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1894 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1895 BGE_RCB_FLAG_RING_DISABLED); 1896 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1897 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1898 (i * (sizeof(uint64_t))), 0); 1899 vrcb += sizeof(struct bge_rcb); 1900 } 1901 1902 /* 1903 * Set up receive return ring 0. Note that the NIC address 1904 * for RX return rings is 0x0. The return rings live entirely 1905 * within the host, so the nicaddr field in the RCB isn't used. 1906 */ 1907 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1908 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1909 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1910 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1911 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1912 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1913 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1914 1915 /* Set random backoff seed for TX */ 1916 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1917 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1918 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1919 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1920 BGE_TX_BACKOFF_SEED_MASK); 1921 1922 /* Set inter-packet gap */ 1923 val = 0x2620; 1924 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 1925 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 1926 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 1927 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 1928 1929 /* 1930 * Specify which ring to use for packets that don't match 1931 * any RX rules. 1932 */ 1933 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1934 1935 /* 1936 * Configure number of RX lists. One interrupt distribution 1937 * list, sixteen active lists, one bad frames class. 1938 */ 1939 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1940 1941 /* Inialize RX list placement stats mask. */ 1942 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1943 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1944 1945 /* Disable host coalescing until we get it set up */ 1946 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1947 1948 /* Poll to make sure it's shut down. */ 1949 for (i = 0; i < BGE_TIMEOUT; i++) { 1950 DELAY(10); 1951 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1952 break; 1953 } 1954 1955 if (i == BGE_TIMEOUT) { 1956 device_printf(sc->bge_dev, 1957 "host coalescing engine failed to idle\n"); 1958 return (ENXIO); 1959 } 1960 1961 /* Set up host coalescing defaults */ 1962 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1963 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1964 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1965 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1966 if (!(BGE_IS_5705_PLUS(sc))) { 1967 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1968 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1969 } 1970 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1971 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1972 1973 /* Set up address of statistics block */ 1974 if (!(BGE_IS_5705_PLUS(sc))) { 1975 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1976 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1977 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1978 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1979 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1980 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1981 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1982 } 1983 1984 /* Set up address of status block */ 1985 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1986 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1987 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1988 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1989 1990 /* Set up status block size. */ 1991 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1992 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1993 val = BGE_STATBLKSZ_FULL; 1994 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1995 } else { 1996 val = BGE_STATBLKSZ_32BYTE; 1997 bzero(sc->bge_ldata.bge_status_block, 32); 1998 } 1999 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2000 sc->bge_cdata.bge_status_map, 2001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2002 2003 /* Turn on host coalescing state machine */ 2004 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2005 2006 /* Turn on RX BD completion state machine and enable attentions */ 2007 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2008 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2009 2010 /* Turn on RX list placement state machine */ 2011 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2012 2013 /* Turn on RX list selector state machine. */ 2014 if (!(BGE_IS_5705_PLUS(sc))) 2015 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2016 2017 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2018 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2019 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2020 BGE_MACMODE_FRMHDR_DMA_ENB; 2021 2022 if (sc->bge_flags & BGE_FLAG_TBI) 2023 val |= BGE_PORTMODE_TBI; 2024 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2025 val |= BGE_PORTMODE_GMII; 2026 else 2027 val |= BGE_PORTMODE_MII; 2028 2029 /* Turn on DMA, clear stats */ 2030 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2031 2032 /* Set misc. local control, enable interrupts on attentions */ 2033 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2034 2035 #ifdef notdef 2036 /* Assert GPIO pins for PHY reset */ 2037 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2038 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2039 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2040 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2041 #endif 2042 2043 /* Turn on DMA completion state machine */ 2044 if (!(BGE_IS_5705_PLUS(sc))) 2045 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2046 2047 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2048 2049 /* Enable host coalescing bug fix. */ 2050 if (BGE_IS_5755_PLUS(sc)) 2051 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2052 2053 /* Request larger DMA burst size to get better performance. */ 2054 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2055 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2056 2057 /* Turn on write DMA state machine */ 2058 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2059 DELAY(40); 2060 2061 /* Turn on read DMA state machine */ 2062 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2063 2064 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2065 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2066 2067 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2068 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2069 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2070 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2071 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2072 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2073 if (sc->bge_flags & BGE_FLAG_PCIE) 2074 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2075 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2076 val |= BGE_RDMAMODE_TSO4_ENABLE; 2077 if (sc->bge_flags & BGE_FLAG_TSO3 || 2078 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2079 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2080 val |= BGE_RDMAMODE_TSO6_ENABLE; 2081 } 2082 2083 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 2084 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2085 BGE_RDMAMODE_H2BNC_VLAN_DET; 2086 2087 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2088 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2089 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2090 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2091 BGE_IS_5717_PLUS(sc)) { 2092 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2093 /* 2094 * Adjust tx margin to prevent TX data corruption and 2095 * fix internal FIFO overflow. 2096 */ 2097 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2098 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2099 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2100 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2101 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2102 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2103 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2104 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2105 } 2106 /* 2107 * Enable fix for read DMA FIFO overruns. 2108 * The fix is to limit the number of RX BDs 2109 * the hardware would fetch at a fime. 2110 */ 2111 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2112 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2113 } 2114 2115 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2116 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2117 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2118 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2119 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2120 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2121 } 2122 2123 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2124 DELAY(40); 2125 2126 /* Turn on RX data completion state machine */ 2127 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2128 2129 /* Turn on RX BD initiator state machine */ 2130 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2131 2132 /* Turn on RX data and RX BD initiator state machine */ 2133 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2134 2135 /* Turn on Mbuf cluster free state machine */ 2136 if (!(BGE_IS_5705_PLUS(sc))) 2137 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2138 2139 /* Turn on send BD completion state machine */ 2140 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2141 2142 /* Turn on send data completion state machine */ 2143 val = BGE_SDCMODE_ENABLE; 2144 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2145 val |= BGE_SDCMODE_CDELAY; 2146 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2147 2148 /* Turn on send data initiator state machine */ 2149 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2150 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2151 BGE_SDIMODE_HW_LSO_PRE_DMA); 2152 else 2153 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2154 2155 /* Turn on send BD initiator state machine */ 2156 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2157 2158 /* Turn on send BD selector state machine */ 2159 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2160 2161 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2162 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2163 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2164 2165 /* ack/clear link change events */ 2166 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2167 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2168 BGE_MACSTAT_LINK_CHANGED); 2169 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2170 2171 /* 2172 * Enable attention when the link has changed state for 2173 * devices that use auto polling. 2174 */ 2175 if (sc->bge_flags & BGE_FLAG_TBI) { 2176 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2177 } else { 2178 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2179 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2180 DELAY(80); 2181 } 2182 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2183 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2184 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2185 BGE_EVTENB_MI_INTERRUPT); 2186 } 2187 2188 /* 2189 * Clear any pending link state attention. 2190 * Otherwise some link state change events may be lost until attention 2191 * is cleared by bge_intr() -> bge_link_upd() sequence. 2192 * It's not necessary on newer BCM chips - perhaps enabling link 2193 * state change attentions implies clearing pending attention. 2194 */ 2195 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2196 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2197 BGE_MACSTAT_LINK_CHANGED); 2198 2199 /* Enable link state change attentions. */ 2200 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2201 2202 return (0); 2203 } 2204 2205 const struct bge_revision * 2206 bge_lookup_rev(uint32_t chipid) 2207 { 2208 const struct bge_revision *br; 2209 2210 for (br = bge_revisions; br->br_name != NULL; br++) { 2211 if (br->br_chipid == chipid) 2212 return (br); 2213 } 2214 2215 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2216 if (br->br_chipid == BGE_ASICREV(chipid)) 2217 return (br); 2218 } 2219 2220 return (NULL); 2221 } 2222 2223 const struct bge_vendor * 2224 bge_lookup_vendor(uint16_t vid) 2225 { 2226 const struct bge_vendor *v; 2227 2228 for (v = bge_vendors; v->v_name != NULL; v++) 2229 if (v->v_id == vid) 2230 return (v); 2231 2232 panic("%s: unknown vendor %d", __func__, vid); 2233 return (NULL); 2234 } 2235 2236 /* 2237 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2238 * against our list and return its name if we find a match. 2239 * 2240 * Note that since the Broadcom controller contains VPD support, we 2241 * try to get the device name string from the controller itself instead 2242 * of the compiled-in string. It guarantees we'll always announce the 2243 * right product name. We fall back to the compiled-in string when 2244 * VPD is unavailable or corrupt. 2245 */ 2246 static int 2247 bge_probe(device_t dev) 2248 { 2249 char buf[96]; 2250 char model[64]; 2251 const struct bge_revision *br; 2252 const char *pname; 2253 struct bge_softc *sc = device_get_softc(dev); 2254 const struct bge_type *t = bge_devs; 2255 const struct bge_vendor *v; 2256 uint32_t id; 2257 uint16_t did, vid; 2258 2259 sc->bge_dev = dev; 2260 vid = pci_get_vendor(dev); 2261 did = pci_get_device(dev); 2262 while(t->bge_vid != 0) { 2263 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2264 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2265 BGE_PCIMISCCTL_ASICREV_SHIFT; 2266 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2267 /* 2268 * Find the ASCI revision. Different chips 2269 * use different registers. 2270 */ 2271 switch (pci_get_device(dev)) { 2272 case BCOM_DEVICEID_BCM5717: 2273 case BCOM_DEVICEID_BCM5718: 2274 case BCOM_DEVICEID_BCM5719: 2275 case BCOM_DEVICEID_BCM5720: 2276 id = pci_read_config(dev, 2277 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2278 break; 2279 case BCOM_DEVICEID_BCM57761: 2280 case BCOM_DEVICEID_BCM57765: 2281 case BCOM_DEVICEID_BCM57781: 2282 case BCOM_DEVICEID_BCM57785: 2283 case BCOM_DEVICEID_BCM57791: 2284 case BCOM_DEVICEID_BCM57795: 2285 id = pci_read_config(dev, 2286 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2287 break; 2288 default: 2289 id = pci_read_config(dev, 2290 BGE_PCI_PRODID_ASICREV, 4); 2291 } 2292 } 2293 br = bge_lookup_rev(id); 2294 v = bge_lookup_vendor(vid); 2295 if (bge_has_eaddr(sc) && 2296 pci_get_vpd_ident(dev, &pname) == 0) 2297 snprintf(model, 64, "%s", pname); 2298 else 2299 snprintf(model, 64, "%s %s", v->v_name, 2300 br != NULL ? br->br_name : 2301 "NetXtreme Ethernet Controller"); 2302 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2303 br != NULL ? "" : "unknown ", id); 2304 device_set_desc_copy(dev, buf); 2305 return (0); 2306 } 2307 t++; 2308 } 2309 2310 return (ENXIO); 2311 } 2312 2313 static void 2314 bge_dma_free(struct bge_softc *sc) 2315 { 2316 int i; 2317 2318 /* Destroy DMA maps for RX buffers. */ 2319 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2320 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2321 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2322 sc->bge_cdata.bge_rx_std_dmamap[i]); 2323 } 2324 if (sc->bge_cdata.bge_rx_std_sparemap) 2325 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2326 sc->bge_cdata.bge_rx_std_sparemap); 2327 2328 /* Destroy DMA maps for jumbo RX buffers. */ 2329 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2330 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2331 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2332 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2333 } 2334 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2335 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2336 sc->bge_cdata.bge_rx_jumbo_sparemap); 2337 2338 /* Destroy DMA maps for TX buffers. */ 2339 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2340 if (sc->bge_cdata.bge_tx_dmamap[i]) 2341 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2342 sc->bge_cdata.bge_tx_dmamap[i]); 2343 } 2344 2345 if (sc->bge_cdata.bge_rx_mtag) 2346 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2347 if (sc->bge_cdata.bge_tx_mtag) 2348 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2349 2350 2351 /* Destroy standard RX ring. */ 2352 if (sc->bge_cdata.bge_rx_std_ring_map) 2353 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2354 sc->bge_cdata.bge_rx_std_ring_map); 2355 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2356 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2357 sc->bge_ldata.bge_rx_std_ring, 2358 sc->bge_cdata.bge_rx_std_ring_map); 2359 2360 if (sc->bge_cdata.bge_rx_std_ring_tag) 2361 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2362 2363 /* Destroy jumbo RX ring. */ 2364 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2365 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2366 sc->bge_cdata.bge_rx_jumbo_ring_map); 2367 2368 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2369 sc->bge_ldata.bge_rx_jumbo_ring) 2370 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2371 sc->bge_ldata.bge_rx_jumbo_ring, 2372 sc->bge_cdata.bge_rx_jumbo_ring_map); 2373 2374 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2375 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2376 2377 /* Destroy RX return ring. */ 2378 if (sc->bge_cdata.bge_rx_return_ring_map) 2379 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2380 sc->bge_cdata.bge_rx_return_ring_map); 2381 2382 if (sc->bge_cdata.bge_rx_return_ring_map && 2383 sc->bge_ldata.bge_rx_return_ring) 2384 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2385 sc->bge_ldata.bge_rx_return_ring, 2386 sc->bge_cdata.bge_rx_return_ring_map); 2387 2388 if (sc->bge_cdata.bge_rx_return_ring_tag) 2389 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2390 2391 /* Destroy TX ring. */ 2392 if (sc->bge_cdata.bge_tx_ring_map) 2393 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2394 sc->bge_cdata.bge_tx_ring_map); 2395 2396 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2397 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2398 sc->bge_ldata.bge_tx_ring, 2399 sc->bge_cdata.bge_tx_ring_map); 2400 2401 if (sc->bge_cdata.bge_tx_ring_tag) 2402 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2403 2404 /* Destroy status block. */ 2405 if (sc->bge_cdata.bge_status_map) 2406 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2407 sc->bge_cdata.bge_status_map); 2408 2409 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2410 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2411 sc->bge_ldata.bge_status_block, 2412 sc->bge_cdata.bge_status_map); 2413 2414 if (sc->bge_cdata.bge_status_tag) 2415 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2416 2417 /* Destroy statistics block. */ 2418 if (sc->bge_cdata.bge_stats_map) 2419 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2420 sc->bge_cdata.bge_stats_map); 2421 2422 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2423 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2424 sc->bge_ldata.bge_stats, 2425 sc->bge_cdata.bge_stats_map); 2426 2427 if (sc->bge_cdata.bge_stats_tag) 2428 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2429 2430 if (sc->bge_cdata.bge_buffer_tag) 2431 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2432 2433 /* Destroy the parent tag. */ 2434 if (sc->bge_cdata.bge_parent_tag) 2435 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2436 } 2437 2438 static int 2439 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2440 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2441 bus_addr_t *paddr, const char *msg) 2442 { 2443 struct bge_dmamap_arg ctx; 2444 bus_addr_t lowaddr; 2445 bus_size_t ring_end; 2446 int error; 2447 2448 lowaddr = BUS_SPACE_MAXADDR; 2449 again: 2450 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2451 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2452 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2453 if (error != 0) { 2454 device_printf(sc->bge_dev, 2455 "could not create %s dma tag\n", msg); 2456 return (ENOMEM); 2457 } 2458 /* Allocate DMA'able memory for ring. */ 2459 error = bus_dmamem_alloc(*tag, (void **)ring, 2460 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2461 if (error != 0) { 2462 device_printf(sc->bge_dev, 2463 "could not allocate DMA'able memory for %s\n", msg); 2464 return (ENOMEM); 2465 } 2466 /* Load the address of the ring. */ 2467 ctx.bge_busaddr = 0; 2468 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2469 &ctx, BUS_DMA_NOWAIT); 2470 if (error != 0) { 2471 device_printf(sc->bge_dev, 2472 "could not load DMA'able memory for %s\n", msg); 2473 return (ENOMEM); 2474 } 2475 *paddr = ctx.bge_busaddr; 2476 ring_end = *paddr + maxsize; 2477 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2478 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2479 /* 2480 * 4GB boundary crossed. Limit maximum allowable DMA 2481 * address space to 32bit and try again. 2482 */ 2483 bus_dmamap_unload(*tag, *map); 2484 bus_dmamem_free(*tag, *ring, *map); 2485 bus_dma_tag_destroy(*tag); 2486 if (bootverbose) 2487 device_printf(sc->bge_dev, "4GB boundary crossed, " 2488 "limit DMA address space to 32bit for %s\n", msg); 2489 *ring = NULL; 2490 *tag = NULL; 2491 *map = NULL; 2492 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2493 goto again; 2494 } 2495 return (0); 2496 } 2497 2498 static int 2499 bge_dma_alloc(struct bge_softc *sc) 2500 { 2501 bus_addr_t lowaddr; 2502 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2503 int i, error; 2504 2505 lowaddr = BUS_SPACE_MAXADDR; 2506 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2507 lowaddr = BGE_DMA_MAXADDR; 2508 /* 2509 * Allocate the parent bus DMA tag appropriate for PCI. 2510 */ 2511 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2512 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2513 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2514 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2515 if (error != 0) { 2516 device_printf(sc->bge_dev, 2517 "could not allocate parent dma tag\n"); 2518 return (ENOMEM); 2519 } 2520 2521 /* Create tag for standard RX ring. */ 2522 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2523 &sc->bge_cdata.bge_rx_std_ring_tag, 2524 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2525 &sc->bge_cdata.bge_rx_std_ring_map, 2526 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2527 if (error) 2528 return (error); 2529 2530 /* Create tag for RX return ring. */ 2531 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2532 &sc->bge_cdata.bge_rx_return_ring_tag, 2533 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2534 &sc->bge_cdata.bge_rx_return_ring_map, 2535 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2536 if (error) 2537 return (error); 2538 2539 /* Create tag for TX ring. */ 2540 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2541 &sc->bge_cdata.bge_tx_ring_tag, 2542 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2543 &sc->bge_cdata.bge_tx_ring_map, 2544 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2545 if (error) 2546 return (error); 2547 2548 /* 2549 * Create tag for status block. 2550 * Because we only use single Tx/Rx/Rx return ring, use 2551 * minimum status block size except BCM5700 AX/BX which 2552 * seems to want to see full status block size regardless 2553 * of configured number of ring. 2554 */ 2555 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2556 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2557 sbsz = BGE_STATUS_BLK_SZ; 2558 else 2559 sbsz = 32; 2560 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2561 &sc->bge_cdata.bge_status_tag, 2562 (uint8_t **)&sc->bge_ldata.bge_status_block, 2563 &sc->bge_cdata.bge_status_map, 2564 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2565 if (error) 2566 return (error); 2567 2568 /* Create tag for statistics block. */ 2569 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2570 &sc->bge_cdata.bge_stats_tag, 2571 (uint8_t **)&sc->bge_ldata.bge_stats, 2572 &sc->bge_cdata.bge_stats_map, 2573 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2574 if (error) 2575 return (error); 2576 2577 /* Create tag for jumbo RX ring. */ 2578 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2579 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2580 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2581 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2582 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2583 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2584 if (error) 2585 return (error); 2586 } 2587 2588 /* Create parent tag for buffers. */ 2589 boundary = 0; 2590 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2591 boundary = BGE_DMA_BNDRY; 2592 /* 2593 * XXX 2594 * watchdog timeout issue was observed on BCM5704 which 2595 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2596 * Limiting DMA address space to 32bits seems to address 2597 * it. 2598 */ 2599 if (sc->bge_flags & BGE_FLAG_PCIX) 2600 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2601 } 2602 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2603 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 2604 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2605 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 2606 if (error != 0) { 2607 device_printf(sc->bge_dev, 2608 "could not allocate buffer dma tag\n"); 2609 return (ENOMEM); 2610 } 2611 /* Create tag for Tx mbufs. */ 2612 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2613 txsegsz = BGE_TSOSEG_SZ; 2614 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2615 } else { 2616 txsegsz = MCLBYTES; 2617 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2618 } 2619 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2620 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2621 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2622 &sc->bge_cdata.bge_tx_mtag); 2623 2624 if (error) { 2625 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2626 return (ENOMEM); 2627 } 2628 2629 /* Create tag for Rx mbufs. */ 2630 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 2631 rxmaxsegsz = MJUM9BYTES; 2632 else 2633 rxmaxsegsz = MCLBYTES; 2634 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2635 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 2636 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2637 2638 if (error) { 2639 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2640 return (ENOMEM); 2641 } 2642 2643 /* Create DMA maps for RX buffers. */ 2644 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2645 &sc->bge_cdata.bge_rx_std_sparemap); 2646 if (error) { 2647 device_printf(sc->bge_dev, 2648 "can't create spare DMA map for RX\n"); 2649 return (ENOMEM); 2650 } 2651 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2652 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2653 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2654 if (error) { 2655 device_printf(sc->bge_dev, 2656 "can't create DMA map for RX\n"); 2657 return (ENOMEM); 2658 } 2659 } 2660 2661 /* Create DMA maps for TX buffers. */ 2662 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2663 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2664 &sc->bge_cdata.bge_tx_dmamap[i]); 2665 if (error) { 2666 device_printf(sc->bge_dev, 2667 "can't create DMA map for TX\n"); 2668 return (ENOMEM); 2669 } 2670 } 2671 2672 /* Create tags for jumbo RX buffers. */ 2673 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2674 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2675 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2676 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2677 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2678 if (error) { 2679 device_printf(sc->bge_dev, 2680 "could not allocate jumbo dma tag\n"); 2681 return (ENOMEM); 2682 } 2683 /* Create DMA maps for jumbo RX buffers. */ 2684 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2685 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2686 if (error) { 2687 device_printf(sc->bge_dev, 2688 "can't create spare DMA map for jumbo RX\n"); 2689 return (ENOMEM); 2690 } 2691 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2692 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2693 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2694 if (error) { 2695 device_printf(sc->bge_dev, 2696 "can't create DMA map for jumbo RX\n"); 2697 return (ENOMEM); 2698 } 2699 } 2700 } 2701 2702 return (0); 2703 } 2704 2705 /* 2706 * Return true if this device has more than one port. 2707 */ 2708 static int 2709 bge_has_multiple_ports(struct bge_softc *sc) 2710 { 2711 device_t dev = sc->bge_dev; 2712 u_int b, d, f, fscan, s; 2713 2714 d = pci_get_domain(dev); 2715 b = pci_get_bus(dev); 2716 s = pci_get_slot(dev); 2717 f = pci_get_function(dev); 2718 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2719 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2720 return (1); 2721 return (0); 2722 } 2723 2724 /* 2725 * Return true if MSI can be used with this device. 2726 */ 2727 static int 2728 bge_can_use_msi(struct bge_softc *sc) 2729 { 2730 int can_use_msi = 0; 2731 2732 /* Disable MSI for polling(4). */ 2733 #ifdef DEVICE_POLLING 2734 return (0); 2735 #endif 2736 switch (sc->bge_asicrev) { 2737 case BGE_ASICREV_BCM5714_A0: 2738 case BGE_ASICREV_BCM5714: 2739 /* 2740 * Apparently, MSI doesn't work when these chips are 2741 * configured in single-port mode. 2742 */ 2743 if (bge_has_multiple_ports(sc)) 2744 can_use_msi = 1; 2745 break; 2746 case BGE_ASICREV_BCM5750: 2747 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2748 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2749 can_use_msi = 1; 2750 break; 2751 default: 2752 if (BGE_IS_575X_PLUS(sc)) 2753 can_use_msi = 1; 2754 } 2755 return (can_use_msi); 2756 } 2757 2758 static int 2759 bge_attach(device_t dev) 2760 { 2761 struct ifnet *ifp; 2762 struct bge_softc *sc; 2763 uint32_t hwcfg = 0, misccfg; 2764 u_char eaddr[ETHER_ADDR_LEN]; 2765 int capmask, error, f, msicount, phy_addr, reg, rid, trys; 2766 2767 sc = device_get_softc(dev); 2768 sc->bge_dev = dev; 2769 2770 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2771 2772 /* 2773 * Map control/status registers. 2774 */ 2775 pci_enable_busmaster(dev); 2776 2777 rid = PCIR_BAR(0); 2778 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2779 RF_ACTIVE); 2780 2781 if (sc->bge_res == NULL) { 2782 device_printf (sc->bge_dev, "couldn't map memory\n"); 2783 error = ENXIO; 2784 goto fail; 2785 } 2786 2787 /* Save various chip information. */ 2788 sc->bge_chipid = 2789 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2790 BGE_PCIMISCCTL_ASICREV_SHIFT; 2791 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2792 /* 2793 * Find the ASCI revision. Different chips use different 2794 * registers. 2795 */ 2796 switch (pci_get_device(dev)) { 2797 case BCOM_DEVICEID_BCM5717: 2798 case BCOM_DEVICEID_BCM5718: 2799 case BCOM_DEVICEID_BCM5719: 2800 case BCOM_DEVICEID_BCM5720: 2801 sc->bge_chipid = pci_read_config(dev, 2802 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2803 break; 2804 case BCOM_DEVICEID_BCM57761: 2805 case BCOM_DEVICEID_BCM57765: 2806 case BCOM_DEVICEID_BCM57781: 2807 case BCOM_DEVICEID_BCM57785: 2808 case BCOM_DEVICEID_BCM57791: 2809 case BCOM_DEVICEID_BCM57795: 2810 sc->bge_chipid = pci_read_config(dev, 2811 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2812 break; 2813 default: 2814 sc->bge_chipid = pci_read_config(dev, 2815 BGE_PCI_PRODID_ASICREV, 4); 2816 } 2817 } 2818 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2819 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2820 2821 /* Set default PHY address. */ 2822 phy_addr = 1; 2823 /* 2824 * PHY address mapping for various devices. 2825 * 2826 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2827 * ---------+-------+-------+-------+-------+ 2828 * BCM57XX | 1 | X | X | X | 2829 * BCM5704 | 1 | X | 1 | X | 2830 * BCM5717 | 1 | 8 | 2 | 9 | 2831 * BCM5719 | 1 | 8 | 2 | 9 | 2832 * BCM5720 | 1 | 8 | 2 | 9 | 2833 * 2834 * Other addresses may respond but they are not 2835 * IEEE compliant PHYs and should be ignored. 2836 */ 2837 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2838 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2839 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2840 f = pci_get_function(dev); 2841 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2842 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2843 BGE_SGDIGSTS_IS_SERDES) 2844 phy_addr = f + 8; 2845 else 2846 phy_addr = f + 1; 2847 } else { 2848 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2849 BGE_CPMU_PHY_STRAP_IS_SERDES) 2850 phy_addr = f + 8; 2851 else 2852 phy_addr = f + 1; 2853 } 2854 } 2855 2856 /* 2857 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2858 * 5705 A0 and A1 chips. 2859 */ 2860 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2861 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2862 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2863 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2864 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2865 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 2866 2867 if (bge_has_eaddr(sc)) 2868 sc->bge_flags |= BGE_FLAG_EADDR; 2869 2870 /* Save chipset family. */ 2871 switch (sc->bge_asicrev) { 2872 case BGE_ASICREV_BCM5717: 2873 case BGE_ASICREV_BCM5719: 2874 case BGE_ASICREV_BCM5720: 2875 case BGE_ASICREV_BCM57765: 2876 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 2877 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 2878 BGE_FLAG_JUMBO_FRAME; 2879 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 2880 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2881 /* Jumbo frame on BCM5719 A0 does not work. */ 2882 sc->bge_flags &= ~BGE_FLAG_JUMBO; 2883 } 2884 break; 2885 case BGE_ASICREV_BCM5755: 2886 case BGE_ASICREV_BCM5761: 2887 case BGE_ASICREV_BCM5784: 2888 case BGE_ASICREV_BCM5785: 2889 case BGE_ASICREV_BCM5787: 2890 case BGE_ASICREV_BCM57780: 2891 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2892 BGE_FLAG_5705_PLUS; 2893 break; 2894 case BGE_ASICREV_BCM5700: 2895 case BGE_ASICREV_BCM5701: 2896 case BGE_ASICREV_BCM5703: 2897 case BGE_ASICREV_BCM5704: 2898 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2899 break; 2900 case BGE_ASICREV_BCM5714_A0: 2901 case BGE_ASICREV_BCM5780: 2902 case BGE_ASICREV_BCM5714: 2903 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 2904 /* FALLTHROUGH */ 2905 case BGE_ASICREV_BCM5750: 2906 case BGE_ASICREV_BCM5752: 2907 case BGE_ASICREV_BCM5906: 2908 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2909 /* FALLTHROUGH */ 2910 case BGE_ASICREV_BCM5705: 2911 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2912 break; 2913 } 2914 2915 /* Set various PHY bug flags. */ 2916 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2917 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2918 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 2919 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2920 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2921 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 2922 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2923 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 2924 if (pci_get_subvendor(dev) == DELL_VENDORID) 2925 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 2926 if ((BGE_IS_5705_PLUS(sc)) && 2927 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2928 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 2929 sc->bge_asicrev != BGE_ASICREV_BCM5719 && 2930 sc->bge_asicrev != BGE_ASICREV_BCM5720 && 2931 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2932 sc->bge_asicrev != BGE_ASICREV_BCM57765 && 2933 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2934 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2935 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2936 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2937 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2938 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2939 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 2940 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 2941 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 2942 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 2943 } else 2944 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 2945 } 2946 2947 /* Identify the chips that use an CPMU. */ 2948 if (BGE_IS_5717_PLUS(sc) || 2949 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2950 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2951 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2952 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2953 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 2954 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 2955 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2956 else 2957 sc->bge_mi_mode = BGE_MIMODE_BASE; 2958 /* Enable auto polling for BCM570[0-5]. */ 2959 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 2960 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2961 2962 /* 2963 * All Broadcom controllers have 4GB boundary DMA bug. 2964 * Whenever an address crosses a multiple of the 4GB boundary 2965 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2966 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2967 * state machine will lockup and cause the device to hang. 2968 */ 2969 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2970 2971 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 2972 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 2973 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 2974 2975 /* 2976 * BCM5719 cannot handle DMA requests for DMA segments that 2977 * have larger than 4KB in size. However the maximum DMA 2978 * segment size created in DMA tag is 4KB for TSO, so we 2979 * wouldn't encounter the issue here. 2980 */ 2981 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2982 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 2983 2984 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2985 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2986 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2987 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2988 sc->bge_flags |= BGE_FLAG_5788; 2989 } 2990 2991 capmask = BMSR_DEFCAPMASK; 2992 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2993 (misccfg == 0x4000 || misccfg == 0x8000)) || 2994 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2995 pci_get_vendor(dev) == BCOM_VENDORID && 2996 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 2997 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 2998 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 2999 (pci_get_vendor(dev) == BCOM_VENDORID && 3000 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3001 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3002 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3003 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3004 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3005 /* These chips are 10/100 only. */ 3006 capmask &= ~BMSR_EXTSTAT; 3007 } 3008 3009 /* 3010 * Some controllers seem to require a special firmware to use 3011 * TSO. But the firmware is not available to FreeBSD and Linux 3012 * claims that the TSO performed by the firmware is slower than 3013 * hardware based TSO. Moreover the firmware based TSO has one 3014 * known bug which can't handle TSO if ethernet header + IP/TCP 3015 * header is greater than 80 bytes. The workaround for the TSO 3016 * bug exist but it seems it's too expensive than not using 3017 * TSO at all. Some hardwares also have the TSO bug so limit 3018 * the TSO to the controllers that are not affected TSO issues 3019 * (e.g. 5755 or higher). 3020 */ 3021 if (BGE_IS_5717_PLUS(sc)) { 3022 /* BCM5717 requires different TSO configuration. */ 3023 sc->bge_flags |= BGE_FLAG_TSO3; 3024 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3025 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3026 /* TSO on BCM5719 A0 does not work. */ 3027 sc->bge_flags &= ~BGE_FLAG_TSO3; 3028 } 3029 } else if (BGE_IS_5755_PLUS(sc)) { 3030 /* 3031 * BCM5754 and BCM5787 shares the same ASIC id so 3032 * explicit device id check is required. 3033 * Due to unknown reason TSO does not work on BCM5755M. 3034 */ 3035 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3036 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3037 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3038 sc->bge_flags |= BGE_FLAG_TSO; 3039 } 3040 3041 /* 3042 * Check if this is a PCI-X or PCI Express device. 3043 */ 3044 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3045 /* 3046 * Found a PCI Express capabilities register, this 3047 * must be a PCI Express device. 3048 */ 3049 sc->bge_flags |= BGE_FLAG_PCIE; 3050 sc->bge_expcap = reg; 3051 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3052 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3053 pci_set_max_read_req(dev, 2048); 3054 else if (pci_get_max_read_req(dev) != 4096) 3055 pci_set_max_read_req(dev, 4096); 3056 } else { 3057 /* 3058 * Check if the device is in PCI-X Mode. 3059 * (This bit is not valid on PCI Express controllers.) 3060 */ 3061 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3062 sc->bge_pcixcap = reg; 3063 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3064 BGE_PCISTATE_PCI_BUSMODE) == 0) 3065 sc->bge_flags |= BGE_FLAG_PCIX; 3066 } 3067 3068 /* 3069 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3070 * not actually a MAC controller bug but an issue with the embedded 3071 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3072 */ 3073 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3074 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3075 /* 3076 * Allocate the interrupt, using MSI if possible. These devices 3077 * support 8 MSI messages, but only the first one is used in 3078 * normal operation. 3079 */ 3080 rid = 0; 3081 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3082 sc->bge_msicap = reg; 3083 if (bge_can_use_msi(sc)) { 3084 msicount = pci_msi_count(dev); 3085 if (msicount > 1) 3086 msicount = 1; 3087 } else 3088 msicount = 0; 3089 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3090 rid = 1; 3091 sc->bge_flags |= BGE_FLAG_MSI; 3092 } 3093 } 3094 3095 /* 3096 * All controllers except BCM5700 supports tagged status but 3097 * we use tagged status only for MSI case on BCM5717. Otherwise 3098 * MSI on BCM5717 does not work. 3099 */ 3100 #ifndef DEVICE_POLLING 3101 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3102 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3103 #endif 3104 3105 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3106 RF_SHAREABLE | RF_ACTIVE); 3107 3108 if (sc->bge_irq == NULL) { 3109 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3110 error = ENXIO; 3111 goto fail; 3112 } 3113 3114 device_printf(dev, 3115 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 3116 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 3117 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 3118 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 3119 3120 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3121 3122 /* Try to reset the chip. */ 3123 if (bge_reset(sc)) { 3124 device_printf(sc->bge_dev, "chip reset failed\n"); 3125 error = ENXIO; 3126 goto fail; 3127 } 3128 3129 sc->bge_asf_mode = 0; 3130 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3131 BGE_SRAM_DATA_SIG_MAGIC)) { 3132 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) 3133 & BGE_HWCFG_ASF) { 3134 sc->bge_asf_mode |= ASF_ENABLE; 3135 sc->bge_asf_mode |= ASF_STACKUP; 3136 if (BGE_IS_575X_PLUS(sc)) 3137 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3138 } 3139 } 3140 3141 /* Try to reset the chip again the nice way. */ 3142 bge_stop_fw(sc); 3143 bge_sig_pre_reset(sc, BGE_RESET_STOP); 3144 if (bge_reset(sc)) { 3145 device_printf(sc->bge_dev, "chip reset failed\n"); 3146 error = ENXIO; 3147 goto fail; 3148 } 3149 3150 bge_sig_legacy(sc, BGE_RESET_STOP); 3151 bge_sig_post_reset(sc, BGE_RESET_STOP); 3152 3153 if (bge_chipinit(sc)) { 3154 device_printf(sc->bge_dev, "chip initialization failed\n"); 3155 error = ENXIO; 3156 goto fail; 3157 } 3158 3159 error = bge_get_eaddr(sc, eaddr); 3160 if (error) { 3161 device_printf(sc->bge_dev, 3162 "failed to read station address\n"); 3163 error = ENXIO; 3164 goto fail; 3165 } 3166 3167 /* 5705 limits RX return ring to 512 entries. */ 3168 if (BGE_IS_5717_PLUS(sc)) 3169 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3170 else if (BGE_IS_5705_PLUS(sc)) 3171 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3172 else 3173 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3174 3175 if (bge_dma_alloc(sc)) { 3176 device_printf(sc->bge_dev, 3177 "failed to allocate DMA resources\n"); 3178 error = ENXIO; 3179 goto fail; 3180 } 3181 3182 bge_add_sysctls(sc); 3183 3184 /* Set default tuneable values. */ 3185 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3186 sc->bge_rx_coal_ticks = 150; 3187 sc->bge_tx_coal_ticks = 150; 3188 sc->bge_rx_max_coal_bds = 10; 3189 sc->bge_tx_max_coal_bds = 10; 3190 3191 /* Initialize checksum features to use. */ 3192 sc->bge_csum_features = BGE_CSUM_FEATURES; 3193 if (sc->bge_forced_udpcsum != 0) 3194 sc->bge_csum_features |= CSUM_UDP; 3195 3196 /* Set up ifnet structure */ 3197 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3198 if (ifp == NULL) { 3199 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3200 error = ENXIO; 3201 goto fail; 3202 } 3203 ifp->if_softc = sc; 3204 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3205 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3206 ifp->if_ioctl = bge_ioctl; 3207 ifp->if_start = bge_start; 3208 ifp->if_init = bge_init; 3209 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3210 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3211 IFQ_SET_READY(&ifp->if_snd); 3212 ifp->if_hwassist = sc->bge_csum_features; 3213 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3214 IFCAP_VLAN_MTU; 3215 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3216 ifp->if_hwassist |= CSUM_TSO; 3217 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3218 } 3219 #ifdef IFCAP_VLAN_HWCSUM 3220 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3221 #endif 3222 ifp->if_capenable = ifp->if_capabilities; 3223 #ifdef DEVICE_POLLING 3224 ifp->if_capabilities |= IFCAP_POLLING; 3225 #endif 3226 3227 /* 3228 * 5700 B0 chips do not support checksumming correctly due 3229 * to hardware bugs. 3230 */ 3231 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3232 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3233 ifp->if_capenable &= ~IFCAP_HWCSUM; 3234 ifp->if_hwassist = 0; 3235 } 3236 3237 /* 3238 * Figure out what sort of media we have by checking the 3239 * hardware config word in the first 32k of NIC internal memory, 3240 * or fall back to examining the EEPROM if necessary. 3241 * Note: on some BCM5700 cards, this value appears to be unset. 3242 * If that's the case, we have to rely on identifying the NIC 3243 * by its PCI subsystem ID, as we do below for the SysKonnect 3244 * SK-9D41. 3245 */ 3246 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3247 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3248 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3249 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3250 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3251 sizeof(hwcfg))) { 3252 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3253 error = ENXIO; 3254 goto fail; 3255 } 3256 hwcfg = ntohl(hwcfg); 3257 } 3258 3259 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3260 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3261 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3262 if (BGE_IS_5714_FAMILY(sc)) 3263 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3264 else 3265 sc->bge_flags |= BGE_FLAG_TBI; 3266 } 3267 3268 if (sc->bge_flags & BGE_FLAG_TBI) { 3269 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3270 bge_ifmedia_sts); 3271 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3272 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3273 0, NULL); 3274 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3275 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3276 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3277 } else { 3278 /* 3279 * Do transceiver setup and tell the firmware the 3280 * driver is down so we can try to get access the 3281 * probe if ASF is running. Retry a couple of times 3282 * if we get a conflict with the ASF firmware accessing 3283 * the PHY. 3284 */ 3285 trys = 0; 3286 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3287 again: 3288 bge_asf_driver_up(sc); 3289 3290 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3291 bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, 3292 MIIF_DOPAUSE); 3293 if (error != 0) { 3294 if (trys++ < 4) { 3295 device_printf(sc->bge_dev, "Try again\n"); 3296 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 3297 BMCR_RESET); 3298 goto again; 3299 } 3300 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3301 goto fail; 3302 } 3303 3304 /* 3305 * Now tell the firmware we are going up after probing the PHY 3306 */ 3307 if (sc->bge_asf_mode & ASF_STACKUP) 3308 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3309 } 3310 3311 /* 3312 * When using the BCM5701 in PCI-X mode, data corruption has 3313 * been observed in the first few bytes of some received packets. 3314 * Aligning the packet buffer in memory eliminates the corruption. 3315 * Unfortunately, this misaligns the packet payloads. On platforms 3316 * which do not support unaligned accesses, we will realign the 3317 * payloads by copying the received packets. 3318 */ 3319 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3320 sc->bge_flags & BGE_FLAG_PCIX) 3321 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3322 3323 /* 3324 * Call MI attach routine. 3325 */ 3326 ether_ifattach(ifp, eaddr); 3327 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3328 3329 /* Tell upper layer we support long frames. */ 3330 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3331 3332 /* 3333 * Hookup IRQ last. 3334 */ 3335 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3336 /* Take advantage of single-shot MSI. */ 3337 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3338 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3339 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3340 taskqueue_thread_enqueue, &sc->bge_tq); 3341 if (sc->bge_tq == NULL) { 3342 device_printf(dev, "could not create taskqueue.\n"); 3343 ether_ifdetach(ifp); 3344 error = ENXIO; 3345 goto fail; 3346 } 3347 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3348 device_get_nameunit(sc->bge_dev)); 3349 error = bus_setup_intr(dev, sc->bge_irq, 3350 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3351 &sc->bge_intrhand); 3352 if (error) 3353 ether_ifdetach(ifp); 3354 } else 3355 error = bus_setup_intr(dev, sc->bge_irq, 3356 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3357 &sc->bge_intrhand); 3358 3359 if (error) { 3360 bge_detach(dev); 3361 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3362 } 3363 3364 return (0); 3365 3366 fail: 3367 bge_release_resources(sc); 3368 3369 return (error); 3370 } 3371 3372 static int 3373 bge_detach(device_t dev) 3374 { 3375 struct bge_softc *sc; 3376 struct ifnet *ifp; 3377 3378 sc = device_get_softc(dev); 3379 ifp = sc->bge_ifp; 3380 3381 #ifdef DEVICE_POLLING 3382 if (ifp->if_capenable & IFCAP_POLLING) 3383 ether_poll_deregister(ifp); 3384 #endif 3385 3386 BGE_LOCK(sc); 3387 bge_stop(sc); 3388 bge_reset(sc); 3389 BGE_UNLOCK(sc); 3390 3391 callout_drain(&sc->bge_stat_ch); 3392 3393 if (sc->bge_tq) 3394 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3395 ether_ifdetach(ifp); 3396 3397 if (sc->bge_flags & BGE_FLAG_TBI) { 3398 ifmedia_removeall(&sc->bge_ifmedia); 3399 } else { 3400 bus_generic_detach(dev); 3401 device_delete_child(dev, sc->bge_miibus); 3402 } 3403 3404 bge_release_resources(sc); 3405 3406 return (0); 3407 } 3408 3409 static void 3410 bge_release_resources(struct bge_softc *sc) 3411 { 3412 device_t dev; 3413 3414 dev = sc->bge_dev; 3415 3416 if (sc->bge_tq != NULL) 3417 taskqueue_free(sc->bge_tq); 3418 3419 if (sc->bge_intrhand != NULL) 3420 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3421 3422 if (sc->bge_irq != NULL) 3423 bus_release_resource(dev, SYS_RES_IRQ, 3424 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3425 3426 if (sc->bge_flags & BGE_FLAG_MSI) 3427 pci_release_msi(dev); 3428 3429 if (sc->bge_res != NULL) 3430 bus_release_resource(dev, SYS_RES_MEMORY, 3431 PCIR_BAR(0), sc->bge_res); 3432 3433 if (sc->bge_ifp != NULL) 3434 if_free(sc->bge_ifp); 3435 3436 bge_dma_free(sc); 3437 3438 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3439 BGE_LOCK_DESTROY(sc); 3440 } 3441 3442 static int 3443 bge_reset(struct bge_softc *sc) 3444 { 3445 device_t dev; 3446 uint32_t cachesize, command, pcistate, reset, val; 3447 void (*write_op)(struct bge_softc *, int, int); 3448 uint16_t devctl; 3449 int i; 3450 3451 dev = sc->bge_dev; 3452 3453 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3454 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3455 if (sc->bge_flags & BGE_FLAG_PCIE) 3456 write_op = bge_writemem_direct; 3457 else 3458 write_op = bge_writemem_ind; 3459 } else 3460 write_op = bge_writereg_ind; 3461 3462 /* Save some important PCI state. */ 3463 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3464 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3465 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3466 3467 pci_write_config(dev, BGE_PCI_MISC_CTL, 3468 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3469 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3470 3471 /* Disable fastboot on controllers that support it. */ 3472 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3473 BGE_IS_5755_PLUS(sc)) { 3474 if (bootverbose) 3475 device_printf(dev, "Disabling fastboot\n"); 3476 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3477 } 3478 3479 /* 3480 * Write the magic number to SRAM at offset 0xB50. 3481 * When firmware finishes its initialization it will 3482 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3483 */ 3484 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3485 3486 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3487 3488 /* XXX: Broadcom Linux driver. */ 3489 if (sc->bge_flags & BGE_FLAG_PCIE) { 3490 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3491 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3492 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3493 /* Prevent PCIE link training during global reset */ 3494 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3495 reset |= 1 << 29; 3496 } 3497 } 3498 3499 /* 3500 * Set GPHY Power Down Override to leave GPHY 3501 * powered up in D0 uninitialized. 3502 */ 3503 if (BGE_IS_5705_PLUS(sc) && 3504 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 3505 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3506 3507 /* Issue global reset */ 3508 write_op(sc, BGE_MISC_CFG, reset); 3509 3510 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3511 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3512 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3513 val | BGE_VCPU_STATUS_DRV_RESET); 3514 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3515 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3516 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3517 } 3518 3519 DELAY(1000); 3520 3521 /* XXX: Broadcom Linux driver. */ 3522 if (sc->bge_flags & BGE_FLAG_PCIE) { 3523 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3524 DELAY(500000); /* wait for link training to complete */ 3525 val = pci_read_config(dev, 0xC4, 4); 3526 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3527 } 3528 devctl = pci_read_config(dev, 3529 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3530 /* Clear enable no snoop and disable relaxed ordering. */ 3531 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3532 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3533 /* Set PCIE max payload size to 128. */ 3534 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3535 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3536 devctl, 2); 3537 /* Clear error status. */ 3538 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3539 PCIM_EXP_STA_CORRECTABLE_ERROR | 3540 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3541 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3542 } 3543 3544 /* Reset some of the PCI state that got zapped by reset. */ 3545 pci_write_config(dev, BGE_PCI_MISC_CTL, 3546 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3547 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3548 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3549 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3550 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3551 /* 3552 * Disable PCI-X relaxed ordering to ensure status block update 3553 * comes first then packet buffer DMA. Otherwise driver may 3554 * read stale status block. 3555 */ 3556 if (sc->bge_flags & BGE_FLAG_PCIX) { 3557 devctl = pci_read_config(dev, 3558 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3559 devctl &= ~PCIXM_COMMAND_ERO; 3560 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3561 devctl &= ~PCIXM_COMMAND_MAX_READ; 3562 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3563 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3564 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3565 PCIXM_COMMAND_MAX_READ); 3566 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3567 } 3568 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3569 devctl, 2); 3570 } 3571 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 3572 if (BGE_IS_5714_FAMILY(sc)) { 3573 /* This chip disables MSI on reset. */ 3574 if (sc->bge_flags & BGE_FLAG_MSI) { 3575 val = pci_read_config(dev, 3576 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3577 pci_write_config(dev, 3578 sc->bge_msicap + PCIR_MSI_CTRL, 3579 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3580 val = CSR_READ_4(sc, BGE_MSI_MODE); 3581 CSR_WRITE_4(sc, BGE_MSI_MODE, 3582 val | BGE_MSIMODE_ENABLE); 3583 } 3584 val = CSR_READ_4(sc, BGE_MARB_MODE); 3585 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3586 } else 3587 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3588 3589 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3590 for (i = 0; i < BGE_TIMEOUT; i++) { 3591 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3592 if (val & BGE_VCPU_STATUS_INIT_DONE) 3593 break; 3594 DELAY(100); 3595 } 3596 if (i == BGE_TIMEOUT) { 3597 device_printf(dev, "reset timed out\n"); 3598 return (1); 3599 } 3600 } else { 3601 /* 3602 * Poll until we see the 1's complement of the magic number. 3603 * This indicates that the firmware initialization is complete. 3604 * We expect this to fail if no chip containing the Ethernet 3605 * address is fitted though. 3606 */ 3607 for (i = 0; i < BGE_TIMEOUT; i++) { 3608 DELAY(10); 3609 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 3610 if (val == ~BGE_SRAM_FW_MB_MAGIC) 3611 break; 3612 } 3613 3614 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3615 device_printf(dev, 3616 "firmware handshake timed out, found 0x%08x\n", 3617 val); 3618 /* BCM57765 A0 needs additional time before accessing. */ 3619 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 3620 DELAY(10 * 1000); /* XXX */ 3621 } 3622 3623 /* 3624 * XXX Wait for the value of the PCISTATE register to 3625 * return to its original pre-reset state. This is a 3626 * fairly good indicator of reset completion. If we don't 3627 * wait for the reset to fully complete, trying to read 3628 * from the device's non-PCI registers may yield garbage 3629 * results. 3630 */ 3631 for (i = 0; i < BGE_TIMEOUT; i++) { 3632 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3633 break; 3634 DELAY(10); 3635 } 3636 3637 /* Fix up byte swapping. */ 3638 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 3639 3640 /* Tell the ASF firmware we are up */ 3641 if (sc->bge_asf_mode & ASF_STACKUP) 3642 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3643 3644 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3645 3646 /* 3647 * The 5704 in TBI mode apparently needs some special 3648 * adjustment to insure the SERDES drive level is set 3649 * to 1.2V. 3650 */ 3651 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3652 sc->bge_flags & BGE_FLAG_TBI) { 3653 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3654 val = (val & ~0xFFF) | 0x880; 3655 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3656 } 3657 3658 /* XXX: Broadcom Linux driver. */ 3659 if (sc->bge_flags & BGE_FLAG_PCIE && 3660 !BGE_IS_5717_PLUS(sc) && 3661 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3662 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3663 /* Enable Data FIFO protection. */ 3664 val = CSR_READ_4(sc, 0x7C00); 3665 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3666 } 3667 DELAY(10000); 3668 3669 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 3670 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 3671 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 3672 3673 return (0); 3674 } 3675 3676 static __inline void 3677 bge_rxreuse_std(struct bge_softc *sc, int i) 3678 { 3679 struct bge_rx_bd *r; 3680 3681 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3682 r->bge_flags = BGE_RXBDFLAG_END; 3683 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3684 r->bge_idx = i; 3685 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3686 } 3687 3688 static __inline void 3689 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3690 { 3691 struct bge_extrx_bd *r; 3692 3693 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3694 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3695 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3696 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3697 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3698 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3699 r->bge_idx = i; 3700 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3701 } 3702 3703 /* 3704 * Frame reception handling. This is called if there's a frame 3705 * on the receive return list. 3706 * 3707 * Note: we have to be able to handle two possibilities here: 3708 * 1) the frame is from the jumbo receive ring 3709 * 2) the frame is from the standard receive ring 3710 */ 3711 3712 static int 3713 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3714 { 3715 struct ifnet *ifp; 3716 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3717 uint16_t rx_cons; 3718 3719 rx_cons = sc->bge_rx_saved_considx; 3720 3721 /* Nothing to do. */ 3722 if (rx_cons == rx_prod) 3723 return (rx_npkts); 3724 3725 ifp = sc->bge_ifp; 3726 3727 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3728 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3729 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3730 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3731 if (BGE_IS_JUMBO_CAPABLE(sc) && 3732 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3733 (MCLBYTES - ETHER_ALIGN)) 3734 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3735 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3736 3737 while (rx_cons != rx_prod) { 3738 struct bge_rx_bd *cur_rx; 3739 uint32_t rxidx; 3740 struct mbuf *m = NULL; 3741 uint16_t vlan_tag = 0; 3742 int have_tag = 0; 3743 3744 #ifdef DEVICE_POLLING 3745 if (ifp->if_capenable & IFCAP_POLLING) { 3746 if (sc->rxcycles <= 0) 3747 break; 3748 sc->rxcycles--; 3749 } 3750 #endif 3751 3752 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3753 3754 rxidx = cur_rx->bge_idx; 3755 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3756 3757 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3758 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3759 have_tag = 1; 3760 vlan_tag = cur_rx->bge_vlan_tag; 3761 } 3762 3763 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3764 jumbocnt++; 3765 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3766 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3767 bge_rxreuse_jumbo(sc, rxidx); 3768 continue; 3769 } 3770 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3771 bge_rxreuse_jumbo(sc, rxidx); 3772 ifp->if_iqdrops++; 3773 continue; 3774 } 3775 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3776 } else { 3777 stdcnt++; 3778 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3779 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3780 bge_rxreuse_std(sc, rxidx); 3781 continue; 3782 } 3783 if (bge_newbuf_std(sc, rxidx) != 0) { 3784 bge_rxreuse_std(sc, rxidx); 3785 ifp->if_iqdrops++; 3786 continue; 3787 } 3788 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3789 } 3790 3791 ifp->if_ipackets++; 3792 #ifndef __NO_STRICT_ALIGNMENT 3793 /* 3794 * For architectures with strict alignment we must make sure 3795 * the payload is aligned. 3796 */ 3797 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3798 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3799 cur_rx->bge_len); 3800 m->m_data += ETHER_ALIGN; 3801 } 3802 #endif 3803 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3804 m->m_pkthdr.rcvif = ifp; 3805 3806 if (ifp->if_capenable & IFCAP_RXCSUM) 3807 bge_rxcsum(sc, cur_rx, m); 3808 3809 /* 3810 * If we received a packet with a vlan tag, 3811 * attach that information to the packet. 3812 */ 3813 if (have_tag) { 3814 m->m_pkthdr.ether_vtag = vlan_tag; 3815 m->m_flags |= M_VLANTAG; 3816 } 3817 3818 if (holdlck != 0) { 3819 BGE_UNLOCK(sc); 3820 (*ifp->if_input)(ifp, m); 3821 BGE_LOCK(sc); 3822 } else 3823 (*ifp->if_input)(ifp, m); 3824 rx_npkts++; 3825 3826 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3827 return (rx_npkts); 3828 } 3829 3830 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3831 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3832 if (stdcnt > 0) 3833 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3834 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3835 3836 if (jumbocnt > 0) 3837 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3838 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3839 3840 sc->bge_rx_saved_considx = rx_cons; 3841 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3842 if (stdcnt) 3843 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3844 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3845 if (jumbocnt) 3846 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3847 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3848 #ifdef notyet 3849 /* 3850 * This register wraps very quickly under heavy packet drops. 3851 * If you need correct statistics, you can enable this check. 3852 */ 3853 if (BGE_IS_5705_PLUS(sc)) 3854 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3855 #endif 3856 return (rx_npkts); 3857 } 3858 3859 static void 3860 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 3861 { 3862 3863 if (BGE_IS_5717_PLUS(sc)) { 3864 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 3865 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3866 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3867 if ((cur_rx->bge_error_flag & 3868 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 3869 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3870 } 3871 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 3872 m->m_pkthdr.csum_data = 3873 cur_rx->bge_tcp_udp_csum; 3874 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3875 CSUM_PSEUDO_HDR; 3876 } 3877 } 3878 } else { 3879 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3880 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3881 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3882 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3883 } 3884 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3885 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3886 m->m_pkthdr.csum_data = 3887 cur_rx->bge_tcp_udp_csum; 3888 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3889 CSUM_PSEUDO_HDR; 3890 } 3891 } 3892 } 3893 3894 static void 3895 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3896 { 3897 struct bge_tx_bd *cur_tx; 3898 struct ifnet *ifp; 3899 3900 BGE_LOCK_ASSERT(sc); 3901 3902 /* Nothing to do. */ 3903 if (sc->bge_tx_saved_considx == tx_cons) 3904 return; 3905 3906 ifp = sc->bge_ifp; 3907 3908 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3909 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3910 /* 3911 * Go through our tx ring and free mbufs for those 3912 * frames that have been sent. 3913 */ 3914 while (sc->bge_tx_saved_considx != tx_cons) { 3915 uint32_t idx; 3916 3917 idx = sc->bge_tx_saved_considx; 3918 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3919 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3920 ifp->if_opackets++; 3921 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3922 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3923 sc->bge_cdata.bge_tx_dmamap[idx], 3924 BUS_DMASYNC_POSTWRITE); 3925 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3926 sc->bge_cdata.bge_tx_dmamap[idx]); 3927 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3928 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3929 } 3930 sc->bge_txcnt--; 3931 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3932 } 3933 3934 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3935 if (sc->bge_txcnt == 0) 3936 sc->bge_timer = 0; 3937 } 3938 3939 #ifdef DEVICE_POLLING 3940 static int 3941 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3942 { 3943 struct bge_softc *sc = ifp->if_softc; 3944 uint16_t rx_prod, tx_cons; 3945 uint32_t statusword; 3946 int rx_npkts = 0; 3947 3948 BGE_LOCK(sc); 3949 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3950 BGE_UNLOCK(sc); 3951 return (rx_npkts); 3952 } 3953 3954 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3955 sc->bge_cdata.bge_status_map, 3956 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3957 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3958 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3959 3960 statusword = sc->bge_ldata.bge_status_block->bge_status; 3961 sc->bge_ldata.bge_status_block->bge_status = 0; 3962 3963 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3964 sc->bge_cdata.bge_status_map, 3965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3966 3967 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3968 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3969 sc->bge_link_evt++; 3970 3971 if (cmd == POLL_AND_CHECK_STATUS) 3972 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3973 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3974 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3975 bge_link_upd(sc); 3976 3977 sc->rxcycles = count; 3978 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3979 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3980 BGE_UNLOCK(sc); 3981 return (rx_npkts); 3982 } 3983 bge_txeof(sc, tx_cons); 3984 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3985 bge_start_locked(ifp); 3986 3987 BGE_UNLOCK(sc); 3988 return (rx_npkts); 3989 } 3990 #endif /* DEVICE_POLLING */ 3991 3992 static int 3993 bge_msi_intr(void *arg) 3994 { 3995 struct bge_softc *sc; 3996 3997 sc = (struct bge_softc *)arg; 3998 /* 3999 * This interrupt is not shared and controller already 4000 * disabled further interrupt. 4001 */ 4002 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4003 return (FILTER_HANDLED); 4004 } 4005 4006 static void 4007 bge_intr_task(void *arg, int pending) 4008 { 4009 struct bge_softc *sc; 4010 struct ifnet *ifp; 4011 uint32_t status, status_tag; 4012 uint16_t rx_prod, tx_cons; 4013 4014 sc = (struct bge_softc *)arg; 4015 ifp = sc->bge_ifp; 4016 4017 BGE_LOCK(sc); 4018 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4019 BGE_UNLOCK(sc); 4020 return; 4021 } 4022 4023 /* Get updated status block. */ 4024 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4025 sc->bge_cdata.bge_status_map, 4026 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4027 4028 /* Save producer/consumer indexess. */ 4029 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4030 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4031 status = sc->bge_ldata.bge_status_block->bge_status; 4032 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4033 sc->bge_ldata.bge_status_block->bge_status = 0; 4034 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4035 sc->bge_cdata.bge_status_map, 4036 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4037 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4038 status_tag = 0; 4039 4040 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4041 bge_link_upd(sc); 4042 4043 /* Let controller work. */ 4044 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4045 4046 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4047 sc->bge_rx_saved_considx != rx_prod) { 4048 /* Check RX return ring producer/consumer. */ 4049 BGE_UNLOCK(sc); 4050 bge_rxeof(sc, rx_prod, 0); 4051 BGE_LOCK(sc); 4052 } 4053 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4054 /* Check TX ring producer/consumer. */ 4055 bge_txeof(sc, tx_cons); 4056 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4057 bge_start_locked(ifp); 4058 } 4059 BGE_UNLOCK(sc); 4060 } 4061 4062 static void 4063 bge_intr(void *xsc) 4064 { 4065 struct bge_softc *sc; 4066 struct ifnet *ifp; 4067 uint32_t statusword; 4068 uint16_t rx_prod, tx_cons; 4069 4070 sc = xsc; 4071 4072 BGE_LOCK(sc); 4073 4074 ifp = sc->bge_ifp; 4075 4076 #ifdef DEVICE_POLLING 4077 if (ifp->if_capenable & IFCAP_POLLING) { 4078 BGE_UNLOCK(sc); 4079 return; 4080 } 4081 #endif 4082 4083 /* 4084 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4085 * disable interrupts by writing nonzero like we used to, since with 4086 * our current organization this just gives complications and 4087 * pessimizations for re-enabling interrupts. We used to have races 4088 * instead of the necessary complications. Disabling interrupts 4089 * would just reduce the chance of a status update while we are 4090 * running (by switching to the interrupt-mode coalescence 4091 * parameters), but this chance is already very low so it is more 4092 * efficient to get another interrupt than prevent it. 4093 * 4094 * We do the ack first to ensure another interrupt if there is a 4095 * status update after the ack. We don't check for the status 4096 * changing later because it is more efficient to get another 4097 * interrupt than prevent it, not quite as above (not checking is 4098 * a smaller optimization than not toggling the interrupt enable, 4099 * since checking doesn't involve PCI accesses and toggling require 4100 * the status check). So toggling would probably be a pessimization 4101 * even with MSI. It would only be needed for using a task queue. 4102 */ 4103 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4104 4105 /* 4106 * Do the mandatory PCI flush as well as get the link status. 4107 */ 4108 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4109 4110 /* Make sure the descriptor ring indexes are coherent. */ 4111 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4112 sc->bge_cdata.bge_status_map, 4113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4114 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4115 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4116 sc->bge_ldata.bge_status_block->bge_status = 0; 4117 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4118 sc->bge_cdata.bge_status_map, 4119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4120 4121 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4122 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4123 statusword || sc->bge_link_evt) 4124 bge_link_upd(sc); 4125 4126 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4127 /* Check RX return ring producer/consumer. */ 4128 bge_rxeof(sc, rx_prod, 1); 4129 } 4130 4131 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4132 /* Check TX ring producer/consumer. */ 4133 bge_txeof(sc, tx_cons); 4134 } 4135 4136 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4137 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4138 bge_start_locked(ifp); 4139 4140 BGE_UNLOCK(sc); 4141 } 4142 4143 static void 4144 bge_asf_driver_up(struct bge_softc *sc) 4145 { 4146 if (sc->bge_asf_mode & ASF_STACKUP) { 4147 /* Send ASF heartbeat aprox. every 2s */ 4148 if (sc->bge_asf_count) 4149 sc->bge_asf_count --; 4150 else { 4151 sc->bge_asf_count = 2; 4152 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4153 BGE_FW_CMD_DRV_ALIVE); 4154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4155 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4156 BGE_FW_HB_TIMEOUT_SEC); 4157 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4158 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4159 BGE_RX_CPU_DRV_EVENT); 4160 } 4161 } 4162 } 4163 4164 static void 4165 bge_tick(void *xsc) 4166 { 4167 struct bge_softc *sc = xsc; 4168 struct mii_data *mii = NULL; 4169 4170 BGE_LOCK_ASSERT(sc); 4171 4172 /* Synchronize with possible callout reset/stop. */ 4173 if (callout_pending(&sc->bge_stat_ch) || 4174 !callout_active(&sc->bge_stat_ch)) 4175 return; 4176 4177 if (BGE_IS_5705_PLUS(sc)) 4178 bge_stats_update_regs(sc); 4179 else 4180 bge_stats_update(sc); 4181 4182 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4183 mii = device_get_softc(sc->bge_miibus); 4184 /* 4185 * Do not touch PHY if we have link up. This could break 4186 * IPMI/ASF mode or produce extra input errors 4187 * (extra errors was reported for bcm5701 & bcm5704). 4188 */ 4189 if (!sc->bge_link) 4190 mii_tick(mii); 4191 } else { 4192 /* 4193 * Since in TBI mode auto-polling can't be used we should poll 4194 * link status manually. Here we register pending link event 4195 * and trigger interrupt. 4196 */ 4197 #ifdef DEVICE_POLLING 4198 /* In polling mode we poll link state in bge_poll(). */ 4199 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4200 #endif 4201 { 4202 sc->bge_link_evt++; 4203 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4204 sc->bge_flags & BGE_FLAG_5788) 4205 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4206 else 4207 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4208 } 4209 } 4210 4211 bge_asf_driver_up(sc); 4212 bge_watchdog(sc); 4213 4214 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4215 } 4216 4217 static void 4218 bge_stats_update_regs(struct bge_softc *sc) 4219 { 4220 struct ifnet *ifp; 4221 struct bge_mac_stats *stats; 4222 4223 ifp = sc->bge_ifp; 4224 stats = &sc->bge_mac_stats; 4225 4226 stats->ifHCOutOctets += 4227 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4228 stats->etherStatsCollisions += 4229 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4230 stats->outXonSent += 4231 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4232 stats->outXoffSent += 4233 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4234 stats->dot3StatsInternalMacTransmitErrors += 4235 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4236 stats->dot3StatsSingleCollisionFrames += 4237 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4238 stats->dot3StatsMultipleCollisionFrames += 4239 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4240 stats->dot3StatsDeferredTransmissions += 4241 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4242 stats->dot3StatsExcessiveCollisions += 4243 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4244 stats->dot3StatsLateCollisions += 4245 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4246 stats->ifHCOutUcastPkts += 4247 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4248 stats->ifHCOutMulticastPkts += 4249 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4250 stats->ifHCOutBroadcastPkts += 4251 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4252 4253 stats->ifHCInOctets += 4254 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4255 stats->etherStatsFragments += 4256 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4257 stats->ifHCInUcastPkts += 4258 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4259 stats->ifHCInMulticastPkts += 4260 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4261 stats->ifHCInBroadcastPkts += 4262 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4263 stats->dot3StatsFCSErrors += 4264 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4265 stats->dot3StatsAlignmentErrors += 4266 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4267 stats->xonPauseFramesReceived += 4268 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4269 stats->xoffPauseFramesReceived += 4270 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4271 stats->macControlFramesReceived += 4272 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4273 stats->xoffStateEntered += 4274 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4275 stats->dot3StatsFramesTooLong += 4276 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4277 stats->etherStatsJabbers += 4278 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4279 stats->etherStatsUndersizePkts += 4280 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4281 4282 stats->FramesDroppedDueToFilters += 4283 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4284 stats->DmaWriteQueueFull += 4285 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4286 stats->DmaWriteHighPriQueueFull += 4287 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4288 stats->NoMoreRxBDs += 4289 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4290 /* 4291 * XXX 4292 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4293 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4294 * includes number of unwanted multicast frames. This comes 4295 * from silicon bug and known workaround to get rough(not 4296 * exact) counter is to enable interrupt on MBUF low water 4297 * attention. This can be accomplished by setting 4298 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4299 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4300 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4301 * However that change would generate more interrupts and 4302 * there are still possibilities of losing multiple frames 4303 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4304 * Given that the workaround still would not get correct 4305 * counter I don't think it's worth to implement it. So 4306 * ignore reading the counter on controllers that have the 4307 * silicon bug. 4308 */ 4309 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4310 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4311 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4312 stats->InputDiscards += 4313 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4314 stats->InputErrors += 4315 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4316 stats->RecvThresholdHit += 4317 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4318 4319 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4320 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4321 stats->InputErrors); 4322 } 4323 4324 static void 4325 bge_stats_clear_regs(struct bge_softc *sc) 4326 { 4327 4328 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4329 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4330 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4331 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4332 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4333 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4334 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4335 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4336 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4337 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4338 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4339 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4340 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4341 4342 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4343 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4344 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4345 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4346 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4347 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4348 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4349 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4350 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4351 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4352 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4353 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4354 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4355 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4356 4357 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4358 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4359 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4360 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4361 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4362 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4363 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4364 } 4365 4366 static void 4367 bge_stats_update(struct bge_softc *sc) 4368 { 4369 struct ifnet *ifp; 4370 bus_size_t stats; 4371 uint32_t cnt; /* current register value */ 4372 4373 ifp = sc->bge_ifp; 4374 4375 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4376 4377 #define READ_STAT(sc, stats, stat) \ 4378 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4379 4380 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4381 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4382 sc->bge_tx_collisions = cnt; 4383 4384 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4385 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4386 sc->bge_rx_discards = cnt; 4387 4388 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4389 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4390 sc->bge_tx_discards = cnt; 4391 4392 #undef READ_STAT 4393 } 4394 4395 /* 4396 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4397 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4398 * but when such padded frames employ the bge IP/TCP checksum offload, 4399 * the hardware checksum assist gives incorrect results (possibly 4400 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4401 * If we pad such runts with zeros, the onboard checksum comes out correct. 4402 */ 4403 static __inline int 4404 bge_cksum_pad(struct mbuf *m) 4405 { 4406 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4407 struct mbuf *last; 4408 4409 /* If there's only the packet-header and we can pad there, use it. */ 4410 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4411 M_TRAILINGSPACE(m) >= padlen) { 4412 last = m; 4413 } else { 4414 /* 4415 * Walk packet chain to find last mbuf. We will either 4416 * pad there, or append a new mbuf and pad it. 4417 */ 4418 for (last = m; last->m_next != NULL; last = last->m_next); 4419 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4420 /* Allocate new empty mbuf, pad it. Compact later. */ 4421 struct mbuf *n; 4422 4423 MGET(n, M_DONTWAIT, MT_DATA); 4424 if (n == NULL) 4425 return (ENOBUFS); 4426 n->m_len = 0; 4427 last->m_next = n; 4428 last = n; 4429 } 4430 } 4431 4432 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4433 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4434 last->m_len += padlen; 4435 m->m_pkthdr.len += padlen; 4436 4437 return (0); 4438 } 4439 4440 static struct mbuf * 4441 bge_check_short_dma(struct mbuf *m) 4442 { 4443 struct mbuf *n; 4444 int found; 4445 4446 /* 4447 * If device receive two back-to-back send BDs with less than 4448 * or equal to 8 total bytes then the device may hang. The two 4449 * back-to-back send BDs must in the same frame for this failure 4450 * to occur. Scan mbuf chains and see whether two back-to-back 4451 * send BDs are there. If this is the case, allocate new mbuf 4452 * and copy the frame to workaround the silicon bug. 4453 */ 4454 for (n = m, found = 0; n != NULL; n = n->m_next) { 4455 if (n->m_len < 8) { 4456 found++; 4457 if (found > 1) 4458 break; 4459 continue; 4460 } 4461 found = 0; 4462 } 4463 4464 if (found > 1) { 4465 n = m_defrag(m, M_DONTWAIT); 4466 if (n == NULL) 4467 m_freem(m); 4468 } else 4469 n = m; 4470 return (n); 4471 } 4472 4473 static struct mbuf * 4474 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 4475 uint16_t *flags) 4476 { 4477 struct ip *ip; 4478 struct tcphdr *tcp; 4479 struct mbuf *n; 4480 uint16_t hlen; 4481 uint32_t poff; 4482 4483 if (M_WRITABLE(m) == 0) { 4484 /* Get a writable copy. */ 4485 n = m_dup(m, M_DONTWAIT); 4486 m_freem(m); 4487 if (n == NULL) 4488 return (NULL); 4489 m = n; 4490 } 4491 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 4492 if (m == NULL) 4493 return (NULL); 4494 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4495 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 4496 m = m_pullup(m, poff + sizeof(struct tcphdr)); 4497 if (m == NULL) 4498 return (NULL); 4499 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4500 m = m_pullup(m, poff + (tcp->th_off << 2)); 4501 if (m == NULL) 4502 return (NULL); 4503 /* 4504 * It seems controller doesn't modify IP length and TCP pseudo 4505 * checksum. These checksum computed by upper stack should be 0. 4506 */ 4507 *mss = m->m_pkthdr.tso_segsz; 4508 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4509 ip->ip_sum = 0; 4510 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 4511 /* Clear pseudo checksum computed by TCP stack. */ 4512 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4513 tcp->th_sum = 0; 4514 /* 4515 * Broadcom controllers uses different descriptor format for 4516 * TSO depending on ASIC revision. Due to TSO-capable firmware 4517 * license issue and lower performance of firmware based TSO 4518 * we only support hardware based TSO. 4519 */ 4520 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 4521 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 4522 if (sc->bge_flags & BGE_FLAG_TSO3) { 4523 /* 4524 * For BCM5717 and newer controllers, hardware based TSO 4525 * uses the 14 lower bits of the bge_mss field to store the 4526 * MSS and the upper 2 bits to store the lowest 2 bits of 4527 * the IP/TCP header length. The upper 6 bits of the header 4528 * length are stored in the bge_flags[14:10,4] field. Jumbo 4529 * frames are supported. 4530 */ 4531 *mss |= ((hlen & 0x3) << 14); 4532 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 4533 } else { 4534 /* 4535 * For BCM5755 and newer controllers, hardware based TSO uses 4536 * the lower 11 bits to store the MSS and the upper 5 bits to 4537 * store the IP/TCP header length. Jumbo frames are not 4538 * supported. 4539 */ 4540 *mss |= (hlen << 11); 4541 } 4542 return (m); 4543 } 4544 4545 /* 4546 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4547 * pointers to descriptors. 4548 */ 4549 static int 4550 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 4551 { 4552 bus_dma_segment_t segs[BGE_NSEG_NEW]; 4553 bus_dmamap_t map; 4554 struct bge_tx_bd *d; 4555 struct mbuf *m = *m_head; 4556 uint32_t idx = *txidx; 4557 uint16_t csum_flags, mss, vlan_tag; 4558 int nsegs, i, error; 4559 4560 csum_flags = 0; 4561 mss = 0; 4562 vlan_tag = 0; 4563 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 4564 m->m_next != NULL) { 4565 *m_head = bge_check_short_dma(m); 4566 if (*m_head == NULL) 4567 return (ENOBUFS); 4568 m = *m_head; 4569 } 4570 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 4571 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 4572 if (*m_head == NULL) 4573 return (ENOBUFS); 4574 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 4575 BGE_TXBDFLAG_CPU_POST_DMA; 4576 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 4577 if (m->m_pkthdr.csum_flags & CSUM_IP) 4578 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4579 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 4580 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4581 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4582 (error = bge_cksum_pad(m)) != 0) { 4583 m_freem(m); 4584 *m_head = NULL; 4585 return (error); 4586 } 4587 } 4588 if (m->m_flags & M_LASTFRAG) 4589 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 4590 else if (m->m_flags & M_FRAG) 4591 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 4592 } 4593 4594 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 4595 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 4596 m->m_pkthdr.len > ETHER_MAX_LEN) 4597 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 4598 if (sc->bge_forced_collapse > 0 && 4599 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 4600 /* 4601 * Forcedly collapse mbuf chains to overcome hardware 4602 * limitation which only support a single outstanding 4603 * DMA read operation. 4604 */ 4605 if (sc->bge_forced_collapse == 1) 4606 m = m_defrag(m, M_DONTWAIT); 4607 else 4608 m = m_collapse(m, M_DONTWAIT, 4609 sc->bge_forced_collapse); 4610 if (m == NULL) 4611 m = *m_head; 4612 *m_head = m; 4613 } 4614 } 4615 4616 map = sc->bge_cdata.bge_tx_dmamap[idx]; 4617 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4618 &nsegs, BUS_DMA_NOWAIT); 4619 if (error == EFBIG) { 4620 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4621 if (m == NULL) { 4622 m_freem(*m_head); 4623 *m_head = NULL; 4624 return (ENOBUFS); 4625 } 4626 *m_head = m; 4627 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4628 m, segs, &nsegs, BUS_DMA_NOWAIT); 4629 if (error) { 4630 m_freem(m); 4631 *m_head = NULL; 4632 return (error); 4633 } 4634 } else if (error != 0) 4635 return (error); 4636 4637 /* Check if we have enough free send BDs. */ 4638 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4639 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4640 return (ENOBUFS); 4641 } 4642 4643 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4644 4645 if (m->m_flags & M_VLANTAG) { 4646 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4647 vlan_tag = m->m_pkthdr.ether_vtag; 4648 } 4649 for (i = 0; ; i++) { 4650 d = &sc->bge_ldata.bge_tx_ring[idx]; 4651 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4652 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4653 d->bge_len = segs[i].ds_len; 4654 d->bge_flags = csum_flags; 4655 d->bge_vlan_tag = vlan_tag; 4656 d->bge_mss = mss; 4657 if (i == nsegs - 1) 4658 break; 4659 BGE_INC(idx, BGE_TX_RING_CNT); 4660 } 4661 4662 /* Mark the last segment as end of packet... */ 4663 d->bge_flags |= BGE_TXBDFLAG_END; 4664 4665 /* 4666 * Insure that the map for this transmission 4667 * is placed at the array index of the last descriptor 4668 * in this chain. 4669 */ 4670 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4671 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4672 sc->bge_cdata.bge_tx_chain[idx] = m; 4673 sc->bge_txcnt += nsegs; 4674 4675 BGE_INC(idx, BGE_TX_RING_CNT); 4676 *txidx = idx; 4677 4678 return (0); 4679 } 4680 4681 /* 4682 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4683 * to the mbuf data regions directly in the transmit descriptors. 4684 */ 4685 static void 4686 bge_start_locked(struct ifnet *ifp) 4687 { 4688 struct bge_softc *sc; 4689 struct mbuf *m_head; 4690 uint32_t prodidx; 4691 int count; 4692 4693 sc = ifp->if_softc; 4694 BGE_LOCK_ASSERT(sc); 4695 4696 if (!sc->bge_link || 4697 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4698 IFF_DRV_RUNNING) 4699 return; 4700 4701 prodidx = sc->bge_tx_prodidx; 4702 4703 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4704 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4705 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4706 break; 4707 } 4708 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4709 if (m_head == NULL) 4710 break; 4711 4712 /* 4713 * XXX 4714 * The code inside the if() block is never reached since we 4715 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4716 * requests to checksum TCP/UDP in a fragmented packet. 4717 * 4718 * XXX 4719 * safety overkill. If this is a fragmented packet chain 4720 * with delayed TCP/UDP checksums, then only encapsulate 4721 * it if we have enough descriptors to handle the entire 4722 * chain at once. 4723 * (paranoia -- may not actually be needed) 4724 */ 4725 if (m_head->m_flags & M_FIRSTFRAG && 4726 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4727 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4728 m_head->m_pkthdr.csum_data + 16) { 4729 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4730 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4731 break; 4732 } 4733 } 4734 4735 /* 4736 * Pack the data into the transmit ring. If we 4737 * don't have room, set the OACTIVE flag and wait 4738 * for the NIC to drain the ring. 4739 */ 4740 if (bge_encap(sc, &m_head, &prodidx)) { 4741 if (m_head == NULL) 4742 break; 4743 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4744 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4745 break; 4746 } 4747 ++count; 4748 4749 /* 4750 * If there's a BPF listener, bounce a copy of this frame 4751 * to him. 4752 */ 4753 #ifdef ETHER_BPF_MTAP 4754 ETHER_BPF_MTAP(ifp, m_head); 4755 #else 4756 BPF_MTAP(ifp, m_head); 4757 #endif 4758 } 4759 4760 if (count > 0) { 4761 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4762 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4763 /* Transmit. */ 4764 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4765 /* 5700 b2 errata */ 4766 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4767 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4768 4769 sc->bge_tx_prodidx = prodidx; 4770 4771 /* 4772 * Set a timeout in case the chip goes out to lunch. 4773 */ 4774 sc->bge_timer = 5; 4775 } 4776 } 4777 4778 /* 4779 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4780 * to the mbuf data regions directly in the transmit descriptors. 4781 */ 4782 static void 4783 bge_start(struct ifnet *ifp) 4784 { 4785 struct bge_softc *sc; 4786 4787 sc = ifp->if_softc; 4788 BGE_LOCK(sc); 4789 bge_start_locked(ifp); 4790 BGE_UNLOCK(sc); 4791 } 4792 4793 static void 4794 bge_init_locked(struct bge_softc *sc) 4795 { 4796 struct ifnet *ifp; 4797 uint16_t *m; 4798 uint32_t mode; 4799 4800 BGE_LOCK_ASSERT(sc); 4801 4802 ifp = sc->bge_ifp; 4803 4804 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4805 return; 4806 4807 /* Cancel pending I/O and flush buffers. */ 4808 bge_stop(sc); 4809 4810 bge_stop_fw(sc); 4811 bge_sig_pre_reset(sc, BGE_RESET_START); 4812 bge_reset(sc); 4813 bge_sig_legacy(sc, BGE_RESET_START); 4814 bge_sig_post_reset(sc, BGE_RESET_START); 4815 4816 bge_chipinit(sc); 4817 4818 /* 4819 * Init the various state machines, ring 4820 * control blocks and firmware. 4821 */ 4822 if (bge_blockinit(sc)) { 4823 device_printf(sc->bge_dev, "initialization failure\n"); 4824 return; 4825 } 4826 4827 ifp = sc->bge_ifp; 4828 4829 /* Specify MTU. */ 4830 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4831 ETHER_HDR_LEN + ETHER_CRC_LEN + 4832 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4833 4834 /* Load our MAC address. */ 4835 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4836 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4837 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4838 4839 /* Program promiscuous mode. */ 4840 bge_setpromisc(sc); 4841 4842 /* Program multicast filter. */ 4843 bge_setmulti(sc); 4844 4845 /* Program VLAN tag stripping. */ 4846 bge_setvlan(sc); 4847 4848 /* Override UDP checksum offloading. */ 4849 if (sc->bge_forced_udpcsum == 0) 4850 sc->bge_csum_features &= ~CSUM_UDP; 4851 else 4852 sc->bge_csum_features |= CSUM_UDP; 4853 if (ifp->if_capabilities & IFCAP_TXCSUM && 4854 ifp->if_capenable & IFCAP_TXCSUM) { 4855 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4856 ifp->if_hwassist |= sc->bge_csum_features; 4857 } 4858 4859 /* Init RX ring. */ 4860 if (bge_init_rx_ring_std(sc) != 0) { 4861 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4862 bge_stop(sc); 4863 return; 4864 } 4865 4866 /* 4867 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4868 * memory to insure that the chip has in fact read the first 4869 * entry of the ring. 4870 */ 4871 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4872 uint32_t v, i; 4873 for (i = 0; i < 10; i++) { 4874 DELAY(20); 4875 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4876 if (v == (MCLBYTES - ETHER_ALIGN)) 4877 break; 4878 } 4879 if (i == 10) 4880 device_printf (sc->bge_dev, 4881 "5705 A0 chip failed to load RX ring\n"); 4882 } 4883 4884 /* Init jumbo RX ring. */ 4885 if (BGE_IS_JUMBO_CAPABLE(sc) && 4886 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4887 (MCLBYTES - ETHER_ALIGN)) { 4888 if (bge_init_rx_ring_jumbo(sc) != 0) { 4889 device_printf(sc->bge_dev, 4890 "no memory for jumbo Rx buffers.\n"); 4891 bge_stop(sc); 4892 return; 4893 } 4894 } 4895 4896 /* Init our RX return ring index. */ 4897 sc->bge_rx_saved_considx = 0; 4898 4899 /* Init our RX/TX stat counters. */ 4900 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4901 4902 /* Init TX ring. */ 4903 bge_init_tx_ring(sc); 4904 4905 /* Enable TX MAC state machine lockup fix. */ 4906 mode = CSR_READ_4(sc, BGE_TX_MODE); 4907 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 4908 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4909 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 4910 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 4911 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 4912 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 4913 } 4914 /* Turn on transmitter. */ 4915 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4916 4917 /* Turn on receiver. */ 4918 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4919 4920 /* 4921 * Set the number of good frames to receive after RX MBUF 4922 * Low Watermark has been reached. After the RX MAC receives 4923 * this number of frames, it will drop subsequent incoming 4924 * frames until the MBUF High Watermark is reached. 4925 */ 4926 if (sc->bge_asicrev == BGE_ASICREV_BCM57765) 4927 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 4928 else 4929 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4930 4931 /* Clear MAC statistics. */ 4932 if (BGE_IS_5705_PLUS(sc)) 4933 bge_stats_clear_regs(sc); 4934 4935 /* Tell firmware we're alive. */ 4936 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4937 4938 #ifdef DEVICE_POLLING 4939 /* Disable interrupts if we are polling. */ 4940 if (ifp->if_capenable & IFCAP_POLLING) { 4941 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4942 BGE_PCIMISCCTL_MASK_PCI_INTR); 4943 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4944 } else 4945 #endif 4946 4947 /* Enable host interrupts. */ 4948 { 4949 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4950 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4951 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4952 } 4953 4954 bge_ifmedia_upd_locked(ifp); 4955 4956 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4957 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4958 4959 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4960 } 4961 4962 static void 4963 bge_init(void *xsc) 4964 { 4965 struct bge_softc *sc = xsc; 4966 4967 BGE_LOCK(sc); 4968 bge_init_locked(sc); 4969 BGE_UNLOCK(sc); 4970 } 4971 4972 /* 4973 * Set media options. 4974 */ 4975 static int 4976 bge_ifmedia_upd(struct ifnet *ifp) 4977 { 4978 struct bge_softc *sc = ifp->if_softc; 4979 int res; 4980 4981 BGE_LOCK(sc); 4982 res = bge_ifmedia_upd_locked(ifp); 4983 BGE_UNLOCK(sc); 4984 4985 return (res); 4986 } 4987 4988 static int 4989 bge_ifmedia_upd_locked(struct ifnet *ifp) 4990 { 4991 struct bge_softc *sc = ifp->if_softc; 4992 struct mii_data *mii; 4993 struct mii_softc *miisc; 4994 struct ifmedia *ifm; 4995 4996 BGE_LOCK_ASSERT(sc); 4997 4998 ifm = &sc->bge_ifmedia; 4999 5000 /* If this is a 1000baseX NIC, enable the TBI port. */ 5001 if (sc->bge_flags & BGE_FLAG_TBI) { 5002 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5003 return (EINVAL); 5004 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5005 case IFM_AUTO: 5006 /* 5007 * The BCM5704 ASIC appears to have a special 5008 * mechanism for programming the autoneg 5009 * advertisement registers in TBI mode. 5010 */ 5011 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5012 uint32_t sgdig; 5013 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5014 if (sgdig & BGE_SGDIGSTS_DONE) { 5015 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5016 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5017 sgdig |= BGE_SGDIGCFG_AUTO | 5018 BGE_SGDIGCFG_PAUSE_CAP | 5019 BGE_SGDIGCFG_ASYM_PAUSE; 5020 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5021 sgdig | BGE_SGDIGCFG_SEND); 5022 DELAY(5); 5023 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5024 } 5025 } 5026 break; 5027 case IFM_1000_SX: 5028 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5029 BGE_CLRBIT(sc, BGE_MAC_MODE, 5030 BGE_MACMODE_HALF_DUPLEX); 5031 } else { 5032 BGE_SETBIT(sc, BGE_MAC_MODE, 5033 BGE_MACMODE_HALF_DUPLEX); 5034 } 5035 break; 5036 default: 5037 return (EINVAL); 5038 } 5039 return (0); 5040 } 5041 5042 sc->bge_link_evt++; 5043 mii = device_get_softc(sc->bge_miibus); 5044 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5045 PHY_RESET(miisc); 5046 mii_mediachg(mii); 5047 5048 /* 5049 * Force an interrupt so that we will call bge_link_upd 5050 * if needed and clear any pending link state attention. 5051 * Without this we are not getting any further interrupts 5052 * for link state changes and thus will not UP the link and 5053 * not be able to send in bge_start_locked. The only 5054 * way to get things working was to receive a packet and 5055 * get an RX intr. 5056 * bge_tick should help for fiber cards and we might not 5057 * need to do this here if BGE_FLAG_TBI is set but as 5058 * we poll for fiber anyway it should not harm. 5059 */ 5060 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5061 sc->bge_flags & BGE_FLAG_5788) 5062 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5063 else 5064 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5065 5066 return (0); 5067 } 5068 5069 /* 5070 * Report current media status. 5071 */ 5072 static void 5073 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5074 { 5075 struct bge_softc *sc = ifp->if_softc; 5076 struct mii_data *mii; 5077 5078 BGE_LOCK(sc); 5079 5080 if (sc->bge_flags & BGE_FLAG_TBI) { 5081 ifmr->ifm_status = IFM_AVALID; 5082 ifmr->ifm_active = IFM_ETHER; 5083 if (CSR_READ_4(sc, BGE_MAC_STS) & 5084 BGE_MACSTAT_TBI_PCS_SYNCHED) 5085 ifmr->ifm_status |= IFM_ACTIVE; 5086 else { 5087 ifmr->ifm_active |= IFM_NONE; 5088 BGE_UNLOCK(sc); 5089 return; 5090 } 5091 ifmr->ifm_active |= IFM_1000_SX; 5092 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5093 ifmr->ifm_active |= IFM_HDX; 5094 else 5095 ifmr->ifm_active |= IFM_FDX; 5096 BGE_UNLOCK(sc); 5097 return; 5098 } 5099 5100 mii = device_get_softc(sc->bge_miibus); 5101 mii_pollstat(mii); 5102 ifmr->ifm_active = mii->mii_media_active; 5103 ifmr->ifm_status = mii->mii_media_status; 5104 5105 BGE_UNLOCK(sc); 5106 } 5107 5108 static int 5109 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5110 { 5111 struct bge_softc *sc = ifp->if_softc; 5112 struct ifreq *ifr = (struct ifreq *) data; 5113 struct mii_data *mii; 5114 int flags, mask, error = 0; 5115 5116 switch (command) { 5117 case SIOCSIFMTU: 5118 if (BGE_IS_JUMBO_CAPABLE(sc) || 5119 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5120 if (ifr->ifr_mtu < ETHERMIN || 5121 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5122 error = EINVAL; 5123 break; 5124 } 5125 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5126 error = EINVAL; 5127 break; 5128 } 5129 BGE_LOCK(sc); 5130 if (ifp->if_mtu != ifr->ifr_mtu) { 5131 ifp->if_mtu = ifr->ifr_mtu; 5132 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5133 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5134 bge_init_locked(sc); 5135 } 5136 } 5137 BGE_UNLOCK(sc); 5138 break; 5139 case SIOCSIFFLAGS: 5140 BGE_LOCK(sc); 5141 if (ifp->if_flags & IFF_UP) { 5142 /* 5143 * If only the state of the PROMISC flag changed, 5144 * then just use the 'set promisc mode' command 5145 * instead of reinitializing the entire NIC. Doing 5146 * a full re-init means reloading the firmware and 5147 * waiting for it to start up, which may take a 5148 * second or two. Similarly for ALLMULTI. 5149 */ 5150 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5151 flags = ifp->if_flags ^ sc->bge_if_flags; 5152 if (flags & IFF_PROMISC) 5153 bge_setpromisc(sc); 5154 if (flags & IFF_ALLMULTI) 5155 bge_setmulti(sc); 5156 } else 5157 bge_init_locked(sc); 5158 } else { 5159 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5160 bge_stop(sc); 5161 } 5162 } 5163 sc->bge_if_flags = ifp->if_flags; 5164 BGE_UNLOCK(sc); 5165 error = 0; 5166 break; 5167 case SIOCADDMULTI: 5168 case SIOCDELMULTI: 5169 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5170 BGE_LOCK(sc); 5171 bge_setmulti(sc); 5172 BGE_UNLOCK(sc); 5173 error = 0; 5174 } 5175 break; 5176 case SIOCSIFMEDIA: 5177 case SIOCGIFMEDIA: 5178 if (sc->bge_flags & BGE_FLAG_TBI) { 5179 error = ifmedia_ioctl(ifp, ifr, 5180 &sc->bge_ifmedia, command); 5181 } else { 5182 mii = device_get_softc(sc->bge_miibus); 5183 error = ifmedia_ioctl(ifp, ifr, 5184 &mii->mii_media, command); 5185 } 5186 break; 5187 case SIOCSIFCAP: 5188 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5189 #ifdef DEVICE_POLLING 5190 if (mask & IFCAP_POLLING) { 5191 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5192 error = ether_poll_register(bge_poll, ifp); 5193 if (error) 5194 return (error); 5195 BGE_LOCK(sc); 5196 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5197 BGE_PCIMISCCTL_MASK_PCI_INTR); 5198 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5199 ifp->if_capenable |= IFCAP_POLLING; 5200 BGE_UNLOCK(sc); 5201 } else { 5202 error = ether_poll_deregister(ifp); 5203 /* Enable interrupt even in error case */ 5204 BGE_LOCK(sc); 5205 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5206 BGE_PCIMISCCTL_MASK_PCI_INTR); 5207 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5208 ifp->if_capenable &= ~IFCAP_POLLING; 5209 BGE_UNLOCK(sc); 5210 } 5211 } 5212 #endif 5213 if ((mask & IFCAP_TXCSUM) != 0 && 5214 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5215 ifp->if_capenable ^= IFCAP_TXCSUM; 5216 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5217 ifp->if_hwassist |= sc->bge_csum_features; 5218 else 5219 ifp->if_hwassist &= ~sc->bge_csum_features; 5220 } 5221 5222 if ((mask & IFCAP_RXCSUM) != 0 && 5223 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5224 ifp->if_capenable ^= IFCAP_RXCSUM; 5225 5226 if ((mask & IFCAP_TSO4) != 0 && 5227 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5228 ifp->if_capenable ^= IFCAP_TSO4; 5229 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5230 ifp->if_hwassist |= CSUM_TSO; 5231 else 5232 ifp->if_hwassist &= ~CSUM_TSO; 5233 } 5234 5235 if (mask & IFCAP_VLAN_MTU) { 5236 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5237 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5238 bge_init(sc); 5239 } 5240 5241 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5242 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5243 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5244 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5245 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5246 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5247 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5248 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5249 BGE_LOCK(sc); 5250 bge_setvlan(sc); 5251 BGE_UNLOCK(sc); 5252 } 5253 #ifdef VLAN_CAPABILITIES 5254 VLAN_CAPABILITIES(ifp); 5255 #endif 5256 break; 5257 default: 5258 error = ether_ioctl(ifp, command, data); 5259 break; 5260 } 5261 5262 return (error); 5263 } 5264 5265 static void 5266 bge_watchdog(struct bge_softc *sc) 5267 { 5268 struct ifnet *ifp; 5269 5270 BGE_LOCK_ASSERT(sc); 5271 5272 if (sc->bge_timer == 0 || --sc->bge_timer) 5273 return; 5274 5275 ifp = sc->bge_ifp; 5276 5277 if_printf(ifp, "watchdog timeout -- resetting\n"); 5278 5279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5280 bge_init_locked(sc); 5281 5282 ifp->if_oerrors++; 5283 } 5284 5285 static void 5286 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5287 { 5288 int i; 5289 5290 BGE_CLRBIT(sc, reg, bit); 5291 5292 for (i = 0; i < BGE_TIMEOUT; i++) { 5293 if ((CSR_READ_4(sc, reg) & bit) == 0) 5294 return; 5295 DELAY(100); 5296 } 5297 } 5298 5299 /* 5300 * Stop the adapter and free any mbufs allocated to the 5301 * RX and TX lists. 5302 */ 5303 static void 5304 bge_stop(struct bge_softc *sc) 5305 { 5306 struct ifnet *ifp; 5307 5308 BGE_LOCK_ASSERT(sc); 5309 5310 ifp = sc->bge_ifp; 5311 5312 callout_stop(&sc->bge_stat_ch); 5313 5314 /* Disable host interrupts. */ 5315 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5316 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5317 5318 /* 5319 * Tell firmware we're shutting down. 5320 */ 5321 bge_stop_fw(sc); 5322 bge_sig_pre_reset(sc, BGE_RESET_STOP); 5323 5324 /* 5325 * Disable all of the receiver blocks. 5326 */ 5327 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5328 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5329 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5330 if (BGE_IS_5700_FAMILY(sc)) 5331 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5332 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5333 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5334 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5335 5336 /* 5337 * Disable all of the transmit blocks. 5338 */ 5339 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5340 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5341 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5342 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5343 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5344 if (BGE_IS_5700_FAMILY(sc)) 5345 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5346 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5347 5348 /* 5349 * Shut down all of the memory managers and related 5350 * state machines. 5351 */ 5352 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5353 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5354 if (BGE_IS_5700_FAMILY(sc)) 5355 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5356 5357 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5358 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5359 if (!(BGE_IS_5705_PLUS(sc))) { 5360 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5361 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5362 } 5363 /* Update MAC statistics. */ 5364 if (BGE_IS_5705_PLUS(sc)) 5365 bge_stats_update_regs(sc); 5366 5367 bge_reset(sc); 5368 bge_sig_legacy(sc, BGE_RESET_STOP); 5369 bge_sig_post_reset(sc, BGE_RESET_STOP); 5370 5371 /* 5372 * Keep the ASF firmware running if up. 5373 */ 5374 if (sc->bge_asf_mode & ASF_STACKUP) 5375 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5376 else 5377 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5378 5379 /* Free the RX lists. */ 5380 bge_free_rx_ring_std(sc); 5381 5382 /* Free jumbo RX list. */ 5383 if (BGE_IS_JUMBO_CAPABLE(sc)) 5384 bge_free_rx_ring_jumbo(sc); 5385 5386 /* Free TX buffers. */ 5387 bge_free_tx_ring(sc); 5388 5389 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5390 5391 /* Clear MAC's link state (PHY may still have link UP). */ 5392 if (bootverbose && sc->bge_link) 5393 if_printf(sc->bge_ifp, "link DOWN\n"); 5394 sc->bge_link = 0; 5395 5396 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5397 } 5398 5399 /* 5400 * Stop all chip I/O so that the kernel's probe routines don't 5401 * get confused by errant DMAs when rebooting. 5402 */ 5403 static int 5404 bge_shutdown(device_t dev) 5405 { 5406 struct bge_softc *sc; 5407 5408 sc = device_get_softc(dev); 5409 BGE_LOCK(sc); 5410 bge_stop(sc); 5411 bge_reset(sc); 5412 BGE_UNLOCK(sc); 5413 5414 return (0); 5415 } 5416 5417 static int 5418 bge_suspend(device_t dev) 5419 { 5420 struct bge_softc *sc; 5421 5422 sc = device_get_softc(dev); 5423 BGE_LOCK(sc); 5424 bge_stop(sc); 5425 BGE_UNLOCK(sc); 5426 5427 return (0); 5428 } 5429 5430 static int 5431 bge_resume(device_t dev) 5432 { 5433 struct bge_softc *sc; 5434 struct ifnet *ifp; 5435 5436 sc = device_get_softc(dev); 5437 BGE_LOCK(sc); 5438 ifp = sc->bge_ifp; 5439 if (ifp->if_flags & IFF_UP) { 5440 bge_init_locked(sc); 5441 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5442 bge_start_locked(ifp); 5443 } 5444 BGE_UNLOCK(sc); 5445 5446 return (0); 5447 } 5448 5449 static void 5450 bge_link_upd(struct bge_softc *sc) 5451 { 5452 struct mii_data *mii; 5453 uint32_t link, status; 5454 5455 BGE_LOCK_ASSERT(sc); 5456 5457 /* Clear 'pending link event' flag. */ 5458 sc->bge_link_evt = 0; 5459 5460 /* 5461 * Process link state changes. 5462 * Grrr. The link status word in the status block does 5463 * not work correctly on the BCM5700 rev AX and BX chips, 5464 * according to all available information. Hence, we have 5465 * to enable MII interrupts in order to properly obtain 5466 * async link changes. Unfortunately, this also means that 5467 * we have to read the MAC status register to detect link 5468 * changes, thereby adding an additional register access to 5469 * the interrupt handler. 5470 * 5471 * XXX: perhaps link state detection procedure used for 5472 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5473 */ 5474 5475 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5476 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5477 status = CSR_READ_4(sc, BGE_MAC_STS); 5478 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5479 mii = device_get_softc(sc->bge_miibus); 5480 mii_pollstat(mii); 5481 if (!sc->bge_link && 5482 mii->mii_media_status & IFM_ACTIVE && 5483 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5484 sc->bge_link++; 5485 if (bootverbose) 5486 if_printf(sc->bge_ifp, "link UP\n"); 5487 } else if (sc->bge_link && 5488 (!(mii->mii_media_status & IFM_ACTIVE) || 5489 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5490 sc->bge_link = 0; 5491 if (bootverbose) 5492 if_printf(sc->bge_ifp, "link DOWN\n"); 5493 } 5494 5495 /* Clear the interrupt. */ 5496 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5497 BGE_EVTENB_MI_INTERRUPT); 5498 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 5499 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 5500 BRGPHY_INTRS); 5501 } 5502 return; 5503 } 5504 5505 if (sc->bge_flags & BGE_FLAG_TBI) { 5506 status = CSR_READ_4(sc, BGE_MAC_STS); 5507 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5508 if (!sc->bge_link) { 5509 sc->bge_link++; 5510 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 5511 BGE_CLRBIT(sc, BGE_MAC_MODE, 5512 BGE_MACMODE_TBI_SEND_CFGS); 5513 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5514 if (bootverbose) 5515 if_printf(sc->bge_ifp, "link UP\n"); 5516 if_link_state_change(sc->bge_ifp, 5517 LINK_STATE_UP); 5518 } 5519 } else if (sc->bge_link) { 5520 sc->bge_link = 0; 5521 if (bootverbose) 5522 if_printf(sc->bge_ifp, "link DOWN\n"); 5523 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 5524 } 5525 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 5526 /* 5527 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 5528 * in status word always set. Workaround this bug by reading 5529 * PHY link status directly. 5530 */ 5531 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 5532 5533 if (link != sc->bge_link || 5534 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 5535 mii = device_get_softc(sc->bge_miibus); 5536 mii_pollstat(mii); 5537 if (!sc->bge_link && 5538 mii->mii_media_status & IFM_ACTIVE && 5539 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5540 sc->bge_link++; 5541 if (bootverbose) 5542 if_printf(sc->bge_ifp, "link UP\n"); 5543 } else if (sc->bge_link && 5544 (!(mii->mii_media_status & IFM_ACTIVE) || 5545 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5546 sc->bge_link = 0; 5547 if (bootverbose) 5548 if_printf(sc->bge_ifp, "link DOWN\n"); 5549 } 5550 } 5551 } else { 5552 /* 5553 * For controllers that call mii_tick, we have to poll 5554 * link status. 5555 */ 5556 mii = device_get_softc(sc->bge_miibus); 5557 mii_pollstat(mii); 5558 bge_miibus_statchg(sc->bge_dev); 5559 } 5560 5561 /* Clear the attention. */ 5562 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 5563 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 5564 BGE_MACSTAT_LINK_CHANGED); 5565 } 5566 5567 static void 5568 bge_add_sysctls(struct bge_softc *sc) 5569 { 5570 struct sysctl_ctx_list *ctx; 5571 struct sysctl_oid_list *children; 5572 char tn[32]; 5573 int unit; 5574 5575 ctx = device_get_sysctl_ctx(sc->bge_dev); 5576 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 5577 5578 #ifdef BGE_REGISTER_DEBUG 5579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 5580 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 5581 "Debug Information"); 5582 5583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 5584 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 5585 "Register Read"); 5586 5587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 5588 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 5589 "Memory Read"); 5590 5591 #endif 5592 5593 unit = device_get_unit(sc->bge_dev); 5594 /* 5595 * A common design characteristic for many Broadcom client controllers 5596 * is that they only support a single outstanding DMA read operation 5597 * on the PCIe bus. This means that it will take twice as long to fetch 5598 * a TX frame that is split into header and payload buffers as it does 5599 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 5600 * these controllers, coalescing buffers to reduce the number of memory 5601 * reads is effective way to get maximum performance(about 940Mbps). 5602 * Without collapsing TX buffers the maximum TCP bulk transfer 5603 * performance is about 850Mbps. However forcing coalescing mbufs 5604 * consumes a lot of CPU cycles, so leave it off by default. 5605 */ 5606 sc->bge_forced_collapse = 0; 5607 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 5608 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 5609 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 5610 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 5611 "Number of fragmented TX buffers of a frame allowed before " 5612 "forced collapsing"); 5613 5614 /* 5615 * It seems all Broadcom controllers have a bug that can generate UDP 5616 * datagrams with checksum value 0 when TX UDP checksum offloading is 5617 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 5618 * Even though the probability of generating such UDP datagrams is 5619 * low, I don't want to see FreeBSD boxes to inject such datagrams 5620 * into network so disable UDP checksum offloading by default. Users 5621 * still override this behavior by setting a sysctl variable, 5622 * dev.bge.0.forced_udpcsum. 5623 */ 5624 sc->bge_forced_udpcsum = 0; 5625 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 5626 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 5627 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 5628 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 5629 "Enable UDP checksum offloading even if controller can " 5630 "generate UDP checksum value 0"); 5631 5632 if (BGE_IS_5705_PLUS(sc)) 5633 bge_add_sysctl_stats_regs(sc, ctx, children); 5634 else 5635 bge_add_sysctl_stats(sc, ctx, children); 5636 } 5637 5638 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 5639 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 5640 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 5641 desc) 5642 5643 static void 5644 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5645 struct sysctl_oid_list *parent) 5646 { 5647 struct sysctl_oid *tree; 5648 struct sysctl_oid_list *children, *schildren; 5649 5650 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5651 NULL, "BGE Statistics"); 5652 schildren = children = SYSCTL_CHILDREN(tree); 5653 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 5654 children, COSFramesDroppedDueToFilters, 5655 "FramesDroppedDueToFilters"); 5656 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 5657 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 5658 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 5659 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 5660 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 5661 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 5662 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 5663 children, ifInDiscards, "InputDiscards"); 5664 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 5665 children, ifInErrors, "InputErrors"); 5666 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 5667 children, nicRecvThresholdHit, "RecvThresholdHit"); 5668 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 5669 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 5670 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 5671 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 5672 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 5673 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 5674 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 5675 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 5676 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 5677 children, nicRingStatusUpdate, "RingStatusUpdate"); 5678 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 5679 children, nicInterrupts, "Interrupts"); 5680 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 5681 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 5682 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 5683 children, nicSendThresholdHit, "SendThresholdHit"); 5684 5685 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 5686 NULL, "BGE RX Statistics"); 5687 children = SYSCTL_CHILDREN(tree); 5688 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 5689 children, rxstats.ifHCInOctets, "ifHCInOctets"); 5690 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 5691 children, rxstats.etherStatsFragments, "Fragments"); 5692 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 5693 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 5694 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 5695 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 5696 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 5697 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 5698 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 5699 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 5700 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 5701 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 5702 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 5703 children, rxstats.xoffPauseFramesReceived, 5704 "xoffPauseFramesReceived"); 5705 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5706 children, rxstats.macControlFramesReceived, 5707 "ControlFramesReceived"); 5708 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5709 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5710 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5711 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5712 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5713 children, rxstats.etherStatsJabbers, "Jabbers"); 5714 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5715 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5716 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5717 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5718 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5719 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5720 5721 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5722 NULL, "BGE TX Statistics"); 5723 children = SYSCTL_CHILDREN(tree); 5724 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5725 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 5726 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5727 children, txstats.etherStatsCollisions, "Collisions"); 5728 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5729 children, txstats.outXonSent, "XonSent"); 5730 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5731 children, txstats.outXoffSent, "XoffSent"); 5732 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5733 children, txstats.flowControlDone, "flowControlDone"); 5734 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5735 children, txstats.dot3StatsInternalMacTransmitErrors, 5736 "InternalMacTransmitErrors"); 5737 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5738 children, txstats.dot3StatsSingleCollisionFrames, 5739 "SingleCollisionFrames"); 5740 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5741 children, txstats.dot3StatsMultipleCollisionFrames, 5742 "MultipleCollisionFrames"); 5743 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5744 children, txstats.dot3StatsDeferredTransmissions, 5745 "DeferredTransmissions"); 5746 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5747 children, txstats.dot3StatsExcessiveCollisions, 5748 "ExcessiveCollisions"); 5749 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5750 children, txstats.dot3StatsLateCollisions, 5751 "LateCollisions"); 5752 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5753 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 5754 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5755 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5756 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5757 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5758 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5759 children, txstats.dot3StatsCarrierSenseErrors, 5760 "CarrierSenseErrors"); 5761 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5762 children, txstats.ifOutDiscards, "Discards"); 5763 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5764 children, txstats.ifOutErrors, "Errors"); 5765 } 5766 5767 #undef BGE_SYSCTL_STAT 5768 5769 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 5770 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 5771 5772 static void 5773 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5774 struct sysctl_oid_list *parent) 5775 { 5776 struct sysctl_oid *tree; 5777 struct sysctl_oid_list *child, *schild; 5778 struct bge_mac_stats *stats; 5779 5780 stats = &sc->bge_mac_stats; 5781 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5782 NULL, "BGE Statistics"); 5783 schild = child = SYSCTL_CHILDREN(tree); 5784 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 5785 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 5786 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 5787 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 5788 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 5789 &stats->DmaWriteHighPriQueueFull, 5790 "NIC DMA Write High Priority Queue Full"); 5791 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 5792 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 5793 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 5794 &stats->InputDiscards, "Discarded Input Frames"); 5795 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 5796 &stats->InputErrors, "Input Errors"); 5797 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 5798 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 5799 5800 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 5801 NULL, "BGE RX Statistics"); 5802 child = SYSCTL_CHILDREN(tree); 5803 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 5804 &stats->ifHCInOctets, "Inbound Octets"); 5805 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 5806 &stats->etherStatsFragments, "Fragments"); 5807 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5808 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 5809 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5810 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 5811 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5812 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 5813 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 5814 &stats->dot3StatsFCSErrors, "FCS Errors"); 5815 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 5816 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 5817 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 5818 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 5819 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 5820 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 5821 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 5822 &stats->macControlFramesReceived, "MAC Control Frames Received"); 5823 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 5824 &stats->xoffStateEntered, "XOFF State Entered"); 5825 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 5826 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 5827 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 5828 &stats->etherStatsJabbers, "Jabbers"); 5829 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 5830 &stats->etherStatsUndersizePkts, "Undersized Packets"); 5831 5832 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 5833 NULL, "BGE TX Statistics"); 5834 child = SYSCTL_CHILDREN(tree); 5835 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 5836 &stats->ifHCOutOctets, "Outbound Octets"); 5837 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 5838 &stats->etherStatsCollisions, "TX Collisions"); 5839 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 5840 &stats->outXonSent, "XON Sent"); 5841 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 5842 &stats->outXoffSent, "XOFF Sent"); 5843 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 5844 &stats->dot3StatsInternalMacTransmitErrors, 5845 "Internal MAC TX Errors"); 5846 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 5847 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 5848 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 5849 &stats->dot3StatsMultipleCollisionFrames, 5850 "Multiple Collision Frames"); 5851 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 5852 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 5853 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 5854 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 5855 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 5856 &stats->dot3StatsLateCollisions, "Late Collisions"); 5857 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5858 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 5859 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5860 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 5861 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5862 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 5863 } 5864 5865 #undef BGE_SYSCTL_STAT_ADD64 5866 5867 static int 5868 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5869 { 5870 struct bge_softc *sc; 5871 uint32_t result; 5872 int offset; 5873 5874 sc = (struct bge_softc *)arg1; 5875 offset = arg2; 5876 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5877 offsetof(bge_hostaddr, bge_addr_lo)); 5878 return (sysctl_handle_int(oidp, &result, 0, req)); 5879 } 5880 5881 #ifdef BGE_REGISTER_DEBUG 5882 static int 5883 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5884 { 5885 struct bge_softc *sc; 5886 uint16_t *sbdata; 5887 int error, result, sbsz; 5888 int i, j; 5889 5890 result = -1; 5891 error = sysctl_handle_int(oidp, &result, 0, req); 5892 if (error || (req->newptr == NULL)) 5893 return (error); 5894 5895 if (result == 1) { 5896 sc = (struct bge_softc *)arg1; 5897 5898 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5899 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 5900 sbsz = BGE_STATUS_BLK_SZ; 5901 else 5902 sbsz = 32; 5903 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5904 printf("Status Block:\n"); 5905 BGE_LOCK(sc); 5906 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 5907 sc->bge_cdata.bge_status_map, 5908 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 5909 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 5910 printf("%06x:", i); 5911 for (j = 0; j < 8; j++) 5912 printf(" %04x", sbdata[i++]); 5913 printf("\n"); 5914 } 5915 5916 printf("Registers:\n"); 5917 for (i = 0x800; i < 0xA00; ) { 5918 printf("%06x:", i); 5919 for (j = 0; j < 8; j++) { 5920 printf(" %08x", CSR_READ_4(sc, i)); 5921 i += 4; 5922 } 5923 printf("\n"); 5924 } 5925 BGE_UNLOCK(sc); 5926 5927 printf("Hardware Flags:\n"); 5928 if (BGE_IS_5717_PLUS(sc)) 5929 printf(" - 5717 Plus\n"); 5930 if (BGE_IS_5755_PLUS(sc)) 5931 printf(" - 5755 Plus\n"); 5932 if (BGE_IS_575X_PLUS(sc)) 5933 printf(" - 575X Plus\n"); 5934 if (BGE_IS_5705_PLUS(sc)) 5935 printf(" - 5705 Plus\n"); 5936 if (BGE_IS_5714_FAMILY(sc)) 5937 printf(" - 5714 Family\n"); 5938 if (BGE_IS_5700_FAMILY(sc)) 5939 printf(" - 5700 Family\n"); 5940 if (sc->bge_flags & BGE_FLAG_JUMBO) 5941 printf(" - Supports Jumbo Frames\n"); 5942 if (sc->bge_flags & BGE_FLAG_PCIX) 5943 printf(" - PCI-X Bus\n"); 5944 if (sc->bge_flags & BGE_FLAG_PCIE) 5945 printf(" - PCI Express Bus\n"); 5946 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 5947 printf(" - No 3 LEDs\n"); 5948 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5949 printf(" - RX Alignment Bug\n"); 5950 } 5951 5952 return (error); 5953 } 5954 5955 static int 5956 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5957 { 5958 struct bge_softc *sc; 5959 int error; 5960 uint16_t result; 5961 uint32_t val; 5962 5963 result = -1; 5964 error = sysctl_handle_int(oidp, &result, 0, req); 5965 if (error || (req->newptr == NULL)) 5966 return (error); 5967 5968 if (result < 0x8000) { 5969 sc = (struct bge_softc *)arg1; 5970 val = CSR_READ_4(sc, result); 5971 printf("reg 0x%06X = 0x%08X\n", result, val); 5972 } 5973 5974 return (error); 5975 } 5976 5977 static int 5978 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5979 { 5980 struct bge_softc *sc; 5981 int error; 5982 uint16_t result; 5983 uint32_t val; 5984 5985 result = -1; 5986 error = sysctl_handle_int(oidp, &result, 0, req); 5987 if (error || (req->newptr == NULL)) 5988 return (error); 5989 5990 if (result < 0x8000) { 5991 sc = (struct bge_softc *)arg1; 5992 val = bge_readmem_ind(sc, result); 5993 printf("mem 0x%06X = 0x%08X\n", result, val); 5994 } 5995 5996 return (error); 5997 } 5998 #endif 5999 6000 static int 6001 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6002 { 6003 6004 if (sc->bge_flags & BGE_FLAG_EADDR) 6005 return (1); 6006 6007 #ifdef __sparc64__ 6008 OF_getetheraddr(sc->bge_dev, ether_addr); 6009 return (0); 6010 #endif 6011 return (1); 6012 } 6013 6014 static int 6015 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6016 { 6017 uint32_t mac_addr; 6018 6019 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6020 if ((mac_addr >> 16) == 0x484b) { 6021 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6022 ether_addr[1] = (uint8_t)mac_addr; 6023 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6024 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6025 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6026 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6027 ether_addr[5] = (uint8_t)mac_addr; 6028 return (0); 6029 } 6030 return (1); 6031 } 6032 6033 static int 6034 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6035 { 6036 int mac_offset = BGE_EE_MAC_OFFSET; 6037 6038 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6039 mac_offset = BGE_EE_MAC_OFFSET_5906; 6040 6041 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6042 ETHER_ADDR_LEN)); 6043 } 6044 6045 static int 6046 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6047 { 6048 6049 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6050 return (1); 6051 6052 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6053 ETHER_ADDR_LEN)); 6054 } 6055 6056 static int 6057 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6058 { 6059 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6060 /* NOTE: Order is critical */ 6061 bge_get_eaddr_fw, 6062 bge_get_eaddr_mem, 6063 bge_get_eaddr_nvram, 6064 bge_get_eaddr_eeprom, 6065 NULL 6066 }; 6067 const bge_eaddr_fcn_t *func; 6068 6069 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6070 if ((*func)(sc, eaddr) == 0) 6071 break; 6072 } 6073 return (*func == NULL ? ENXIO : 0); 6074 } 6075