1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } const bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 226 227 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 228 229 { TC_VENDORID, TC_DEVICEID_3C996 }, 230 231 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 232 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 233 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 234 235 { 0, 0 } 236 }; 237 238 static const struct bge_vendor { 239 uint16_t v_id; 240 const char *v_name; 241 } const bge_vendors[] = { 242 { ALTEON_VENDORID, "Alteon" }, 243 { ALTIMA_VENDORID, "Altima" }, 244 { APPLE_VENDORID, "Apple" }, 245 { BCOM_VENDORID, "Broadcom" }, 246 { SK_VENDORID, "SysKonnect" }, 247 { TC_VENDORID, "3Com" }, 248 { FJTSU_VENDORID, "Fujitsu" }, 249 250 { 0, NULL } 251 }; 252 253 static const struct bge_revision { 254 uint32_t br_chipid; 255 const char *br_name; 256 } const bge_revisions[] = { 257 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 258 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 259 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 260 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 261 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 262 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 263 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 264 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 265 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 266 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 267 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 268 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 269 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 270 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 271 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 272 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 273 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 274 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 275 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 276 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 277 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 278 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 279 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 280 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 281 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 282 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 283 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 284 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 285 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 286 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 287 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 288 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 289 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 290 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 291 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 292 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 293 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 294 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 295 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 296 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 297 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 298 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 299 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 300 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 301 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 302 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 303 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 304 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 305 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 306 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 307 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 308 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 309 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 310 /* 5754 and 5787 share the same ASIC ID */ 311 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 312 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 313 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 314 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 315 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 316 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 317 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 318 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 319 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 320 321 { 0, NULL } 322 }; 323 324 /* 325 * Some defaults for major revisions, so that newer steppings 326 * that we don't know about have a shot at working. 327 */ 328 static const struct bge_revision const bge_majorrevs[] = { 329 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 330 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 331 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 332 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 333 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 334 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 335 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 336 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 337 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 338 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 339 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 340 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 341 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 342 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 343 /* 5754 and 5787 share the same ASIC ID */ 344 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 345 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 346 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 347 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 348 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 349 350 { 0, NULL } 351 }; 352 353 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 354 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 355 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 356 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 357 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 358 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 359 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 360 361 const struct bge_revision * bge_lookup_rev(uint32_t); 362 const struct bge_vendor * bge_lookup_vendor(uint16_t); 363 364 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 365 366 static int bge_probe(device_t); 367 static int bge_attach(device_t); 368 static int bge_detach(device_t); 369 static int bge_suspend(device_t); 370 static int bge_resume(device_t); 371 static void bge_release_resources(struct bge_softc *); 372 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 373 static int bge_dma_alloc(struct bge_softc *); 374 static void bge_dma_free(struct bge_softc *); 375 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 376 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 377 378 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 379 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 380 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 381 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 382 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 383 384 static void bge_txeof(struct bge_softc *, uint16_t); 385 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 386 static int bge_rxeof(struct bge_softc *, uint16_t, int); 387 388 static void bge_asf_driver_up (struct bge_softc *); 389 static void bge_tick(void *); 390 static void bge_stats_clear_regs(struct bge_softc *); 391 static void bge_stats_update(struct bge_softc *); 392 static void bge_stats_update_regs(struct bge_softc *); 393 static struct mbuf *bge_check_short_dma(struct mbuf *); 394 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 395 uint16_t *, uint16_t *); 396 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 397 398 static void bge_intr(void *); 399 static int bge_msi_intr(void *); 400 static void bge_intr_task(void *, int); 401 static void bge_start_locked(struct ifnet *); 402 static void bge_start(struct ifnet *); 403 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 404 static void bge_init_locked(struct bge_softc *); 405 static void bge_init(void *); 406 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 407 static void bge_stop(struct bge_softc *); 408 static void bge_watchdog(struct bge_softc *); 409 static int bge_shutdown(device_t); 410 static int bge_ifmedia_upd_locked(struct ifnet *); 411 static int bge_ifmedia_upd(struct ifnet *); 412 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 413 414 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 415 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 416 417 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 418 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 419 420 static void bge_setpromisc(struct bge_softc *); 421 static void bge_setmulti(struct bge_softc *); 422 static void bge_setvlan(struct bge_softc *); 423 424 static __inline void bge_rxreuse_std(struct bge_softc *, int); 425 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 426 static int bge_newbuf_std(struct bge_softc *, int); 427 static int bge_newbuf_jumbo(struct bge_softc *, int); 428 static int bge_init_rx_ring_std(struct bge_softc *); 429 static void bge_free_rx_ring_std(struct bge_softc *); 430 static int bge_init_rx_ring_jumbo(struct bge_softc *); 431 static void bge_free_rx_ring_jumbo(struct bge_softc *); 432 static void bge_free_tx_ring(struct bge_softc *); 433 static int bge_init_tx_ring(struct bge_softc *); 434 435 static int bge_chipinit(struct bge_softc *); 436 static int bge_blockinit(struct bge_softc *); 437 438 static int bge_has_eaddr(struct bge_softc *); 439 static uint32_t bge_readmem_ind(struct bge_softc *, int); 440 static void bge_writemem_ind(struct bge_softc *, int, int); 441 static void bge_writembx(struct bge_softc *, int, int); 442 #ifdef notdef 443 static uint32_t bge_readreg_ind(struct bge_softc *, int); 444 #endif 445 static void bge_writemem_direct(struct bge_softc *, int, int); 446 static void bge_writereg_ind(struct bge_softc *, int, int); 447 448 static int bge_miibus_readreg(device_t, int, int); 449 static int bge_miibus_writereg(device_t, int, int, int); 450 static void bge_miibus_statchg(device_t); 451 #ifdef DEVICE_POLLING 452 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 453 #endif 454 455 #define BGE_RESET_START 1 456 #define BGE_RESET_STOP 2 457 static void bge_sig_post_reset(struct bge_softc *, int); 458 static void bge_sig_legacy(struct bge_softc *, int); 459 static void bge_sig_pre_reset(struct bge_softc *, int); 460 static void bge_stop_fw(struct bge_softc *); 461 static int bge_reset(struct bge_softc *); 462 static void bge_link_upd(struct bge_softc *); 463 464 /* 465 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 466 * leak information to untrusted users. It is also known to cause alignment 467 * traps on certain architectures. 468 */ 469 #ifdef BGE_REGISTER_DEBUG 470 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 471 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 472 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 473 #endif 474 static void bge_add_sysctls(struct bge_softc *); 475 static void bge_add_sysctl_stats_regs(struct bge_softc *, 476 struct sysctl_ctx_list *, struct sysctl_oid_list *); 477 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 478 struct sysctl_oid_list *); 479 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 480 481 static device_method_t bge_methods[] = { 482 /* Device interface */ 483 DEVMETHOD(device_probe, bge_probe), 484 DEVMETHOD(device_attach, bge_attach), 485 DEVMETHOD(device_detach, bge_detach), 486 DEVMETHOD(device_shutdown, bge_shutdown), 487 DEVMETHOD(device_suspend, bge_suspend), 488 DEVMETHOD(device_resume, bge_resume), 489 490 /* bus interface */ 491 DEVMETHOD(bus_print_child, bus_generic_print_child), 492 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 493 494 /* MII interface */ 495 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 496 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 497 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 498 499 { 0, 0 } 500 }; 501 502 static driver_t bge_driver = { 503 "bge", 504 bge_methods, 505 sizeof(struct bge_softc) 506 }; 507 508 static devclass_t bge_devclass; 509 510 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 511 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 512 513 static int bge_allow_asf = 1; 514 515 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 516 517 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 518 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 519 "Allow ASF mode if available"); 520 521 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 522 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 523 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 524 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 525 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 526 527 static int 528 bge_has_eaddr(struct bge_softc *sc) 529 { 530 #ifdef __sparc64__ 531 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 532 device_t dev; 533 uint32_t subvendor; 534 535 dev = sc->bge_dev; 536 537 /* 538 * The on-board BGEs found in sun4u machines aren't fitted with 539 * an EEPROM which means that we have to obtain the MAC address 540 * via OFW and that some tests will always fail. We distinguish 541 * such BGEs by the subvendor ID, which also has to be obtained 542 * from OFW instead of the PCI configuration space as the latter 543 * indicates Broadcom as the subvendor of the netboot interface. 544 * For early Blade 1500 and 2500 we even have to check the OFW 545 * device path as the subvendor ID always defaults to Broadcom 546 * there. 547 */ 548 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 549 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 550 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 551 return (0); 552 memset(buf, 0, sizeof(buf)); 553 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 554 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 555 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 556 return (0); 557 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 558 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 559 return (0); 560 } 561 #endif 562 return (1); 563 } 564 565 static uint32_t 566 bge_readmem_ind(struct bge_softc *sc, int off) 567 { 568 device_t dev; 569 uint32_t val; 570 571 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 572 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 573 return (0); 574 575 dev = sc->bge_dev; 576 577 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 578 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 579 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 580 return (val); 581 } 582 583 static void 584 bge_writemem_ind(struct bge_softc *sc, int off, int val) 585 { 586 device_t dev; 587 588 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 589 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 590 return; 591 592 dev = sc->bge_dev; 593 594 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 595 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 596 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 597 } 598 599 #ifdef notdef 600 static uint32_t 601 bge_readreg_ind(struct bge_softc *sc, int off) 602 { 603 device_t dev; 604 605 dev = sc->bge_dev; 606 607 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 608 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 609 } 610 #endif 611 612 static void 613 bge_writereg_ind(struct bge_softc *sc, int off, int val) 614 { 615 device_t dev; 616 617 dev = sc->bge_dev; 618 619 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 620 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 621 } 622 623 static void 624 bge_writemem_direct(struct bge_softc *sc, int off, int val) 625 { 626 CSR_WRITE_4(sc, off, val); 627 } 628 629 static void 630 bge_writembx(struct bge_softc *sc, int off, int val) 631 { 632 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 633 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 634 635 CSR_WRITE_4(sc, off, val); 636 } 637 638 /* 639 * Map a single buffer address. 640 */ 641 642 static void 643 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 644 { 645 struct bge_dmamap_arg *ctx; 646 647 if (error) 648 return; 649 650 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 651 652 ctx = arg; 653 ctx->bge_busaddr = segs->ds_addr; 654 } 655 656 static uint8_t 657 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 658 { 659 uint32_t access, byte = 0; 660 int i; 661 662 /* Lock. */ 663 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 664 for (i = 0; i < 8000; i++) { 665 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 666 break; 667 DELAY(20); 668 } 669 if (i == 8000) 670 return (1); 671 672 /* Enable access. */ 673 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 674 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 675 676 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 677 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 678 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 679 DELAY(10); 680 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 681 DELAY(10); 682 break; 683 } 684 } 685 686 if (i == BGE_TIMEOUT * 10) { 687 if_printf(sc->bge_ifp, "nvram read timed out\n"); 688 return (1); 689 } 690 691 /* Get result. */ 692 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 693 694 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 695 696 /* Disable access. */ 697 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 698 699 /* Unlock. */ 700 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 701 CSR_READ_4(sc, BGE_NVRAM_SWARB); 702 703 return (0); 704 } 705 706 /* 707 * Read a sequence of bytes from NVRAM. 708 */ 709 static int 710 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 711 { 712 int err = 0, i; 713 uint8_t byte = 0; 714 715 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 716 return (1); 717 718 for (i = 0; i < cnt; i++) { 719 err = bge_nvram_getbyte(sc, off + i, &byte); 720 if (err) 721 break; 722 *(dest + i) = byte; 723 } 724 725 return (err ? 1 : 0); 726 } 727 728 /* 729 * Read a byte of data stored in the EEPROM at address 'addr.' The 730 * BCM570x supports both the traditional bitbang interface and an 731 * auto access interface for reading the EEPROM. We use the auto 732 * access method. 733 */ 734 static uint8_t 735 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 736 { 737 int i; 738 uint32_t byte = 0; 739 740 /* 741 * Enable use of auto EEPROM access so we can avoid 742 * having to use the bitbang method. 743 */ 744 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 745 746 /* Reset the EEPROM, load the clock period. */ 747 CSR_WRITE_4(sc, BGE_EE_ADDR, 748 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 749 DELAY(20); 750 751 /* Issue the read EEPROM command. */ 752 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 753 754 /* Wait for completion */ 755 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 756 DELAY(10); 757 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 758 break; 759 } 760 761 if (i == BGE_TIMEOUT * 10) { 762 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 763 return (1); 764 } 765 766 /* Get result. */ 767 byte = CSR_READ_4(sc, BGE_EE_DATA); 768 769 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 770 771 return (0); 772 } 773 774 /* 775 * Read a sequence of bytes from the EEPROM. 776 */ 777 static int 778 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 779 { 780 int i, error = 0; 781 uint8_t byte = 0; 782 783 for (i = 0; i < cnt; i++) { 784 error = bge_eeprom_getbyte(sc, off + i, &byte); 785 if (error) 786 break; 787 *(dest + i) = byte; 788 } 789 790 return (error ? 1 : 0); 791 } 792 793 static int 794 bge_miibus_readreg(device_t dev, int phy, int reg) 795 { 796 struct bge_softc *sc; 797 uint32_t val; 798 int i; 799 800 sc = device_get_softc(dev); 801 802 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 803 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 804 CSR_WRITE_4(sc, BGE_MI_MODE, 805 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 806 DELAY(80); 807 } 808 809 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 810 BGE_MIPHY(phy) | BGE_MIREG(reg)); 811 812 /* Poll for the PHY register access to complete. */ 813 for (i = 0; i < BGE_TIMEOUT; i++) { 814 DELAY(10); 815 val = CSR_READ_4(sc, BGE_MI_COMM); 816 if ((val & BGE_MICOMM_BUSY) == 0) { 817 DELAY(5); 818 val = CSR_READ_4(sc, BGE_MI_COMM); 819 break; 820 } 821 } 822 823 if (i == BGE_TIMEOUT) { 824 device_printf(sc->bge_dev, 825 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 826 phy, reg, val); 827 val = 0; 828 } 829 830 /* Restore the autopoll bit if necessary. */ 831 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 832 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 833 DELAY(80); 834 } 835 836 if (val & BGE_MICOMM_READFAIL) 837 return (0); 838 839 return (val & 0xFFFF); 840 } 841 842 static int 843 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 844 { 845 struct bge_softc *sc; 846 int i; 847 848 sc = device_get_softc(dev); 849 850 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 851 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 852 return (0); 853 854 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 855 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 856 CSR_WRITE_4(sc, BGE_MI_MODE, 857 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 858 DELAY(80); 859 } 860 861 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 862 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 863 864 for (i = 0; i < BGE_TIMEOUT; i++) { 865 DELAY(10); 866 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 867 DELAY(5); 868 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 869 break; 870 } 871 } 872 873 /* Restore the autopoll bit if necessary. */ 874 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 875 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 876 DELAY(80); 877 } 878 879 if (i == BGE_TIMEOUT) 880 device_printf(sc->bge_dev, 881 "PHY write timed out (phy %d, reg %d, val %d)\n", 882 phy, reg, val); 883 884 return (0); 885 } 886 887 static void 888 bge_miibus_statchg(device_t dev) 889 { 890 struct bge_softc *sc; 891 struct mii_data *mii; 892 sc = device_get_softc(dev); 893 mii = device_get_softc(sc->bge_miibus); 894 895 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 896 (IFM_ACTIVE | IFM_AVALID)) { 897 switch (IFM_SUBTYPE(mii->mii_media_active)) { 898 case IFM_10_T: 899 case IFM_100_TX: 900 sc->bge_link = 1; 901 break; 902 case IFM_1000_T: 903 case IFM_1000_SX: 904 case IFM_2500_SX: 905 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 906 sc->bge_link = 1; 907 else 908 sc->bge_link = 0; 909 break; 910 default: 911 sc->bge_link = 0; 912 break; 913 } 914 } else 915 sc->bge_link = 0; 916 if (sc->bge_link == 0) 917 return; 918 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 919 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 920 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 921 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 922 else 923 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 924 925 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 926 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 927 if ((IFM_OPTIONS(mii->mii_media_active) & 928 IFM_ETH_TXPAUSE) != 0) 929 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 930 else 931 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 932 if ((IFM_OPTIONS(mii->mii_media_active) & 933 IFM_ETH_RXPAUSE) != 0) 934 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 935 else 936 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 937 } else { 938 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 939 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 940 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 941 } 942 } 943 944 /* 945 * Intialize a standard receive ring descriptor. 946 */ 947 static int 948 bge_newbuf_std(struct bge_softc *sc, int i) 949 { 950 struct mbuf *m; 951 struct bge_rx_bd *r; 952 bus_dma_segment_t segs[1]; 953 bus_dmamap_t map; 954 int error, nsegs; 955 956 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 957 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 958 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 959 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 960 if (m == NULL) 961 return (ENOBUFS); 962 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 963 } else { 964 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 965 if (m == NULL) 966 return (ENOBUFS); 967 m->m_len = m->m_pkthdr.len = MCLBYTES; 968 } 969 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 970 m_adj(m, ETHER_ALIGN); 971 972 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 973 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 974 if (error != 0) { 975 m_freem(m); 976 return (error); 977 } 978 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 979 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 980 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 981 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 982 sc->bge_cdata.bge_rx_std_dmamap[i]); 983 } 984 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 985 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 986 sc->bge_cdata.bge_rx_std_sparemap = map; 987 sc->bge_cdata.bge_rx_std_chain[i] = m; 988 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 989 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 990 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 991 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 992 r->bge_flags = BGE_RXBDFLAG_END; 993 r->bge_len = segs[0].ds_len; 994 r->bge_idx = i; 995 996 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 997 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 998 999 return (0); 1000 } 1001 1002 /* 1003 * Initialize a jumbo receive ring descriptor. This allocates 1004 * a jumbo buffer from the pool managed internally by the driver. 1005 */ 1006 static int 1007 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1008 { 1009 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1010 bus_dmamap_t map; 1011 struct bge_extrx_bd *r; 1012 struct mbuf *m; 1013 int error, nsegs; 1014 1015 MGETHDR(m, M_DONTWAIT, MT_DATA); 1016 if (m == NULL) 1017 return (ENOBUFS); 1018 1019 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 1020 if (!(m->m_flags & M_EXT)) { 1021 m_freem(m); 1022 return (ENOBUFS); 1023 } 1024 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1025 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1026 m_adj(m, ETHER_ALIGN); 1027 1028 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1029 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1030 if (error != 0) { 1031 m_freem(m); 1032 return (error); 1033 } 1034 1035 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1036 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1037 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1038 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1039 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1040 } 1041 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1042 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1043 sc->bge_cdata.bge_rx_jumbo_sparemap; 1044 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1045 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1046 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1047 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1048 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1049 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1050 1051 /* 1052 * Fill in the extended RX buffer descriptor. 1053 */ 1054 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1055 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1056 r->bge_idx = i; 1057 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1058 switch (nsegs) { 1059 case 4: 1060 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1061 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1062 r->bge_len3 = segs[3].ds_len; 1063 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1064 case 3: 1065 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1066 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1067 r->bge_len2 = segs[2].ds_len; 1068 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1069 case 2: 1070 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1071 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1072 r->bge_len1 = segs[1].ds_len; 1073 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1074 case 1: 1075 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1076 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1077 r->bge_len0 = segs[0].ds_len; 1078 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1079 break; 1080 default: 1081 panic("%s: %d segments\n", __func__, nsegs); 1082 } 1083 1084 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1085 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1086 1087 return (0); 1088 } 1089 1090 static int 1091 bge_init_rx_ring_std(struct bge_softc *sc) 1092 { 1093 int error, i; 1094 1095 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1096 sc->bge_std = 0; 1097 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1098 if ((error = bge_newbuf_std(sc, i)) != 0) 1099 return (error); 1100 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1101 } 1102 1103 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1104 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1105 1106 sc->bge_std = 0; 1107 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1108 1109 return (0); 1110 } 1111 1112 static void 1113 bge_free_rx_ring_std(struct bge_softc *sc) 1114 { 1115 int i; 1116 1117 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1118 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1119 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1120 sc->bge_cdata.bge_rx_std_dmamap[i], 1121 BUS_DMASYNC_POSTREAD); 1122 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1123 sc->bge_cdata.bge_rx_std_dmamap[i]); 1124 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1125 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1126 } 1127 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1128 sizeof(struct bge_rx_bd)); 1129 } 1130 } 1131 1132 static int 1133 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1134 { 1135 struct bge_rcb *rcb; 1136 int error, i; 1137 1138 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1139 sc->bge_jumbo = 0; 1140 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1141 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1142 return (error); 1143 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1144 } 1145 1146 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1147 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1148 1149 sc->bge_jumbo = 0; 1150 1151 /* Enable the jumbo receive producer ring. */ 1152 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1153 rcb->bge_maxlen_flags = 1154 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1155 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1156 1157 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1158 1159 return (0); 1160 } 1161 1162 static void 1163 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1164 { 1165 int i; 1166 1167 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1168 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1169 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1170 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1171 BUS_DMASYNC_POSTREAD); 1172 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1173 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1174 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1175 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1176 } 1177 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1178 sizeof(struct bge_extrx_bd)); 1179 } 1180 } 1181 1182 static void 1183 bge_free_tx_ring(struct bge_softc *sc) 1184 { 1185 int i; 1186 1187 if (sc->bge_ldata.bge_tx_ring == NULL) 1188 return; 1189 1190 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1191 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1192 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1193 sc->bge_cdata.bge_tx_dmamap[i], 1194 BUS_DMASYNC_POSTWRITE); 1195 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1196 sc->bge_cdata.bge_tx_dmamap[i]); 1197 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1198 sc->bge_cdata.bge_tx_chain[i] = NULL; 1199 } 1200 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1201 sizeof(struct bge_tx_bd)); 1202 } 1203 } 1204 1205 static int 1206 bge_init_tx_ring(struct bge_softc *sc) 1207 { 1208 sc->bge_txcnt = 0; 1209 sc->bge_tx_saved_considx = 0; 1210 1211 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1212 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1213 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1214 1215 /* Initialize transmit producer index for host-memory send ring. */ 1216 sc->bge_tx_prodidx = 0; 1217 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1218 1219 /* 5700 b2 errata */ 1220 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1221 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1222 1223 /* NIC-memory send ring not used; initialize to zero. */ 1224 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1225 /* 5700 b2 errata */ 1226 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1227 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1228 1229 return (0); 1230 } 1231 1232 static void 1233 bge_setpromisc(struct bge_softc *sc) 1234 { 1235 struct ifnet *ifp; 1236 1237 BGE_LOCK_ASSERT(sc); 1238 1239 ifp = sc->bge_ifp; 1240 1241 /* Enable or disable promiscuous mode as needed. */ 1242 if (ifp->if_flags & IFF_PROMISC) 1243 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1244 else 1245 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1246 } 1247 1248 static void 1249 bge_setmulti(struct bge_softc *sc) 1250 { 1251 struct ifnet *ifp; 1252 struct ifmultiaddr *ifma; 1253 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1254 int h, i; 1255 1256 BGE_LOCK_ASSERT(sc); 1257 1258 ifp = sc->bge_ifp; 1259 1260 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1261 for (i = 0; i < 4; i++) 1262 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1263 return; 1264 } 1265 1266 /* First, zot all the existing filters. */ 1267 for (i = 0; i < 4; i++) 1268 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1269 1270 /* Now program new ones. */ 1271 if_maddr_rlock(ifp); 1272 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1273 if (ifma->ifma_addr->sa_family != AF_LINK) 1274 continue; 1275 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1276 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1277 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1278 } 1279 if_maddr_runlock(ifp); 1280 1281 for (i = 0; i < 4; i++) 1282 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1283 } 1284 1285 static void 1286 bge_setvlan(struct bge_softc *sc) 1287 { 1288 struct ifnet *ifp; 1289 1290 BGE_LOCK_ASSERT(sc); 1291 1292 ifp = sc->bge_ifp; 1293 1294 /* Enable or disable VLAN tag stripping as needed. */ 1295 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1296 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1297 else 1298 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1299 } 1300 1301 static void 1302 bge_sig_pre_reset(struct bge_softc *sc, int type) 1303 { 1304 1305 /* 1306 * Some chips don't like this so only do this if ASF is enabled 1307 */ 1308 if (sc->bge_asf_mode) 1309 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1310 1311 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1312 switch (type) { 1313 case BGE_RESET_START: 1314 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1315 break; 1316 case BGE_RESET_STOP: 1317 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1318 break; 1319 } 1320 } 1321 } 1322 1323 static void 1324 bge_sig_post_reset(struct bge_softc *sc, int type) 1325 { 1326 1327 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1328 switch (type) { 1329 case BGE_RESET_START: 1330 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1331 /* START DONE */ 1332 break; 1333 case BGE_RESET_STOP: 1334 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1335 break; 1336 } 1337 } 1338 } 1339 1340 static void 1341 bge_sig_legacy(struct bge_softc *sc, int type) 1342 { 1343 1344 if (sc->bge_asf_mode) { 1345 switch (type) { 1346 case BGE_RESET_START: 1347 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1348 break; 1349 case BGE_RESET_STOP: 1350 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1351 break; 1352 } 1353 } 1354 } 1355 1356 static void 1357 bge_stop_fw(struct bge_softc *sc) 1358 { 1359 int i; 1360 1361 if (sc->bge_asf_mode) { 1362 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1363 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1364 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1365 1366 for (i = 0; i < 100; i++ ) { 1367 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1368 break; 1369 DELAY(10); 1370 } 1371 } 1372 } 1373 1374 /* 1375 * Do endian, PCI and DMA initialization. 1376 */ 1377 static int 1378 bge_chipinit(struct bge_softc *sc) 1379 { 1380 uint32_t dma_rw_ctl, misc_ctl; 1381 uint16_t val; 1382 int i; 1383 1384 /* Set endianness before we access any non-PCI registers. */ 1385 misc_ctl = BGE_INIT; 1386 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1387 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1388 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1389 1390 /* Clear the MAC control register */ 1391 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1392 1393 /* 1394 * Clear the MAC statistics block in the NIC's 1395 * internal memory. 1396 */ 1397 for (i = BGE_STATS_BLOCK; 1398 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1399 BGE_MEMWIN_WRITE(sc, i, 0); 1400 1401 for (i = BGE_STATUS_BLOCK; 1402 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1403 BGE_MEMWIN_WRITE(sc, i, 0); 1404 1405 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1406 /* 1407 * Fix data corruption caused by non-qword write with WB. 1408 * Fix master abort in PCI mode. 1409 * Fix PCI latency timer. 1410 */ 1411 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1412 val |= (1 << 10) | (1 << 12) | (1 << 13); 1413 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1414 } 1415 1416 /* 1417 * Set up the PCI DMA control register. 1418 */ 1419 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1420 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1421 if (sc->bge_flags & BGE_FLAG_PCIE) { 1422 /* Read watermark not used, 128 bytes for write. */ 1423 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1424 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1425 if (BGE_IS_5714_FAMILY(sc)) { 1426 /* 256 bytes for read and write. */ 1427 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1428 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1429 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1430 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1431 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1432 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1433 /* 1434 * In the BCM5703, the DMA read watermark should 1435 * be set to less than or equal to the maximum 1436 * memory read byte count of the PCI-X command 1437 * register. 1438 */ 1439 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1440 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1441 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1442 /* 1536 bytes for read, 384 bytes for write. */ 1443 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1444 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1445 } else { 1446 /* 384 bytes for read and write. */ 1447 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1448 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1449 0x0F; 1450 } 1451 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1452 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1453 uint32_t tmp; 1454 1455 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1456 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1457 if (tmp == 6 || tmp == 7) 1458 dma_rw_ctl |= 1459 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1460 1461 /* Set PCI-X DMA write workaround. */ 1462 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1463 } 1464 } else { 1465 /* Conventional PCI bus: 256 bytes for read and write. */ 1466 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1467 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1468 1469 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1470 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1471 dma_rw_ctl |= 0x0F; 1472 } 1473 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1474 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1475 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1476 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1477 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1478 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1479 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1480 if (BGE_IS_5717_PLUS(sc)) { 1481 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1482 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1483 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1484 } 1485 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1486 1487 /* 1488 * Set up general mode register. 1489 */ 1490 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1491 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1492 BGE_MODECTL_TX_NO_PHDR_CSUM); 1493 1494 /* 1495 * BCM5701 B5 have a bug causing data corruption when using 1496 * 64-bit DMA reads, which can be terminated early and then 1497 * completed later as 32-bit accesses, in combination with 1498 * certain bridges. 1499 */ 1500 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1501 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1502 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1503 1504 /* 1505 * Tell the firmware the driver is running 1506 */ 1507 if (sc->bge_asf_mode & ASF_STACKUP) 1508 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1509 1510 /* 1511 * Disable memory write invalidate. Apparently it is not supported 1512 * properly by these devices. Also ensure that INTx isn't disabled, 1513 * as these chips need it even when using MSI. 1514 */ 1515 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1516 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1517 1518 /* Set the timer prescaler (always 66Mhz) */ 1519 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1520 1521 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1522 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1523 DELAY(40); /* XXX */ 1524 1525 /* Put PHY into ready state */ 1526 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1527 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1528 DELAY(40); 1529 } 1530 1531 return (0); 1532 } 1533 1534 static int 1535 bge_blockinit(struct bge_softc *sc) 1536 { 1537 struct bge_rcb *rcb; 1538 bus_size_t vrcb; 1539 bge_hostaddr taddr; 1540 uint32_t val; 1541 int i, limit; 1542 1543 /* 1544 * Initialize the memory window pointer register so that 1545 * we can access the first 32K of internal NIC RAM. This will 1546 * allow us to set up the TX send ring RCBs and the RX return 1547 * ring RCBs, plus other things which live in NIC memory. 1548 */ 1549 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1550 1551 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1552 1553 if (!(BGE_IS_5705_PLUS(sc))) { 1554 /* Configure mbuf memory pool */ 1555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1556 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1557 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1558 else 1559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1560 1561 /* Configure DMA resource pool */ 1562 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1563 BGE_DMA_DESCRIPTORS); 1564 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1565 } 1566 1567 /* Configure mbuf pool watermarks */ 1568 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1569 sc->bge_asicrev == BGE_ASICREV_BCM57765) { 1570 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1571 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1572 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1573 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1574 } else { 1575 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1576 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1577 } 1578 } else if (!BGE_IS_5705_PLUS(sc)) { 1579 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1580 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1581 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1582 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1583 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1584 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1585 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1586 } else { 1587 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1588 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1589 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1590 } 1591 1592 /* Configure DMA resource watermarks */ 1593 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1594 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1595 1596 /* Enable buffer manager */ 1597 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1598 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1599 1600 /* Poll for buffer manager start indication */ 1601 for (i = 0; i < BGE_TIMEOUT; i++) { 1602 DELAY(10); 1603 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1604 break; 1605 } 1606 1607 if (i == BGE_TIMEOUT) { 1608 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 1609 return (ENXIO); 1610 } 1611 1612 /* Enable flow-through queues */ 1613 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1614 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1615 1616 /* Wait until queue initialization is complete */ 1617 for (i = 0; i < BGE_TIMEOUT; i++) { 1618 DELAY(10); 1619 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1620 break; 1621 } 1622 1623 if (i == BGE_TIMEOUT) { 1624 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1625 return (ENXIO); 1626 } 1627 1628 /* 1629 * Summary of rings supported by the controller: 1630 * 1631 * Standard Receive Producer Ring 1632 * - This ring is used to feed receive buffers for "standard" 1633 * sized frames (typically 1536 bytes) to the controller. 1634 * 1635 * Jumbo Receive Producer Ring 1636 * - This ring is used to feed receive buffers for jumbo sized 1637 * frames (i.e. anything bigger than the "standard" frames) 1638 * to the controller. 1639 * 1640 * Mini Receive Producer Ring 1641 * - This ring is used to feed receive buffers for "mini" 1642 * sized frames to the controller. 1643 * - This feature required external memory for the controller 1644 * but was never used in a production system. Should always 1645 * be disabled. 1646 * 1647 * Receive Return Ring 1648 * - After the controller has placed an incoming frame into a 1649 * receive buffer that buffer is moved into a receive return 1650 * ring. The driver is then responsible to passing the 1651 * buffer up to the stack. Many versions of the controller 1652 * support multiple RR rings. 1653 * 1654 * Send Ring 1655 * - This ring is used for outgoing frames. Many versions of 1656 * the controller support multiple send rings. 1657 */ 1658 1659 /* Initialize the standard receive producer ring control block. */ 1660 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1661 rcb->bge_hostaddr.bge_addr_lo = 1662 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1663 rcb->bge_hostaddr.bge_addr_hi = 1664 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1665 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1666 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1667 if (BGE_IS_5717_PLUS(sc)) { 1668 /* 1669 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1670 * Bits 15-2 : Maximum RX frame size 1671 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1672 * Bit 0 : Reserved 1673 */ 1674 rcb->bge_maxlen_flags = 1675 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 1676 } else if (BGE_IS_5705_PLUS(sc)) { 1677 /* 1678 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1679 * Bits 15-2 : Reserved (should be 0) 1680 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1681 * Bit 0 : Reserved 1682 */ 1683 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1684 } else { 1685 /* 1686 * Ring size is always XXX entries 1687 * Bits 31-16: Maximum RX frame size 1688 * Bits 15-2 : Reserved (should be 0) 1689 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1690 * Bit 0 : Reserved 1691 */ 1692 rcb->bge_maxlen_flags = 1693 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1694 } 1695 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 1696 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1697 else 1698 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1699 /* Write the standard receive producer ring control block. */ 1700 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1701 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1702 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1703 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1704 1705 /* Reset the standard receive producer ring producer index. */ 1706 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1707 1708 /* 1709 * Initialize the jumbo RX producer ring control 1710 * block. We set the 'ring disabled' bit in the 1711 * flags field until we're actually ready to start 1712 * using this ring (i.e. once we set the MTU 1713 * high enough to require it). 1714 */ 1715 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1716 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1717 /* Get the jumbo receive producer ring RCB parameters. */ 1718 rcb->bge_hostaddr.bge_addr_lo = 1719 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1720 rcb->bge_hostaddr.bge_addr_hi = 1721 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1722 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1723 sc->bge_cdata.bge_rx_jumbo_ring_map, 1724 BUS_DMASYNC_PREREAD); 1725 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1726 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1727 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 1728 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1729 else 1730 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1731 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1732 rcb->bge_hostaddr.bge_addr_hi); 1733 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1734 rcb->bge_hostaddr.bge_addr_lo); 1735 /* Program the jumbo receive producer ring RCB parameters. */ 1736 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1737 rcb->bge_maxlen_flags); 1738 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1739 /* Reset the jumbo receive producer ring producer index. */ 1740 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1741 } 1742 1743 /* Disable the mini receive producer ring RCB. */ 1744 if (BGE_IS_5700_FAMILY(sc)) { 1745 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1746 rcb->bge_maxlen_flags = 1747 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1748 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1749 rcb->bge_maxlen_flags); 1750 /* Reset the mini receive producer ring producer index. */ 1751 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1752 } 1753 1754 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1755 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1756 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1757 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1758 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 1759 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1760 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1761 } 1762 /* 1763 * The BD ring replenish thresholds control how often the 1764 * hardware fetches new BD's from the producer rings in host 1765 * memory. Setting the value too low on a busy system can 1766 * starve the hardware and recue the throughpout. 1767 * 1768 * Set the BD ring replentish thresholds. The recommended 1769 * values are 1/8th the number of descriptors allocated to 1770 * each ring. 1771 * XXX The 5754 requires a lower threshold, so it might be a 1772 * requirement of all 575x family chips. The Linux driver sets 1773 * the lower threshold for all 5705 family chips as well, but there 1774 * are reports that it might not need to be so strict. 1775 * 1776 * XXX Linux does some extra fiddling here for the 5906 parts as 1777 * well. 1778 */ 1779 if (BGE_IS_5705_PLUS(sc)) 1780 val = 8; 1781 else 1782 val = BGE_STD_RX_RING_CNT / 8; 1783 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1784 if (BGE_IS_JUMBO_CAPABLE(sc)) 1785 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1786 BGE_JUMBO_RX_RING_CNT/8); 1787 if (BGE_IS_5717_PLUS(sc)) { 1788 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1789 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1790 } 1791 1792 /* 1793 * Disable all send rings by setting the 'ring disabled' bit 1794 * in the flags field of all the TX send ring control blocks, 1795 * located in NIC memory. 1796 */ 1797 if (!BGE_IS_5705_PLUS(sc)) 1798 /* 5700 to 5704 had 16 send rings. */ 1799 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1800 else 1801 limit = 1; 1802 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1803 for (i = 0; i < limit; i++) { 1804 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1805 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1806 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1807 vrcb += sizeof(struct bge_rcb); 1808 } 1809 1810 /* Configure send ring RCB 0 (we use only the first ring) */ 1811 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1812 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1813 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1814 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1815 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 1816 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 1817 else 1818 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1819 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1820 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1821 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1822 1823 /* 1824 * Disable all receive return rings by setting the 1825 * 'ring diabled' bit in the flags field of all the receive 1826 * return ring control blocks, located in NIC memory. 1827 */ 1828 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) { 1829 /* Should be 17, use 16 until we get an SRAM map. */ 1830 limit = 16; 1831 } else if (!BGE_IS_5705_PLUS(sc)) 1832 limit = BGE_RX_RINGS_MAX; 1833 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1834 sc->bge_asicrev == BGE_ASICREV_BCM57765) 1835 limit = 4; 1836 else 1837 limit = 1; 1838 /* Disable all receive return rings. */ 1839 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1840 for (i = 0; i < limit; i++) { 1841 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1842 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1843 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1844 BGE_RCB_FLAG_RING_DISABLED); 1845 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1846 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1847 (i * (sizeof(uint64_t))), 0); 1848 vrcb += sizeof(struct bge_rcb); 1849 } 1850 1851 /* 1852 * Set up receive return ring 0. Note that the NIC address 1853 * for RX return rings is 0x0. The return rings live entirely 1854 * within the host, so the nicaddr field in the RCB isn't used. 1855 */ 1856 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1857 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1858 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1859 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1860 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1861 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1862 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1863 1864 /* Set random backoff seed for TX */ 1865 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1866 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1867 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1868 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1869 BGE_TX_BACKOFF_SEED_MASK); 1870 1871 /* Set inter-packet gap */ 1872 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1873 1874 /* 1875 * Specify which ring to use for packets that don't match 1876 * any RX rules. 1877 */ 1878 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1879 1880 /* 1881 * Configure number of RX lists. One interrupt distribution 1882 * list, sixteen active lists, one bad frames class. 1883 */ 1884 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1885 1886 /* Inialize RX list placement stats mask. */ 1887 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1888 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1889 1890 /* Disable host coalescing until we get it set up */ 1891 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1892 1893 /* Poll to make sure it's shut down. */ 1894 for (i = 0; i < BGE_TIMEOUT; i++) { 1895 DELAY(10); 1896 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1897 break; 1898 } 1899 1900 if (i == BGE_TIMEOUT) { 1901 device_printf(sc->bge_dev, 1902 "host coalescing engine failed to idle\n"); 1903 return (ENXIO); 1904 } 1905 1906 /* Set up host coalescing defaults */ 1907 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1908 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1909 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1910 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1911 if (!(BGE_IS_5705_PLUS(sc))) { 1912 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1913 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1914 } 1915 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1916 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1917 1918 /* Set up address of statistics block */ 1919 if (!(BGE_IS_5705_PLUS(sc))) { 1920 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1921 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1922 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1923 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1924 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1925 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1926 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1927 } 1928 1929 /* Set up address of status block */ 1930 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1931 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1932 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1933 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1934 1935 /* Set up status block size. */ 1936 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1937 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1938 val = BGE_STATBLKSZ_FULL; 1939 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1940 } else { 1941 val = BGE_STATBLKSZ_32BYTE; 1942 bzero(sc->bge_ldata.bge_status_block, 32); 1943 } 1944 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1945 sc->bge_cdata.bge_status_map, 1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1947 1948 /* Turn on host coalescing state machine */ 1949 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1950 1951 /* Turn on RX BD completion state machine and enable attentions */ 1952 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1953 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1954 1955 /* Turn on RX list placement state machine */ 1956 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1957 1958 /* Turn on RX list selector state machine. */ 1959 if (!(BGE_IS_5705_PLUS(sc))) 1960 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1961 1962 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1963 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1964 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1965 BGE_MACMODE_FRMHDR_DMA_ENB; 1966 1967 if (sc->bge_flags & BGE_FLAG_TBI) 1968 val |= BGE_PORTMODE_TBI; 1969 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1970 val |= BGE_PORTMODE_GMII; 1971 else 1972 val |= BGE_PORTMODE_MII; 1973 1974 /* Turn on DMA, clear stats */ 1975 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1976 1977 /* Set misc. local control, enable interrupts on attentions */ 1978 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1979 1980 #ifdef notdef 1981 /* Assert GPIO pins for PHY reset */ 1982 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1983 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1984 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1985 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1986 #endif 1987 1988 /* Turn on DMA completion state machine */ 1989 if (!(BGE_IS_5705_PLUS(sc))) 1990 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1991 1992 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1993 1994 /* Enable host coalescing bug fix. */ 1995 if (BGE_IS_5755_PLUS(sc)) 1996 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1997 1998 /* Request larger DMA burst size to get better performance. */ 1999 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2000 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2001 2002 /* Turn on write DMA state machine */ 2003 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2004 DELAY(40); 2005 2006 /* Turn on read DMA state machine */ 2007 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2008 2009 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2010 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2011 2012 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2013 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2014 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2015 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2016 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2017 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2018 if (sc->bge_flags & BGE_FLAG_PCIE) 2019 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2020 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2021 val |= BGE_RDMAMODE_TSO4_ENABLE; 2022 if (sc->bge_flags & BGE_FLAG_TSO3 || 2023 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2024 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2025 val |= BGE_RDMAMODE_TSO6_ENABLE; 2026 } 2027 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2028 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2029 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2030 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2031 BGE_IS_5717_PLUS(sc)) { 2032 /* 2033 * Enable fix for read DMA FIFO overruns. 2034 * The fix is to limit the number of RX BDs 2035 * the hardware would fetch at a fime. 2036 */ 2037 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 2038 CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) | 2039 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2040 } 2041 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2042 DELAY(40); 2043 2044 /* Turn on RX data completion state machine */ 2045 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2046 2047 /* Turn on RX BD initiator state machine */ 2048 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2049 2050 /* Turn on RX data and RX BD initiator state machine */ 2051 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2052 2053 /* Turn on Mbuf cluster free state machine */ 2054 if (!(BGE_IS_5705_PLUS(sc))) 2055 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2056 2057 /* Turn on send BD completion state machine */ 2058 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2059 2060 /* Turn on send data completion state machine */ 2061 val = BGE_SDCMODE_ENABLE; 2062 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2063 val |= BGE_SDCMODE_CDELAY; 2064 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2065 2066 /* Turn on send data initiator state machine */ 2067 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2068 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2069 BGE_SDIMODE_HW_LSO_PRE_DMA); 2070 else 2071 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2072 2073 /* Turn on send BD initiator state machine */ 2074 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2075 2076 /* Turn on send BD selector state machine */ 2077 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2078 2079 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2080 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2081 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2082 2083 /* ack/clear link change events */ 2084 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2085 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2086 BGE_MACSTAT_LINK_CHANGED); 2087 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2088 2089 /* 2090 * Enable attention when the link has changed state for 2091 * devices that use auto polling. 2092 */ 2093 if (sc->bge_flags & BGE_FLAG_TBI) { 2094 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2095 } else { 2096 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2097 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2098 DELAY(80); 2099 } 2100 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2101 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2102 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2103 BGE_EVTENB_MI_INTERRUPT); 2104 } 2105 2106 /* 2107 * Clear any pending link state attention. 2108 * Otherwise some link state change events may be lost until attention 2109 * is cleared by bge_intr() -> bge_link_upd() sequence. 2110 * It's not necessary on newer BCM chips - perhaps enabling link 2111 * state change attentions implies clearing pending attention. 2112 */ 2113 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2114 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2115 BGE_MACSTAT_LINK_CHANGED); 2116 2117 /* Enable link state change attentions. */ 2118 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2119 2120 return (0); 2121 } 2122 2123 const struct bge_revision * 2124 bge_lookup_rev(uint32_t chipid) 2125 { 2126 const struct bge_revision *br; 2127 2128 for (br = bge_revisions; br->br_name != NULL; br++) { 2129 if (br->br_chipid == chipid) 2130 return (br); 2131 } 2132 2133 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2134 if (br->br_chipid == BGE_ASICREV(chipid)) 2135 return (br); 2136 } 2137 2138 return (NULL); 2139 } 2140 2141 const struct bge_vendor * 2142 bge_lookup_vendor(uint16_t vid) 2143 { 2144 const struct bge_vendor *v; 2145 2146 for (v = bge_vendors; v->v_name != NULL; v++) 2147 if (v->v_id == vid) 2148 return (v); 2149 2150 panic("%s: unknown vendor %d", __func__, vid); 2151 return (NULL); 2152 } 2153 2154 /* 2155 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2156 * against our list and return its name if we find a match. 2157 * 2158 * Note that since the Broadcom controller contains VPD support, we 2159 * try to get the device name string from the controller itself instead 2160 * of the compiled-in string. It guarantees we'll always announce the 2161 * right product name. We fall back to the compiled-in string when 2162 * VPD is unavailable or corrupt. 2163 */ 2164 static int 2165 bge_probe(device_t dev) 2166 { 2167 char buf[96]; 2168 char model[64]; 2169 const struct bge_revision *br; 2170 const char *pname; 2171 struct bge_softc *sc = device_get_softc(dev); 2172 const struct bge_type *t = bge_devs; 2173 const struct bge_vendor *v; 2174 uint32_t id; 2175 uint16_t did, vid; 2176 2177 sc->bge_dev = dev; 2178 vid = pci_get_vendor(dev); 2179 did = pci_get_device(dev); 2180 while(t->bge_vid != 0) { 2181 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2182 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2183 BGE_PCIMISCCTL_ASICREV_SHIFT; 2184 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2185 /* 2186 * Find the ASCI revision. Different chips 2187 * use different registers. 2188 */ 2189 switch (pci_get_device(dev)) { 2190 case BCOM_DEVICEID_BCM5717: 2191 case BCOM_DEVICEID_BCM5718: 2192 id = pci_read_config(dev, 2193 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2194 break; 2195 case BCOM_DEVICEID_BCM57761: 2196 case BCOM_DEVICEID_BCM57765: 2197 case BCOM_DEVICEID_BCM57781: 2198 case BCOM_DEVICEID_BCM57785: 2199 case BCOM_DEVICEID_BCM57791: 2200 case BCOM_DEVICEID_BCM57795: 2201 id = pci_read_config(dev, 2202 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2203 break; 2204 default: 2205 id = pci_read_config(dev, 2206 BGE_PCI_PRODID_ASICREV, 4); 2207 } 2208 } 2209 br = bge_lookup_rev(id); 2210 v = bge_lookup_vendor(vid); 2211 if (bge_has_eaddr(sc) && 2212 pci_get_vpd_ident(dev, &pname) == 0) 2213 snprintf(model, 64, "%s", pname); 2214 else 2215 snprintf(model, 64, "%s %s", v->v_name, 2216 br != NULL ? br->br_name : 2217 "NetXtreme Ethernet Controller"); 2218 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2219 br != NULL ? "" : "unknown ", id); 2220 device_set_desc_copy(dev, buf); 2221 return (0); 2222 } 2223 t++; 2224 } 2225 2226 return (ENXIO); 2227 } 2228 2229 static void 2230 bge_dma_free(struct bge_softc *sc) 2231 { 2232 int i; 2233 2234 /* Destroy DMA maps for RX buffers. */ 2235 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2236 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2237 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2238 sc->bge_cdata.bge_rx_std_dmamap[i]); 2239 } 2240 if (sc->bge_cdata.bge_rx_std_sparemap) 2241 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2242 sc->bge_cdata.bge_rx_std_sparemap); 2243 2244 /* Destroy DMA maps for jumbo RX buffers. */ 2245 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2246 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2247 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2248 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2249 } 2250 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2251 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2252 sc->bge_cdata.bge_rx_jumbo_sparemap); 2253 2254 /* Destroy DMA maps for TX buffers. */ 2255 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2256 if (sc->bge_cdata.bge_tx_dmamap[i]) 2257 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2258 sc->bge_cdata.bge_tx_dmamap[i]); 2259 } 2260 2261 if (sc->bge_cdata.bge_rx_mtag) 2262 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2263 if (sc->bge_cdata.bge_tx_mtag) 2264 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2265 2266 2267 /* Destroy standard RX ring. */ 2268 if (sc->bge_cdata.bge_rx_std_ring_map) 2269 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2270 sc->bge_cdata.bge_rx_std_ring_map); 2271 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2272 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2273 sc->bge_ldata.bge_rx_std_ring, 2274 sc->bge_cdata.bge_rx_std_ring_map); 2275 2276 if (sc->bge_cdata.bge_rx_std_ring_tag) 2277 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2278 2279 /* Destroy jumbo RX ring. */ 2280 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2281 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2282 sc->bge_cdata.bge_rx_jumbo_ring_map); 2283 2284 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2285 sc->bge_ldata.bge_rx_jumbo_ring) 2286 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2287 sc->bge_ldata.bge_rx_jumbo_ring, 2288 sc->bge_cdata.bge_rx_jumbo_ring_map); 2289 2290 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2291 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2292 2293 /* Destroy RX return ring. */ 2294 if (sc->bge_cdata.bge_rx_return_ring_map) 2295 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2296 sc->bge_cdata.bge_rx_return_ring_map); 2297 2298 if (sc->bge_cdata.bge_rx_return_ring_map && 2299 sc->bge_ldata.bge_rx_return_ring) 2300 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2301 sc->bge_ldata.bge_rx_return_ring, 2302 sc->bge_cdata.bge_rx_return_ring_map); 2303 2304 if (sc->bge_cdata.bge_rx_return_ring_tag) 2305 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2306 2307 /* Destroy TX ring. */ 2308 if (sc->bge_cdata.bge_tx_ring_map) 2309 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2310 sc->bge_cdata.bge_tx_ring_map); 2311 2312 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2313 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2314 sc->bge_ldata.bge_tx_ring, 2315 sc->bge_cdata.bge_tx_ring_map); 2316 2317 if (sc->bge_cdata.bge_tx_ring_tag) 2318 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2319 2320 /* Destroy status block. */ 2321 if (sc->bge_cdata.bge_status_map) 2322 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2323 sc->bge_cdata.bge_status_map); 2324 2325 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2326 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2327 sc->bge_ldata.bge_status_block, 2328 sc->bge_cdata.bge_status_map); 2329 2330 if (sc->bge_cdata.bge_status_tag) 2331 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2332 2333 /* Destroy statistics block. */ 2334 if (sc->bge_cdata.bge_stats_map) 2335 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2336 sc->bge_cdata.bge_stats_map); 2337 2338 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2339 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2340 sc->bge_ldata.bge_stats, 2341 sc->bge_cdata.bge_stats_map); 2342 2343 if (sc->bge_cdata.bge_stats_tag) 2344 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2345 2346 if (sc->bge_cdata.bge_buffer_tag) 2347 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2348 2349 /* Destroy the parent tag. */ 2350 if (sc->bge_cdata.bge_parent_tag) 2351 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2352 } 2353 2354 static int 2355 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2356 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2357 bus_addr_t *paddr, const char *msg) 2358 { 2359 struct bge_dmamap_arg ctx; 2360 bus_addr_t lowaddr; 2361 bus_size_t ring_end; 2362 int error; 2363 2364 lowaddr = BUS_SPACE_MAXADDR; 2365 again: 2366 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2367 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2368 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2369 if (error != 0) { 2370 device_printf(sc->bge_dev, 2371 "could not create %s dma tag\n", msg); 2372 return (ENOMEM); 2373 } 2374 /* Allocate DMA'able memory for ring. */ 2375 error = bus_dmamem_alloc(*tag, (void **)ring, 2376 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2377 if (error != 0) { 2378 device_printf(sc->bge_dev, 2379 "could not allocate DMA'able memory for %s\n", msg); 2380 return (ENOMEM); 2381 } 2382 /* Load the address of the ring. */ 2383 ctx.bge_busaddr = 0; 2384 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2385 &ctx, BUS_DMA_NOWAIT); 2386 if (error != 0) { 2387 device_printf(sc->bge_dev, 2388 "could not load DMA'able memory for %s\n", msg); 2389 return (ENOMEM); 2390 } 2391 *paddr = ctx.bge_busaddr; 2392 ring_end = *paddr + maxsize; 2393 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2394 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2395 /* 2396 * 4GB boundary crossed. Limit maximum allowable DMA 2397 * address space to 32bit and try again. 2398 */ 2399 bus_dmamap_unload(*tag, *map); 2400 bus_dmamem_free(*tag, *ring, *map); 2401 bus_dma_tag_destroy(*tag); 2402 if (bootverbose) 2403 device_printf(sc->bge_dev, "4GB boundary crossed, " 2404 "limit DMA address space to 32bit for %s\n", msg); 2405 *ring = NULL; 2406 *tag = NULL; 2407 *map = NULL; 2408 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2409 goto again; 2410 } 2411 return (0); 2412 } 2413 2414 static int 2415 bge_dma_alloc(struct bge_softc *sc) 2416 { 2417 bus_addr_t lowaddr; 2418 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2419 int i, error; 2420 2421 lowaddr = BUS_SPACE_MAXADDR; 2422 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2423 lowaddr = BGE_DMA_MAXADDR; 2424 /* 2425 * Allocate the parent bus DMA tag appropriate for PCI. 2426 */ 2427 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2428 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2429 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2430 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2431 if (error != 0) { 2432 device_printf(sc->bge_dev, 2433 "could not allocate parent dma tag\n"); 2434 return (ENOMEM); 2435 } 2436 2437 /* Create tag for standard RX ring. */ 2438 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2439 &sc->bge_cdata.bge_rx_std_ring_tag, 2440 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2441 &sc->bge_cdata.bge_rx_std_ring_map, 2442 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2443 if (error) 2444 return (error); 2445 2446 /* Create tag for RX return ring. */ 2447 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2448 &sc->bge_cdata.bge_rx_return_ring_tag, 2449 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2450 &sc->bge_cdata.bge_rx_return_ring_map, 2451 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2452 if (error) 2453 return (error); 2454 2455 /* Create tag for TX ring. */ 2456 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2457 &sc->bge_cdata.bge_tx_ring_tag, 2458 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2459 &sc->bge_cdata.bge_tx_ring_map, 2460 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2461 if (error) 2462 return (error); 2463 2464 /* 2465 * Create tag for status block. 2466 * Because we only use single Tx/Rx/Rx return ring, use 2467 * minimum status block size except BCM5700 AX/BX which 2468 * seems to want to see full status block size regardless 2469 * of configured number of ring. 2470 */ 2471 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2472 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2473 sbsz = BGE_STATUS_BLK_SZ; 2474 else 2475 sbsz = 32; 2476 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2477 &sc->bge_cdata.bge_status_tag, 2478 (uint8_t **)&sc->bge_ldata.bge_status_block, 2479 &sc->bge_cdata.bge_status_map, 2480 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2481 if (error) 2482 return (error); 2483 2484 /* Create tag for statistics block. */ 2485 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2486 &sc->bge_cdata.bge_stats_tag, 2487 (uint8_t **)&sc->bge_ldata.bge_stats, 2488 &sc->bge_cdata.bge_stats_map, 2489 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2490 if (error) 2491 return (error); 2492 2493 /* Create tag for jumbo RX ring. */ 2494 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2495 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2496 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2497 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2498 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2499 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2500 if (error) 2501 return (error); 2502 } 2503 2504 /* Create parent tag for buffers. */ 2505 boundary = 0; 2506 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2507 boundary = BGE_DMA_BNDRY; 2508 /* 2509 * XXX 2510 * watchdog timeout issue was observed on BCM5704 which 2511 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2512 * Limiting DMA address space to 32bits seems to address 2513 * it. 2514 */ 2515 if (sc->bge_flags & BGE_FLAG_PCIX) 2516 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2517 } 2518 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2519 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 2520 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2521 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 2522 if (error != 0) { 2523 device_printf(sc->bge_dev, 2524 "could not allocate buffer dma tag\n"); 2525 return (ENOMEM); 2526 } 2527 /* Create tag for Tx mbufs. */ 2528 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2529 txsegsz = BGE_TSOSEG_SZ; 2530 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2531 } else { 2532 txsegsz = MCLBYTES; 2533 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2534 } 2535 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2536 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2537 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2538 &sc->bge_cdata.bge_tx_mtag); 2539 2540 if (error) { 2541 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2542 return (ENOMEM); 2543 } 2544 2545 /* Create tag for Rx mbufs. */ 2546 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 2547 rxmaxsegsz = MJUM9BYTES; 2548 else 2549 rxmaxsegsz = MCLBYTES; 2550 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2551 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 2552 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2553 2554 if (error) { 2555 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2556 return (ENOMEM); 2557 } 2558 2559 /* Create DMA maps for RX buffers. */ 2560 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2561 &sc->bge_cdata.bge_rx_std_sparemap); 2562 if (error) { 2563 device_printf(sc->bge_dev, 2564 "can't create spare DMA map for RX\n"); 2565 return (ENOMEM); 2566 } 2567 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2568 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2569 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2570 if (error) { 2571 device_printf(sc->bge_dev, 2572 "can't create DMA map for RX\n"); 2573 return (ENOMEM); 2574 } 2575 } 2576 2577 /* Create DMA maps for TX buffers. */ 2578 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2579 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2580 &sc->bge_cdata.bge_tx_dmamap[i]); 2581 if (error) { 2582 device_printf(sc->bge_dev, 2583 "can't create DMA map for TX\n"); 2584 return (ENOMEM); 2585 } 2586 } 2587 2588 /* Create tags for jumbo RX buffers. */ 2589 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2590 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2591 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2592 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2593 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2594 if (error) { 2595 device_printf(sc->bge_dev, 2596 "could not allocate jumbo dma tag\n"); 2597 return (ENOMEM); 2598 } 2599 /* Create DMA maps for jumbo RX buffers. */ 2600 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2601 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2602 if (error) { 2603 device_printf(sc->bge_dev, 2604 "can't create spare DMA map for jumbo RX\n"); 2605 return (ENOMEM); 2606 } 2607 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2608 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2609 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2610 if (error) { 2611 device_printf(sc->bge_dev, 2612 "can't create DMA map for jumbo RX\n"); 2613 return (ENOMEM); 2614 } 2615 } 2616 } 2617 2618 return (0); 2619 } 2620 2621 /* 2622 * Return true if this device has more than one port. 2623 */ 2624 static int 2625 bge_has_multiple_ports(struct bge_softc *sc) 2626 { 2627 device_t dev = sc->bge_dev; 2628 u_int b, d, f, fscan, s; 2629 2630 d = pci_get_domain(dev); 2631 b = pci_get_bus(dev); 2632 s = pci_get_slot(dev); 2633 f = pci_get_function(dev); 2634 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2635 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2636 return (1); 2637 return (0); 2638 } 2639 2640 /* 2641 * Return true if MSI can be used with this device. 2642 */ 2643 static int 2644 bge_can_use_msi(struct bge_softc *sc) 2645 { 2646 int can_use_msi = 0; 2647 2648 /* Disable MSI for polling(4). */ 2649 #ifdef DEVICE_POLLING 2650 return (0); 2651 #endif 2652 switch (sc->bge_asicrev) { 2653 case BGE_ASICREV_BCM5714_A0: 2654 case BGE_ASICREV_BCM5714: 2655 /* 2656 * Apparently, MSI doesn't work when these chips are 2657 * configured in single-port mode. 2658 */ 2659 if (bge_has_multiple_ports(sc)) 2660 can_use_msi = 1; 2661 break; 2662 case BGE_ASICREV_BCM5750: 2663 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2664 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2665 can_use_msi = 1; 2666 break; 2667 default: 2668 if (BGE_IS_575X_PLUS(sc)) 2669 can_use_msi = 1; 2670 } 2671 return (can_use_msi); 2672 } 2673 2674 static int 2675 bge_attach(device_t dev) 2676 { 2677 struct ifnet *ifp; 2678 struct bge_softc *sc; 2679 uint32_t hwcfg = 0, misccfg; 2680 u_char eaddr[ETHER_ADDR_LEN]; 2681 int capmask, error, f, msicount, phy_addr, reg, rid, trys; 2682 2683 sc = device_get_softc(dev); 2684 sc->bge_dev = dev; 2685 2686 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2687 2688 /* 2689 * Map control/status registers. 2690 */ 2691 pci_enable_busmaster(dev); 2692 2693 rid = PCIR_BAR(0); 2694 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2695 RF_ACTIVE); 2696 2697 if (sc->bge_res == NULL) { 2698 device_printf (sc->bge_dev, "couldn't map memory\n"); 2699 error = ENXIO; 2700 goto fail; 2701 } 2702 2703 /* Save various chip information. */ 2704 sc->bge_chipid = 2705 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2706 BGE_PCIMISCCTL_ASICREV_SHIFT; 2707 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2708 /* 2709 * Find the ASCI revision. Different chips use different 2710 * registers. 2711 */ 2712 switch (pci_get_device(dev)) { 2713 case BCOM_DEVICEID_BCM5717: 2714 case BCOM_DEVICEID_BCM5718: 2715 sc->bge_chipid = pci_read_config(dev, 2716 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2717 break; 2718 case BCOM_DEVICEID_BCM57761: 2719 case BCOM_DEVICEID_BCM57765: 2720 case BCOM_DEVICEID_BCM57781: 2721 case BCOM_DEVICEID_BCM57785: 2722 case BCOM_DEVICEID_BCM57791: 2723 case BCOM_DEVICEID_BCM57795: 2724 sc->bge_chipid = pci_read_config(dev, 2725 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2726 break; 2727 default: 2728 sc->bge_chipid = pci_read_config(dev, 2729 BGE_PCI_PRODID_ASICREV, 4); 2730 } 2731 } 2732 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2733 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2734 2735 /* Set default PHY address. */ 2736 phy_addr = 1; 2737 /* 2738 * PHY address mapping for various devices. 2739 * 2740 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2741 * ---------+-------+-------+-------+-------+ 2742 * BCM57XX | 1 | X | X | X | 2743 * BCM5704 | 1 | X | 1 | X | 2744 * BCM5717 | 1 | 8 | 2 | 9 | 2745 * 2746 * Other addresses may respond but they are not 2747 * IEEE compliant PHYs and should be ignored. 2748 */ 2749 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) { 2750 f = pci_get_function(dev); 2751 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2752 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2753 BGE_SGDIGSTS_IS_SERDES) 2754 phy_addr = f + 8; 2755 else 2756 phy_addr = f + 1; 2757 } else if (sc->bge_chipid == BGE_CHIPID_BCM5717_B0) { 2758 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2759 BGE_CPMU_PHY_STRAP_IS_SERDES) 2760 phy_addr = f + 8; 2761 else 2762 phy_addr = f + 1; 2763 } 2764 } 2765 2766 /* 2767 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2768 * 5705 A0 and A1 chips. 2769 */ 2770 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2771 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2772 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2773 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2774 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2775 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 2776 2777 if (bge_has_eaddr(sc)) 2778 sc->bge_flags |= BGE_FLAG_EADDR; 2779 2780 /* Save chipset family. */ 2781 switch (sc->bge_asicrev) { 2782 case BGE_ASICREV_BCM5717: 2783 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 2784 case BGE_ASICREV_BCM57765: 2785 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 2786 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 2787 BGE_FLAG_JUMBO_FRAME; 2788 break; 2789 case BGE_ASICREV_BCM5755: 2790 case BGE_ASICREV_BCM5761: 2791 case BGE_ASICREV_BCM5784: 2792 case BGE_ASICREV_BCM5785: 2793 case BGE_ASICREV_BCM5787: 2794 case BGE_ASICREV_BCM57780: 2795 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2796 BGE_FLAG_5705_PLUS; 2797 break; 2798 case BGE_ASICREV_BCM5700: 2799 case BGE_ASICREV_BCM5701: 2800 case BGE_ASICREV_BCM5703: 2801 case BGE_ASICREV_BCM5704: 2802 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2803 break; 2804 case BGE_ASICREV_BCM5714_A0: 2805 case BGE_ASICREV_BCM5780: 2806 case BGE_ASICREV_BCM5714: 2807 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 2808 /* FALLTHROUGH */ 2809 case BGE_ASICREV_BCM5750: 2810 case BGE_ASICREV_BCM5752: 2811 case BGE_ASICREV_BCM5906: 2812 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2813 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2814 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 2815 /* FALLTHROUGH */ 2816 case BGE_ASICREV_BCM5705: 2817 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2818 break; 2819 } 2820 2821 /* Set various PHY bug flags. */ 2822 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2823 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2824 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 2825 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2826 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2827 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 2828 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2829 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 2830 if (pci_get_subvendor(dev) == DELL_VENDORID) 2831 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 2832 if ((BGE_IS_5705_PLUS(sc)) && 2833 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2834 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 2835 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2836 sc->bge_asicrev != BGE_ASICREV_BCM57765 && 2837 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2838 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2839 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2840 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2841 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2842 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2843 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 2844 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 2845 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 2846 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 2847 } else 2848 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 2849 } 2850 2851 /* Identify the chips that use an CPMU. */ 2852 if (BGE_IS_5717_PLUS(sc) || 2853 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2854 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2855 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2856 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2857 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 2858 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 2859 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2860 else 2861 sc->bge_mi_mode = BGE_MIMODE_BASE; 2862 /* Enable auto polling for BCM570[0-5]. */ 2863 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 2864 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2865 2866 /* 2867 * All controllers that are not 5755 or higher have 4GB 2868 * boundary DMA bug. 2869 * Whenever an address crosses a multiple of the 4GB boundary 2870 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2871 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2872 * state machine will lockup and cause the device to hang. 2873 */ 2874 if (BGE_IS_5755_PLUS(sc) == 0) 2875 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2876 2877 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2878 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2879 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2880 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2881 sc->bge_flags |= BGE_FLAG_5788; 2882 } 2883 2884 capmask = BMSR_DEFCAPMASK; 2885 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2886 (misccfg == 0x4000 || misccfg == 0x8000)) || 2887 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2888 pci_get_vendor(dev) == BCOM_VENDORID && 2889 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 2890 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 2891 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 2892 (pci_get_vendor(dev) == BCOM_VENDORID && 2893 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 2894 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 2895 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 2896 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 2897 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2898 /* These chips are 10/100 only. */ 2899 capmask &= ~BMSR_EXTSTAT; 2900 } 2901 2902 /* 2903 * Some controllers seem to require a special firmware to use 2904 * TSO. But the firmware is not available to FreeBSD and Linux 2905 * claims that the TSO performed by the firmware is slower than 2906 * hardware based TSO. Moreover the firmware based TSO has one 2907 * known bug which can't handle TSO if ethernet header + IP/TCP 2908 * header is greater than 80 bytes. The workaround for the TSO 2909 * bug exist but it seems it's too expensive than not using 2910 * TSO at all. Some hardwares also have the TSO bug so limit 2911 * the TSO to the controllers that are not affected TSO issues 2912 * (e.g. 5755 or higher). 2913 */ 2914 if (BGE_IS_5717_PLUS(sc)) { 2915 /* BCM5717 requires different TSO configuration. */ 2916 sc->bge_flags |= BGE_FLAG_TSO3; 2917 } else if (BGE_IS_5755_PLUS(sc)) { 2918 /* 2919 * BCM5754 and BCM5787 shares the same ASIC id so 2920 * explicit device id check is required. 2921 * Due to unknown reason TSO does not work on BCM5755M. 2922 */ 2923 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2924 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 2925 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 2926 sc->bge_flags |= BGE_FLAG_TSO; 2927 } 2928 2929 /* 2930 * Check if this is a PCI-X or PCI Express device. 2931 */ 2932 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 2933 /* 2934 * Found a PCI Express capabilities register, this 2935 * must be a PCI Express device. 2936 */ 2937 sc->bge_flags |= BGE_FLAG_PCIE; 2938 sc->bge_expcap = reg; 2939 if (pci_get_max_read_req(dev) != 4096) 2940 pci_set_max_read_req(dev, 4096); 2941 } else { 2942 /* 2943 * Check if the device is in PCI-X Mode. 2944 * (This bit is not valid on PCI Express controllers.) 2945 */ 2946 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 2947 sc->bge_pcixcap = reg; 2948 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2949 BGE_PCISTATE_PCI_BUSMODE) == 0) 2950 sc->bge_flags |= BGE_FLAG_PCIX; 2951 } 2952 2953 /* 2954 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2955 * not actually a MAC controller bug but an issue with the embedded 2956 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2957 */ 2958 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2959 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2960 /* 2961 * Allocate the interrupt, using MSI if possible. These devices 2962 * support 8 MSI messages, but only the first one is used in 2963 * normal operation. 2964 */ 2965 rid = 0; 2966 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 2967 sc->bge_msicap = reg; 2968 if (bge_can_use_msi(sc)) { 2969 msicount = pci_msi_count(dev); 2970 if (msicount > 1) 2971 msicount = 1; 2972 } else 2973 msicount = 0; 2974 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2975 rid = 1; 2976 sc->bge_flags |= BGE_FLAG_MSI; 2977 } 2978 } 2979 2980 /* 2981 * All controllers except BCM5700 supports tagged status but 2982 * we use tagged status only for MSI case on BCM5717. Otherwise 2983 * MSI on BCM5717 does not work. 2984 */ 2985 #ifndef DEVICE_POLLING 2986 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 2987 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 2988 #endif 2989 2990 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2991 RF_SHAREABLE | RF_ACTIVE); 2992 2993 if (sc->bge_irq == NULL) { 2994 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2995 error = ENXIO; 2996 goto fail; 2997 } 2998 2999 device_printf(dev, 3000 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 3001 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 3002 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 3003 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 3004 3005 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3006 3007 /* Try to reset the chip. */ 3008 if (bge_reset(sc)) { 3009 device_printf(sc->bge_dev, "chip reset failed\n"); 3010 error = ENXIO; 3011 goto fail; 3012 } 3013 3014 sc->bge_asf_mode = 0; 3015 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 3016 == BGE_MAGIC_NUMBER)) { 3017 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 3018 & BGE_HWCFG_ASF) { 3019 sc->bge_asf_mode |= ASF_ENABLE; 3020 sc->bge_asf_mode |= ASF_STACKUP; 3021 if (BGE_IS_575X_PLUS(sc)) 3022 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3023 } 3024 } 3025 3026 /* Try to reset the chip again the nice way. */ 3027 bge_stop_fw(sc); 3028 bge_sig_pre_reset(sc, BGE_RESET_STOP); 3029 if (bge_reset(sc)) { 3030 device_printf(sc->bge_dev, "chip reset failed\n"); 3031 error = ENXIO; 3032 goto fail; 3033 } 3034 3035 bge_sig_legacy(sc, BGE_RESET_STOP); 3036 bge_sig_post_reset(sc, BGE_RESET_STOP); 3037 3038 if (bge_chipinit(sc)) { 3039 device_printf(sc->bge_dev, "chip initialization failed\n"); 3040 error = ENXIO; 3041 goto fail; 3042 } 3043 3044 error = bge_get_eaddr(sc, eaddr); 3045 if (error) { 3046 device_printf(sc->bge_dev, 3047 "failed to read station address\n"); 3048 error = ENXIO; 3049 goto fail; 3050 } 3051 3052 /* 5705 limits RX return ring to 512 entries. */ 3053 if (BGE_IS_5717_PLUS(sc)) 3054 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3055 else if (BGE_IS_5705_PLUS(sc)) 3056 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3057 else 3058 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3059 3060 if (bge_dma_alloc(sc)) { 3061 device_printf(sc->bge_dev, 3062 "failed to allocate DMA resources\n"); 3063 error = ENXIO; 3064 goto fail; 3065 } 3066 3067 bge_add_sysctls(sc); 3068 3069 /* Set default tuneable values. */ 3070 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3071 sc->bge_rx_coal_ticks = 150; 3072 sc->bge_tx_coal_ticks = 150; 3073 sc->bge_rx_max_coal_bds = 10; 3074 sc->bge_tx_max_coal_bds = 10; 3075 3076 /* Initialize checksum features to use. */ 3077 sc->bge_csum_features = BGE_CSUM_FEATURES; 3078 if (sc->bge_forced_udpcsum != 0) 3079 sc->bge_csum_features |= CSUM_UDP; 3080 3081 /* Set up ifnet structure */ 3082 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3083 if (ifp == NULL) { 3084 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3085 error = ENXIO; 3086 goto fail; 3087 } 3088 ifp->if_softc = sc; 3089 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3090 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3091 ifp->if_ioctl = bge_ioctl; 3092 ifp->if_start = bge_start; 3093 ifp->if_init = bge_init; 3094 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3095 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3096 IFQ_SET_READY(&ifp->if_snd); 3097 ifp->if_hwassist = sc->bge_csum_features; 3098 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3099 IFCAP_VLAN_MTU; 3100 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3101 ifp->if_hwassist |= CSUM_TSO; 3102 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3103 } 3104 #ifdef IFCAP_VLAN_HWCSUM 3105 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3106 #endif 3107 ifp->if_capenable = ifp->if_capabilities; 3108 #ifdef DEVICE_POLLING 3109 ifp->if_capabilities |= IFCAP_POLLING; 3110 #endif 3111 3112 /* 3113 * 5700 B0 chips do not support checksumming correctly due 3114 * to hardware bugs. 3115 */ 3116 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3117 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3118 ifp->if_capenable &= ~IFCAP_HWCSUM; 3119 ifp->if_hwassist = 0; 3120 } 3121 3122 /* 3123 * Figure out what sort of media we have by checking the 3124 * hardware config word in the first 32k of NIC internal memory, 3125 * or fall back to examining the EEPROM if necessary. 3126 * Note: on some BCM5700 cards, this value appears to be unset. 3127 * If that's the case, we have to rely on identifying the NIC 3128 * by its PCI subsystem ID, as we do below for the SysKonnect 3129 * SK-9D41. 3130 */ 3131 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 3132 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 3133 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3134 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3135 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3136 sizeof(hwcfg))) { 3137 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3138 error = ENXIO; 3139 goto fail; 3140 } 3141 hwcfg = ntohl(hwcfg); 3142 } 3143 3144 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3145 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3146 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3147 if (BGE_IS_5714_FAMILY(sc)) 3148 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3149 else 3150 sc->bge_flags |= BGE_FLAG_TBI; 3151 } 3152 3153 if (sc->bge_flags & BGE_FLAG_TBI) { 3154 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3155 bge_ifmedia_sts); 3156 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3157 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3158 0, NULL); 3159 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3160 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3161 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3162 } else { 3163 /* 3164 * Do transceiver setup and tell the firmware the 3165 * driver is down so we can try to get access the 3166 * probe if ASF is running. Retry a couple of times 3167 * if we get a conflict with the ASF firmware accessing 3168 * the PHY. 3169 */ 3170 trys = 0; 3171 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3172 again: 3173 bge_asf_driver_up(sc); 3174 3175 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3176 bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, 3177 MIIF_DOPAUSE); 3178 if (error != 0) { 3179 if (trys++ < 4) { 3180 device_printf(sc->bge_dev, "Try again\n"); 3181 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 3182 BMCR_RESET); 3183 goto again; 3184 } 3185 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3186 goto fail; 3187 } 3188 3189 /* 3190 * Now tell the firmware we are going up after probing the PHY 3191 */ 3192 if (sc->bge_asf_mode & ASF_STACKUP) 3193 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3194 } 3195 3196 /* 3197 * When using the BCM5701 in PCI-X mode, data corruption has 3198 * been observed in the first few bytes of some received packets. 3199 * Aligning the packet buffer in memory eliminates the corruption. 3200 * Unfortunately, this misaligns the packet payloads. On platforms 3201 * which do not support unaligned accesses, we will realign the 3202 * payloads by copying the received packets. 3203 */ 3204 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3205 sc->bge_flags & BGE_FLAG_PCIX) 3206 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3207 3208 /* 3209 * Call MI attach routine. 3210 */ 3211 ether_ifattach(ifp, eaddr); 3212 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3213 3214 /* Tell upper layer we support long frames. */ 3215 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3216 3217 /* 3218 * Hookup IRQ last. 3219 */ 3220 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3221 /* Take advantage of single-shot MSI. */ 3222 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3223 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3224 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3225 taskqueue_thread_enqueue, &sc->bge_tq); 3226 if (sc->bge_tq == NULL) { 3227 device_printf(dev, "could not create taskqueue.\n"); 3228 ether_ifdetach(ifp); 3229 error = ENXIO; 3230 goto fail; 3231 } 3232 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3233 device_get_nameunit(sc->bge_dev)); 3234 error = bus_setup_intr(dev, sc->bge_irq, 3235 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3236 &sc->bge_intrhand); 3237 if (error) 3238 ether_ifdetach(ifp); 3239 } else 3240 error = bus_setup_intr(dev, sc->bge_irq, 3241 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3242 &sc->bge_intrhand); 3243 3244 if (error) { 3245 bge_detach(dev); 3246 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3247 } 3248 3249 return (0); 3250 3251 fail: 3252 bge_release_resources(sc); 3253 3254 return (error); 3255 } 3256 3257 static int 3258 bge_detach(device_t dev) 3259 { 3260 struct bge_softc *sc; 3261 struct ifnet *ifp; 3262 3263 sc = device_get_softc(dev); 3264 ifp = sc->bge_ifp; 3265 3266 #ifdef DEVICE_POLLING 3267 if (ifp->if_capenable & IFCAP_POLLING) 3268 ether_poll_deregister(ifp); 3269 #endif 3270 3271 BGE_LOCK(sc); 3272 bge_stop(sc); 3273 bge_reset(sc); 3274 BGE_UNLOCK(sc); 3275 3276 callout_drain(&sc->bge_stat_ch); 3277 3278 if (sc->bge_tq) 3279 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3280 ether_ifdetach(ifp); 3281 3282 if (sc->bge_flags & BGE_FLAG_TBI) { 3283 ifmedia_removeall(&sc->bge_ifmedia); 3284 } else { 3285 bus_generic_detach(dev); 3286 device_delete_child(dev, sc->bge_miibus); 3287 } 3288 3289 bge_release_resources(sc); 3290 3291 return (0); 3292 } 3293 3294 static void 3295 bge_release_resources(struct bge_softc *sc) 3296 { 3297 device_t dev; 3298 3299 dev = sc->bge_dev; 3300 3301 if (sc->bge_tq != NULL) 3302 taskqueue_free(sc->bge_tq); 3303 3304 if (sc->bge_intrhand != NULL) 3305 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3306 3307 if (sc->bge_irq != NULL) 3308 bus_release_resource(dev, SYS_RES_IRQ, 3309 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3310 3311 if (sc->bge_flags & BGE_FLAG_MSI) 3312 pci_release_msi(dev); 3313 3314 if (sc->bge_res != NULL) 3315 bus_release_resource(dev, SYS_RES_MEMORY, 3316 PCIR_BAR(0), sc->bge_res); 3317 3318 if (sc->bge_ifp != NULL) 3319 if_free(sc->bge_ifp); 3320 3321 bge_dma_free(sc); 3322 3323 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3324 BGE_LOCK_DESTROY(sc); 3325 } 3326 3327 static int 3328 bge_reset(struct bge_softc *sc) 3329 { 3330 device_t dev; 3331 uint32_t cachesize, command, pcistate, reset, val; 3332 void (*write_op)(struct bge_softc *, int, int); 3333 uint16_t devctl; 3334 int i; 3335 3336 dev = sc->bge_dev; 3337 3338 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3339 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3340 if (sc->bge_flags & BGE_FLAG_PCIE) 3341 write_op = bge_writemem_direct; 3342 else 3343 write_op = bge_writemem_ind; 3344 } else 3345 write_op = bge_writereg_ind; 3346 3347 /* Save some important PCI state. */ 3348 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3349 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3350 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3351 3352 pci_write_config(dev, BGE_PCI_MISC_CTL, 3353 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3354 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3355 3356 /* Disable fastboot on controllers that support it. */ 3357 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3358 BGE_IS_5755_PLUS(sc)) { 3359 if (bootverbose) 3360 device_printf(dev, "Disabling fastboot\n"); 3361 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3362 } 3363 3364 /* 3365 * Write the magic number to SRAM at offset 0xB50. 3366 * When firmware finishes its initialization it will 3367 * write ~BGE_MAGIC_NUMBER to the same location. 3368 */ 3369 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3370 3371 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3372 3373 /* XXX: Broadcom Linux driver. */ 3374 if (sc->bge_flags & BGE_FLAG_PCIE) { 3375 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3376 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3377 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3378 /* Prevent PCIE link training during global reset */ 3379 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3380 reset |= 1 << 29; 3381 } 3382 } 3383 3384 /* 3385 * Set GPHY Power Down Override to leave GPHY 3386 * powered up in D0 uninitialized. 3387 */ 3388 if (BGE_IS_5705_PLUS(sc)) 3389 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3390 3391 /* Issue global reset */ 3392 write_op(sc, BGE_MISC_CFG, reset); 3393 3394 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3395 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3396 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3397 val | BGE_VCPU_STATUS_DRV_RESET); 3398 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3399 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3400 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3401 } 3402 3403 DELAY(1000); 3404 3405 /* XXX: Broadcom Linux driver. */ 3406 if (sc->bge_flags & BGE_FLAG_PCIE) { 3407 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3408 DELAY(500000); /* wait for link training to complete */ 3409 val = pci_read_config(dev, 0xC4, 4); 3410 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3411 } 3412 devctl = pci_read_config(dev, 3413 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3414 /* Clear enable no snoop and disable relaxed ordering. */ 3415 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3416 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3417 /* Set PCIE max payload size to 128. */ 3418 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3419 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3420 devctl, 2); 3421 /* Clear error status. */ 3422 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3423 PCIM_EXP_STA_CORRECTABLE_ERROR | 3424 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3425 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3426 } 3427 3428 /* Reset some of the PCI state that got zapped by reset. */ 3429 pci_write_config(dev, BGE_PCI_MISC_CTL, 3430 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3431 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3432 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3433 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3434 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3435 /* 3436 * Disable PCI-X relaxed ordering to ensure status block update 3437 * comes first then packet buffer DMA. Otherwise driver may 3438 * read stale status block. 3439 */ 3440 if (sc->bge_flags & BGE_FLAG_PCIX) { 3441 devctl = pci_read_config(dev, 3442 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3443 devctl &= ~PCIXM_COMMAND_ERO; 3444 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3445 devctl &= ~PCIXM_COMMAND_MAX_READ; 3446 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3447 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3448 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3449 PCIXM_COMMAND_MAX_READ); 3450 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3451 } 3452 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3453 devctl, 2); 3454 } 3455 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 3456 if (BGE_IS_5714_FAMILY(sc)) { 3457 /* This chip disables MSI on reset. */ 3458 if (sc->bge_flags & BGE_FLAG_MSI) { 3459 val = pci_read_config(dev, 3460 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3461 pci_write_config(dev, 3462 sc->bge_msicap + PCIR_MSI_CTRL, 3463 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3464 val = CSR_READ_4(sc, BGE_MSI_MODE); 3465 CSR_WRITE_4(sc, BGE_MSI_MODE, 3466 val | BGE_MSIMODE_ENABLE); 3467 } 3468 val = CSR_READ_4(sc, BGE_MARB_MODE); 3469 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3470 } else 3471 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3472 3473 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3474 for (i = 0; i < BGE_TIMEOUT; i++) { 3475 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3476 if (val & BGE_VCPU_STATUS_INIT_DONE) 3477 break; 3478 DELAY(100); 3479 } 3480 if (i == BGE_TIMEOUT) { 3481 device_printf(dev, "reset timed out\n"); 3482 return (1); 3483 } 3484 } else { 3485 /* 3486 * Poll until we see the 1's complement of the magic number. 3487 * This indicates that the firmware initialization is complete. 3488 * We expect this to fail if no chip containing the Ethernet 3489 * address is fitted though. 3490 */ 3491 for (i = 0; i < BGE_TIMEOUT; i++) { 3492 DELAY(10); 3493 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3494 if (val == ~BGE_MAGIC_NUMBER) 3495 break; 3496 } 3497 3498 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3499 device_printf(dev, 3500 "firmware handshake timed out, found 0x%08x\n", 3501 val); 3502 /* BCM57765 A0 needs additional time before accessing. */ 3503 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 3504 DELAY(10 * 1000); /* XXX */ 3505 } 3506 3507 /* 3508 * XXX Wait for the value of the PCISTATE register to 3509 * return to its original pre-reset state. This is a 3510 * fairly good indicator of reset completion. If we don't 3511 * wait for the reset to fully complete, trying to read 3512 * from the device's non-PCI registers may yield garbage 3513 * results. 3514 */ 3515 for (i = 0; i < BGE_TIMEOUT; i++) { 3516 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3517 break; 3518 DELAY(10); 3519 } 3520 3521 /* Fix up byte swapping. */ 3522 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3523 BGE_MODECTL_BYTESWAP_DATA); 3524 3525 /* Tell the ASF firmware we are up */ 3526 if (sc->bge_asf_mode & ASF_STACKUP) 3527 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3528 3529 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3530 3531 /* 3532 * The 5704 in TBI mode apparently needs some special 3533 * adjustment to insure the SERDES drive level is set 3534 * to 1.2V. 3535 */ 3536 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3537 sc->bge_flags & BGE_FLAG_TBI) { 3538 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3539 val = (val & ~0xFFF) | 0x880; 3540 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3541 } 3542 3543 /* XXX: Broadcom Linux driver. */ 3544 if (sc->bge_flags & BGE_FLAG_PCIE && 3545 !BGE_IS_5717_PLUS(sc) && 3546 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3547 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3548 /* Enable Data FIFO protection. */ 3549 val = CSR_READ_4(sc, 0x7C00); 3550 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3551 } 3552 DELAY(10000); 3553 3554 return (0); 3555 } 3556 3557 static __inline void 3558 bge_rxreuse_std(struct bge_softc *sc, int i) 3559 { 3560 struct bge_rx_bd *r; 3561 3562 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3563 r->bge_flags = BGE_RXBDFLAG_END; 3564 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3565 r->bge_idx = i; 3566 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3567 } 3568 3569 static __inline void 3570 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3571 { 3572 struct bge_extrx_bd *r; 3573 3574 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3575 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3576 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3577 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3578 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3579 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3580 r->bge_idx = i; 3581 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3582 } 3583 3584 /* 3585 * Frame reception handling. This is called if there's a frame 3586 * on the receive return list. 3587 * 3588 * Note: we have to be able to handle two possibilities here: 3589 * 1) the frame is from the jumbo receive ring 3590 * 2) the frame is from the standard receive ring 3591 */ 3592 3593 static int 3594 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3595 { 3596 struct ifnet *ifp; 3597 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3598 uint16_t rx_cons; 3599 3600 rx_cons = sc->bge_rx_saved_considx; 3601 3602 /* Nothing to do. */ 3603 if (rx_cons == rx_prod) 3604 return (rx_npkts); 3605 3606 ifp = sc->bge_ifp; 3607 3608 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3609 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3610 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3611 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3612 if (BGE_IS_JUMBO_CAPABLE(sc) && 3613 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3614 (MCLBYTES - ETHER_ALIGN)) 3615 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3616 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3617 3618 while (rx_cons != rx_prod) { 3619 struct bge_rx_bd *cur_rx; 3620 uint32_t rxidx; 3621 struct mbuf *m = NULL; 3622 uint16_t vlan_tag = 0; 3623 int have_tag = 0; 3624 3625 #ifdef DEVICE_POLLING 3626 if (ifp->if_capenable & IFCAP_POLLING) { 3627 if (sc->rxcycles <= 0) 3628 break; 3629 sc->rxcycles--; 3630 } 3631 #endif 3632 3633 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3634 3635 rxidx = cur_rx->bge_idx; 3636 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3637 3638 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3639 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3640 have_tag = 1; 3641 vlan_tag = cur_rx->bge_vlan_tag; 3642 } 3643 3644 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3645 jumbocnt++; 3646 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3647 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3648 bge_rxreuse_jumbo(sc, rxidx); 3649 continue; 3650 } 3651 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3652 bge_rxreuse_jumbo(sc, rxidx); 3653 ifp->if_iqdrops++; 3654 continue; 3655 } 3656 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3657 } else { 3658 stdcnt++; 3659 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3660 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3661 bge_rxreuse_std(sc, rxidx); 3662 continue; 3663 } 3664 if (bge_newbuf_std(sc, rxidx) != 0) { 3665 bge_rxreuse_std(sc, rxidx); 3666 ifp->if_iqdrops++; 3667 continue; 3668 } 3669 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3670 } 3671 3672 ifp->if_ipackets++; 3673 #ifndef __NO_STRICT_ALIGNMENT 3674 /* 3675 * For architectures with strict alignment we must make sure 3676 * the payload is aligned. 3677 */ 3678 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3679 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3680 cur_rx->bge_len); 3681 m->m_data += ETHER_ALIGN; 3682 } 3683 #endif 3684 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3685 m->m_pkthdr.rcvif = ifp; 3686 3687 if (ifp->if_capenable & IFCAP_RXCSUM) 3688 bge_rxcsum(sc, cur_rx, m); 3689 3690 /* 3691 * If we received a packet with a vlan tag, 3692 * attach that information to the packet. 3693 */ 3694 if (have_tag) { 3695 m->m_pkthdr.ether_vtag = vlan_tag; 3696 m->m_flags |= M_VLANTAG; 3697 } 3698 3699 if (holdlck != 0) { 3700 BGE_UNLOCK(sc); 3701 (*ifp->if_input)(ifp, m); 3702 BGE_LOCK(sc); 3703 } else 3704 (*ifp->if_input)(ifp, m); 3705 rx_npkts++; 3706 3707 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3708 return (rx_npkts); 3709 } 3710 3711 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3712 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3713 if (stdcnt > 0) 3714 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3715 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3716 3717 if (jumbocnt > 0) 3718 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3719 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3720 3721 sc->bge_rx_saved_considx = rx_cons; 3722 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3723 if (stdcnt) 3724 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3725 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3726 if (jumbocnt) 3727 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3728 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3729 #ifdef notyet 3730 /* 3731 * This register wraps very quickly under heavy packet drops. 3732 * If you need correct statistics, you can enable this check. 3733 */ 3734 if (BGE_IS_5705_PLUS(sc)) 3735 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3736 #endif 3737 return (rx_npkts); 3738 } 3739 3740 static void 3741 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 3742 { 3743 3744 if (BGE_IS_5717_PLUS(sc)) { 3745 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 3746 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3747 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3748 if ((cur_rx->bge_error_flag & 3749 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 3750 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3751 } 3752 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 3753 m->m_pkthdr.csum_data = 3754 cur_rx->bge_tcp_udp_csum; 3755 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3756 CSUM_PSEUDO_HDR; 3757 } 3758 } 3759 } else { 3760 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3761 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3762 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3763 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3764 } 3765 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3766 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3767 m->m_pkthdr.csum_data = 3768 cur_rx->bge_tcp_udp_csum; 3769 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3770 CSUM_PSEUDO_HDR; 3771 } 3772 } 3773 } 3774 3775 static void 3776 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3777 { 3778 struct bge_tx_bd *cur_tx; 3779 struct ifnet *ifp; 3780 3781 BGE_LOCK_ASSERT(sc); 3782 3783 /* Nothing to do. */ 3784 if (sc->bge_tx_saved_considx == tx_cons) 3785 return; 3786 3787 ifp = sc->bge_ifp; 3788 3789 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3790 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3791 /* 3792 * Go through our tx ring and free mbufs for those 3793 * frames that have been sent. 3794 */ 3795 while (sc->bge_tx_saved_considx != tx_cons) { 3796 uint32_t idx; 3797 3798 idx = sc->bge_tx_saved_considx; 3799 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3800 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3801 ifp->if_opackets++; 3802 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3803 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3804 sc->bge_cdata.bge_tx_dmamap[idx], 3805 BUS_DMASYNC_POSTWRITE); 3806 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3807 sc->bge_cdata.bge_tx_dmamap[idx]); 3808 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3809 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3810 } 3811 sc->bge_txcnt--; 3812 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3813 } 3814 3815 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3816 if (sc->bge_txcnt == 0) 3817 sc->bge_timer = 0; 3818 } 3819 3820 #ifdef DEVICE_POLLING 3821 static int 3822 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3823 { 3824 struct bge_softc *sc = ifp->if_softc; 3825 uint16_t rx_prod, tx_cons; 3826 uint32_t statusword; 3827 int rx_npkts = 0; 3828 3829 BGE_LOCK(sc); 3830 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3831 BGE_UNLOCK(sc); 3832 return (rx_npkts); 3833 } 3834 3835 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3836 sc->bge_cdata.bge_status_map, 3837 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3838 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3839 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3840 3841 statusword = sc->bge_ldata.bge_status_block->bge_status; 3842 sc->bge_ldata.bge_status_block->bge_status = 0; 3843 3844 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3845 sc->bge_cdata.bge_status_map, 3846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3847 3848 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3849 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3850 sc->bge_link_evt++; 3851 3852 if (cmd == POLL_AND_CHECK_STATUS) 3853 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3854 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3855 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3856 bge_link_upd(sc); 3857 3858 sc->rxcycles = count; 3859 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3860 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3861 BGE_UNLOCK(sc); 3862 return (rx_npkts); 3863 } 3864 bge_txeof(sc, tx_cons); 3865 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3866 bge_start_locked(ifp); 3867 3868 BGE_UNLOCK(sc); 3869 return (rx_npkts); 3870 } 3871 #endif /* DEVICE_POLLING */ 3872 3873 static int 3874 bge_msi_intr(void *arg) 3875 { 3876 struct bge_softc *sc; 3877 3878 sc = (struct bge_softc *)arg; 3879 /* 3880 * This interrupt is not shared and controller already 3881 * disabled further interrupt. 3882 */ 3883 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3884 return (FILTER_HANDLED); 3885 } 3886 3887 static void 3888 bge_intr_task(void *arg, int pending) 3889 { 3890 struct bge_softc *sc; 3891 struct ifnet *ifp; 3892 uint32_t status, status_tag; 3893 uint16_t rx_prod, tx_cons; 3894 3895 sc = (struct bge_softc *)arg; 3896 ifp = sc->bge_ifp; 3897 3898 BGE_LOCK(sc); 3899 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3900 BGE_UNLOCK(sc); 3901 return; 3902 } 3903 3904 /* Get updated status block. */ 3905 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3906 sc->bge_cdata.bge_status_map, 3907 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3908 3909 /* Save producer/consumer indexess. */ 3910 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3911 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3912 status = sc->bge_ldata.bge_status_block->bge_status; 3913 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 3914 sc->bge_ldata.bge_status_block->bge_status = 0; 3915 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3916 sc->bge_cdata.bge_status_map, 3917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3918 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 3919 status_tag = 0; 3920 3921 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 3922 bge_link_upd(sc); 3923 3924 /* Let controller work. */ 3925 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 3926 3927 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3928 sc->bge_rx_saved_considx != rx_prod) { 3929 /* Check RX return ring producer/consumer. */ 3930 BGE_UNLOCK(sc); 3931 bge_rxeof(sc, rx_prod, 0); 3932 BGE_LOCK(sc); 3933 } 3934 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3935 /* Check TX ring producer/consumer. */ 3936 bge_txeof(sc, tx_cons); 3937 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3938 bge_start_locked(ifp); 3939 } 3940 BGE_UNLOCK(sc); 3941 } 3942 3943 static void 3944 bge_intr(void *xsc) 3945 { 3946 struct bge_softc *sc; 3947 struct ifnet *ifp; 3948 uint32_t statusword; 3949 uint16_t rx_prod, tx_cons; 3950 3951 sc = xsc; 3952 3953 BGE_LOCK(sc); 3954 3955 ifp = sc->bge_ifp; 3956 3957 #ifdef DEVICE_POLLING 3958 if (ifp->if_capenable & IFCAP_POLLING) { 3959 BGE_UNLOCK(sc); 3960 return; 3961 } 3962 #endif 3963 3964 /* 3965 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3966 * disable interrupts by writing nonzero like we used to, since with 3967 * our current organization this just gives complications and 3968 * pessimizations for re-enabling interrupts. We used to have races 3969 * instead of the necessary complications. Disabling interrupts 3970 * would just reduce the chance of a status update while we are 3971 * running (by switching to the interrupt-mode coalescence 3972 * parameters), but this chance is already very low so it is more 3973 * efficient to get another interrupt than prevent it. 3974 * 3975 * We do the ack first to ensure another interrupt if there is a 3976 * status update after the ack. We don't check for the status 3977 * changing later because it is more efficient to get another 3978 * interrupt than prevent it, not quite as above (not checking is 3979 * a smaller optimization than not toggling the interrupt enable, 3980 * since checking doesn't involve PCI accesses and toggling require 3981 * the status check). So toggling would probably be a pessimization 3982 * even with MSI. It would only be needed for using a task queue. 3983 */ 3984 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3985 3986 /* 3987 * Do the mandatory PCI flush as well as get the link status. 3988 */ 3989 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3990 3991 /* Make sure the descriptor ring indexes are coherent. */ 3992 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3993 sc->bge_cdata.bge_status_map, 3994 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3995 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3996 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3997 sc->bge_ldata.bge_status_block->bge_status = 0; 3998 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3999 sc->bge_cdata.bge_status_map, 4000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4001 4002 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4003 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4004 statusword || sc->bge_link_evt) 4005 bge_link_upd(sc); 4006 4007 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4008 /* Check RX return ring producer/consumer. */ 4009 bge_rxeof(sc, rx_prod, 1); 4010 } 4011 4012 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4013 /* Check TX ring producer/consumer. */ 4014 bge_txeof(sc, tx_cons); 4015 } 4016 4017 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4018 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4019 bge_start_locked(ifp); 4020 4021 BGE_UNLOCK(sc); 4022 } 4023 4024 static void 4025 bge_asf_driver_up(struct bge_softc *sc) 4026 { 4027 if (sc->bge_asf_mode & ASF_STACKUP) { 4028 /* Send ASF heartbeat aprox. every 2s */ 4029 if (sc->bge_asf_count) 4030 sc->bge_asf_count --; 4031 else { 4032 sc->bge_asf_count = 2; 4033 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 4034 BGE_FW_DRV_ALIVE); 4035 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 4036 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 4037 CSR_WRITE_4(sc, BGE_CPU_EVENT, 4038 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 4039 } 4040 } 4041 } 4042 4043 static void 4044 bge_tick(void *xsc) 4045 { 4046 struct bge_softc *sc = xsc; 4047 struct mii_data *mii = NULL; 4048 4049 BGE_LOCK_ASSERT(sc); 4050 4051 /* Synchronize with possible callout reset/stop. */ 4052 if (callout_pending(&sc->bge_stat_ch) || 4053 !callout_active(&sc->bge_stat_ch)) 4054 return; 4055 4056 if (BGE_IS_5705_PLUS(sc)) 4057 bge_stats_update_regs(sc); 4058 else 4059 bge_stats_update(sc); 4060 4061 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4062 mii = device_get_softc(sc->bge_miibus); 4063 /* 4064 * Do not touch PHY if we have link up. This could break 4065 * IPMI/ASF mode or produce extra input errors 4066 * (extra errors was reported for bcm5701 & bcm5704). 4067 */ 4068 if (!sc->bge_link) 4069 mii_tick(mii); 4070 } else { 4071 /* 4072 * Since in TBI mode auto-polling can't be used we should poll 4073 * link status manually. Here we register pending link event 4074 * and trigger interrupt. 4075 */ 4076 #ifdef DEVICE_POLLING 4077 /* In polling mode we poll link state in bge_poll(). */ 4078 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4079 #endif 4080 { 4081 sc->bge_link_evt++; 4082 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4083 sc->bge_flags & BGE_FLAG_5788) 4084 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4085 else 4086 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4087 } 4088 } 4089 4090 bge_asf_driver_up(sc); 4091 bge_watchdog(sc); 4092 4093 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4094 } 4095 4096 static void 4097 bge_stats_update_regs(struct bge_softc *sc) 4098 { 4099 struct ifnet *ifp; 4100 struct bge_mac_stats *stats; 4101 4102 ifp = sc->bge_ifp; 4103 stats = &sc->bge_mac_stats; 4104 4105 stats->ifHCOutOctets += 4106 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4107 stats->etherStatsCollisions += 4108 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4109 stats->outXonSent += 4110 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4111 stats->outXoffSent += 4112 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4113 stats->dot3StatsInternalMacTransmitErrors += 4114 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4115 stats->dot3StatsSingleCollisionFrames += 4116 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4117 stats->dot3StatsMultipleCollisionFrames += 4118 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4119 stats->dot3StatsDeferredTransmissions += 4120 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4121 stats->dot3StatsExcessiveCollisions += 4122 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4123 stats->dot3StatsLateCollisions += 4124 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4125 stats->ifHCOutUcastPkts += 4126 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4127 stats->ifHCOutMulticastPkts += 4128 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4129 stats->ifHCOutBroadcastPkts += 4130 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4131 4132 stats->ifHCInOctets += 4133 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4134 stats->etherStatsFragments += 4135 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4136 stats->ifHCInUcastPkts += 4137 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4138 stats->ifHCInMulticastPkts += 4139 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4140 stats->ifHCInBroadcastPkts += 4141 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4142 stats->dot3StatsFCSErrors += 4143 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4144 stats->dot3StatsAlignmentErrors += 4145 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4146 stats->xonPauseFramesReceived += 4147 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4148 stats->xoffPauseFramesReceived += 4149 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4150 stats->macControlFramesReceived += 4151 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4152 stats->xoffStateEntered += 4153 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4154 stats->dot3StatsFramesTooLong += 4155 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4156 stats->etherStatsJabbers += 4157 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4158 stats->etherStatsUndersizePkts += 4159 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4160 4161 stats->FramesDroppedDueToFilters += 4162 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4163 stats->DmaWriteQueueFull += 4164 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4165 stats->DmaWriteHighPriQueueFull += 4166 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4167 stats->NoMoreRxBDs += 4168 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4169 stats->InputDiscards += 4170 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4171 stats->InputErrors += 4172 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4173 stats->RecvThresholdHit += 4174 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4175 4176 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4177 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4178 stats->InputErrors); 4179 } 4180 4181 static void 4182 bge_stats_clear_regs(struct bge_softc *sc) 4183 { 4184 4185 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4186 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4187 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4188 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4189 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4190 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4191 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4192 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4193 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4194 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4195 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4196 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4197 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4198 4199 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4200 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4201 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4202 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4203 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4204 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4205 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4206 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4207 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4208 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4209 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4210 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4211 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4212 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4213 4214 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4215 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4216 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4217 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4218 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4219 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4220 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4221 } 4222 4223 static void 4224 bge_stats_update(struct bge_softc *sc) 4225 { 4226 struct ifnet *ifp; 4227 bus_size_t stats; 4228 uint32_t cnt; /* current register value */ 4229 4230 ifp = sc->bge_ifp; 4231 4232 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4233 4234 #define READ_STAT(sc, stats, stat) \ 4235 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4236 4237 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4238 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4239 sc->bge_tx_collisions = cnt; 4240 4241 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4242 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4243 sc->bge_rx_discards = cnt; 4244 4245 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4246 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4247 sc->bge_tx_discards = cnt; 4248 4249 #undef READ_STAT 4250 } 4251 4252 /* 4253 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4254 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4255 * but when such padded frames employ the bge IP/TCP checksum offload, 4256 * the hardware checksum assist gives incorrect results (possibly 4257 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4258 * If we pad such runts with zeros, the onboard checksum comes out correct. 4259 */ 4260 static __inline int 4261 bge_cksum_pad(struct mbuf *m) 4262 { 4263 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4264 struct mbuf *last; 4265 4266 /* If there's only the packet-header and we can pad there, use it. */ 4267 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4268 M_TRAILINGSPACE(m) >= padlen) { 4269 last = m; 4270 } else { 4271 /* 4272 * Walk packet chain to find last mbuf. We will either 4273 * pad there, or append a new mbuf and pad it. 4274 */ 4275 for (last = m; last->m_next != NULL; last = last->m_next); 4276 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4277 /* Allocate new empty mbuf, pad it. Compact later. */ 4278 struct mbuf *n; 4279 4280 MGET(n, M_DONTWAIT, MT_DATA); 4281 if (n == NULL) 4282 return (ENOBUFS); 4283 n->m_len = 0; 4284 last->m_next = n; 4285 last = n; 4286 } 4287 } 4288 4289 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4290 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4291 last->m_len += padlen; 4292 m->m_pkthdr.len += padlen; 4293 4294 return (0); 4295 } 4296 4297 static struct mbuf * 4298 bge_check_short_dma(struct mbuf *m) 4299 { 4300 struct mbuf *n; 4301 int found; 4302 4303 /* 4304 * If device receive two back-to-back send BDs with less than 4305 * or equal to 8 total bytes then the device may hang. The two 4306 * back-to-back send BDs must in the same frame for this failure 4307 * to occur. Scan mbuf chains and see whether two back-to-back 4308 * send BDs are there. If this is the case, allocate new mbuf 4309 * and copy the frame to workaround the silicon bug. 4310 */ 4311 for (n = m, found = 0; n != NULL; n = n->m_next) { 4312 if (n->m_len < 8) { 4313 found++; 4314 if (found > 1) 4315 break; 4316 continue; 4317 } 4318 found = 0; 4319 } 4320 4321 if (found > 1) { 4322 n = m_defrag(m, M_DONTWAIT); 4323 if (n == NULL) 4324 m_freem(m); 4325 } else 4326 n = m; 4327 return (n); 4328 } 4329 4330 static struct mbuf * 4331 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 4332 uint16_t *flags) 4333 { 4334 struct ip *ip; 4335 struct tcphdr *tcp; 4336 struct mbuf *n; 4337 uint16_t hlen; 4338 uint32_t poff; 4339 4340 if (M_WRITABLE(m) == 0) { 4341 /* Get a writable copy. */ 4342 n = m_dup(m, M_DONTWAIT); 4343 m_freem(m); 4344 if (n == NULL) 4345 return (NULL); 4346 m = n; 4347 } 4348 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 4349 if (m == NULL) 4350 return (NULL); 4351 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4352 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 4353 m = m_pullup(m, poff + sizeof(struct tcphdr)); 4354 if (m == NULL) 4355 return (NULL); 4356 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4357 m = m_pullup(m, poff + (tcp->th_off << 2)); 4358 if (m == NULL) 4359 return (NULL); 4360 /* 4361 * It seems controller doesn't modify IP length and TCP pseudo 4362 * checksum. These checksum computed by upper stack should be 0. 4363 */ 4364 *mss = m->m_pkthdr.tso_segsz; 4365 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4366 ip->ip_sum = 0; 4367 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 4368 /* Clear pseudo checksum computed by TCP stack. */ 4369 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4370 tcp->th_sum = 0; 4371 /* 4372 * Broadcom controllers uses different descriptor format for 4373 * TSO depending on ASIC revision. Due to TSO-capable firmware 4374 * license issue and lower performance of firmware based TSO 4375 * we only support hardware based TSO. 4376 */ 4377 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 4378 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 4379 if (sc->bge_flags & BGE_FLAG_TSO3) { 4380 /* 4381 * For BCM5717 and newer controllers, hardware based TSO 4382 * uses the 14 lower bits of the bge_mss field to store the 4383 * MSS and the upper 2 bits to store the lowest 2 bits of 4384 * the IP/TCP header length. The upper 6 bits of the header 4385 * length are stored in the bge_flags[14:10,4] field. Jumbo 4386 * frames are supported. 4387 */ 4388 *mss |= ((hlen & 0x3) << 14); 4389 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 4390 } else { 4391 /* 4392 * For BCM5755 and newer controllers, hardware based TSO uses 4393 * the lower 11 bits to store the MSS and the upper 5 bits to 4394 * store the IP/TCP header length. Jumbo frames are not 4395 * supported. 4396 */ 4397 *mss |= (hlen << 11); 4398 } 4399 return (m); 4400 } 4401 4402 /* 4403 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4404 * pointers to descriptors. 4405 */ 4406 static int 4407 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 4408 { 4409 bus_dma_segment_t segs[BGE_NSEG_NEW]; 4410 bus_dmamap_t map; 4411 struct bge_tx_bd *d; 4412 struct mbuf *m = *m_head; 4413 uint32_t idx = *txidx; 4414 uint16_t csum_flags, mss, vlan_tag; 4415 int nsegs, i, error; 4416 4417 csum_flags = 0; 4418 mss = 0; 4419 vlan_tag = 0; 4420 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 4421 m->m_next != NULL) { 4422 *m_head = bge_check_short_dma(m); 4423 if (*m_head == NULL) 4424 return (ENOBUFS); 4425 m = *m_head; 4426 } 4427 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 4428 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 4429 if (*m_head == NULL) 4430 return (ENOBUFS); 4431 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 4432 BGE_TXBDFLAG_CPU_POST_DMA; 4433 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 4434 if (m->m_pkthdr.csum_flags & CSUM_IP) 4435 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4436 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 4437 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4438 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4439 (error = bge_cksum_pad(m)) != 0) { 4440 m_freem(m); 4441 *m_head = NULL; 4442 return (error); 4443 } 4444 } 4445 if (m->m_flags & M_LASTFRAG) 4446 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 4447 else if (m->m_flags & M_FRAG) 4448 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 4449 } 4450 4451 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 4452 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 4453 m->m_pkthdr.len > ETHER_MAX_LEN) 4454 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 4455 if (sc->bge_forced_collapse > 0 && 4456 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 4457 /* 4458 * Forcedly collapse mbuf chains to overcome hardware 4459 * limitation which only support a single outstanding 4460 * DMA read operation. 4461 */ 4462 if (sc->bge_forced_collapse == 1) 4463 m = m_defrag(m, M_DONTWAIT); 4464 else 4465 m = m_collapse(m, M_DONTWAIT, 4466 sc->bge_forced_collapse); 4467 if (m == NULL) 4468 m = *m_head; 4469 *m_head = m; 4470 } 4471 } 4472 4473 map = sc->bge_cdata.bge_tx_dmamap[idx]; 4474 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4475 &nsegs, BUS_DMA_NOWAIT); 4476 if (error == EFBIG) { 4477 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4478 if (m == NULL) { 4479 m_freem(*m_head); 4480 *m_head = NULL; 4481 return (ENOBUFS); 4482 } 4483 *m_head = m; 4484 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4485 m, segs, &nsegs, BUS_DMA_NOWAIT); 4486 if (error) { 4487 m_freem(m); 4488 *m_head = NULL; 4489 return (error); 4490 } 4491 } else if (error != 0) 4492 return (error); 4493 4494 /* Check if we have enough free send BDs. */ 4495 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4496 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4497 return (ENOBUFS); 4498 } 4499 4500 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4501 4502 if (m->m_flags & M_VLANTAG) { 4503 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4504 vlan_tag = m->m_pkthdr.ether_vtag; 4505 } 4506 for (i = 0; ; i++) { 4507 d = &sc->bge_ldata.bge_tx_ring[idx]; 4508 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4509 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4510 d->bge_len = segs[i].ds_len; 4511 d->bge_flags = csum_flags; 4512 d->bge_vlan_tag = vlan_tag; 4513 d->bge_mss = mss; 4514 if (i == nsegs - 1) 4515 break; 4516 BGE_INC(idx, BGE_TX_RING_CNT); 4517 } 4518 4519 /* Mark the last segment as end of packet... */ 4520 d->bge_flags |= BGE_TXBDFLAG_END; 4521 4522 /* 4523 * Insure that the map for this transmission 4524 * is placed at the array index of the last descriptor 4525 * in this chain. 4526 */ 4527 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4528 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4529 sc->bge_cdata.bge_tx_chain[idx] = m; 4530 sc->bge_txcnt += nsegs; 4531 4532 BGE_INC(idx, BGE_TX_RING_CNT); 4533 *txidx = idx; 4534 4535 return (0); 4536 } 4537 4538 /* 4539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4540 * to the mbuf data regions directly in the transmit descriptors. 4541 */ 4542 static void 4543 bge_start_locked(struct ifnet *ifp) 4544 { 4545 struct bge_softc *sc; 4546 struct mbuf *m_head; 4547 uint32_t prodidx; 4548 int count; 4549 4550 sc = ifp->if_softc; 4551 BGE_LOCK_ASSERT(sc); 4552 4553 if (!sc->bge_link || 4554 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4555 IFF_DRV_RUNNING) 4556 return; 4557 4558 prodidx = sc->bge_tx_prodidx; 4559 4560 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4561 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4562 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4563 break; 4564 } 4565 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4566 if (m_head == NULL) 4567 break; 4568 4569 /* 4570 * XXX 4571 * The code inside the if() block is never reached since we 4572 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4573 * requests to checksum TCP/UDP in a fragmented packet. 4574 * 4575 * XXX 4576 * safety overkill. If this is a fragmented packet chain 4577 * with delayed TCP/UDP checksums, then only encapsulate 4578 * it if we have enough descriptors to handle the entire 4579 * chain at once. 4580 * (paranoia -- may not actually be needed) 4581 */ 4582 if (m_head->m_flags & M_FIRSTFRAG && 4583 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4584 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4585 m_head->m_pkthdr.csum_data + 16) { 4586 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4587 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4588 break; 4589 } 4590 } 4591 4592 /* 4593 * Pack the data into the transmit ring. If we 4594 * don't have room, set the OACTIVE flag and wait 4595 * for the NIC to drain the ring. 4596 */ 4597 if (bge_encap(sc, &m_head, &prodidx)) { 4598 if (m_head == NULL) 4599 break; 4600 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4601 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4602 break; 4603 } 4604 ++count; 4605 4606 /* 4607 * If there's a BPF listener, bounce a copy of this frame 4608 * to him. 4609 */ 4610 #ifdef ETHER_BPF_MTAP 4611 ETHER_BPF_MTAP(ifp, m_head); 4612 #else 4613 BPF_MTAP(ifp, m_head); 4614 #endif 4615 } 4616 4617 if (count > 0) { 4618 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4619 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4620 /* Transmit. */ 4621 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4622 /* 5700 b2 errata */ 4623 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4624 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4625 4626 sc->bge_tx_prodidx = prodidx; 4627 4628 /* 4629 * Set a timeout in case the chip goes out to lunch. 4630 */ 4631 sc->bge_timer = 5; 4632 } 4633 } 4634 4635 /* 4636 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4637 * to the mbuf data regions directly in the transmit descriptors. 4638 */ 4639 static void 4640 bge_start(struct ifnet *ifp) 4641 { 4642 struct bge_softc *sc; 4643 4644 sc = ifp->if_softc; 4645 BGE_LOCK(sc); 4646 bge_start_locked(ifp); 4647 BGE_UNLOCK(sc); 4648 } 4649 4650 static void 4651 bge_init_locked(struct bge_softc *sc) 4652 { 4653 struct ifnet *ifp; 4654 uint16_t *m; 4655 uint32_t mode; 4656 4657 BGE_LOCK_ASSERT(sc); 4658 4659 ifp = sc->bge_ifp; 4660 4661 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4662 return; 4663 4664 /* Cancel pending I/O and flush buffers. */ 4665 bge_stop(sc); 4666 4667 bge_stop_fw(sc); 4668 bge_sig_pre_reset(sc, BGE_RESET_START); 4669 bge_reset(sc); 4670 bge_sig_legacy(sc, BGE_RESET_START); 4671 bge_sig_post_reset(sc, BGE_RESET_START); 4672 4673 bge_chipinit(sc); 4674 4675 /* 4676 * Init the various state machines, ring 4677 * control blocks and firmware. 4678 */ 4679 if (bge_blockinit(sc)) { 4680 device_printf(sc->bge_dev, "initialization failure\n"); 4681 return; 4682 } 4683 4684 ifp = sc->bge_ifp; 4685 4686 /* Specify MTU. */ 4687 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4688 ETHER_HDR_LEN + ETHER_CRC_LEN + 4689 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4690 4691 /* Load our MAC address. */ 4692 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4693 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4694 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4695 4696 /* Program promiscuous mode. */ 4697 bge_setpromisc(sc); 4698 4699 /* Program multicast filter. */ 4700 bge_setmulti(sc); 4701 4702 /* Program VLAN tag stripping. */ 4703 bge_setvlan(sc); 4704 4705 /* Override UDP checksum offloading. */ 4706 if (sc->bge_forced_udpcsum == 0) 4707 sc->bge_csum_features &= ~CSUM_UDP; 4708 else 4709 sc->bge_csum_features |= CSUM_UDP; 4710 if (ifp->if_capabilities & IFCAP_TXCSUM && 4711 ifp->if_capenable & IFCAP_TXCSUM) { 4712 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4713 ifp->if_hwassist |= sc->bge_csum_features; 4714 } 4715 4716 /* Init RX ring. */ 4717 if (bge_init_rx_ring_std(sc) != 0) { 4718 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4719 bge_stop(sc); 4720 return; 4721 } 4722 4723 /* 4724 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4725 * memory to insure that the chip has in fact read the first 4726 * entry of the ring. 4727 */ 4728 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4729 uint32_t v, i; 4730 for (i = 0; i < 10; i++) { 4731 DELAY(20); 4732 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4733 if (v == (MCLBYTES - ETHER_ALIGN)) 4734 break; 4735 } 4736 if (i == 10) 4737 device_printf (sc->bge_dev, 4738 "5705 A0 chip failed to load RX ring\n"); 4739 } 4740 4741 /* Init jumbo RX ring. */ 4742 if (BGE_IS_JUMBO_CAPABLE(sc) && 4743 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4744 (MCLBYTES - ETHER_ALIGN)) { 4745 if (bge_init_rx_ring_jumbo(sc) != 0) { 4746 device_printf(sc->bge_dev, 4747 "no memory for jumbo Rx buffers.\n"); 4748 bge_stop(sc); 4749 return; 4750 } 4751 } 4752 4753 /* Init our RX return ring index. */ 4754 sc->bge_rx_saved_considx = 0; 4755 4756 /* Init our RX/TX stat counters. */ 4757 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4758 4759 /* Init TX ring. */ 4760 bge_init_tx_ring(sc); 4761 4762 /* Enable TX MAC state machine lockup fix. */ 4763 mode = CSR_READ_4(sc, BGE_TX_MODE); 4764 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 4765 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4766 /* Turn on transmitter. */ 4767 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4768 4769 /* Turn on receiver. */ 4770 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4771 4772 /* 4773 * Set the number of good frames to receive after RX MBUF 4774 * Low Watermark has been reached. After the RX MAC receives 4775 * this number of frames, it will drop subsequent incoming 4776 * frames until the MBUF High Watermark is reached. 4777 */ 4778 if (sc->bge_asicrev == BGE_ASICREV_BCM57765) 4779 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 4780 else 4781 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4782 4783 /* Clear MAC statistics. */ 4784 if (BGE_IS_5705_PLUS(sc)) 4785 bge_stats_clear_regs(sc); 4786 4787 /* Tell firmware we're alive. */ 4788 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4789 4790 #ifdef DEVICE_POLLING 4791 /* Disable interrupts if we are polling. */ 4792 if (ifp->if_capenable & IFCAP_POLLING) { 4793 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4794 BGE_PCIMISCCTL_MASK_PCI_INTR); 4795 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4796 } else 4797 #endif 4798 4799 /* Enable host interrupts. */ 4800 { 4801 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4802 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4803 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4804 } 4805 4806 bge_ifmedia_upd_locked(ifp); 4807 4808 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4809 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4810 4811 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4812 } 4813 4814 static void 4815 bge_init(void *xsc) 4816 { 4817 struct bge_softc *sc = xsc; 4818 4819 BGE_LOCK(sc); 4820 bge_init_locked(sc); 4821 BGE_UNLOCK(sc); 4822 } 4823 4824 /* 4825 * Set media options. 4826 */ 4827 static int 4828 bge_ifmedia_upd(struct ifnet *ifp) 4829 { 4830 struct bge_softc *sc = ifp->if_softc; 4831 int res; 4832 4833 BGE_LOCK(sc); 4834 res = bge_ifmedia_upd_locked(ifp); 4835 BGE_UNLOCK(sc); 4836 4837 return (res); 4838 } 4839 4840 static int 4841 bge_ifmedia_upd_locked(struct ifnet *ifp) 4842 { 4843 struct bge_softc *sc = ifp->if_softc; 4844 struct mii_data *mii; 4845 struct mii_softc *miisc; 4846 struct ifmedia *ifm; 4847 4848 BGE_LOCK_ASSERT(sc); 4849 4850 ifm = &sc->bge_ifmedia; 4851 4852 /* If this is a 1000baseX NIC, enable the TBI port. */ 4853 if (sc->bge_flags & BGE_FLAG_TBI) { 4854 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4855 return (EINVAL); 4856 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4857 case IFM_AUTO: 4858 /* 4859 * The BCM5704 ASIC appears to have a special 4860 * mechanism for programming the autoneg 4861 * advertisement registers in TBI mode. 4862 */ 4863 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4864 uint32_t sgdig; 4865 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4866 if (sgdig & BGE_SGDIGSTS_DONE) { 4867 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4868 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4869 sgdig |= BGE_SGDIGCFG_AUTO | 4870 BGE_SGDIGCFG_PAUSE_CAP | 4871 BGE_SGDIGCFG_ASYM_PAUSE; 4872 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4873 sgdig | BGE_SGDIGCFG_SEND); 4874 DELAY(5); 4875 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4876 } 4877 } 4878 break; 4879 case IFM_1000_SX: 4880 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4881 BGE_CLRBIT(sc, BGE_MAC_MODE, 4882 BGE_MACMODE_HALF_DUPLEX); 4883 } else { 4884 BGE_SETBIT(sc, BGE_MAC_MODE, 4885 BGE_MACMODE_HALF_DUPLEX); 4886 } 4887 break; 4888 default: 4889 return (EINVAL); 4890 } 4891 return (0); 4892 } 4893 4894 sc->bge_link_evt++; 4895 mii = device_get_softc(sc->bge_miibus); 4896 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4897 PHY_RESET(miisc); 4898 mii_mediachg(mii); 4899 4900 /* 4901 * Force an interrupt so that we will call bge_link_upd 4902 * if needed and clear any pending link state attention. 4903 * Without this we are not getting any further interrupts 4904 * for link state changes and thus will not UP the link and 4905 * not be able to send in bge_start_locked. The only 4906 * way to get things working was to receive a packet and 4907 * get an RX intr. 4908 * bge_tick should help for fiber cards and we might not 4909 * need to do this here if BGE_FLAG_TBI is set but as 4910 * we poll for fiber anyway it should not harm. 4911 */ 4912 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4913 sc->bge_flags & BGE_FLAG_5788) 4914 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4915 else 4916 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4917 4918 return (0); 4919 } 4920 4921 /* 4922 * Report current media status. 4923 */ 4924 static void 4925 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4926 { 4927 struct bge_softc *sc = ifp->if_softc; 4928 struct mii_data *mii; 4929 4930 BGE_LOCK(sc); 4931 4932 if (sc->bge_flags & BGE_FLAG_TBI) { 4933 ifmr->ifm_status = IFM_AVALID; 4934 ifmr->ifm_active = IFM_ETHER; 4935 if (CSR_READ_4(sc, BGE_MAC_STS) & 4936 BGE_MACSTAT_TBI_PCS_SYNCHED) 4937 ifmr->ifm_status |= IFM_ACTIVE; 4938 else { 4939 ifmr->ifm_active |= IFM_NONE; 4940 BGE_UNLOCK(sc); 4941 return; 4942 } 4943 ifmr->ifm_active |= IFM_1000_SX; 4944 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4945 ifmr->ifm_active |= IFM_HDX; 4946 else 4947 ifmr->ifm_active |= IFM_FDX; 4948 BGE_UNLOCK(sc); 4949 return; 4950 } 4951 4952 mii = device_get_softc(sc->bge_miibus); 4953 mii_pollstat(mii); 4954 ifmr->ifm_active = mii->mii_media_active; 4955 ifmr->ifm_status = mii->mii_media_status; 4956 4957 BGE_UNLOCK(sc); 4958 } 4959 4960 static int 4961 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4962 { 4963 struct bge_softc *sc = ifp->if_softc; 4964 struct ifreq *ifr = (struct ifreq *) data; 4965 struct mii_data *mii; 4966 int flags, mask, error = 0; 4967 4968 switch (command) { 4969 case SIOCSIFMTU: 4970 if (BGE_IS_JUMBO_CAPABLE(sc) || 4971 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 4972 if (ifr->ifr_mtu < ETHERMIN || 4973 ifr->ifr_mtu > BGE_JUMBO_MTU) { 4974 error = EINVAL; 4975 break; 4976 } 4977 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 4978 error = EINVAL; 4979 break; 4980 } 4981 BGE_LOCK(sc); 4982 if (ifp->if_mtu != ifr->ifr_mtu) { 4983 ifp->if_mtu = ifr->ifr_mtu; 4984 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4985 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4986 bge_init_locked(sc); 4987 } 4988 } 4989 BGE_UNLOCK(sc); 4990 break; 4991 case SIOCSIFFLAGS: 4992 BGE_LOCK(sc); 4993 if (ifp->if_flags & IFF_UP) { 4994 /* 4995 * If only the state of the PROMISC flag changed, 4996 * then just use the 'set promisc mode' command 4997 * instead of reinitializing the entire NIC. Doing 4998 * a full re-init means reloading the firmware and 4999 * waiting for it to start up, which may take a 5000 * second or two. Similarly for ALLMULTI. 5001 */ 5002 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5003 flags = ifp->if_flags ^ sc->bge_if_flags; 5004 if (flags & IFF_PROMISC) 5005 bge_setpromisc(sc); 5006 if (flags & IFF_ALLMULTI) 5007 bge_setmulti(sc); 5008 } else 5009 bge_init_locked(sc); 5010 } else { 5011 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5012 bge_stop(sc); 5013 } 5014 } 5015 sc->bge_if_flags = ifp->if_flags; 5016 BGE_UNLOCK(sc); 5017 error = 0; 5018 break; 5019 case SIOCADDMULTI: 5020 case SIOCDELMULTI: 5021 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5022 BGE_LOCK(sc); 5023 bge_setmulti(sc); 5024 BGE_UNLOCK(sc); 5025 error = 0; 5026 } 5027 break; 5028 case SIOCSIFMEDIA: 5029 case SIOCGIFMEDIA: 5030 if (sc->bge_flags & BGE_FLAG_TBI) { 5031 error = ifmedia_ioctl(ifp, ifr, 5032 &sc->bge_ifmedia, command); 5033 } else { 5034 mii = device_get_softc(sc->bge_miibus); 5035 error = ifmedia_ioctl(ifp, ifr, 5036 &mii->mii_media, command); 5037 } 5038 break; 5039 case SIOCSIFCAP: 5040 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5041 #ifdef DEVICE_POLLING 5042 if (mask & IFCAP_POLLING) { 5043 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5044 error = ether_poll_register(bge_poll, ifp); 5045 if (error) 5046 return (error); 5047 BGE_LOCK(sc); 5048 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5049 BGE_PCIMISCCTL_MASK_PCI_INTR); 5050 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5051 ifp->if_capenable |= IFCAP_POLLING; 5052 BGE_UNLOCK(sc); 5053 } else { 5054 error = ether_poll_deregister(ifp); 5055 /* Enable interrupt even in error case */ 5056 BGE_LOCK(sc); 5057 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5058 BGE_PCIMISCCTL_MASK_PCI_INTR); 5059 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5060 ifp->if_capenable &= ~IFCAP_POLLING; 5061 BGE_UNLOCK(sc); 5062 } 5063 } 5064 #endif 5065 if ((mask & IFCAP_TXCSUM) != 0 && 5066 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5067 ifp->if_capenable ^= IFCAP_TXCSUM; 5068 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5069 ifp->if_hwassist |= sc->bge_csum_features; 5070 else 5071 ifp->if_hwassist &= ~sc->bge_csum_features; 5072 } 5073 5074 if ((mask & IFCAP_RXCSUM) != 0 && 5075 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5076 ifp->if_capenable ^= IFCAP_RXCSUM; 5077 5078 if ((mask & IFCAP_TSO4) != 0 && 5079 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5080 ifp->if_capenable ^= IFCAP_TSO4; 5081 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5082 ifp->if_hwassist |= CSUM_TSO; 5083 else 5084 ifp->if_hwassist &= ~CSUM_TSO; 5085 } 5086 5087 if (mask & IFCAP_VLAN_MTU) { 5088 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5089 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5090 bge_init(sc); 5091 } 5092 5093 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5094 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5095 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5096 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5097 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5098 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5099 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5100 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5101 BGE_LOCK(sc); 5102 bge_setvlan(sc); 5103 BGE_UNLOCK(sc); 5104 } 5105 #ifdef VLAN_CAPABILITIES 5106 VLAN_CAPABILITIES(ifp); 5107 #endif 5108 break; 5109 default: 5110 error = ether_ioctl(ifp, command, data); 5111 break; 5112 } 5113 5114 return (error); 5115 } 5116 5117 static void 5118 bge_watchdog(struct bge_softc *sc) 5119 { 5120 struct ifnet *ifp; 5121 5122 BGE_LOCK_ASSERT(sc); 5123 5124 if (sc->bge_timer == 0 || --sc->bge_timer) 5125 return; 5126 5127 ifp = sc->bge_ifp; 5128 5129 if_printf(ifp, "watchdog timeout -- resetting\n"); 5130 5131 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5132 bge_init_locked(sc); 5133 5134 ifp->if_oerrors++; 5135 } 5136 5137 static void 5138 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5139 { 5140 int i; 5141 5142 BGE_CLRBIT(sc, reg, bit); 5143 5144 for (i = 0; i < BGE_TIMEOUT; i++) { 5145 if ((CSR_READ_4(sc, reg) & bit) == 0) 5146 return; 5147 DELAY(100); 5148 } 5149 } 5150 5151 /* 5152 * Stop the adapter and free any mbufs allocated to the 5153 * RX and TX lists. 5154 */ 5155 static void 5156 bge_stop(struct bge_softc *sc) 5157 { 5158 struct ifnet *ifp; 5159 5160 BGE_LOCK_ASSERT(sc); 5161 5162 ifp = sc->bge_ifp; 5163 5164 callout_stop(&sc->bge_stat_ch); 5165 5166 /* Disable host interrupts. */ 5167 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5168 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5169 5170 /* 5171 * Tell firmware we're shutting down. 5172 */ 5173 bge_stop_fw(sc); 5174 bge_sig_pre_reset(sc, BGE_RESET_STOP); 5175 5176 /* 5177 * Disable all of the receiver blocks. 5178 */ 5179 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5180 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5181 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5182 if (BGE_IS_5700_FAMILY(sc)) 5183 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5184 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5185 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5186 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5187 5188 /* 5189 * Disable all of the transmit blocks. 5190 */ 5191 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5192 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5193 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5194 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5195 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5196 if (BGE_IS_5700_FAMILY(sc)) 5197 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5198 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5199 5200 /* 5201 * Shut down all of the memory managers and related 5202 * state machines. 5203 */ 5204 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5205 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5206 if (BGE_IS_5700_FAMILY(sc)) 5207 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5208 5209 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5210 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5211 if (!(BGE_IS_5705_PLUS(sc))) { 5212 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5213 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5214 } 5215 /* Update MAC statistics. */ 5216 if (BGE_IS_5705_PLUS(sc)) 5217 bge_stats_update_regs(sc); 5218 5219 bge_reset(sc); 5220 bge_sig_legacy(sc, BGE_RESET_STOP); 5221 bge_sig_post_reset(sc, BGE_RESET_STOP); 5222 5223 /* 5224 * Keep the ASF firmware running if up. 5225 */ 5226 if (sc->bge_asf_mode & ASF_STACKUP) 5227 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5228 else 5229 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5230 5231 /* Free the RX lists. */ 5232 bge_free_rx_ring_std(sc); 5233 5234 /* Free jumbo RX list. */ 5235 if (BGE_IS_JUMBO_CAPABLE(sc)) 5236 bge_free_rx_ring_jumbo(sc); 5237 5238 /* Free TX buffers. */ 5239 bge_free_tx_ring(sc); 5240 5241 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5242 5243 /* Clear MAC's link state (PHY may still have link UP). */ 5244 if (bootverbose && sc->bge_link) 5245 if_printf(sc->bge_ifp, "link DOWN\n"); 5246 sc->bge_link = 0; 5247 5248 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5249 } 5250 5251 /* 5252 * Stop all chip I/O so that the kernel's probe routines don't 5253 * get confused by errant DMAs when rebooting. 5254 */ 5255 static int 5256 bge_shutdown(device_t dev) 5257 { 5258 struct bge_softc *sc; 5259 5260 sc = device_get_softc(dev); 5261 BGE_LOCK(sc); 5262 bge_stop(sc); 5263 bge_reset(sc); 5264 BGE_UNLOCK(sc); 5265 5266 return (0); 5267 } 5268 5269 static int 5270 bge_suspend(device_t dev) 5271 { 5272 struct bge_softc *sc; 5273 5274 sc = device_get_softc(dev); 5275 BGE_LOCK(sc); 5276 bge_stop(sc); 5277 BGE_UNLOCK(sc); 5278 5279 return (0); 5280 } 5281 5282 static int 5283 bge_resume(device_t dev) 5284 { 5285 struct bge_softc *sc; 5286 struct ifnet *ifp; 5287 5288 sc = device_get_softc(dev); 5289 BGE_LOCK(sc); 5290 ifp = sc->bge_ifp; 5291 if (ifp->if_flags & IFF_UP) { 5292 bge_init_locked(sc); 5293 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5294 bge_start_locked(ifp); 5295 } 5296 BGE_UNLOCK(sc); 5297 5298 return (0); 5299 } 5300 5301 static void 5302 bge_link_upd(struct bge_softc *sc) 5303 { 5304 struct mii_data *mii; 5305 uint32_t link, status; 5306 5307 BGE_LOCK_ASSERT(sc); 5308 5309 /* Clear 'pending link event' flag. */ 5310 sc->bge_link_evt = 0; 5311 5312 /* 5313 * Process link state changes. 5314 * Grrr. The link status word in the status block does 5315 * not work correctly on the BCM5700 rev AX and BX chips, 5316 * according to all available information. Hence, we have 5317 * to enable MII interrupts in order to properly obtain 5318 * async link changes. Unfortunately, this also means that 5319 * we have to read the MAC status register to detect link 5320 * changes, thereby adding an additional register access to 5321 * the interrupt handler. 5322 * 5323 * XXX: perhaps link state detection procedure used for 5324 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5325 */ 5326 5327 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5328 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5329 status = CSR_READ_4(sc, BGE_MAC_STS); 5330 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5331 mii = device_get_softc(sc->bge_miibus); 5332 mii_pollstat(mii); 5333 if (!sc->bge_link && 5334 mii->mii_media_status & IFM_ACTIVE && 5335 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5336 sc->bge_link++; 5337 if (bootverbose) 5338 if_printf(sc->bge_ifp, "link UP\n"); 5339 } else if (sc->bge_link && 5340 (!(mii->mii_media_status & IFM_ACTIVE) || 5341 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5342 sc->bge_link = 0; 5343 if (bootverbose) 5344 if_printf(sc->bge_ifp, "link DOWN\n"); 5345 } 5346 5347 /* Clear the interrupt. */ 5348 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5349 BGE_EVTENB_MI_INTERRUPT); 5350 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 5351 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 5352 BRGPHY_INTRS); 5353 } 5354 return; 5355 } 5356 5357 if (sc->bge_flags & BGE_FLAG_TBI) { 5358 status = CSR_READ_4(sc, BGE_MAC_STS); 5359 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5360 if (!sc->bge_link) { 5361 sc->bge_link++; 5362 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 5363 BGE_CLRBIT(sc, BGE_MAC_MODE, 5364 BGE_MACMODE_TBI_SEND_CFGS); 5365 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5366 if (bootverbose) 5367 if_printf(sc->bge_ifp, "link UP\n"); 5368 if_link_state_change(sc->bge_ifp, 5369 LINK_STATE_UP); 5370 } 5371 } else if (sc->bge_link) { 5372 sc->bge_link = 0; 5373 if (bootverbose) 5374 if_printf(sc->bge_ifp, "link DOWN\n"); 5375 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 5376 } 5377 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 5378 /* 5379 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 5380 * in status word always set. Workaround this bug by reading 5381 * PHY link status directly. 5382 */ 5383 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 5384 5385 if (link != sc->bge_link || 5386 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 5387 mii = device_get_softc(sc->bge_miibus); 5388 mii_pollstat(mii); 5389 if (!sc->bge_link && 5390 mii->mii_media_status & IFM_ACTIVE && 5391 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5392 sc->bge_link++; 5393 if (bootverbose) 5394 if_printf(sc->bge_ifp, "link UP\n"); 5395 } else if (sc->bge_link && 5396 (!(mii->mii_media_status & IFM_ACTIVE) || 5397 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5398 sc->bge_link = 0; 5399 if (bootverbose) 5400 if_printf(sc->bge_ifp, "link DOWN\n"); 5401 } 5402 } 5403 } else { 5404 /* 5405 * For controllers that call mii_tick, we have to poll 5406 * link status. 5407 */ 5408 mii = device_get_softc(sc->bge_miibus); 5409 mii_pollstat(mii); 5410 bge_miibus_statchg(sc->bge_dev); 5411 } 5412 5413 /* Clear the attention. */ 5414 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 5415 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 5416 BGE_MACSTAT_LINK_CHANGED); 5417 } 5418 5419 static void 5420 bge_add_sysctls(struct bge_softc *sc) 5421 { 5422 struct sysctl_ctx_list *ctx; 5423 struct sysctl_oid_list *children; 5424 char tn[32]; 5425 int unit; 5426 5427 ctx = device_get_sysctl_ctx(sc->bge_dev); 5428 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 5429 5430 #ifdef BGE_REGISTER_DEBUG 5431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 5432 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 5433 "Debug Information"); 5434 5435 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 5436 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 5437 "Register Read"); 5438 5439 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 5440 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 5441 "Memory Read"); 5442 5443 #endif 5444 5445 unit = device_get_unit(sc->bge_dev); 5446 /* 5447 * A common design characteristic for many Broadcom client controllers 5448 * is that they only support a single outstanding DMA read operation 5449 * on the PCIe bus. This means that it will take twice as long to fetch 5450 * a TX frame that is split into header and payload buffers as it does 5451 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 5452 * these controllers, coalescing buffers to reduce the number of memory 5453 * reads is effective way to get maximum performance(about 940Mbps). 5454 * Without collapsing TX buffers the maximum TCP bulk transfer 5455 * performance is about 850Mbps. However forcing coalescing mbufs 5456 * consumes a lot of CPU cycles, so leave it off by default. 5457 */ 5458 sc->bge_forced_collapse = 0; 5459 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 5460 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 5461 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 5462 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 5463 "Number of fragmented TX buffers of a frame allowed before " 5464 "forced collapsing"); 5465 5466 /* 5467 * It seems all Broadcom controllers have a bug that can generate UDP 5468 * datagrams with checksum value 0 when TX UDP checksum offloading is 5469 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 5470 * Even though the probability of generating such UDP datagrams is 5471 * low, I don't want to see FreeBSD boxes to inject such datagrams 5472 * into network so disable UDP checksum offloading by default. Users 5473 * still override this behavior by setting a sysctl variable, 5474 * dev.bge.0.forced_udpcsum. 5475 */ 5476 sc->bge_forced_udpcsum = 0; 5477 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 5478 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 5479 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 5480 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 5481 "Enable UDP checksum offloading even if controller can " 5482 "generate UDP checksum value 0"); 5483 5484 if (BGE_IS_5705_PLUS(sc)) 5485 bge_add_sysctl_stats_regs(sc, ctx, children); 5486 else 5487 bge_add_sysctl_stats(sc, ctx, children); 5488 } 5489 5490 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 5491 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 5492 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 5493 desc) 5494 5495 static void 5496 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5497 struct sysctl_oid_list *parent) 5498 { 5499 struct sysctl_oid *tree; 5500 struct sysctl_oid_list *children, *schildren; 5501 5502 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5503 NULL, "BGE Statistics"); 5504 schildren = children = SYSCTL_CHILDREN(tree); 5505 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 5506 children, COSFramesDroppedDueToFilters, 5507 "FramesDroppedDueToFilters"); 5508 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 5509 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 5510 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 5511 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 5512 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 5513 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 5514 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 5515 children, ifInDiscards, "InputDiscards"); 5516 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 5517 children, ifInErrors, "InputErrors"); 5518 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 5519 children, nicRecvThresholdHit, "RecvThresholdHit"); 5520 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 5521 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 5522 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 5523 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 5524 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 5525 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 5526 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 5527 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 5528 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 5529 children, nicRingStatusUpdate, "RingStatusUpdate"); 5530 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 5531 children, nicInterrupts, "Interrupts"); 5532 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 5533 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 5534 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 5535 children, nicSendThresholdHit, "SendThresholdHit"); 5536 5537 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 5538 NULL, "BGE RX Statistics"); 5539 children = SYSCTL_CHILDREN(tree); 5540 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 5541 children, rxstats.ifHCInOctets, "ifHCInOctets"); 5542 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 5543 children, rxstats.etherStatsFragments, "Fragments"); 5544 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 5545 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 5546 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 5547 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 5548 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 5549 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 5550 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 5551 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 5552 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 5553 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 5554 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 5555 children, rxstats.xoffPauseFramesReceived, 5556 "xoffPauseFramesReceived"); 5557 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5558 children, rxstats.macControlFramesReceived, 5559 "ControlFramesReceived"); 5560 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5561 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5562 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5563 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5564 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5565 children, rxstats.etherStatsJabbers, "Jabbers"); 5566 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5567 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5568 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5569 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5570 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5571 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5572 5573 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5574 NULL, "BGE TX Statistics"); 5575 children = SYSCTL_CHILDREN(tree); 5576 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5577 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 5578 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5579 children, txstats.etherStatsCollisions, "Collisions"); 5580 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5581 children, txstats.outXonSent, "XonSent"); 5582 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5583 children, txstats.outXoffSent, "XoffSent"); 5584 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5585 children, txstats.flowControlDone, "flowControlDone"); 5586 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5587 children, txstats.dot3StatsInternalMacTransmitErrors, 5588 "InternalMacTransmitErrors"); 5589 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5590 children, txstats.dot3StatsSingleCollisionFrames, 5591 "SingleCollisionFrames"); 5592 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5593 children, txstats.dot3StatsMultipleCollisionFrames, 5594 "MultipleCollisionFrames"); 5595 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5596 children, txstats.dot3StatsDeferredTransmissions, 5597 "DeferredTransmissions"); 5598 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5599 children, txstats.dot3StatsExcessiveCollisions, 5600 "ExcessiveCollisions"); 5601 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5602 children, txstats.dot3StatsLateCollisions, 5603 "LateCollisions"); 5604 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5605 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 5606 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5607 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5608 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5609 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5610 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5611 children, txstats.dot3StatsCarrierSenseErrors, 5612 "CarrierSenseErrors"); 5613 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5614 children, txstats.ifOutDiscards, "Discards"); 5615 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5616 children, txstats.ifOutErrors, "Errors"); 5617 } 5618 5619 #undef BGE_SYSCTL_STAT 5620 5621 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 5622 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 5623 5624 static void 5625 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5626 struct sysctl_oid_list *parent) 5627 { 5628 struct sysctl_oid *tree; 5629 struct sysctl_oid_list *child, *schild; 5630 struct bge_mac_stats *stats; 5631 5632 stats = &sc->bge_mac_stats; 5633 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5634 NULL, "BGE Statistics"); 5635 schild = child = SYSCTL_CHILDREN(tree); 5636 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 5637 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 5638 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 5639 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 5640 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 5641 &stats->DmaWriteHighPriQueueFull, 5642 "NIC DMA Write High Priority Queue Full"); 5643 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 5644 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 5645 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 5646 &stats->InputDiscards, "Discarded Input Frames"); 5647 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 5648 &stats->InputErrors, "Input Errors"); 5649 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 5650 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 5651 5652 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 5653 NULL, "BGE RX Statistics"); 5654 child = SYSCTL_CHILDREN(tree); 5655 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 5656 &stats->ifHCInOctets, "Inbound Octets"); 5657 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 5658 &stats->etherStatsFragments, "Fragments"); 5659 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5660 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 5661 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5662 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 5663 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5664 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 5665 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 5666 &stats->dot3StatsFCSErrors, "FCS Errors"); 5667 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 5668 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 5669 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 5670 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 5671 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 5672 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 5673 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 5674 &stats->macControlFramesReceived, "MAC Control Frames Received"); 5675 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 5676 &stats->xoffStateEntered, "XOFF State Entered"); 5677 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 5678 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 5679 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 5680 &stats->etherStatsJabbers, "Jabbers"); 5681 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 5682 &stats->etherStatsUndersizePkts, "Undersized Packets"); 5683 5684 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 5685 NULL, "BGE TX Statistics"); 5686 child = SYSCTL_CHILDREN(tree); 5687 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 5688 &stats->ifHCOutOctets, "Outbound Octets"); 5689 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 5690 &stats->etherStatsCollisions, "TX Collisions"); 5691 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 5692 &stats->outXonSent, "XON Sent"); 5693 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 5694 &stats->outXoffSent, "XOFF Sent"); 5695 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 5696 &stats->dot3StatsInternalMacTransmitErrors, 5697 "Internal MAC TX Errors"); 5698 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 5699 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 5700 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 5701 &stats->dot3StatsMultipleCollisionFrames, 5702 "Multiple Collision Frames"); 5703 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 5704 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 5705 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 5706 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 5707 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 5708 &stats->dot3StatsLateCollisions, "Late Collisions"); 5709 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5710 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 5711 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5712 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 5713 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5714 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 5715 } 5716 5717 #undef BGE_SYSCTL_STAT_ADD64 5718 5719 static int 5720 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5721 { 5722 struct bge_softc *sc; 5723 uint32_t result; 5724 int offset; 5725 5726 sc = (struct bge_softc *)arg1; 5727 offset = arg2; 5728 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5729 offsetof(bge_hostaddr, bge_addr_lo)); 5730 return (sysctl_handle_int(oidp, &result, 0, req)); 5731 } 5732 5733 #ifdef BGE_REGISTER_DEBUG 5734 static int 5735 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5736 { 5737 struct bge_softc *sc; 5738 uint16_t *sbdata; 5739 int error; 5740 int result; 5741 int i, j; 5742 5743 result = -1; 5744 error = sysctl_handle_int(oidp, &result, 0, req); 5745 if (error || (req->newptr == NULL)) 5746 return (error); 5747 5748 if (result == 1) { 5749 sc = (struct bge_softc *)arg1; 5750 5751 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5752 printf("Status Block:\n"); 5753 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5754 printf("%06x:", i); 5755 for (j = 0; j < 8; j++) { 5756 printf(" %04x", sbdata[i]); 5757 i += 4; 5758 } 5759 printf("\n"); 5760 } 5761 5762 printf("Registers:\n"); 5763 for (i = 0x800; i < 0xA00; ) { 5764 printf("%06x:", i); 5765 for (j = 0; j < 8; j++) { 5766 printf(" %08x", CSR_READ_4(sc, i)); 5767 i += 4; 5768 } 5769 printf("\n"); 5770 } 5771 5772 printf("Hardware Flags:\n"); 5773 if (BGE_IS_5755_PLUS(sc)) 5774 printf(" - 5755 Plus\n"); 5775 if (BGE_IS_575X_PLUS(sc)) 5776 printf(" - 575X Plus\n"); 5777 if (BGE_IS_5705_PLUS(sc)) 5778 printf(" - 5705 Plus\n"); 5779 if (BGE_IS_5714_FAMILY(sc)) 5780 printf(" - 5714 Family\n"); 5781 if (BGE_IS_5700_FAMILY(sc)) 5782 printf(" - 5700 Family\n"); 5783 if (sc->bge_flags & BGE_FLAG_JUMBO) 5784 printf(" - Supports Jumbo Frames\n"); 5785 if (sc->bge_flags & BGE_FLAG_PCIX) 5786 printf(" - PCI-X Bus\n"); 5787 if (sc->bge_flags & BGE_FLAG_PCIE) 5788 printf(" - PCI Express Bus\n"); 5789 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 5790 printf(" - No 3 LEDs\n"); 5791 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5792 printf(" - RX Alignment Bug\n"); 5793 } 5794 5795 return (error); 5796 } 5797 5798 static int 5799 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5800 { 5801 struct bge_softc *sc; 5802 int error; 5803 uint16_t result; 5804 uint32_t val; 5805 5806 result = -1; 5807 error = sysctl_handle_int(oidp, &result, 0, req); 5808 if (error || (req->newptr == NULL)) 5809 return (error); 5810 5811 if (result < 0x8000) { 5812 sc = (struct bge_softc *)arg1; 5813 val = CSR_READ_4(sc, result); 5814 printf("reg 0x%06X = 0x%08X\n", result, val); 5815 } 5816 5817 return (error); 5818 } 5819 5820 static int 5821 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5822 { 5823 struct bge_softc *sc; 5824 int error; 5825 uint16_t result; 5826 uint32_t val; 5827 5828 result = -1; 5829 error = sysctl_handle_int(oidp, &result, 0, req); 5830 if (error || (req->newptr == NULL)) 5831 return (error); 5832 5833 if (result < 0x8000) { 5834 sc = (struct bge_softc *)arg1; 5835 val = bge_readmem_ind(sc, result); 5836 printf("mem 0x%06X = 0x%08X\n", result, val); 5837 } 5838 5839 return (error); 5840 } 5841 #endif 5842 5843 static int 5844 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5845 { 5846 5847 if (sc->bge_flags & BGE_FLAG_EADDR) 5848 return (1); 5849 5850 #ifdef __sparc64__ 5851 OF_getetheraddr(sc->bge_dev, ether_addr); 5852 return (0); 5853 #endif 5854 return (1); 5855 } 5856 5857 static int 5858 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5859 { 5860 uint32_t mac_addr; 5861 5862 mac_addr = bge_readmem_ind(sc, 0x0c14); 5863 if ((mac_addr >> 16) == 0x484b) { 5864 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5865 ether_addr[1] = (uint8_t)mac_addr; 5866 mac_addr = bge_readmem_ind(sc, 0x0c18); 5867 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5868 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5869 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5870 ether_addr[5] = (uint8_t)mac_addr; 5871 return (0); 5872 } 5873 return (1); 5874 } 5875 5876 static int 5877 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5878 { 5879 int mac_offset = BGE_EE_MAC_OFFSET; 5880 5881 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5882 mac_offset = BGE_EE_MAC_OFFSET_5906; 5883 5884 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5885 ETHER_ADDR_LEN)); 5886 } 5887 5888 static int 5889 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5890 { 5891 5892 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5893 return (1); 5894 5895 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5896 ETHER_ADDR_LEN)); 5897 } 5898 5899 static int 5900 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5901 { 5902 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5903 /* NOTE: Order is critical */ 5904 bge_get_eaddr_fw, 5905 bge_get_eaddr_mem, 5906 bge_get_eaddr_nvram, 5907 bge_get_eaddr_eeprom, 5908 NULL 5909 }; 5910 const bge_eaddr_fcn_t *func; 5911 5912 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5913 if ((*func)(sc, eaddr) == 0) 5914 break; 5915 } 5916 return (*func == NULL ? ENXIO : 0); 5917 } 5918