1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <vm/vm.h> /* for vtophys */ 98 #include <vm/pmap.h> /* for vtophys */ 99 #include <machine/clock.h> /* for DELAY */ 100 #include <machine/bus_memio.h> 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include <dev/mii/miidevs.h> 109 #include <dev/mii/brgphyreg.h> 110 111 #include <pci/pcireg.h> 112 #include <pci/pcivar.h> 113 114 #include <dev/bge/if_bgereg.h> 115 116 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 117 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #if !defined(lint) 124 static const char rcsid[] = 125 "$FreeBSD$"; 126 #endif 127 128 /* 129 * Various supported device vendors/types and their names. Note: the 130 * spec seems to indicate that the hardware still has Alteon's vendor 131 * ID burned into it, though it will always be overriden by the vendor 132 * ID in the EEPROM. Just to be safe, we cover all possibilities. 133 */ 134 135 static struct bge_type bge_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 141 "Broadcom BCM5700 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 143 "Broadcom BCM5701 Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 145 "Broadcom BCM5702X Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { SK_VENDORID, SK_DEVICEID_ALTIMA, 149 "SysKonnect Gigabit Ethernet" }, 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 151 "Altima AC1000 Gigabit Ethernet" }, 152 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 153 "Altima AC9100 Gigabit Ethernet" }, 154 { 0, 0, NULL } 155 }; 156 157 static int bge_probe (device_t); 158 static int bge_attach (device_t); 159 static int bge_detach (device_t); 160 static void bge_release_resources 161 (struct bge_softc *); 162 static void bge_txeof (struct bge_softc *); 163 static void bge_rxeof (struct bge_softc *); 164 165 static void bge_tick (void *); 166 static void bge_stats_update (struct bge_softc *); 167 static int bge_encap (struct bge_softc *, struct mbuf *, 168 u_int32_t *); 169 170 static void bge_intr (void *); 171 static void bge_start (struct ifnet *); 172 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 173 static void bge_init (void *); 174 static void bge_stop (struct bge_softc *); 175 static void bge_watchdog (struct ifnet *); 176 static void bge_shutdown (device_t); 177 static int bge_ifmedia_upd (struct ifnet *); 178 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 179 180 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 181 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 182 183 static u_int32_t bge_crc (caddr_t); 184 static void bge_setmulti (struct bge_softc *); 185 186 static void bge_handle_events (struct bge_softc *); 187 static int bge_alloc_jumbo_mem (struct bge_softc *); 188 static void bge_free_jumbo_mem (struct bge_softc *); 189 static void *bge_jalloc (struct bge_softc *); 190 static void bge_jfree (void *, void *); 191 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 192 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 193 static int bge_init_rx_ring_std (struct bge_softc *); 194 static void bge_free_rx_ring_std (struct bge_softc *); 195 static int bge_init_rx_ring_jumbo (struct bge_softc *); 196 static void bge_free_rx_ring_jumbo (struct bge_softc *); 197 static void bge_free_tx_ring (struct bge_softc *); 198 static int bge_init_tx_ring (struct bge_softc *); 199 200 static int bge_chipinit (struct bge_softc *); 201 static int bge_blockinit (struct bge_softc *); 202 203 #ifdef notdef 204 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 205 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 206 static void bge_vpd_read (struct bge_softc *); 207 #endif 208 209 static u_int32_t bge_readmem_ind 210 (struct bge_softc *, int); 211 static void bge_writemem_ind (struct bge_softc *, int, int); 212 #ifdef notdef 213 static u_int32_t bge_readreg_ind 214 (struct bge_softc *, int); 215 #endif 216 static void bge_writereg_ind (struct bge_softc *, int, int); 217 218 static int bge_miibus_readreg (device_t, int, int); 219 static int bge_miibus_writereg (device_t, int, int, int); 220 static void bge_miibus_statchg (device_t); 221 222 static void bge_reset (struct bge_softc *); 223 static void bge_phy_hack (struct bge_softc *); 224 225 static device_method_t bge_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, bge_probe), 228 DEVMETHOD(device_attach, bge_attach), 229 DEVMETHOD(device_detach, bge_detach), 230 DEVMETHOD(device_shutdown, bge_shutdown), 231 232 /* bus interface */ 233 DEVMETHOD(bus_print_child, bus_generic_print_child), 234 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 235 236 /* MII interface */ 237 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 238 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 239 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 240 241 { 0, 0 } 242 }; 243 244 static driver_t bge_driver = { 245 "bge", 246 bge_methods, 247 sizeof(struct bge_softc) 248 }; 249 250 static devclass_t bge_devclass; 251 252 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 253 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 254 255 static u_int32_t 256 bge_readmem_ind(sc, off) 257 struct bge_softc *sc; 258 int off; 259 { 260 device_t dev; 261 262 dev = sc->bge_dev; 263 264 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 265 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 266 } 267 268 static void 269 bge_writemem_ind(sc, off, val) 270 struct bge_softc *sc; 271 int off, val; 272 { 273 device_t dev; 274 275 dev = sc->bge_dev; 276 277 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 278 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 279 280 return; 281 } 282 283 #ifdef notdef 284 static u_int32_t 285 bge_readreg_ind(sc, off) 286 struct bge_softc *sc; 287 int off; 288 { 289 device_t dev; 290 291 dev = sc->bge_dev; 292 293 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 294 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 295 } 296 #endif 297 298 static void 299 bge_writereg_ind(sc, off, val) 300 struct bge_softc *sc; 301 int off, val; 302 { 303 device_t dev; 304 305 dev = sc->bge_dev; 306 307 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 308 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 309 310 return; 311 } 312 313 #ifdef notdef 314 static u_int8_t 315 bge_vpd_readbyte(sc, addr) 316 struct bge_softc *sc; 317 int addr; 318 { 319 int i; 320 device_t dev; 321 u_int32_t val; 322 323 dev = sc->bge_dev; 324 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 325 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 326 DELAY(10); 327 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 328 break; 329 } 330 331 if (i == BGE_TIMEOUT) { 332 printf("bge%d: VPD read timed out\n", sc->bge_unit); 333 return(0); 334 } 335 336 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 337 338 return((val >> ((addr % 4) * 8)) & 0xFF); 339 } 340 341 static void 342 bge_vpd_read_res(sc, res, addr) 343 struct bge_softc *sc; 344 struct vpd_res *res; 345 int addr; 346 { 347 int i; 348 u_int8_t *ptr; 349 350 ptr = (u_int8_t *)res; 351 for (i = 0; i < sizeof(struct vpd_res); i++) 352 ptr[i] = bge_vpd_readbyte(sc, i + addr); 353 354 return; 355 } 356 357 static void 358 bge_vpd_read(sc) 359 struct bge_softc *sc; 360 { 361 int pos = 0, i; 362 struct vpd_res res; 363 364 if (sc->bge_vpd_prodname != NULL) 365 free(sc->bge_vpd_prodname, M_DEVBUF); 366 if (sc->bge_vpd_readonly != NULL) 367 free(sc->bge_vpd_readonly, M_DEVBUF); 368 sc->bge_vpd_prodname = NULL; 369 sc->bge_vpd_readonly = NULL; 370 371 bge_vpd_read_res(sc, &res, pos); 372 373 if (res.vr_id != VPD_RES_ID) { 374 printf("bge%d: bad VPD resource id: expected %x got %x\n", 375 sc->bge_unit, VPD_RES_ID, res.vr_id); 376 return; 377 } 378 379 pos += sizeof(res); 380 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 381 for (i = 0; i < res.vr_len; i++) 382 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 383 sc->bge_vpd_prodname[i] = '\0'; 384 pos += i; 385 386 bge_vpd_read_res(sc, &res, pos); 387 388 if (res.vr_id != VPD_RES_READ) { 389 printf("bge%d: bad VPD resource id: expected %x got %x\n", 390 sc->bge_unit, VPD_RES_READ, res.vr_id); 391 return; 392 } 393 394 pos += sizeof(res); 395 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 396 for (i = 0; i < res.vr_len + 1; i++) 397 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 398 399 return; 400 } 401 #endif 402 403 /* 404 * Read a byte of data stored in the EEPROM at address 'addr.' The 405 * BCM570x supports both the traditional bitbang interface and an 406 * auto access interface for reading the EEPROM. We use the auto 407 * access method. 408 */ 409 static u_int8_t 410 bge_eeprom_getbyte(sc, addr, dest) 411 struct bge_softc *sc; 412 int addr; 413 u_int8_t *dest; 414 { 415 int i; 416 u_int32_t byte = 0; 417 418 /* 419 * Enable use of auto EEPROM access so we can avoid 420 * having to use the bitbang method. 421 */ 422 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 423 424 /* Reset the EEPROM, load the clock period. */ 425 CSR_WRITE_4(sc, BGE_EE_ADDR, 426 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 427 DELAY(20); 428 429 /* Issue the read EEPROM command. */ 430 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 431 432 /* Wait for completion */ 433 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 434 DELAY(10); 435 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 436 break; 437 } 438 439 if (i == BGE_TIMEOUT) { 440 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 441 return(0); 442 } 443 444 /* Get result. */ 445 byte = CSR_READ_4(sc, BGE_EE_DATA); 446 447 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 448 449 return(0); 450 } 451 452 /* 453 * Read a sequence of bytes from the EEPROM. 454 */ 455 static int 456 bge_read_eeprom(sc, dest, off, cnt) 457 struct bge_softc *sc; 458 caddr_t dest; 459 int off; 460 int cnt; 461 { 462 int err = 0, i; 463 u_int8_t byte = 0; 464 465 for (i = 0; i < cnt; i++) { 466 err = bge_eeprom_getbyte(sc, off + i, &byte); 467 if (err) 468 break; 469 *(dest + i) = byte; 470 } 471 472 return(err ? 1 : 0); 473 } 474 475 static int 476 bge_miibus_readreg(dev, phy, reg) 477 device_t dev; 478 int phy, reg; 479 { 480 struct bge_softc *sc; 481 struct ifnet *ifp; 482 u_int32_t val; 483 int i; 484 485 sc = device_get_softc(dev); 486 ifp = &sc->arpcom.ac_if; 487 488 if (phy != 1) 489 switch(sc->bge_asicrev) { 490 case BGE_ASICREV_BCM5701_B5: 491 case BGE_ASICREV_BCM5703_A2: 492 return(0); 493 } 494 495 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 496 BGE_MIPHY(phy)|BGE_MIREG(reg)); 497 498 for (i = 0; i < BGE_TIMEOUT; i++) { 499 val = CSR_READ_4(sc, BGE_MI_COMM); 500 if (!(val & BGE_MICOMM_BUSY)) 501 break; 502 } 503 504 if (i == BGE_TIMEOUT) { 505 printf("bge%d: PHY read timed out\n", sc->bge_unit); 506 return(0); 507 } 508 509 val = CSR_READ_4(sc, BGE_MI_COMM); 510 511 if (val & BGE_MICOMM_READFAIL) 512 return(0); 513 514 return(val & 0xFFFF); 515 } 516 517 static int 518 bge_miibus_writereg(dev, phy, reg, val) 519 device_t dev; 520 int phy, reg, val; 521 { 522 struct bge_softc *sc; 523 int i; 524 525 sc = device_get_softc(dev); 526 527 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 528 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 529 530 for (i = 0; i < BGE_TIMEOUT; i++) { 531 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 532 break; 533 } 534 535 if (i == BGE_TIMEOUT) { 536 printf("bge%d: PHY read timed out\n", sc->bge_unit); 537 return(0); 538 } 539 540 return(0); 541 } 542 543 static void 544 bge_miibus_statchg(dev) 545 device_t dev; 546 { 547 struct bge_softc *sc; 548 struct mii_data *mii; 549 550 sc = device_get_softc(dev); 551 mii = device_get_softc(sc->bge_miibus); 552 553 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 554 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 555 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 556 } else { 557 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 558 } 559 560 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 561 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 562 } else { 563 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 564 } 565 566 bge_phy_hack(sc); 567 568 return; 569 } 570 571 /* 572 * Handle events that have triggered interrupts. 573 */ 574 static void 575 bge_handle_events(sc) 576 struct bge_softc *sc; 577 { 578 579 return; 580 } 581 582 /* 583 * Memory management for jumbo frames. 584 */ 585 586 static int 587 bge_alloc_jumbo_mem(sc) 588 struct bge_softc *sc; 589 { 590 caddr_t ptr; 591 register int i; 592 struct bge_jpool_entry *entry; 593 594 /* Grab a big chunk o' storage. */ 595 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 596 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 597 598 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 599 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 600 return(ENOBUFS); 601 } 602 603 SLIST_INIT(&sc->bge_jfree_listhead); 604 SLIST_INIT(&sc->bge_jinuse_listhead); 605 606 /* 607 * Now divide it up into 9K pieces and save the addresses 608 * in an array. 609 */ 610 ptr = sc->bge_cdata.bge_jumbo_buf; 611 for (i = 0; i < BGE_JSLOTS; i++) { 612 sc->bge_cdata.bge_jslots[i] = ptr; 613 ptr += BGE_JLEN; 614 entry = malloc(sizeof(struct bge_jpool_entry), 615 M_DEVBUF, M_NOWAIT); 616 if (entry == NULL) { 617 contigfree(sc->bge_cdata.bge_jumbo_buf, 618 BGE_JMEM, M_DEVBUF); 619 sc->bge_cdata.bge_jumbo_buf = NULL; 620 printf("bge%d: no memory for jumbo " 621 "buffer queue!\n", sc->bge_unit); 622 return(ENOBUFS); 623 } 624 entry->slot = i; 625 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 626 entry, jpool_entries); 627 } 628 629 return(0); 630 } 631 632 static void 633 bge_free_jumbo_mem(sc) 634 struct bge_softc *sc; 635 { 636 int i; 637 struct bge_jpool_entry *entry; 638 639 for (i = 0; i < BGE_JSLOTS; i++) { 640 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 641 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 642 free(entry, M_DEVBUF); 643 } 644 645 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 646 647 return; 648 } 649 650 /* 651 * Allocate a jumbo buffer. 652 */ 653 static void * 654 bge_jalloc(sc) 655 struct bge_softc *sc; 656 { 657 struct bge_jpool_entry *entry; 658 659 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 660 661 if (entry == NULL) { 662 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 663 return(NULL); 664 } 665 666 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 667 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 668 return(sc->bge_cdata.bge_jslots[entry->slot]); 669 } 670 671 /* 672 * Release a jumbo buffer. 673 */ 674 static void 675 bge_jfree(buf, args) 676 void *buf; 677 void *args; 678 { 679 struct bge_jpool_entry *entry; 680 struct bge_softc *sc; 681 int i; 682 683 /* Extract the softc struct pointer. */ 684 sc = (struct bge_softc *)args; 685 686 if (sc == NULL) 687 panic("bge_jfree: can't find softc pointer!"); 688 689 /* calculate the slot this buffer belongs to */ 690 691 i = ((vm_offset_t)buf 692 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 693 694 if ((i < 0) || (i >= BGE_JSLOTS)) 695 panic("bge_jfree: asked to free buffer that we don't manage!"); 696 697 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 698 if (entry == NULL) 699 panic("bge_jfree: buffer not in use!"); 700 entry->slot = i; 701 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 702 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 703 704 return; 705 } 706 707 708 /* 709 * Intialize a standard receive ring descriptor. 710 */ 711 static int 712 bge_newbuf_std(sc, i, m) 713 struct bge_softc *sc; 714 int i; 715 struct mbuf *m; 716 { 717 struct mbuf *m_new = NULL; 718 struct bge_rx_bd *r; 719 720 if (m == NULL) { 721 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 722 if (m_new == NULL) { 723 return(ENOBUFS); 724 } 725 726 MCLGET(m_new, M_DONTWAIT); 727 if (!(m_new->m_flags & M_EXT)) { 728 m_freem(m_new); 729 return(ENOBUFS); 730 } 731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 732 } else { 733 m_new = m; 734 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 735 m_new->m_data = m_new->m_ext.ext_buf; 736 } 737 738 if (!sc->bge_rx_alignment_bug) 739 m_adj(m_new, ETHER_ALIGN); 740 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 741 r = &sc->bge_rdata->bge_rx_std_ring[i]; 742 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 743 r->bge_flags = BGE_RXBDFLAG_END; 744 r->bge_len = m_new->m_len; 745 r->bge_idx = i; 746 747 return(0); 748 } 749 750 /* 751 * Initialize a jumbo receive ring descriptor. This allocates 752 * a jumbo buffer from the pool managed internally by the driver. 753 */ 754 static int 755 bge_newbuf_jumbo(sc, i, m) 756 struct bge_softc *sc; 757 int i; 758 struct mbuf *m; 759 { 760 struct mbuf *m_new = NULL; 761 struct bge_rx_bd *r; 762 763 if (m == NULL) { 764 caddr_t *buf = NULL; 765 766 /* Allocate the mbuf. */ 767 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 return(ENOBUFS); 770 } 771 772 /* Allocate the jumbo buffer */ 773 buf = bge_jalloc(sc); 774 if (buf == NULL) { 775 m_freem(m_new); 776 printf("bge%d: jumbo allocation failed " 777 "-- packet dropped!\n", sc->bge_unit); 778 return(ENOBUFS); 779 } 780 781 /* Attach the buffer to the mbuf. */ 782 m_new->m_data = (void *) buf; 783 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 784 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 785 (struct bge_softc *)sc, 0, EXT_NET_DRV); 786 } else { 787 m_new = m; 788 m_new->m_data = m_new->m_ext.ext_buf; 789 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 790 } 791 792 if (!sc->bge_rx_alignment_bug) 793 m_adj(m_new, ETHER_ALIGN); 794 /* Set up the descriptor. */ 795 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 796 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 797 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 798 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 799 r->bge_len = m_new->m_len; 800 r->bge_idx = i; 801 802 return(0); 803 } 804 805 /* 806 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 807 * that's 1MB or memory, which is a lot. For now, we fill only the first 808 * 256 ring entries and hope that our CPU is fast enough to keep up with 809 * the NIC. 810 */ 811 static int 812 bge_init_rx_ring_std(sc) 813 struct bge_softc *sc; 814 { 815 int i; 816 817 for (i = 0; i < BGE_SSLOTS; i++) { 818 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 819 return(ENOBUFS); 820 }; 821 822 sc->bge_std = i - 1; 823 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 824 825 return(0); 826 } 827 828 static void 829 bge_free_rx_ring_std(sc) 830 struct bge_softc *sc; 831 { 832 int i; 833 834 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 835 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 836 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 837 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 838 } 839 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 840 sizeof(struct bge_rx_bd)); 841 } 842 843 return; 844 } 845 846 static int 847 bge_init_rx_ring_jumbo(sc) 848 struct bge_softc *sc; 849 { 850 int i; 851 struct bge_rcb *rcb; 852 struct bge_rcb_opaque *rcbo; 853 854 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 855 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 856 return(ENOBUFS); 857 }; 858 859 sc->bge_jumbo = i - 1; 860 861 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 862 rcbo = (struct bge_rcb_opaque *)rcb; 863 rcb->bge_flags = 0; 864 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 865 866 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 867 868 return(0); 869 } 870 871 static void 872 bge_free_rx_ring_jumbo(sc) 873 struct bge_softc *sc; 874 { 875 int i; 876 877 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 878 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 879 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 880 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 881 } 882 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 883 sizeof(struct bge_rx_bd)); 884 } 885 886 return; 887 } 888 889 static void 890 bge_free_tx_ring(sc) 891 struct bge_softc *sc; 892 { 893 int i; 894 895 if (sc->bge_rdata->bge_tx_ring == NULL) 896 return; 897 898 for (i = 0; i < BGE_TX_RING_CNT; i++) { 899 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 900 m_freem(sc->bge_cdata.bge_tx_chain[i]); 901 sc->bge_cdata.bge_tx_chain[i] = NULL; 902 } 903 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 904 sizeof(struct bge_tx_bd)); 905 } 906 907 return; 908 } 909 910 static int 911 bge_init_tx_ring(sc) 912 struct bge_softc *sc; 913 { 914 sc->bge_txcnt = 0; 915 sc->bge_tx_saved_considx = 0; 916 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 917 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 918 919 return(0); 920 } 921 922 #define BGE_POLY 0xEDB88320 923 924 static u_int32_t 925 bge_crc(addr) 926 caddr_t addr; 927 { 928 u_int32_t idx, bit, data, crc; 929 930 /* Compute CRC for the address value. */ 931 crc = 0xFFFFFFFF; /* initial value */ 932 933 for (idx = 0; idx < 6; idx++) { 934 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 935 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 936 } 937 938 return(crc & 0x7F); 939 } 940 941 static void 942 bge_setmulti(sc) 943 struct bge_softc *sc; 944 { 945 struct ifnet *ifp; 946 struct ifmultiaddr *ifma; 947 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 948 int h, i; 949 950 ifp = &sc->arpcom.ac_if; 951 952 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 953 for (i = 0; i < 4; i++) 954 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 955 return; 956 } 957 958 /* First, zot all the existing filters. */ 959 for (i = 0; i < 4; i++) 960 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 961 962 /* Now program new ones. */ 963 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 964 if (ifma->ifma_addr->sa_family != AF_LINK) 965 continue; 966 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 967 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 968 } 969 970 for (i = 0; i < 4; i++) 971 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 972 973 return; 974 } 975 976 /* 977 * Do endian, PCI and DMA initialization. Also check the on-board ROM 978 * self-test results. 979 */ 980 static int 981 bge_chipinit(sc) 982 struct bge_softc *sc; 983 { 984 int i; 985 986 /* Set endianness before we access any non-PCI registers. */ 987 #if BYTE_ORDER == BIG_ENDIAN 988 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 989 BGE_BIGENDIAN_INIT, 4); 990 #else 991 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 992 BGE_LITTLEENDIAN_INIT, 4); 993 #endif 994 995 /* 996 * Check the 'ROM failed' bit on the RX CPU to see if 997 * self-tests passed. 998 */ 999 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1000 printf("bge%d: RX CPU self-diagnostics failed!\n", 1001 sc->bge_unit); 1002 return(ENODEV); 1003 } 1004 1005 /* Clear the MAC control register */ 1006 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1007 1008 /* 1009 * Clear the MAC statistics block in the NIC's 1010 * internal memory. 1011 */ 1012 for (i = BGE_STATS_BLOCK; 1013 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1014 BGE_MEMWIN_WRITE(sc, i, 0); 1015 1016 for (i = BGE_STATUS_BLOCK; 1017 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1018 BGE_MEMWIN_WRITE(sc, i, 0); 1019 1020 /* Set up the PCI DMA control register. */ 1021 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1022 BGE_PCISTATE_PCI_BUSMODE) { 1023 /* Conventional PCI bus */ 1024 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1025 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4); 1026 } else { 1027 /* PCI-X bus */ 1028 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1029 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4); 1030 } 1031 1032 /* 1033 * Set up general mode register. 1034 */ 1035 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1036 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1037 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1038 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1039 BGE_MODECTL_RX_NO_PHDR_CSUM); 1040 1041 /* 1042 * Disable memory write invalidate. Apparently it is not supported 1043 * properly by these devices. 1044 */ 1045 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1046 1047 #ifdef __brokenalpha__ 1048 /* 1049 * Must insure that we do not cross an 8K (bytes) boundary 1050 * for DMA reads. Our highest limit is 1K bytes. This is a 1051 * restriction on some ALPHA platforms with early revision 1052 * 21174 PCI chipsets, such as the AlphaPC 164lx 1053 */ 1054 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1055 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1056 #endif 1057 1058 /* Set the timer prescaler (always 66Mhz) */ 1059 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1060 1061 return(0); 1062 } 1063 1064 static int 1065 bge_blockinit(sc) 1066 struct bge_softc *sc; 1067 { 1068 struct bge_rcb *rcb; 1069 struct bge_rcb_opaque *rcbo; 1070 int i; 1071 1072 /* 1073 * Initialize the memory window pointer register so that 1074 * we can access the first 32K of internal NIC RAM. This will 1075 * allow us to set up the TX send ring RCBs and the RX return 1076 * ring RCBs, plus other things which live in NIC memory. 1077 */ 1078 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1079 1080 /* Configure mbuf memory pool */ 1081 if (sc->bge_extram) { 1082 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1083 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1084 } else { 1085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1086 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1087 } 1088 1089 /* Configure DMA resource pool */ 1090 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1091 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1092 1093 /* Configure mbuf pool watermarks */ 1094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1095 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1096 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1097 1098 /* Configure DMA resource watermarks */ 1099 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1100 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1101 1102 /* Enable buffer manager */ 1103 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1104 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1105 1106 /* Poll for buffer manager start indication */ 1107 for (i = 0; i < BGE_TIMEOUT; i++) { 1108 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1109 break; 1110 DELAY(10); 1111 } 1112 1113 if (i == BGE_TIMEOUT) { 1114 printf("bge%d: buffer manager failed to start\n", 1115 sc->bge_unit); 1116 return(ENXIO); 1117 } 1118 1119 /* Enable flow-through queues */ 1120 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1121 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1122 1123 /* Wait until queue initialization is complete */ 1124 for (i = 0; i < BGE_TIMEOUT; i++) { 1125 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1126 break; 1127 DELAY(10); 1128 } 1129 1130 if (i == BGE_TIMEOUT) { 1131 printf("bge%d: flow-through queue init failed\n", 1132 sc->bge_unit); 1133 return(ENXIO); 1134 } 1135 1136 /* Initialize the standard RX ring control block */ 1137 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1138 BGE_HOSTADDR(rcb->bge_hostaddr) = 1139 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1140 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1141 if (sc->bge_extram) 1142 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1143 else 1144 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1145 rcb->bge_flags = 0; 1146 rcbo = (struct bge_rcb_opaque *)rcb; 1147 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1148 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1149 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1150 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1151 1152 /* 1153 * Initialize the jumbo RX ring control block 1154 * We set the 'ring disabled' bit in the flags 1155 * field until we're actually ready to start 1156 * using this ring (i.e. once we set the MTU 1157 * high enough to require it). 1158 */ 1159 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1160 BGE_HOSTADDR(rcb->bge_hostaddr) = 1161 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1162 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1163 if (sc->bge_extram) 1164 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1165 else 1166 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1167 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1168 1169 rcbo = (struct bge_rcb_opaque *)rcb; 1170 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1171 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1172 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1173 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1174 1175 /* Set up dummy disabled mini ring RCB */ 1176 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1177 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1178 rcbo = (struct bge_rcb_opaque *)rcb; 1179 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1180 1181 /* 1182 * Set the BD ring replentish thresholds. The recommended 1183 * values are 1/8th the number of descriptors allocated to 1184 * each ring. 1185 */ 1186 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1187 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1188 1189 /* 1190 * Disable all unused send rings by setting the 'ring disabled' 1191 * bit in the flags field of all the TX send ring control blocks. 1192 * These are located in NIC memory. 1193 */ 1194 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1195 BGE_SEND_RING_RCB); 1196 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1197 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1198 rcb->bge_max_len = 0; 1199 rcb->bge_nicaddr = 0; 1200 rcb++; 1201 } 1202 1203 /* Configure TX RCB 0 (we use only the first ring) */ 1204 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1205 BGE_SEND_RING_RCB); 1206 rcb->bge_hostaddr.bge_addr_hi = 0; 1207 BGE_HOSTADDR(rcb->bge_hostaddr) = 1208 vtophys(&sc->bge_rdata->bge_tx_ring); 1209 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1210 rcb->bge_max_len = BGE_TX_RING_CNT; 1211 rcb->bge_flags = 0; 1212 1213 /* Disable all unused RX return rings */ 1214 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1215 BGE_RX_RETURN_RING_RCB); 1216 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1217 rcb->bge_hostaddr.bge_addr_hi = 0; 1218 rcb->bge_hostaddr.bge_addr_lo = 0; 1219 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1220 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1221 rcb->bge_nicaddr = 0; 1222 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1223 (i * (sizeof(u_int64_t))), 0); 1224 rcb++; 1225 } 1226 1227 /* Initialize RX ring indexes */ 1228 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1229 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1230 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1231 1232 /* 1233 * Set up RX return ring 0 1234 * Note that the NIC address for RX return rings is 0x00000000. 1235 * The return rings live entirely within the host, so the 1236 * nicaddr field in the RCB isn't used. 1237 */ 1238 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1239 BGE_RX_RETURN_RING_RCB); 1240 rcb->bge_hostaddr.bge_addr_hi = 0; 1241 BGE_HOSTADDR(rcb->bge_hostaddr) = 1242 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1243 rcb->bge_nicaddr = 0x00000000; 1244 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1245 rcb->bge_flags = 0; 1246 1247 /* Set random backoff seed for TX */ 1248 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1249 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1250 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1251 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1252 BGE_TX_BACKOFF_SEED_MASK); 1253 1254 /* Set inter-packet gap */ 1255 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1256 1257 /* 1258 * Specify which ring to use for packets that don't match 1259 * any RX rules. 1260 */ 1261 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1262 1263 /* 1264 * Configure number of RX lists. One interrupt distribution 1265 * list, sixteen active lists, one bad frames class. 1266 */ 1267 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1268 1269 /* Inialize RX list placement stats mask. */ 1270 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1271 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1272 1273 /* Disable host coalescing until we get it set up */ 1274 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1275 1276 /* Poll to make sure it's shut down. */ 1277 for (i = 0; i < BGE_TIMEOUT; i++) { 1278 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1279 break; 1280 DELAY(10); 1281 } 1282 1283 if (i == BGE_TIMEOUT) { 1284 printf("bge%d: host coalescing engine failed to idle\n", 1285 sc->bge_unit); 1286 return(ENXIO); 1287 } 1288 1289 /* Set up host coalescing defaults */ 1290 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1291 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1292 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1293 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1294 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1295 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1296 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1297 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1298 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1299 1300 /* Set up address of statistics block */ 1301 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1302 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1303 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1304 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1305 1306 /* Set up address of status block */ 1307 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1308 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1309 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1310 vtophys(&sc->bge_rdata->bge_status_block)); 1311 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1312 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1313 1314 /* Turn on host coalescing state machine */ 1315 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1316 1317 /* Turn on RX BD completion state machine and enable attentions */ 1318 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1319 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1320 1321 /* Turn on RX list placement state machine */ 1322 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1323 1324 /* Turn on RX list selector state machine. */ 1325 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1326 1327 /* Turn on DMA, clear stats */ 1328 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1329 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1330 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1331 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1332 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1333 1334 /* Set misc. local control, enable interrupts on attentions */ 1335 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1336 1337 #ifdef notdef 1338 /* Assert GPIO pins for PHY reset */ 1339 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1340 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1341 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1342 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1343 #endif 1344 1345 /* Turn on DMA completion state machine */ 1346 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1347 1348 /* Turn on write DMA state machine */ 1349 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1350 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1351 1352 /* Turn on read DMA state machine */ 1353 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1354 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1355 1356 /* Turn on RX data completion state machine */ 1357 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1358 1359 /* Turn on RX BD initiator state machine */ 1360 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1361 1362 /* Turn on RX data and RX BD initiator state machine */ 1363 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1364 1365 /* Turn on Mbuf cluster free state machine */ 1366 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1367 1368 /* Turn on send BD completion state machine */ 1369 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1370 1371 /* Turn on send data completion state machine */ 1372 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1373 1374 /* Turn on send data initiator state machine */ 1375 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1376 1377 /* Turn on send BD initiator state machine */ 1378 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1379 1380 /* Turn on send BD selector state machine */ 1381 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1382 1383 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1384 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1385 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1386 1387 /* init LED register */ 1388 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1389 1390 /* ack/clear link change events */ 1391 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1392 BGE_MACSTAT_CFG_CHANGED); 1393 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1394 1395 /* Enable PHY auto polling (for MII/GMII only) */ 1396 if (sc->bge_tbi) { 1397 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1398 } else { 1399 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1400 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1401 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1402 BGE_EVTENB_MI_INTERRUPT); 1403 } 1404 1405 /* Enable link state change attentions. */ 1406 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1407 1408 return(0); 1409 } 1410 1411 /* 1412 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1413 * against our list and return its name if we find a match. Note 1414 * that since the Broadcom controller contains VPD support, we 1415 * can get the device name string from the controller itself instead 1416 * of the compiled-in string. This is a little slow, but it guarantees 1417 * we'll always announce the right product name. 1418 */ 1419 static int 1420 bge_probe(dev) 1421 device_t dev; 1422 { 1423 struct bge_type *t; 1424 struct bge_softc *sc; 1425 1426 t = bge_devs; 1427 1428 sc = device_get_softc(dev); 1429 bzero(sc, sizeof(struct bge_softc)); 1430 sc->bge_unit = device_get_unit(dev); 1431 sc->bge_dev = dev; 1432 1433 while(t->bge_name != NULL) { 1434 if ((pci_get_vendor(dev) == t->bge_vid) && 1435 (pci_get_device(dev) == t->bge_did)) { 1436 #ifdef notdef 1437 bge_vpd_read(sc); 1438 device_set_desc(dev, sc->bge_vpd_prodname); 1439 #endif 1440 device_set_desc(dev, t->bge_name); 1441 return(0); 1442 } 1443 t++; 1444 } 1445 1446 return(ENXIO); 1447 } 1448 1449 static int 1450 bge_attach(dev) 1451 device_t dev; 1452 { 1453 int s; 1454 u_int32_t command; 1455 struct ifnet *ifp; 1456 struct bge_softc *sc; 1457 u_int32_t hwcfg = 0; 1458 u_int32_t mac_addr = 0; 1459 int unit, error = 0, rid; 1460 1461 s = splimp(); 1462 1463 sc = device_get_softc(dev); 1464 unit = device_get_unit(dev); 1465 sc->bge_dev = dev; 1466 sc->bge_unit = unit; 1467 1468 /* 1469 * Map control/status registers. 1470 */ 1471 pci_enable_busmaster(dev); 1472 pci_enable_io(dev, SYS_RES_MEMORY); 1473 command = pci_read_config(dev, PCIR_COMMAND, 4); 1474 1475 if (!(command & PCIM_CMD_MEMEN)) { 1476 printf("bge%d: failed to enable memory mapping!\n", unit); 1477 error = ENXIO; 1478 goto fail; 1479 } 1480 1481 rid = BGE_PCI_BAR0; 1482 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1483 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1484 1485 if (sc->bge_res == NULL) { 1486 printf ("bge%d: couldn't map memory\n", unit); 1487 error = ENXIO; 1488 goto fail; 1489 } 1490 1491 sc->bge_btag = rman_get_bustag(sc->bge_res); 1492 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1493 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1494 1495 /* Allocate interrupt */ 1496 rid = 0; 1497 1498 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1499 RF_SHAREABLE | RF_ACTIVE); 1500 1501 if (sc->bge_irq == NULL) { 1502 printf("bge%d: couldn't map interrupt\n", unit); 1503 error = ENXIO; 1504 goto fail; 1505 } 1506 1507 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1508 bge_intr, sc, &sc->bge_intrhand); 1509 1510 if (error) { 1511 bge_release_resources(sc); 1512 printf("bge%d: couldn't set up irq\n", unit); 1513 goto fail; 1514 } 1515 1516 sc->bge_unit = unit; 1517 1518 /* Try to reset the chip. */ 1519 bge_reset(sc); 1520 1521 if (bge_chipinit(sc)) { 1522 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1523 bge_release_resources(sc); 1524 error = ENXIO; 1525 goto fail; 1526 } 1527 1528 /* 1529 * Get station address from the EEPROM. 1530 */ 1531 mac_addr = bge_readmem_ind(sc, 0x0c14); 1532 if ((mac_addr >> 16) == 0x484b) { 1533 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1534 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1535 mac_addr = bge_readmem_ind(sc, 0x0c18); 1536 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1537 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1538 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1539 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1540 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1541 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1542 printf("bge%d: failed to read station address\n", unit); 1543 bge_release_resources(sc); 1544 error = ENXIO; 1545 goto fail; 1546 } 1547 1548 /* 1549 * A Broadcom chip was detected. Inform the world. 1550 */ 1551 printf("bge%d: Ethernet address: %6D\n", unit, 1552 sc->arpcom.ac_enaddr, ":"); 1553 1554 /* Allocate the general information block and ring buffers. */ 1555 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1556 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1557 1558 if (sc->bge_rdata == NULL) { 1559 bge_release_resources(sc); 1560 error = ENXIO; 1561 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1562 goto fail; 1563 } 1564 1565 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1566 1567 /* Try to allocate memory for jumbo buffers. */ 1568 if (bge_alloc_jumbo_mem(sc)) { 1569 printf("bge%d: jumbo buffer allocation " 1570 "failed\n", sc->bge_unit); 1571 bge_release_resources(sc); 1572 error = ENXIO; 1573 goto fail; 1574 } 1575 1576 /* Set default tuneable values. */ 1577 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1578 sc->bge_rx_coal_ticks = 150; 1579 sc->bge_tx_coal_ticks = 150; 1580 sc->bge_rx_max_coal_bds = 64; 1581 sc->bge_tx_max_coal_bds = 128; 1582 1583 /* Set up ifnet structure */ 1584 ifp = &sc->arpcom.ac_if; 1585 ifp->if_softc = sc; 1586 ifp->if_unit = sc->bge_unit; 1587 ifp->if_name = "bge"; 1588 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1589 ifp->if_ioctl = bge_ioctl; 1590 ifp->if_output = ether_output; 1591 ifp->if_start = bge_start; 1592 ifp->if_watchdog = bge_watchdog; 1593 ifp->if_init = bge_init; 1594 ifp->if_mtu = ETHERMTU; 1595 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1596 ifp->if_hwassist = BGE_CSUM_FEATURES; 1597 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1598 ifp->if_capenable = ifp->if_capabilities; 1599 1600 /* Save ASIC rev. */ 1601 1602 sc->bge_asicrev = 1603 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1604 BGE_PCIMISCCTL_ASICREV; 1605 1606 /* Pretend all 5700s are the same */ 1607 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1608 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1609 1610 /* 1611 * Figure out what sort of media we have by checking the 1612 * hardware config word in the EEPROM. Note: on some BCM5700 1613 * cards, this value appears to be unset. If that's the 1614 * case, we have to rely on identifying the NIC by its PCI 1615 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1616 */ 1617 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1618 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1619 if ((ntohl(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1620 sc->bge_tbi = 1; 1621 1622 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1623 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1624 sc->bge_tbi = 1; 1625 1626 if (sc->bge_tbi) { 1627 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1628 bge_ifmedia_upd, bge_ifmedia_sts); 1629 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1630 ifmedia_add(&sc->bge_ifmedia, 1631 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1632 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1633 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1634 } else { 1635 /* 1636 * Do transceiver setup. 1637 */ 1638 if (mii_phy_probe(dev, &sc->bge_miibus, 1639 bge_ifmedia_upd, bge_ifmedia_sts)) { 1640 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1641 bge_release_resources(sc); 1642 bge_free_jumbo_mem(sc); 1643 error = ENXIO; 1644 goto fail; 1645 } 1646 } 1647 1648 /* 1649 * When using the BCM5701 in PCI-X mode, data corruption has 1650 * been observed in the first few bytes of some received packets. 1651 * Aligning the packet buffer in memory eliminates the corruption. 1652 * Unfortunately, this misaligns the packet payloads. On platforms 1653 * which do not support unaligned accesses, we will realign the 1654 * payloads by copying the received packets. 1655 */ 1656 switch (sc->bge_asicrev) { 1657 case BGE_ASICREV_BCM5701_A0: 1658 case BGE_ASICREV_BCM5701_B0: 1659 case BGE_ASICREV_BCM5701_B2: 1660 case BGE_ASICREV_BCM5701_B5: 1661 /* If in PCI-X mode, work around the alignment bug. */ 1662 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1663 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1664 BGE_PCISTATE_PCI_BUSSPEED) 1665 sc->bge_rx_alignment_bug = 1; 1666 break; 1667 } 1668 1669 /* 1670 * Call MI attach routine. 1671 */ 1672 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1673 callout_handle_init(&sc->bge_stat_ch); 1674 1675 fail: 1676 splx(s); 1677 1678 return(error); 1679 } 1680 1681 static int 1682 bge_detach(dev) 1683 device_t dev; 1684 { 1685 struct bge_softc *sc; 1686 struct ifnet *ifp; 1687 int s; 1688 1689 s = splimp(); 1690 1691 sc = device_get_softc(dev); 1692 ifp = &sc->arpcom.ac_if; 1693 1694 ether_ifdetach(ifp); 1695 bge_stop(sc); 1696 bge_reset(sc); 1697 1698 if (sc->bge_tbi) { 1699 ifmedia_removeall(&sc->bge_ifmedia); 1700 } else { 1701 bus_generic_detach(dev); 1702 device_delete_child(dev, sc->bge_miibus); 1703 } 1704 1705 bge_release_resources(sc); 1706 bge_free_jumbo_mem(sc); 1707 1708 splx(s); 1709 1710 return(0); 1711 } 1712 1713 static void 1714 bge_release_resources(sc) 1715 struct bge_softc *sc; 1716 { 1717 device_t dev; 1718 1719 dev = sc->bge_dev; 1720 1721 if (sc->bge_vpd_prodname != NULL) 1722 free(sc->bge_vpd_prodname, M_DEVBUF); 1723 1724 if (sc->bge_vpd_readonly != NULL) 1725 free(sc->bge_vpd_readonly, M_DEVBUF); 1726 1727 if (sc->bge_intrhand != NULL) 1728 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1729 1730 if (sc->bge_irq != NULL) 1731 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1732 1733 if (sc->bge_res != NULL) 1734 bus_release_resource(dev, SYS_RES_MEMORY, 1735 BGE_PCI_BAR0, sc->bge_res); 1736 1737 if (sc->bge_rdata != NULL) 1738 contigfree(sc->bge_rdata, 1739 sizeof(struct bge_ring_data), M_DEVBUF); 1740 1741 return; 1742 } 1743 1744 static void 1745 bge_reset(sc) 1746 struct bge_softc *sc; 1747 { 1748 device_t dev; 1749 u_int32_t cachesize, command, pcistate; 1750 int i, val = 0; 1751 1752 dev = sc->bge_dev; 1753 1754 /* Save some important PCI state. */ 1755 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1756 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1757 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1758 1759 pci_write_config(dev, BGE_PCI_MISC_CTL, 1760 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1761 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1762 1763 /* Issue global reset */ 1764 bge_writereg_ind(sc, BGE_MISC_CFG, 1765 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1766 1767 DELAY(1000); 1768 1769 /* Reset some of the PCI state that got zapped by reset */ 1770 pci_write_config(dev, BGE_PCI_MISC_CTL, 1771 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1772 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1773 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1774 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1775 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1776 1777 /* 1778 * Prevent PXE restart: write a magic number to the 1779 * general communications memory at 0xB50. 1780 */ 1781 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1782 /* 1783 * Poll the value location we just wrote until 1784 * we see the 1's complement of the magic number. 1785 * This indicates that the firmware initialization 1786 * is complete. 1787 */ 1788 for (i = 0; i < BGE_TIMEOUT; i++) { 1789 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1790 if (val == ~BGE_MAGIC_NUMBER) 1791 break; 1792 DELAY(10); 1793 } 1794 1795 if (i == BGE_TIMEOUT) { 1796 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1797 return; 1798 } 1799 1800 /* 1801 * XXX Wait for the value of the PCISTATE register to 1802 * return to its original pre-reset state. This is a 1803 * fairly good indicator of reset completion. If we don't 1804 * wait for the reset to fully complete, trying to read 1805 * from the device's non-PCI registers may yield garbage 1806 * results. 1807 */ 1808 for (i = 0; i < BGE_TIMEOUT; i++) { 1809 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1810 break; 1811 DELAY(10); 1812 } 1813 1814 /* Enable memory arbiter. */ 1815 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1816 1817 /* Fix up byte swapping */ 1818 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1819 BGE_MODECTL_BYTESWAP_DATA); 1820 1821 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1822 1823 DELAY(10000); 1824 1825 return; 1826 } 1827 1828 /* 1829 * Frame reception handling. This is called if there's a frame 1830 * on the receive return list. 1831 * 1832 * Note: we have to be able to handle two possibilities here: 1833 * 1) the frame is from the jumbo recieve ring 1834 * 2) the frame is from the standard receive ring 1835 */ 1836 1837 static void 1838 bge_rxeof(sc) 1839 struct bge_softc *sc; 1840 { 1841 struct ifnet *ifp; 1842 int stdcnt = 0, jumbocnt = 0; 1843 1844 ifp = &sc->arpcom.ac_if; 1845 1846 while(sc->bge_rx_saved_considx != 1847 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1848 struct bge_rx_bd *cur_rx; 1849 u_int32_t rxidx; 1850 struct ether_header *eh; 1851 struct mbuf *m = NULL; 1852 u_int16_t vlan_tag = 0; 1853 int have_tag = 0; 1854 1855 cur_rx = 1856 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1857 1858 rxidx = cur_rx->bge_idx; 1859 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1860 1861 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1862 have_tag = 1; 1863 vlan_tag = cur_rx->bge_vlan_tag; 1864 } 1865 1866 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1867 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1868 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1869 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1870 jumbocnt++; 1871 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1872 ifp->if_ierrors++; 1873 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1874 continue; 1875 } 1876 if (bge_newbuf_jumbo(sc, 1877 sc->bge_jumbo, NULL) == ENOBUFS) { 1878 ifp->if_ierrors++; 1879 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1880 continue; 1881 } 1882 } else { 1883 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1884 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1885 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1886 stdcnt++; 1887 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1888 ifp->if_ierrors++; 1889 bge_newbuf_std(sc, sc->bge_std, m); 1890 continue; 1891 } 1892 if (bge_newbuf_std(sc, sc->bge_std, 1893 NULL) == ENOBUFS) { 1894 ifp->if_ierrors++; 1895 bge_newbuf_std(sc, sc->bge_std, m); 1896 continue; 1897 } 1898 } 1899 1900 ifp->if_ipackets++; 1901 #ifndef __i386__ 1902 /* 1903 * The i386 allows unaligned accesses, but for other 1904 * platforms we must make sure the payload is aligned. 1905 */ 1906 if (sc->bge_rx_alignment_bug) { 1907 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1908 cur_rx->bge_len); 1909 m->m_data += ETHER_ALIGN; 1910 } 1911 #endif 1912 eh = mtod(m, struct ether_header *); 1913 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1914 m->m_pkthdr.rcvif = ifp; 1915 1916 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1917 if (ifp->if_hwassist) { 1918 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1919 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1920 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1921 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1922 m->m_pkthdr.csum_data = 1923 cur_rx->bge_tcp_udp_csum; 1924 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1925 } 1926 } 1927 #endif 1928 1929 /* 1930 * If we received a packet with a vlan tag, 1931 * attach that information to the packet. 1932 */ 1933 if (have_tag) 1934 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1935 1936 (*ifp->if_input)(ifp, m); 1937 } 1938 1939 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1940 if (stdcnt) 1941 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1942 if (jumbocnt) 1943 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1944 1945 return; 1946 } 1947 1948 static void 1949 bge_txeof(sc) 1950 struct bge_softc *sc; 1951 { 1952 struct bge_tx_bd *cur_tx = NULL; 1953 struct ifnet *ifp; 1954 1955 ifp = &sc->arpcom.ac_if; 1956 1957 /* 1958 * Go through our tx ring and free mbufs for those 1959 * frames that have been sent. 1960 */ 1961 while (sc->bge_tx_saved_considx != 1962 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1963 u_int32_t idx = 0; 1964 1965 idx = sc->bge_tx_saved_considx; 1966 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1967 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1968 ifp->if_opackets++; 1969 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1970 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1971 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1972 } 1973 sc->bge_txcnt--; 1974 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1975 ifp->if_timer = 0; 1976 } 1977 1978 if (cur_tx != NULL) 1979 ifp->if_flags &= ~IFF_OACTIVE; 1980 1981 return; 1982 } 1983 1984 static void 1985 bge_intr(xsc) 1986 void *xsc; 1987 { 1988 struct bge_softc *sc; 1989 struct ifnet *ifp; 1990 1991 sc = xsc; 1992 ifp = &sc->arpcom.ac_if; 1993 1994 #ifdef notdef 1995 /* Avoid this for now -- checking this register is expensive. */ 1996 /* Make sure this is really our interrupt. */ 1997 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1998 return; 1999 #endif 2000 /* Ack interrupt and stop others from occuring. */ 2001 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2002 2003 /* 2004 * Process link state changes. 2005 * Grrr. The link status word in the status block does 2006 * not work correctly on the BCM5700 rev AX and BX chips, 2007 * according to all avaibable information. Hence, we have 2008 * to enable MII interrupts in order to properly obtain 2009 * async link changes. Unfortunately, this also means that 2010 * we have to read the MAC status register to detect link 2011 * changes, thereby adding an additional register access to 2012 * the interrupt handler. 2013 */ 2014 2015 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2016 u_int32_t status; 2017 2018 status = CSR_READ_4(sc, BGE_MAC_STS); 2019 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2020 sc->bge_link = 0; 2021 untimeout(bge_tick, sc, sc->bge_stat_ch); 2022 bge_tick(sc); 2023 /* Clear the interrupt */ 2024 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2025 BGE_EVTENB_MI_INTERRUPT); 2026 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2027 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2028 BRGPHY_INTRS); 2029 } 2030 } else { 2031 if (sc->bge_rdata->bge_status_block.bge_status & 2032 BGE_STATFLAG_LINKSTATE_CHANGED) { 2033 sc->bge_link = 0; 2034 untimeout(bge_tick, sc, sc->bge_stat_ch); 2035 bge_tick(sc); 2036 /* Clear the interrupt */ 2037 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2038 BGE_MACSTAT_CFG_CHANGED); 2039 } 2040 } 2041 2042 if (ifp->if_flags & IFF_RUNNING) { 2043 /* Check RX return ring producer/consumer */ 2044 bge_rxeof(sc); 2045 2046 /* Check TX ring producer/consumer */ 2047 bge_txeof(sc); 2048 } 2049 2050 bge_handle_events(sc); 2051 2052 /* Re-enable interrupts. */ 2053 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2054 2055 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2056 bge_start(ifp); 2057 2058 return; 2059 } 2060 2061 static void 2062 bge_tick(xsc) 2063 void *xsc; 2064 { 2065 struct bge_softc *sc; 2066 struct mii_data *mii = NULL; 2067 struct ifmedia *ifm = NULL; 2068 struct ifnet *ifp; 2069 int s; 2070 2071 sc = xsc; 2072 ifp = &sc->arpcom.ac_if; 2073 2074 s = splimp(); 2075 2076 bge_stats_update(sc); 2077 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2078 if (sc->bge_link) { 2079 splx(s); 2080 return; 2081 } 2082 2083 if (sc->bge_tbi) { 2084 ifm = &sc->bge_ifmedia; 2085 if (CSR_READ_4(sc, BGE_MAC_STS) & 2086 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2087 sc->bge_link++; 2088 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2089 printf("bge%d: gigabit link up\n", sc->bge_unit); 2090 if (ifp->if_snd.ifq_head != NULL) 2091 bge_start(ifp); 2092 } 2093 splx(s); 2094 return; 2095 } 2096 2097 mii = device_get_softc(sc->bge_miibus); 2098 mii_tick(mii); 2099 2100 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2101 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2102 sc->bge_link++; 2103 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2104 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2105 printf("bge%d: gigabit link up\n", 2106 sc->bge_unit); 2107 if (ifp->if_snd.ifq_head != NULL) 2108 bge_start(ifp); 2109 } 2110 2111 splx(s); 2112 2113 return; 2114 } 2115 2116 static void 2117 bge_stats_update(sc) 2118 struct bge_softc *sc; 2119 { 2120 struct ifnet *ifp; 2121 struct bge_stats *stats; 2122 2123 ifp = &sc->arpcom.ac_if; 2124 2125 stats = (struct bge_stats *)(sc->bge_vhandle + 2126 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2127 2128 ifp->if_collisions += 2129 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2130 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2131 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2132 stats->dot3StatsLateCollisions.bge_addr_lo) - 2133 ifp->if_collisions; 2134 2135 #ifdef notdef 2136 ifp->if_collisions += 2137 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2138 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2139 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2140 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2141 ifp->if_collisions; 2142 #endif 2143 2144 return; 2145 } 2146 2147 /* 2148 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2149 * pointers to descriptors. 2150 */ 2151 static int 2152 bge_encap(sc, m_head, txidx) 2153 struct bge_softc *sc; 2154 struct mbuf *m_head; 2155 u_int32_t *txidx; 2156 { 2157 struct bge_tx_bd *f = NULL; 2158 struct mbuf *m; 2159 u_int32_t frag, cur, cnt = 0; 2160 u_int16_t csum_flags = 0; 2161 struct m_tag *mtag; 2162 2163 m = m_head; 2164 cur = frag = *txidx; 2165 2166 if (m_head->m_pkthdr.csum_flags) { 2167 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2168 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2169 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2170 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2171 if (m_head->m_flags & M_LASTFRAG) 2172 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2173 else if (m_head->m_flags & M_FRAG) 2174 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2175 } 2176 2177 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2178 2179 /* 2180 * Start packing the mbufs in this chain into 2181 * the fragment pointers. Stop when we run out 2182 * of fragments or hit the end of the mbuf chain. 2183 */ 2184 for (m = m_head; m != NULL; m = m->m_next) { 2185 if (m->m_len != 0) { 2186 f = &sc->bge_rdata->bge_tx_ring[frag]; 2187 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2188 break; 2189 BGE_HOSTADDR(f->bge_addr) = 2190 vtophys(mtod(m, vm_offset_t)); 2191 f->bge_len = m->m_len; 2192 f->bge_flags = csum_flags; 2193 if (mtag != NULL) { 2194 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2195 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2196 } else { 2197 f->bge_vlan_tag = 0; 2198 } 2199 /* 2200 * Sanity check: avoid coming within 16 descriptors 2201 * of the end of the ring. 2202 */ 2203 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2204 return(ENOBUFS); 2205 cur = frag; 2206 BGE_INC(frag, BGE_TX_RING_CNT); 2207 cnt++; 2208 } 2209 } 2210 2211 if (m != NULL) 2212 return(ENOBUFS); 2213 2214 if (frag == sc->bge_tx_saved_considx) 2215 return(ENOBUFS); 2216 2217 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2218 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2219 sc->bge_txcnt += cnt; 2220 2221 *txidx = frag; 2222 2223 return(0); 2224 } 2225 2226 /* 2227 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2228 * to the mbuf data regions directly in the transmit descriptors. 2229 */ 2230 static void 2231 bge_start(ifp) 2232 struct ifnet *ifp; 2233 { 2234 struct bge_softc *sc; 2235 struct mbuf *m_head = NULL; 2236 u_int32_t prodidx = 0; 2237 2238 sc = ifp->if_softc; 2239 2240 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2241 return; 2242 2243 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2244 2245 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2246 IF_DEQUEUE(&ifp->if_snd, m_head); 2247 if (m_head == NULL) 2248 break; 2249 2250 /* 2251 * XXX 2252 * safety overkill. If this is a fragmented packet chain 2253 * with delayed TCP/UDP checksums, then only encapsulate 2254 * it if we have enough descriptors to handle the entire 2255 * chain at once. 2256 * (paranoia -- may not actually be needed) 2257 */ 2258 if (m_head->m_flags & M_FIRSTFRAG && 2259 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2260 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2261 m_head->m_pkthdr.csum_data + 16) { 2262 IF_PREPEND(&ifp->if_snd, m_head); 2263 ifp->if_flags |= IFF_OACTIVE; 2264 break; 2265 } 2266 } 2267 2268 /* 2269 * Pack the data into the transmit ring. If we 2270 * don't have room, set the OACTIVE flag and wait 2271 * for the NIC to drain the ring. 2272 */ 2273 if (bge_encap(sc, m_head, &prodidx)) { 2274 IF_PREPEND(&ifp->if_snd, m_head); 2275 ifp->if_flags |= IFF_OACTIVE; 2276 break; 2277 } 2278 2279 /* 2280 * If there's a BPF listener, bounce a copy of this frame 2281 * to him. 2282 */ 2283 BPF_MTAP(ifp, m_head); 2284 } 2285 2286 /* Transmit */ 2287 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2288 2289 /* 2290 * Set a timeout in case the chip goes out to lunch. 2291 */ 2292 ifp->if_timer = 5; 2293 2294 return; 2295 } 2296 2297 /* 2298 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2299 * program its internal DSP. Failing to do this can result in 2300 * massive packet loss at 1Gb speeds. 2301 */ 2302 static void 2303 bge_phy_hack(sc) 2304 struct bge_softc *sc; 2305 { 2306 struct bge_bcom_hack bhack[] = { 2307 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2308 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2309 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2310 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2311 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2312 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2313 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2314 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2315 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2316 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2317 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2318 { 0, 0 } }; 2319 u_int16_t vid, did; 2320 int i; 2321 2322 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2323 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2324 2325 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2326 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2327 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2328 i = 0; 2329 while(bhack[i].reg) { 2330 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2331 bhack[i].val); 2332 i++; 2333 } 2334 } 2335 2336 return; 2337 } 2338 2339 static void 2340 bge_init(xsc) 2341 void *xsc; 2342 { 2343 struct bge_softc *sc = xsc; 2344 struct ifnet *ifp; 2345 u_int16_t *m; 2346 int s; 2347 2348 s = splimp(); 2349 2350 ifp = &sc->arpcom.ac_if; 2351 2352 if (ifp->if_flags & IFF_RUNNING) { 2353 splx(s); 2354 return; 2355 } 2356 2357 /* Cancel pending I/O and flush buffers. */ 2358 bge_stop(sc); 2359 bge_reset(sc); 2360 bge_chipinit(sc); 2361 2362 /* 2363 * Init the various state machines, ring 2364 * control blocks and firmware. 2365 */ 2366 if (bge_blockinit(sc)) { 2367 printf("bge%d: initialization failure\n", sc->bge_unit); 2368 splx(s); 2369 return; 2370 } 2371 2372 ifp = &sc->arpcom.ac_if; 2373 2374 /* Specify MTU. */ 2375 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2376 ETHER_HDR_LEN + ETHER_CRC_LEN); 2377 2378 /* Load our MAC address. */ 2379 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2380 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2381 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2382 2383 /* Enable or disable promiscuous mode as needed. */ 2384 if (ifp->if_flags & IFF_PROMISC) { 2385 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2386 } else { 2387 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2388 } 2389 2390 /* Program multicast filter. */ 2391 bge_setmulti(sc); 2392 2393 /* Init RX ring. */ 2394 bge_init_rx_ring_std(sc); 2395 2396 /* Init jumbo RX ring. */ 2397 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2398 bge_init_rx_ring_jumbo(sc); 2399 2400 /* Init our RX return ring index */ 2401 sc->bge_rx_saved_considx = 0; 2402 2403 /* Init TX ring. */ 2404 bge_init_tx_ring(sc); 2405 2406 /* Turn on transmitter */ 2407 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2408 2409 /* Turn on receiver */ 2410 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2411 2412 /* Tell firmware we're alive. */ 2413 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2414 2415 /* Enable host interrupts. */ 2416 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2417 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2418 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2419 2420 bge_ifmedia_upd(ifp); 2421 2422 ifp->if_flags |= IFF_RUNNING; 2423 ifp->if_flags &= ~IFF_OACTIVE; 2424 2425 splx(s); 2426 2427 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2428 2429 return; 2430 } 2431 2432 /* 2433 * Set media options. 2434 */ 2435 static int 2436 bge_ifmedia_upd(ifp) 2437 struct ifnet *ifp; 2438 { 2439 struct bge_softc *sc; 2440 struct mii_data *mii; 2441 struct ifmedia *ifm; 2442 2443 sc = ifp->if_softc; 2444 ifm = &sc->bge_ifmedia; 2445 2446 /* If this is a 1000baseX NIC, enable the TBI port. */ 2447 if (sc->bge_tbi) { 2448 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2449 return(EINVAL); 2450 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2451 case IFM_AUTO: 2452 break; 2453 case IFM_1000_SX: 2454 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2455 BGE_CLRBIT(sc, BGE_MAC_MODE, 2456 BGE_MACMODE_HALF_DUPLEX); 2457 } else { 2458 BGE_SETBIT(sc, BGE_MAC_MODE, 2459 BGE_MACMODE_HALF_DUPLEX); 2460 } 2461 break; 2462 default: 2463 return(EINVAL); 2464 } 2465 return(0); 2466 } 2467 2468 mii = device_get_softc(sc->bge_miibus); 2469 sc->bge_link = 0; 2470 if (mii->mii_instance) { 2471 struct mii_softc *miisc; 2472 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2473 miisc = LIST_NEXT(miisc, mii_list)) 2474 mii_phy_reset(miisc); 2475 } 2476 bge_phy_hack(sc); 2477 mii_mediachg(mii); 2478 2479 return(0); 2480 } 2481 2482 /* 2483 * Report current media status. 2484 */ 2485 static void 2486 bge_ifmedia_sts(ifp, ifmr) 2487 struct ifnet *ifp; 2488 struct ifmediareq *ifmr; 2489 { 2490 struct bge_softc *sc; 2491 struct mii_data *mii; 2492 2493 sc = ifp->if_softc; 2494 2495 if (sc->bge_tbi) { 2496 ifmr->ifm_status = IFM_AVALID; 2497 ifmr->ifm_active = IFM_ETHER; 2498 if (CSR_READ_4(sc, BGE_MAC_STS) & 2499 BGE_MACSTAT_TBI_PCS_SYNCHED) 2500 ifmr->ifm_status |= IFM_ACTIVE; 2501 ifmr->ifm_active |= IFM_1000_SX; 2502 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2503 ifmr->ifm_active |= IFM_HDX; 2504 else 2505 ifmr->ifm_active |= IFM_FDX; 2506 return; 2507 } 2508 2509 mii = device_get_softc(sc->bge_miibus); 2510 mii_pollstat(mii); 2511 ifmr->ifm_active = mii->mii_media_active; 2512 ifmr->ifm_status = mii->mii_media_status; 2513 2514 return; 2515 } 2516 2517 static int 2518 bge_ioctl(ifp, command, data) 2519 struct ifnet *ifp; 2520 u_long command; 2521 caddr_t data; 2522 { 2523 struct bge_softc *sc = ifp->if_softc; 2524 struct ifreq *ifr = (struct ifreq *) data; 2525 int s, mask, error = 0; 2526 struct mii_data *mii; 2527 2528 s = splimp(); 2529 2530 switch(command) { 2531 case SIOCSIFMTU: 2532 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2533 error = EINVAL; 2534 else { 2535 ifp->if_mtu = ifr->ifr_mtu; 2536 ifp->if_flags &= ~IFF_RUNNING; 2537 bge_init(sc); 2538 } 2539 break; 2540 case SIOCSIFFLAGS: 2541 if (ifp->if_flags & IFF_UP) { 2542 /* 2543 * If only the state of the PROMISC flag changed, 2544 * then just use the 'set promisc mode' command 2545 * instead of reinitializing the entire NIC. Doing 2546 * a full re-init means reloading the firmware and 2547 * waiting for it to start up, which may take a 2548 * second or two. 2549 */ 2550 if (ifp->if_flags & IFF_RUNNING && 2551 ifp->if_flags & IFF_PROMISC && 2552 !(sc->bge_if_flags & IFF_PROMISC)) { 2553 BGE_SETBIT(sc, BGE_RX_MODE, 2554 BGE_RXMODE_RX_PROMISC); 2555 } else if (ifp->if_flags & IFF_RUNNING && 2556 !(ifp->if_flags & IFF_PROMISC) && 2557 sc->bge_if_flags & IFF_PROMISC) { 2558 BGE_CLRBIT(sc, BGE_RX_MODE, 2559 BGE_RXMODE_RX_PROMISC); 2560 } else 2561 bge_init(sc); 2562 } else { 2563 if (ifp->if_flags & IFF_RUNNING) { 2564 bge_stop(sc); 2565 } 2566 } 2567 sc->bge_if_flags = ifp->if_flags; 2568 error = 0; 2569 break; 2570 case SIOCADDMULTI: 2571 case SIOCDELMULTI: 2572 if (ifp->if_flags & IFF_RUNNING) { 2573 bge_setmulti(sc); 2574 error = 0; 2575 } 2576 break; 2577 case SIOCSIFMEDIA: 2578 case SIOCGIFMEDIA: 2579 if (sc->bge_tbi) { 2580 error = ifmedia_ioctl(ifp, ifr, 2581 &sc->bge_ifmedia, command); 2582 } else { 2583 mii = device_get_softc(sc->bge_miibus); 2584 error = ifmedia_ioctl(ifp, ifr, 2585 &mii->mii_media, command); 2586 } 2587 break; 2588 case SIOCSIFCAP: 2589 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2590 if (mask & IFCAP_HWCSUM) { 2591 if (IFCAP_HWCSUM & ifp->if_capenable) 2592 ifp->if_capenable &= ~IFCAP_HWCSUM; 2593 else 2594 ifp->if_capenable |= IFCAP_HWCSUM; 2595 } 2596 error = 0; 2597 break; 2598 default: 2599 error = ether_ioctl(ifp, command, data); 2600 break; 2601 } 2602 2603 (void)splx(s); 2604 2605 return(error); 2606 } 2607 2608 static void 2609 bge_watchdog(ifp) 2610 struct ifnet *ifp; 2611 { 2612 struct bge_softc *sc; 2613 2614 sc = ifp->if_softc; 2615 2616 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2617 2618 ifp->if_flags &= ~IFF_RUNNING; 2619 bge_init(sc); 2620 2621 ifp->if_oerrors++; 2622 2623 return; 2624 } 2625 2626 /* 2627 * Stop the adapter and free any mbufs allocated to the 2628 * RX and TX lists. 2629 */ 2630 static void 2631 bge_stop(sc) 2632 struct bge_softc *sc; 2633 { 2634 struct ifnet *ifp; 2635 struct ifmedia_entry *ifm; 2636 struct mii_data *mii = NULL; 2637 int mtmp, itmp; 2638 2639 ifp = &sc->arpcom.ac_if; 2640 2641 if (!sc->bge_tbi) 2642 mii = device_get_softc(sc->bge_miibus); 2643 2644 untimeout(bge_tick, sc, sc->bge_stat_ch); 2645 2646 /* 2647 * Disable all of the receiver blocks 2648 */ 2649 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2650 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2651 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2652 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2653 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2654 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2655 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2656 2657 /* 2658 * Disable all of the transmit blocks 2659 */ 2660 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2661 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2662 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2663 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2664 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2665 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2666 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2667 2668 /* 2669 * Shut down all of the memory managers and related 2670 * state machines. 2671 */ 2672 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2673 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2674 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2675 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2676 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2677 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2678 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2679 2680 /* Disable host interrupts. */ 2681 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2682 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2683 2684 /* 2685 * Tell firmware we're shutting down. 2686 */ 2687 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2688 2689 /* Free the RX lists. */ 2690 bge_free_rx_ring_std(sc); 2691 2692 /* Free jumbo RX list. */ 2693 bge_free_rx_ring_jumbo(sc); 2694 2695 /* Free TX buffers. */ 2696 bge_free_tx_ring(sc); 2697 2698 /* 2699 * Isolate/power down the PHY, but leave the media selection 2700 * unchanged so that things will be put back to normal when 2701 * we bring the interface back up. 2702 */ 2703 if (!sc->bge_tbi) { 2704 itmp = ifp->if_flags; 2705 ifp->if_flags |= IFF_UP; 2706 ifm = mii->mii_media.ifm_cur; 2707 mtmp = ifm->ifm_media; 2708 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2709 mii_mediachg(mii); 2710 ifm->ifm_media = mtmp; 2711 ifp->if_flags = itmp; 2712 } 2713 2714 sc->bge_link = 0; 2715 2716 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2717 2718 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2719 2720 return; 2721 } 2722 2723 /* 2724 * Stop all chip I/O so that the kernel's probe routines don't 2725 * get confused by errant DMAs when rebooting. 2726 */ 2727 static void 2728 bge_shutdown(dev) 2729 device_t dev; 2730 { 2731 struct bge_softc *sc; 2732 2733 sc = device_get_softc(dev); 2734 2735 bge_stop(sc); 2736 bge_reset(sc); 2737 2738 return; 2739 } 2740