1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 41 * 42 * The Broadcom BCM5700 is based on technology originally developed by 43 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 44 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 45 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 46 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 47 * frames, highly configurable RX filtering, and 16 RX and TX queues 48 * (which, along with RX filter rules, can be used for QOS applications). 49 * Other features, such as TCP segmentation, may be available as part 50 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 51 * firmware images can be stored in hardware and need not be compiled 52 * into the driver. 53 * 54 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 55 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 56 * 57 * The BCM5701 is a single-chip solution incorporating both the BCM5700 58 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 59 * does not support external SSRAM. 60 * 61 * Broadcom also produces a variation of the BCM5700 under the "Altima" 62 * brand name, which is functionally similar but lacks PCI-X support. 63 * 64 * Without external SSRAM, you can only have at most 4 TX rings, 65 * and the use of the mini RX ring is disabled. This seems to imply 66 * that these features are simply not available on the BCM5701. As a 67 * result, this driver does not implement any support for the mini RX 68 * ring. 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_device_polling.h" 73 #endif 74 75 #include <sys/param.h> 76 #include <sys/endian.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/module.h> 83 #include <sys/socket.h> 84 #include <sys/sysctl.h> 85 #include <sys/taskqueue.h> 86 87 #include <net/if.h> 88 #include <net/if_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <net/if_types.h> 97 #include <net/if_vlan_var.h> 98 99 #include <netinet/in_systm.h> 100 #include <netinet/in.h> 101 #include <netinet/ip.h> 102 #include <netinet/tcp.h> 103 #include <netinet/netdump/netdump.h> 104 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 #include "miidevs.h" 113 #include <dev/mii/brgphyreg.h> 114 115 #ifdef __sparc64__ 116 #include <dev/ofw/ofw_bus.h> 117 #include <dev/ofw/openfirm.h> 118 #include <machine/ofw_machdep.h> 119 #include <machine/ver.h> 120 #endif 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 125 #include <dev/bge/if_bgereg.h> 126 127 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 128 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 129 130 MODULE_DEPEND(bge, pci, 1, 1, 1); 131 MODULE_DEPEND(bge, ether, 1, 1, 1); 132 MODULE_DEPEND(bge, miibus, 1, 1, 1); 133 134 /* "device miibus" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 /* 138 * Various supported device vendors/types and their names. Note: the 139 * spec seems to indicate that the hardware still has Alteon's vendor 140 * ID burned into it, though it will always be overriden by the vendor 141 * ID in the EEPROM. Just to be safe, we cover all possibilities. 142 */ 143 static const struct bge_type { 144 uint16_t bge_vid; 145 uint16_t bge_did; 146 } bge_devs[] = { 147 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 148 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 149 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 151 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 152 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 153 154 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 155 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 238 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 239 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 240 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 241 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 242 243 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 244 245 { TC_VENDORID, TC_DEVICEID_3C996 }, 246 247 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 248 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 249 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 250 251 { 0, 0 } 252 }; 253 254 static const struct bge_vendor { 255 uint16_t v_id; 256 const char *v_name; 257 } bge_vendors[] = { 258 { ALTEON_VENDORID, "Alteon" }, 259 { ALTIMA_VENDORID, "Altima" }, 260 { APPLE_VENDORID, "Apple" }, 261 { BCOM_VENDORID, "Broadcom" }, 262 { SK_VENDORID, "SysKonnect" }, 263 { TC_VENDORID, "3Com" }, 264 { FJTSU_VENDORID, "Fujitsu" }, 265 266 { 0, NULL } 267 }; 268 269 static const struct bge_revision { 270 uint32_t br_chipid; 271 const char *br_name; 272 } bge_revisions[] = { 273 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 274 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 275 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 276 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 277 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 278 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 279 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 280 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 281 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 282 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 283 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 284 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 285 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 286 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 287 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 288 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 289 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 290 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 291 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 292 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 293 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 294 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 295 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 296 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 297 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 298 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 299 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 300 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 301 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 302 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 303 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 304 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 305 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 306 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 307 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 308 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 309 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 310 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 311 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 312 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 313 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 314 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 315 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 316 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 317 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 318 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" }, 319 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 320 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 321 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 322 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 323 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 324 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 325 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 326 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 327 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 328 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 329 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 330 /* 5754 and 5787 share the same ASIC ID */ 331 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 332 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 333 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 334 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 335 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 336 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 337 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 338 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 339 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 340 341 { 0, NULL } 342 }; 343 344 /* 345 * Some defaults for major revisions, so that newer steppings 346 * that we don't know about have a shot at working. 347 */ 348 static const struct bge_revision bge_majorrevs[] = { 349 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 350 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 351 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 352 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 353 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 354 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 355 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 356 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 357 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 358 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 359 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 360 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 361 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 362 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 363 /* 5754 and 5787 share the same ASIC ID */ 364 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 365 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 366 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 367 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 368 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 369 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 370 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 371 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 372 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 373 374 { 0, NULL } 375 }; 376 377 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 378 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 379 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 380 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 381 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 382 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 383 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 384 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 385 386 static uint32_t bge_chipid(device_t); 387 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 388 static const struct bge_revision * bge_lookup_rev(uint32_t); 389 390 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 391 392 static int bge_probe(device_t); 393 static int bge_attach(device_t); 394 static int bge_detach(device_t); 395 static int bge_suspend(device_t); 396 static int bge_resume(device_t); 397 static void bge_release_resources(struct bge_softc *); 398 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 399 static int bge_dma_alloc(struct bge_softc *); 400 static void bge_dma_free(struct bge_softc *); 401 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 402 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 403 404 static void bge_devinfo(struct bge_softc *); 405 static int bge_mbox_reorder(struct bge_softc *); 406 407 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 408 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 409 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 410 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 411 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 412 413 static void bge_txeof(struct bge_softc *, uint16_t); 414 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 415 static int bge_rxeof(struct bge_softc *, uint16_t, int); 416 417 static void bge_asf_driver_up (struct bge_softc *); 418 static void bge_tick(void *); 419 static void bge_stats_clear_regs(struct bge_softc *); 420 static void bge_stats_update(struct bge_softc *); 421 static void bge_stats_update_regs(struct bge_softc *); 422 static struct mbuf *bge_check_short_dma(struct mbuf *); 423 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 424 uint16_t *, uint16_t *); 425 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 426 427 static void bge_intr(void *); 428 static int bge_msi_intr(void *); 429 static void bge_intr_task(void *, int); 430 static void bge_start(if_t); 431 static void bge_start_locked(if_t); 432 static void bge_start_tx(struct bge_softc *, uint32_t); 433 static int bge_ioctl(if_t, u_long, caddr_t); 434 static void bge_init_locked(struct bge_softc *); 435 static void bge_init(void *); 436 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 437 static void bge_stop(struct bge_softc *); 438 static void bge_watchdog(struct bge_softc *); 439 static int bge_shutdown(device_t); 440 static int bge_ifmedia_upd_locked(if_t); 441 static int bge_ifmedia_upd(if_t); 442 static void bge_ifmedia_sts(if_t, struct ifmediareq *); 443 static uint64_t bge_get_counter(if_t, ift_counter); 444 445 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 446 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 447 448 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 449 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 450 451 static void bge_setpromisc(struct bge_softc *); 452 static void bge_setmulti(struct bge_softc *); 453 static void bge_setvlan(struct bge_softc *); 454 455 static __inline void bge_rxreuse_std(struct bge_softc *, int); 456 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 457 static int bge_newbuf_std(struct bge_softc *, int); 458 static int bge_newbuf_jumbo(struct bge_softc *, int); 459 static int bge_init_rx_ring_std(struct bge_softc *); 460 static void bge_free_rx_ring_std(struct bge_softc *); 461 static int bge_init_rx_ring_jumbo(struct bge_softc *); 462 static void bge_free_rx_ring_jumbo(struct bge_softc *); 463 static void bge_free_tx_ring(struct bge_softc *); 464 static int bge_init_tx_ring(struct bge_softc *); 465 466 static int bge_chipinit(struct bge_softc *); 467 static int bge_blockinit(struct bge_softc *); 468 static uint32_t bge_dma_swap_options(struct bge_softc *); 469 470 static int bge_has_eaddr(struct bge_softc *); 471 static uint32_t bge_readmem_ind(struct bge_softc *, int); 472 static void bge_writemem_ind(struct bge_softc *, int, int); 473 static void bge_writembx(struct bge_softc *, int, int); 474 #ifdef notdef 475 static uint32_t bge_readreg_ind(struct bge_softc *, int); 476 #endif 477 static void bge_writemem_direct(struct bge_softc *, int, int); 478 static void bge_writereg_ind(struct bge_softc *, int, int); 479 480 static int bge_miibus_readreg(device_t, int, int); 481 static int bge_miibus_writereg(device_t, int, int, int); 482 static void bge_miibus_statchg(device_t); 483 #ifdef DEVICE_POLLING 484 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 485 #endif 486 487 #define BGE_RESET_SHUTDOWN 0 488 #define BGE_RESET_START 1 489 #define BGE_RESET_SUSPEND 2 490 static void bge_sig_post_reset(struct bge_softc *, int); 491 static void bge_sig_legacy(struct bge_softc *, int); 492 static void bge_sig_pre_reset(struct bge_softc *, int); 493 static void bge_stop_fw(struct bge_softc *); 494 static int bge_reset(struct bge_softc *); 495 static void bge_link_upd(struct bge_softc *); 496 497 static void bge_ape_lock_init(struct bge_softc *); 498 static void bge_ape_read_fw_ver(struct bge_softc *); 499 static int bge_ape_lock(struct bge_softc *, int); 500 static void bge_ape_unlock(struct bge_softc *, int); 501 static void bge_ape_send_event(struct bge_softc *, uint32_t); 502 static void bge_ape_driver_state_change(struct bge_softc *, int); 503 504 /* 505 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 506 * leak information to untrusted users. It is also known to cause alignment 507 * traps on certain architectures. 508 */ 509 #ifdef BGE_REGISTER_DEBUG 510 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 511 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 512 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 513 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 514 #endif 515 static void bge_add_sysctls(struct bge_softc *); 516 static void bge_add_sysctl_stats_regs(struct bge_softc *, 517 struct sysctl_ctx_list *, struct sysctl_oid_list *); 518 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 519 struct sysctl_oid_list *); 520 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 521 522 NETDUMP_DEFINE(bge); 523 524 static device_method_t bge_methods[] = { 525 /* Device interface */ 526 DEVMETHOD(device_probe, bge_probe), 527 DEVMETHOD(device_attach, bge_attach), 528 DEVMETHOD(device_detach, bge_detach), 529 DEVMETHOD(device_shutdown, bge_shutdown), 530 DEVMETHOD(device_suspend, bge_suspend), 531 DEVMETHOD(device_resume, bge_resume), 532 533 /* MII interface */ 534 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 535 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 536 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 537 538 DEVMETHOD_END 539 }; 540 541 static driver_t bge_driver = { 542 "bge", 543 bge_methods, 544 sizeof(struct bge_softc) 545 }; 546 547 static devclass_t bge_devclass; 548 549 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 550 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs, 551 nitems(bge_devs) - 1); 552 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 553 554 static int bge_allow_asf = 1; 555 556 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 557 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 558 "Allow ASF mode if available"); 559 560 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 561 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 562 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 563 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 564 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 565 566 static int 567 bge_has_eaddr(struct bge_softc *sc) 568 { 569 #ifdef __sparc64__ 570 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 571 device_t dev; 572 uint32_t subvendor; 573 574 dev = sc->bge_dev; 575 576 /* 577 * The on-board BGEs found in sun4u machines aren't fitted with 578 * an EEPROM which means that we have to obtain the MAC address 579 * via OFW and that some tests will always fail. We distinguish 580 * such BGEs by the subvendor ID, which also has to be obtained 581 * from OFW instead of the PCI configuration space as the latter 582 * indicates Broadcom as the subvendor of the netboot interface. 583 * For early Blade 1500 and 2500 we even have to check the OFW 584 * device path as the subvendor ID always defaults to Broadcom 585 * there. 586 */ 587 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 588 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 589 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 590 return (0); 591 memset(buf, 0, sizeof(buf)); 592 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 593 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 594 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 595 return (0); 596 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 597 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 598 return (0); 599 } 600 #endif 601 return (1); 602 } 603 604 static uint32_t 605 bge_readmem_ind(struct bge_softc *sc, int off) 606 { 607 device_t dev; 608 uint32_t val; 609 610 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 611 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 612 return (0); 613 614 dev = sc->bge_dev; 615 616 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 617 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 618 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 619 return (val); 620 } 621 622 static void 623 bge_writemem_ind(struct bge_softc *sc, int off, int val) 624 { 625 device_t dev; 626 627 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 628 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 629 return; 630 631 dev = sc->bge_dev; 632 633 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 634 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 635 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 636 } 637 638 #ifdef notdef 639 static uint32_t 640 bge_readreg_ind(struct bge_softc *sc, int off) 641 { 642 device_t dev; 643 644 dev = sc->bge_dev; 645 646 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 647 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 648 } 649 #endif 650 651 static void 652 bge_writereg_ind(struct bge_softc *sc, int off, int val) 653 { 654 device_t dev; 655 656 dev = sc->bge_dev; 657 658 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 659 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 660 } 661 662 static void 663 bge_writemem_direct(struct bge_softc *sc, int off, int val) 664 { 665 CSR_WRITE_4(sc, off, val); 666 } 667 668 static void 669 bge_writembx(struct bge_softc *sc, int off, int val) 670 { 671 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 672 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 673 674 CSR_WRITE_4(sc, off, val); 675 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 676 CSR_READ_4(sc, off); 677 } 678 679 /* 680 * Clear all stale locks and select the lock for this driver instance. 681 */ 682 static void 683 bge_ape_lock_init(struct bge_softc *sc) 684 { 685 uint32_t bit, regbase; 686 int i; 687 688 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 689 regbase = BGE_APE_LOCK_GRANT; 690 else 691 regbase = BGE_APE_PER_LOCK_GRANT; 692 693 /* Clear any stale locks. */ 694 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 695 switch (i) { 696 case BGE_APE_LOCK_PHY0: 697 case BGE_APE_LOCK_PHY1: 698 case BGE_APE_LOCK_PHY2: 699 case BGE_APE_LOCK_PHY3: 700 bit = BGE_APE_LOCK_GRANT_DRIVER0; 701 break; 702 default: 703 if (sc->bge_func_addr == 0) 704 bit = BGE_APE_LOCK_GRANT_DRIVER0; 705 else 706 bit = (1 << sc->bge_func_addr); 707 } 708 APE_WRITE_4(sc, regbase + 4 * i, bit); 709 } 710 711 /* Select the PHY lock based on the device's function number. */ 712 switch (sc->bge_func_addr) { 713 case 0: 714 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 715 break; 716 case 1: 717 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 718 break; 719 case 2: 720 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 721 break; 722 case 3: 723 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 724 break; 725 default: 726 device_printf(sc->bge_dev, 727 "PHY lock not supported on this function\n"); 728 } 729 } 730 731 /* 732 * Check for APE firmware, set flags, and print version info. 733 */ 734 static void 735 bge_ape_read_fw_ver(struct bge_softc *sc) 736 { 737 const char *fwtype; 738 uint32_t apedata, features; 739 740 /* Check for a valid APE signature in shared memory. */ 741 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 742 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 743 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 744 return; 745 } 746 747 /* Check if APE firmware is running. */ 748 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 749 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 750 device_printf(sc->bge_dev, "APE signature found " 751 "but FW status not ready! 0x%08x\n", apedata); 752 return; 753 } 754 755 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 756 757 /* Fetch the APE firwmare type and version. */ 758 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 759 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 760 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 761 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 762 fwtype = "NCSI"; 763 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 764 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 765 fwtype = "DASH"; 766 } else 767 fwtype = "UNKN"; 768 769 /* Print the APE firmware version. */ 770 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 771 fwtype, 772 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 773 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 774 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 775 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 776 } 777 778 static int 779 bge_ape_lock(struct bge_softc *sc, int locknum) 780 { 781 uint32_t bit, gnt, req, status; 782 int i, off; 783 784 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 785 return (0); 786 787 /* Lock request/grant registers have different bases. */ 788 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 789 req = BGE_APE_LOCK_REQ; 790 gnt = BGE_APE_LOCK_GRANT; 791 } else { 792 req = BGE_APE_PER_LOCK_REQ; 793 gnt = BGE_APE_PER_LOCK_GRANT; 794 } 795 796 off = 4 * locknum; 797 798 switch (locknum) { 799 case BGE_APE_LOCK_GPIO: 800 /* Lock required when using GPIO. */ 801 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 802 return (0); 803 if (sc->bge_func_addr == 0) 804 bit = BGE_APE_LOCK_REQ_DRIVER0; 805 else 806 bit = (1 << sc->bge_func_addr); 807 break; 808 case BGE_APE_LOCK_GRC: 809 /* Lock required to reset the device. */ 810 if (sc->bge_func_addr == 0) 811 bit = BGE_APE_LOCK_REQ_DRIVER0; 812 else 813 bit = (1 << sc->bge_func_addr); 814 break; 815 case BGE_APE_LOCK_MEM: 816 /* Lock required when accessing certain APE memory. */ 817 if (sc->bge_func_addr == 0) 818 bit = BGE_APE_LOCK_REQ_DRIVER0; 819 else 820 bit = (1 << sc->bge_func_addr); 821 break; 822 case BGE_APE_LOCK_PHY0: 823 case BGE_APE_LOCK_PHY1: 824 case BGE_APE_LOCK_PHY2: 825 case BGE_APE_LOCK_PHY3: 826 /* Lock required when accessing PHYs. */ 827 bit = BGE_APE_LOCK_REQ_DRIVER0; 828 break; 829 default: 830 return (EINVAL); 831 } 832 833 /* Request a lock. */ 834 APE_WRITE_4(sc, req + off, bit); 835 836 /* Wait up to 1 second to acquire lock. */ 837 for (i = 0; i < 20000; i++) { 838 status = APE_READ_4(sc, gnt + off); 839 if (status == bit) 840 break; 841 DELAY(50); 842 } 843 844 /* Handle any errors. */ 845 if (status != bit) { 846 device_printf(sc->bge_dev, "APE lock %d request failed! " 847 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 848 locknum, req + off, bit & 0xFFFF, gnt + off, 849 status & 0xFFFF); 850 /* Revoke the lock request. */ 851 APE_WRITE_4(sc, gnt + off, bit); 852 return (EBUSY); 853 } 854 855 return (0); 856 } 857 858 static void 859 bge_ape_unlock(struct bge_softc *sc, int locknum) 860 { 861 uint32_t bit, gnt; 862 int off; 863 864 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 865 return; 866 867 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 868 gnt = BGE_APE_LOCK_GRANT; 869 else 870 gnt = BGE_APE_PER_LOCK_GRANT; 871 872 off = 4 * locknum; 873 874 switch (locknum) { 875 case BGE_APE_LOCK_GPIO: 876 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 877 return; 878 if (sc->bge_func_addr == 0) 879 bit = BGE_APE_LOCK_GRANT_DRIVER0; 880 else 881 bit = (1 << sc->bge_func_addr); 882 break; 883 case BGE_APE_LOCK_GRC: 884 if (sc->bge_func_addr == 0) 885 bit = BGE_APE_LOCK_GRANT_DRIVER0; 886 else 887 bit = (1 << sc->bge_func_addr); 888 break; 889 case BGE_APE_LOCK_MEM: 890 if (sc->bge_func_addr == 0) 891 bit = BGE_APE_LOCK_GRANT_DRIVER0; 892 else 893 bit = (1 << sc->bge_func_addr); 894 break; 895 case BGE_APE_LOCK_PHY0: 896 case BGE_APE_LOCK_PHY1: 897 case BGE_APE_LOCK_PHY2: 898 case BGE_APE_LOCK_PHY3: 899 bit = BGE_APE_LOCK_GRANT_DRIVER0; 900 break; 901 default: 902 return; 903 } 904 905 APE_WRITE_4(sc, gnt + off, bit); 906 } 907 908 /* 909 * Send an event to the APE firmware. 910 */ 911 static void 912 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 913 { 914 uint32_t apedata; 915 int i; 916 917 /* NCSI does not support APE events. */ 918 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 919 return; 920 921 /* Wait up to 1ms for APE to service previous event. */ 922 for (i = 10; i > 0; i--) { 923 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 924 break; 925 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 926 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 927 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 928 BGE_APE_EVENT_STATUS_EVENT_PENDING); 929 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 930 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 931 break; 932 } 933 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 934 DELAY(100); 935 } 936 if (i == 0) 937 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 938 event); 939 } 940 941 static void 942 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 943 { 944 uint32_t apedata, event; 945 946 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 947 return; 948 949 switch (kind) { 950 case BGE_RESET_START: 951 /* If this is the first load, clear the load counter. */ 952 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 953 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 954 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 955 else { 956 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 957 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 958 } 959 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 960 BGE_APE_HOST_SEG_SIG_MAGIC); 961 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 962 BGE_APE_HOST_SEG_LEN_MAGIC); 963 964 /* Add some version info if bge(4) supports it. */ 965 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 966 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 967 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 968 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 969 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 970 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 971 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 972 BGE_APE_HOST_DRVR_STATE_START); 973 event = BGE_APE_EVENT_STATUS_STATE_START; 974 break; 975 case BGE_RESET_SHUTDOWN: 976 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 977 BGE_APE_HOST_DRVR_STATE_UNLOAD); 978 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 979 break; 980 case BGE_RESET_SUSPEND: 981 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 982 break; 983 default: 984 return; 985 } 986 987 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 988 BGE_APE_EVENT_STATUS_STATE_CHNGE); 989 } 990 991 /* 992 * Map a single buffer address. 993 */ 994 995 static void 996 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 997 { 998 struct bge_dmamap_arg *ctx; 999 1000 if (error) 1001 return; 1002 1003 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 1004 1005 ctx = arg; 1006 ctx->bge_busaddr = segs->ds_addr; 1007 } 1008 1009 static uint8_t 1010 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1011 { 1012 uint32_t access, byte = 0; 1013 int i; 1014 1015 /* Lock. */ 1016 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1017 for (i = 0; i < 8000; i++) { 1018 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1019 break; 1020 DELAY(20); 1021 } 1022 if (i == 8000) 1023 return (1); 1024 1025 /* Enable access. */ 1026 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1027 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1028 1029 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1030 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1031 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1032 DELAY(10); 1033 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1034 DELAY(10); 1035 break; 1036 } 1037 } 1038 1039 if (i == BGE_TIMEOUT * 10) { 1040 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1041 return (1); 1042 } 1043 1044 /* Get result. */ 1045 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1046 1047 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1048 1049 /* Disable access. */ 1050 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1051 1052 /* Unlock. */ 1053 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1054 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1055 1056 return (0); 1057 } 1058 1059 /* 1060 * Read a sequence of bytes from NVRAM. 1061 */ 1062 static int 1063 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1064 { 1065 int err = 0, i; 1066 uint8_t byte = 0; 1067 1068 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1069 return (1); 1070 1071 for (i = 0; i < cnt; i++) { 1072 err = bge_nvram_getbyte(sc, off + i, &byte); 1073 if (err) 1074 break; 1075 *(dest + i) = byte; 1076 } 1077 1078 return (err ? 1 : 0); 1079 } 1080 1081 /* 1082 * Read a byte of data stored in the EEPROM at address 'addr.' The 1083 * BCM570x supports both the traditional bitbang interface and an 1084 * auto access interface for reading the EEPROM. We use the auto 1085 * access method. 1086 */ 1087 static uint8_t 1088 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1089 { 1090 int i; 1091 uint32_t byte = 0; 1092 1093 /* 1094 * Enable use of auto EEPROM access so we can avoid 1095 * having to use the bitbang method. 1096 */ 1097 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1098 1099 /* Reset the EEPROM, load the clock period. */ 1100 CSR_WRITE_4(sc, BGE_EE_ADDR, 1101 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1102 DELAY(20); 1103 1104 /* Issue the read EEPROM command. */ 1105 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1106 1107 /* Wait for completion */ 1108 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1109 DELAY(10); 1110 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1111 break; 1112 } 1113 1114 if (i == BGE_TIMEOUT * 10) { 1115 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1116 return (1); 1117 } 1118 1119 /* Get result. */ 1120 byte = CSR_READ_4(sc, BGE_EE_DATA); 1121 1122 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * Read a sequence of bytes from the EEPROM. 1129 */ 1130 static int 1131 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1132 { 1133 int i, error = 0; 1134 uint8_t byte = 0; 1135 1136 for (i = 0; i < cnt; i++) { 1137 error = bge_eeprom_getbyte(sc, off + i, &byte); 1138 if (error) 1139 break; 1140 *(dest + i) = byte; 1141 } 1142 1143 return (error ? 1 : 0); 1144 } 1145 1146 static int 1147 bge_miibus_readreg(device_t dev, int phy, int reg) 1148 { 1149 struct bge_softc *sc; 1150 uint32_t val; 1151 int i; 1152 1153 sc = device_get_softc(dev); 1154 1155 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1156 return (0); 1157 1158 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1159 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1160 CSR_WRITE_4(sc, BGE_MI_MODE, 1161 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1162 DELAY(80); 1163 } 1164 1165 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1166 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1167 1168 /* Poll for the PHY register access to complete. */ 1169 for (i = 0; i < BGE_TIMEOUT; i++) { 1170 DELAY(10); 1171 val = CSR_READ_4(sc, BGE_MI_COMM); 1172 if ((val & BGE_MICOMM_BUSY) == 0) { 1173 DELAY(5); 1174 val = CSR_READ_4(sc, BGE_MI_COMM); 1175 break; 1176 } 1177 } 1178 1179 if (i == BGE_TIMEOUT) { 1180 device_printf(sc->bge_dev, 1181 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1182 phy, reg, val); 1183 val = 0; 1184 } 1185 1186 /* Restore the autopoll bit if necessary. */ 1187 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1188 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1189 DELAY(80); 1190 } 1191 1192 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1193 1194 if (val & BGE_MICOMM_READFAIL) 1195 return (0); 1196 1197 return (val & 0xFFFF); 1198 } 1199 1200 static int 1201 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1202 { 1203 struct bge_softc *sc; 1204 int i; 1205 1206 sc = device_get_softc(dev); 1207 1208 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1209 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1210 return (0); 1211 1212 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1213 return (0); 1214 1215 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1216 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1217 CSR_WRITE_4(sc, BGE_MI_MODE, 1218 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1219 DELAY(80); 1220 } 1221 1222 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1223 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1224 1225 for (i = 0; i < BGE_TIMEOUT; i++) { 1226 DELAY(10); 1227 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1228 DELAY(5); 1229 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1230 break; 1231 } 1232 } 1233 1234 /* Restore the autopoll bit if necessary. */ 1235 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1236 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1237 DELAY(80); 1238 } 1239 1240 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1241 1242 if (i == BGE_TIMEOUT) 1243 device_printf(sc->bge_dev, 1244 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1245 phy, reg, val); 1246 1247 return (0); 1248 } 1249 1250 static void 1251 bge_miibus_statchg(device_t dev) 1252 { 1253 struct bge_softc *sc; 1254 struct mii_data *mii; 1255 uint32_t mac_mode, rx_mode, tx_mode; 1256 1257 sc = device_get_softc(dev); 1258 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1259 return; 1260 mii = device_get_softc(sc->bge_miibus); 1261 1262 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1263 (IFM_ACTIVE | IFM_AVALID)) { 1264 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1265 case IFM_10_T: 1266 case IFM_100_TX: 1267 sc->bge_link = 1; 1268 break; 1269 case IFM_1000_T: 1270 case IFM_1000_SX: 1271 case IFM_2500_SX: 1272 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1273 sc->bge_link = 1; 1274 else 1275 sc->bge_link = 0; 1276 break; 1277 default: 1278 sc->bge_link = 0; 1279 break; 1280 } 1281 } else 1282 sc->bge_link = 0; 1283 if (sc->bge_link == 0) 1284 return; 1285 1286 /* 1287 * APE firmware touches these registers to keep the MAC 1288 * connected to the outside world. Try to keep the 1289 * accesses atomic. 1290 */ 1291 1292 /* Set the port mode (MII/GMII) to match the link speed. */ 1293 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1294 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1295 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1296 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1297 1298 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1299 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1300 mac_mode |= BGE_PORTMODE_GMII; 1301 else 1302 mac_mode |= BGE_PORTMODE_MII; 1303 1304 /* Set MAC flow control behavior to match link flow control settings. */ 1305 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1306 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1307 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1308 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1309 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1310 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1311 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1312 } else 1313 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1314 1315 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1316 DELAY(40); 1317 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1318 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1319 } 1320 1321 /* 1322 * Intialize a standard receive ring descriptor. 1323 */ 1324 static int 1325 bge_newbuf_std(struct bge_softc *sc, int i) 1326 { 1327 struct mbuf *m; 1328 struct bge_rx_bd *r; 1329 bus_dma_segment_t segs[1]; 1330 bus_dmamap_t map; 1331 int error, nsegs; 1332 1333 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1334 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1335 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1336 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1337 if (m == NULL) 1338 return (ENOBUFS); 1339 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1340 } else { 1341 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1342 if (m == NULL) 1343 return (ENOBUFS); 1344 m->m_len = m->m_pkthdr.len = MCLBYTES; 1345 } 1346 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1347 m_adj(m, ETHER_ALIGN); 1348 1349 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1350 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1351 if (error != 0) { 1352 m_freem(m); 1353 return (error); 1354 } 1355 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1356 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1357 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1358 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1359 sc->bge_cdata.bge_rx_std_dmamap[i]); 1360 } 1361 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1362 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1363 sc->bge_cdata.bge_rx_std_sparemap = map; 1364 sc->bge_cdata.bge_rx_std_chain[i] = m; 1365 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1366 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1367 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1368 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1369 r->bge_flags = BGE_RXBDFLAG_END; 1370 r->bge_len = segs[0].ds_len; 1371 r->bge_idx = i; 1372 1373 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1374 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1375 1376 return (0); 1377 } 1378 1379 /* 1380 * Initialize a jumbo receive ring descriptor. This allocates 1381 * a jumbo buffer from the pool managed internally by the driver. 1382 */ 1383 static int 1384 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1385 { 1386 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1387 bus_dmamap_t map; 1388 struct bge_extrx_bd *r; 1389 struct mbuf *m; 1390 int error, nsegs; 1391 1392 MGETHDR(m, M_NOWAIT, MT_DATA); 1393 if (m == NULL) 1394 return (ENOBUFS); 1395 1396 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) { 1397 m_freem(m); 1398 return (ENOBUFS); 1399 } 1400 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1401 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1402 m_adj(m, ETHER_ALIGN); 1403 1404 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1405 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1406 if (error != 0) { 1407 m_freem(m); 1408 return (error); 1409 } 1410 1411 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1412 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1413 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1414 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1415 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1416 } 1417 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1418 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1419 sc->bge_cdata.bge_rx_jumbo_sparemap; 1420 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1421 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1422 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1423 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1424 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1425 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1426 1427 /* 1428 * Fill in the extended RX buffer descriptor. 1429 */ 1430 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1431 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1432 r->bge_idx = i; 1433 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1434 switch (nsegs) { 1435 case 4: 1436 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1437 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1438 r->bge_len3 = segs[3].ds_len; 1439 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1440 case 3: 1441 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1442 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1443 r->bge_len2 = segs[2].ds_len; 1444 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1445 case 2: 1446 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1447 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1448 r->bge_len1 = segs[1].ds_len; 1449 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1450 case 1: 1451 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1452 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1453 r->bge_len0 = segs[0].ds_len; 1454 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1455 break; 1456 default: 1457 panic("%s: %d segments\n", __func__, nsegs); 1458 } 1459 1460 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1461 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1462 1463 return (0); 1464 } 1465 1466 static int 1467 bge_init_rx_ring_std(struct bge_softc *sc) 1468 { 1469 int error, i; 1470 1471 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1472 sc->bge_std = 0; 1473 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1474 if ((error = bge_newbuf_std(sc, i)) != 0) 1475 return (error); 1476 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1477 } 1478 1479 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1480 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1481 1482 sc->bge_std = 0; 1483 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1484 1485 return (0); 1486 } 1487 1488 static void 1489 bge_free_rx_ring_std(struct bge_softc *sc) 1490 { 1491 int i; 1492 1493 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1494 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1495 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1496 sc->bge_cdata.bge_rx_std_dmamap[i], 1497 BUS_DMASYNC_POSTREAD); 1498 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1499 sc->bge_cdata.bge_rx_std_dmamap[i]); 1500 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1501 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1502 } 1503 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1504 sizeof(struct bge_rx_bd)); 1505 } 1506 } 1507 1508 static int 1509 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1510 { 1511 struct bge_rcb *rcb; 1512 int error, i; 1513 1514 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1515 sc->bge_jumbo = 0; 1516 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1517 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1518 return (error); 1519 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1520 } 1521 1522 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1523 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1524 1525 sc->bge_jumbo = 0; 1526 1527 /* Enable the jumbo receive producer ring. */ 1528 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1529 rcb->bge_maxlen_flags = 1530 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1531 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1532 1533 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1534 1535 return (0); 1536 } 1537 1538 static void 1539 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1540 { 1541 int i; 1542 1543 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1544 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1545 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1546 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1547 BUS_DMASYNC_POSTREAD); 1548 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1549 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1550 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1551 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1552 } 1553 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1554 sizeof(struct bge_extrx_bd)); 1555 } 1556 } 1557 1558 static void 1559 bge_free_tx_ring(struct bge_softc *sc) 1560 { 1561 int i; 1562 1563 if (sc->bge_ldata.bge_tx_ring == NULL) 1564 return; 1565 1566 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1567 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1568 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1569 sc->bge_cdata.bge_tx_dmamap[i], 1570 BUS_DMASYNC_POSTWRITE); 1571 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1572 sc->bge_cdata.bge_tx_dmamap[i]); 1573 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1574 sc->bge_cdata.bge_tx_chain[i] = NULL; 1575 } 1576 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1577 sizeof(struct bge_tx_bd)); 1578 } 1579 } 1580 1581 static int 1582 bge_init_tx_ring(struct bge_softc *sc) 1583 { 1584 sc->bge_txcnt = 0; 1585 sc->bge_tx_saved_considx = 0; 1586 1587 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1588 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1589 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1590 1591 /* Initialize transmit producer index for host-memory send ring. */ 1592 sc->bge_tx_prodidx = 0; 1593 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1594 1595 /* 5700 b2 errata */ 1596 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1597 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1598 1599 /* NIC-memory send ring not used; initialize to zero. */ 1600 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1601 /* 5700 b2 errata */ 1602 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1603 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1604 1605 return (0); 1606 } 1607 1608 static void 1609 bge_setpromisc(struct bge_softc *sc) 1610 { 1611 if_t ifp; 1612 1613 BGE_LOCK_ASSERT(sc); 1614 1615 ifp = sc->bge_ifp; 1616 1617 /* Enable or disable promiscuous mode as needed. */ 1618 if (if_getflags(ifp) & IFF_PROMISC) 1619 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1620 else 1621 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1622 } 1623 1624 static void 1625 bge_setmulti(struct bge_softc *sc) 1626 { 1627 if_t ifp; 1628 int mc_count = 0; 1629 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1630 int h, i, mcnt; 1631 unsigned char *mta; 1632 1633 BGE_LOCK_ASSERT(sc); 1634 1635 ifp = sc->bge_ifp; 1636 1637 mc_count = if_multiaddr_count(ifp, -1); 1638 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * 1639 mc_count, M_DEVBUF, M_NOWAIT); 1640 1641 if(mta == NULL) { 1642 device_printf(sc->bge_dev, 1643 "Failed to allocated temp mcast list\n"); 1644 return; 1645 } 1646 1647 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 1648 for (i = 0; i < 4; i++) 1649 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1650 free(mta, M_DEVBUF); 1651 return; 1652 } 1653 1654 /* First, zot all the existing filters. */ 1655 for (i = 0; i < 4; i++) 1656 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1657 1658 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 1659 for(i = 0; i < mcnt; i++) { 1660 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 1661 ETHER_ADDR_LEN) & 0x7F; 1662 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1663 } 1664 1665 for (i = 0; i < 4; i++) 1666 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1667 1668 free(mta, M_DEVBUF); 1669 } 1670 1671 static void 1672 bge_setvlan(struct bge_softc *sc) 1673 { 1674 if_t ifp; 1675 1676 BGE_LOCK_ASSERT(sc); 1677 1678 ifp = sc->bge_ifp; 1679 1680 /* Enable or disable VLAN tag stripping as needed. */ 1681 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1682 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1683 else 1684 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1685 } 1686 1687 static void 1688 bge_sig_pre_reset(struct bge_softc *sc, int type) 1689 { 1690 1691 /* 1692 * Some chips don't like this so only do this if ASF is enabled 1693 */ 1694 if (sc->bge_asf_mode) 1695 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1696 1697 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1698 switch (type) { 1699 case BGE_RESET_START: 1700 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1701 BGE_FW_DRV_STATE_START); 1702 break; 1703 case BGE_RESET_SHUTDOWN: 1704 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1705 BGE_FW_DRV_STATE_UNLOAD); 1706 break; 1707 case BGE_RESET_SUSPEND: 1708 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1709 BGE_FW_DRV_STATE_SUSPEND); 1710 break; 1711 } 1712 } 1713 1714 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1715 bge_ape_driver_state_change(sc, type); 1716 } 1717 1718 static void 1719 bge_sig_post_reset(struct bge_softc *sc, int type) 1720 { 1721 1722 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1723 switch (type) { 1724 case BGE_RESET_START: 1725 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1726 BGE_FW_DRV_STATE_START_DONE); 1727 /* START DONE */ 1728 break; 1729 case BGE_RESET_SHUTDOWN: 1730 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1731 BGE_FW_DRV_STATE_UNLOAD_DONE); 1732 break; 1733 } 1734 } 1735 if (type == BGE_RESET_SHUTDOWN) 1736 bge_ape_driver_state_change(sc, type); 1737 } 1738 1739 static void 1740 bge_sig_legacy(struct bge_softc *sc, int type) 1741 { 1742 1743 if (sc->bge_asf_mode) { 1744 switch (type) { 1745 case BGE_RESET_START: 1746 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1747 BGE_FW_DRV_STATE_START); 1748 break; 1749 case BGE_RESET_SHUTDOWN: 1750 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1751 BGE_FW_DRV_STATE_UNLOAD); 1752 break; 1753 } 1754 } 1755 } 1756 1757 static void 1758 bge_stop_fw(struct bge_softc *sc) 1759 { 1760 int i; 1761 1762 if (sc->bge_asf_mode) { 1763 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1764 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1765 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1766 1767 for (i = 0; i < 100; i++ ) { 1768 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1769 BGE_RX_CPU_DRV_EVENT)) 1770 break; 1771 DELAY(10); 1772 } 1773 } 1774 } 1775 1776 static uint32_t 1777 bge_dma_swap_options(struct bge_softc *sc) 1778 { 1779 uint32_t dma_options; 1780 1781 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1782 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1783 #if BYTE_ORDER == BIG_ENDIAN 1784 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1785 #endif 1786 return (dma_options); 1787 } 1788 1789 /* 1790 * Do endian, PCI and DMA initialization. 1791 */ 1792 static int 1793 bge_chipinit(struct bge_softc *sc) 1794 { 1795 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1796 uint16_t val; 1797 int i; 1798 1799 /* Set endianness before we access any non-PCI registers. */ 1800 misc_ctl = BGE_INIT; 1801 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1802 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1803 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1804 1805 /* 1806 * Clear the MAC statistics block in the NIC's 1807 * internal memory. 1808 */ 1809 for (i = BGE_STATS_BLOCK; 1810 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1811 BGE_MEMWIN_WRITE(sc, i, 0); 1812 1813 for (i = BGE_STATUS_BLOCK; 1814 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1815 BGE_MEMWIN_WRITE(sc, i, 0); 1816 1817 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1818 /* 1819 * Fix data corruption caused by non-qword write with WB. 1820 * Fix master abort in PCI mode. 1821 * Fix PCI latency timer. 1822 */ 1823 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1824 val |= (1 << 10) | (1 << 12) | (1 << 13); 1825 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1826 } 1827 1828 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1829 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1830 /* 1831 * For the 57766 and non Ax versions of 57765, bootcode 1832 * needs to setup the PCIE Fast Training Sequence (FTS) 1833 * value to prevent transmit hangs. 1834 */ 1835 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1836 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1837 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1838 BGE_CPMU_PADRNG_CTL_RDIV2); 1839 } 1840 } 1841 1842 /* 1843 * Set up the PCI DMA control register. 1844 */ 1845 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1846 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1847 if (sc->bge_flags & BGE_FLAG_PCIE) { 1848 if (sc->bge_mps >= 256) 1849 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1850 else 1851 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1852 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1853 if (BGE_IS_5714_FAMILY(sc)) { 1854 /* 256 bytes for read and write. */ 1855 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1856 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1857 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1858 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1859 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1860 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1861 /* 1862 * In the BCM5703, the DMA read watermark should 1863 * be set to less than or equal to the maximum 1864 * memory read byte count of the PCI-X command 1865 * register. 1866 */ 1867 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1868 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1869 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1870 /* 1536 bytes for read, 384 bytes for write. */ 1871 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1872 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1873 } else { 1874 /* 384 bytes for read and write. */ 1875 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1876 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1877 0x0F; 1878 } 1879 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1880 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1881 uint32_t tmp; 1882 1883 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1884 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1885 if (tmp == 6 || tmp == 7) 1886 dma_rw_ctl |= 1887 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1888 1889 /* Set PCI-X DMA write workaround. */ 1890 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1891 } 1892 } else { 1893 /* Conventional PCI bus: 256 bytes for read and write. */ 1894 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1895 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1896 1897 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1898 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1899 dma_rw_ctl |= 0x0F; 1900 } 1901 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1902 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1903 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1904 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1905 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1906 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1907 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1908 if (BGE_IS_5717_PLUS(sc)) { 1909 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1910 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1911 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1912 /* 1913 * Enable HW workaround for controllers that misinterpret 1914 * a status tag update and leave interrupts permanently 1915 * disabled. 1916 */ 1917 if (!BGE_IS_57765_PLUS(sc) && 1918 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1919 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1920 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1921 } 1922 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1923 1924 /* 1925 * Set up general mode register. 1926 */ 1927 mode_ctl = bge_dma_swap_options(sc); 1928 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1929 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1930 /* Retain Host-2-BMC settings written by APE firmware. */ 1931 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1932 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1933 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1934 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1935 } 1936 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1937 BGE_MODECTL_TX_NO_PHDR_CSUM; 1938 1939 /* 1940 * BCM5701 B5 have a bug causing data corruption when using 1941 * 64-bit DMA reads, which can be terminated early and then 1942 * completed later as 32-bit accesses, in combination with 1943 * certain bridges. 1944 */ 1945 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1946 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1947 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1948 1949 /* 1950 * Tell the firmware the driver is running 1951 */ 1952 if (sc->bge_asf_mode & ASF_STACKUP) 1953 mode_ctl |= BGE_MODECTL_STACKUP; 1954 1955 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1956 1957 /* 1958 * Disable memory write invalidate. Apparently it is not supported 1959 * properly by these devices. 1960 */ 1961 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1962 1963 /* Set the timer prescaler (always 66 MHz). */ 1964 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1965 1966 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1967 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1968 DELAY(40); /* XXX */ 1969 1970 /* Put PHY into ready state */ 1971 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1972 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1973 DELAY(40); 1974 } 1975 1976 return (0); 1977 } 1978 1979 static int 1980 bge_blockinit(struct bge_softc *sc) 1981 { 1982 struct bge_rcb *rcb; 1983 bus_size_t vrcb; 1984 bge_hostaddr taddr; 1985 uint32_t dmactl, rdmareg, val; 1986 int i, limit; 1987 1988 /* 1989 * Initialize the memory window pointer register so that 1990 * we can access the first 32K of internal NIC RAM. This will 1991 * allow us to set up the TX send ring RCBs and the RX return 1992 * ring RCBs, plus other things which live in NIC memory. 1993 */ 1994 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1995 1996 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1997 1998 if (!(BGE_IS_5705_PLUS(sc))) { 1999 /* Configure mbuf memory pool */ 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2001 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 2002 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2003 else 2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2005 2006 /* Configure DMA resource pool */ 2007 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2008 BGE_DMA_DESCRIPTORS); 2009 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2010 } 2011 2012 /* Configure mbuf pool watermarks */ 2013 if (BGE_IS_5717_PLUS(sc)) { 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2015 if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2018 } else { 2019 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2020 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2021 } 2022 } else if (!BGE_IS_5705_PLUS(sc)) { 2023 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2024 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2025 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2026 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2027 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2028 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2029 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2030 } else { 2031 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2032 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2033 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2034 } 2035 2036 /* Configure DMA resource watermarks */ 2037 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2038 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2039 2040 /* Enable buffer manager */ 2041 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2042 /* 2043 * Change the arbitration algorithm of TXMBUF read request to 2044 * round-robin instead of priority based for BCM5719. When 2045 * TXFIFO is almost empty, RDMA will hold its request until 2046 * TXFIFO is not almost empty. 2047 */ 2048 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2049 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2050 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2051 2052 /* Poll for buffer manager start indication */ 2053 for (i = 0; i < BGE_TIMEOUT; i++) { 2054 DELAY(10); 2055 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2056 break; 2057 } 2058 2059 if (i == BGE_TIMEOUT) { 2060 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2061 return (ENXIO); 2062 } 2063 2064 /* Enable flow-through queues */ 2065 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2066 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2067 2068 /* Wait until queue initialization is complete */ 2069 for (i = 0; i < BGE_TIMEOUT; i++) { 2070 DELAY(10); 2071 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2072 break; 2073 } 2074 2075 if (i == BGE_TIMEOUT) { 2076 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2077 return (ENXIO); 2078 } 2079 2080 /* 2081 * Summary of rings supported by the controller: 2082 * 2083 * Standard Receive Producer Ring 2084 * - This ring is used to feed receive buffers for "standard" 2085 * sized frames (typically 1536 bytes) to the controller. 2086 * 2087 * Jumbo Receive Producer Ring 2088 * - This ring is used to feed receive buffers for jumbo sized 2089 * frames (i.e. anything bigger than the "standard" frames) 2090 * to the controller. 2091 * 2092 * Mini Receive Producer Ring 2093 * - This ring is used to feed receive buffers for "mini" 2094 * sized frames to the controller. 2095 * - This feature required external memory for the controller 2096 * but was never used in a production system. Should always 2097 * be disabled. 2098 * 2099 * Receive Return Ring 2100 * - After the controller has placed an incoming frame into a 2101 * receive buffer that buffer is moved into a receive return 2102 * ring. The driver is then responsible to passing the 2103 * buffer up to the stack. Many versions of the controller 2104 * support multiple RR rings. 2105 * 2106 * Send Ring 2107 * - This ring is used for outgoing frames. Many versions of 2108 * the controller support multiple send rings. 2109 */ 2110 2111 /* Initialize the standard receive producer ring control block. */ 2112 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2113 rcb->bge_hostaddr.bge_addr_lo = 2114 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2115 rcb->bge_hostaddr.bge_addr_hi = 2116 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2117 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2118 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2119 if (BGE_IS_5717_PLUS(sc)) { 2120 /* 2121 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2122 * Bits 15-2 : Maximum RX frame size 2123 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2124 * Bit 0 : Reserved 2125 */ 2126 rcb->bge_maxlen_flags = 2127 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2128 } else if (BGE_IS_5705_PLUS(sc)) { 2129 /* 2130 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2131 * Bits 15-2 : Reserved (should be 0) 2132 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2133 * Bit 0 : Reserved 2134 */ 2135 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2136 } else { 2137 /* 2138 * Ring size is always XXX entries 2139 * Bits 31-16: Maximum RX frame size 2140 * Bits 15-2 : Reserved (should be 0) 2141 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2142 * Bit 0 : Reserved 2143 */ 2144 rcb->bge_maxlen_flags = 2145 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2146 } 2147 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2148 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2149 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2150 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2151 else 2152 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2153 /* Write the standard receive producer ring control block. */ 2154 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2155 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2156 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2157 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2158 2159 /* Reset the standard receive producer ring producer index. */ 2160 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2161 2162 /* 2163 * Initialize the jumbo RX producer ring control 2164 * block. We set the 'ring disabled' bit in the 2165 * flags field until we're actually ready to start 2166 * using this ring (i.e. once we set the MTU 2167 * high enough to require it). 2168 */ 2169 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2170 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2171 /* Get the jumbo receive producer ring RCB parameters. */ 2172 rcb->bge_hostaddr.bge_addr_lo = 2173 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2174 rcb->bge_hostaddr.bge_addr_hi = 2175 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2176 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2177 sc->bge_cdata.bge_rx_jumbo_ring_map, 2178 BUS_DMASYNC_PREREAD); 2179 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2180 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2181 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2182 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2183 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2184 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2185 else 2186 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2187 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2188 rcb->bge_hostaddr.bge_addr_hi); 2189 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2190 rcb->bge_hostaddr.bge_addr_lo); 2191 /* Program the jumbo receive producer ring RCB parameters. */ 2192 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2193 rcb->bge_maxlen_flags); 2194 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2195 /* Reset the jumbo receive producer ring producer index. */ 2196 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2197 } 2198 2199 /* Disable the mini receive producer ring RCB. */ 2200 if (BGE_IS_5700_FAMILY(sc)) { 2201 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2202 rcb->bge_maxlen_flags = 2203 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2204 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2205 rcb->bge_maxlen_flags); 2206 /* Reset the mini receive producer ring producer index. */ 2207 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2208 } 2209 2210 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2211 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2212 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2213 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2214 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2215 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2216 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2217 } 2218 /* 2219 * The BD ring replenish thresholds control how often the 2220 * hardware fetches new BD's from the producer rings in host 2221 * memory. Setting the value too low on a busy system can 2222 * starve the hardware and recue the throughpout. 2223 * 2224 * Set the BD ring replentish thresholds. The recommended 2225 * values are 1/8th the number of descriptors allocated to 2226 * each ring. 2227 * XXX The 5754 requires a lower threshold, so it might be a 2228 * requirement of all 575x family chips. The Linux driver sets 2229 * the lower threshold for all 5705 family chips as well, but there 2230 * are reports that it might not need to be so strict. 2231 * 2232 * XXX Linux does some extra fiddling here for the 5906 parts as 2233 * well. 2234 */ 2235 if (BGE_IS_5705_PLUS(sc)) 2236 val = 8; 2237 else 2238 val = BGE_STD_RX_RING_CNT / 8; 2239 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2240 if (BGE_IS_JUMBO_CAPABLE(sc)) 2241 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2242 BGE_JUMBO_RX_RING_CNT/8); 2243 if (BGE_IS_5717_PLUS(sc)) { 2244 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2245 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2246 } 2247 2248 /* 2249 * Disable all send rings by setting the 'ring disabled' bit 2250 * in the flags field of all the TX send ring control blocks, 2251 * located in NIC memory. 2252 */ 2253 if (!BGE_IS_5705_PLUS(sc)) 2254 /* 5700 to 5704 had 16 send rings. */ 2255 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2256 else if (BGE_IS_57765_PLUS(sc) || 2257 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2258 limit = 2; 2259 else if (BGE_IS_5717_PLUS(sc)) 2260 limit = 4; 2261 else 2262 limit = 1; 2263 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2264 for (i = 0; i < limit; i++) { 2265 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2266 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2267 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2268 vrcb += sizeof(struct bge_rcb); 2269 } 2270 2271 /* Configure send ring RCB 0 (we use only the first ring) */ 2272 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2273 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2274 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2275 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2276 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2277 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2278 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2279 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2280 else 2281 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2282 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2283 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2284 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2285 2286 /* 2287 * Disable all receive return rings by setting the 2288 * 'ring diabled' bit in the flags field of all the receive 2289 * return ring control blocks, located in NIC memory. 2290 */ 2291 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2292 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2293 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2294 /* Should be 17, use 16 until we get an SRAM map. */ 2295 limit = 16; 2296 } else if (!BGE_IS_5705_PLUS(sc)) 2297 limit = BGE_RX_RINGS_MAX; 2298 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2299 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2300 BGE_IS_57765_PLUS(sc)) 2301 limit = 4; 2302 else 2303 limit = 1; 2304 /* Disable all receive return rings. */ 2305 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2306 for (i = 0; i < limit; i++) { 2307 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2308 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2309 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2310 BGE_RCB_FLAG_RING_DISABLED); 2311 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2312 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2313 (i * (sizeof(uint64_t))), 0); 2314 vrcb += sizeof(struct bge_rcb); 2315 } 2316 2317 /* 2318 * Set up receive return ring 0. Note that the NIC address 2319 * for RX return rings is 0x0. The return rings live entirely 2320 * within the host, so the nicaddr field in the RCB isn't used. 2321 */ 2322 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2323 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2324 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2325 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2326 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2327 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2328 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2329 2330 /* Set random backoff seed for TX */ 2331 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2332 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2333 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2334 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2335 BGE_TX_BACKOFF_SEED_MASK); 2336 2337 /* Set inter-packet gap */ 2338 val = 0x2620; 2339 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2340 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2341 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2342 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2343 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2344 2345 /* 2346 * Specify which ring to use for packets that don't match 2347 * any RX rules. 2348 */ 2349 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2350 2351 /* 2352 * Configure number of RX lists. One interrupt distribution 2353 * list, sixteen active lists, one bad frames class. 2354 */ 2355 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2356 2357 /* Inialize RX list placement stats mask. */ 2358 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2359 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2360 2361 /* Disable host coalescing until we get it set up */ 2362 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2363 2364 /* Poll to make sure it's shut down. */ 2365 for (i = 0; i < BGE_TIMEOUT; i++) { 2366 DELAY(10); 2367 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2368 break; 2369 } 2370 2371 if (i == BGE_TIMEOUT) { 2372 device_printf(sc->bge_dev, 2373 "host coalescing engine failed to idle\n"); 2374 return (ENXIO); 2375 } 2376 2377 /* Set up host coalescing defaults */ 2378 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2379 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2380 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2381 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2382 if (!(BGE_IS_5705_PLUS(sc))) { 2383 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2384 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2385 } 2386 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2387 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2388 2389 /* Set up address of statistics block */ 2390 if (!(BGE_IS_5705_PLUS(sc))) { 2391 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2392 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2393 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2394 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2395 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2396 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2397 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2398 } 2399 2400 /* Set up address of status block */ 2401 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2402 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2403 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2404 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2405 2406 /* Set up status block size. */ 2407 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2408 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2409 val = BGE_STATBLKSZ_FULL; 2410 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2411 } else { 2412 val = BGE_STATBLKSZ_32BYTE; 2413 bzero(sc->bge_ldata.bge_status_block, 32); 2414 } 2415 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2416 sc->bge_cdata.bge_status_map, 2417 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2418 2419 /* Turn on host coalescing state machine */ 2420 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2421 2422 /* Turn on RX BD completion state machine and enable attentions */ 2423 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2424 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2425 2426 /* Turn on RX list placement state machine */ 2427 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2428 2429 /* Turn on RX list selector state machine. */ 2430 if (!(BGE_IS_5705_PLUS(sc))) 2431 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2432 2433 /* Turn on DMA, clear stats. */ 2434 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2435 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2436 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2437 BGE_MACMODE_FRMHDR_DMA_ENB; 2438 2439 if (sc->bge_flags & BGE_FLAG_TBI) 2440 val |= BGE_PORTMODE_TBI; 2441 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2442 val |= BGE_PORTMODE_GMII; 2443 else 2444 val |= BGE_PORTMODE_MII; 2445 2446 /* Allow APE to send/receive frames. */ 2447 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2448 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2449 2450 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2451 DELAY(40); 2452 2453 /* Set misc. local control, enable interrupts on attentions */ 2454 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2455 2456 #ifdef notdef 2457 /* Assert GPIO pins for PHY reset */ 2458 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2459 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2460 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2461 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2462 #endif 2463 2464 /* Turn on DMA completion state machine */ 2465 if (!(BGE_IS_5705_PLUS(sc))) 2466 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2467 2468 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2469 2470 /* Enable host coalescing bug fix. */ 2471 if (BGE_IS_5755_PLUS(sc)) 2472 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2473 2474 /* Request larger DMA burst size to get better performance. */ 2475 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2476 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2477 2478 /* Turn on write DMA state machine */ 2479 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2480 DELAY(40); 2481 2482 /* Turn on read DMA state machine */ 2483 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2484 2485 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2486 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2487 2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2489 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2490 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2491 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2492 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2493 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2494 if (sc->bge_flags & BGE_FLAG_PCIE) 2495 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2496 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2497 val |= BGE_RDMAMODE_TSO4_ENABLE; 2498 if (sc->bge_flags & BGE_FLAG_TSO3 || 2499 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2500 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2501 val |= BGE_RDMAMODE_TSO6_ENABLE; 2502 } 2503 2504 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2505 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2506 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2507 BGE_RDMAMODE_H2BNC_VLAN_DET; 2508 /* 2509 * Allow multiple outstanding read requests from 2510 * non-LSO read DMA engine. 2511 */ 2512 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2513 } 2514 2515 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2516 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2517 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2518 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2519 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2520 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2521 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2522 else 2523 rdmareg = BGE_RDMA_RSRVCTRL; 2524 dmactl = CSR_READ_4(sc, rdmareg); 2525 /* 2526 * Adjust tx margin to prevent TX data corruption and 2527 * fix internal FIFO overflow. 2528 */ 2529 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2530 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2531 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2532 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2533 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2534 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2535 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2536 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2537 } 2538 /* 2539 * Enable fix for read DMA FIFO overruns. 2540 * The fix is to limit the number of RX BDs 2541 * the hardware would fetch at a fime. 2542 */ 2543 CSR_WRITE_4(sc, rdmareg, dmactl | 2544 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2545 } 2546 2547 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2548 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2549 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2550 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2551 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2552 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2553 /* 2554 * Allow 4KB burst length reads for non-LSO frames. 2555 * Enable 512B burst length reads for buffer descriptors. 2556 */ 2557 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2558 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2559 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2560 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2561 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2562 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2563 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2564 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2565 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2566 } 2567 2568 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2569 DELAY(40); 2570 2571 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2572 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2573 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2574 if ((val & 0xFFFF) > BGE_FRAMELEN) 2575 break; 2576 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2577 break; 2578 } 2579 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2580 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2581 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2582 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2583 else 2584 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2585 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2586 } 2587 } 2588 2589 /* Turn on RX data completion state machine */ 2590 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2591 2592 /* Turn on RX BD initiator state machine */ 2593 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2594 2595 /* Turn on RX data and RX BD initiator state machine */ 2596 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2597 2598 /* Turn on Mbuf cluster free state machine */ 2599 if (!(BGE_IS_5705_PLUS(sc))) 2600 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2601 2602 /* Turn on send BD completion state machine */ 2603 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2604 2605 /* Turn on send data completion state machine */ 2606 val = BGE_SDCMODE_ENABLE; 2607 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2608 val |= BGE_SDCMODE_CDELAY; 2609 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2610 2611 /* Turn on send data initiator state machine */ 2612 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2613 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2614 BGE_SDIMODE_HW_LSO_PRE_DMA); 2615 else 2616 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2617 2618 /* Turn on send BD initiator state machine */ 2619 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2620 2621 /* Turn on send BD selector state machine */ 2622 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2623 2624 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2625 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2626 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2627 2628 /* ack/clear link change events */ 2629 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2630 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2631 BGE_MACSTAT_LINK_CHANGED); 2632 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2633 2634 /* 2635 * Enable attention when the link has changed state for 2636 * devices that use auto polling. 2637 */ 2638 if (sc->bge_flags & BGE_FLAG_TBI) { 2639 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2640 } else { 2641 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2642 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2643 DELAY(80); 2644 } 2645 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2646 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2647 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2648 BGE_EVTENB_MI_INTERRUPT); 2649 } 2650 2651 /* 2652 * Clear any pending link state attention. 2653 * Otherwise some link state change events may be lost until attention 2654 * is cleared by bge_intr() -> bge_link_upd() sequence. 2655 * It's not necessary on newer BCM chips - perhaps enabling link 2656 * state change attentions implies clearing pending attention. 2657 */ 2658 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2659 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2660 BGE_MACSTAT_LINK_CHANGED); 2661 2662 /* Enable link state change attentions. */ 2663 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2664 2665 return (0); 2666 } 2667 2668 static const struct bge_revision * 2669 bge_lookup_rev(uint32_t chipid) 2670 { 2671 const struct bge_revision *br; 2672 2673 for (br = bge_revisions; br->br_name != NULL; br++) { 2674 if (br->br_chipid == chipid) 2675 return (br); 2676 } 2677 2678 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2679 if (br->br_chipid == BGE_ASICREV(chipid)) 2680 return (br); 2681 } 2682 2683 return (NULL); 2684 } 2685 2686 static const struct bge_vendor * 2687 bge_lookup_vendor(uint16_t vid) 2688 { 2689 const struct bge_vendor *v; 2690 2691 for (v = bge_vendors; v->v_name != NULL; v++) 2692 if (v->v_id == vid) 2693 return (v); 2694 2695 return (NULL); 2696 } 2697 2698 static uint32_t 2699 bge_chipid(device_t dev) 2700 { 2701 uint32_t id; 2702 2703 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2704 BGE_PCIMISCCTL_ASICREV_SHIFT; 2705 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2706 /* 2707 * Find the ASCI revision. Different chips use different 2708 * registers. 2709 */ 2710 switch (pci_get_device(dev)) { 2711 case BCOM_DEVICEID_BCM5717C: 2712 /* 5717 C0 seems to belong to 5720 line. */ 2713 id = BGE_CHIPID_BCM5720_A0; 2714 break; 2715 case BCOM_DEVICEID_BCM5717: 2716 case BCOM_DEVICEID_BCM5718: 2717 case BCOM_DEVICEID_BCM5719: 2718 case BCOM_DEVICEID_BCM5720: 2719 case BCOM_DEVICEID_BCM5725: 2720 case BCOM_DEVICEID_BCM5727: 2721 case BCOM_DEVICEID_BCM5762: 2722 case BCOM_DEVICEID_BCM57764: 2723 case BCOM_DEVICEID_BCM57767: 2724 case BCOM_DEVICEID_BCM57787: 2725 id = pci_read_config(dev, 2726 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2727 break; 2728 case BCOM_DEVICEID_BCM57761: 2729 case BCOM_DEVICEID_BCM57762: 2730 case BCOM_DEVICEID_BCM57765: 2731 case BCOM_DEVICEID_BCM57766: 2732 case BCOM_DEVICEID_BCM57781: 2733 case BCOM_DEVICEID_BCM57782: 2734 case BCOM_DEVICEID_BCM57785: 2735 case BCOM_DEVICEID_BCM57786: 2736 case BCOM_DEVICEID_BCM57791: 2737 case BCOM_DEVICEID_BCM57795: 2738 id = pci_read_config(dev, 2739 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2740 break; 2741 default: 2742 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2743 } 2744 } 2745 return (id); 2746 } 2747 2748 /* 2749 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2750 * against our list and return its name if we find a match. 2751 * 2752 * Note that since the Broadcom controller contains VPD support, we 2753 * try to get the device name string from the controller itself instead 2754 * of the compiled-in string. It guarantees we'll always announce the 2755 * right product name. We fall back to the compiled-in string when 2756 * VPD is unavailable or corrupt. 2757 */ 2758 static int 2759 bge_probe(device_t dev) 2760 { 2761 char buf[96]; 2762 char model[64]; 2763 const struct bge_revision *br; 2764 const char *pname; 2765 struct bge_softc *sc; 2766 const struct bge_type *t = bge_devs; 2767 const struct bge_vendor *v; 2768 uint32_t id; 2769 uint16_t did, vid; 2770 2771 sc = device_get_softc(dev); 2772 sc->bge_dev = dev; 2773 vid = pci_get_vendor(dev); 2774 did = pci_get_device(dev); 2775 while(t->bge_vid != 0) { 2776 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2777 id = bge_chipid(dev); 2778 br = bge_lookup_rev(id); 2779 if (bge_has_eaddr(sc) && 2780 pci_get_vpd_ident(dev, &pname) == 0) 2781 snprintf(model, sizeof(model), "%s", pname); 2782 else { 2783 v = bge_lookup_vendor(vid); 2784 snprintf(model, sizeof(model), "%s %s", 2785 v != NULL ? v->v_name : "Unknown", 2786 br != NULL ? br->br_name : 2787 "NetXtreme/NetLink Ethernet Controller"); 2788 } 2789 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2790 model, br != NULL ? "" : "unknown ", id); 2791 device_set_desc_copy(dev, buf); 2792 return (BUS_PROBE_DEFAULT); 2793 } 2794 t++; 2795 } 2796 2797 return (ENXIO); 2798 } 2799 2800 static void 2801 bge_dma_free(struct bge_softc *sc) 2802 { 2803 int i; 2804 2805 /* Destroy DMA maps for RX buffers. */ 2806 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2807 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2808 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2809 sc->bge_cdata.bge_rx_std_dmamap[i]); 2810 } 2811 if (sc->bge_cdata.bge_rx_std_sparemap) 2812 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2813 sc->bge_cdata.bge_rx_std_sparemap); 2814 2815 /* Destroy DMA maps for jumbo RX buffers. */ 2816 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2817 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2818 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2819 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2820 } 2821 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2822 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2823 sc->bge_cdata.bge_rx_jumbo_sparemap); 2824 2825 /* Destroy DMA maps for TX buffers. */ 2826 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2827 if (sc->bge_cdata.bge_tx_dmamap[i]) 2828 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2829 sc->bge_cdata.bge_tx_dmamap[i]); 2830 } 2831 2832 if (sc->bge_cdata.bge_rx_mtag) 2833 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2834 if (sc->bge_cdata.bge_mtag_jumbo) 2835 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2836 if (sc->bge_cdata.bge_tx_mtag) 2837 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2838 2839 /* Destroy standard RX ring. */ 2840 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2841 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2842 sc->bge_cdata.bge_rx_std_ring_map); 2843 if (sc->bge_ldata.bge_rx_std_ring) 2844 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2845 sc->bge_ldata.bge_rx_std_ring, 2846 sc->bge_cdata.bge_rx_std_ring_map); 2847 2848 if (sc->bge_cdata.bge_rx_std_ring_tag) 2849 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2850 2851 /* Destroy jumbo RX ring. */ 2852 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2853 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2854 sc->bge_cdata.bge_rx_jumbo_ring_map); 2855 2856 if (sc->bge_ldata.bge_rx_jumbo_ring) 2857 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2858 sc->bge_ldata.bge_rx_jumbo_ring, 2859 sc->bge_cdata.bge_rx_jumbo_ring_map); 2860 2861 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2862 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2863 2864 /* Destroy RX return ring. */ 2865 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2866 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2867 sc->bge_cdata.bge_rx_return_ring_map); 2868 2869 if (sc->bge_ldata.bge_rx_return_ring) 2870 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2871 sc->bge_ldata.bge_rx_return_ring, 2872 sc->bge_cdata.bge_rx_return_ring_map); 2873 2874 if (sc->bge_cdata.bge_rx_return_ring_tag) 2875 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2876 2877 /* Destroy TX ring. */ 2878 if (sc->bge_ldata.bge_tx_ring_paddr) 2879 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2880 sc->bge_cdata.bge_tx_ring_map); 2881 2882 if (sc->bge_ldata.bge_tx_ring) 2883 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2884 sc->bge_ldata.bge_tx_ring, 2885 sc->bge_cdata.bge_tx_ring_map); 2886 2887 if (sc->bge_cdata.bge_tx_ring_tag) 2888 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2889 2890 /* Destroy status block. */ 2891 if (sc->bge_ldata.bge_status_block_paddr) 2892 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2893 sc->bge_cdata.bge_status_map); 2894 2895 if (sc->bge_ldata.bge_status_block) 2896 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2897 sc->bge_ldata.bge_status_block, 2898 sc->bge_cdata.bge_status_map); 2899 2900 if (sc->bge_cdata.bge_status_tag) 2901 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2902 2903 /* Destroy statistics block. */ 2904 if (sc->bge_ldata.bge_stats_paddr) 2905 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2906 sc->bge_cdata.bge_stats_map); 2907 2908 if (sc->bge_ldata.bge_stats) 2909 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2910 sc->bge_ldata.bge_stats, 2911 sc->bge_cdata.bge_stats_map); 2912 2913 if (sc->bge_cdata.bge_stats_tag) 2914 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2915 2916 if (sc->bge_cdata.bge_buffer_tag) 2917 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2918 2919 /* Destroy the parent tag. */ 2920 if (sc->bge_cdata.bge_parent_tag) 2921 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2922 } 2923 2924 static int 2925 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2926 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2927 bus_addr_t *paddr, const char *msg) 2928 { 2929 struct bge_dmamap_arg ctx; 2930 bus_addr_t lowaddr; 2931 bus_size_t ring_end; 2932 int error; 2933 2934 lowaddr = BUS_SPACE_MAXADDR; 2935 again: 2936 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2937 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2938 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2939 if (error != 0) { 2940 device_printf(sc->bge_dev, 2941 "could not create %s dma tag\n", msg); 2942 return (ENOMEM); 2943 } 2944 /* Allocate DMA'able memory for ring. */ 2945 error = bus_dmamem_alloc(*tag, (void **)ring, 2946 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2947 if (error != 0) { 2948 device_printf(sc->bge_dev, 2949 "could not allocate DMA'able memory for %s\n", msg); 2950 return (ENOMEM); 2951 } 2952 /* Load the address of the ring. */ 2953 ctx.bge_busaddr = 0; 2954 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2955 &ctx, BUS_DMA_NOWAIT); 2956 if (error != 0) { 2957 device_printf(sc->bge_dev, 2958 "could not load DMA'able memory for %s\n", msg); 2959 return (ENOMEM); 2960 } 2961 *paddr = ctx.bge_busaddr; 2962 ring_end = *paddr + maxsize; 2963 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2964 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2965 /* 2966 * 4GB boundary crossed. Limit maximum allowable DMA 2967 * address space to 32bit and try again. 2968 */ 2969 bus_dmamap_unload(*tag, *map); 2970 bus_dmamem_free(*tag, *ring, *map); 2971 bus_dma_tag_destroy(*tag); 2972 if (bootverbose) 2973 device_printf(sc->bge_dev, "4GB boundary crossed, " 2974 "limit DMA address space to 32bit for %s\n", msg); 2975 *ring = NULL; 2976 *tag = NULL; 2977 *map = NULL; 2978 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2979 goto again; 2980 } 2981 return (0); 2982 } 2983 2984 static int 2985 bge_dma_alloc(struct bge_softc *sc) 2986 { 2987 bus_addr_t lowaddr; 2988 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2989 int i, error; 2990 2991 lowaddr = BUS_SPACE_MAXADDR; 2992 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2993 lowaddr = BGE_DMA_MAXADDR; 2994 /* 2995 * Allocate the parent bus DMA tag appropriate for PCI. 2996 */ 2997 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2998 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2999 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3000 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 3001 if (error != 0) { 3002 device_printf(sc->bge_dev, 3003 "could not allocate parent dma tag\n"); 3004 return (ENOMEM); 3005 } 3006 3007 /* Create tag for standard RX ring. */ 3008 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 3009 &sc->bge_cdata.bge_rx_std_ring_tag, 3010 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 3011 &sc->bge_cdata.bge_rx_std_ring_map, 3012 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 3013 if (error) 3014 return (error); 3015 3016 /* Create tag for RX return ring. */ 3017 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 3018 &sc->bge_cdata.bge_rx_return_ring_tag, 3019 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 3020 &sc->bge_cdata.bge_rx_return_ring_map, 3021 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 3022 if (error) 3023 return (error); 3024 3025 /* Create tag for TX ring. */ 3026 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 3027 &sc->bge_cdata.bge_tx_ring_tag, 3028 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 3029 &sc->bge_cdata.bge_tx_ring_map, 3030 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 3031 if (error) 3032 return (error); 3033 3034 /* 3035 * Create tag for status block. 3036 * Because we only use single Tx/Rx/Rx return ring, use 3037 * minimum status block size except BCM5700 AX/BX which 3038 * seems to want to see full status block size regardless 3039 * of configured number of ring. 3040 */ 3041 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3042 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 3043 sbsz = BGE_STATUS_BLK_SZ; 3044 else 3045 sbsz = 32; 3046 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3047 &sc->bge_cdata.bge_status_tag, 3048 (uint8_t **)&sc->bge_ldata.bge_status_block, 3049 &sc->bge_cdata.bge_status_map, 3050 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3051 if (error) 3052 return (error); 3053 3054 /* Create tag for statistics block. */ 3055 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3056 &sc->bge_cdata.bge_stats_tag, 3057 (uint8_t **)&sc->bge_ldata.bge_stats, 3058 &sc->bge_cdata.bge_stats_map, 3059 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3060 if (error) 3061 return (error); 3062 3063 /* Create tag for jumbo RX ring. */ 3064 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3065 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3066 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3067 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3068 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3069 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3070 if (error) 3071 return (error); 3072 } 3073 3074 /* Create parent tag for buffers. */ 3075 boundary = 0; 3076 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3077 boundary = BGE_DMA_BNDRY; 3078 /* 3079 * XXX 3080 * watchdog timeout issue was observed on BCM5704 which 3081 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3082 * Both limiting DMA address space to 32bits and flushing 3083 * mailbox write seem to address the issue. 3084 */ 3085 if (sc->bge_pcixcap != 0) 3086 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3087 } 3088 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 3089 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 3090 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3091 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 3092 if (error != 0) { 3093 device_printf(sc->bge_dev, 3094 "could not allocate buffer dma tag\n"); 3095 return (ENOMEM); 3096 } 3097 /* Create tag for Tx mbufs. */ 3098 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3099 txsegsz = BGE_TSOSEG_SZ; 3100 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3101 } else { 3102 txsegsz = MCLBYTES; 3103 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3104 } 3105 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3106 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3107 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3108 &sc->bge_cdata.bge_tx_mtag); 3109 3110 if (error) { 3111 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3112 return (ENOMEM); 3113 } 3114 3115 /* Create tag for Rx mbufs. */ 3116 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3117 rxmaxsegsz = MJUM9BYTES; 3118 else 3119 rxmaxsegsz = MCLBYTES; 3120 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3121 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3122 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3123 3124 if (error) { 3125 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3126 return (ENOMEM); 3127 } 3128 3129 /* Create DMA maps for RX buffers. */ 3130 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3131 &sc->bge_cdata.bge_rx_std_sparemap); 3132 if (error) { 3133 device_printf(sc->bge_dev, 3134 "can't create spare DMA map for RX\n"); 3135 return (ENOMEM); 3136 } 3137 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3138 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3139 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3140 if (error) { 3141 device_printf(sc->bge_dev, 3142 "can't create DMA map for RX\n"); 3143 return (ENOMEM); 3144 } 3145 } 3146 3147 /* Create DMA maps for TX buffers. */ 3148 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3149 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3150 &sc->bge_cdata.bge_tx_dmamap[i]); 3151 if (error) { 3152 device_printf(sc->bge_dev, 3153 "can't create DMA map for TX\n"); 3154 return (ENOMEM); 3155 } 3156 } 3157 3158 /* Create tags for jumbo RX buffers. */ 3159 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3160 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3161 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3162 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3163 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3164 if (error) { 3165 device_printf(sc->bge_dev, 3166 "could not allocate jumbo dma tag\n"); 3167 return (ENOMEM); 3168 } 3169 /* Create DMA maps for jumbo RX buffers. */ 3170 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3171 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3172 if (error) { 3173 device_printf(sc->bge_dev, 3174 "can't create spare DMA map for jumbo RX\n"); 3175 return (ENOMEM); 3176 } 3177 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3178 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3179 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3180 if (error) { 3181 device_printf(sc->bge_dev, 3182 "can't create DMA map for jumbo RX\n"); 3183 return (ENOMEM); 3184 } 3185 } 3186 } 3187 3188 return (0); 3189 } 3190 3191 /* 3192 * Return true if this device has more than one port. 3193 */ 3194 static int 3195 bge_has_multiple_ports(struct bge_softc *sc) 3196 { 3197 device_t dev = sc->bge_dev; 3198 u_int b, d, f, fscan, s; 3199 3200 d = pci_get_domain(dev); 3201 b = pci_get_bus(dev); 3202 s = pci_get_slot(dev); 3203 f = pci_get_function(dev); 3204 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3205 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3206 return (1); 3207 return (0); 3208 } 3209 3210 /* 3211 * Return true if MSI can be used with this device. 3212 */ 3213 static int 3214 bge_can_use_msi(struct bge_softc *sc) 3215 { 3216 int can_use_msi = 0; 3217 3218 if (sc->bge_msi == 0) 3219 return (0); 3220 3221 /* Disable MSI for polling(4). */ 3222 #ifdef DEVICE_POLLING 3223 return (0); 3224 #endif 3225 switch (sc->bge_asicrev) { 3226 case BGE_ASICREV_BCM5714_A0: 3227 case BGE_ASICREV_BCM5714: 3228 /* 3229 * Apparently, MSI doesn't work when these chips are 3230 * configured in single-port mode. 3231 */ 3232 if (bge_has_multiple_ports(sc)) 3233 can_use_msi = 1; 3234 break; 3235 case BGE_ASICREV_BCM5750: 3236 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3237 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3238 can_use_msi = 1; 3239 break; 3240 case BGE_ASICREV_BCM5784: 3241 /* 3242 * Prevent infinite "watchdog timeout" errors 3243 * in some MacBook Pro and make it work out-of-the-box. 3244 */ 3245 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX) 3246 break; 3247 /* FALLTHROUGH */ 3248 default: 3249 if (BGE_IS_575X_PLUS(sc)) 3250 can_use_msi = 1; 3251 } 3252 return (can_use_msi); 3253 } 3254 3255 static int 3256 bge_mbox_reorder(struct bge_softc *sc) 3257 { 3258 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3259 static const struct mbox_reorder { 3260 const uint16_t vendor; 3261 const uint16_t device; 3262 const char *desc; 3263 } mbox_reorder_lists[] = { 3264 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3265 }; 3266 devclass_t pci, pcib; 3267 device_t bus, dev; 3268 int i; 3269 3270 pci = devclass_find("pci"); 3271 pcib = devclass_find("pcib"); 3272 dev = sc->bge_dev; 3273 bus = device_get_parent(dev); 3274 for (;;) { 3275 dev = device_get_parent(bus); 3276 bus = device_get_parent(dev); 3277 if (device_get_devclass(dev) != pcib) 3278 break; 3279 if (device_get_devclass(bus) != pci) 3280 break; 3281 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3282 if (pci_get_vendor(dev) == 3283 mbox_reorder_lists[i].vendor && 3284 pci_get_device(dev) == 3285 mbox_reorder_lists[i].device) { 3286 device_printf(sc->bge_dev, 3287 "enabling MBOX workaround for %s\n", 3288 mbox_reorder_lists[i].desc); 3289 return (1); 3290 } 3291 } 3292 } 3293 return (0); 3294 } 3295 3296 static void 3297 bge_devinfo(struct bge_softc *sc) 3298 { 3299 uint32_t cfg, clk; 3300 3301 device_printf(sc->bge_dev, 3302 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3303 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3304 if (sc->bge_flags & BGE_FLAG_PCIE) 3305 printf("PCI-E\n"); 3306 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3307 printf("PCI-X "); 3308 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3309 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3310 clk = 133; 3311 else { 3312 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3313 switch (clk) { 3314 case 0: 3315 clk = 33; 3316 break; 3317 case 2: 3318 clk = 50; 3319 break; 3320 case 4: 3321 clk = 66; 3322 break; 3323 case 6: 3324 clk = 100; 3325 break; 3326 case 7: 3327 clk = 133; 3328 break; 3329 } 3330 } 3331 printf("%u MHz\n", clk); 3332 } else { 3333 if (sc->bge_pcixcap != 0) 3334 printf("PCI on PCI-X "); 3335 else 3336 printf("PCI "); 3337 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3338 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3339 clk = 66; 3340 else 3341 clk = 33; 3342 if (cfg & BGE_PCISTATE_32BIT_BUS) 3343 printf("%u MHz; 32bit\n", clk); 3344 else 3345 printf("%u MHz; 64bit\n", clk); 3346 } 3347 } 3348 3349 static int 3350 bge_attach(device_t dev) 3351 { 3352 if_t ifp; 3353 struct bge_softc *sc; 3354 uint32_t hwcfg = 0, misccfg, pcistate; 3355 u_char eaddr[ETHER_ADDR_LEN]; 3356 int capmask, error, reg, rid, trys; 3357 3358 sc = device_get_softc(dev); 3359 sc->bge_dev = dev; 3360 3361 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3362 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3363 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3364 3365 pci_enable_busmaster(dev); 3366 3367 /* 3368 * Allocate control/status registers. 3369 */ 3370 rid = PCIR_BAR(0); 3371 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3372 RF_ACTIVE); 3373 3374 if (sc->bge_res == NULL) { 3375 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3376 error = ENXIO; 3377 goto fail; 3378 } 3379 3380 /* Save various chip information. */ 3381 sc->bge_func_addr = pci_get_function(dev); 3382 sc->bge_chipid = bge_chipid(dev); 3383 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3384 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3385 3386 /* Set default PHY address. */ 3387 sc->bge_phy_addr = 1; 3388 /* 3389 * PHY address mapping for various devices. 3390 * 3391 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3392 * ---------+-------+-------+-------+-------+ 3393 * BCM57XX | 1 | X | X | X | 3394 * BCM5704 | 1 | X | 1 | X | 3395 * BCM5717 | 1 | 8 | 2 | 9 | 3396 * BCM5719 | 1 | 8 | 2 | 9 | 3397 * BCM5720 | 1 | 8 | 2 | 9 | 3398 * 3399 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3400 * ---------+-------+-------+-------+-------+ 3401 * BCM57XX | X | X | X | X | 3402 * BCM5704 | X | X | X | X | 3403 * BCM5717 | X | X | X | X | 3404 * BCM5719 | 3 | 10 | 4 | 11 | 3405 * BCM5720 | X | X | X | X | 3406 * 3407 * Other addresses may respond but they are not 3408 * IEEE compliant PHYs and should be ignored. 3409 */ 3410 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3411 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3412 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3413 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3414 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3415 BGE_SGDIGSTS_IS_SERDES) 3416 sc->bge_phy_addr = sc->bge_func_addr + 8; 3417 else 3418 sc->bge_phy_addr = sc->bge_func_addr + 1; 3419 } else { 3420 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3421 BGE_CPMU_PHY_STRAP_IS_SERDES) 3422 sc->bge_phy_addr = sc->bge_func_addr + 8; 3423 else 3424 sc->bge_phy_addr = sc->bge_func_addr + 1; 3425 } 3426 } 3427 3428 if (bge_has_eaddr(sc)) 3429 sc->bge_flags |= BGE_FLAG_EADDR; 3430 3431 /* Save chipset family. */ 3432 switch (sc->bge_asicrev) { 3433 case BGE_ASICREV_BCM5762: 3434 case BGE_ASICREV_BCM57765: 3435 case BGE_ASICREV_BCM57766: 3436 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3437 /* FALLTHROUGH */ 3438 case BGE_ASICREV_BCM5717: 3439 case BGE_ASICREV_BCM5719: 3440 case BGE_ASICREV_BCM5720: 3441 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3442 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3443 BGE_FLAG_JUMBO_FRAME; 3444 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3445 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3446 /* 3447 * Enable work around for DMA engine miscalculation 3448 * of TXMBUF available space. 3449 */ 3450 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3451 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3452 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3453 /* Jumbo frame on BCM5719 A0 does not work. */ 3454 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3455 } 3456 } 3457 break; 3458 case BGE_ASICREV_BCM5755: 3459 case BGE_ASICREV_BCM5761: 3460 case BGE_ASICREV_BCM5784: 3461 case BGE_ASICREV_BCM5785: 3462 case BGE_ASICREV_BCM5787: 3463 case BGE_ASICREV_BCM57780: 3464 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3465 BGE_FLAG_5705_PLUS; 3466 break; 3467 case BGE_ASICREV_BCM5700: 3468 case BGE_ASICREV_BCM5701: 3469 case BGE_ASICREV_BCM5703: 3470 case BGE_ASICREV_BCM5704: 3471 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3472 break; 3473 case BGE_ASICREV_BCM5714_A0: 3474 case BGE_ASICREV_BCM5780: 3475 case BGE_ASICREV_BCM5714: 3476 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3477 /* FALLTHROUGH */ 3478 case BGE_ASICREV_BCM5750: 3479 case BGE_ASICREV_BCM5752: 3480 case BGE_ASICREV_BCM5906: 3481 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3482 /* FALLTHROUGH */ 3483 case BGE_ASICREV_BCM5705: 3484 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3485 break; 3486 } 3487 3488 /* Identify chips with APE processor. */ 3489 switch (sc->bge_asicrev) { 3490 case BGE_ASICREV_BCM5717: 3491 case BGE_ASICREV_BCM5719: 3492 case BGE_ASICREV_BCM5720: 3493 case BGE_ASICREV_BCM5761: 3494 case BGE_ASICREV_BCM5762: 3495 sc->bge_flags |= BGE_FLAG_APE; 3496 break; 3497 } 3498 3499 /* Chips with APE need BAR2 access for APE registers/memory. */ 3500 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3501 rid = PCIR_BAR(2); 3502 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3503 RF_ACTIVE); 3504 if (sc->bge_res2 == NULL) { 3505 device_printf (sc->bge_dev, 3506 "couldn't map BAR2 memory\n"); 3507 error = ENXIO; 3508 goto fail; 3509 } 3510 3511 /* Enable APE register/memory access by host driver. */ 3512 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3513 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3514 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3515 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3516 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3517 3518 bge_ape_lock_init(sc); 3519 bge_ape_read_fw_ver(sc); 3520 } 3521 3522 /* Add SYSCTLs, requires the chipset family to be set. */ 3523 bge_add_sysctls(sc); 3524 3525 /* Identify the chips that use an CPMU. */ 3526 if (BGE_IS_5717_PLUS(sc) || 3527 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3528 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3529 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3530 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3531 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3532 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3533 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3534 else 3535 sc->bge_mi_mode = BGE_MIMODE_BASE; 3536 /* Enable auto polling for BCM570[0-5]. */ 3537 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3538 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3539 3540 /* 3541 * All Broadcom controllers have 4GB boundary DMA bug. 3542 * Whenever an address crosses a multiple of the 4GB boundary 3543 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3544 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3545 * state machine will lockup and cause the device to hang. 3546 */ 3547 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3548 3549 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3550 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3551 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3552 3553 /* 3554 * BCM5719 cannot handle DMA requests for DMA segments that 3555 * have larger than 4KB in size. However the maximum DMA 3556 * segment size created in DMA tag is 4KB for TSO, so we 3557 * wouldn't encounter the issue here. 3558 */ 3559 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3560 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3561 3562 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3563 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3564 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3565 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3566 sc->bge_flags |= BGE_FLAG_5788; 3567 } 3568 3569 capmask = BMSR_DEFCAPMASK; 3570 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3571 (misccfg == 0x4000 || misccfg == 0x8000)) || 3572 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3573 pci_get_vendor(dev) == BCOM_VENDORID && 3574 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3575 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3576 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3577 (pci_get_vendor(dev) == BCOM_VENDORID && 3578 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3579 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3580 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3581 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3582 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3583 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3584 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3585 /* These chips are 10/100 only. */ 3586 capmask &= ~BMSR_EXTSTAT; 3587 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3588 } 3589 3590 /* 3591 * Some controllers seem to require a special firmware to use 3592 * TSO. But the firmware is not available to FreeBSD and Linux 3593 * claims that the TSO performed by the firmware is slower than 3594 * hardware based TSO. Moreover the firmware based TSO has one 3595 * known bug which can't handle TSO if Ethernet header + IP/TCP 3596 * header is greater than 80 bytes. A workaround for the TSO 3597 * bug exist but it seems it's too expensive than not using 3598 * TSO at all. Some hardwares also have the TSO bug so limit 3599 * the TSO to the controllers that are not affected TSO issues 3600 * (e.g. 5755 or higher). 3601 */ 3602 if (BGE_IS_5717_PLUS(sc)) { 3603 /* BCM5717 requires different TSO configuration. */ 3604 sc->bge_flags |= BGE_FLAG_TSO3; 3605 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3606 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3607 /* TSO on BCM5719 A0 does not work. */ 3608 sc->bge_flags &= ~BGE_FLAG_TSO3; 3609 } 3610 } else if (BGE_IS_5755_PLUS(sc)) { 3611 /* 3612 * BCM5754 and BCM5787 shares the same ASIC id so 3613 * explicit device id check is required. 3614 * Due to unknown reason TSO does not work on BCM5755M. 3615 */ 3616 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3617 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3618 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3619 sc->bge_flags |= BGE_FLAG_TSO; 3620 } 3621 3622 /* 3623 * Check if this is a PCI-X or PCI Express device. 3624 */ 3625 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3626 /* 3627 * Found a PCI Express capabilities register, this 3628 * must be a PCI Express device. 3629 */ 3630 sc->bge_flags |= BGE_FLAG_PCIE; 3631 sc->bge_expcap = reg; 3632 /* Extract supported maximum payload size. */ 3633 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3634 PCIER_DEVICE_CAP, 2); 3635 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3636 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3637 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3638 sc->bge_expmrq = 2048; 3639 else 3640 sc->bge_expmrq = 4096; 3641 pci_set_max_read_req(dev, sc->bge_expmrq); 3642 } else { 3643 /* 3644 * Check if the device is in PCI-X Mode. 3645 * (This bit is not valid on PCI Express controllers.) 3646 */ 3647 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3648 sc->bge_pcixcap = reg; 3649 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3650 BGE_PCISTATE_PCI_BUSMODE) == 0) 3651 sc->bge_flags |= BGE_FLAG_PCIX; 3652 } 3653 3654 /* 3655 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3656 * not actually a MAC controller bug but an issue with the embedded 3657 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3658 */ 3659 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3660 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3661 /* 3662 * Some PCI-X bridges are known to trigger write reordering to 3663 * the mailbox registers. Typical phenomena is watchdog timeouts 3664 * caused by out-of-order TX completions. Enable workaround for 3665 * PCI-X devices that live behind these bridges. 3666 * Note, PCI-X controllers can run in PCI mode so we can't use 3667 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3668 */ 3669 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3670 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3671 /* 3672 * Allocate the interrupt, using MSI if possible. These devices 3673 * support 8 MSI messages, but only the first one is used in 3674 * normal operation. 3675 */ 3676 rid = 0; 3677 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3678 sc->bge_msicap = reg; 3679 reg = 1; 3680 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3681 rid = 1; 3682 sc->bge_flags |= BGE_FLAG_MSI; 3683 } 3684 } 3685 3686 /* 3687 * All controllers except BCM5700 supports tagged status but 3688 * we use tagged status only for MSI case on BCM5717. Otherwise 3689 * MSI on BCM5717 does not work. 3690 */ 3691 #ifndef DEVICE_POLLING 3692 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3693 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3694 #endif 3695 3696 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3697 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3698 3699 if (sc->bge_irq == NULL) { 3700 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3701 error = ENXIO; 3702 goto fail; 3703 } 3704 3705 bge_devinfo(sc); 3706 3707 sc->bge_asf_mode = 0; 3708 /* No ASF if APE present. */ 3709 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3710 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3711 BGE_SRAM_DATA_SIG_MAGIC)) { 3712 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3713 BGE_HWCFG_ASF) { 3714 sc->bge_asf_mode |= ASF_ENABLE; 3715 sc->bge_asf_mode |= ASF_STACKUP; 3716 if (BGE_IS_575X_PLUS(sc)) 3717 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3718 } 3719 } 3720 } 3721 3722 bge_stop_fw(sc); 3723 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3724 if (bge_reset(sc)) { 3725 device_printf(sc->bge_dev, "chip reset failed\n"); 3726 error = ENXIO; 3727 goto fail; 3728 } 3729 3730 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3731 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3732 3733 if (bge_chipinit(sc)) { 3734 device_printf(sc->bge_dev, "chip initialization failed\n"); 3735 error = ENXIO; 3736 goto fail; 3737 } 3738 3739 error = bge_get_eaddr(sc, eaddr); 3740 if (error) { 3741 device_printf(sc->bge_dev, 3742 "failed to read station address\n"); 3743 error = ENXIO; 3744 goto fail; 3745 } 3746 3747 /* 5705 limits RX return ring to 512 entries. */ 3748 if (BGE_IS_5717_PLUS(sc)) 3749 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3750 else if (BGE_IS_5705_PLUS(sc)) 3751 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3752 else 3753 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3754 3755 if (bge_dma_alloc(sc)) { 3756 device_printf(sc->bge_dev, 3757 "failed to allocate DMA resources\n"); 3758 error = ENXIO; 3759 goto fail; 3760 } 3761 3762 /* Set default tuneable values. */ 3763 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3764 sc->bge_rx_coal_ticks = 150; 3765 sc->bge_tx_coal_ticks = 150; 3766 sc->bge_rx_max_coal_bds = 10; 3767 sc->bge_tx_max_coal_bds = 10; 3768 3769 /* Initialize checksum features to use. */ 3770 sc->bge_csum_features = BGE_CSUM_FEATURES; 3771 if (sc->bge_forced_udpcsum != 0) 3772 sc->bge_csum_features |= CSUM_UDP; 3773 3774 /* Set up ifnet structure */ 3775 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3776 if (ifp == NULL) { 3777 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3778 error = ENXIO; 3779 goto fail; 3780 } 3781 if_setsoftc(ifp, sc); 3782 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3783 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3784 if_setioctlfn(ifp, bge_ioctl); 3785 if_setstartfn(ifp, bge_start); 3786 if_setinitfn(ifp, bge_init); 3787 if_setgetcounterfn(ifp, bge_get_counter); 3788 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3789 if_setsendqready(ifp); 3790 if_sethwassist(ifp, sc->bge_csum_features); 3791 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3792 IFCAP_VLAN_MTU); 3793 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3794 if_sethwassistbits(ifp, CSUM_TSO, 0); 3795 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3796 } 3797 #ifdef IFCAP_VLAN_HWCSUM 3798 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 3799 #endif 3800 if_setcapenable(ifp, if_getcapabilities(ifp)); 3801 #ifdef DEVICE_POLLING 3802 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 3803 #endif 3804 3805 /* 3806 * 5700 B0 chips do not support checksumming correctly due 3807 * to hardware bugs. 3808 */ 3809 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3810 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3811 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3812 if_sethwassist(ifp, 0); 3813 } 3814 3815 /* 3816 * Figure out what sort of media we have by checking the 3817 * hardware config word in the first 32k of NIC internal memory, 3818 * or fall back to examining the EEPROM if necessary. 3819 * Note: on some BCM5700 cards, this value appears to be unset. 3820 * If that's the case, we have to rely on identifying the NIC 3821 * by its PCI subsystem ID, as we do below for the SysKonnect 3822 * SK-9D41. 3823 */ 3824 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3825 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3826 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3827 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3828 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3829 sizeof(hwcfg))) { 3830 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3831 error = ENXIO; 3832 goto fail; 3833 } 3834 hwcfg = ntohl(hwcfg); 3835 } 3836 3837 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3838 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3839 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3840 if (BGE_IS_5705_PLUS(sc)) { 3841 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3842 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3843 } else 3844 sc->bge_flags |= BGE_FLAG_TBI; 3845 } 3846 3847 /* Set various PHY bug flags. */ 3848 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3849 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3850 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3851 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3852 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3853 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3854 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3855 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3856 if (pci_get_subvendor(dev) == DELL_VENDORID) 3857 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3858 if ((BGE_IS_5705_PLUS(sc)) && 3859 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3860 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3861 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3862 !BGE_IS_5717_PLUS(sc)) { 3863 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3864 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3865 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3866 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3867 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3868 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3869 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3870 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3871 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3872 } else 3873 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3874 } 3875 3876 /* 3877 * Don't enable Ethernet@WireSpeed for the 5700 or the 3878 * 5705 A0 and A1 chips. 3879 */ 3880 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3881 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3882 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3883 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3884 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3885 3886 if (sc->bge_flags & BGE_FLAG_TBI) { 3887 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3888 bge_ifmedia_sts); 3889 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3890 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3891 0, NULL); 3892 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3893 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3894 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3895 } else { 3896 /* 3897 * Do transceiver setup and tell the firmware the 3898 * driver is down so we can try to get access the 3899 * probe if ASF is running. Retry a couple of times 3900 * if we get a conflict with the ASF firmware accessing 3901 * the PHY. 3902 */ 3903 trys = 0; 3904 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3905 again: 3906 bge_asf_driver_up(sc); 3907 3908 error = mii_attach(dev, &sc->bge_miibus, ifp, 3909 (ifm_change_cb_t)bge_ifmedia_upd, 3910 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3911 MII_OFFSET_ANY, MIIF_DOPAUSE); 3912 if (error != 0) { 3913 if (trys++ < 4) { 3914 device_printf(sc->bge_dev, "Try again\n"); 3915 bge_miibus_writereg(sc->bge_dev, 3916 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3917 goto again; 3918 } 3919 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3920 goto fail; 3921 } 3922 3923 /* 3924 * Now tell the firmware we are going up after probing the PHY 3925 */ 3926 if (sc->bge_asf_mode & ASF_STACKUP) 3927 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3928 } 3929 3930 /* 3931 * When using the BCM5701 in PCI-X mode, data corruption has 3932 * been observed in the first few bytes of some received packets. 3933 * Aligning the packet buffer in memory eliminates the corruption. 3934 * Unfortunately, this misaligns the packet payloads. On platforms 3935 * which do not support unaligned accesses, we will realign the 3936 * payloads by copying the received packets. 3937 */ 3938 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3939 sc->bge_flags & BGE_FLAG_PCIX) 3940 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3941 3942 /* 3943 * Call MI attach routine. 3944 */ 3945 ether_ifattach(ifp, eaddr); 3946 3947 /* Tell upper layer we support long frames. */ 3948 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 3949 3950 /* 3951 * Hookup IRQ last. 3952 */ 3953 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3954 /* Take advantage of single-shot MSI. */ 3955 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3956 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3957 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3958 taskqueue_thread_enqueue, &sc->bge_tq); 3959 if (sc->bge_tq == NULL) { 3960 device_printf(dev, "could not create taskqueue.\n"); 3961 ether_ifdetach(ifp); 3962 error = ENOMEM; 3963 goto fail; 3964 } 3965 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3966 "%s taskq", device_get_nameunit(sc->bge_dev)); 3967 if (error != 0) { 3968 device_printf(dev, "could not start threads.\n"); 3969 ether_ifdetach(ifp); 3970 goto fail; 3971 } 3972 error = bus_setup_intr(dev, sc->bge_irq, 3973 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3974 &sc->bge_intrhand); 3975 } else 3976 error = bus_setup_intr(dev, sc->bge_irq, 3977 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3978 &sc->bge_intrhand); 3979 3980 if (error) { 3981 ether_ifdetach(ifp); 3982 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3983 goto fail; 3984 } 3985 3986 /* Attach driver netdump methods. */ 3987 NETDUMP_SET(ifp, bge); 3988 3989 fail: 3990 if (error) 3991 bge_detach(dev); 3992 return (error); 3993 } 3994 3995 static int 3996 bge_detach(device_t dev) 3997 { 3998 struct bge_softc *sc; 3999 if_t ifp; 4000 4001 sc = device_get_softc(dev); 4002 ifp = sc->bge_ifp; 4003 4004 #ifdef DEVICE_POLLING 4005 if (if_getcapenable(ifp) & IFCAP_POLLING) 4006 ether_poll_deregister(ifp); 4007 #endif 4008 4009 if (device_is_attached(dev)) { 4010 ether_ifdetach(ifp); 4011 BGE_LOCK(sc); 4012 bge_stop(sc); 4013 BGE_UNLOCK(sc); 4014 callout_drain(&sc->bge_stat_ch); 4015 } 4016 4017 if (sc->bge_tq) 4018 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 4019 4020 if (sc->bge_flags & BGE_FLAG_TBI) 4021 ifmedia_removeall(&sc->bge_ifmedia); 4022 else if (sc->bge_miibus != NULL) { 4023 bus_generic_detach(dev); 4024 device_delete_child(dev, sc->bge_miibus); 4025 } 4026 4027 bge_release_resources(sc); 4028 4029 return (0); 4030 } 4031 4032 static void 4033 bge_release_resources(struct bge_softc *sc) 4034 { 4035 device_t dev; 4036 4037 dev = sc->bge_dev; 4038 4039 if (sc->bge_tq != NULL) 4040 taskqueue_free(sc->bge_tq); 4041 4042 if (sc->bge_intrhand != NULL) 4043 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 4044 4045 if (sc->bge_irq != NULL) { 4046 bus_release_resource(dev, SYS_RES_IRQ, 4047 rman_get_rid(sc->bge_irq), sc->bge_irq); 4048 pci_release_msi(dev); 4049 } 4050 4051 if (sc->bge_res != NULL) 4052 bus_release_resource(dev, SYS_RES_MEMORY, 4053 rman_get_rid(sc->bge_res), sc->bge_res); 4054 4055 if (sc->bge_res2 != NULL) 4056 bus_release_resource(dev, SYS_RES_MEMORY, 4057 rman_get_rid(sc->bge_res2), sc->bge_res2); 4058 4059 if (sc->bge_ifp != NULL) 4060 if_free(sc->bge_ifp); 4061 4062 bge_dma_free(sc); 4063 4064 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4065 BGE_LOCK_DESTROY(sc); 4066 } 4067 4068 static int 4069 bge_reset(struct bge_softc *sc) 4070 { 4071 device_t dev; 4072 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4073 void (*write_op)(struct bge_softc *, int, int); 4074 uint16_t devctl; 4075 int i; 4076 4077 dev = sc->bge_dev; 4078 4079 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4080 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4081 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4082 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4083 4084 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4085 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4086 if (sc->bge_flags & BGE_FLAG_PCIE) 4087 write_op = bge_writemem_direct; 4088 else 4089 write_op = bge_writemem_ind; 4090 } else 4091 write_op = bge_writereg_ind; 4092 4093 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4094 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4095 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4096 for (i = 0; i < 8000; i++) { 4097 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4098 BGE_NVRAMSWARB_GNT1) 4099 break; 4100 DELAY(20); 4101 } 4102 if (i == 8000) { 4103 if (bootverbose) 4104 device_printf(dev, "NVRAM lock timedout!\n"); 4105 } 4106 } 4107 /* Take APE lock when performing reset. */ 4108 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4109 4110 /* Save some important PCI state. */ 4111 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4112 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4113 4114 pci_write_config(dev, BGE_PCI_MISC_CTL, 4115 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4116 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4117 4118 /* Disable fastboot on controllers that support it. */ 4119 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4120 BGE_IS_5755_PLUS(sc)) { 4121 if (bootverbose) 4122 device_printf(dev, "Disabling fastboot\n"); 4123 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4124 } 4125 4126 /* 4127 * Write the magic number to SRAM at offset 0xB50. 4128 * When firmware finishes its initialization it will 4129 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4130 */ 4131 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4132 4133 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4134 4135 /* XXX: Broadcom Linux driver. */ 4136 if (sc->bge_flags & BGE_FLAG_PCIE) { 4137 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4138 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4139 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4140 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4141 } 4142 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4143 /* Prevent PCIE link training during global reset */ 4144 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4145 reset |= 1 << 29; 4146 } 4147 } 4148 4149 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4150 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4151 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4152 val | BGE_VCPU_STATUS_DRV_RESET); 4153 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4154 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4155 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4156 } 4157 4158 /* 4159 * Set GPHY Power Down Override to leave GPHY 4160 * powered up in D0 uninitialized. 4161 */ 4162 if (BGE_IS_5705_PLUS(sc) && 4163 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4164 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4165 4166 /* Issue global reset */ 4167 write_op(sc, BGE_MISC_CFG, reset); 4168 4169 if (sc->bge_flags & BGE_FLAG_PCIE) 4170 DELAY(100 * 1000); 4171 else 4172 DELAY(1000); 4173 4174 /* XXX: Broadcom Linux driver. */ 4175 if (sc->bge_flags & BGE_FLAG_PCIE) { 4176 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4177 DELAY(500000); /* wait for link training to complete */ 4178 val = pci_read_config(dev, 0xC4, 4); 4179 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4180 } 4181 devctl = pci_read_config(dev, 4182 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4183 /* Clear enable no snoop and disable relaxed ordering. */ 4184 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4185 PCIEM_CTL_NOSNOOP_ENABLE); 4186 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4187 devctl, 2); 4188 pci_set_max_read_req(dev, sc->bge_expmrq); 4189 /* Clear error status. */ 4190 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4191 PCIEM_STA_CORRECTABLE_ERROR | 4192 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4193 PCIEM_STA_UNSUPPORTED_REQ, 2); 4194 } 4195 4196 /* Reset some of the PCI state that got zapped by reset. */ 4197 pci_write_config(dev, BGE_PCI_MISC_CTL, 4198 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4199 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4200 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4201 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4202 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4203 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4204 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4205 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4206 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4207 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4208 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4209 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4210 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4211 /* 4212 * Disable PCI-X relaxed ordering to ensure status block update 4213 * comes first then packet buffer DMA. Otherwise driver may 4214 * read stale status block. 4215 */ 4216 if (sc->bge_flags & BGE_FLAG_PCIX) { 4217 devctl = pci_read_config(dev, 4218 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4219 devctl &= ~PCIXM_COMMAND_ERO; 4220 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4221 devctl &= ~PCIXM_COMMAND_MAX_READ; 4222 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4223 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4224 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4225 PCIXM_COMMAND_MAX_READ); 4226 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4227 } 4228 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4229 devctl, 2); 4230 } 4231 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4232 if (BGE_IS_5714_FAMILY(sc)) { 4233 /* This chip disables MSI on reset. */ 4234 if (sc->bge_flags & BGE_FLAG_MSI) { 4235 val = pci_read_config(dev, 4236 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4237 pci_write_config(dev, 4238 sc->bge_msicap + PCIR_MSI_CTRL, 4239 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4240 val = CSR_READ_4(sc, BGE_MSI_MODE); 4241 CSR_WRITE_4(sc, BGE_MSI_MODE, 4242 val | BGE_MSIMODE_ENABLE); 4243 } 4244 val = CSR_READ_4(sc, BGE_MARB_MODE); 4245 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4246 } else 4247 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4248 4249 /* Fix up byte swapping. */ 4250 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4251 4252 val = CSR_READ_4(sc, BGE_MAC_MODE); 4253 val = (val & ~mac_mode_mask) | mac_mode; 4254 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4255 DELAY(40); 4256 4257 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4258 4259 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4260 for (i = 0; i < BGE_TIMEOUT; i++) { 4261 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4262 if (val & BGE_VCPU_STATUS_INIT_DONE) 4263 break; 4264 DELAY(100); 4265 } 4266 if (i == BGE_TIMEOUT) { 4267 device_printf(dev, "reset timed out\n"); 4268 return (1); 4269 } 4270 } else { 4271 /* 4272 * Poll until we see the 1's complement of the magic number. 4273 * This indicates that the firmware initialization is complete. 4274 * We expect this to fail if no chip containing the Ethernet 4275 * address is fitted though. 4276 */ 4277 for (i = 0; i < BGE_TIMEOUT; i++) { 4278 DELAY(10); 4279 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4280 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4281 break; 4282 } 4283 4284 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4285 device_printf(dev, 4286 "firmware handshake timed out, found 0x%08x\n", 4287 val); 4288 /* BCM57765 A0 needs additional time before accessing. */ 4289 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4290 DELAY(10 * 1000); /* XXX */ 4291 } 4292 4293 /* 4294 * The 5704 in TBI mode apparently needs some special 4295 * adjustment to insure the SERDES drive level is set 4296 * to 1.2V. 4297 */ 4298 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4299 sc->bge_flags & BGE_FLAG_TBI) { 4300 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4301 val = (val & ~0xFFF) | 0x880; 4302 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4303 } 4304 4305 /* XXX: Broadcom Linux driver. */ 4306 if (sc->bge_flags & BGE_FLAG_PCIE && 4307 !BGE_IS_5717_PLUS(sc) && 4308 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4309 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4310 /* Enable Data FIFO protection. */ 4311 val = CSR_READ_4(sc, 0x7C00); 4312 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4313 } 4314 4315 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4316 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4317 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4318 4319 return (0); 4320 } 4321 4322 static __inline void 4323 bge_rxreuse_std(struct bge_softc *sc, int i) 4324 { 4325 struct bge_rx_bd *r; 4326 4327 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4328 r->bge_flags = BGE_RXBDFLAG_END; 4329 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4330 r->bge_idx = i; 4331 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4332 } 4333 4334 static __inline void 4335 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4336 { 4337 struct bge_extrx_bd *r; 4338 4339 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4340 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4341 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4342 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4343 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4344 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4345 r->bge_idx = i; 4346 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4347 } 4348 4349 /* 4350 * Frame reception handling. This is called if there's a frame 4351 * on the receive return list. 4352 * 4353 * Note: we have to be able to handle two possibilities here: 4354 * 1) the frame is from the jumbo receive ring 4355 * 2) the frame is from the standard receive ring 4356 */ 4357 4358 static int 4359 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4360 { 4361 if_t ifp; 4362 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4363 uint16_t rx_cons; 4364 4365 rx_cons = sc->bge_rx_saved_considx; 4366 4367 /* Nothing to do. */ 4368 if (rx_cons == rx_prod) 4369 return (rx_npkts); 4370 4371 ifp = sc->bge_ifp; 4372 4373 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4374 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4375 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4376 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4377 if (BGE_IS_JUMBO_CAPABLE(sc) && 4378 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4379 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4380 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4381 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4382 4383 while (rx_cons != rx_prod) { 4384 struct bge_rx_bd *cur_rx; 4385 uint32_t rxidx; 4386 struct mbuf *m = NULL; 4387 uint16_t vlan_tag = 0; 4388 int have_tag = 0; 4389 4390 #ifdef DEVICE_POLLING 4391 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4392 if (sc->rxcycles <= 0) 4393 break; 4394 sc->rxcycles--; 4395 } 4396 #endif 4397 4398 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4399 4400 rxidx = cur_rx->bge_idx; 4401 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4402 4403 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4404 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4405 have_tag = 1; 4406 vlan_tag = cur_rx->bge_vlan_tag; 4407 } 4408 4409 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4410 jumbocnt++; 4411 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4412 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4413 bge_rxreuse_jumbo(sc, rxidx); 4414 continue; 4415 } 4416 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4417 bge_rxreuse_jumbo(sc, rxidx); 4418 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4419 continue; 4420 } 4421 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4422 } else { 4423 stdcnt++; 4424 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4425 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4426 bge_rxreuse_std(sc, rxidx); 4427 continue; 4428 } 4429 if (bge_newbuf_std(sc, rxidx) != 0) { 4430 bge_rxreuse_std(sc, rxidx); 4431 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4432 continue; 4433 } 4434 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4435 } 4436 4437 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 4438 #ifndef __NO_STRICT_ALIGNMENT 4439 /* 4440 * For architectures with strict alignment we must make sure 4441 * the payload is aligned. 4442 */ 4443 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4444 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4445 cur_rx->bge_len); 4446 m->m_data += ETHER_ALIGN; 4447 } 4448 #endif 4449 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4450 m->m_pkthdr.rcvif = ifp; 4451 4452 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 4453 bge_rxcsum(sc, cur_rx, m); 4454 4455 /* 4456 * If we received a packet with a vlan tag, 4457 * attach that information to the packet. 4458 */ 4459 if (have_tag) { 4460 m->m_pkthdr.ether_vtag = vlan_tag; 4461 m->m_flags |= M_VLANTAG; 4462 } 4463 4464 if (holdlck != 0) { 4465 BGE_UNLOCK(sc); 4466 if_input(ifp, m); 4467 BGE_LOCK(sc); 4468 } else 4469 if_input(ifp, m); 4470 rx_npkts++; 4471 4472 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4473 return (rx_npkts); 4474 } 4475 4476 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4477 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4478 if (stdcnt > 0) 4479 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4480 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4481 4482 if (jumbocnt > 0) 4483 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4484 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4485 4486 sc->bge_rx_saved_considx = rx_cons; 4487 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4488 if (stdcnt) 4489 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4490 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4491 if (jumbocnt) 4492 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4493 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4494 #ifdef notyet 4495 /* 4496 * This register wraps very quickly under heavy packet drops. 4497 * If you need correct statistics, you can enable this check. 4498 */ 4499 if (BGE_IS_5705_PLUS(sc)) 4500 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4501 #endif 4502 return (rx_npkts); 4503 } 4504 4505 static void 4506 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4507 { 4508 4509 if (BGE_IS_5717_PLUS(sc)) { 4510 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4511 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4512 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4513 if ((cur_rx->bge_error_flag & 4514 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4515 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4516 } 4517 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4518 m->m_pkthdr.csum_data = 4519 cur_rx->bge_tcp_udp_csum; 4520 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4521 CSUM_PSEUDO_HDR; 4522 } 4523 } 4524 } else { 4525 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4526 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4527 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4528 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4529 } 4530 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4531 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4532 m->m_pkthdr.csum_data = 4533 cur_rx->bge_tcp_udp_csum; 4534 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4535 CSUM_PSEUDO_HDR; 4536 } 4537 } 4538 } 4539 4540 static void 4541 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4542 { 4543 struct bge_tx_bd *cur_tx; 4544 if_t ifp; 4545 4546 BGE_LOCK_ASSERT(sc); 4547 4548 /* Nothing to do. */ 4549 if (sc->bge_tx_saved_considx == tx_cons) 4550 return; 4551 4552 ifp = sc->bge_ifp; 4553 4554 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4555 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4556 /* 4557 * Go through our tx ring and free mbufs for those 4558 * frames that have been sent. 4559 */ 4560 while (sc->bge_tx_saved_considx != tx_cons) { 4561 uint32_t idx; 4562 4563 idx = sc->bge_tx_saved_considx; 4564 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4565 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4566 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 4567 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4568 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4569 sc->bge_cdata.bge_tx_dmamap[idx], 4570 BUS_DMASYNC_POSTWRITE); 4571 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4572 sc->bge_cdata.bge_tx_dmamap[idx]); 4573 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4574 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4575 } 4576 sc->bge_txcnt--; 4577 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4578 } 4579 4580 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4581 if (sc->bge_txcnt == 0) 4582 sc->bge_timer = 0; 4583 } 4584 4585 #ifdef DEVICE_POLLING 4586 static int 4587 bge_poll(if_t ifp, enum poll_cmd cmd, int count) 4588 { 4589 struct bge_softc *sc = if_getsoftc(ifp); 4590 uint16_t rx_prod, tx_cons; 4591 uint32_t statusword; 4592 int rx_npkts = 0; 4593 4594 BGE_LOCK(sc); 4595 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4596 BGE_UNLOCK(sc); 4597 return (rx_npkts); 4598 } 4599 4600 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4601 sc->bge_cdata.bge_status_map, 4602 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4603 /* Fetch updates from the status block. */ 4604 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4605 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4606 4607 statusword = sc->bge_ldata.bge_status_block->bge_status; 4608 /* Clear the status so the next pass only sees the changes. */ 4609 sc->bge_ldata.bge_status_block->bge_status = 0; 4610 4611 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4612 sc->bge_cdata.bge_status_map, 4613 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4614 4615 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4616 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4617 sc->bge_link_evt++; 4618 4619 if (cmd == POLL_AND_CHECK_STATUS) 4620 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4621 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4622 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4623 bge_link_upd(sc); 4624 4625 sc->rxcycles = count; 4626 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4627 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4628 BGE_UNLOCK(sc); 4629 return (rx_npkts); 4630 } 4631 bge_txeof(sc, tx_cons); 4632 if (!if_sendq_empty(ifp)) 4633 bge_start_locked(ifp); 4634 4635 BGE_UNLOCK(sc); 4636 return (rx_npkts); 4637 } 4638 #endif /* DEVICE_POLLING */ 4639 4640 static int 4641 bge_msi_intr(void *arg) 4642 { 4643 struct bge_softc *sc; 4644 4645 sc = (struct bge_softc *)arg; 4646 /* 4647 * This interrupt is not shared and controller already 4648 * disabled further interrupt. 4649 */ 4650 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4651 return (FILTER_HANDLED); 4652 } 4653 4654 static void 4655 bge_intr_task(void *arg, int pending) 4656 { 4657 struct bge_softc *sc; 4658 if_t ifp; 4659 uint32_t status, status_tag; 4660 uint16_t rx_prod, tx_cons; 4661 4662 sc = (struct bge_softc *)arg; 4663 ifp = sc->bge_ifp; 4664 4665 BGE_LOCK(sc); 4666 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 4667 BGE_UNLOCK(sc); 4668 return; 4669 } 4670 4671 /* Get updated status block. */ 4672 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4673 sc->bge_cdata.bge_status_map, 4674 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4675 4676 /* Save producer/consumer indices. */ 4677 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4678 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4679 status = sc->bge_ldata.bge_status_block->bge_status; 4680 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4681 /* Dirty the status flag. */ 4682 sc->bge_ldata.bge_status_block->bge_status = 0; 4683 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4684 sc->bge_cdata.bge_status_map, 4685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4686 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4687 status_tag = 0; 4688 4689 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4690 bge_link_upd(sc); 4691 4692 /* Let controller work. */ 4693 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4694 4695 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4696 sc->bge_rx_saved_considx != rx_prod) { 4697 /* Check RX return ring producer/consumer. */ 4698 BGE_UNLOCK(sc); 4699 bge_rxeof(sc, rx_prod, 0); 4700 BGE_LOCK(sc); 4701 } 4702 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4703 /* Check TX ring producer/consumer. */ 4704 bge_txeof(sc, tx_cons); 4705 if (!if_sendq_empty(ifp)) 4706 bge_start_locked(ifp); 4707 } 4708 BGE_UNLOCK(sc); 4709 } 4710 4711 static void 4712 bge_intr(void *xsc) 4713 { 4714 struct bge_softc *sc; 4715 if_t ifp; 4716 uint32_t statusword; 4717 uint16_t rx_prod, tx_cons; 4718 4719 sc = xsc; 4720 4721 BGE_LOCK(sc); 4722 4723 ifp = sc->bge_ifp; 4724 4725 #ifdef DEVICE_POLLING 4726 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4727 BGE_UNLOCK(sc); 4728 return; 4729 } 4730 #endif 4731 4732 /* 4733 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4734 * disable interrupts by writing nonzero like we used to, since with 4735 * our current organization this just gives complications and 4736 * pessimizations for re-enabling interrupts. We used to have races 4737 * instead of the necessary complications. Disabling interrupts 4738 * would just reduce the chance of a status update while we are 4739 * running (by switching to the interrupt-mode coalescence 4740 * parameters), but this chance is already very low so it is more 4741 * efficient to get another interrupt than prevent it. 4742 * 4743 * We do the ack first to ensure another interrupt if there is a 4744 * status update after the ack. We don't check for the status 4745 * changing later because it is more efficient to get another 4746 * interrupt than prevent it, not quite as above (not checking is 4747 * a smaller optimization than not toggling the interrupt enable, 4748 * since checking doesn't involve PCI accesses and toggling require 4749 * the status check). So toggling would probably be a pessimization 4750 * even with MSI. It would only be needed for using a task queue. 4751 */ 4752 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4753 4754 /* 4755 * Do the mandatory PCI flush as well as get the link status. 4756 */ 4757 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4758 4759 /* Make sure the descriptor ring indexes are coherent. */ 4760 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4761 sc->bge_cdata.bge_status_map, 4762 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4763 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4764 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4765 sc->bge_ldata.bge_status_block->bge_status = 0; 4766 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4767 sc->bge_cdata.bge_status_map, 4768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4769 4770 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4771 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4772 statusword || sc->bge_link_evt) 4773 bge_link_upd(sc); 4774 4775 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4776 /* Check RX return ring producer/consumer. */ 4777 bge_rxeof(sc, rx_prod, 1); 4778 } 4779 4780 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4781 /* Check TX ring producer/consumer. */ 4782 bge_txeof(sc, tx_cons); 4783 } 4784 4785 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4786 !if_sendq_empty(ifp)) 4787 bge_start_locked(ifp); 4788 4789 BGE_UNLOCK(sc); 4790 } 4791 4792 static void 4793 bge_asf_driver_up(struct bge_softc *sc) 4794 { 4795 if (sc->bge_asf_mode & ASF_STACKUP) { 4796 /* Send ASF heartbeat aprox. every 2s */ 4797 if (sc->bge_asf_count) 4798 sc->bge_asf_count --; 4799 else { 4800 sc->bge_asf_count = 2; 4801 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4802 BGE_FW_CMD_DRV_ALIVE); 4803 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4804 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4805 BGE_FW_HB_TIMEOUT_SEC); 4806 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4807 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4808 BGE_RX_CPU_DRV_EVENT); 4809 } 4810 } 4811 } 4812 4813 static void 4814 bge_tick(void *xsc) 4815 { 4816 struct bge_softc *sc = xsc; 4817 struct mii_data *mii = NULL; 4818 4819 BGE_LOCK_ASSERT(sc); 4820 4821 /* Synchronize with possible callout reset/stop. */ 4822 if (callout_pending(&sc->bge_stat_ch) || 4823 !callout_active(&sc->bge_stat_ch)) 4824 return; 4825 4826 if (BGE_IS_5705_PLUS(sc)) 4827 bge_stats_update_regs(sc); 4828 else 4829 bge_stats_update(sc); 4830 4831 /* XXX Add APE heartbeat check here? */ 4832 4833 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4834 mii = device_get_softc(sc->bge_miibus); 4835 /* 4836 * Do not touch PHY if we have link up. This could break 4837 * IPMI/ASF mode or produce extra input errors 4838 * (extra errors was reported for bcm5701 & bcm5704). 4839 */ 4840 if (!sc->bge_link) 4841 mii_tick(mii); 4842 } else { 4843 /* 4844 * Since in TBI mode auto-polling can't be used we should poll 4845 * link status manually. Here we register pending link event 4846 * and trigger interrupt. 4847 */ 4848 #ifdef DEVICE_POLLING 4849 /* In polling mode we poll link state in bge_poll(). */ 4850 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 4851 #endif 4852 { 4853 sc->bge_link_evt++; 4854 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4855 sc->bge_flags & BGE_FLAG_5788) 4856 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4857 else 4858 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4859 } 4860 } 4861 4862 bge_asf_driver_up(sc); 4863 bge_watchdog(sc); 4864 4865 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4866 } 4867 4868 static void 4869 bge_stats_update_regs(struct bge_softc *sc) 4870 { 4871 if_t ifp; 4872 struct bge_mac_stats *stats; 4873 uint32_t val; 4874 4875 ifp = sc->bge_ifp; 4876 stats = &sc->bge_mac_stats; 4877 4878 stats->ifHCOutOctets += 4879 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4880 stats->etherStatsCollisions += 4881 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4882 stats->outXonSent += 4883 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4884 stats->outXoffSent += 4885 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4886 stats->dot3StatsInternalMacTransmitErrors += 4887 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4888 stats->dot3StatsSingleCollisionFrames += 4889 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4890 stats->dot3StatsMultipleCollisionFrames += 4891 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4892 stats->dot3StatsDeferredTransmissions += 4893 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4894 stats->dot3StatsExcessiveCollisions += 4895 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4896 stats->dot3StatsLateCollisions += 4897 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4898 stats->ifHCOutUcastPkts += 4899 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4900 stats->ifHCOutMulticastPkts += 4901 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4902 stats->ifHCOutBroadcastPkts += 4903 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4904 4905 stats->ifHCInOctets += 4906 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4907 stats->etherStatsFragments += 4908 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4909 stats->ifHCInUcastPkts += 4910 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4911 stats->ifHCInMulticastPkts += 4912 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4913 stats->ifHCInBroadcastPkts += 4914 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4915 stats->dot3StatsFCSErrors += 4916 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4917 stats->dot3StatsAlignmentErrors += 4918 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4919 stats->xonPauseFramesReceived += 4920 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4921 stats->xoffPauseFramesReceived += 4922 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4923 stats->macControlFramesReceived += 4924 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4925 stats->xoffStateEntered += 4926 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4927 stats->dot3StatsFramesTooLong += 4928 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4929 stats->etherStatsJabbers += 4930 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4931 stats->etherStatsUndersizePkts += 4932 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4933 4934 stats->FramesDroppedDueToFilters += 4935 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4936 stats->DmaWriteQueueFull += 4937 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4938 stats->DmaWriteHighPriQueueFull += 4939 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4940 stats->NoMoreRxBDs += 4941 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4942 /* 4943 * XXX 4944 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4945 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4946 * includes number of unwanted multicast frames. This comes 4947 * from silicon bug and known workaround to get rough(not 4948 * exact) counter is to enable interrupt on MBUF low water 4949 * attention. This can be accomplished by setting 4950 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4951 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4952 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4953 * However that change would generate more interrupts and 4954 * there are still possibilities of losing multiple frames 4955 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4956 * Given that the workaround still would not get correct 4957 * counter I don't think it's worth to implement it. So 4958 * ignore reading the counter on controllers that have the 4959 * silicon bug. 4960 */ 4961 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4962 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4963 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4964 stats->InputDiscards += 4965 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4966 stats->InputErrors += 4967 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4968 stats->RecvThresholdHit += 4969 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4970 4971 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4972 /* 4973 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4974 * frames, it's safe to disable workaround for DMA engine's 4975 * miscalculation of TXMBUF space. 4976 */ 4977 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4978 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4979 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4980 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4981 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4982 else 4983 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4984 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4985 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4986 } 4987 } 4988 } 4989 4990 static void 4991 bge_stats_clear_regs(struct bge_softc *sc) 4992 { 4993 4994 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4995 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4996 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4997 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4998 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4999 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 5000 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 5001 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 5002 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 5003 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 5004 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 5005 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 5006 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 5007 5008 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 5009 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 5010 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 5011 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 5012 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 5013 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 5014 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 5015 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 5016 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 5017 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 5018 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 5019 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 5020 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 5021 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 5022 5023 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 5024 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 5025 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 5026 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 5027 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 5028 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 5029 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 5030 } 5031 5032 static void 5033 bge_stats_update(struct bge_softc *sc) 5034 { 5035 if_t ifp; 5036 bus_size_t stats; 5037 uint32_t cnt; /* current register value */ 5038 5039 ifp = sc->bge_ifp; 5040 5041 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 5042 5043 #define READ_STAT(sc, stats, stat) \ 5044 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 5045 5046 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 5047 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions); 5048 sc->bge_tx_collisions = cnt; 5049 5050 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 5051 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds); 5052 sc->bge_rx_nobds = cnt; 5053 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5054 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs); 5055 sc->bge_rx_inerrs = cnt; 5056 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5057 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards); 5058 sc->bge_rx_discards = cnt; 5059 5060 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5061 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards); 5062 sc->bge_tx_discards = cnt; 5063 5064 #undef READ_STAT 5065 } 5066 5067 /* 5068 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5069 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5070 * but when such padded frames employ the bge IP/TCP checksum offload, 5071 * the hardware checksum assist gives incorrect results (possibly 5072 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5073 * If we pad such runts with zeros, the onboard checksum comes out correct. 5074 */ 5075 static __inline int 5076 bge_cksum_pad(struct mbuf *m) 5077 { 5078 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5079 struct mbuf *last; 5080 5081 /* If there's only the packet-header and we can pad there, use it. */ 5082 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5083 M_TRAILINGSPACE(m) >= padlen) { 5084 last = m; 5085 } else { 5086 /* 5087 * Walk packet chain to find last mbuf. We will either 5088 * pad there, or append a new mbuf and pad it. 5089 */ 5090 for (last = m; last->m_next != NULL; last = last->m_next); 5091 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5092 /* Allocate new empty mbuf, pad it. Compact later. */ 5093 struct mbuf *n; 5094 5095 MGET(n, M_NOWAIT, MT_DATA); 5096 if (n == NULL) 5097 return (ENOBUFS); 5098 n->m_len = 0; 5099 last->m_next = n; 5100 last = n; 5101 } 5102 } 5103 5104 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5105 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5106 last->m_len += padlen; 5107 m->m_pkthdr.len += padlen; 5108 5109 return (0); 5110 } 5111 5112 static struct mbuf * 5113 bge_check_short_dma(struct mbuf *m) 5114 { 5115 struct mbuf *n; 5116 int found; 5117 5118 /* 5119 * If device receive two back-to-back send BDs with less than 5120 * or equal to 8 total bytes then the device may hang. The two 5121 * back-to-back send BDs must in the same frame for this failure 5122 * to occur. Scan mbuf chains and see whether two back-to-back 5123 * send BDs are there. If this is the case, allocate new mbuf 5124 * and copy the frame to workaround the silicon bug. 5125 */ 5126 for (n = m, found = 0; n != NULL; n = n->m_next) { 5127 if (n->m_len < 8) { 5128 found++; 5129 if (found > 1) 5130 break; 5131 continue; 5132 } 5133 found = 0; 5134 } 5135 5136 if (found > 1) { 5137 n = m_defrag(m, M_NOWAIT); 5138 if (n == NULL) 5139 m_freem(m); 5140 } else 5141 n = m; 5142 return (n); 5143 } 5144 5145 static struct mbuf * 5146 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5147 uint16_t *flags) 5148 { 5149 struct ip *ip; 5150 struct tcphdr *tcp; 5151 struct mbuf *n; 5152 uint16_t hlen; 5153 uint32_t poff; 5154 5155 if (M_WRITABLE(m) == 0) { 5156 /* Get a writable copy. */ 5157 n = m_dup(m, M_NOWAIT); 5158 m_freem(m); 5159 if (n == NULL) 5160 return (NULL); 5161 m = n; 5162 } 5163 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5164 if (m == NULL) 5165 return (NULL); 5166 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5167 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5168 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5169 if (m == NULL) 5170 return (NULL); 5171 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5172 m = m_pullup(m, poff + (tcp->th_off << 2)); 5173 if (m == NULL) 5174 return (NULL); 5175 /* 5176 * It seems controller doesn't modify IP length and TCP pseudo 5177 * checksum. These checksum computed by upper stack should be 0. 5178 */ 5179 *mss = m->m_pkthdr.tso_segsz; 5180 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5181 ip->ip_sum = 0; 5182 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5183 /* Clear pseudo checksum computed by TCP stack. */ 5184 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5185 tcp->th_sum = 0; 5186 /* 5187 * Broadcom controllers uses different descriptor format for 5188 * TSO depending on ASIC revision. Due to TSO-capable firmware 5189 * license issue and lower performance of firmware based TSO 5190 * we only support hardware based TSO. 5191 */ 5192 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5193 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5194 if (sc->bge_flags & BGE_FLAG_TSO3) { 5195 /* 5196 * For BCM5717 and newer controllers, hardware based TSO 5197 * uses the 14 lower bits of the bge_mss field to store the 5198 * MSS and the upper 2 bits to store the lowest 2 bits of 5199 * the IP/TCP header length. The upper 6 bits of the header 5200 * length are stored in the bge_flags[14:10,4] field. Jumbo 5201 * frames are supported. 5202 */ 5203 *mss |= ((hlen & 0x3) << 14); 5204 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5205 } else { 5206 /* 5207 * For BCM5755 and newer controllers, hardware based TSO uses 5208 * the lower 11 bits to store the MSS and the upper 5 bits to 5209 * store the IP/TCP header length. Jumbo frames are not 5210 * supported. 5211 */ 5212 *mss |= (hlen << 11); 5213 } 5214 return (m); 5215 } 5216 5217 /* 5218 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5219 * pointers to descriptors. 5220 */ 5221 static int 5222 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5223 { 5224 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5225 bus_dmamap_t map; 5226 struct bge_tx_bd *d; 5227 struct mbuf *m = *m_head; 5228 uint32_t idx = *txidx; 5229 uint16_t csum_flags, mss, vlan_tag; 5230 int nsegs, i, error; 5231 5232 csum_flags = 0; 5233 mss = 0; 5234 vlan_tag = 0; 5235 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5236 m->m_next != NULL) { 5237 *m_head = bge_check_short_dma(m); 5238 if (*m_head == NULL) 5239 return (ENOBUFS); 5240 m = *m_head; 5241 } 5242 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5243 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5244 if (*m_head == NULL) 5245 return (ENOBUFS); 5246 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5247 BGE_TXBDFLAG_CPU_POST_DMA; 5248 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5249 if (m->m_pkthdr.csum_flags & CSUM_IP) 5250 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5251 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5252 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5253 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5254 (error = bge_cksum_pad(m)) != 0) { 5255 m_freem(m); 5256 *m_head = NULL; 5257 return (error); 5258 } 5259 } 5260 } 5261 5262 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5263 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5264 m->m_pkthdr.len > ETHER_MAX_LEN) 5265 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5266 if (sc->bge_forced_collapse > 0 && 5267 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5268 /* 5269 * Forcedly collapse mbuf chains to overcome hardware 5270 * limitation which only support a single outstanding 5271 * DMA read operation. 5272 */ 5273 if (sc->bge_forced_collapse == 1) 5274 m = m_defrag(m, M_NOWAIT); 5275 else 5276 m = m_collapse(m, M_NOWAIT, 5277 sc->bge_forced_collapse); 5278 if (m == NULL) 5279 m = *m_head; 5280 *m_head = m; 5281 } 5282 } 5283 5284 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5285 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5286 &nsegs, BUS_DMA_NOWAIT); 5287 if (error == EFBIG) { 5288 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5289 if (m == NULL) { 5290 m_freem(*m_head); 5291 *m_head = NULL; 5292 return (ENOBUFS); 5293 } 5294 *m_head = m; 5295 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5296 m, segs, &nsegs, BUS_DMA_NOWAIT); 5297 if (error) { 5298 m_freem(m); 5299 *m_head = NULL; 5300 return (error); 5301 } 5302 } else if (error != 0) 5303 return (error); 5304 5305 /* Check if we have enough free send BDs. */ 5306 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5307 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5308 return (ENOBUFS); 5309 } 5310 5311 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5312 5313 if (m->m_flags & M_VLANTAG) { 5314 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5315 vlan_tag = m->m_pkthdr.ether_vtag; 5316 } 5317 5318 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5319 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5320 /* 5321 * 5725 family of devices corrupts TSO packets when TSO DMA 5322 * buffers cross into regions which are within MSS bytes of 5323 * a 4GB boundary. If we encounter the condition, drop the 5324 * packet. 5325 */ 5326 for (i = 0; ; i++) { 5327 d = &sc->bge_ldata.bge_tx_ring[idx]; 5328 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5329 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5330 d->bge_len = segs[i].ds_len; 5331 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5332 d->bge_addr.bge_addr_lo) 5333 break; 5334 d->bge_flags = csum_flags; 5335 d->bge_vlan_tag = vlan_tag; 5336 d->bge_mss = mss; 5337 if (i == nsegs - 1) 5338 break; 5339 BGE_INC(idx, BGE_TX_RING_CNT); 5340 } 5341 if (i != nsegs - 1) { 5342 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5343 BUS_DMASYNC_POSTWRITE); 5344 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5345 m_freem(*m_head); 5346 *m_head = NULL; 5347 return (EIO); 5348 } 5349 } else { 5350 for (i = 0; ; i++) { 5351 d = &sc->bge_ldata.bge_tx_ring[idx]; 5352 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5353 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5354 d->bge_len = segs[i].ds_len; 5355 d->bge_flags = csum_flags; 5356 d->bge_vlan_tag = vlan_tag; 5357 d->bge_mss = mss; 5358 if (i == nsegs - 1) 5359 break; 5360 BGE_INC(idx, BGE_TX_RING_CNT); 5361 } 5362 } 5363 5364 /* Mark the last segment as end of packet... */ 5365 d->bge_flags |= BGE_TXBDFLAG_END; 5366 5367 /* 5368 * Insure that the map for this transmission 5369 * is placed at the array index of the last descriptor 5370 * in this chain. 5371 */ 5372 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5373 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5374 sc->bge_cdata.bge_tx_chain[idx] = m; 5375 sc->bge_txcnt += nsegs; 5376 5377 BGE_INC(idx, BGE_TX_RING_CNT); 5378 *txidx = idx; 5379 5380 return (0); 5381 } 5382 5383 /* 5384 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5385 * to the mbuf data regions directly in the transmit descriptors. 5386 */ 5387 static void 5388 bge_start_locked(if_t ifp) 5389 { 5390 struct bge_softc *sc; 5391 struct mbuf *m_head; 5392 uint32_t prodidx; 5393 int count; 5394 5395 sc = if_getsoftc(ifp); 5396 BGE_LOCK_ASSERT(sc); 5397 5398 if (!sc->bge_link || 5399 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5400 IFF_DRV_RUNNING) 5401 return; 5402 5403 prodidx = sc->bge_tx_prodidx; 5404 5405 for (count = 0; !if_sendq_empty(ifp);) { 5406 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5407 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5408 break; 5409 } 5410 m_head = if_dequeue(ifp); 5411 if (m_head == NULL) 5412 break; 5413 5414 /* 5415 * Pack the data into the transmit ring. If we 5416 * don't have room, set the OACTIVE flag and wait 5417 * for the NIC to drain the ring. 5418 */ 5419 if (bge_encap(sc, &m_head, &prodidx)) { 5420 if (m_head == NULL) 5421 break; 5422 if_sendq_prepend(ifp, m_head); 5423 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5424 break; 5425 } 5426 ++count; 5427 5428 /* 5429 * If there's a BPF listener, bounce a copy of this frame 5430 * to him. 5431 */ 5432 if_bpfmtap(ifp, m_head); 5433 } 5434 5435 if (count > 0) 5436 bge_start_tx(sc, prodidx); 5437 } 5438 5439 static void 5440 bge_start_tx(struct bge_softc *sc, uint32_t prodidx) 5441 { 5442 5443 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5444 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5445 /* Transmit. */ 5446 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5447 /* 5700 b2 errata */ 5448 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5449 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5450 5451 sc->bge_tx_prodidx = prodidx; 5452 5453 /* Set a timeout in case the chip goes out to lunch. */ 5454 sc->bge_timer = BGE_TX_TIMEOUT; 5455 } 5456 5457 /* 5458 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5459 * to the mbuf data regions directly in the transmit descriptors. 5460 */ 5461 static void 5462 bge_start(if_t ifp) 5463 { 5464 struct bge_softc *sc; 5465 5466 sc = if_getsoftc(ifp); 5467 BGE_LOCK(sc); 5468 bge_start_locked(ifp); 5469 BGE_UNLOCK(sc); 5470 } 5471 5472 static void 5473 bge_init_locked(struct bge_softc *sc) 5474 { 5475 if_t ifp; 5476 uint16_t *m; 5477 uint32_t mode; 5478 5479 BGE_LOCK_ASSERT(sc); 5480 5481 ifp = sc->bge_ifp; 5482 5483 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5484 return; 5485 5486 /* Cancel pending I/O and flush buffers. */ 5487 bge_stop(sc); 5488 5489 bge_stop_fw(sc); 5490 bge_sig_pre_reset(sc, BGE_RESET_START); 5491 bge_reset(sc); 5492 bge_sig_legacy(sc, BGE_RESET_START); 5493 bge_sig_post_reset(sc, BGE_RESET_START); 5494 5495 bge_chipinit(sc); 5496 5497 /* 5498 * Init the various state machines, ring 5499 * control blocks and firmware. 5500 */ 5501 if (bge_blockinit(sc)) { 5502 device_printf(sc->bge_dev, "initialization failure\n"); 5503 return; 5504 } 5505 5506 ifp = sc->bge_ifp; 5507 5508 /* Specify MTU. */ 5509 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5510 ETHER_HDR_LEN + ETHER_CRC_LEN + 5511 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5512 5513 /* Load our MAC address. */ 5514 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5515 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5516 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5517 5518 /* Program promiscuous mode. */ 5519 bge_setpromisc(sc); 5520 5521 /* Program multicast filter. */ 5522 bge_setmulti(sc); 5523 5524 /* Program VLAN tag stripping. */ 5525 bge_setvlan(sc); 5526 5527 /* Override UDP checksum offloading. */ 5528 if (sc->bge_forced_udpcsum == 0) 5529 sc->bge_csum_features &= ~CSUM_UDP; 5530 else 5531 sc->bge_csum_features |= CSUM_UDP; 5532 if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5533 if_getcapenable(ifp) & IFCAP_TXCSUM) { 5534 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5535 if_sethwassistbits(ifp, sc->bge_csum_features, 0); 5536 } 5537 5538 /* Init RX ring. */ 5539 if (bge_init_rx_ring_std(sc) != 0) { 5540 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5541 bge_stop(sc); 5542 return; 5543 } 5544 5545 /* 5546 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5547 * memory to insure that the chip has in fact read the first 5548 * entry of the ring. 5549 */ 5550 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5551 uint32_t v, i; 5552 for (i = 0; i < 10; i++) { 5553 DELAY(20); 5554 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5555 if (v == (MCLBYTES - ETHER_ALIGN)) 5556 break; 5557 } 5558 if (i == 10) 5559 device_printf (sc->bge_dev, 5560 "5705 A0 chip failed to load RX ring\n"); 5561 } 5562 5563 /* Init jumbo RX ring. */ 5564 if (BGE_IS_JUMBO_CAPABLE(sc) && 5565 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5566 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 5567 if (bge_init_rx_ring_jumbo(sc) != 0) { 5568 device_printf(sc->bge_dev, 5569 "no memory for jumbo Rx buffers.\n"); 5570 bge_stop(sc); 5571 return; 5572 } 5573 } 5574 5575 /* Init our RX return ring index. */ 5576 sc->bge_rx_saved_considx = 0; 5577 5578 /* Init our RX/TX stat counters. */ 5579 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5580 5581 /* Init TX ring. */ 5582 bge_init_tx_ring(sc); 5583 5584 /* Enable TX MAC state machine lockup fix. */ 5585 mode = CSR_READ_4(sc, BGE_TX_MODE); 5586 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5587 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5588 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5589 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5590 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5591 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5592 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5593 } 5594 /* Turn on transmitter. */ 5595 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5596 DELAY(100); 5597 5598 /* Turn on receiver. */ 5599 mode = CSR_READ_4(sc, BGE_RX_MODE); 5600 if (BGE_IS_5755_PLUS(sc)) 5601 mode |= BGE_RXMODE_IPV6_ENABLE; 5602 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5603 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5604 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5605 DELAY(10); 5606 5607 /* 5608 * Set the number of good frames to receive after RX MBUF 5609 * Low Watermark has been reached. After the RX MAC receives 5610 * this number of frames, it will drop subsequent incoming 5611 * frames until the MBUF High Watermark is reached. 5612 */ 5613 if (BGE_IS_57765_PLUS(sc)) 5614 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5615 else 5616 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5617 5618 /* Clear MAC statistics. */ 5619 if (BGE_IS_5705_PLUS(sc)) 5620 bge_stats_clear_regs(sc); 5621 5622 /* Tell firmware we're alive. */ 5623 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5624 5625 #ifdef DEVICE_POLLING 5626 /* Disable interrupts if we are polling. */ 5627 if (if_getcapenable(ifp) & IFCAP_POLLING) { 5628 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5629 BGE_PCIMISCCTL_MASK_PCI_INTR); 5630 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5631 } else 5632 #endif 5633 5634 /* Enable host interrupts. */ 5635 { 5636 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5637 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5638 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5639 } 5640 5641 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5642 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 5643 5644 bge_ifmedia_upd_locked(ifp); 5645 5646 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5647 } 5648 5649 static void 5650 bge_init(void *xsc) 5651 { 5652 struct bge_softc *sc = xsc; 5653 5654 BGE_LOCK(sc); 5655 bge_init_locked(sc); 5656 BGE_UNLOCK(sc); 5657 } 5658 5659 /* 5660 * Set media options. 5661 */ 5662 static int 5663 bge_ifmedia_upd(if_t ifp) 5664 { 5665 struct bge_softc *sc = if_getsoftc(ifp); 5666 int res; 5667 5668 BGE_LOCK(sc); 5669 res = bge_ifmedia_upd_locked(ifp); 5670 BGE_UNLOCK(sc); 5671 5672 return (res); 5673 } 5674 5675 static int 5676 bge_ifmedia_upd_locked(if_t ifp) 5677 { 5678 struct bge_softc *sc = if_getsoftc(ifp); 5679 struct mii_data *mii; 5680 struct mii_softc *miisc; 5681 struct ifmedia *ifm; 5682 5683 BGE_LOCK_ASSERT(sc); 5684 5685 ifm = &sc->bge_ifmedia; 5686 5687 /* If this is a 1000baseX NIC, enable the TBI port. */ 5688 if (sc->bge_flags & BGE_FLAG_TBI) { 5689 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5690 return (EINVAL); 5691 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5692 case IFM_AUTO: 5693 /* 5694 * The BCM5704 ASIC appears to have a special 5695 * mechanism for programming the autoneg 5696 * advertisement registers in TBI mode. 5697 */ 5698 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5699 uint32_t sgdig; 5700 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5701 if (sgdig & BGE_SGDIGSTS_DONE) { 5702 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5703 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5704 sgdig |= BGE_SGDIGCFG_AUTO | 5705 BGE_SGDIGCFG_PAUSE_CAP | 5706 BGE_SGDIGCFG_ASYM_PAUSE; 5707 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5708 sgdig | BGE_SGDIGCFG_SEND); 5709 DELAY(5); 5710 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5711 } 5712 } 5713 break; 5714 case IFM_1000_SX: 5715 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5716 BGE_CLRBIT(sc, BGE_MAC_MODE, 5717 BGE_MACMODE_HALF_DUPLEX); 5718 } else { 5719 BGE_SETBIT(sc, BGE_MAC_MODE, 5720 BGE_MACMODE_HALF_DUPLEX); 5721 } 5722 DELAY(40); 5723 break; 5724 default: 5725 return (EINVAL); 5726 } 5727 return (0); 5728 } 5729 5730 sc->bge_link_evt++; 5731 mii = device_get_softc(sc->bge_miibus); 5732 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5733 PHY_RESET(miisc); 5734 mii_mediachg(mii); 5735 5736 /* 5737 * Force an interrupt so that we will call bge_link_upd 5738 * if needed and clear any pending link state attention. 5739 * Without this we are not getting any further interrupts 5740 * for link state changes and thus will not UP the link and 5741 * not be able to send in bge_start_locked. The only 5742 * way to get things working was to receive a packet and 5743 * get an RX intr. 5744 * bge_tick should help for fiber cards and we might not 5745 * need to do this here if BGE_FLAG_TBI is set but as 5746 * we poll for fiber anyway it should not harm. 5747 */ 5748 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5749 sc->bge_flags & BGE_FLAG_5788) 5750 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5751 else 5752 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5753 5754 return (0); 5755 } 5756 5757 /* 5758 * Report current media status. 5759 */ 5760 static void 5761 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 5762 { 5763 struct bge_softc *sc = if_getsoftc(ifp); 5764 struct mii_data *mii; 5765 5766 BGE_LOCK(sc); 5767 5768 if ((if_getflags(ifp) & IFF_UP) == 0) { 5769 BGE_UNLOCK(sc); 5770 return; 5771 } 5772 if (sc->bge_flags & BGE_FLAG_TBI) { 5773 ifmr->ifm_status = IFM_AVALID; 5774 ifmr->ifm_active = IFM_ETHER; 5775 if (CSR_READ_4(sc, BGE_MAC_STS) & 5776 BGE_MACSTAT_TBI_PCS_SYNCHED) 5777 ifmr->ifm_status |= IFM_ACTIVE; 5778 else { 5779 ifmr->ifm_active |= IFM_NONE; 5780 BGE_UNLOCK(sc); 5781 return; 5782 } 5783 ifmr->ifm_active |= IFM_1000_SX; 5784 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5785 ifmr->ifm_active |= IFM_HDX; 5786 else 5787 ifmr->ifm_active |= IFM_FDX; 5788 BGE_UNLOCK(sc); 5789 return; 5790 } 5791 5792 mii = device_get_softc(sc->bge_miibus); 5793 mii_pollstat(mii); 5794 ifmr->ifm_active = mii->mii_media_active; 5795 ifmr->ifm_status = mii->mii_media_status; 5796 5797 BGE_UNLOCK(sc); 5798 } 5799 5800 static int 5801 bge_ioctl(if_t ifp, u_long command, caddr_t data) 5802 { 5803 struct bge_softc *sc = if_getsoftc(ifp); 5804 struct ifreq *ifr = (struct ifreq *) data; 5805 struct mii_data *mii; 5806 int flags, mask, error = 0; 5807 5808 switch (command) { 5809 case SIOCSIFMTU: 5810 if (BGE_IS_JUMBO_CAPABLE(sc) || 5811 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5812 if (ifr->ifr_mtu < ETHERMIN || 5813 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5814 error = EINVAL; 5815 break; 5816 } 5817 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5818 error = EINVAL; 5819 break; 5820 } 5821 BGE_LOCK(sc); 5822 if (if_getmtu(ifp) != ifr->ifr_mtu) { 5823 if_setmtu(ifp, ifr->ifr_mtu); 5824 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5825 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5826 bge_init_locked(sc); 5827 } 5828 } 5829 BGE_UNLOCK(sc); 5830 break; 5831 case SIOCSIFFLAGS: 5832 BGE_LOCK(sc); 5833 if (if_getflags(ifp) & IFF_UP) { 5834 /* 5835 * If only the state of the PROMISC flag changed, 5836 * then just use the 'set promisc mode' command 5837 * instead of reinitializing the entire NIC. Doing 5838 * a full re-init means reloading the firmware and 5839 * waiting for it to start up, which may take a 5840 * second or two. Similarly for ALLMULTI. 5841 */ 5842 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5843 flags = if_getflags(ifp) ^ sc->bge_if_flags; 5844 if (flags & IFF_PROMISC) 5845 bge_setpromisc(sc); 5846 if (flags & IFF_ALLMULTI) 5847 bge_setmulti(sc); 5848 } else 5849 bge_init_locked(sc); 5850 } else { 5851 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5852 bge_stop(sc); 5853 } 5854 } 5855 sc->bge_if_flags = if_getflags(ifp); 5856 BGE_UNLOCK(sc); 5857 error = 0; 5858 break; 5859 case SIOCADDMULTI: 5860 case SIOCDELMULTI: 5861 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5862 BGE_LOCK(sc); 5863 bge_setmulti(sc); 5864 BGE_UNLOCK(sc); 5865 error = 0; 5866 } 5867 break; 5868 case SIOCSIFMEDIA: 5869 case SIOCGIFMEDIA: 5870 if (sc->bge_flags & BGE_FLAG_TBI) { 5871 error = ifmedia_ioctl(ifp, ifr, 5872 &sc->bge_ifmedia, command); 5873 } else { 5874 mii = device_get_softc(sc->bge_miibus); 5875 error = ifmedia_ioctl(ifp, ifr, 5876 &mii->mii_media, command); 5877 } 5878 break; 5879 case SIOCSIFCAP: 5880 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 5881 #ifdef DEVICE_POLLING 5882 if (mask & IFCAP_POLLING) { 5883 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5884 error = ether_poll_register(bge_poll, ifp); 5885 if (error) 5886 return (error); 5887 BGE_LOCK(sc); 5888 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5889 BGE_PCIMISCCTL_MASK_PCI_INTR); 5890 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5891 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 5892 BGE_UNLOCK(sc); 5893 } else { 5894 error = ether_poll_deregister(ifp); 5895 /* Enable interrupt even in error case */ 5896 BGE_LOCK(sc); 5897 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5898 BGE_PCIMISCCTL_MASK_PCI_INTR); 5899 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5900 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 5901 BGE_UNLOCK(sc); 5902 } 5903 } 5904 #endif 5905 if ((mask & IFCAP_TXCSUM) != 0 && 5906 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5907 if_togglecapenable(ifp, IFCAP_TXCSUM); 5908 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5909 if_sethwassistbits(ifp, 5910 sc->bge_csum_features, 0); 5911 else 5912 if_sethwassistbits(ifp, 0, 5913 sc->bge_csum_features); 5914 } 5915 5916 if ((mask & IFCAP_RXCSUM) != 0 && 5917 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5918 if_togglecapenable(ifp, IFCAP_RXCSUM); 5919 5920 if ((mask & IFCAP_TSO4) != 0 && 5921 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5922 if_togglecapenable(ifp, IFCAP_TSO4); 5923 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5924 if_sethwassistbits(ifp, CSUM_TSO, 0); 5925 else 5926 if_sethwassistbits(ifp, 0, CSUM_TSO); 5927 } 5928 5929 if (mask & IFCAP_VLAN_MTU) { 5930 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5931 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5932 bge_init(sc); 5933 } 5934 5935 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5936 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5937 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 5938 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5939 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5940 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5941 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5942 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5943 BGE_LOCK(sc); 5944 bge_setvlan(sc); 5945 BGE_UNLOCK(sc); 5946 } 5947 #ifdef VLAN_CAPABILITIES 5948 if_vlancap(ifp); 5949 #endif 5950 break; 5951 default: 5952 error = ether_ioctl(ifp, command, data); 5953 break; 5954 } 5955 5956 return (error); 5957 } 5958 5959 static void 5960 bge_watchdog(struct bge_softc *sc) 5961 { 5962 if_t ifp; 5963 uint32_t status; 5964 5965 BGE_LOCK_ASSERT(sc); 5966 5967 if (sc->bge_timer == 0 || --sc->bge_timer) 5968 return; 5969 5970 /* If pause frames are active then don't reset the hardware. */ 5971 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5972 status = CSR_READ_4(sc, BGE_RX_STS); 5973 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5974 /* 5975 * If link partner has us in XOFF state then wait for 5976 * the condition to clear. 5977 */ 5978 CSR_WRITE_4(sc, BGE_RX_STS, status); 5979 sc->bge_timer = BGE_TX_TIMEOUT; 5980 return; 5981 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5982 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5983 /* 5984 * If link partner has us in XOFF state then wait for 5985 * the condition to clear. 5986 */ 5987 CSR_WRITE_4(sc, BGE_RX_STS, status); 5988 sc->bge_timer = BGE_TX_TIMEOUT; 5989 return; 5990 } 5991 /* 5992 * Any other condition is unexpected and the controller 5993 * should be reset. 5994 */ 5995 } 5996 5997 ifp = sc->bge_ifp; 5998 5999 if_printf(ifp, "watchdog timeout -- resetting\n"); 6000 6001 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6002 bge_init_locked(sc); 6003 6004 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 6005 } 6006 6007 static void 6008 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 6009 { 6010 int i; 6011 6012 BGE_CLRBIT(sc, reg, bit); 6013 6014 for (i = 0; i < BGE_TIMEOUT; i++) { 6015 if ((CSR_READ_4(sc, reg) & bit) == 0) 6016 return; 6017 DELAY(100); 6018 } 6019 } 6020 6021 /* 6022 * Stop the adapter and free any mbufs allocated to the 6023 * RX and TX lists. 6024 */ 6025 static void 6026 bge_stop(struct bge_softc *sc) 6027 { 6028 if_t ifp; 6029 6030 BGE_LOCK_ASSERT(sc); 6031 6032 ifp = sc->bge_ifp; 6033 6034 callout_stop(&sc->bge_stat_ch); 6035 6036 /* Disable host interrupts. */ 6037 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6038 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 6039 6040 /* 6041 * Tell firmware we're shutting down. 6042 */ 6043 bge_stop_fw(sc); 6044 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6045 6046 /* 6047 * Disable all of the receiver blocks. 6048 */ 6049 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6050 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6051 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6052 if (BGE_IS_5700_FAMILY(sc)) 6053 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6054 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6055 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6056 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6057 6058 /* 6059 * Disable all of the transmit blocks. 6060 */ 6061 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6062 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6063 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6064 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6065 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6066 if (BGE_IS_5700_FAMILY(sc)) 6067 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6068 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6069 6070 /* 6071 * Shut down all of the memory managers and related 6072 * state machines. 6073 */ 6074 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6075 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6076 if (BGE_IS_5700_FAMILY(sc)) 6077 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6078 6079 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6080 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6081 if (!(BGE_IS_5705_PLUS(sc))) { 6082 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6083 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6084 } 6085 /* Update MAC statistics. */ 6086 if (BGE_IS_5705_PLUS(sc)) 6087 bge_stats_update_regs(sc); 6088 6089 bge_reset(sc); 6090 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6091 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6092 6093 /* 6094 * Keep the ASF firmware running if up. 6095 */ 6096 if (sc->bge_asf_mode & ASF_STACKUP) 6097 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6098 else 6099 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6100 6101 /* Free the RX lists. */ 6102 bge_free_rx_ring_std(sc); 6103 6104 /* Free jumbo RX list. */ 6105 if (BGE_IS_JUMBO_CAPABLE(sc)) 6106 bge_free_rx_ring_jumbo(sc); 6107 6108 /* Free TX buffers. */ 6109 bge_free_tx_ring(sc); 6110 6111 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6112 6113 /* Clear MAC's link state (PHY may still have link UP). */ 6114 if (bootverbose && sc->bge_link) 6115 if_printf(sc->bge_ifp, "link DOWN\n"); 6116 sc->bge_link = 0; 6117 6118 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 6119 } 6120 6121 /* 6122 * Stop all chip I/O so that the kernel's probe routines don't 6123 * get confused by errant DMAs when rebooting. 6124 */ 6125 static int 6126 bge_shutdown(device_t dev) 6127 { 6128 struct bge_softc *sc; 6129 6130 sc = device_get_softc(dev); 6131 BGE_LOCK(sc); 6132 bge_stop(sc); 6133 BGE_UNLOCK(sc); 6134 6135 return (0); 6136 } 6137 6138 static int 6139 bge_suspend(device_t dev) 6140 { 6141 struct bge_softc *sc; 6142 6143 sc = device_get_softc(dev); 6144 BGE_LOCK(sc); 6145 bge_stop(sc); 6146 BGE_UNLOCK(sc); 6147 6148 return (0); 6149 } 6150 6151 static int 6152 bge_resume(device_t dev) 6153 { 6154 struct bge_softc *sc; 6155 if_t ifp; 6156 6157 sc = device_get_softc(dev); 6158 BGE_LOCK(sc); 6159 ifp = sc->bge_ifp; 6160 if (if_getflags(ifp) & IFF_UP) { 6161 bge_init_locked(sc); 6162 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6163 bge_start_locked(ifp); 6164 } 6165 BGE_UNLOCK(sc); 6166 6167 return (0); 6168 } 6169 6170 static void 6171 bge_link_upd(struct bge_softc *sc) 6172 { 6173 struct mii_data *mii; 6174 uint32_t link, status; 6175 6176 BGE_LOCK_ASSERT(sc); 6177 6178 /* Clear 'pending link event' flag. */ 6179 sc->bge_link_evt = 0; 6180 6181 /* 6182 * Process link state changes. 6183 * Grrr. The link status word in the status block does 6184 * not work correctly on the BCM5700 rev AX and BX chips, 6185 * according to all available information. Hence, we have 6186 * to enable MII interrupts in order to properly obtain 6187 * async link changes. Unfortunately, this also means that 6188 * we have to read the MAC status register to detect link 6189 * changes, thereby adding an additional register access to 6190 * the interrupt handler. 6191 * 6192 * XXX: perhaps link state detection procedure used for 6193 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6194 */ 6195 6196 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6197 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6198 status = CSR_READ_4(sc, BGE_MAC_STS); 6199 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6200 mii = device_get_softc(sc->bge_miibus); 6201 mii_pollstat(mii); 6202 if (!sc->bge_link && 6203 mii->mii_media_status & IFM_ACTIVE && 6204 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6205 sc->bge_link++; 6206 if (bootverbose) 6207 if_printf(sc->bge_ifp, "link UP\n"); 6208 } else if (sc->bge_link && 6209 (!(mii->mii_media_status & IFM_ACTIVE) || 6210 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6211 sc->bge_link = 0; 6212 if (bootverbose) 6213 if_printf(sc->bge_ifp, "link DOWN\n"); 6214 } 6215 6216 /* Clear the interrupt. */ 6217 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6218 BGE_EVTENB_MI_INTERRUPT); 6219 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6220 BRGPHY_MII_ISR); 6221 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6222 BRGPHY_MII_IMR, BRGPHY_INTRS); 6223 } 6224 return; 6225 } 6226 6227 if (sc->bge_flags & BGE_FLAG_TBI) { 6228 status = CSR_READ_4(sc, BGE_MAC_STS); 6229 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6230 if (!sc->bge_link) { 6231 sc->bge_link++; 6232 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6233 BGE_CLRBIT(sc, BGE_MAC_MODE, 6234 BGE_MACMODE_TBI_SEND_CFGS); 6235 DELAY(40); 6236 } 6237 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6238 if (bootverbose) 6239 if_printf(sc->bge_ifp, "link UP\n"); 6240 if_link_state_change(sc->bge_ifp, 6241 LINK_STATE_UP); 6242 } 6243 } else if (sc->bge_link) { 6244 sc->bge_link = 0; 6245 if (bootverbose) 6246 if_printf(sc->bge_ifp, "link DOWN\n"); 6247 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6248 } 6249 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6250 /* 6251 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6252 * in status word always set. Workaround this bug by reading 6253 * PHY link status directly. 6254 */ 6255 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6256 6257 if (link != sc->bge_link || 6258 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6259 mii = device_get_softc(sc->bge_miibus); 6260 mii_pollstat(mii); 6261 if (!sc->bge_link && 6262 mii->mii_media_status & IFM_ACTIVE && 6263 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6264 sc->bge_link++; 6265 if (bootverbose) 6266 if_printf(sc->bge_ifp, "link UP\n"); 6267 } else if (sc->bge_link && 6268 (!(mii->mii_media_status & IFM_ACTIVE) || 6269 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6270 sc->bge_link = 0; 6271 if (bootverbose) 6272 if_printf(sc->bge_ifp, "link DOWN\n"); 6273 } 6274 } 6275 } else { 6276 /* 6277 * For controllers that call mii_tick, we have to poll 6278 * link status. 6279 */ 6280 mii = device_get_softc(sc->bge_miibus); 6281 mii_pollstat(mii); 6282 bge_miibus_statchg(sc->bge_dev); 6283 } 6284 6285 /* Disable MAC attention when link is up. */ 6286 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6287 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6288 BGE_MACSTAT_LINK_CHANGED); 6289 } 6290 6291 static void 6292 bge_add_sysctls(struct bge_softc *sc) 6293 { 6294 struct sysctl_ctx_list *ctx; 6295 struct sysctl_oid_list *children; 6296 int unit; 6297 6298 ctx = device_get_sysctl_ctx(sc->bge_dev); 6299 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6300 6301 #ifdef BGE_REGISTER_DEBUG 6302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6303 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6304 "Debug Information"); 6305 6306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6307 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6308 "MAC Register Read"); 6309 6310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6311 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6312 "APE Register Read"); 6313 6314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6315 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6316 "Memory Read"); 6317 6318 #endif 6319 6320 unit = device_get_unit(sc->bge_dev); 6321 /* 6322 * A common design characteristic for many Broadcom client controllers 6323 * is that they only support a single outstanding DMA read operation 6324 * on the PCIe bus. This means that it will take twice as long to fetch 6325 * a TX frame that is split into header and payload buffers as it does 6326 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6327 * these controllers, coalescing buffers to reduce the number of memory 6328 * reads is effective way to get maximum performance(about 940Mbps). 6329 * Without collapsing TX buffers the maximum TCP bulk transfer 6330 * performance is about 850Mbps. However forcing coalescing mbufs 6331 * consumes a lot of CPU cycles, so leave it off by default. 6332 */ 6333 sc->bge_forced_collapse = 0; 6334 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6335 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6336 "Number of fragmented TX buffers of a frame allowed before " 6337 "forced collapsing"); 6338 6339 sc->bge_msi = 1; 6340 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6341 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 6342 6343 /* 6344 * It seems all Broadcom controllers have a bug that can generate UDP 6345 * datagrams with checksum value 0 when TX UDP checksum offloading is 6346 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6347 * Even though the probability of generating such UDP datagrams is 6348 * low, I don't want to see FreeBSD boxes to inject such datagrams 6349 * into network so disable UDP checksum offloading by default. Users 6350 * still override this behavior by setting a sysctl variable, 6351 * dev.bge.0.forced_udpcsum. 6352 */ 6353 sc->bge_forced_udpcsum = 0; 6354 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6355 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 6356 "Enable UDP checksum offloading even if controller can " 6357 "generate UDP checksum value 0"); 6358 6359 if (BGE_IS_5705_PLUS(sc)) 6360 bge_add_sysctl_stats_regs(sc, ctx, children); 6361 else 6362 bge_add_sysctl_stats(sc, ctx, children); 6363 } 6364 6365 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6366 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6367 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6368 desc) 6369 6370 static void 6371 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6372 struct sysctl_oid_list *parent) 6373 { 6374 struct sysctl_oid *tree; 6375 struct sysctl_oid_list *children, *schildren; 6376 6377 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6378 NULL, "BGE Statistics"); 6379 schildren = children = SYSCTL_CHILDREN(tree); 6380 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6381 children, COSFramesDroppedDueToFilters, 6382 "FramesDroppedDueToFilters"); 6383 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6384 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6385 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6386 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6387 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6388 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6390 children, ifInDiscards, "InputDiscards"); 6391 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6392 children, ifInErrors, "InputErrors"); 6393 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6394 children, nicRecvThresholdHit, "RecvThresholdHit"); 6395 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6396 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6397 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6398 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6399 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6400 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6401 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6402 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6403 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6404 children, nicRingStatusUpdate, "RingStatusUpdate"); 6405 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6406 children, nicInterrupts, "Interrupts"); 6407 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6408 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6409 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6410 children, nicSendThresholdHit, "SendThresholdHit"); 6411 6412 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6413 NULL, "BGE RX Statistics"); 6414 children = SYSCTL_CHILDREN(tree); 6415 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6416 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6417 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6418 children, rxstats.etherStatsFragments, "Fragments"); 6419 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6420 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6421 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6422 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6423 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6424 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6426 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6427 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6428 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6429 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6430 children, rxstats.xoffPauseFramesReceived, 6431 "xoffPauseFramesReceived"); 6432 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6433 children, rxstats.macControlFramesReceived, 6434 "ControlFramesReceived"); 6435 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6436 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6437 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6438 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6439 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6440 children, rxstats.etherStatsJabbers, "Jabbers"); 6441 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6442 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6443 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6444 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6445 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6446 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6447 6448 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6449 NULL, "BGE TX Statistics"); 6450 children = SYSCTL_CHILDREN(tree); 6451 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6452 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6453 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6454 children, txstats.etherStatsCollisions, "Collisions"); 6455 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6456 children, txstats.outXonSent, "XonSent"); 6457 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6458 children, txstats.outXoffSent, "XoffSent"); 6459 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6460 children, txstats.flowControlDone, "flowControlDone"); 6461 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6462 children, txstats.dot3StatsInternalMacTransmitErrors, 6463 "InternalMacTransmitErrors"); 6464 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6465 children, txstats.dot3StatsSingleCollisionFrames, 6466 "SingleCollisionFrames"); 6467 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6468 children, txstats.dot3StatsMultipleCollisionFrames, 6469 "MultipleCollisionFrames"); 6470 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6471 children, txstats.dot3StatsDeferredTransmissions, 6472 "DeferredTransmissions"); 6473 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6474 children, txstats.dot3StatsExcessiveCollisions, 6475 "ExcessiveCollisions"); 6476 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6477 children, txstats.dot3StatsLateCollisions, 6478 "LateCollisions"); 6479 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6480 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6481 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6482 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6483 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6484 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6485 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6486 children, txstats.dot3StatsCarrierSenseErrors, 6487 "CarrierSenseErrors"); 6488 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6489 children, txstats.ifOutDiscards, "Discards"); 6490 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6491 children, txstats.ifOutErrors, "Errors"); 6492 } 6493 6494 #undef BGE_SYSCTL_STAT 6495 6496 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6497 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6498 6499 static void 6500 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6501 struct sysctl_oid_list *parent) 6502 { 6503 struct sysctl_oid *tree; 6504 struct sysctl_oid_list *child, *schild; 6505 struct bge_mac_stats *stats; 6506 6507 stats = &sc->bge_mac_stats; 6508 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6509 NULL, "BGE Statistics"); 6510 schild = child = SYSCTL_CHILDREN(tree); 6511 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6512 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6513 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6514 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6516 &stats->DmaWriteHighPriQueueFull, 6517 "NIC DMA Write High Priority Queue Full"); 6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6519 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6520 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6521 &stats->InputDiscards, "Discarded Input Frames"); 6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6523 &stats->InputErrors, "Input Errors"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6525 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6526 6527 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6528 NULL, "BGE RX Statistics"); 6529 child = SYSCTL_CHILDREN(tree); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6531 &stats->ifHCInOctets, "Inbound Octets"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6533 &stats->etherStatsFragments, "Fragments"); 6534 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6535 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6536 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6537 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6538 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6539 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6540 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6541 &stats->dot3StatsFCSErrors, "FCS Errors"); 6542 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6543 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6544 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6545 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6546 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6547 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6548 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6549 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6550 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6551 &stats->xoffStateEntered, "XOFF State Entered"); 6552 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6553 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6554 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6555 &stats->etherStatsJabbers, "Jabbers"); 6556 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6557 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6558 6559 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6560 NULL, "BGE TX Statistics"); 6561 child = SYSCTL_CHILDREN(tree); 6562 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6563 &stats->ifHCOutOctets, "Outbound Octets"); 6564 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6565 &stats->etherStatsCollisions, "TX Collisions"); 6566 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6567 &stats->outXonSent, "XON Sent"); 6568 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6569 &stats->outXoffSent, "XOFF Sent"); 6570 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6571 &stats->dot3StatsInternalMacTransmitErrors, 6572 "Internal MAC TX Errors"); 6573 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6574 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6575 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6576 &stats->dot3StatsMultipleCollisionFrames, 6577 "Multiple Collision Frames"); 6578 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6579 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6580 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6581 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6582 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6583 &stats->dot3StatsLateCollisions, "Late Collisions"); 6584 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6585 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6586 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6587 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6588 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6589 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6590 } 6591 6592 #undef BGE_SYSCTL_STAT_ADD64 6593 6594 static int 6595 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6596 { 6597 struct bge_softc *sc; 6598 uint32_t result; 6599 int offset; 6600 6601 sc = (struct bge_softc *)arg1; 6602 offset = arg2; 6603 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6604 offsetof(bge_hostaddr, bge_addr_lo)); 6605 return (sysctl_handle_int(oidp, &result, 0, req)); 6606 } 6607 6608 #ifdef BGE_REGISTER_DEBUG 6609 static int 6610 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6611 { 6612 struct bge_softc *sc; 6613 uint16_t *sbdata; 6614 int error, result, sbsz; 6615 int i, j; 6616 6617 result = -1; 6618 error = sysctl_handle_int(oidp, &result, 0, req); 6619 if (error || (req->newptr == NULL)) 6620 return (error); 6621 6622 if (result == 1) { 6623 sc = (struct bge_softc *)arg1; 6624 6625 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6626 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6627 sbsz = BGE_STATUS_BLK_SZ; 6628 else 6629 sbsz = 32; 6630 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6631 printf("Status Block:\n"); 6632 BGE_LOCK(sc); 6633 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6634 sc->bge_cdata.bge_status_map, 6635 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6636 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6637 printf("%06x:", i); 6638 for (j = 0; j < 8; j++) 6639 printf(" %04x", sbdata[i++]); 6640 printf("\n"); 6641 } 6642 6643 printf("Registers:\n"); 6644 for (i = 0x800; i < 0xA00; ) { 6645 printf("%06x:", i); 6646 for (j = 0; j < 8; j++) { 6647 printf(" %08x", CSR_READ_4(sc, i)); 6648 i += 4; 6649 } 6650 printf("\n"); 6651 } 6652 BGE_UNLOCK(sc); 6653 6654 printf("Hardware Flags:\n"); 6655 if (BGE_IS_5717_PLUS(sc)) 6656 printf(" - 5717 Plus\n"); 6657 if (BGE_IS_5755_PLUS(sc)) 6658 printf(" - 5755 Plus\n"); 6659 if (BGE_IS_575X_PLUS(sc)) 6660 printf(" - 575X Plus\n"); 6661 if (BGE_IS_5705_PLUS(sc)) 6662 printf(" - 5705 Plus\n"); 6663 if (BGE_IS_5714_FAMILY(sc)) 6664 printf(" - 5714 Family\n"); 6665 if (BGE_IS_5700_FAMILY(sc)) 6666 printf(" - 5700 Family\n"); 6667 if (sc->bge_flags & BGE_FLAG_JUMBO) 6668 printf(" - Supports Jumbo Frames\n"); 6669 if (sc->bge_flags & BGE_FLAG_PCIX) 6670 printf(" - PCI-X Bus\n"); 6671 if (sc->bge_flags & BGE_FLAG_PCIE) 6672 printf(" - PCI Express Bus\n"); 6673 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6674 printf(" - No 3 LEDs\n"); 6675 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6676 printf(" - RX Alignment Bug\n"); 6677 } 6678 6679 return (error); 6680 } 6681 6682 static int 6683 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6684 { 6685 struct bge_softc *sc; 6686 int error; 6687 uint16_t result; 6688 uint32_t val; 6689 6690 result = -1; 6691 error = sysctl_handle_int(oidp, &result, 0, req); 6692 if (error || (req->newptr == NULL)) 6693 return (error); 6694 6695 if (result < 0x8000) { 6696 sc = (struct bge_softc *)arg1; 6697 val = CSR_READ_4(sc, result); 6698 printf("reg 0x%06X = 0x%08X\n", result, val); 6699 } 6700 6701 return (error); 6702 } 6703 6704 static int 6705 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6706 { 6707 struct bge_softc *sc; 6708 int error; 6709 uint16_t result; 6710 uint32_t val; 6711 6712 result = -1; 6713 error = sysctl_handle_int(oidp, &result, 0, req); 6714 if (error || (req->newptr == NULL)) 6715 return (error); 6716 6717 if (result < 0x8000) { 6718 sc = (struct bge_softc *)arg1; 6719 val = APE_READ_4(sc, result); 6720 printf("reg 0x%06X = 0x%08X\n", result, val); 6721 } 6722 6723 return (error); 6724 } 6725 6726 static int 6727 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6728 { 6729 struct bge_softc *sc; 6730 int error; 6731 uint16_t result; 6732 uint32_t val; 6733 6734 result = -1; 6735 error = sysctl_handle_int(oidp, &result, 0, req); 6736 if (error || (req->newptr == NULL)) 6737 return (error); 6738 6739 if (result < 0x8000) { 6740 sc = (struct bge_softc *)arg1; 6741 val = bge_readmem_ind(sc, result); 6742 printf("mem 0x%06X = 0x%08X\n", result, val); 6743 } 6744 6745 return (error); 6746 } 6747 #endif 6748 6749 static int 6750 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6751 { 6752 #ifdef __sparc64__ 6753 if (sc->bge_flags & BGE_FLAG_EADDR) 6754 return (1); 6755 6756 OF_getetheraddr(sc->bge_dev, ether_addr); 6757 return (0); 6758 #else 6759 return (1); 6760 #endif 6761 } 6762 6763 static int 6764 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6765 { 6766 uint32_t mac_addr; 6767 6768 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6769 if ((mac_addr >> 16) == 0x484b) { 6770 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6771 ether_addr[1] = (uint8_t)mac_addr; 6772 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6773 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6774 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6775 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6776 ether_addr[5] = (uint8_t)mac_addr; 6777 return (0); 6778 } 6779 return (1); 6780 } 6781 6782 static int 6783 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6784 { 6785 int mac_offset = BGE_EE_MAC_OFFSET; 6786 6787 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6788 mac_offset = BGE_EE_MAC_OFFSET_5906; 6789 6790 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6791 ETHER_ADDR_LEN)); 6792 } 6793 6794 static int 6795 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6796 { 6797 6798 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6799 return (1); 6800 6801 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6802 ETHER_ADDR_LEN)); 6803 } 6804 6805 static int 6806 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6807 { 6808 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6809 /* NOTE: Order is critical */ 6810 bge_get_eaddr_fw, 6811 bge_get_eaddr_mem, 6812 bge_get_eaddr_nvram, 6813 bge_get_eaddr_eeprom, 6814 NULL 6815 }; 6816 const bge_eaddr_fcn_t *func; 6817 6818 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6819 if ((*func)(sc, eaddr) == 0) 6820 break; 6821 } 6822 return (*func == NULL ? ENXIO : 0); 6823 } 6824 6825 static uint64_t 6826 bge_get_counter(if_t ifp, ift_counter cnt) 6827 { 6828 struct bge_softc *sc; 6829 struct bge_mac_stats *stats; 6830 6831 sc = if_getsoftc(ifp); 6832 if (!BGE_IS_5705_PLUS(sc)) 6833 return (if_get_counter_default(ifp, cnt)); 6834 stats = &sc->bge_mac_stats; 6835 6836 switch (cnt) { 6837 case IFCOUNTER_IERRORS: 6838 return (stats->NoMoreRxBDs + stats->InputDiscards + 6839 stats->InputErrors); 6840 case IFCOUNTER_COLLISIONS: 6841 return (stats->etherStatsCollisions); 6842 default: 6843 return (if_get_counter_default(ifp, cnt)); 6844 } 6845 } 6846 6847 #ifdef NETDUMP 6848 static void 6849 bge_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6850 { 6851 struct bge_softc *sc; 6852 6853 sc = if_getsoftc(ifp); 6854 BGE_LOCK(sc); 6855 *nrxr = sc->bge_return_ring_cnt; 6856 *ncl = NETDUMP_MAX_IN_FLIGHT; 6857 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 && 6858 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 6859 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) 6860 *clsize = MJUM9BYTES; 6861 else 6862 *clsize = MCLBYTES; 6863 BGE_UNLOCK(sc); 6864 } 6865 6866 static void 6867 bge_netdump_event(if_t ifp __unused, enum netdump_ev event __unused) 6868 { 6869 } 6870 6871 static int 6872 bge_netdump_transmit(if_t ifp, struct mbuf *m) 6873 { 6874 struct bge_softc *sc; 6875 uint32_t prodidx; 6876 int error; 6877 6878 sc = if_getsoftc(ifp); 6879 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6880 IFF_DRV_RUNNING) 6881 return (1); 6882 6883 prodidx = sc->bge_tx_prodidx; 6884 error = bge_encap(sc, &m, &prodidx); 6885 if (error == 0) 6886 bge_start_tx(sc, prodidx); 6887 return (error); 6888 } 6889 6890 static int 6891 bge_netdump_poll(if_t ifp, int count) 6892 { 6893 struct bge_softc *sc; 6894 uint32_t rx_prod, tx_cons; 6895 6896 sc = if_getsoftc(ifp); 6897 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6898 IFF_DRV_RUNNING) 6899 return (1); 6900 6901 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6902 sc->bge_cdata.bge_status_map, 6903 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6904 6905 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 6906 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 6907 6908 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6909 sc->bge_cdata.bge_status_map, 6910 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6911 6912 (void)bge_rxeof(sc, rx_prod, 0); 6913 bge_txeof(sc, tx_cons); 6914 return (0); 6915 } 6916 #endif /* NETDUMP */ 6917