1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_var.h> 87 #include <net/if_arp.h> 88 #include <net/ethernet.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #include <net/bpf.h> 93 94 #include <net/if_types.h> 95 #include <net/if_vlan_var.h> 96 97 #include <netinet/in_systm.h> 98 #include <netinet/in.h> 99 #include <netinet/ip.h> 100 #include <netinet/tcp.h> 101 102 #include <machine/bus.h> 103 #include <machine/resource.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include "miidevs.h" 110 #include <dev/mii/brgphyreg.h> 111 112 #ifdef __sparc64__ 113 #include <dev/ofw/ofw_bus.h> 114 #include <dev/ofw/openfirm.h> 115 #include <machine/ofw_machdep.h> 116 #include <machine/ver.h> 117 #endif 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 122 #include <dev/bge/if_bgereg.h> 123 124 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 126 127 MODULE_DEPEND(bge, pci, 1, 1, 1); 128 MODULE_DEPEND(bge, ether, 1, 1, 1); 129 MODULE_DEPEND(bge, miibus, 1, 1, 1); 130 131 /* "device miibus" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. Note: the 136 * spec seems to indicate that the hardware still has Alteon's vendor 137 * ID burned into it, though it will always be overriden by the vendor 138 * ID in the EEPROM. Just to be safe, we cover all possibilities. 139 */ 140 static const struct bge_type { 141 uint16_t bge_vid; 142 uint16_t bge_did; 143 } bge_devs[] = { 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 145 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 146 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 149 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 150 151 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 152 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 238 239 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 240 241 { TC_VENDORID, TC_DEVICEID_3C996 }, 242 243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 244 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 245 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 246 247 { 0, 0 } 248 }; 249 250 static const struct bge_vendor { 251 uint16_t v_id; 252 const char *v_name; 253 } bge_vendors[] = { 254 { ALTEON_VENDORID, "Alteon" }, 255 { ALTIMA_VENDORID, "Altima" }, 256 { APPLE_VENDORID, "Apple" }, 257 { BCOM_VENDORID, "Broadcom" }, 258 { SK_VENDORID, "SysKonnect" }, 259 { TC_VENDORID, "3Com" }, 260 { FJTSU_VENDORID, "Fujitsu" }, 261 262 { 0, NULL } 263 }; 264 265 static const struct bge_revision { 266 uint32_t br_chipid; 267 const char *br_name; 268 } bge_revisions[] = { 269 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 270 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 271 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 272 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 273 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 274 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 275 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 276 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 277 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 278 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 279 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 280 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 281 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 282 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 283 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 284 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 285 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 286 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 287 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 288 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 289 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 290 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 291 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 292 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 293 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 294 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 295 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 296 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 297 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 298 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 299 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 300 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 301 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 302 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 303 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 304 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 305 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 306 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 307 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 308 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 309 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 310 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 311 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 312 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 313 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 314 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 315 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 316 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 317 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 318 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 319 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 320 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 321 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 322 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 323 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 324 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 325 /* 5754 and 5787 share the same ASIC ID */ 326 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 327 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 328 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 329 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 330 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 331 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 332 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 333 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 334 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 335 336 { 0, NULL } 337 }; 338 339 /* 340 * Some defaults for major revisions, so that newer steppings 341 * that we don't know about have a shot at working. 342 */ 343 static const struct bge_revision bge_majorrevs[] = { 344 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 345 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 346 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 347 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 348 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 349 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 350 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 351 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 352 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 353 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 354 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 355 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 356 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 357 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 358 /* 5754 and 5787 share the same ASIC ID */ 359 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 360 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 361 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 362 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 363 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 364 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 365 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 366 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 367 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 368 369 { 0, NULL } 370 }; 371 372 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 373 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 374 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 375 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 376 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 377 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 378 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 379 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 380 381 static uint32_t bge_chipid(device_t); 382 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 383 static const struct bge_revision * bge_lookup_rev(uint32_t); 384 385 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 386 387 static int bge_probe(device_t); 388 static int bge_attach(device_t); 389 static int bge_detach(device_t); 390 static int bge_suspend(device_t); 391 static int bge_resume(device_t); 392 static void bge_release_resources(struct bge_softc *); 393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 394 static int bge_dma_alloc(struct bge_softc *); 395 static void bge_dma_free(struct bge_softc *); 396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 397 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 398 399 static void bge_devinfo(struct bge_softc *); 400 static int bge_mbox_reorder(struct bge_softc *); 401 402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 407 408 static void bge_txeof(struct bge_softc *, uint16_t); 409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 410 static int bge_rxeof(struct bge_softc *, uint16_t, int); 411 412 static void bge_asf_driver_up (struct bge_softc *); 413 static void bge_tick(void *); 414 static void bge_stats_clear_regs(struct bge_softc *); 415 static void bge_stats_update(struct bge_softc *); 416 static void bge_stats_update_regs(struct bge_softc *); 417 static struct mbuf *bge_check_short_dma(struct mbuf *); 418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 419 uint16_t *, uint16_t *); 420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 421 422 static void bge_intr(void *); 423 static int bge_msi_intr(void *); 424 static void bge_intr_task(void *, int); 425 static void bge_start_locked(if_t); 426 static void bge_start(if_t); 427 static int bge_ioctl(if_t, u_long, caddr_t); 428 static void bge_init_locked(struct bge_softc *); 429 static void bge_init(void *); 430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 431 static void bge_stop(struct bge_softc *); 432 static void bge_watchdog(struct bge_softc *); 433 static int bge_shutdown(device_t); 434 static int bge_ifmedia_upd_locked(if_t); 435 static int bge_ifmedia_upd(if_t); 436 static void bge_ifmedia_sts(if_t, struct ifmediareq *); 437 static uint64_t bge_get_counter(if_t, ift_counter); 438 439 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 440 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 441 442 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 443 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 444 445 static void bge_setpromisc(struct bge_softc *); 446 static void bge_setmulti(struct bge_softc *); 447 static void bge_setvlan(struct bge_softc *); 448 449 static __inline void bge_rxreuse_std(struct bge_softc *, int); 450 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 451 static int bge_newbuf_std(struct bge_softc *, int); 452 static int bge_newbuf_jumbo(struct bge_softc *, int); 453 static int bge_init_rx_ring_std(struct bge_softc *); 454 static void bge_free_rx_ring_std(struct bge_softc *); 455 static int bge_init_rx_ring_jumbo(struct bge_softc *); 456 static void bge_free_rx_ring_jumbo(struct bge_softc *); 457 static void bge_free_tx_ring(struct bge_softc *); 458 static int bge_init_tx_ring(struct bge_softc *); 459 460 static int bge_chipinit(struct bge_softc *); 461 static int bge_blockinit(struct bge_softc *); 462 static uint32_t bge_dma_swap_options(struct bge_softc *); 463 464 static int bge_has_eaddr(struct bge_softc *); 465 static uint32_t bge_readmem_ind(struct bge_softc *, int); 466 static void bge_writemem_ind(struct bge_softc *, int, int); 467 static void bge_writembx(struct bge_softc *, int, int); 468 #ifdef notdef 469 static uint32_t bge_readreg_ind(struct bge_softc *, int); 470 #endif 471 static void bge_writemem_direct(struct bge_softc *, int, int); 472 static void bge_writereg_ind(struct bge_softc *, int, int); 473 474 static int bge_miibus_readreg(device_t, int, int); 475 static int bge_miibus_writereg(device_t, int, int, int); 476 static void bge_miibus_statchg(device_t); 477 #ifdef DEVICE_POLLING 478 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 479 #endif 480 481 #define BGE_RESET_SHUTDOWN 0 482 #define BGE_RESET_START 1 483 #define BGE_RESET_SUSPEND 2 484 static void bge_sig_post_reset(struct bge_softc *, int); 485 static void bge_sig_legacy(struct bge_softc *, int); 486 static void bge_sig_pre_reset(struct bge_softc *, int); 487 static void bge_stop_fw(struct bge_softc *); 488 static int bge_reset(struct bge_softc *); 489 static void bge_link_upd(struct bge_softc *); 490 491 static void bge_ape_lock_init(struct bge_softc *); 492 static void bge_ape_read_fw_ver(struct bge_softc *); 493 static int bge_ape_lock(struct bge_softc *, int); 494 static void bge_ape_unlock(struct bge_softc *, int); 495 static void bge_ape_send_event(struct bge_softc *, uint32_t); 496 static void bge_ape_driver_state_change(struct bge_softc *, int); 497 498 /* 499 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 500 * leak information to untrusted users. It is also known to cause alignment 501 * traps on certain architectures. 502 */ 503 #ifdef BGE_REGISTER_DEBUG 504 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 505 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 506 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 507 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 508 #endif 509 static void bge_add_sysctls(struct bge_softc *); 510 static void bge_add_sysctl_stats_regs(struct bge_softc *, 511 struct sysctl_ctx_list *, struct sysctl_oid_list *); 512 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 513 struct sysctl_oid_list *); 514 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 515 516 static device_method_t bge_methods[] = { 517 /* Device interface */ 518 DEVMETHOD(device_probe, bge_probe), 519 DEVMETHOD(device_attach, bge_attach), 520 DEVMETHOD(device_detach, bge_detach), 521 DEVMETHOD(device_shutdown, bge_shutdown), 522 DEVMETHOD(device_suspend, bge_suspend), 523 DEVMETHOD(device_resume, bge_resume), 524 525 /* MII interface */ 526 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 527 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 528 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 529 530 DEVMETHOD_END 531 }; 532 533 static driver_t bge_driver = { 534 "bge", 535 bge_methods, 536 sizeof(struct bge_softc) 537 }; 538 539 static devclass_t bge_devclass; 540 541 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 542 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 543 544 static int bge_allow_asf = 1; 545 546 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 547 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 548 "Allow ASF mode if available"); 549 550 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 551 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 552 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 553 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 554 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 555 556 static int 557 bge_has_eaddr(struct bge_softc *sc) 558 { 559 #ifdef __sparc64__ 560 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 561 device_t dev; 562 uint32_t subvendor; 563 564 dev = sc->bge_dev; 565 566 /* 567 * The on-board BGEs found in sun4u machines aren't fitted with 568 * an EEPROM which means that we have to obtain the MAC address 569 * via OFW and that some tests will always fail. We distinguish 570 * such BGEs by the subvendor ID, which also has to be obtained 571 * from OFW instead of the PCI configuration space as the latter 572 * indicates Broadcom as the subvendor of the netboot interface. 573 * For early Blade 1500 and 2500 we even have to check the OFW 574 * device path as the subvendor ID always defaults to Broadcom 575 * there. 576 */ 577 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 578 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 579 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 580 return (0); 581 memset(buf, 0, sizeof(buf)); 582 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 583 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 584 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 585 return (0); 586 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 587 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 588 return (0); 589 } 590 #endif 591 return (1); 592 } 593 594 static uint32_t 595 bge_readmem_ind(struct bge_softc *sc, int off) 596 { 597 device_t dev; 598 uint32_t val; 599 600 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 601 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 602 return (0); 603 604 dev = sc->bge_dev; 605 606 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 607 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 608 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 609 return (val); 610 } 611 612 static void 613 bge_writemem_ind(struct bge_softc *sc, int off, int val) 614 { 615 device_t dev; 616 617 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 618 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 619 return; 620 621 dev = sc->bge_dev; 622 623 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 624 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 625 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 626 } 627 628 #ifdef notdef 629 static uint32_t 630 bge_readreg_ind(struct bge_softc *sc, int off) 631 { 632 device_t dev; 633 634 dev = sc->bge_dev; 635 636 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 637 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 638 } 639 #endif 640 641 static void 642 bge_writereg_ind(struct bge_softc *sc, int off, int val) 643 { 644 device_t dev; 645 646 dev = sc->bge_dev; 647 648 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 649 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 650 } 651 652 static void 653 bge_writemem_direct(struct bge_softc *sc, int off, int val) 654 { 655 CSR_WRITE_4(sc, off, val); 656 } 657 658 static void 659 bge_writembx(struct bge_softc *sc, int off, int val) 660 { 661 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 662 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 663 664 CSR_WRITE_4(sc, off, val); 665 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 666 CSR_READ_4(sc, off); 667 } 668 669 /* 670 * Clear all stale locks and select the lock for this driver instance. 671 */ 672 static void 673 bge_ape_lock_init(struct bge_softc *sc) 674 { 675 uint32_t bit, regbase; 676 int i; 677 678 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 679 regbase = BGE_APE_LOCK_GRANT; 680 else 681 regbase = BGE_APE_PER_LOCK_GRANT; 682 683 /* Clear any stale locks. */ 684 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 685 switch (i) { 686 case BGE_APE_LOCK_PHY0: 687 case BGE_APE_LOCK_PHY1: 688 case BGE_APE_LOCK_PHY2: 689 case BGE_APE_LOCK_PHY3: 690 bit = BGE_APE_LOCK_GRANT_DRIVER0; 691 break; 692 default: 693 if (sc->bge_func_addr == 0) 694 bit = BGE_APE_LOCK_GRANT_DRIVER0; 695 else 696 bit = (1 << sc->bge_func_addr); 697 } 698 APE_WRITE_4(sc, regbase + 4 * i, bit); 699 } 700 701 /* Select the PHY lock based on the device's function number. */ 702 switch (sc->bge_func_addr) { 703 case 0: 704 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 705 break; 706 case 1: 707 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 708 break; 709 case 2: 710 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 711 break; 712 case 3: 713 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 714 break; 715 default: 716 device_printf(sc->bge_dev, 717 "PHY lock not supported on this function\n"); 718 } 719 } 720 721 /* 722 * Check for APE firmware, set flags, and print version info. 723 */ 724 static void 725 bge_ape_read_fw_ver(struct bge_softc *sc) 726 { 727 const char *fwtype; 728 uint32_t apedata, features; 729 730 /* Check for a valid APE signature in shared memory. */ 731 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 732 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 733 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 734 return; 735 } 736 737 /* Check if APE firmware is running. */ 738 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 739 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 740 device_printf(sc->bge_dev, "APE signature found " 741 "but FW status not ready! 0x%08x\n", apedata); 742 return; 743 } 744 745 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 746 747 /* Fetch the APE firwmare type and version. */ 748 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 749 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 750 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 751 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 752 fwtype = "NCSI"; 753 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 754 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 755 fwtype = "DASH"; 756 } else 757 fwtype = "UNKN"; 758 759 /* Print the APE firmware version. */ 760 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 761 fwtype, 762 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 763 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 764 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 765 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 766 } 767 768 static int 769 bge_ape_lock(struct bge_softc *sc, int locknum) 770 { 771 uint32_t bit, gnt, req, status; 772 int i, off; 773 774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 775 return (0); 776 777 /* Lock request/grant registers have different bases. */ 778 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 779 req = BGE_APE_LOCK_REQ; 780 gnt = BGE_APE_LOCK_GRANT; 781 } else { 782 req = BGE_APE_PER_LOCK_REQ; 783 gnt = BGE_APE_PER_LOCK_GRANT; 784 } 785 786 off = 4 * locknum; 787 788 switch (locknum) { 789 case BGE_APE_LOCK_GPIO: 790 /* Lock required when using GPIO. */ 791 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 792 return (0); 793 if (sc->bge_func_addr == 0) 794 bit = BGE_APE_LOCK_REQ_DRIVER0; 795 else 796 bit = (1 << sc->bge_func_addr); 797 break; 798 case BGE_APE_LOCK_GRC: 799 /* Lock required to reset the device. */ 800 if (sc->bge_func_addr == 0) 801 bit = BGE_APE_LOCK_REQ_DRIVER0; 802 else 803 bit = (1 << sc->bge_func_addr); 804 break; 805 case BGE_APE_LOCK_MEM: 806 /* Lock required when accessing certain APE memory. */ 807 if (sc->bge_func_addr == 0) 808 bit = BGE_APE_LOCK_REQ_DRIVER0; 809 else 810 bit = (1 << sc->bge_func_addr); 811 break; 812 case BGE_APE_LOCK_PHY0: 813 case BGE_APE_LOCK_PHY1: 814 case BGE_APE_LOCK_PHY2: 815 case BGE_APE_LOCK_PHY3: 816 /* Lock required when accessing PHYs. */ 817 bit = BGE_APE_LOCK_REQ_DRIVER0; 818 break; 819 default: 820 return (EINVAL); 821 } 822 823 /* Request a lock. */ 824 APE_WRITE_4(sc, req + off, bit); 825 826 /* Wait up to 1 second to acquire lock. */ 827 for (i = 0; i < 20000; i++) { 828 status = APE_READ_4(sc, gnt + off); 829 if (status == bit) 830 break; 831 DELAY(50); 832 } 833 834 /* Handle any errors. */ 835 if (status != bit) { 836 device_printf(sc->bge_dev, "APE lock %d request failed! " 837 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 838 locknum, req + off, bit & 0xFFFF, gnt + off, 839 status & 0xFFFF); 840 /* Revoke the lock request. */ 841 APE_WRITE_4(sc, gnt + off, bit); 842 return (EBUSY); 843 } 844 845 return (0); 846 } 847 848 static void 849 bge_ape_unlock(struct bge_softc *sc, int locknum) 850 { 851 uint32_t bit, gnt; 852 int off; 853 854 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 855 return; 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 858 gnt = BGE_APE_LOCK_GRANT; 859 else 860 gnt = BGE_APE_PER_LOCK_GRANT; 861 862 off = 4 * locknum; 863 864 switch (locknum) { 865 case BGE_APE_LOCK_GPIO: 866 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 867 return; 868 if (sc->bge_func_addr == 0) 869 bit = BGE_APE_LOCK_GRANT_DRIVER0; 870 else 871 bit = (1 << sc->bge_func_addr); 872 break; 873 case BGE_APE_LOCK_GRC: 874 if (sc->bge_func_addr == 0) 875 bit = BGE_APE_LOCK_GRANT_DRIVER0; 876 else 877 bit = (1 << sc->bge_func_addr); 878 break; 879 case BGE_APE_LOCK_MEM: 880 if (sc->bge_func_addr == 0) 881 bit = BGE_APE_LOCK_GRANT_DRIVER0; 882 else 883 bit = (1 << sc->bge_func_addr); 884 break; 885 case BGE_APE_LOCK_PHY0: 886 case BGE_APE_LOCK_PHY1: 887 case BGE_APE_LOCK_PHY2: 888 case BGE_APE_LOCK_PHY3: 889 bit = BGE_APE_LOCK_GRANT_DRIVER0; 890 break; 891 default: 892 return; 893 } 894 895 APE_WRITE_4(sc, gnt + off, bit); 896 } 897 898 /* 899 * Send an event to the APE firmware. 900 */ 901 static void 902 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 903 { 904 uint32_t apedata; 905 int i; 906 907 /* NCSI does not support APE events. */ 908 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 909 return; 910 911 /* Wait up to 1ms for APE to service previous event. */ 912 for (i = 10; i > 0; i--) { 913 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 914 break; 915 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 916 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 917 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 918 BGE_APE_EVENT_STATUS_EVENT_PENDING); 919 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 920 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 921 break; 922 } 923 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 924 DELAY(100); 925 } 926 if (i == 0) 927 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 928 event); 929 } 930 931 static void 932 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 933 { 934 uint32_t apedata, event; 935 936 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 937 return; 938 939 switch (kind) { 940 case BGE_RESET_START: 941 /* If this is the first load, clear the load counter. */ 942 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 943 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 944 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 945 else { 946 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 947 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 948 } 949 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 950 BGE_APE_HOST_SEG_SIG_MAGIC); 951 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 952 BGE_APE_HOST_SEG_LEN_MAGIC); 953 954 /* Add some version info if bge(4) supports it. */ 955 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 956 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 957 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 958 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 959 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 960 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 961 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 962 BGE_APE_HOST_DRVR_STATE_START); 963 event = BGE_APE_EVENT_STATUS_STATE_START; 964 break; 965 case BGE_RESET_SHUTDOWN: 966 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 967 BGE_APE_HOST_DRVR_STATE_UNLOAD); 968 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 969 break; 970 case BGE_RESET_SUSPEND: 971 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 972 break; 973 default: 974 return; 975 } 976 977 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 978 BGE_APE_EVENT_STATUS_STATE_CHNGE); 979 } 980 981 /* 982 * Map a single buffer address. 983 */ 984 985 static void 986 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 987 { 988 struct bge_dmamap_arg *ctx; 989 990 if (error) 991 return; 992 993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 994 995 ctx = arg; 996 ctx->bge_busaddr = segs->ds_addr; 997 } 998 999 static uint8_t 1000 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1001 { 1002 uint32_t access, byte = 0; 1003 int i; 1004 1005 /* Lock. */ 1006 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1007 for (i = 0; i < 8000; i++) { 1008 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1009 break; 1010 DELAY(20); 1011 } 1012 if (i == 8000) 1013 return (1); 1014 1015 /* Enable access. */ 1016 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1017 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1018 1019 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1020 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1021 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1022 DELAY(10); 1023 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1024 DELAY(10); 1025 break; 1026 } 1027 } 1028 1029 if (i == BGE_TIMEOUT * 10) { 1030 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1031 return (1); 1032 } 1033 1034 /* Get result. */ 1035 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1036 1037 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1038 1039 /* Disable access. */ 1040 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1041 1042 /* Unlock. */ 1043 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1044 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1045 1046 return (0); 1047 } 1048 1049 /* 1050 * Read a sequence of bytes from NVRAM. 1051 */ 1052 static int 1053 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1054 { 1055 int err = 0, i; 1056 uint8_t byte = 0; 1057 1058 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1059 return (1); 1060 1061 for (i = 0; i < cnt; i++) { 1062 err = bge_nvram_getbyte(sc, off + i, &byte); 1063 if (err) 1064 break; 1065 *(dest + i) = byte; 1066 } 1067 1068 return (err ? 1 : 0); 1069 } 1070 1071 /* 1072 * Read a byte of data stored in the EEPROM at address 'addr.' The 1073 * BCM570x supports both the traditional bitbang interface and an 1074 * auto access interface for reading the EEPROM. We use the auto 1075 * access method. 1076 */ 1077 static uint8_t 1078 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1079 { 1080 int i; 1081 uint32_t byte = 0; 1082 1083 /* 1084 * Enable use of auto EEPROM access so we can avoid 1085 * having to use the bitbang method. 1086 */ 1087 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1088 1089 /* Reset the EEPROM, load the clock period. */ 1090 CSR_WRITE_4(sc, BGE_EE_ADDR, 1091 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1092 DELAY(20); 1093 1094 /* Issue the read EEPROM command. */ 1095 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1096 1097 /* Wait for completion */ 1098 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1099 DELAY(10); 1100 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1101 break; 1102 } 1103 1104 if (i == BGE_TIMEOUT * 10) { 1105 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1106 return (1); 1107 } 1108 1109 /* Get result. */ 1110 byte = CSR_READ_4(sc, BGE_EE_DATA); 1111 1112 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1113 1114 return (0); 1115 } 1116 1117 /* 1118 * Read a sequence of bytes from the EEPROM. 1119 */ 1120 static int 1121 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1122 { 1123 int i, error = 0; 1124 uint8_t byte = 0; 1125 1126 for (i = 0; i < cnt; i++) { 1127 error = bge_eeprom_getbyte(sc, off + i, &byte); 1128 if (error) 1129 break; 1130 *(dest + i) = byte; 1131 } 1132 1133 return (error ? 1 : 0); 1134 } 1135 1136 static int 1137 bge_miibus_readreg(device_t dev, int phy, int reg) 1138 { 1139 struct bge_softc *sc; 1140 uint32_t val; 1141 int i; 1142 1143 sc = device_get_softc(dev); 1144 1145 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1146 return (0); 1147 1148 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1149 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1150 CSR_WRITE_4(sc, BGE_MI_MODE, 1151 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1152 DELAY(80); 1153 } 1154 1155 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1156 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1157 1158 /* Poll for the PHY register access to complete. */ 1159 for (i = 0; i < BGE_TIMEOUT; i++) { 1160 DELAY(10); 1161 val = CSR_READ_4(sc, BGE_MI_COMM); 1162 if ((val & BGE_MICOMM_BUSY) == 0) { 1163 DELAY(5); 1164 val = CSR_READ_4(sc, BGE_MI_COMM); 1165 break; 1166 } 1167 } 1168 1169 if (i == BGE_TIMEOUT) { 1170 device_printf(sc->bge_dev, 1171 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1172 phy, reg, val); 1173 val = 0; 1174 } 1175 1176 /* Restore the autopoll bit if necessary. */ 1177 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1178 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1179 DELAY(80); 1180 } 1181 1182 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1183 1184 if (val & BGE_MICOMM_READFAIL) 1185 return (0); 1186 1187 return (val & 0xFFFF); 1188 } 1189 1190 static int 1191 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1192 { 1193 struct bge_softc *sc; 1194 int i; 1195 1196 sc = device_get_softc(dev); 1197 1198 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1199 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1200 return (0); 1201 1202 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1203 return (0); 1204 1205 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1206 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1207 CSR_WRITE_4(sc, BGE_MI_MODE, 1208 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1209 DELAY(80); 1210 } 1211 1212 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1213 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1214 1215 for (i = 0; i < BGE_TIMEOUT; i++) { 1216 DELAY(10); 1217 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1218 DELAY(5); 1219 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1220 break; 1221 } 1222 } 1223 1224 /* Restore the autopoll bit if necessary. */ 1225 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1226 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1227 DELAY(80); 1228 } 1229 1230 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1231 1232 if (i == BGE_TIMEOUT) 1233 device_printf(sc->bge_dev, 1234 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1235 phy, reg, val); 1236 1237 return (0); 1238 } 1239 1240 static void 1241 bge_miibus_statchg(device_t dev) 1242 { 1243 struct bge_softc *sc; 1244 struct mii_data *mii; 1245 uint32_t mac_mode, rx_mode, tx_mode; 1246 1247 sc = device_get_softc(dev); 1248 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1249 return; 1250 mii = device_get_softc(sc->bge_miibus); 1251 1252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1253 (IFM_ACTIVE | IFM_AVALID)) { 1254 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1255 case IFM_10_T: 1256 case IFM_100_TX: 1257 sc->bge_link = 1; 1258 break; 1259 case IFM_1000_T: 1260 case IFM_1000_SX: 1261 case IFM_2500_SX: 1262 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1263 sc->bge_link = 1; 1264 else 1265 sc->bge_link = 0; 1266 break; 1267 default: 1268 sc->bge_link = 0; 1269 break; 1270 } 1271 } else 1272 sc->bge_link = 0; 1273 if (sc->bge_link == 0) 1274 return; 1275 1276 /* 1277 * APE firmware touches these registers to keep the MAC 1278 * connected to the outside world. Try to keep the 1279 * accesses atomic. 1280 */ 1281 1282 /* Set the port mode (MII/GMII) to match the link speed. */ 1283 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1284 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1285 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1286 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1287 1288 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1289 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1290 mac_mode |= BGE_PORTMODE_GMII; 1291 else 1292 mac_mode |= BGE_PORTMODE_MII; 1293 1294 /* Set MAC flow control behavior to match link flow control settings. */ 1295 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1296 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1299 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1300 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1301 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1302 } else 1303 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1304 1305 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1306 DELAY(40); 1307 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1308 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1309 } 1310 1311 /* 1312 * Intialize a standard receive ring descriptor. 1313 */ 1314 static int 1315 bge_newbuf_std(struct bge_softc *sc, int i) 1316 { 1317 struct mbuf *m; 1318 struct bge_rx_bd *r; 1319 bus_dma_segment_t segs[1]; 1320 bus_dmamap_t map; 1321 int error, nsegs; 1322 1323 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1324 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1325 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1326 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1327 if (m == NULL) 1328 return (ENOBUFS); 1329 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1330 } else { 1331 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1332 if (m == NULL) 1333 return (ENOBUFS); 1334 m->m_len = m->m_pkthdr.len = MCLBYTES; 1335 } 1336 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1337 m_adj(m, ETHER_ALIGN); 1338 1339 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1340 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1341 if (error != 0) { 1342 m_freem(m); 1343 return (error); 1344 } 1345 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1346 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1347 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1349 sc->bge_cdata.bge_rx_std_dmamap[i]); 1350 } 1351 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1352 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1353 sc->bge_cdata.bge_rx_std_sparemap = map; 1354 sc->bge_cdata.bge_rx_std_chain[i] = m; 1355 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1356 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1357 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1358 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1359 r->bge_flags = BGE_RXBDFLAG_END; 1360 r->bge_len = segs[0].ds_len; 1361 r->bge_idx = i; 1362 1363 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1364 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1365 1366 return (0); 1367 } 1368 1369 /* 1370 * Initialize a jumbo receive ring descriptor. This allocates 1371 * a jumbo buffer from the pool managed internally by the driver. 1372 */ 1373 static int 1374 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1375 { 1376 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1377 bus_dmamap_t map; 1378 struct bge_extrx_bd *r; 1379 struct mbuf *m; 1380 int error, nsegs; 1381 1382 MGETHDR(m, M_NOWAIT, MT_DATA); 1383 if (m == NULL) 1384 return (ENOBUFS); 1385 1386 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) { 1387 m_freem(m); 1388 return (ENOBUFS); 1389 } 1390 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1391 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1392 m_adj(m, ETHER_ALIGN); 1393 1394 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1395 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1396 if (error != 0) { 1397 m_freem(m); 1398 return (error); 1399 } 1400 1401 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1402 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1403 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1404 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1405 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1406 } 1407 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1409 sc->bge_cdata.bge_rx_jumbo_sparemap; 1410 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1411 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1412 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1413 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1416 1417 /* 1418 * Fill in the extended RX buffer descriptor. 1419 */ 1420 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1421 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1422 r->bge_idx = i; 1423 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1424 switch (nsegs) { 1425 case 4: 1426 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1427 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1428 r->bge_len3 = segs[3].ds_len; 1429 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1430 case 3: 1431 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1432 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1433 r->bge_len2 = segs[2].ds_len; 1434 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1435 case 2: 1436 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1437 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1438 r->bge_len1 = segs[1].ds_len; 1439 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1440 case 1: 1441 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1442 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1443 r->bge_len0 = segs[0].ds_len; 1444 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1445 break; 1446 default: 1447 panic("%s: %d segments\n", __func__, nsegs); 1448 } 1449 1450 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1451 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1452 1453 return (0); 1454 } 1455 1456 static int 1457 bge_init_rx_ring_std(struct bge_softc *sc) 1458 { 1459 int error, i; 1460 1461 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1462 sc->bge_std = 0; 1463 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1464 if ((error = bge_newbuf_std(sc, i)) != 0) 1465 return (error); 1466 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1467 } 1468 1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1470 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1471 1472 sc->bge_std = 0; 1473 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1474 1475 return (0); 1476 } 1477 1478 static void 1479 bge_free_rx_ring_std(struct bge_softc *sc) 1480 { 1481 int i; 1482 1483 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1484 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1485 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1486 sc->bge_cdata.bge_rx_std_dmamap[i], 1487 BUS_DMASYNC_POSTREAD); 1488 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1489 sc->bge_cdata.bge_rx_std_dmamap[i]); 1490 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1491 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1492 } 1493 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1494 sizeof(struct bge_rx_bd)); 1495 } 1496 } 1497 1498 static int 1499 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1500 { 1501 struct bge_rcb *rcb; 1502 int error, i; 1503 1504 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1505 sc->bge_jumbo = 0; 1506 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1507 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1508 return (error); 1509 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1510 } 1511 1512 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1513 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1514 1515 sc->bge_jumbo = 0; 1516 1517 /* Enable the jumbo receive producer ring. */ 1518 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1519 rcb->bge_maxlen_flags = 1520 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1522 1523 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1524 1525 return (0); 1526 } 1527 1528 static void 1529 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1530 { 1531 int i; 1532 1533 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1534 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1535 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1536 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1537 BUS_DMASYNC_POSTREAD); 1538 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1539 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1540 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1541 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1542 } 1543 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1544 sizeof(struct bge_extrx_bd)); 1545 } 1546 } 1547 1548 static void 1549 bge_free_tx_ring(struct bge_softc *sc) 1550 { 1551 int i; 1552 1553 if (sc->bge_ldata.bge_tx_ring == NULL) 1554 return; 1555 1556 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1557 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1558 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1559 sc->bge_cdata.bge_tx_dmamap[i], 1560 BUS_DMASYNC_POSTWRITE); 1561 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1562 sc->bge_cdata.bge_tx_dmamap[i]); 1563 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1564 sc->bge_cdata.bge_tx_chain[i] = NULL; 1565 } 1566 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1567 sizeof(struct bge_tx_bd)); 1568 } 1569 } 1570 1571 static int 1572 bge_init_tx_ring(struct bge_softc *sc) 1573 { 1574 sc->bge_txcnt = 0; 1575 sc->bge_tx_saved_considx = 0; 1576 1577 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1578 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1579 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1580 1581 /* Initialize transmit producer index for host-memory send ring. */ 1582 sc->bge_tx_prodidx = 0; 1583 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1584 1585 /* 5700 b2 errata */ 1586 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1587 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1588 1589 /* NIC-memory send ring not used; initialize to zero. */ 1590 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1591 /* 5700 b2 errata */ 1592 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1593 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1594 1595 return (0); 1596 } 1597 1598 static void 1599 bge_setpromisc(struct bge_softc *sc) 1600 { 1601 if_t ifp; 1602 1603 BGE_LOCK_ASSERT(sc); 1604 1605 ifp = sc->bge_ifp; 1606 1607 /* Enable or disable promiscuous mode as needed. */ 1608 if (if_getflags(ifp) & IFF_PROMISC) 1609 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1610 else 1611 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1612 } 1613 1614 static void 1615 bge_setmulti(struct bge_softc *sc) 1616 { 1617 if_t ifp; 1618 int mc_count = 0; 1619 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1620 int h, i, mcnt; 1621 unsigned char *mta; 1622 1623 BGE_LOCK_ASSERT(sc); 1624 1625 ifp = sc->bge_ifp; 1626 1627 mc_count = if_multiaddr_count(ifp, -1); 1628 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * 1629 mc_count, M_DEVBUF, M_NOWAIT); 1630 1631 if(mta == NULL) { 1632 device_printf(sc->bge_dev, 1633 "Failed to allocated temp mcast list\n"); 1634 return; 1635 } 1636 1637 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 1638 for (i = 0; i < 4; i++) 1639 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1640 return; 1641 } 1642 1643 /* First, zot all the existing filters. */ 1644 for (i = 0; i < 4; i++) 1645 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1646 1647 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 1648 for(i = 0; i < mcnt; i++) { 1649 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 1650 ETHER_ADDR_LEN) & 0x7F; 1651 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1652 } 1653 1654 for (i = 0; i < 4; i++) 1655 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1656 1657 free(mta, M_DEVBUF); 1658 } 1659 1660 static void 1661 bge_setvlan(struct bge_softc *sc) 1662 { 1663 if_t ifp; 1664 1665 BGE_LOCK_ASSERT(sc); 1666 1667 ifp = sc->bge_ifp; 1668 1669 /* Enable or disable VLAN tag stripping as needed. */ 1670 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1671 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1672 else 1673 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1674 } 1675 1676 static void 1677 bge_sig_pre_reset(struct bge_softc *sc, int type) 1678 { 1679 1680 /* 1681 * Some chips don't like this so only do this if ASF is enabled 1682 */ 1683 if (sc->bge_asf_mode) 1684 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1685 1686 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1687 switch (type) { 1688 case BGE_RESET_START: 1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1690 BGE_FW_DRV_STATE_START); 1691 break; 1692 case BGE_RESET_SHUTDOWN: 1693 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1694 BGE_FW_DRV_STATE_UNLOAD); 1695 break; 1696 case BGE_RESET_SUSPEND: 1697 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1698 BGE_FW_DRV_STATE_SUSPEND); 1699 break; 1700 } 1701 } 1702 1703 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1704 bge_ape_driver_state_change(sc, type); 1705 } 1706 1707 static void 1708 bge_sig_post_reset(struct bge_softc *sc, int type) 1709 { 1710 1711 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1712 switch (type) { 1713 case BGE_RESET_START: 1714 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1715 BGE_FW_DRV_STATE_START_DONE); 1716 /* START DONE */ 1717 break; 1718 case BGE_RESET_SHUTDOWN: 1719 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1720 BGE_FW_DRV_STATE_UNLOAD_DONE); 1721 break; 1722 } 1723 } 1724 if (type == BGE_RESET_SHUTDOWN) 1725 bge_ape_driver_state_change(sc, type); 1726 } 1727 1728 static void 1729 bge_sig_legacy(struct bge_softc *sc, int type) 1730 { 1731 1732 if (sc->bge_asf_mode) { 1733 switch (type) { 1734 case BGE_RESET_START: 1735 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1736 BGE_FW_DRV_STATE_START); 1737 break; 1738 case BGE_RESET_SHUTDOWN: 1739 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1740 BGE_FW_DRV_STATE_UNLOAD); 1741 break; 1742 } 1743 } 1744 } 1745 1746 static void 1747 bge_stop_fw(struct bge_softc *sc) 1748 { 1749 int i; 1750 1751 if (sc->bge_asf_mode) { 1752 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1753 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1754 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1755 1756 for (i = 0; i < 100; i++ ) { 1757 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1758 BGE_RX_CPU_DRV_EVENT)) 1759 break; 1760 DELAY(10); 1761 } 1762 } 1763 } 1764 1765 static uint32_t 1766 bge_dma_swap_options(struct bge_softc *sc) 1767 { 1768 uint32_t dma_options; 1769 1770 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1771 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1772 #if BYTE_ORDER == BIG_ENDIAN 1773 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1774 #endif 1775 return (dma_options); 1776 } 1777 1778 /* 1779 * Do endian, PCI and DMA initialization. 1780 */ 1781 static int 1782 bge_chipinit(struct bge_softc *sc) 1783 { 1784 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1785 uint16_t val; 1786 int i; 1787 1788 /* Set endianness before we access any non-PCI registers. */ 1789 misc_ctl = BGE_INIT; 1790 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1791 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1792 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1793 1794 /* 1795 * Clear the MAC statistics block in the NIC's 1796 * internal memory. 1797 */ 1798 for (i = BGE_STATS_BLOCK; 1799 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1800 BGE_MEMWIN_WRITE(sc, i, 0); 1801 1802 for (i = BGE_STATUS_BLOCK; 1803 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1804 BGE_MEMWIN_WRITE(sc, i, 0); 1805 1806 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1807 /* 1808 * Fix data corruption caused by non-qword write with WB. 1809 * Fix master abort in PCI mode. 1810 * Fix PCI latency timer. 1811 */ 1812 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1813 val |= (1 << 10) | (1 << 12) | (1 << 13); 1814 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1815 } 1816 1817 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1818 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1819 /* 1820 * For the 57766 and non Ax versions of 57765, bootcode 1821 * needs to setup the PCIE Fast Training Sequence (FTS) 1822 * value to prevent transmit hangs. 1823 */ 1824 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1825 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1826 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1827 BGE_CPMU_PADRNG_CTL_RDIV2); 1828 } 1829 } 1830 1831 /* 1832 * Set up the PCI DMA control register. 1833 */ 1834 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1835 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1836 if (sc->bge_flags & BGE_FLAG_PCIE) { 1837 if (sc->bge_mps >= 256) 1838 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1839 else 1840 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1841 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1842 if (BGE_IS_5714_FAMILY(sc)) { 1843 /* 256 bytes for read and write. */ 1844 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1845 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1846 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1847 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1848 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1849 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1850 /* 1851 * In the BCM5703, the DMA read watermark should 1852 * be set to less than or equal to the maximum 1853 * memory read byte count of the PCI-X command 1854 * register. 1855 */ 1856 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1857 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1858 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1859 /* 1536 bytes for read, 384 bytes for write. */ 1860 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1861 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1862 } else { 1863 /* 384 bytes for read and write. */ 1864 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1865 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1866 0x0F; 1867 } 1868 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1869 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1870 uint32_t tmp; 1871 1872 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1873 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1874 if (tmp == 6 || tmp == 7) 1875 dma_rw_ctl |= 1876 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1877 1878 /* Set PCI-X DMA write workaround. */ 1879 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1880 } 1881 } else { 1882 /* Conventional PCI bus: 256 bytes for read and write. */ 1883 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1884 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1885 1886 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1887 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1888 dma_rw_ctl |= 0x0F; 1889 } 1890 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1891 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1892 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1893 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1894 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1895 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1896 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1897 if (BGE_IS_5717_PLUS(sc)) { 1898 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1899 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1900 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1901 /* 1902 * Enable HW workaround for controllers that misinterpret 1903 * a status tag update and leave interrupts permanently 1904 * disabled. 1905 */ 1906 if (!BGE_IS_57765_PLUS(sc) && 1907 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1908 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1909 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1910 } 1911 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1912 1913 /* 1914 * Set up general mode register. 1915 */ 1916 mode_ctl = bge_dma_swap_options(sc); 1917 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1918 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1919 /* Retain Host-2-BMC settings written by APE firmware. */ 1920 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1921 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1922 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1923 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1924 } 1925 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1926 BGE_MODECTL_TX_NO_PHDR_CSUM; 1927 1928 /* 1929 * BCM5701 B5 have a bug causing data corruption when using 1930 * 64-bit DMA reads, which can be terminated early and then 1931 * completed later as 32-bit accesses, in combination with 1932 * certain bridges. 1933 */ 1934 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1935 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1936 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1937 1938 /* 1939 * Tell the firmware the driver is running 1940 */ 1941 if (sc->bge_asf_mode & ASF_STACKUP) 1942 mode_ctl |= BGE_MODECTL_STACKUP; 1943 1944 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1945 1946 /* 1947 * Disable memory write invalidate. Apparently it is not supported 1948 * properly by these devices. 1949 */ 1950 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1951 1952 /* Set the timer prescaler (always 66 MHz). */ 1953 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1954 1955 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1956 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1957 DELAY(40); /* XXX */ 1958 1959 /* Put PHY into ready state */ 1960 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1961 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1962 DELAY(40); 1963 } 1964 1965 return (0); 1966 } 1967 1968 static int 1969 bge_blockinit(struct bge_softc *sc) 1970 { 1971 struct bge_rcb *rcb; 1972 bus_size_t vrcb; 1973 bge_hostaddr taddr; 1974 uint32_t dmactl, rdmareg, val; 1975 int i, limit; 1976 1977 /* 1978 * Initialize the memory window pointer register so that 1979 * we can access the first 32K of internal NIC RAM. This will 1980 * allow us to set up the TX send ring RCBs and the RX return 1981 * ring RCBs, plus other things which live in NIC memory. 1982 */ 1983 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1984 1985 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1986 1987 if (!(BGE_IS_5705_PLUS(sc))) { 1988 /* Configure mbuf memory pool */ 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1990 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1992 else 1993 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1994 1995 /* Configure DMA resource pool */ 1996 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1997 BGE_DMA_DESCRIPTORS); 1998 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1999 } 2000 2001 /* Configure mbuf pool watermarks */ 2002 if (BGE_IS_5717_PLUS(sc)) { 2003 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2004 if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 2005 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2007 } else { 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2010 } 2011 } else if (!BGE_IS_5705_PLUS(sc)) { 2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2015 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2018 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2019 } else { 2020 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2021 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2022 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2023 } 2024 2025 /* Configure DMA resource watermarks */ 2026 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2027 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2028 2029 /* Enable buffer manager */ 2030 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2031 /* 2032 * Change the arbitration algorithm of TXMBUF read request to 2033 * round-robin instead of priority based for BCM5719. When 2034 * TXFIFO is almost empty, RDMA will hold its request until 2035 * TXFIFO is not almost empty. 2036 */ 2037 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2038 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2039 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2040 2041 /* Poll for buffer manager start indication */ 2042 for (i = 0; i < BGE_TIMEOUT; i++) { 2043 DELAY(10); 2044 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2045 break; 2046 } 2047 2048 if (i == BGE_TIMEOUT) { 2049 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2050 return (ENXIO); 2051 } 2052 2053 /* Enable flow-through queues */ 2054 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2055 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2056 2057 /* Wait until queue initialization is complete */ 2058 for (i = 0; i < BGE_TIMEOUT; i++) { 2059 DELAY(10); 2060 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2061 break; 2062 } 2063 2064 if (i == BGE_TIMEOUT) { 2065 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2066 return (ENXIO); 2067 } 2068 2069 /* 2070 * Summary of rings supported by the controller: 2071 * 2072 * Standard Receive Producer Ring 2073 * - This ring is used to feed receive buffers for "standard" 2074 * sized frames (typically 1536 bytes) to the controller. 2075 * 2076 * Jumbo Receive Producer Ring 2077 * - This ring is used to feed receive buffers for jumbo sized 2078 * frames (i.e. anything bigger than the "standard" frames) 2079 * to the controller. 2080 * 2081 * Mini Receive Producer Ring 2082 * - This ring is used to feed receive buffers for "mini" 2083 * sized frames to the controller. 2084 * - This feature required external memory for the controller 2085 * but was never used in a production system. Should always 2086 * be disabled. 2087 * 2088 * Receive Return Ring 2089 * - After the controller has placed an incoming frame into a 2090 * receive buffer that buffer is moved into a receive return 2091 * ring. The driver is then responsible to passing the 2092 * buffer up to the stack. Many versions of the controller 2093 * support multiple RR rings. 2094 * 2095 * Send Ring 2096 * - This ring is used for outgoing frames. Many versions of 2097 * the controller support multiple send rings. 2098 */ 2099 2100 /* Initialize the standard receive producer ring control block. */ 2101 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2102 rcb->bge_hostaddr.bge_addr_lo = 2103 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2104 rcb->bge_hostaddr.bge_addr_hi = 2105 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2106 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2107 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2108 if (BGE_IS_5717_PLUS(sc)) { 2109 /* 2110 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2111 * Bits 15-2 : Maximum RX frame size 2112 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2113 * Bit 0 : Reserved 2114 */ 2115 rcb->bge_maxlen_flags = 2116 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2117 } else if (BGE_IS_5705_PLUS(sc)) { 2118 /* 2119 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2120 * Bits 15-2 : Reserved (should be 0) 2121 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2122 * Bit 0 : Reserved 2123 */ 2124 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2125 } else { 2126 /* 2127 * Ring size is always XXX entries 2128 * Bits 31-16: Maximum RX frame size 2129 * Bits 15-2 : Reserved (should be 0) 2130 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2131 * Bit 0 : Reserved 2132 */ 2133 rcb->bge_maxlen_flags = 2134 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2135 } 2136 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2137 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2138 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2139 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2140 else 2141 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2142 /* Write the standard receive producer ring control block. */ 2143 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2144 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2145 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2146 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2147 2148 /* Reset the standard receive producer ring producer index. */ 2149 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2150 2151 /* 2152 * Initialize the jumbo RX producer ring control 2153 * block. We set the 'ring disabled' bit in the 2154 * flags field until we're actually ready to start 2155 * using this ring (i.e. once we set the MTU 2156 * high enough to require it). 2157 */ 2158 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2159 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2160 /* Get the jumbo receive producer ring RCB parameters. */ 2161 rcb->bge_hostaddr.bge_addr_lo = 2162 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2163 rcb->bge_hostaddr.bge_addr_hi = 2164 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2165 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2166 sc->bge_cdata.bge_rx_jumbo_ring_map, 2167 BUS_DMASYNC_PREREAD); 2168 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2169 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2170 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2171 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2172 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2173 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2174 else 2175 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2176 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2177 rcb->bge_hostaddr.bge_addr_hi); 2178 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2179 rcb->bge_hostaddr.bge_addr_lo); 2180 /* Program the jumbo receive producer ring RCB parameters. */ 2181 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2182 rcb->bge_maxlen_flags); 2183 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2184 /* Reset the jumbo receive producer ring producer index. */ 2185 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2186 } 2187 2188 /* Disable the mini receive producer ring RCB. */ 2189 if (BGE_IS_5700_FAMILY(sc)) { 2190 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2191 rcb->bge_maxlen_flags = 2192 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2193 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2194 rcb->bge_maxlen_flags); 2195 /* Reset the mini receive producer ring producer index. */ 2196 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2197 } 2198 2199 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2200 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2201 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2202 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2203 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2204 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2205 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2206 } 2207 /* 2208 * The BD ring replenish thresholds control how often the 2209 * hardware fetches new BD's from the producer rings in host 2210 * memory. Setting the value too low on a busy system can 2211 * starve the hardware and recue the throughpout. 2212 * 2213 * Set the BD ring replentish thresholds. The recommended 2214 * values are 1/8th the number of descriptors allocated to 2215 * each ring. 2216 * XXX The 5754 requires a lower threshold, so it might be a 2217 * requirement of all 575x family chips. The Linux driver sets 2218 * the lower threshold for all 5705 family chips as well, but there 2219 * are reports that it might not need to be so strict. 2220 * 2221 * XXX Linux does some extra fiddling here for the 5906 parts as 2222 * well. 2223 */ 2224 if (BGE_IS_5705_PLUS(sc)) 2225 val = 8; 2226 else 2227 val = BGE_STD_RX_RING_CNT / 8; 2228 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2229 if (BGE_IS_JUMBO_CAPABLE(sc)) 2230 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2231 BGE_JUMBO_RX_RING_CNT/8); 2232 if (BGE_IS_5717_PLUS(sc)) { 2233 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2234 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2235 } 2236 2237 /* 2238 * Disable all send rings by setting the 'ring disabled' bit 2239 * in the flags field of all the TX send ring control blocks, 2240 * located in NIC memory. 2241 */ 2242 if (!BGE_IS_5705_PLUS(sc)) 2243 /* 5700 to 5704 had 16 send rings. */ 2244 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2245 else if (BGE_IS_57765_PLUS(sc) || 2246 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2247 limit = 2; 2248 else if (BGE_IS_5717_PLUS(sc)) 2249 limit = 4; 2250 else 2251 limit = 1; 2252 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2253 for (i = 0; i < limit; i++) { 2254 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2255 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2256 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2257 vrcb += sizeof(struct bge_rcb); 2258 } 2259 2260 /* Configure send ring RCB 0 (we use only the first ring) */ 2261 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2262 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2263 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2264 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2265 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2266 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2267 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2268 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2269 else 2270 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2271 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2272 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2273 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2274 2275 /* 2276 * Disable all receive return rings by setting the 2277 * 'ring diabled' bit in the flags field of all the receive 2278 * return ring control blocks, located in NIC memory. 2279 */ 2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2281 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2282 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2283 /* Should be 17, use 16 until we get an SRAM map. */ 2284 limit = 16; 2285 } else if (!BGE_IS_5705_PLUS(sc)) 2286 limit = BGE_RX_RINGS_MAX; 2287 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2288 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2289 BGE_IS_57765_PLUS(sc)) 2290 limit = 4; 2291 else 2292 limit = 1; 2293 /* Disable all receive return rings. */ 2294 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2295 for (i = 0; i < limit; i++) { 2296 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2297 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2298 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2299 BGE_RCB_FLAG_RING_DISABLED); 2300 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2301 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2302 (i * (sizeof(uint64_t))), 0); 2303 vrcb += sizeof(struct bge_rcb); 2304 } 2305 2306 /* 2307 * Set up receive return ring 0. Note that the NIC address 2308 * for RX return rings is 0x0. The return rings live entirely 2309 * within the host, so the nicaddr field in the RCB isn't used. 2310 */ 2311 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2312 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2313 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2314 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2315 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2316 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2317 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2318 2319 /* Set random backoff seed for TX */ 2320 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2321 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2322 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2323 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2324 BGE_TX_BACKOFF_SEED_MASK); 2325 2326 /* Set inter-packet gap */ 2327 val = 0x2620; 2328 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2329 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2330 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2331 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2332 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2333 2334 /* 2335 * Specify which ring to use for packets that don't match 2336 * any RX rules. 2337 */ 2338 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2339 2340 /* 2341 * Configure number of RX lists. One interrupt distribution 2342 * list, sixteen active lists, one bad frames class. 2343 */ 2344 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2345 2346 /* Inialize RX list placement stats mask. */ 2347 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2348 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2349 2350 /* Disable host coalescing until we get it set up */ 2351 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2352 2353 /* Poll to make sure it's shut down. */ 2354 for (i = 0; i < BGE_TIMEOUT; i++) { 2355 DELAY(10); 2356 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2357 break; 2358 } 2359 2360 if (i == BGE_TIMEOUT) { 2361 device_printf(sc->bge_dev, 2362 "host coalescing engine failed to idle\n"); 2363 return (ENXIO); 2364 } 2365 2366 /* Set up host coalescing defaults */ 2367 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2368 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2369 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2370 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2371 if (!(BGE_IS_5705_PLUS(sc))) { 2372 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2373 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2374 } 2375 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2376 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2377 2378 /* Set up address of statistics block */ 2379 if (!(BGE_IS_5705_PLUS(sc))) { 2380 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2381 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2382 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2383 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2384 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2385 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2386 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2387 } 2388 2389 /* Set up address of status block */ 2390 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2391 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2392 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2393 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2394 2395 /* Set up status block size. */ 2396 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2397 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2398 val = BGE_STATBLKSZ_FULL; 2399 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2400 } else { 2401 val = BGE_STATBLKSZ_32BYTE; 2402 bzero(sc->bge_ldata.bge_status_block, 32); 2403 } 2404 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2405 sc->bge_cdata.bge_status_map, 2406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2407 2408 /* Turn on host coalescing state machine */ 2409 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2410 2411 /* Turn on RX BD completion state machine and enable attentions */ 2412 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2413 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2414 2415 /* Turn on RX list placement state machine */ 2416 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2417 2418 /* Turn on RX list selector state machine. */ 2419 if (!(BGE_IS_5705_PLUS(sc))) 2420 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2421 2422 /* Turn on DMA, clear stats. */ 2423 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2424 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2425 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2426 BGE_MACMODE_FRMHDR_DMA_ENB; 2427 2428 if (sc->bge_flags & BGE_FLAG_TBI) 2429 val |= BGE_PORTMODE_TBI; 2430 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2431 val |= BGE_PORTMODE_GMII; 2432 else 2433 val |= BGE_PORTMODE_MII; 2434 2435 /* Allow APE to send/receive frames. */ 2436 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2437 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2438 2439 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2440 DELAY(40); 2441 2442 /* Set misc. local control, enable interrupts on attentions */ 2443 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2444 2445 #ifdef notdef 2446 /* Assert GPIO pins for PHY reset */ 2447 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2448 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2449 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2450 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2451 #endif 2452 2453 /* Turn on DMA completion state machine */ 2454 if (!(BGE_IS_5705_PLUS(sc))) 2455 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2456 2457 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2458 2459 /* Enable host coalescing bug fix. */ 2460 if (BGE_IS_5755_PLUS(sc)) 2461 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2462 2463 /* Request larger DMA burst size to get better performance. */ 2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2465 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2466 2467 /* Turn on write DMA state machine */ 2468 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2469 DELAY(40); 2470 2471 /* Turn on read DMA state machine */ 2472 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2473 2474 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2475 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2476 2477 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2478 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2479 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2480 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2481 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2482 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2483 if (sc->bge_flags & BGE_FLAG_PCIE) 2484 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2485 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2486 val |= BGE_RDMAMODE_TSO4_ENABLE; 2487 if (sc->bge_flags & BGE_FLAG_TSO3 || 2488 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2489 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2490 val |= BGE_RDMAMODE_TSO6_ENABLE; 2491 } 2492 2493 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2494 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2495 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2496 BGE_RDMAMODE_H2BNC_VLAN_DET; 2497 /* 2498 * Allow multiple outstanding read requests from 2499 * non-LSO read DMA engine. 2500 */ 2501 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2502 } 2503 2504 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2505 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2506 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2507 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2508 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2509 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2510 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2511 else 2512 rdmareg = BGE_RDMA_RSRVCTRL; 2513 dmactl = CSR_READ_4(sc, rdmareg); 2514 /* 2515 * Adjust tx margin to prevent TX data corruption and 2516 * fix internal FIFO overflow. 2517 */ 2518 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2519 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2520 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2521 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2522 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2523 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2524 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2525 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2526 } 2527 /* 2528 * Enable fix for read DMA FIFO overruns. 2529 * The fix is to limit the number of RX BDs 2530 * the hardware would fetch at a fime. 2531 */ 2532 CSR_WRITE_4(sc, rdmareg, dmactl | 2533 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2534 } 2535 2536 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2537 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2538 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2539 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2540 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2541 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2542 /* 2543 * Allow 4KB burst length reads for non-LSO frames. 2544 * Enable 512B burst length reads for buffer descriptors. 2545 */ 2546 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2547 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2548 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2549 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2550 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2551 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2552 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2553 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2554 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2555 } 2556 2557 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2558 DELAY(40); 2559 2560 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2561 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2562 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2563 if ((val & 0xFFFF) > BGE_FRAMELEN) 2564 break; 2565 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2566 break; 2567 } 2568 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2569 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2570 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2571 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2572 else 2573 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2574 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2575 } 2576 } 2577 2578 /* Turn on RX data completion state machine */ 2579 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2580 2581 /* Turn on RX BD initiator state machine */ 2582 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2583 2584 /* Turn on RX data and RX BD initiator state machine */ 2585 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2586 2587 /* Turn on Mbuf cluster free state machine */ 2588 if (!(BGE_IS_5705_PLUS(sc))) 2589 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2590 2591 /* Turn on send BD completion state machine */ 2592 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2593 2594 /* Turn on send data completion state machine */ 2595 val = BGE_SDCMODE_ENABLE; 2596 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2597 val |= BGE_SDCMODE_CDELAY; 2598 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2599 2600 /* Turn on send data initiator state machine */ 2601 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2602 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2603 BGE_SDIMODE_HW_LSO_PRE_DMA); 2604 else 2605 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2606 2607 /* Turn on send BD initiator state machine */ 2608 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2609 2610 /* Turn on send BD selector state machine */ 2611 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2612 2613 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2614 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2615 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2616 2617 /* ack/clear link change events */ 2618 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2619 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2620 BGE_MACSTAT_LINK_CHANGED); 2621 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2622 2623 /* 2624 * Enable attention when the link has changed state for 2625 * devices that use auto polling. 2626 */ 2627 if (sc->bge_flags & BGE_FLAG_TBI) { 2628 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2629 } else { 2630 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2631 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2632 DELAY(80); 2633 } 2634 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2635 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2636 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2637 BGE_EVTENB_MI_INTERRUPT); 2638 } 2639 2640 /* 2641 * Clear any pending link state attention. 2642 * Otherwise some link state change events may be lost until attention 2643 * is cleared by bge_intr() -> bge_link_upd() sequence. 2644 * It's not necessary on newer BCM chips - perhaps enabling link 2645 * state change attentions implies clearing pending attention. 2646 */ 2647 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2648 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2649 BGE_MACSTAT_LINK_CHANGED); 2650 2651 /* Enable link state change attentions. */ 2652 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2653 2654 return (0); 2655 } 2656 2657 static const struct bge_revision * 2658 bge_lookup_rev(uint32_t chipid) 2659 { 2660 const struct bge_revision *br; 2661 2662 for (br = bge_revisions; br->br_name != NULL; br++) { 2663 if (br->br_chipid == chipid) 2664 return (br); 2665 } 2666 2667 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2668 if (br->br_chipid == BGE_ASICREV(chipid)) 2669 return (br); 2670 } 2671 2672 return (NULL); 2673 } 2674 2675 static const struct bge_vendor * 2676 bge_lookup_vendor(uint16_t vid) 2677 { 2678 const struct bge_vendor *v; 2679 2680 for (v = bge_vendors; v->v_name != NULL; v++) 2681 if (v->v_id == vid) 2682 return (v); 2683 2684 return (NULL); 2685 } 2686 2687 static uint32_t 2688 bge_chipid(device_t dev) 2689 { 2690 uint32_t id; 2691 2692 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2693 BGE_PCIMISCCTL_ASICREV_SHIFT; 2694 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2695 /* 2696 * Find the ASCI revision. Different chips use different 2697 * registers. 2698 */ 2699 switch (pci_get_device(dev)) { 2700 case BCOM_DEVICEID_BCM5717: 2701 case BCOM_DEVICEID_BCM5718: 2702 case BCOM_DEVICEID_BCM5719: 2703 case BCOM_DEVICEID_BCM5720: 2704 case BCOM_DEVICEID_BCM5725: 2705 case BCOM_DEVICEID_BCM5727: 2706 case BCOM_DEVICEID_BCM5762: 2707 case BCOM_DEVICEID_BCM57764: 2708 case BCOM_DEVICEID_BCM57767: 2709 case BCOM_DEVICEID_BCM57787: 2710 id = pci_read_config(dev, 2711 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2712 break; 2713 case BCOM_DEVICEID_BCM57761: 2714 case BCOM_DEVICEID_BCM57762: 2715 case BCOM_DEVICEID_BCM57765: 2716 case BCOM_DEVICEID_BCM57766: 2717 case BCOM_DEVICEID_BCM57781: 2718 case BCOM_DEVICEID_BCM57782: 2719 case BCOM_DEVICEID_BCM57785: 2720 case BCOM_DEVICEID_BCM57786: 2721 case BCOM_DEVICEID_BCM57791: 2722 case BCOM_DEVICEID_BCM57795: 2723 id = pci_read_config(dev, 2724 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2725 break; 2726 default: 2727 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2728 } 2729 } 2730 return (id); 2731 } 2732 2733 /* 2734 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2735 * against our list and return its name if we find a match. 2736 * 2737 * Note that since the Broadcom controller contains VPD support, we 2738 * try to get the device name string from the controller itself instead 2739 * of the compiled-in string. It guarantees we'll always announce the 2740 * right product name. We fall back to the compiled-in string when 2741 * VPD is unavailable or corrupt. 2742 */ 2743 static int 2744 bge_probe(device_t dev) 2745 { 2746 char buf[96]; 2747 char model[64]; 2748 const struct bge_revision *br; 2749 const char *pname; 2750 struct bge_softc *sc; 2751 const struct bge_type *t = bge_devs; 2752 const struct bge_vendor *v; 2753 uint32_t id; 2754 uint16_t did, vid; 2755 2756 sc = device_get_softc(dev); 2757 sc->bge_dev = dev; 2758 vid = pci_get_vendor(dev); 2759 did = pci_get_device(dev); 2760 while(t->bge_vid != 0) { 2761 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2762 id = bge_chipid(dev); 2763 br = bge_lookup_rev(id); 2764 if (bge_has_eaddr(sc) && 2765 pci_get_vpd_ident(dev, &pname) == 0) 2766 snprintf(model, sizeof(model), "%s", pname); 2767 else { 2768 v = bge_lookup_vendor(vid); 2769 snprintf(model, sizeof(model), "%s %s", 2770 v != NULL ? v->v_name : "Unknown", 2771 br != NULL ? br->br_name : 2772 "NetXtreme/NetLink Ethernet Controller"); 2773 } 2774 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2775 model, br != NULL ? "" : "unknown ", id); 2776 device_set_desc_copy(dev, buf); 2777 return (BUS_PROBE_DEFAULT); 2778 } 2779 t++; 2780 } 2781 2782 return (ENXIO); 2783 } 2784 2785 static void 2786 bge_dma_free(struct bge_softc *sc) 2787 { 2788 int i; 2789 2790 /* Destroy DMA maps for RX buffers. */ 2791 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2792 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2793 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2794 sc->bge_cdata.bge_rx_std_dmamap[i]); 2795 } 2796 if (sc->bge_cdata.bge_rx_std_sparemap) 2797 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2798 sc->bge_cdata.bge_rx_std_sparemap); 2799 2800 /* Destroy DMA maps for jumbo RX buffers. */ 2801 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2802 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2803 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2804 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2805 } 2806 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2807 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2808 sc->bge_cdata.bge_rx_jumbo_sparemap); 2809 2810 /* Destroy DMA maps for TX buffers. */ 2811 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2812 if (sc->bge_cdata.bge_tx_dmamap[i]) 2813 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2814 sc->bge_cdata.bge_tx_dmamap[i]); 2815 } 2816 2817 if (sc->bge_cdata.bge_rx_mtag) 2818 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2819 if (sc->bge_cdata.bge_mtag_jumbo) 2820 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2821 if (sc->bge_cdata.bge_tx_mtag) 2822 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2823 2824 /* Destroy standard RX ring. */ 2825 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2826 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2827 sc->bge_cdata.bge_rx_std_ring_map); 2828 if (sc->bge_ldata.bge_rx_std_ring) 2829 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2830 sc->bge_ldata.bge_rx_std_ring, 2831 sc->bge_cdata.bge_rx_std_ring_map); 2832 2833 if (sc->bge_cdata.bge_rx_std_ring_tag) 2834 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2835 2836 /* Destroy jumbo RX ring. */ 2837 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2838 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2839 sc->bge_cdata.bge_rx_jumbo_ring_map); 2840 2841 if (sc->bge_ldata.bge_rx_jumbo_ring) 2842 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2843 sc->bge_ldata.bge_rx_jumbo_ring, 2844 sc->bge_cdata.bge_rx_jumbo_ring_map); 2845 2846 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2847 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2848 2849 /* Destroy RX return ring. */ 2850 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2851 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2852 sc->bge_cdata.bge_rx_return_ring_map); 2853 2854 if (sc->bge_ldata.bge_rx_return_ring) 2855 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2856 sc->bge_ldata.bge_rx_return_ring, 2857 sc->bge_cdata.bge_rx_return_ring_map); 2858 2859 if (sc->bge_cdata.bge_rx_return_ring_tag) 2860 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2861 2862 /* Destroy TX ring. */ 2863 if (sc->bge_ldata.bge_tx_ring_paddr) 2864 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2865 sc->bge_cdata.bge_tx_ring_map); 2866 2867 if (sc->bge_ldata.bge_tx_ring) 2868 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2869 sc->bge_ldata.bge_tx_ring, 2870 sc->bge_cdata.bge_tx_ring_map); 2871 2872 if (sc->bge_cdata.bge_tx_ring_tag) 2873 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2874 2875 /* Destroy status block. */ 2876 if (sc->bge_ldata.bge_status_block_paddr) 2877 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2878 sc->bge_cdata.bge_status_map); 2879 2880 if (sc->bge_ldata.bge_status_block) 2881 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2882 sc->bge_ldata.bge_status_block, 2883 sc->bge_cdata.bge_status_map); 2884 2885 if (sc->bge_cdata.bge_status_tag) 2886 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2887 2888 /* Destroy statistics block. */ 2889 if (sc->bge_ldata.bge_stats_paddr) 2890 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2891 sc->bge_cdata.bge_stats_map); 2892 2893 if (sc->bge_ldata.bge_stats) 2894 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2895 sc->bge_ldata.bge_stats, 2896 sc->bge_cdata.bge_stats_map); 2897 2898 if (sc->bge_cdata.bge_stats_tag) 2899 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2900 2901 if (sc->bge_cdata.bge_buffer_tag) 2902 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2903 2904 /* Destroy the parent tag. */ 2905 if (sc->bge_cdata.bge_parent_tag) 2906 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2907 } 2908 2909 static int 2910 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2911 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2912 bus_addr_t *paddr, const char *msg) 2913 { 2914 struct bge_dmamap_arg ctx; 2915 int error; 2916 2917 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2918 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2919 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2920 if (error != 0) { 2921 device_printf(sc->bge_dev, 2922 "could not create %s dma tag\n", msg); 2923 return (ENOMEM); 2924 } 2925 /* Allocate DMA'able memory for ring. */ 2926 error = bus_dmamem_alloc(*tag, (void **)ring, 2927 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2928 if (error != 0) { 2929 device_printf(sc->bge_dev, 2930 "could not allocate DMA'able memory for %s\n", msg); 2931 return (ENOMEM); 2932 } 2933 /* Load the address of the ring. */ 2934 ctx.bge_busaddr = 0; 2935 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2936 &ctx, BUS_DMA_NOWAIT); 2937 if (error != 0) { 2938 device_printf(sc->bge_dev, 2939 "could not load DMA'able memory for %s\n", msg); 2940 return (ENOMEM); 2941 } 2942 *paddr = ctx.bge_busaddr; 2943 return (0); 2944 } 2945 2946 static int 2947 bge_dma_alloc(struct bge_softc *sc) 2948 { 2949 bus_addr_t lowaddr; 2950 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2951 int i, error; 2952 2953 lowaddr = BUS_SPACE_MAXADDR; 2954 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2955 lowaddr = BGE_DMA_MAXADDR; 2956 /* 2957 * Allocate the parent bus DMA tag appropriate for PCI. 2958 */ 2959 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2960 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2961 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2962 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2963 if (error != 0) { 2964 device_printf(sc->bge_dev, 2965 "could not allocate parent dma tag\n"); 2966 return (ENOMEM); 2967 } 2968 2969 /* Create tag for standard RX ring. */ 2970 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2971 &sc->bge_cdata.bge_rx_std_ring_tag, 2972 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2973 &sc->bge_cdata.bge_rx_std_ring_map, 2974 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2975 if (error) 2976 return (error); 2977 2978 /* Create tag for RX return ring. */ 2979 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2980 &sc->bge_cdata.bge_rx_return_ring_tag, 2981 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2982 &sc->bge_cdata.bge_rx_return_ring_map, 2983 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2984 if (error) 2985 return (error); 2986 2987 /* Create tag for TX ring. */ 2988 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2989 &sc->bge_cdata.bge_tx_ring_tag, 2990 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2991 &sc->bge_cdata.bge_tx_ring_map, 2992 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2993 if (error) 2994 return (error); 2995 2996 /* 2997 * Create tag for status block. 2998 * Because we only use single Tx/Rx/Rx return ring, use 2999 * minimum status block size except BCM5700 AX/BX which 3000 * seems to want to see full status block size regardless 3001 * of configured number of ring. 3002 */ 3003 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3004 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 3005 sbsz = BGE_STATUS_BLK_SZ; 3006 else 3007 sbsz = 32; 3008 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3009 &sc->bge_cdata.bge_status_tag, 3010 (uint8_t **)&sc->bge_ldata.bge_status_block, 3011 &sc->bge_cdata.bge_status_map, 3012 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3013 if (error) 3014 return (error); 3015 3016 /* Create tag for statistics block. */ 3017 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3018 &sc->bge_cdata.bge_stats_tag, 3019 (uint8_t **)&sc->bge_ldata.bge_stats, 3020 &sc->bge_cdata.bge_stats_map, 3021 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3022 if (error) 3023 return (error); 3024 3025 /* Create tag for jumbo RX ring. */ 3026 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3027 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3028 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3029 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3030 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3031 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3032 if (error) 3033 return (error); 3034 } 3035 3036 /* Create parent tag for buffers. */ 3037 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3038 /* 3039 * XXX 3040 * watchdog timeout issue was observed on BCM5704 which 3041 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3042 * Both limiting DMA address space to 32bits and flushing 3043 * mailbox write seem to address the issue. 3044 */ 3045 if (sc->bge_pcixcap != 0) 3046 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3047 } 3048 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3049 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3050 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3051 &sc->bge_cdata.bge_buffer_tag); 3052 if (error != 0) { 3053 device_printf(sc->bge_dev, 3054 "could not allocate buffer dma tag\n"); 3055 return (ENOMEM); 3056 } 3057 /* Create tag for Tx mbufs. */ 3058 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3059 txsegsz = BGE_TSOSEG_SZ; 3060 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3061 } else { 3062 txsegsz = MCLBYTES; 3063 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3064 } 3065 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3066 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3067 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3068 &sc->bge_cdata.bge_tx_mtag); 3069 3070 if (error) { 3071 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3072 return (ENOMEM); 3073 } 3074 3075 /* Create tag for Rx mbufs. */ 3076 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3077 rxmaxsegsz = MJUM9BYTES; 3078 else 3079 rxmaxsegsz = MCLBYTES; 3080 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3081 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3082 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3083 3084 if (error) { 3085 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3086 return (ENOMEM); 3087 } 3088 3089 /* Create DMA maps for RX buffers. */ 3090 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3091 &sc->bge_cdata.bge_rx_std_sparemap); 3092 if (error) { 3093 device_printf(sc->bge_dev, 3094 "can't create spare DMA map for RX\n"); 3095 return (ENOMEM); 3096 } 3097 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3098 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3099 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3100 if (error) { 3101 device_printf(sc->bge_dev, 3102 "can't create DMA map for RX\n"); 3103 return (ENOMEM); 3104 } 3105 } 3106 3107 /* Create DMA maps for TX buffers. */ 3108 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3109 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3110 &sc->bge_cdata.bge_tx_dmamap[i]); 3111 if (error) { 3112 device_printf(sc->bge_dev, 3113 "can't create DMA map for TX\n"); 3114 return (ENOMEM); 3115 } 3116 } 3117 3118 /* Create tags for jumbo RX buffers. */ 3119 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3120 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3121 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3122 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3123 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3124 if (error) { 3125 device_printf(sc->bge_dev, 3126 "could not allocate jumbo dma tag\n"); 3127 return (ENOMEM); 3128 } 3129 /* Create DMA maps for jumbo RX buffers. */ 3130 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3131 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3132 if (error) { 3133 device_printf(sc->bge_dev, 3134 "can't create spare DMA map for jumbo RX\n"); 3135 return (ENOMEM); 3136 } 3137 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3138 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3139 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3140 if (error) { 3141 device_printf(sc->bge_dev, 3142 "can't create DMA map for jumbo RX\n"); 3143 return (ENOMEM); 3144 } 3145 } 3146 } 3147 3148 return (0); 3149 } 3150 3151 /* 3152 * Return true if this device has more than one port. 3153 */ 3154 static int 3155 bge_has_multiple_ports(struct bge_softc *sc) 3156 { 3157 device_t dev = sc->bge_dev; 3158 u_int b, d, f, fscan, s; 3159 3160 d = pci_get_domain(dev); 3161 b = pci_get_bus(dev); 3162 s = pci_get_slot(dev); 3163 f = pci_get_function(dev); 3164 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3165 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3166 return (1); 3167 return (0); 3168 } 3169 3170 /* 3171 * Return true if MSI can be used with this device. 3172 */ 3173 static int 3174 bge_can_use_msi(struct bge_softc *sc) 3175 { 3176 int can_use_msi = 0; 3177 3178 if (sc->bge_msi == 0) 3179 return (0); 3180 3181 /* Disable MSI for polling(4). */ 3182 #ifdef DEVICE_POLLING 3183 return (0); 3184 #endif 3185 switch (sc->bge_asicrev) { 3186 case BGE_ASICREV_BCM5714_A0: 3187 case BGE_ASICREV_BCM5714: 3188 /* 3189 * Apparently, MSI doesn't work when these chips are 3190 * configured in single-port mode. 3191 */ 3192 if (bge_has_multiple_ports(sc)) 3193 can_use_msi = 1; 3194 break; 3195 case BGE_ASICREV_BCM5750: 3196 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3197 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3198 can_use_msi = 1; 3199 break; 3200 default: 3201 if (BGE_IS_575X_PLUS(sc)) 3202 can_use_msi = 1; 3203 } 3204 return (can_use_msi); 3205 } 3206 3207 static int 3208 bge_mbox_reorder(struct bge_softc *sc) 3209 { 3210 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3211 static const struct mbox_reorder { 3212 const uint16_t vendor; 3213 const uint16_t device; 3214 const char *desc; 3215 } mbox_reorder_lists[] = { 3216 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3217 }; 3218 devclass_t pci, pcib; 3219 device_t bus, dev; 3220 int i; 3221 3222 pci = devclass_find("pci"); 3223 pcib = devclass_find("pcib"); 3224 dev = sc->bge_dev; 3225 bus = device_get_parent(dev); 3226 for (;;) { 3227 dev = device_get_parent(bus); 3228 bus = device_get_parent(dev); 3229 if (device_get_devclass(dev) != pcib) 3230 break; 3231 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3232 if (pci_get_vendor(dev) == 3233 mbox_reorder_lists[i].vendor && 3234 pci_get_device(dev) == 3235 mbox_reorder_lists[i].device) { 3236 device_printf(sc->bge_dev, 3237 "enabling MBOX workaround for %s\n", 3238 mbox_reorder_lists[i].desc); 3239 return (1); 3240 } 3241 } 3242 if (device_get_devclass(bus) != pci) 3243 break; 3244 } 3245 return (0); 3246 } 3247 3248 static void 3249 bge_devinfo(struct bge_softc *sc) 3250 { 3251 uint32_t cfg, clk; 3252 3253 device_printf(sc->bge_dev, 3254 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3255 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3256 if (sc->bge_flags & BGE_FLAG_PCIE) 3257 printf("PCI-E\n"); 3258 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3259 printf("PCI-X "); 3260 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3261 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3262 clk = 133; 3263 else { 3264 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3265 switch (clk) { 3266 case 0: 3267 clk = 33; 3268 break; 3269 case 2: 3270 clk = 50; 3271 break; 3272 case 4: 3273 clk = 66; 3274 break; 3275 case 6: 3276 clk = 100; 3277 break; 3278 case 7: 3279 clk = 133; 3280 break; 3281 } 3282 } 3283 printf("%u MHz\n", clk); 3284 } else { 3285 if (sc->bge_pcixcap != 0) 3286 printf("PCI on PCI-X "); 3287 else 3288 printf("PCI "); 3289 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3290 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3291 clk = 66; 3292 else 3293 clk = 33; 3294 if (cfg & BGE_PCISTATE_32BIT_BUS) 3295 printf("%u MHz; 32bit\n", clk); 3296 else 3297 printf("%u MHz; 64bit\n", clk); 3298 } 3299 } 3300 3301 static int 3302 bge_attach(device_t dev) 3303 { 3304 if_t ifp; 3305 struct bge_softc *sc; 3306 uint32_t hwcfg = 0, misccfg, pcistate; 3307 u_char eaddr[ETHER_ADDR_LEN]; 3308 int capmask, error, reg, rid, trys; 3309 3310 sc = device_get_softc(dev); 3311 sc->bge_dev = dev; 3312 3313 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3314 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3315 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3316 3317 pci_enable_busmaster(dev); 3318 3319 /* 3320 * Allocate control/status registers. 3321 */ 3322 rid = PCIR_BAR(0); 3323 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3324 RF_ACTIVE); 3325 3326 if (sc->bge_res == NULL) { 3327 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3328 error = ENXIO; 3329 goto fail; 3330 } 3331 3332 /* Save various chip information. */ 3333 sc->bge_func_addr = pci_get_function(dev); 3334 sc->bge_chipid = bge_chipid(dev); 3335 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3336 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3337 3338 /* Set default PHY address. */ 3339 sc->bge_phy_addr = 1; 3340 /* 3341 * PHY address mapping for various devices. 3342 * 3343 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3344 * ---------+-------+-------+-------+-------+ 3345 * BCM57XX | 1 | X | X | X | 3346 * BCM5704 | 1 | X | 1 | X | 3347 * BCM5717 | 1 | 8 | 2 | 9 | 3348 * BCM5719 | 1 | 8 | 2 | 9 | 3349 * BCM5720 | 1 | 8 | 2 | 9 | 3350 * 3351 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3352 * ---------+-------+-------+-------+-------+ 3353 * BCM57XX | X | X | X | X | 3354 * BCM5704 | X | X | X | X | 3355 * BCM5717 | X | X | X | X | 3356 * BCM5719 | 3 | 10 | 4 | 11 | 3357 * BCM5720 | X | X | X | X | 3358 * 3359 * Other addresses may respond but they are not 3360 * IEEE compliant PHYs and should be ignored. 3361 */ 3362 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3363 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3364 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3365 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3366 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3367 BGE_SGDIGSTS_IS_SERDES) 3368 sc->bge_phy_addr = sc->bge_func_addr + 8; 3369 else 3370 sc->bge_phy_addr = sc->bge_func_addr + 1; 3371 } else { 3372 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3373 BGE_CPMU_PHY_STRAP_IS_SERDES) 3374 sc->bge_phy_addr = sc->bge_func_addr + 8; 3375 else 3376 sc->bge_phy_addr = sc->bge_func_addr + 1; 3377 } 3378 } 3379 3380 if (bge_has_eaddr(sc)) 3381 sc->bge_flags |= BGE_FLAG_EADDR; 3382 3383 /* Save chipset family. */ 3384 switch (sc->bge_asicrev) { 3385 case BGE_ASICREV_BCM5762: 3386 case BGE_ASICREV_BCM57765: 3387 case BGE_ASICREV_BCM57766: 3388 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3389 /* FALLTHROUGH */ 3390 case BGE_ASICREV_BCM5717: 3391 case BGE_ASICREV_BCM5719: 3392 case BGE_ASICREV_BCM5720: 3393 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3394 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3395 BGE_FLAG_JUMBO_FRAME; 3396 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3397 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3398 /* 3399 * Enable work around for DMA engine miscalculation 3400 * of TXMBUF available space. 3401 */ 3402 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3403 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3404 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3405 /* Jumbo frame on BCM5719 A0 does not work. */ 3406 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3407 } 3408 } 3409 break; 3410 case BGE_ASICREV_BCM5755: 3411 case BGE_ASICREV_BCM5761: 3412 case BGE_ASICREV_BCM5784: 3413 case BGE_ASICREV_BCM5785: 3414 case BGE_ASICREV_BCM5787: 3415 case BGE_ASICREV_BCM57780: 3416 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3417 BGE_FLAG_5705_PLUS; 3418 break; 3419 case BGE_ASICREV_BCM5700: 3420 case BGE_ASICREV_BCM5701: 3421 case BGE_ASICREV_BCM5703: 3422 case BGE_ASICREV_BCM5704: 3423 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3424 break; 3425 case BGE_ASICREV_BCM5714_A0: 3426 case BGE_ASICREV_BCM5780: 3427 case BGE_ASICREV_BCM5714: 3428 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3429 /* FALLTHROUGH */ 3430 case BGE_ASICREV_BCM5750: 3431 case BGE_ASICREV_BCM5752: 3432 case BGE_ASICREV_BCM5906: 3433 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3434 /* FALLTHROUGH */ 3435 case BGE_ASICREV_BCM5705: 3436 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3437 break; 3438 } 3439 3440 /* Identify chips with APE processor. */ 3441 switch (sc->bge_asicrev) { 3442 case BGE_ASICREV_BCM5717: 3443 case BGE_ASICREV_BCM5719: 3444 case BGE_ASICREV_BCM5720: 3445 case BGE_ASICREV_BCM5761: 3446 case BGE_ASICREV_BCM5762: 3447 sc->bge_flags |= BGE_FLAG_APE; 3448 break; 3449 } 3450 3451 /* Chips with APE need BAR2 access for APE registers/memory. */ 3452 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3453 rid = PCIR_BAR(2); 3454 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3455 RF_ACTIVE); 3456 if (sc->bge_res2 == NULL) { 3457 device_printf (sc->bge_dev, 3458 "couldn't map BAR2 memory\n"); 3459 error = ENXIO; 3460 goto fail; 3461 } 3462 3463 /* Enable APE register/memory access by host driver. */ 3464 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3465 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3466 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3467 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3468 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3469 3470 bge_ape_lock_init(sc); 3471 bge_ape_read_fw_ver(sc); 3472 } 3473 3474 /* Add SYSCTLs, requires the chipset family to be set. */ 3475 bge_add_sysctls(sc); 3476 3477 /* Identify the chips that use an CPMU. */ 3478 if (BGE_IS_5717_PLUS(sc) || 3479 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3480 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3481 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3482 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3483 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3484 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3485 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3486 else 3487 sc->bge_mi_mode = BGE_MIMODE_BASE; 3488 /* Enable auto polling for BCM570[0-5]. */ 3489 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3490 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3491 3492 /* 3493 * All Broadcom controllers have 4GB boundary DMA bug. 3494 * Whenever an address crosses a multiple of the 4GB boundary 3495 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3496 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3497 * state machine will lockup and cause the device to hang. 3498 */ 3499 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3500 3501 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3502 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3503 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3504 3505 /* 3506 * BCM5719 cannot handle DMA requests for DMA segments that 3507 * have larger than 4KB in size. However the maximum DMA 3508 * segment size created in DMA tag is 4KB for TSO, so we 3509 * wouldn't encounter the issue here. 3510 */ 3511 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3512 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3513 3514 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3515 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3516 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3517 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3518 sc->bge_flags |= BGE_FLAG_5788; 3519 } 3520 3521 capmask = BMSR_DEFCAPMASK; 3522 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3523 (misccfg == 0x4000 || misccfg == 0x8000)) || 3524 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3525 pci_get_vendor(dev) == BCOM_VENDORID && 3526 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3527 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3528 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3529 (pci_get_vendor(dev) == BCOM_VENDORID && 3530 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3531 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3532 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3533 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3534 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3535 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3536 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3537 /* These chips are 10/100 only. */ 3538 capmask &= ~BMSR_EXTSTAT; 3539 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3540 } 3541 3542 /* 3543 * Some controllers seem to require a special firmware to use 3544 * TSO. But the firmware is not available to FreeBSD and Linux 3545 * claims that the TSO performed by the firmware is slower than 3546 * hardware based TSO. Moreover the firmware based TSO has one 3547 * known bug which can't handle TSO if Ethernet header + IP/TCP 3548 * header is greater than 80 bytes. A workaround for the TSO 3549 * bug exist but it seems it's too expensive than not using 3550 * TSO at all. Some hardwares also have the TSO bug so limit 3551 * the TSO to the controllers that are not affected TSO issues 3552 * (e.g. 5755 or higher). 3553 */ 3554 if (BGE_IS_5717_PLUS(sc)) { 3555 /* BCM5717 requires different TSO configuration. */ 3556 sc->bge_flags |= BGE_FLAG_TSO3; 3557 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3558 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3559 /* TSO on BCM5719 A0 does not work. */ 3560 sc->bge_flags &= ~BGE_FLAG_TSO3; 3561 } 3562 } else if (BGE_IS_5755_PLUS(sc)) { 3563 /* 3564 * BCM5754 and BCM5787 shares the same ASIC id so 3565 * explicit device id check is required. 3566 * Due to unknown reason TSO does not work on BCM5755M. 3567 */ 3568 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3569 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3570 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3571 sc->bge_flags |= BGE_FLAG_TSO; 3572 } 3573 3574 /* 3575 * Check if this is a PCI-X or PCI Express device. 3576 */ 3577 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3578 /* 3579 * Found a PCI Express capabilities register, this 3580 * must be a PCI Express device. 3581 */ 3582 sc->bge_flags |= BGE_FLAG_PCIE; 3583 sc->bge_expcap = reg; 3584 /* Extract supported maximum payload size. */ 3585 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3586 PCIER_DEVICE_CAP, 2); 3587 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3588 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3589 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3590 sc->bge_expmrq = 2048; 3591 else 3592 sc->bge_expmrq = 4096; 3593 pci_set_max_read_req(dev, sc->bge_expmrq); 3594 } else { 3595 /* 3596 * Check if the device is in PCI-X Mode. 3597 * (This bit is not valid on PCI Express controllers.) 3598 */ 3599 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3600 sc->bge_pcixcap = reg; 3601 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3602 BGE_PCISTATE_PCI_BUSMODE) == 0) 3603 sc->bge_flags |= BGE_FLAG_PCIX; 3604 } 3605 3606 /* 3607 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3608 * not actually a MAC controller bug but an issue with the embedded 3609 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3610 */ 3611 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3612 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3613 /* 3614 * Some PCI-X bridges are known to trigger write reordering to 3615 * the mailbox registers. Typical phenomena is watchdog timeouts 3616 * caused by out-of-order TX completions. Enable workaround for 3617 * PCI-X devices that live behind these bridges. 3618 * Note, PCI-X controllers can run in PCI mode so we can't use 3619 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3620 */ 3621 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3622 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3623 /* 3624 * Allocate the interrupt, using MSI if possible. These devices 3625 * support 8 MSI messages, but only the first one is used in 3626 * normal operation. 3627 */ 3628 rid = 0; 3629 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3630 sc->bge_msicap = reg; 3631 reg = 1; 3632 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3633 rid = 1; 3634 sc->bge_flags |= BGE_FLAG_MSI; 3635 } 3636 } 3637 3638 /* 3639 * All controllers except BCM5700 supports tagged status but 3640 * we use tagged status only for MSI case on BCM5717. Otherwise 3641 * MSI on BCM5717 does not work. 3642 */ 3643 #ifndef DEVICE_POLLING 3644 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3645 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3646 #endif 3647 3648 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3649 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3650 3651 if (sc->bge_irq == NULL) { 3652 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3653 error = ENXIO; 3654 goto fail; 3655 } 3656 3657 bge_devinfo(sc); 3658 3659 sc->bge_asf_mode = 0; 3660 /* No ASF if APE present. */ 3661 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3662 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3663 BGE_SRAM_DATA_SIG_MAGIC)) { 3664 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3665 BGE_HWCFG_ASF) { 3666 sc->bge_asf_mode |= ASF_ENABLE; 3667 sc->bge_asf_mode |= ASF_STACKUP; 3668 if (BGE_IS_575X_PLUS(sc)) 3669 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3670 } 3671 } 3672 } 3673 3674 bge_stop_fw(sc); 3675 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3676 if (bge_reset(sc)) { 3677 device_printf(sc->bge_dev, "chip reset failed\n"); 3678 error = ENXIO; 3679 goto fail; 3680 } 3681 3682 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3683 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3684 3685 if (bge_chipinit(sc)) { 3686 device_printf(sc->bge_dev, "chip initialization failed\n"); 3687 error = ENXIO; 3688 goto fail; 3689 } 3690 3691 error = bge_get_eaddr(sc, eaddr); 3692 if (error) { 3693 device_printf(sc->bge_dev, 3694 "failed to read station address\n"); 3695 error = ENXIO; 3696 goto fail; 3697 } 3698 3699 /* 5705 limits RX return ring to 512 entries. */ 3700 if (BGE_IS_5717_PLUS(sc)) 3701 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3702 else if (BGE_IS_5705_PLUS(sc)) 3703 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3704 else 3705 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3706 3707 if (bge_dma_alloc(sc)) { 3708 device_printf(sc->bge_dev, 3709 "failed to allocate DMA resources\n"); 3710 error = ENXIO; 3711 goto fail; 3712 } 3713 3714 /* Set default tuneable values. */ 3715 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3716 sc->bge_rx_coal_ticks = 150; 3717 sc->bge_tx_coal_ticks = 150; 3718 sc->bge_rx_max_coal_bds = 10; 3719 sc->bge_tx_max_coal_bds = 10; 3720 3721 /* Initialize checksum features to use. */ 3722 sc->bge_csum_features = BGE_CSUM_FEATURES; 3723 if (sc->bge_forced_udpcsum != 0) 3724 sc->bge_csum_features |= CSUM_UDP; 3725 3726 /* Set up ifnet structure */ 3727 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3728 if (ifp == NULL) { 3729 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3730 error = ENXIO; 3731 goto fail; 3732 } 3733 if_setsoftc(ifp, sc); 3734 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3735 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3736 if_setioctlfn(ifp, bge_ioctl); 3737 if_setstartfn(ifp, bge_start); 3738 if_setinitfn(ifp, bge_init); 3739 if_setgetcounterfn(ifp, bge_get_counter); 3740 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3741 if_setsendqready(ifp); 3742 if_sethwassist(ifp, sc->bge_csum_features); 3743 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3744 IFCAP_VLAN_MTU); 3745 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3746 if_sethwassistbits(ifp, CSUM_TSO, 0); 3747 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3748 } 3749 #ifdef IFCAP_VLAN_HWCSUM 3750 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 3751 #endif 3752 if_setcapenable(ifp, if_getcapabilities(ifp)); 3753 #ifdef DEVICE_POLLING 3754 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 3755 #endif 3756 3757 /* 3758 * 5700 B0 chips do not support checksumming correctly due 3759 * to hardware bugs. 3760 */ 3761 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3762 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3763 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3764 if_sethwassist(ifp, 0); 3765 } 3766 3767 /* 3768 * Figure out what sort of media we have by checking the 3769 * hardware config word in the first 32k of NIC internal memory, 3770 * or fall back to examining the EEPROM if necessary. 3771 * Note: on some BCM5700 cards, this value appears to be unset. 3772 * If that's the case, we have to rely on identifying the NIC 3773 * by its PCI subsystem ID, as we do below for the SysKonnect 3774 * SK-9D41. 3775 */ 3776 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3777 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3778 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3779 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3780 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3781 sizeof(hwcfg))) { 3782 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3783 error = ENXIO; 3784 goto fail; 3785 } 3786 hwcfg = ntohl(hwcfg); 3787 } 3788 3789 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3790 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3791 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3792 if (BGE_IS_5705_PLUS(sc)) { 3793 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3794 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3795 } else 3796 sc->bge_flags |= BGE_FLAG_TBI; 3797 } 3798 3799 /* Set various PHY bug flags. */ 3800 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3801 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3802 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3803 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3804 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3805 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3806 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3807 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3808 if (pci_get_subvendor(dev) == DELL_VENDORID) 3809 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3810 if ((BGE_IS_5705_PLUS(sc)) && 3811 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3812 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3813 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3814 !BGE_IS_5717_PLUS(sc)) { 3815 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3816 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3817 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3818 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3819 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3820 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3821 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3822 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3823 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3824 } else 3825 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3826 } 3827 3828 /* 3829 * Don't enable Ethernet@WireSpeed for the 5700 or the 3830 * 5705 A0 and A1 chips. 3831 */ 3832 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3833 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3834 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3835 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3836 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3837 3838 if (sc->bge_flags & BGE_FLAG_TBI) { 3839 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3840 bge_ifmedia_sts); 3841 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3842 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3843 0, NULL); 3844 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3845 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3846 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3847 } else { 3848 /* 3849 * Do transceiver setup and tell the firmware the 3850 * driver is down so we can try to get access the 3851 * probe if ASF is running. Retry a couple of times 3852 * if we get a conflict with the ASF firmware accessing 3853 * the PHY. 3854 */ 3855 trys = 0; 3856 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3857 again: 3858 bge_asf_driver_up(sc); 3859 3860 error = mii_attach(dev, &sc->bge_miibus, ifp, 3861 (ifm_change_cb_t)bge_ifmedia_upd, 3862 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3863 MII_OFFSET_ANY, MIIF_DOPAUSE); 3864 if (error != 0) { 3865 if (trys++ < 4) { 3866 device_printf(sc->bge_dev, "Try again\n"); 3867 bge_miibus_writereg(sc->bge_dev, 3868 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3869 goto again; 3870 } 3871 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3872 goto fail; 3873 } 3874 3875 /* 3876 * Now tell the firmware we are going up after probing the PHY 3877 */ 3878 if (sc->bge_asf_mode & ASF_STACKUP) 3879 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3880 } 3881 3882 /* 3883 * When using the BCM5701 in PCI-X mode, data corruption has 3884 * been observed in the first few bytes of some received packets. 3885 * Aligning the packet buffer in memory eliminates the corruption. 3886 * Unfortunately, this misaligns the packet payloads. On platforms 3887 * which do not support unaligned accesses, we will realign the 3888 * payloads by copying the received packets. 3889 */ 3890 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3891 sc->bge_flags & BGE_FLAG_PCIX) 3892 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3893 3894 /* 3895 * Call MI attach routine. 3896 */ 3897 ether_ifattach(ifp, eaddr); 3898 3899 /* Tell upper layer we support long frames. */ 3900 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 3901 3902 /* 3903 * Hookup IRQ last. 3904 */ 3905 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3906 /* Take advantage of single-shot MSI. */ 3907 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3908 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3909 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3910 taskqueue_thread_enqueue, &sc->bge_tq); 3911 if (sc->bge_tq == NULL) { 3912 device_printf(dev, "could not create taskqueue.\n"); 3913 ether_ifdetach(ifp); 3914 error = ENOMEM; 3915 goto fail; 3916 } 3917 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3918 "%s taskq", device_get_nameunit(sc->bge_dev)); 3919 if (error != 0) { 3920 device_printf(dev, "could not start threads.\n"); 3921 ether_ifdetach(ifp); 3922 goto fail; 3923 } 3924 error = bus_setup_intr(dev, sc->bge_irq, 3925 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3926 &sc->bge_intrhand); 3927 } else 3928 error = bus_setup_intr(dev, sc->bge_irq, 3929 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3930 &sc->bge_intrhand); 3931 3932 if (error) { 3933 ether_ifdetach(ifp); 3934 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3935 } 3936 3937 fail: 3938 if (error) 3939 bge_detach(dev); 3940 return (error); 3941 } 3942 3943 static int 3944 bge_detach(device_t dev) 3945 { 3946 struct bge_softc *sc; 3947 if_t ifp; 3948 3949 sc = device_get_softc(dev); 3950 ifp = sc->bge_ifp; 3951 3952 #ifdef DEVICE_POLLING 3953 if (if_getcapenable(ifp) & IFCAP_POLLING) 3954 ether_poll_deregister(ifp); 3955 #endif 3956 3957 if (device_is_attached(dev)) { 3958 ether_ifdetach(ifp); 3959 BGE_LOCK(sc); 3960 bge_stop(sc); 3961 BGE_UNLOCK(sc); 3962 callout_drain(&sc->bge_stat_ch); 3963 } 3964 3965 if (sc->bge_tq) 3966 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3967 3968 if (sc->bge_flags & BGE_FLAG_TBI) 3969 ifmedia_removeall(&sc->bge_ifmedia); 3970 else if (sc->bge_miibus != NULL) { 3971 bus_generic_detach(dev); 3972 device_delete_child(dev, sc->bge_miibus); 3973 } 3974 3975 bge_release_resources(sc); 3976 3977 return (0); 3978 } 3979 3980 static void 3981 bge_release_resources(struct bge_softc *sc) 3982 { 3983 device_t dev; 3984 3985 dev = sc->bge_dev; 3986 3987 if (sc->bge_tq != NULL) 3988 taskqueue_free(sc->bge_tq); 3989 3990 if (sc->bge_intrhand != NULL) 3991 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3992 3993 if (sc->bge_irq != NULL) { 3994 bus_release_resource(dev, SYS_RES_IRQ, 3995 rman_get_rid(sc->bge_irq), sc->bge_irq); 3996 pci_release_msi(dev); 3997 } 3998 3999 if (sc->bge_res != NULL) 4000 bus_release_resource(dev, SYS_RES_MEMORY, 4001 rman_get_rid(sc->bge_res), sc->bge_res); 4002 4003 if (sc->bge_res2 != NULL) 4004 bus_release_resource(dev, SYS_RES_MEMORY, 4005 rman_get_rid(sc->bge_res2), sc->bge_res2); 4006 4007 if (sc->bge_ifp != NULL) 4008 if_free(sc->bge_ifp); 4009 4010 bge_dma_free(sc); 4011 4012 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4013 BGE_LOCK_DESTROY(sc); 4014 } 4015 4016 static int 4017 bge_reset(struct bge_softc *sc) 4018 { 4019 device_t dev; 4020 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4021 void (*write_op)(struct bge_softc *, int, int); 4022 uint16_t devctl; 4023 int i; 4024 4025 dev = sc->bge_dev; 4026 4027 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4028 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4029 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4030 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4031 4032 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4033 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4034 if (sc->bge_flags & BGE_FLAG_PCIE) 4035 write_op = bge_writemem_direct; 4036 else 4037 write_op = bge_writemem_ind; 4038 } else 4039 write_op = bge_writereg_ind; 4040 4041 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4042 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4043 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4044 for (i = 0; i < 8000; i++) { 4045 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4046 BGE_NVRAMSWARB_GNT1) 4047 break; 4048 DELAY(20); 4049 } 4050 if (i == 8000) { 4051 if (bootverbose) 4052 device_printf(dev, "NVRAM lock timedout!\n"); 4053 } 4054 } 4055 /* Take APE lock when performing reset. */ 4056 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4057 4058 /* Save some important PCI state. */ 4059 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4060 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4061 4062 pci_write_config(dev, BGE_PCI_MISC_CTL, 4063 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4064 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4065 4066 /* Disable fastboot on controllers that support it. */ 4067 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4068 BGE_IS_5755_PLUS(sc)) { 4069 if (bootverbose) 4070 device_printf(dev, "Disabling fastboot\n"); 4071 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4072 } 4073 4074 /* 4075 * Write the magic number to SRAM at offset 0xB50. 4076 * When firmware finishes its initialization it will 4077 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4078 */ 4079 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4080 4081 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4082 4083 /* XXX: Broadcom Linux driver. */ 4084 if (sc->bge_flags & BGE_FLAG_PCIE) { 4085 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4086 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4087 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4088 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4089 } 4090 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4091 /* Prevent PCIE link training during global reset */ 4092 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4093 reset |= 1 << 29; 4094 } 4095 } 4096 4097 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4098 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4099 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4100 val | BGE_VCPU_STATUS_DRV_RESET); 4101 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4102 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4103 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4104 } 4105 4106 /* 4107 * Set GPHY Power Down Override to leave GPHY 4108 * powered up in D0 uninitialized. 4109 */ 4110 if (BGE_IS_5705_PLUS(sc) && 4111 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4112 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4113 4114 /* Issue global reset */ 4115 write_op(sc, BGE_MISC_CFG, reset); 4116 4117 if (sc->bge_flags & BGE_FLAG_PCIE) 4118 DELAY(100 * 1000); 4119 else 4120 DELAY(1000); 4121 4122 /* XXX: Broadcom Linux driver. */ 4123 if (sc->bge_flags & BGE_FLAG_PCIE) { 4124 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4125 DELAY(500000); /* wait for link training to complete */ 4126 val = pci_read_config(dev, 0xC4, 4); 4127 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4128 } 4129 devctl = pci_read_config(dev, 4130 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4131 /* Clear enable no snoop and disable relaxed ordering. */ 4132 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4133 PCIEM_CTL_NOSNOOP_ENABLE); 4134 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4135 devctl, 2); 4136 pci_set_max_read_req(dev, sc->bge_expmrq); 4137 /* Clear error status. */ 4138 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4139 PCIEM_STA_CORRECTABLE_ERROR | 4140 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4141 PCIEM_STA_UNSUPPORTED_REQ, 2); 4142 } 4143 4144 /* Reset some of the PCI state that got zapped by reset. */ 4145 pci_write_config(dev, BGE_PCI_MISC_CTL, 4146 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4147 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4148 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4149 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4150 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4151 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4152 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4153 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4154 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4155 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4156 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4157 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4158 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4159 /* 4160 * Disable PCI-X relaxed ordering to ensure status block update 4161 * comes first then packet buffer DMA. Otherwise driver may 4162 * read stale status block. 4163 */ 4164 if (sc->bge_flags & BGE_FLAG_PCIX) { 4165 devctl = pci_read_config(dev, 4166 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4167 devctl &= ~PCIXM_COMMAND_ERO; 4168 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4169 devctl &= ~PCIXM_COMMAND_MAX_READ; 4170 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4171 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4172 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4173 PCIXM_COMMAND_MAX_READ); 4174 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4175 } 4176 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4177 devctl, 2); 4178 } 4179 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4180 if (BGE_IS_5714_FAMILY(sc)) { 4181 /* This chip disables MSI on reset. */ 4182 if (sc->bge_flags & BGE_FLAG_MSI) { 4183 val = pci_read_config(dev, 4184 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4185 pci_write_config(dev, 4186 sc->bge_msicap + PCIR_MSI_CTRL, 4187 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4188 val = CSR_READ_4(sc, BGE_MSI_MODE); 4189 CSR_WRITE_4(sc, BGE_MSI_MODE, 4190 val | BGE_MSIMODE_ENABLE); 4191 } 4192 val = CSR_READ_4(sc, BGE_MARB_MODE); 4193 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4194 } else 4195 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4196 4197 /* Fix up byte swapping. */ 4198 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4199 4200 val = CSR_READ_4(sc, BGE_MAC_MODE); 4201 val = (val & ~mac_mode_mask) | mac_mode; 4202 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4203 DELAY(40); 4204 4205 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4206 4207 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4208 for (i = 0; i < BGE_TIMEOUT; i++) { 4209 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4210 if (val & BGE_VCPU_STATUS_INIT_DONE) 4211 break; 4212 DELAY(100); 4213 } 4214 if (i == BGE_TIMEOUT) { 4215 device_printf(dev, "reset timed out\n"); 4216 return (1); 4217 } 4218 } else { 4219 /* 4220 * Poll until we see the 1's complement of the magic number. 4221 * This indicates that the firmware initialization is complete. 4222 * We expect this to fail if no chip containing the Ethernet 4223 * address is fitted though. 4224 */ 4225 for (i = 0; i < BGE_TIMEOUT; i++) { 4226 DELAY(10); 4227 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4228 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4229 break; 4230 } 4231 4232 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4233 device_printf(dev, 4234 "firmware handshake timed out, found 0x%08x\n", 4235 val); 4236 /* BCM57765 A0 needs additional time before accessing. */ 4237 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4238 DELAY(10 * 1000); /* XXX */ 4239 } 4240 4241 /* 4242 * The 5704 in TBI mode apparently needs some special 4243 * adjustment to insure the SERDES drive level is set 4244 * to 1.2V. 4245 */ 4246 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4247 sc->bge_flags & BGE_FLAG_TBI) { 4248 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4249 val = (val & ~0xFFF) | 0x880; 4250 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4251 } 4252 4253 /* XXX: Broadcom Linux driver. */ 4254 if (sc->bge_flags & BGE_FLAG_PCIE && 4255 !BGE_IS_5717_PLUS(sc) && 4256 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4257 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4258 /* Enable Data FIFO protection. */ 4259 val = CSR_READ_4(sc, 0x7C00); 4260 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4261 } 4262 4263 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4264 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4265 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4266 4267 return (0); 4268 } 4269 4270 static __inline void 4271 bge_rxreuse_std(struct bge_softc *sc, int i) 4272 { 4273 struct bge_rx_bd *r; 4274 4275 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4276 r->bge_flags = BGE_RXBDFLAG_END; 4277 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4278 r->bge_idx = i; 4279 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4280 } 4281 4282 static __inline void 4283 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4284 { 4285 struct bge_extrx_bd *r; 4286 4287 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4288 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4289 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4290 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4291 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4292 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4293 r->bge_idx = i; 4294 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4295 } 4296 4297 /* 4298 * Frame reception handling. This is called if there's a frame 4299 * on the receive return list. 4300 * 4301 * Note: we have to be able to handle two possibilities here: 4302 * 1) the frame is from the jumbo receive ring 4303 * 2) the frame is from the standard receive ring 4304 */ 4305 4306 static int 4307 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4308 { 4309 if_t ifp; 4310 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4311 uint16_t rx_cons; 4312 4313 rx_cons = sc->bge_rx_saved_considx; 4314 4315 /* Nothing to do. */ 4316 if (rx_cons == rx_prod) 4317 return (rx_npkts); 4318 4319 ifp = sc->bge_ifp; 4320 4321 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4322 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4323 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4324 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4325 if (BGE_IS_JUMBO_CAPABLE(sc) && 4326 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4327 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4328 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4329 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4330 4331 while (rx_cons != rx_prod) { 4332 struct bge_rx_bd *cur_rx; 4333 uint32_t rxidx; 4334 struct mbuf *m = NULL; 4335 uint16_t vlan_tag = 0; 4336 int have_tag = 0; 4337 4338 #ifdef DEVICE_POLLING 4339 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4340 if (sc->rxcycles <= 0) 4341 break; 4342 sc->rxcycles--; 4343 } 4344 #endif 4345 4346 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4347 4348 rxidx = cur_rx->bge_idx; 4349 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4350 4351 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4352 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4353 have_tag = 1; 4354 vlan_tag = cur_rx->bge_vlan_tag; 4355 } 4356 4357 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4358 jumbocnt++; 4359 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4360 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4361 bge_rxreuse_jumbo(sc, rxidx); 4362 continue; 4363 } 4364 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4365 bge_rxreuse_jumbo(sc, rxidx); 4366 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4367 continue; 4368 } 4369 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4370 } else { 4371 stdcnt++; 4372 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4373 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4374 bge_rxreuse_std(sc, rxidx); 4375 continue; 4376 } 4377 if (bge_newbuf_std(sc, rxidx) != 0) { 4378 bge_rxreuse_std(sc, rxidx); 4379 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4380 continue; 4381 } 4382 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4383 } 4384 4385 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 4386 #ifndef __NO_STRICT_ALIGNMENT 4387 /* 4388 * For architectures with strict alignment we must make sure 4389 * the payload is aligned. 4390 */ 4391 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4392 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4393 cur_rx->bge_len); 4394 m->m_data += ETHER_ALIGN; 4395 } 4396 #endif 4397 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4398 m->m_pkthdr.rcvif = ifp; 4399 4400 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 4401 bge_rxcsum(sc, cur_rx, m); 4402 4403 /* 4404 * If we received a packet with a vlan tag, 4405 * attach that information to the packet. 4406 */ 4407 if (have_tag) { 4408 m->m_pkthdr.ether_vtag = vlan_tag; 4409 m->m_flags |= M_VLANTAG; 4410 } 4411 4412 if (holdlck != 0) { 4413 BGE_UNLOCK(sc); 4414 if_input(ifp, m); 4415 BGE_LOCK(sc); 4416 } else 4417 if_input(ifp, m); 4418 rx_npkts++; 4419 4420 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4421 return (rx_npkts); 4422 } 4423 4424 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4425 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4426 if (stdcnt > 0) 4427 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4428 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4429 4430 if (jumbocnt > 0) 4431 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4432 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4433 4434 sc->bge_rx_saved_considx = rx_cons; 4435 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4436 if (stdcnt) 4437 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4438 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4439 if (jumbocnt) 4440 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4441 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4442 #ifdef notyet 4443 /* 4444 * This register wraps very quickly under heavy packet drops. 4445 * If you need correct statistics, you can enable this check. 4446 */ 4447 if (BGE_IS_5705_PLUS(sc)) 4448 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4449 #endif 4450 return (rx_npkts); 4451 } 4452 4453 static void 4454 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4455 { 4456 4457 if (BGE_IS_5717_PLUS(sc)) { 4458 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4459 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4460 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4461 if ((cur_rx->bge_error_flag & 4462 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4463 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4464 } 4465 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4466 m->m_pkthdr.csum_data = 4467 cur_rx->bge_tcp_udp_csum; 4468 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4469 CSUM_PSEUDO_HDR; 4470 } 4471 } 4472 } else { 4473 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4474 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4475 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4476 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4477 } 4478 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4479 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4480 m->m_pkthdr.csum_data = 4481 cur_rx->bge_tcp_udp_csum; 4482 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4483 CSUM_PSEUDO_HDR; 4484 } 4485 } 4486 } 4487 4488 static void 4489 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4490 { 4491 struct bge_tx_bd *cur_tx; 4492 if_t ifp; 4493 4494 BGE_LOCK_ASSERT(sc); 4495 4496 /* Nothing to do. */ 4497 if (sc->bge_tx_saved_considx == tx_cons) 4498 return; 4499 4500 ifp = sc->bge_ifp; 4501 4502 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4503 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4504 /* 4505 * Go through our tx ring and free mbufs for those 4506 * frames that have been sent. 4507 */ 4508 while (sc->bge_tx_saved_considx != tx_cons) { 4509 uint32_t idx; 4510 4511 idx = sc->bge_tx_saved_considx; 4512 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4513 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4514 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 4515 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4516 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4517 sc->bge_cdata.bge_tx_dmamap[idx], 4518 BUS_DMASYNC_POSTWRITE); 4519 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4520 sc->bge_cdata.bge_tx_dmamap[idx]); 4521 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4522 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4523 } 4524 sc->bge_txcnt--; 4525 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4526 } 4527 4528 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4529 if (sc->bge_txcnt == 0) 4530 sc->bge_timer = 0; 4531 } 4532 4533 #ifdef DEVICE_POLLING 4534 static int 4535 bge_poll(if_t ifp, enum poll_cmd cmd, int count) 4536 { 4537 struct bge_softc *sc = if_getsoftc(ifp); 4538 uint16_t rx_prod, tx_cons; 4539 uint32_t statusword; 4540 int rx_npkts = 0; 4541 4542 BGE_LOCK(sc); 4543 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4544 BGE_UNLOCK(sc); 4545 return (rx_npkts); 4546 } 4547 4548 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4549 sc->bge_cdata.bge_status_map, 4550 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4551 /* Fetch updates from the status block. */ 4552 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4553 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4554 4555 statusword = sc->bge_ldata.bge_status_block->bge_status; 4556 /* Clear the status so the next pass only sees the changes. */ 4557 sc->bge_ldata.bge_status_block->bge_status = 0; 4558 4559 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4560 sc->bge_cdata.bge_status_map, 4561 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4562 4563 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4564 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4565 sc->bge_link_evt++; 4566 4567 if (cmd == POLL_AND_CHECK_STATUS) 4568 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4569 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4570 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4571 bge_link_upd(sc); 4572 4573 sc->rxcycles = count; 4574 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4575 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4576 BGE_UNLOCK(sc); 4577 return (rx_npkts); 4578 } 4579 bge_txeof(sc, tx_cons); 4580 if (!if_sendq_empty(ifp)) 4581 bge_start_locked(ifp); 4582 4583 BGE_UNLOCK(sc); 4584 return (rx_npkts); 4585 } 4586 #endif /* DEVICE_POLLING */ 4587 4588 static int 4589 bge_msi_intr(void *arg) 4590 { 4591 struct bge_softc *sc; 4592 4593 sc = (struct bge_softc *)arg; 4594 /* 4595 * This interrupt is not shared and controller already 4596 * disabled further interrupt. 4597 */ 4598 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4599 return (FILTER_HANDLED); 4600 } 4601 4602 static void 4603 bge_intr_task(void *arg, int pending) 4604 { 4605 struct bge_softc *sc; 4606 if_t ifp; 4607 uint32_t status, status_tag; 4608 uint16_t rx_prod, tx_cons; 4609 4610 sc = (struct bge_softc *)arg; 4611 ifp = sc->bge_ifp; 4612 4613 BGE_LOCK(sc); 4614 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 4615 BGE_UNLOCK(sc); 4616 return; 4617 } 4618 4619 /* Get updated status block. */ 4620 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4621 sc->bge_cdata.bge_status_map, 4622 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4623 4624 /* Save producer/consumer indices. */ 4625 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4626 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4627 status = sc->bge_ldata.bge_status_block->bge_status; 4628 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4629 /* Dirty the status flag. */ 4630 sc->bge_ldata.bge_status_block->bge_status = 0; 4631 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4632 sc->bge_cdata.bge_status_map, 4633 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4634 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4635 status_tag = 0; 4636 4637 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4638 bge_link_upd(sc); 4639 4640 /* Let controller work. */ 4641 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4642 4643 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4644 sc->bge_rx_saved_considx != rx_prod) { 4645 /* Check RX return ring producer/consumer. */ 4646 BGE_UNLOCK(sc); 4647 bge_rxeof(sc, rx_prod, 0); 4648 BGE_LOCK(sc); 4649 } 4650 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4651 /* Check TX ring producer/consumer. */ 4652 bge_txeof(sc, tx_cons); 4653 if (!if_sendq_empty(ifp)) 4654 bge_start_locked(ifp); 4655 } 4656 BGE_UNLOCK(sc); 4657 } 4658 4659 static void 4660 bge_intr(void *xsc) 4661 { 4662 struct bge_softc *sc; 4663 if_t ifp; 4664 uint32_t statusword; 4665 uint16_t rx_prod, tx_cons; 4666 4667 sc = xsc; 4668 4669 BGE_LOCK(sc); 4670 4671 ifp = sc->bge_ifp; 4672 4673 #ifdef DEVICE_POLLING 4674 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4675 BGE_UNLOCK(sc); 4676 return; 4677 } 4678 #endif 4679 4680 /* 4681 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4682 * disable interrupts by writing nonzero like we used to, since with 4683 * our current organization this just gives complications and 4684 * pessimizations for re-enabling interrupts. We used to have races 4685 * instead of the necessary complications. Disabling interrupts 4686 * would just reduce the chance of a status update while we are 4687 * running (by switching to the interrupt-mode coalescence 4688 * parameters), but this chance is already very low so it is more 4689 * efficient to get another interrupt than prevent it. 4690 * 4691 * We do the ack first to ensure another interrupt if there is a 4692 * status update after the ack. We don't check for the status 4693 * changing later because it is more efficient to get another 4694 * interrupt than prevent it, not quite as above (not checking is 4695 * a smaller optimization than not toggling the interrupt enable, 4696 * since checking doesn't involve PCI accesses and toggling require 4697 * the status check). So toggling would probably be a pessimization 4698 * even with MSI. It would only be needed for using a task queue. 4699 */ 4700 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4701 4702 /* 4703 * Do the mandatory PCI flush as well as get the link status. 4704 */ 4705 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4706 4707 /* Make sure the descriptor ring indexes are coherent. */ 4708 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4709 sc->bge_cdata.bge_status_map, 4710 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4711 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4712 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4713 sc->bge_ldata.bge_status_block->bge_status = 0; 4714 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4715 sc->bge_cdata.bge_status_map, 4716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4717 4718 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4719 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4720 statusword || sc->bge_link_evt) 4721 bge_link_upd(sc); 4722 4723 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4724 /* Check RX return ring producer/consumer. */ 4725 bge_rxeof(sc, rx_prod, 1); 4726 } 4727 4728 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4729 /* Check TX ring producer/consumer. */ 4730 bge_txeof(sc, tx_cons); 4731 } 4732 4733 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4734 !if_sendq_empty(ifp)) 4735 bge_start_locked(ifp); 4736 4737 BGE_UNLOCK(sc); 4738 } 4739 4740 static void 4741 bge_asf_driver_up(struct bge_softc *sc) 4742 { 4743 if (sc->bge_asf_mode & ASF_STACKUP) { 4744 /* Send ASF heartbeat aprox. every 2s */ 4745 if (sc->bge_asf_count) 4746 sc->bge_asf_count --; 4747 else { 4748 sc->bge_asf_count = 2; 4749 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4750 BGE_FW_CMD_DRV_ALIVE); 4751 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4752 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4753 BGE_FW_HB_TIMEOUT_SEC); 4754 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4755 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4756 BGE_RX_CPU_DRV_EVENT); 4757 } 4758 } 4759 } 4760 4761 static void 4762 bge_tick(void *xsc) 4763 { 4764 struct bge_softc *sc = xsc; 4765 struct mii_data *mii = NULL; 4766 4767 BGE_LOCK_ASSERT(sc); 4768 4769 /* Synchronize with possible callout reset/stop. */ 4770 if (callout_pending(&sc->bge_stat_ch) || 4771 !callout_active(&sc->bge_stat_ch)) 4772 return; 4773 4774 if (BGE_IS_5705_PLUS(sc)) 4775 bge_stats_update_regs(sc); 4776 else 4777 bge_stats_update(sc); 4778 4779 /* XXX Add APE heartbeat check here? */ 4780 4781 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4782 mii = device_get_softc(sc->bge_miibus); 4783 /* 4784 * Do not touch PHY if we have link up. This could break 4785 * IPMI/ASF mode or produce extra input errors 4786 * (extra errors was reported for bcm5701 & bcm5704). 4787 */ 4788 if (!sc->bge_link) 4789 mii_tick(mii); 4790 } else { 4791 /* 4792 * Since in TBI mode auto-polling can't be used we should poll 4793 * link status manually. Here we register pending link event 4794 * and trigger interrupt. 4795 */ 4796 #ifdef DEVICE_POLLING 4797 /* In polling mode we poll link state in bge_poll(). */ 4798 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 4799 #endif 4800 { 4801 sc->bge_link_evt++; 4802 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4803 sc->bge_flags & BGE_FLAG_5788) 4804 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4805 else 4806 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4807 } 4808 } 4809 4810 bge_asf_driver_up(sc); 4811 bge_watchdog(sc); 4812 4813 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4814 } 4815 4816 static void 4817 bge_stats_update_regs(struct bge_softc *sc) 4818 { 4819 if_t ifp; 4820 struct bge_mac_stats *stats; 4821 uint32_t val; 4822 4823 ifp = sc->bge_ifp; 4824 stats = &sc->bge_mac_stats; 4825 4826 stats->ifHCOutOctets += 4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4828 stats->etherStatsCollisions += 4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4830 stats->outXonSent += 4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4832 stats->outXoffSent += 4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4834 stats->dot3StatsInternalMacTransmitErrors += 4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4836 stats->dot3StatsSingleCollisionFrames += 4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4838 stats->dot3StatsMultipleCollisionFrames += 4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4840 stats->dot3StatsDeferredTransmissions += 4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4842 stats->dot3StatsExcessiveCollisions += 4843 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4844 stats->dot3StatsLateCollisions += 4845 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4846 stats->ifHCOutUcastPkts += 4847 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4848 stats->ifHCOutMulticastPkts += 4849 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4850 stats->ifHCOutBroadcastPkts += 4851 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4852 4853 stats->ifHCInOctets += 4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4855 stats->etherStatsFragments += 4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4857 stats->ifHCInUcastPkts += 4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4859 stats->ifHCInMulticastPkts += 4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4861 stats->ifHCInBroadcastPkts += 4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4863 stats->dot3StatsFCSErrors += 4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4865 stats->dot3StatsAlignmentErrors += 4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4867 stats->xonPauseFramesReceived += 4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4869 stats->xoffPauseFramesReceived += 4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4871 stats->macControlFramesReceived += 4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4873 stats->xoffStateEntered += 4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4875 stats->dot3StatsFramesTooLong += 4876 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4877 stats->etherStatsJabbers += 4878 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4879 stats->etherStatsUndersizePkts += 4880 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4881 4882 stats->FramesDroppedDueToFilters += 4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4884 stats->DmaWriteQueueFull += 4885 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4886 stats->DmaWriteHighPriQueueFull += 4887 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4888 stats->NoMoreRxBDs += 4889 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4890 /* 4891 * XXX 4892 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4893 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4894 * includes number of unwanted multicast frames. This comes 4895 * from silicon bug and known workaround to get rough(not 4896 * exact) counter is to enable interrupt on MBUF low water 4897 * attention. This can be accomplished by setting 4898 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4899 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4900 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4901 * However that change would generate more interrupts and 4902 * there are still possibilities of losing multiple frames 4903 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4904 * Given that the workaround still would not get correct 4905 * counter I don't think it's worth to implement it. So 4906 * ignore reading the counter on controllers that have the 4907 * silicon bug. 4908 */ 4909 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4910 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4911 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4912 stats->InputDiscards += 4913 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4914 stats->InputErrors += 4915 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4916 stats->RecvThresholdHit += 4917 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4918 4919 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4920 /* 4921 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4922 * frames, it's safe to disable workaround for DMA engine's 4923 * miscalculation of TXMBUF space. 4924 */ 4925 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4926 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4927 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4928 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4929 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4930 else 4931 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4932 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4933 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4934 } 4935 } 4936 } 4937 4938 static void 4939 bge_stats_clear_regs(struct bge_softc *sc) 4940 { 4941 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4953 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4954 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4955 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4968 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4969 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4970 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4975 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4976 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4977 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4978 } 4979 4980 static void 4981 bge_stats_update(struct bge_softc *sc) 4982 { 4983 if_t ifp; 4984 bus_size_t stats; 4985 uint32_t cnt; /* current register value */ 4986 4987 ifp = sc->bge_ifp; 4988 4989 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4990 4991 #define READ_STAT(sc, stats, stat) \ 4992 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4993 4994 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4995 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions); 4996 sc->bge_tx_collisions = cnt; 4997 4998 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4999 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds); 5000 sc->bge_rx_nobds = cnt; 5001 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5002 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs); 5003 sc->bge_rx_inerrs = cnt; 5004 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5005 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards); 5006 sc->bge_rx_discards = cnt; 5007 5008 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5009 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards); 5010 sc->bge_tx_discards = cnt; 5011 5012 #undef READ_STAT 5013 } 5014 5015 /* 5016 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5017 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5018 * but when such padded frames employ the bge IP/TCP checksum offload, 5019 * the hardware checksum assist gives incorrect results (possibly 5020 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5021 * If we pad such runts with zeros, the onboard checksum comes out correct. 5022 */ 5023 static __inline int 5024 bge_cksum_pad(struct mbuf *m) 5025 { 5026 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5027 struct mbuf *last; 5028 5029 /* If there's only the packet-header and we can pad there, use it. */ 5030 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5031 M_TRAILINGSPACE(m) >= padlen) { 5032 last = m; 5033 } else { 5034 /* 5035 * Walk packet chain to find last mbuf. We will either 5036 * pad there, or append a new mbuf and pad it. 5037 */ 5038 for (last = m; last->m_next != NULL; last = last->m_next); 5039 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5040 /* Allocate new empty mbuf, pad it. Compact later. */ 5041 struct mbuf *n; 5042 5043 MGET(n, M_NOWAIT, MT_DATA); 5044 if (n == NULL) 5045 return (ENOBUFS); 5046 n->m_len = 0; 5047 last->m_next = n; 5048 last = n; 5049 } 5050 } 5051 5052 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5053 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5054 last->m_len += padlen; 5055 m->m_pkthdr.len += padlen; 5056 5057 return (0); 5058 } 5059 5060 static struct mbuf * 5061 bge_check_short_dma(struct mbuf *m) 5062 { 5063 struct mbuf *n; 5064 int found; 5065 5066 /* 5067 * If device receive two back-to-back send BDs with less than 5068 * or equal to 8 total bytes then the device may hang. The two 5069 * back-to-back send BDs must in the same frame for this failure 5070 * to occur. Scan mbuf chains and see whether two back-to-back 5071 * send BDs are there. If this is the case, allocate new mbuf 5072 * and copy the frame to workaround the silicon bug. 5073 */ 5074 for (n = m, found = 0; n != NULL; n = n->m_next) { 5075 if (n->m_len < 8) { 5076 found++; 5077 if (found > 1) 5078 break; 5079 continue; 5080 } 5081 found = 0; 5082 } 5083 5084 if (found > 1) { 5085 n = m_defrag(m, M_NOWAIT); 5086 if (n == NULL) 5087 m_freem(m); 5088 } else 5089 n = m; 5090 return (n); 5091 } 5092 5093 static struct mbuf * 5094 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5095 uint16_t *flags) 5096 { 5097 struct ip *ip; 5098 struct tcphdr *tcp; 5099 struct mbuf *n; 5100 uint16_t hlen; 5101 uint32_t poff; 5102 5103 if (M_WRITABLE(m) == 0) { 5104 /* Get a writable copy. */ 5105 n = m_dup(m, M_NOWAIT); 5106 m_freem(m); 5107 if (n == NULL) 5108 return (NULL); 5109 m = n; 5110 } 5111 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5112 if (m == NULL) 5113 return (NULL); 5114 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5115 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5116 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5117 if (m == NULL) 5118 return (NULL); 5119 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5120 m = m_pullup(m, poff + (tcp->th_off << 2)); 5121 if (m == NULL) 5122 return (NULL); 5123 /* 5124 * It seems controller doesn't modify IP length and TCP pseudo 5125 * checksum. These checksum computed by upper stack should be 0. 5126 */ 5127 *mss = m->m_pkthdr.tso_segsz; 5128 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5129 ip->ip_sum = 0; 5130 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5131 /* Clear pseudo checksum computed by TCP stack. */ 5132 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5133 tcp->th_sum = 0; 5134 /* 5135 * Broadcom controllers uses different descriptor format for 5136 * TSO depending on ASIC revision. Due to TSO-capable firmware 5137 * license issue and lower performance of firmware based TSO 5138 * we only support hardware based TSO. 5139 */ 5140 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5141 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5142 if (sc->bge_flags & BGE_FLAG_TSO3) { 5143 /* 5144 * For BCM5717 and newer controllers, hardware based TSO 5145 * uses the 14 lower bits of the bge_mss field to store the 5146 * MSS and the upper 2 bits to store the lowest 2 bits of 5147 * the IP/TCP header length. The upper 6 bits of the header 5148 * length are stored in the bge_flags[14:10,4] field. Jumbo 5149 * frames are supported. 5150 */ 5151 *mss |= ((hlen & 0x3) << 14); 5152 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5153 } else { 5154 /* 5155 * For BCM5755 and newer controllers, hardware based TSO uses 5156 * the lower 11 bits to store the MSS and the upper 5 bits to 5157 * store the IP/TCP header length. Jumbo frames are not 5158 * supported. 5159 */ 5160 *mss |= (hlen << 11); 5161 } 5162 return (m); 5163 } 5164 5165 /* 5166 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5167 * pointers to descriptors. 5168 */ 5169 static int 5170 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5171 { 5172 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5173 bus_dmamap_t map; 5174 struct bge_tx_bd *d; 5175 struct mbuf *m = *m_head; 5176 uint32_t idx = *txidx; 5177 uint16_t csum_flags, mss, vlan_tag; 5178 int nsegs, i, error; 5179 5180 csum_flags = 0; 5181 mss = 0; 5182 vlan_tag = 0; 5183 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5184 m->m_next != NULL) { 5185 *m_head = bge_check_short_dma(m); 5186 if (*m_head == NULL) 5187 return (ENOBUFS); 5188 m = *m_head; 5189 } 5190 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5191 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5192 if (*m_head == NULL) 5193 return (ENOBUFS); 5194 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5195 BGE_TXBDFLAG_CPU_POST_DMA; 5196 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5197 if (m->m_pkthdr.csum_flags & CSUM_IP) 5198 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5199 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5200 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5201 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5202 (error = bge_cksum_pad(m)) != 0) { 5203 m_freem(m); 5204 *m_head = NULL; 5205 return (error); 5206 } 5207 } 5208 } 5209 5210 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5211 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5212 m->m_pkthdr.len > ETHER_MAX_LEN) 5213 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5214 if (sc->bge_forced_collapse > 0 && 5215 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5216 /* 5217 * Forcedly collapse mbuf chains to overcome hardware 5218 * limitation which only support a single outstanding 5219 * DMA read operation. 5220 */ 5221 if (sc->bge_forced_collapse == 1) 5222 m = m_defrag(m, M_NOWAIT); 5223 else 5224 m = m_collapse(m, M_NOWAIT, 5225 sc->bge_forced_collapse); 5226 if (m == NULL) 5227 m = *m_head; 5228 *m_head = m; 5229 } 5230 } 5231 5232 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5233 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5234 &nsegs, BUS_DMA_NOWAIT); 5235 if (error == EFBIG) { 5236 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5237 if (m == NULL) { 5238 m_freem(*m_head); 5239 *m_head = NULL; 5240 return (ENOBUFS); 5241 } 5242 *m_head = m; 5243 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5244 m, segs, &nsegs, BUS_DMA_NOWAIT); 5245 if (error) { 5246 m_freem(m); 5247 *m_head = NULL; 5248 return (error); 5249 } 5250 } else if (error != 0) 5251 return (error); 5252 5253 /* Check if we have enough free send BDs. */ 5254 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5255 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5256 return (ENOBUFS); 5257 } 5258 5259 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5260 5261 if (m->m_flags & M_VLANTAG) { 5262 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5263 vlan_tag = m->m_pkthdr.ether_vtag; 5264 } 5265 5266 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5267 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5268 /* 5269 * 5725 family of devices corrupts TSO packets when TSO DMA 5270 * buffers cross into regions which are within MSS bytes of 5271 * a 4GB boundary. If we encounter the condition, drop the 5272 * packet. 5273 */ 5274 for (i = 0; ; i++) { 5275 d = &sc->bge_ldata.bge_tx_ring[idx]; 5276 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5277 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5278 d->bge_len = segs[i].ds_len; 5279 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5280 d->bge_addr.bge_addr_lo) 5281 break; 5282 d->bge_flags = csum_flags; 5283 d->bge_vlan_tag = vlan_tag; 5284 d->bge_mss = mss; 5285 if (i == nsegs - 1) 5286 break; 5287 BGE_INC(idx, BGE_TX_RING_CNT); 5288 } 5289 if (i != nsegs - 1) { 5290 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5291 BUS_DMASYNC_POSTWRITE); 5292 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5293 m_freem(*m_head); 5294 *m_head = NULL; 5295 return (EIO); 5296 } 5297 } else { 5298 for (i = 0; ; i++) { 5299 d = &sc->bge_ldata.bge_tx_ring[idx]; 5300 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5301 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5302 d->bge_len = segs[i].ds_len; 5303 d->bge_flags = csum_flags; 5304 d->bge_vlan_tag = vlan_tag; 5305 d->bge_mss = mss; 5306 if (i == nsegs - 1) 5307 break; 5308 BGE_INC(idx, BGE_TX_RING_CNT); 5309 } 5310 } 5311 5312 /* Mark the last segment as end of packet... */ 5313 d->bge_flags |= BGE_TXBDFLAG_END; 5314 5315 /* 5316 * Insure that the map for this transmission 5317 * is placed at the array index of the last descriptor 5318 * in this chain. 5319 */ 5320 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5321 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5322 sc->bge_cdata.bge_tx_chain[idx] = m; 5323 sc->bge_txcnt += nsegs; 5324 5325 BGE_INC(idx, BGE_TX_RING_CNT); 5326 *txidx = idx; 5327 5328 return (0); 5329 } 5330 5331 /* 5332 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5333 * to the mbuf data regions directly in the transmit descriptors. 5334 */ 5335 static void 5336 bge_start_locked(if_t ifp) 5337 { 5338 struct bge_softc *sc; 5339 struct mbuf *m_head; 5340 uint32_t prodidx; 5341 int count; 5342 5343 sc = if_getsoftc(ifp); 5344 BGE_LOCK_ASSERT(sc); 5345 5346 if (!sc->bge_link || 5347 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5348 IFF_DRV_RUNNING) 5349 return; 5350 5351 prodidx = sc->bge_tx_prodidx; 5352 5353 for (count = 0; !if_sendq_empty(ifp);) { 5354 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5355 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5356 break; 5357 } 5358 m_head = if_dequeue(ifp); 5359 if (m_head == NULL) 5360 break; 5361 5362 /* 5363 * Pack the data into the transmit ring. If we 5364 * don't have room, set the OACTIVE flag and wait 5365 * for the NIC to drain the ring. 5366 */ 5367 if (bge_encap(sc, &m_head, &prodidx)) { 5368 if (m_head == NULL) 5369 break; 5370 if_sendq_prepend(ifp, m_head); 5371 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5372 break; 5373 } 5374 ++count; 5375 5376 /* 5377 * If there's a BPF listener, bounce a copy of this frame 5378 * to him. 5379 */ 5380 if_bpfmtap(ifp, m_head); 5381 } 5382 5383 if (count > 0) { 5384 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5385 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5386 /* Transmit. */ 5387 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5388 /* 5700 b2 errata */ 5389 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5390 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5391 5392 sc->bge_tx_prodidx = prodidx; 5393 5394 /* 5395 * Set a timeout in case the chip goes out to lunch. 5396 */ 5397 sc->bge_timer = BGE_TX_TIMEOUT; 5398 } 5399 } 5400 5401 /* 5402 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5403 * to the mbuf data regions directly in the transmit descriptors. 5404 */ 5405 static void 5406 bge_start(if_t ifp) 5407 { 5408 struct bge_softc *sc; 5409 5410 sc = if_getsoftc(ifp); 5411 BGE_LOCK(sc); 5412 bge_start_locked(ifp); 5413 BGE_UNLOCK(sc); 5414 } 5415 5416 static void 5417 bge_init_locked(struct bge_softc *sc) 5418 { 5419 if_t ifp; 5420 uint16_t *m; 5421 uint32_t mode; 5422 5423 BGE_LOCK_ASSERT(sc); 5424 5425 ifp = sc->bge_ifp; 5426 5427 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5428 return; 5429 5430 /* Cancel pending I/O and flush buffers. */ 5431 bge_stop(sc); 5432 5433 bge_stop_fw(sc); 5434 bge_sig_pre_reset(sc, BGE_RESET_START); 5435 bge_reset(sc); 5436 bge_sig_legacy(sc, BGE_RESET_START); 5437 bge_sig_post_reset(sc, BGE_RESET_START); 5438 5439 bge_chipinit(sc); 5440 5441 /* 5442 * Init the various state machines, ring 5443 * control blocks and firmware. 5444 */ 5445 if (bge_blockinit(sc)) { 5446 device_printf(sc->bge_dev, "initialization failure\n"); 5447 return; 5448 } 5449 5450 ifp = sc->bge_ifp; 5451 5452 /* Specify MTU. */ 5453 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5454 ETHER_HDR_LEN + ETHER_CRC_LEN + 5455 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5456 5457 /* Load our MAC address. */ 5458 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5459 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5460 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5461 5462 /* Program promiscuous mode. */ 5463 bge_setpromisc(sc); 5464 5465 /* Program multicast filter. */ 5466 bge_setmulti(sc); 5467 5468 /* Program VLAN tag stripping. */ 5469 bge_setvlan(sc); 5470 5471 /* Override UDP checksum offloading. */ 5472 if (sc->bge_forced_udpcsum == 0) 5473 sc->bge_csum_features &= ~CSUM_UDP; 5474 else 5475 sc->bge_csum_features |= CSUM_UDP; 5476 if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5477 if_getcapenable(ifp) & IFCAP_TXCSUM) { 5478 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5479 if_sethwassistbits(ifp, sc->bge_csum_features, 0); 5480 } 5481 5482 /* Init RX ring. */ 5483 if (bge_init_rx_ring_std(sc) != 0) { 5484 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5485 bge_stop(sc); 5486 return; 5487 } 5488 5489 /* 5490 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5491 * memory to insure that the chip has in fact read the first 5492 * entry of the ring. 5493 */ 5494 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5495 uint32_t v, i; 5496 for (i = 0; i < 10; i++) { 5497 DELAY(20); 5498 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5499 if (v == (MCLBYTES - ETHER_ALIGN)) 5500 break; 5501 } 5502 if (i == 10) 5503 device_printf (sc->bge_dev, 5504 "5705 A0 chip failed to load RX ring\n"); 5505 } 5506 5507 /* Init jumbo RX ring. */ 5508 if (BGE_IS_JUMBO_CAPABLE(sc) && 5509 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5510 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 5511 if (bge_init_rx_ring_jumbo(sc) != 0) { 5512 device_printf(sc->bge_dev, 5513 "no memory for jumbo Rx buffers.\n"); 5514 bge_stop(sc); 5515 return; 5516 } 5517 } 5518 5519 /* Init our RX return ring index. */ 5520 sc->bge_rx_saved_considx = 0; 5521 5522 /* Init our RX/TX stat counters. */ 5523 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5524 5525 /* Init TX ring. */ 5526 bge_init_tx_ring(sc); 5527 5528 /* Enable TX MAC state machine lockup fix. */ 5529 mode = CSR_READ_4(sc, BGE_TX_MODE); 5530 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5531 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5532 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5533 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5534 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5535 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5536 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5537 } 5538 /* Turn on transmitter. */ 5539 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5540 DELAY(100); 5541 5542 /* Turn on receiver. */ 5543 mode = CSR_READ_4(sc, BGE_RX_MODE); 5544 if (BGE_IS_5755_PLUS(sc)) 5545 mode |= BGE_RXMODE_IPV6_ENABLE; 5546 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5547 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5548 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5549 DELAY(10); 5550 5551 /* 5552 * Set the number of good frames to receive after RX MBUF 5553 * Low Watermark has been reached. After the RX MAC receives 5554 * this number of frames, it will drop subsequent incoming 5555 * frames until the MBUF High Watermark is reached. 5556 */ 5557 if (BGE_IS_57765_PLUS(sc)) 5558 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5559 else 5560 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5561 5562 /* Clear MAC statistics. */ 5563 if (BGE_IS_5705_PLUS(sc)) 5564 bge_stats_clear_regs(sc); 5565 5566 /* Tell firmware we're alive. */ 5567 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5568 5569 #ifdef DEVICE_POLLING 5570 /* Disable interrupts if we are polling. */ 5571 if (if_getcapenable(ifp) & IFCAP_POLLING) { 5572 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5573 BGE_PCIMISCCTL_MASK_PCI_INTR); 5574 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5575 } else 5576 #endif 5577 5578 /* Enable host interrupts. */ 5579 { 5580 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5581 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5582 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5583 } 5584 5585 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5586 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 5587 5588 bge_ifmedia_upd_locked(ifp); 5589 5590 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5591 } 5592 5593 static void 5594 bge_init(void *xsc) 5595 { 5596 struct bge_softc *sc = xsc; 5597 5598 BGE_LOCK(sc); 5599 bge_init_locked(sc); 5600 BGE_UNLOCK(sc); 5601 } 5602 5603 /* 5604 * Set media options. 5605 */ 5606 static int 5607 bge_ifmedia_upd(if_t ifp) 5608 { 5609 struct bge_softc *sc = if_getsoftc(ifp); 5610 int res; 5611 5612 BGE_LOCK(sc); 5613 res = bge_ifmedia_upd_locked(ifp); 5614 BGE_UNLOCK(sc); 5615 5616 return (res); 5617 } 5618 5619 static int 5620 bge_ifmedia_upd_locked(if_t ifp) 5621 { 5622 struct bge_softc *sc = if_getsoftc(ifp); 5623 struct mii_data *mii; 5624 struct mii_softc *miisc; 5625 struct ifmedia *ifm; 5626 5627 BGE_LOCK_ASSERT(sc); 5628 5629 ifm = &sc->bge_ifmedia; 5630 5631 /* If this is a 1000baseX NIC, enable the TBI port. */ 5632 if (sc->bge_flags & BGE_FLAG_TBI) { 5633 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5634 return (EINVAL); 5635 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5636 case IFM_AUTO: 5637 /* 5638 * The BCM5704 ASIC appears to have a special 5639 * mechanism for programming the autoneg 5640 * advertisement registers in TBI mode. 5641 */ 5642 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5643 uint32_t sgdig; 5644 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5645 if (sgdig & BGE_SGDIGSTS_DONE) { 5646 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5647 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5648 sgdig |= BGE_SGDIGCFG_AUTO | 5649 BGE_SGDIGCFG_PAUSE_CAP | 5650 BGE_SGDIGCFG_ASYM_PAUSE; 5651 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5652 sgdig | BGE_SGDIGCFG_SEND); 5653 DELAY(5); 5654 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5655 } 5656 } 5657 break; 5658 case IFM_1000_SX: 5659 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5660 BGE_CLRBIT(sc, BGE_MAC_MODE, 5661 BGE_MACMODE_HALF_DUPLEX); 5662 } else { 5663 BGE_SETBIT(sc, BGE_MAC_MODE, 5664 BGE_MACMODE_HALF_DUPLEX); 5665 } 5666 DELAY(40); 5667 break; 5668 default: 5669 return (EINVAL); 5670 } 5671 return (0); 5672 } 5673 5674 sc->bge_link_evt++; 5675 mii = device_get_softc(sc->bge_miibus); 5676 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5677 PHY_RESET(miisc); 5678 mii_mediachg(mii); 5679 5680 /* 5681 * Force an interrupt so that we will call bge_link_upd 5682 * if needed and clear any pending link state attention. 5683 * Without this we are not getting any further interrupts 5684 * for link state changes and thus will not UP the link and 5685 * not be able to send in bge_start_locked. The only 5686 * way to get things working was to receive a packet and 5687 * get an RX intr. 5688 * bge_tick should help for fiber cards and we might not 5689 * need to do this here if BGE_FLAG_TBI is set but as 5690 * we poll for fiber anyway it should not harm. 5691 */ 5692 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5693 sc->bge_flags & BGE_FLAG_5788) 5694 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5695 else 5696 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5697 5698 return (0); 5699 } 5700 5701 /* 5702 * Report current media status. 5703 */ 5704 static void 5705 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 5706 { 5707 struct bge_softc *sc = if_getsoftc(ifp); 5708 struct mii_data *mii; 5709 5710 BGE_LOCK(sc); 5711 5712 if ((if_getflags(ifp) & IFF_UP) == 0) { 5713 BGE_UNLOCK(sc); 5714 return; 5715 } 5716 if (sc->bge_flags & BGE_FLAG_TBI) { 5717 ifmr->ifm_status = IFM_AVALID; 5718 ifmr->ifm_active = IFM_ETHER; 5719 if (CSR_READ_4(sc, BGE_MAC_STS) & 5720 BGE_MACSTAT_TBI_PCS_SYNCHED) 5721 ifmr->ifm_status |= IFM_ACTIVE; 5722 else { 5723 ifmr->ifm_active |= IFM_NONE; 5724 BGE_UNLOCK(sc); 5725 return; 5726 } 5727 ifmr->ifm_active |= IFM_1000_SX; 5728 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5729 ifmr->ifm_active |= IFM_HDX; 5730 else 5731 ifmr->ifm_active |= IFM_FDX; 5732 BGE_UNLOCK(sc); 5733 return; 5734 } 5735 5736 mii = device_get_softc(sc->bge_miibus); 5737 mii_pollstat(mii); 5738 ifmr->ifm_active = mii->mii_media_active; 5739 ifmr->ifm_status = mii->mii_media_status; 5740 5741 BGE_UNLOCK(sc); 5742 } 5743 5744 static int 5745 bge_ioctl(if_t ifp, u_long command, caddr_t data) 5746 { 5747 struct bge_softc *sc = if_getsoftc(ifp); 5748 struct ifreq *ifr = (struct ifreq *) data; 5749 struct mii_data *mii; 5750 int flags, mask, error = 0; 5751 5752 switch (command) { 5753 case SIOCSIFMTU: 5754 if (BGE_IS_JUMBO_CAPABLE(sc) || 5755 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5756 if (ifr->ifr_mtu < ETHERMIN || 5757 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5758 error = EINVAL; 5759 break; 5760 } 5761 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5762 error = EINVAL; 5763 break; 5764 } 5765 BGE_LOCK(sc); 5766 if (if_getmtu(ifp) != ifr->ifr_mtu) { 5767 if_setmtu(ifp, ifr->ifr_mtu); 5768 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5769 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5770 bge_init_locked(sc); 5771 } 5772 } 5773 BGE_UNLOCK(sc); 5774 break; 5775 case SIOCSIFFLAGS: 5776 BGE_LOCK(sc); 5777 if (if_getflags(ifp) & IFF_UP) { 5778 /* 5779 * If only the state of the PROMISC flag changed, 5780 * then just use the 'set promisc mode' command 5781 * instead of reinitializing the entire NIC. Doing 5782 * a full re-init means reloading the firmware and 5783 * waiting for it to start up, which may take a 5784 * second or two. Similarly for ALLMULTI. 5785 */ 5786 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5787 flags = if_getflags(ifp) ^ sc->bge_if_flags; 5788 if (flags & IFF_PROMISC) 5789 bge_setpromisc(sc); 5790 if (flags & IFF_ALLMULTI) 5791 bge_setmulti(sc); 5792 } else 5793 bge_init_locked(sc); 5794 } else { 5795 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5796 bge_stop(sc); 5797 } 5798 } 5799 sc->bge_if_flags = if_getflags(ifp); 5800 BGE_UNLOCK(sc); 5801 error = 0; 5802 break; 5803 case SIOCADDMULTI: 5804 case SIOCDELMULTI: 5805 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5806 BGE_LOCK(sc); 5807 bge_setmulti(sc); 5808 BGE_UNLOCK(sc); 5809 error = 0; 5810 } 5811 break; 5812 case SIOCSIFMEDIA: 5813 case SIOCGIFMEDIA: 5814 if (sc->bge_flags & BGE_FLAG_TBI) { 5815 error = ifmedia_ioctl(ifp, ifr, 5816 &sc->bge_ifmedia, command); 5817 } else { 5818 mii = device_get_softc(sc->bge_miibus); 5819 error = ifmedia_ioctl(ifp, ifr, 5820 &mii->mii_media, command); 5821 } 5822 break; 5823 case SIOCSIFCAP: 5824 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 5825 #ifdef DEVICE_POLLING 5826 if (mask & IFCAP_POLLING) { 5827 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5828 error = ether_poll_register(bge_poll, ifp); 5829 if (error) 5830 return (error); 5831 BGE_LOCK(sc); 5832 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5833 BGE_PCIMISCCTL_MASK_PCI_INTR); 5834 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5835 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 5836 BGE_UNLOCK(sc); 5837 } else { 5838 error = ether_poll_deregister(ifp); 5839 /* Enable interrupt even in error case */ 5840 BGE_LOCK(sc); 5841 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5842 BGE_PCIMISCCTL_MASK_PCI_INTR); 5843 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5844 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 5845 BGE_UNLOCK(sc); 5846 } 5847 } 5848 #endif 5849 if ((mask & IFCAP_TXCSUM) != 0 && 5850 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5851 if_togglecapenable(ifp, IFCAP_TXCSUM); 5852 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5853 if_sethwassistbits(ifp, 5854 sc->bge_csum_features, 0); 5855 else 5856 if_sethwassistbits(ifp, 0, 5857 sc->bge_csum_features); 5858 } 5859 5860 if ((mask & IFCAP_RXCSUM) != 0 && 5861 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5862 if_togglecapenable(ifp, IFCAP_RXCSUM); 5863 5864 if ((mask & IFCAP_TSO4) != 0 && 5865 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5866 if_togglecapenable(ifp, IFCAP_TSO4); 5867 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5868 if_sethwassistbits(ifp, CSUM_TSO, 0); 5869 else 5870 if_sethwassistbits(ifp, 0, CSUM_TSO); 5871 } 5872 5873 if (mask & IFCAP_VLAN_MTU) { 5874 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5875 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5876 bge_init(sc); 5877 } 5878 5879 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5880 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5881 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 5882 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5883 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5884 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5885 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5886 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5887 BGE_LOCK(sc); 5888 bge_setvlan(sc); 5889 BGE_UNLOCK(sc); 5890 } 5891 #ifdef VLAN_CAPABILITIES 5892 if_vlancap(ifp); 5893 #endif 5894 break; 5895 default: 5896 error = ether_ioctl(ifp, command, data); 5897 break; 5898 } 5899 5900 return (error); 5901 } 5902 5903 static void 5904 bge_watchdog(struct bge_softc *sc) 5905 { 5906 if_t ifp; 5907 uint32_t status; 5908 5909 BGE_LOCK_ASSERT(sc); 5910 5911 if (sc->bge_timer == 0 || --sc->bge_timer) 5912 return; 5913 5914 /* If pause frames are active then don't reset the hardware. */ 5915 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5916 status = CSR_READ_4(sc, BGE_RX_STS); 5917 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5918 /* 5919 * If link partner has us in XOFF state then wait for 5920 * the condition to clear. 5921 */ 5922 CSR_WRITE_4(sc, BGE_RX_STS, status); 5923 sc->bge_timer = BGE_TX_TIMEOUT; 5924 return; 5925 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5926 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5927 /* 5928 * If link partner has us in XOFF state then wait for 5929 * the condition to clear. 5930 */ 5931 CSR_WRITE_4(sc, BGE_RX_STS, status); 5932 sc->bge_timer = BGE_TX_TIMEOUT; 5933 return; 5934 } 5935 /* 5936 * Any other condition is unexpected and the controller 5937 * should be reset. 5938 */ 5939 } 5940 5941 ifp = sc->bge_ifp; 5942 5943 if_printf(ifp, "watchdog timeout -- resetting\n"); 5944 5945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5946 bge_init_locked(sc); 5947 5948 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 5949 } 5950 5951 static void 5952 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5953 { 5954 int i; 5955 5956 BGE_CLRBIT(sc, reg, bit); 5957 5958 for (i = 0; i < BGE_TIMEOUT; i++) { 5959 if ((CSR_READ_4(sc, reg) & bit) == 0) 5960 return; 5961 DELAY(100); 5962 } 5963 } 5964 5965 /* 5966 * Stop the adapter and free any mbufs allocated to the 5967 * RX and TX lists. 5968 */ 5969 static void 5970 bge_stop(struct bge_softc *sc) 5971 { 5972 if_t ifp; 5973 5974 BGE_LOCK_ASSERT(sc); 5975 5976 ifp = sc->bge_ifp; 5977 5978 callout_stop(&sc->bge_stat_ch); 5979 5980 /* Disable host interrupts. */ 5981 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5982 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5983 5984 /* 5985 * Tell firmware we're shutting down. 5986 */ 5987 bge_stop_fw(sc); 5988 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5989 5990 /* 5991 * Disable all of the receiver blocks. 5992 */ 5993 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5996 if (BGE_IS_5700_FAMILY(sc)) 5997 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5998 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6001 6002 /* 6003 * Disable all of the transmit blocks. 6004 */ 6005 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6006 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6008 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6009 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6010 if (BGE_IS_5700_FAMILY(sc)) 6011 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6012 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6013 6014 /* 6015 * Shut down all of the memory managers and related 6016 * state machines. 6017 */ 6018 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6019 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6020 if (BGE_IS_5700_FAMILY(sc)) 6021 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6022 6023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6024 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6025 if (!(BGE_IS_5705_PLUS(sc))) { 6026 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6027 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6028 } 6029 /* Update MAC statistics. */ 6030 if (BGE_IS_5705_PLUS(sc)) 6031 bge_stats_update_regs(sc); 6032 6033 bge_reset(sc); 6034 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6035 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6036 6037 /* 6038 * Keep the ASF firmware running if up. 6039 */ 6040 if (sc->bge_asf_mode & ASF_STACKUP) 6041 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6042 else 6043 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6044 6045 /* Free the RX lists. */ 6046 bge_free_rx_ring_std(sc); 6047 6048 /* Free jumbo RX list. */ 6049 if (BGE_IS_JUMBO_CAPABLE(sc)) 6050 bge_free_rx_ring_jumbo(sc); 6051 6052 /* Free TX buffers. */ 6053 bge_free_tx_ring(sc); 6054 6055 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6056 6057 /* Clear MAC's link state (PHY may still have link UP). */ 6058 if (bootverbose && sc->bge_link) 6059 if_printf(sc->bge_ifp, "link DOWN\n"); 6060 sc->bge_link = 0; 6061 6062 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 6063 } 6064 6065 /* 6066 * Stop all chip I/O so that the kernel's probe routines don't 6067 * get confused by errant DMAs when rebooting. 6068 */ 6069 static int 6070 bge_shutdown(device_t dev) 6071 { 6072 struct bge_softc *sc; 6073 6074 sc = device_get_softc(dev); 6075 BGE_LOCK(sc); 6076 bge_stop(sc); 6077 BGE_UNLOCK(sc); 6078 6079 return (0); 6080 } 6081 6082 static int 6083 bge_suspend(device_t dev) 6084 { 6085 struct bge_softc *sc; 6086 6087 sc = device_get_softc(dev); 6088 BGE_LOCK(sc); 6089 bge_stop(sc); 6090 BGE_UNLOCK(sc); 6091 6092 return (0); 6093 } 6094 6095 static int 6096 bge_resume(device_t dev) 6097 { 6098 struct bge_softc *sc; 6099 if_t ifp; 6100 6101 sc = device_get_softc(dev); 6102 BGE_LOCK(sc); 6103 ifp = sc->bge_ifp; 6104 if (if_getflags(ifp) & IFF_UP) { 6105 bge_init_locked(sc); 6106 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6107 bge_start_locked(ifp); 6108 } 6109 BGE_UNLOCK(sc); 6110 6111 return (0); 6112 } 6113 6114 static void 6115 bge_link_upd(struct bge_softc *sc) 6116 { 6117 struct mii_data *mii; 6118 uint32_t link, status; 6119 6120 BGE_LOCK_ASSERT(sc); 6121 6122 /* Clear 'pending link event' flag. */ 6123 sc->bge_link_evt = 0; 6124 6125 /* 6126 * Process link state changes. 6127 * Grrr. The link status word in the status block does 6128 * not work correctly on the BCM5700 rev AX and BX chips, 6129 * according to all available information. Hence, we have 6130 * to enable MII interrupts in order to properly obtain 6131 * async link changes. Unfortunately, this also means that 6132 * we have to read the MAC status register to detect link 6133 * changes, thereby adding an additional register access to 6134 * the interrupt handler. 6135 * 6136 * XXX: perhaps link state detection procedure used for 6137 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6138 */ 6139 6140 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6141 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6142 status = CSR_READ_4(sc, BGE_MAC_STS); 6143 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6144 mii = device_get_softc(sc->bge_miibus); 6145 mii_pollstat(mii); 6146 if (!sc->bge_link && 6147 mii->mii_media_status & IFM_ACTIVE && 6148 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6149 sc->bge_link++; 6150 if (bootverbose) 6151 if_printf(sc->bge_ifp, "link UP\n"); 6152 } else if (sc->bge_link && 6153 (!(mii->mii_media_status & IFM_ACTIVE) || 6154 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6155 sc->bge_link = 0; 6156 if (bootverbose) 6157 if_printf(sc->bge_ifp, "link DOWN\n"); 6158 } 6159 6160 /* Clear the interrupt. */ 6161 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6162 BGE_EVTENB_MI_INTERRUPT); 6163 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6164 BRGPHY_MII_ISR); 6165 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6166 BRGPHY_MII_IMR, BRGPHY_INTRS); 6167 } 6168 return; 6169 } 6170 6171 if (sc->bge_flags & BGE_FLAG_TBI) { 6172 status = CSR_READ_4(sc, BGE_MAC_STS); 6173 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6174 if (!sc->bge_link) { 6175 sc->bge_link++; 6176 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6177 BGE_CLRBIT(sc, BGE_MAC_MODE, 6178 BGE_MACMODE_TBI_SEND_CFGS); 6179 DELAY(40); 6180 } 6181 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6182 if (bootverbose) 6183 if_printf(sc->bge_ifp, "link UP\n"); 6184 if_link_state_change(sc->bge_ifp, 6185 LINK_STATE_UP); 6186 } 6187 } else if (sc->bge_link) { 6188 sc->bge_link = 0; 6189 if (bootverbose) 6190 if_printf(sc->bge_ifp, "link DOWN\n"); 6191 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6192 } 6193 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6194 /* 6195 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6196 * in status word always set. Workaround this bug by reading 6197 * PHY link status directly. 6198 */ 6199 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6200 6201 if (link != sc->bge_link || 6202 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6203 mii = device_get_softc(sc->bge_miibus); 6204 mii_pollstat(mii); 6205 if (!sc->bge_link && 6206 mii->mii_media_status & IFM_ACTIVE && 6207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6208 sc->bge_link++; 6209 if (bootverbose) 6210 if_printf(sc->bge_ifp, "link UP\n"); 6211 } else if (sc->bge_link && 6212 (!(mii->mii_media_status & IFM_ACTIVE) || 6213 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6214 sc->bge_link = 0; 6215 if (bootverbose) 6216 if_printf(sc->bge_ifp, "link DOWN\n"); 6217 } 6218 } 6219 } else { 6220 /* 6221 * For controllers that call mii_tick, we have to poll 6222 * link status. 6223 */ 6224 mii = device_get_softc(sc->bge_miibus); 6225 mii_pollstat(mii); 6226 bge_miibus_statchg(sc->bge_dev); 6227 } 6228 6229 /* Disable MAC attention when link is up. */ 6230 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6231 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6232 BGE_MACSTAT_LINK_CHANGED); 6233 } 6234 6235 static void 6236 bge_add_sysctls(struct bge_softc *sc) 6237 { 6238 struct sysctl_ctx_list *ctx; 6239 struct sysctl_oid_list *children; 6240 int unit; 6241 6242 ctx = device_get_sysctl_ctx(sc->bge_dev); 6243 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6244 6245 #ifdef BGE_REGISTER_DEBUG 6246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6247 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6248 "Debug Information"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6251 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6252 "MAC Register Read"); 6253 6254 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6255 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6256 "APE Register Read"); 6257 6258 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6259 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6260 "Memory Read"); 6261 6262 #endif 6263 6264 unit = device_get_unit(sc->bge_dev); 6265 /* 6266 * A common design characteristic for many Broadcom client controllers 6267 * is that they only support a single outstanding DMA read operation 6268 * on the PCIe bus. This means that it will take twice as long to fetch 6269 * a TX frame that is split into header and payload buffers as it does 6270 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6271 * these controllers, coalescing buffers to reduce the number of memory 6272 * reads is effective way to get maximum performance(about 940Mbps). 6273 * Without collapsing TX buffers the maximum TCP bulk transfer 6274 * performance is about 850Mbps. However forcing coalescing mbufs 6275 * consumes a lot of CPU cycles, so leave it off by default. 6276 */ 6277 sc->bge_forced_collapse = 0; 6278 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6279 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6280 "Number of fragmented TX buffers of a frame allowed before " 6281 "forced collapsing"); 6282 6283 sc->bge_msi = 1; 6284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6285 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 6286 6287 /* 6288 * It seems all Broadcom controllers have a bug that can generate UDP 6289 * datagrams with checksum value 0 when TX UDP checksum offloading is 6290 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6291 * Even though the probability of generating such UDP datagrams is 6292 * low, I don't want to see FreeBSD boxes to inject such datagrams 6293 * into network so disable UDP checksum offloading by default. Users 6294 * still override this behavior by setting a sysctl variable, 6295 * dev.bge.0.forced_udpcsum. 6296 */ 6297 sc->bge_forced_udpcsum = 0; 6298 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6299 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 6300 "Enable UDP checksum offloading even if controller can " 6301 "generate UDP checksum value 0"); 6302 6303 if (BGE_IS_5705_PLUS(sc)) 6304 bge_add_sysctl_stats_regs(sc, ctx, children); 6305 else 6306 bge_add_sysctl_stats(sc, ctx, children); 6307 } 6308 6309 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6310 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6311 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6312 desc) 6313 6314 static void 6315 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6316 struct sysctl_oid_list *parent) 6317 { 6318 struct sysctl_oid *tree; 6319 struct sysctl_oid_list *children, *schildren; 6320 6321 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6322 NULL, "BGE Statistics"); 6323 schildren = children = SYSCTL_CHILDREN(tree); 6324 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6325 children, COSFramesDroppedDueToFilters, 6326 "FramesDroppedDueToFilters"); 6327 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6328 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6329 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6330 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6331 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6332 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6333 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6334 children, ifInDiscards, "InputDiscards"); 6335 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6336 children, ifInErrors, "InputErrors"); 6337 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6338 children, nicRecvThresholdHit, "RecvThresholdHit"); 6339 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6340 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6341 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6342 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6343 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6344 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6345 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6346 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6347 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6348 children, nicRingStatusUpdate, "RingStatusUpdate"); 6349 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6350 children, nicInterrupts, "Interrupts"); 6351 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6352 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6353 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6354 children, nicSendThresholdHit, "SendThresholdHit"); 6355 6356 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6357 NULL, "BGE RX Statistics"); 6358 children = SYSCTL_CHILDREN(tree); 6359 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6360 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6361 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6362 children, rxstats.etherStatsFragments, "Fragments"); 6363 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6364 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6365 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6366 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6367 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6368 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6369 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6370 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6371 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6372 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6373 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6374 children, rxstats.xoffPauseFramesReceived, 6375 "xoffPauseFramesReceived"); 6376 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6377 children, rxstats.macControlFramesReceived, 6378 "ControlFramesReceived"); 6379 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6380 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6381 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6382 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6383 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6384 children, rxstats.etherStatsJabbers, "Jabbers"); 6385 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6386 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6387 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6388 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6390 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6391 6392 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6393 NULL, "BGE TX Statistics"); 6394 children = SYSCTL_CHILDREN(tree); 6395 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6396 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6397 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6398 children, txstats.etherStatsCollisions, "Collisions"); 6399 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6400 children, txstats.outXonSent, "XonSent"); 6401 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6402 children, txstats.outXoffSent, "XoffSent"); 6403 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6404 children, txstats.flowControlDone, "flowControlDone"); 6405 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6406 children, txstats.dot3StatsInternalMacTransmitErrors, 6407 "InternalMacTransmitErrors"); 6408 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6409 children, txstats.dot3StatsSingleCollisionFrames, 6410 "SingleCollisionFrames"); 6411 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6412 children, txstats.dot3StatsMultipleCollisionFrames, 6413 "MultipleCollisionFrames"); 6414 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6415 children, txstats.dot3StatsDeferredTransmissions, 6416 "DeferredTransmissions"); 6417 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6418 children, txstats.dot3StatsExcessiveCollisions, 6419 "ExcessiveCollisions"); 6420 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6421 children, txstats.dot3StatsLateCollisions, 6422 "LateCollisions"); 6423 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6424 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6426 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6427 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6428 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6429 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6430 children, txstats.dot3StatsCarrierSenseErrors, 6431 "CarrierSenseErrors"); 6432 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6433 children, txstats.ifOutDiscards, "Discards"); 6434 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6435 children, txstats.ifOutErrors, "Errors"); 6436 } 6437 6438 #undef BGE_SYSCTL_STAT 6439 6440 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6441 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6442 6443 static void 6444 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6445 struct sysctl_oid_list *parent) 6446 { 6447 struct sysctl_oid *tree; 6448 struct sysctl_oid_list *child, *schild; 6449 struct bge_mac_stats *stats; 6450 6451 stats = &sc->bge_mac_stats; 6452 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6453 NULL, "BGE Statistics"); 6454 schild = child = SYSCTL_CHILDREN(tree); 6455 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6456 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6457 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6458 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6459 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6460 &stats->DmaWriteHighPriQueueFull, 6461 "NIC DMA Write High Priority Queue Full"); 6462 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6463 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6465 &stats->InputDiscards, "Discarded Input Frames"); 6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6467 &stats->InputErrors, "Input Errors"); 6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6469 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6470 6471 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6472 NULL, "BGE RX Statistics"); 6473 child = SYSCTL_CHILDREN(tree); 6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6475 &stats->ifHCInOctets, "Inbound Octets"); 6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6477 &stats->etherStatsFragments, "Fragments"); 6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6479 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6481 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6483 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6485 &stats->dot3StatsFCSErrors, "FCS Errors"); 6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6487 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6489 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6491 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6493 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6495 &stats->xoffStateEntered, "XOFF State Entered"); 6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6497 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6499 &stats->etherStatsJabbers, "Jabbers"); 6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6501 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6502 6503 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6504 NULL, "BGE TX Statistics"); 6505 child = SYSCTL_CHILDREN(tree); 6506 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6507 &stats->ifHCOutOctets, "Outbound Octets"); 6508 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6509 &stats->etherStatsCollisions, "TX Collisions"); 6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6511 &stats->outXonSent, "XON Sent"); 6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6513 &stats->outXoffSent, "XOFF Sent"); 6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6515 &stats->dot3StatsInternalMacTransmitErrors, 6516 "Internal MAC TX Errors"); 6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6518 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6520 &stats->dot3StatsMultipleCollisionFrames, 6521 "Multiple Collision Frames"); 6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6523 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6525 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6527 &stats->dot3StatsLateCollisions, "Late Collisions"); 6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6529 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6531 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6533 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6534 } 6535 6536 #undef BGE_SYSCTL_STAT_ADD64 6537 6538 static int 6539 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6540 { 6541 struct bge_softc *sc; 6542 uint32_t result; 6543 int offset; 6544 6545 sc = (struct bge_softc *)arg1; 6546 offset = arg2; 6547 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6548 offsetof(bge_hostaddr, bge_addr_lo)); 6549 return (sysctl_handle_int(oidp, &result, 0, req)); 6550 } 6551 6552 #ifdef BGE_REGISTER_DEBUG 6553 static int 6554 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6555 { 6556 struct bge_softc *sc; 6557 uint16_t *sbdata; 6558 int error, result, sbsz; 6559 int i, j; 6560 6561 result = -1; 6562 error = sysctl_handle_int(oidp, &result, 0, req); 6563 if (error || (req->newptr == NULL)) 6564 return (error); 6565 6566 if (result == 1) { 6567 sc = (struct bge_softc *)arg1; 6568 6569 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6570 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6571 sbsz = BGE_STATUS_BLK_SZ; 6572 else 6573 sbsz = 32; 6574 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6575 printf("Status Block:\n"); 6576 BGE_LOCK(sc); 6577 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6578 sc->bge_cdata.bge_status_map, 6579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6580 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6581 printf("%06x:", i); 6582 for (j = 0; j < 8; j++) 6583 printf(" %04x", sbdata[i++]); 6584 printf("\n"); 6585 } 6586 6587 printf("Registers:\n"); 6588 for (i = 0x800; i < 0xA00; ) { 6589 printf("%06x:", i); 6590 for (j = 0; j < 8; j++) { 6591 printf(" %08x", CSR_READ_4(sc, i)); 6592 i += 4; 6593 } 6594 printf("\n"); 6595 } 6596 BGE_UNLOCK(sc); 6597 6598 printf("Hardware Flags:\n"); 6599 if (BGE_IS_5717_PLUS(sc)) 6600 printf(" - 5717 Plus\n"); 6601 if (BGE_IS_5755_PLUS(sc)) 6602 printf(" - 5755 Plus\n"); 6603 if (BGE_IS_575X_PLUS(sc)) 6604 printf(" - 575X Plus\n"); 6605 if (BGE_IS_5705_PLUS(sc)) 6606 printf(" - 5705 Plus\n"); 6607 if (BGE_IS_5714_FAMILY(sc)) 6608 printf(" - 5714 Family\n"); 6609 if (BGE_IS_5700_FAMILY(sc)) 6610 printf(" - 5700 Family\n"); 6611 if (sc->bge_flags & BGE_FLAG_JUMBO) 6612 printf(" - Supports Jumbo Frames\n"); 6613 if (sc->bge_flags & BGE_FLAG_PCIX) 6614 printf(" - PCI-X Bus\n"); 6615 if (sc->bge_flags & BGE_FLAG_PCIE) 6616 printf(" - PCI Express Bus\n"); 6617 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6618 printf(" - No 3 LEDs\n"); 6619 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6620 printf(" - RX Alignment Bug\n"); 6621 } 6622 6623 return (error); 6624 } 6625 6626 static int 6627 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6628 { 6629 struct bge_softc *sc; 6630 int error; 6631 uint16_t result; 6632 uint32_t val; 6633 6634 result = -1; 6635 error = sysctl_handle_int(oidp, &result, 0, req); 6636 if (error || (req->newptr == NULL)) 6637 return (error); 6638 6639 if (result < 0x8000) { 6640 sc = (struct bge_softc *)arg1; 6641 val = CSR_READ_4(sc, result); 6642 printf("reg 0x%06X = 0x%08X\n", result, val); 6643 } 6644 6645 return (error); 6646 } 6647 6648 static int 6649 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6650 { 6651 struct bge_softc *sc; 6652 int error; 6653 uint16_t result; 6654 uint32_t val; 6655 6656 result = -1; 6657 error = sysctl_handle_int(oidp, &result, 0, req); 6658 if (error || (req->newptr == NULL)) 6659 return (error); 6660 6661 if (result < 0x8000) { 6662 sc = (struct bge_softc *)arg1; 6663 val = APE_READ_4(sc, result); 6664 printf("reg 0x%06X = 0x%08X\n", result, val); 6665 } 6666 6667 return (error); 6668 } 6669 6670 static int 6671 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6672 { 6673 struct bge_softc *sc; 6674 int error; 6675 uint16_t result; 6676 uint32_t val; 6677 6678 result = -1; 6679 error = sysctl_handle_int(oidp, &result, 0, req); 6680 if (error || (req->newptr == NULL)) 6681 return (error); 6682 6683 if (result < 0x8000) { 6684 sc = (struct bge_softc *)arg1; 6685 val = bge_readmem_ind(sc, result); 6686 printf("mem 0x%06X = 0x%08X\n", result, val); 6687 } 6688 6689 return (error); 6690 } 6691 #endif 6692 6693 static int 6694 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6695 { 6696 6697 if (sc->bge_flags & BGE_FLAG_EADDR) 6698 return (1); 6699 6700 #ifdef __sparc64__ 6701 OF_getetheraddr(sc->bge_dev, ether_addr); 6702 return (0); 6703 #endif 6704 return (1); 6705 } 6706 6707 static int 6708 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6709 { 6710 uint32_t mac_addr; 6711 6712 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6713 if ((mac_addr >> 16) == 0x484b) { 6714 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6715 ether_addr[1] = (uint8_t)mac_addr; 6716 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6717 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6718 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6719 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6720 ether_addr[5] = (uint8_t)mac_addr; 6721 return (0); 6722 } 6723 return (1); 6724 } 6725 6726 static int 6727 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6728 { 6729 int mac_offset = BGE_EE_MAC_OFFSET; 6730 6731 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6732 mac_offset = BGE_EE_MAC_OFFSET_5906; 6733 6734 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6735 ETHER_ADDR_LEN)); 6736 } 6737 6738 static int 6739 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6740 { 6741 6742 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6743 return (1); 6744 6745 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6746 ETHER_ADDR_LEN)); 6747 } 6748 6749 static int 6750 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6751 { 6752 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6753 /* NOTE: Order is critical */ 6754 bge_get_eaddr_fw, 6755 bge_get_eaddr_mem, 6756 bge_get_eaddr_nvram, 6757 bge_get_eaddr_eeprom, 6758 NULL 6759 }; 6760 const bge_eaddr_fcn_t *func; 6761 6762 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6763 if ((*func)(sc, eaddr) == 0) 6764 break; 6765 } 6766 return (*func == NULL ? ENXIO : 0); 6767 } 6768 6769 static uint64_t 6770 bge_get_counter(if_t ifp, ift_counter cnt) 6771 { 6772 struct bge_softc *sc; 6773 struct bge_mac_stats *stats; 6774 6775 sc = if_getsoftc(ifp); 6776 if (!BGE_IS_5705_PLUS(sc)) 6777 return (if_get_counter_default(ifp, cnt)); 6778 stats = &sc->bge_mac_stats; 6779 6780 switch (cnt) { 6781 case IFCOUNTER_IERRORS: 6782 return (stats->NoMoreRxBDs + stats->InputDiscards + 6783 stats->InputErrors); 6784 case IFCOUNTER_COLLISIONS: 6785 return (stats->etherStatsCollisions); 6786 default: 6787 return (if_get_counter_default(ifp, cnt)); 6788 } 6789 } 6790