1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/endian.h> 71 #include <sys/systm.h> 72 #include <sys/sockio.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/queue.h> 78 79 #include <net/if.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_dl.h> 83 #include <net/if_media.h> 84 85 #include <net/bpf.h> 86 87 #include <net/if_types.h> 88 #include <net/if_vlan_var.h> 89 90 #include <netinet/in_systm.h> 91 #include <netinet/in.h> 92 #include <netinet/ip.h> 93 94 #include <machine/clock.h> /* for DELAY */ 95 #include <machine/bus_memio.h> 96 #include <machine/bus.h> 97 #include <machine/resource.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include "miidevs.h" 104 #include <dev/mii/brgphyreg.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 109 #include <dev/bge/if_bgereg.h> 110 111 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 112 113 MODULE_DEPEND(bge, pci, 1, 1, 1); 114 MODULE_DEPEND(bge, ether, 1, 1, 1); 115 MODULE_DEPEND(bge, miibus, 1, 1, 1); 116 117 /* "controller miibus0" required. See GENERIC if you get errors here. */ 118 #include "miibus_if.h" 119 120 /* 121 * Various supported device vendors/types and their names. Note: the 122 * spec seems to indicate that the hardware still has Alteon's vendor 123 * ID burned into it, though it will always be overriden by the vendor 124 * ID in the EEPROM. Just to be safe, we cover all possibilities. 125 */ 126 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 127 128 static struct bge_type bge_devs[] = { 129 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 130 "Broadcom BCM5700 Gigabit Ethernet" }, 131 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 132 "Broadcom BCM5701 Gigabit Ethernet" }, 133 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 134 "Broadcom BCM5700 Gigabit Ethernet" }, 135 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 136 "Broadcom BCM5701 Gigabit Ethernet" }, 137 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 138 "Broadcom BCM5702 Gigabit Ethernet" }, 139 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 140 "Broadcom BCM5702X Gigabit Ethernet" }, 141 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 142 "Broadcom BCM5703 Gigabit Ethernet" }, 143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 144 "Broadcom BCM5703X Gigabit Ethernet" }, 145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 146 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 148 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 150 "Broadcom BCM5705 Gigabit Ethernet" }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 152 "Broadcom BCM5705M Gigabit Ethernet" }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 154 "Broadcom BCM5705M Gigabit Ethernet" }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 156 "Broadcom BCM5782 Gigabit Ethernet" }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788, 158 "Broadcom BCM5788 Gigabit Ethernet" }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 160 "Broadcom BCM5901 Fast Ethernet" }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 162 "Broadcom BCM5901A2 Fast Ethernet" }, 163 { SK_VENDORID, SK_DEVICEID_ALTIMA, 164 "SysKonnect Gigabit Ethernet" }, 165 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 166 "Altima AC1000 Gigabit Ethernet" }, 167 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002, 168 "Altima AC1002 Gigabit Ethernet" }, 169 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 170 "Altima AC9100 Gigabit Ethernet" }, 171 { 0, 0, NULL } 172 }; 173 174 static int bge_probe (device_t); 175 static int bge_attach (device_t); 176 static int bge_detach (device_t); 177 static void bge_release_resources 178 (struct bge_softc *); 179 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 180 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 181 bus_size_t, int); 182 static int bge_dma_alloc (device_t); 183 static void bge_dma_free (struct bge_softc *); 184 185 static void bge_txeof (struct bge_softc *); 186 static void bge_rxeof (struct bge_softc *); 187 188 static void bge_tick_locked (struct bge_softc *); 189 static void bge_tick (void *); 190 static void bge_stats_update (struct bge_softc *); 191 static void bge_stats_update_regs 192 (struct bge_softc *); 193 static int bge_encap (struct bge_softc *, struct mbuf *, 194 u_int32_t *); 195 196 static void bge_intr (void *); 197 static void bge_start_locked (struct ifnet *); 198 static void bge_start (struct ifnet *); 199 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 200 static void bge_init_locked (struct bge_softc *); 201 static void bge_init (void *); 202 static void bge_stop (struct bge_softc *); 203 static void bge_watchdog (struct ifnet *); 204 static void bge_shutdown (device_t); 205 static int bge_ifmedia_upd (struct ifnet *); 206 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 207 208 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 209 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 210 211 static uint32_t bge_mchash (const uint8_t *); 212 static void bge_setmulti (struct bge_softc *); 213 214 static void bge_handle_events (struct bge_softc *); 215 static int bge_alloc_jumbo_mem (struct bge_softc *); 216 static void bge_free_jumbo_mem (struct bge_softc *); 217 static void *bge_jalloc (struct bge_softc *); 218 static void bge_jfree (void *, void *); 219 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 220 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 221 static int bge_init_rx_ring_std (struct bge_softc *); 222 static void bge_free_rx_ring_std (struct bge_softc *); 223 static int bge_init_rx_ring_jumbo (struct bge_softc *); 224 static void bge_free_rx_ring_jumbo (struct bge_softc *); 225 static void bge_free_tx_ring (struct bge_softc *); 226 static int bge_init_tx_ring (struct bge_softc *); 227 228 static int bge_chipinit (struct bge_softc *); 229 static int bge_blockinit (struct bge_softc *); 230 231 #ifdef notdef 232 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 233 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 234 static void bge_vpd_read (struct bge_softc *); 235 #endif 236 237 static u_int32_t bge_readmem_ind 238 (struct bge_softc *, int); 239 static void bge_writemem_ind (struct bge_softc *, int, int); 240 #ifdef notdef 241 static u_int32_t bge_readreg_ind 242 (struct bge_softc *, int); 243 #endif 244 static void bge_writereg_ind (struct bge_softc *, int, int); 245 246 static int bge_miibus_readreg (device_t, int, int); 247 static int bge_miibus_writereg (device_t, int, int, int); 248 static void bge_miibus_statchg (device_t); 249 250 static void bge_reset (struct bge_softc *); 251 252 static device_method_t bge_methods[] = { 253 /* Device interface */ 254 DEVMETHOD(device_probe, bge_probe), 255 DEVMETHOD(device_attach, bge_attach), 256 DEVMETHOD(device_detach, bge_detach), 257 DEVMETHOD(device_shutdown, bge_shutdown), 258 259 /* bus interface */ 260 DEVMETHOD(bus_print_child, bus_generic_print_child), 261 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 265 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 266 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 267 268 { 0, 0 } 269 }; 270 271 static driver_t bge_driver = { 272 "bge", 273 bge_methods, 274 sizeof(struct bge_softc) 275 }; 276 277 static devclass_t bge_devclass; 278 279 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 280 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 281 282 static u_int32_t 283 bge_readmem_ind(sc, off) 284 struct bge_softc *sc; 285 int off; 286 { 287 device_t dev; 288 289 dev = sc->bge_dev; 290 291 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 292 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 293 } 294 295 static void 296 bge_writemem_ind(sc, off, val) 297 struct bge_softc *sc; 298 int off, val; 299 { 300 device_t dev; 301 302 dev = sc->bge_dev; 303 304 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 305 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 306 307 return; 308 } 309 310 #ifdef notdef 311 static u_int32_t 312 bge_readreg_ind(sc, off) 313 struct bge_softc *sc; 314 int off; 315 { 316 device_t dev; 317 318 dev = sc->bge_dev; 319 320 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 321 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 322 } 323 #endif 324 325 static void 326 bge_writereg_ind(sc, off, val) 327 struct bge_softc *sc; 328 int off, val; 329 { 330 device_t dev; 331 332 dev = sc->bge_dev; 333 334 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 335 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 336 337 return; 338 } 339 340 /* 341 * Map a single buffer address. 342 */ 343 344 static void 345 bge_dma_map_addr(arg, segs, nseg, error) 346 void *arg; 347 bus_dma_segment_t *segs; 348 int nseg; 349 int error; 350 { 351 struct bge_dmamap_arg *ctx; 352 353 if (error) 354 return; 355 356 ctx = arg; 357 358 if (nseg > ctx->bge_maxsegs) { 359 ctx->bge_maxsegs = 0; 360 return; 361 } 362 363 ctx->bge_busaddr = segs->ds_addr; 364 365 return; 366 } 367 368 /* 369 * Map an mbuf chain into an TX ring. 370 */ 371 372 static void 373 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 374 void *arg; 375 bus_dma_segment_t *segs; 376 int nseg; 377 bus_size_t mapsize; 378 int error; 379 { 380 struct bge_dmamap_arg *ctx; 381 struct bge_tx_bd *d = NULL; 382 int i = 0, idx; 383 384 if (error) 385 return; 386 387 ctx = arg; 388 389 /* Signal error to caller if there's too many segments */ 390 if (nseg > ctx->bge_maxsegs) { 391 ctx->bge_maxsegs = 0; 392 return; 393 } 394 395 idx = ctx->bge_idx; 396 while(1) { 397 d = &ctx->bge_ring[idx]; 398 d->bge_addr.bge_addr_lo = 399 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 400 d->bge_addr.bge_addr_hi = 401 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 402 d->bge_len = htole16(segs[i].ds_len); 403 d->bge_flags = htole16(ctx->bge_flags); 404 i++; 405 if (i == nseg) 406 break; 407 BGE_INC(idx, BGE_TX_RING_CNT); 408 } 409 410 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 411 ctx->bge_maxsegs = nseg; 412 ctx->bge_idx = idx; 413 414 return; 415 } 416 417 418 #ifdef notdef 419 static u_int8_t 420 bge_vpd_readbyte(sc, addr) 421 struct bge_softc *sc; 422 int addr; 423 { 424 int i; 425 device_t dev; 426 u_int32_t val; 427 428 dev = sc->bge_dev; 429 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 430 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 431 DELAY(10); 432 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 433 break; 434 } 435 436 if (i == BGE_TIMEOUT) { 437 printf("bge%d: VPD read timed out\n", sc->bge_unit); 438 return(0); 439 } 440 441 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 442 443 return((val >> ((addr % 4) * 8)) & 0xFF); 444 } 445 446 static void 447 bge_vpd_read_res(sc, res, addr) 448 struct bge_softc *sc; 449 struct vpd_res *res; 450 int addr; 451 { 452 int i; 453 u_int8_t *ptr; 454 455 ptr = (u_int8_t *)res; 456 for (i = 0; i < sizeof(struct vpd_res); i++) 457 ptr[i] = bge_vpd_readbyte(sc, i + addr); 458 459 return; 460 } 461 462 static void 463 bge_vpd_read(sc) 464 struct bge_softc *sc; 465 { 466 int pos = 0, i; 467 struct vpd_res res; 468 469 if (sc->bge_vpd_prodname != NULL) 470 free(sc->bge_vpd_prodname, M_DEVBUF); 471 if (sc->bge_vpd_readonly != NULL) 472 free(sc->bge_vpd_readonly, M_DEVBUF); 473 sc->bge_vpd_prodname = NULL; 474 sc->bge_vpd_readonly = NULL; 475 476 bge_vpd_read_res(sc, &res, pos); 477 478 if (res.vr_id != VPD_RES_ID) { 479 printf("bge%d: bad VPD resource id: expected %x got %x\n", 480 sc->bge_unit, VPD_RES_ID, res.vr_id); 481 return; 482 } 483 484 pos += sizeof(res); 485 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 486 for (i = 0; i < res.vr_len; i++) 487 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 488 sc->bge_vpd_prodname[i] = '\0'; 489 pos += i; 490 491 bge_vpd_read_res(sc, &res, pos); 492 493 if (res.vr_id != VPD_RES_READ) { 494 printf("bge%d: bad VPD resource id: expected %x got %x\n", 495 sc->bge_unit, VPD_RES_READ, res.vr_id); 496 return; 497 } 498 499 pos += sizeof(res); 500 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 501 for (i = 0; i < res.vr_len + 1; i++) 502 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 503 504 return; 505 } 506 #endif 507 508 /* 509 * Read a byte of data stored in the EEPROM at address 'addr.' The 510 * BCM570x supports both the traditional bitbang interface and an 511 * auto access interface for reading the EEPROM. We use the auto 512 * access method. 513 */ 514 static u_int8_t 515 bge_eeprom_getbyte(sc, addr, dest) 516 struct bge_softc *sc; 517 int addr; 518 u_int8_t *dest; 519 { 520 int i; 521 u_int32_t byte = 0; 522 523 /* 524 * Enable use of auto EEPROM access so we can avoid 525 * having to use the bitbang method. 526 */ 527 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 528 529 /* Reset the EEPROM, load the clock period. */ 530 CSR_WRITE_4(sc, BGE_EE_ADDR, 531 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 532 DELAY(20); 533 534 /* Issue the read EEPROM command. */ 535 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 536 537 /* Wait for completion */ 538 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 539 DELAY(10); 540 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 541 break; 542 } 543 544 if (i == BGE_TIMEOUT) { 545 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 546 return(0); 547 } 548 549 /* Get result. */ 550 byte = CSR_READ_4(sc, BGE_EE_DATA); 551 552 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 553 554 return(0); 555 } 556 557 /* 558 * Read a sequence of bytes from the EEPROM. 559 */ 560 static int 561 bge_read_eeprom(sc, dest, off, cnt) 562 struct bge_softc *sc; 563 caddr_t dest; 564 int off; 565 int cnt; 566 { 567 int err = 0, i; 568 u_int8_t byte = 0; 569 570 for (i = 0; i < cnt; i++) { 571 err = bge_eeprom_getbyte(sc, off + i, &byte); 572 if (err) 573 break; 574 *(dest + i) = byte; 575 } 576 577 return(err ? 1 : 0); 578 } 579 580 static int 581 bge_miibus_readreg(dev, phy, reg) 582 device_t dev; 583 int phy, reg; 584 { 585 struct bge_softc *sc; 586 u_int32_t val, autopoll; 587 int i; 588 589 sc = device_get_softc(dev); 590 591 /* 592 * Broadcom's own driver always assumes the internal 593 * PHY is at GMII address 1. On some chips, the PHY responds 594 * to accesses at all addresses, which could cause us to 595 * bogusly attach the PHY 32 times at probe type. Always 596 * restricting the lookup to address 1 is simpler than 597 * trying to figure out which chips revisions should be 598 * special-cased. 599 */ 600 if (phy != 1) 601 return(0); 602 603 /* Reading with autopolling on may trigger PCI errors */ 604 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 605 if (autopoll & BGE_MIMODE_AUTOPOLL) { 606 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 607 DELAY(40); 608 } 609 610 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 611 BGE_MIPHY(phy)|BGE_MIREG(reg)); 612 613 for (i = 0; i < BGE_TIMEOUT; i++) { 614 val = CSR_READ_4(sc, BGE_MI_COMM); 615 if (!(val & BGE_MICOMM_BUSY)) 616 break; 617 } 618 619 if (i == BGE_TIMEOUT) { 620 printf("bge%d: PHY read timed out\n", sc->bge_unit); 621 val = 0; 622 goto done; 623 } 624 625 val = CSR_READ_4(sc, BGE_MI_COMM); 626 627 done: 628 if (autopoll & BGE_MIMODE_AUTOPOLL) { 629 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 630 DELAY(40); 631 } 632 633 if (val & BGE_MICOMM_READFAIL) 634 return(0); 635 636 return(val & 0xFFFF); 637 } 638 639 static int 640 bge_miibus_writereg(dev, phy, reg, val) 641 device_t dev; 642 int phy, reg, val; 643 { 644 struct bge_softc *sc; 645 u_int32_t autopoll; 646 int i; 647 648 sc = device_get_softc(dev); 649 650 /* Reading with autopolling on may trigger PCI errors */ 651 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 652 if (autopoll & BGE_MIMODE_AUTOPOLL) { 653 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 654 DELAY(40); 655 } 656 657 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 658 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 659 660 for (i = 0; i < BGE_TIMEOUT; i++) { 661 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 662 break; 663 } 664 665 if (autopoll & BGE_MIMODE_AUTOPOLL) { 666 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 667 DELAY(40); 668 } 669 670 if (i == BGE_TIMEOUT) { 671 printf("bge%d: PHY read timed out\n", sc->bge_unit); 672 return(0); 673 } 674 675 return(0); 676 } 677 678 static void 679 bge_miibus_statchg(dev) 680 device_t dev; 681 { 682 struct bge_softc *sc; 683 struct mii_data *mii; 684 685 sc = device_get_softc(dev); 686 mii = device_get_softc(sc->bge_miibus); 687 688 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 689 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 690 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 691 } else { 692 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 693 } 694 695 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 696 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 697 } else { 698 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 699 } 700 701 return; 702 } 703 704 /* 705 * Handle events that have triggered interrupts. 706 */ 707 static void 708 bge_handle_events(sc) 709 struct bge_softc *sc; 710 { 711 712 return; 713 } 714 715 /* 716 * Memory management for jumbo frames. 717 */ 718 719 static int 720 bge_alloc_jumbo_mem(sc) 721 struct bge_softc *sc; 722 { 723 caddr_t ptr; 724 register int i, error; 725 struct bge_jpool_entry *entry; 726 727 /* Create tag for jumbo buffer block */ 728 729 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 730 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 731 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 732 &sc->bge_cdata.bge_jumbo_tag); 733 734 if (error) { 735 printf("bge%d: could not allocate jumbo dma tag\n", 736 sc->bge_unit); 737 return (ENOMEM); 738 } 739 740 /* Allocate DMA'able memory for jumbo buffer block */ 741 742 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 743 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 744 &sc->bge_cdata.bge_jumbo_map); 745 746 if (error) 747 return (ENOMEM); 748 749 SLIST_INIT(&sc->bge_jfree_listhead); 750 SLIST_INIT(&sc->bge_jinuse_listhead); 751 752 /* 753 * Now divide it up into 9K pieces and save the addresses 754 * in an array. 755 */ 756 ptr = sc->bge_ldata.bge_jumbo_buf; 757 for (i = 0; i < BGE_JSLOTS; i++) { 758 sc->bge_cdata.bge_jslots[i] = ptr; 759 ptr += BGE_JLEN; 760 entry = malloc(sizeof(struct bge_jpool_entry), 761 M_DEVBUF, M_NOWAIT); 762 if (entry == NULL) { 763 bge_free_jumbo_mem(sc); 764 sc->bge_ldata.bge_jumbo_buf = NULL; 765 printf("bge%d: no memory for jumbo " 766 "buffer queue!\n", sc->bge_unit); 767 return(ENOBUFS); 768 } 769 entry->slot = i; 770 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 771 entry, jpool_entries); 772 } 773 774 return(0); 775 } 776 777 static void 778 bge_free_jumbo_mem(sc) 779 struct bge_softc *sc; 780 { 781 int i; 782 struct bge_jpool_entry *entry; 783 784 for (i = 0; i < BGE_JSLOTS; i++) { 785 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 786 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 787 free(entry, M_DEVBUF); 788 } 789 790 /* Destroy jumbo buffer block */ 791 792 if (sc->bge_ldata.bge_rx_jumbo_ring) 793 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 794 sc->bge_ldata.bge_jumbo_buf, 795 sc->bge_cdata.bge_jumbo_map); 796 797 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 798 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 799 sc->bge_cdata.bge_jumbo_map); 800 801 if (sc->bge_cdata.bge_jumbo_tag) 802 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 803 804 return; 805 } 806 807 /* 808 * Allocate a jumbo buffer. 809 */ 810 static void * 811 bge_jalloc(sc) 812 struct bge_softc *sc; 813 { 814 struct bge_jpool_entry *entry; 815 816 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 817 818 if (entry == NULL) { 819 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 820 return(NULL); 821 } 822 823 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 824 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 825 return(sc->bge_cdata.bge_jslots[entry->slot]); 826 } 827 828 /* 829 * Release a jumbo buffer. 830 */ 831 static void 832 bge_jfree(buf, args) 833 void *buf; 834 void *args; 835 { 836 struct bge_jpool_entry *entry; 837 struct bge_softc *sc; 838 int i; 839 840 /* Extract the softc struct pointer. */ 841 sc = (struct bge_softc *)args; 842 843 if (sc == NULL) 844 panic("bge_jfree: can't find softc pointer!"); 845 846 /* calculate the slot this buffer belongs to */ 847 848 i = ((vm_offset_t)buf 849 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 850 851 if ((i < 0) || (i >= BGE_JSLOTS)) 852 panic("bge_jfree: asked to free buffer that we don't manage!"); 853 854 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 855 if (entry == NULL) 856 panic("bge_jfree: buffer not in use!"); 857 entry->slot = i; 858 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 859 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 860 861 return; 862 } 863 864 865 /* 866 * Intialize a standard receive ring descriptor. 867 */ 868 static int 869 bge_newbuf_std(sc, i, m) 870 struct bge_softc *sc; 871 int i; 872 struct mbuf *m; 873 { 874 struct mbuf *m_new = NULL; 875 struct bge_rx_bd *r; 876 struct bge_dmamap_arg ctx; 877 int error; 878 879 if (m == NULL) { 880 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 881 if (m_new == NULL) { 882 return(ENOBUFS); 883 } 884 885 MCLGET(m_new, M_DONTWAIT); 886 if (!(m_new->m_flags & M_EXT)) { 887 m_freem(m_new); 888 return(ENOBUFS); 889 } 890 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 891 } else { 892 m_new = m; 893 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 894 m_new->m_data = m_new->m_ext.ext_buf; 895 } 896 897 if (!sc->bge_rx_alignment_bug) 898 m_adj(m_new, ETHER_ALIGN); 899 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 900 r = &sc->bge_ldata.bge_rx_std_ring[i]; 901 ctx.bge_maxsegs = 1; 902 ctx.sc = sc; 903 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 904 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 905 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 906 if (error || ctx.bge_maxsegs == 0) { 907 if (m == NULL) 908 m_freem(m_new); 909 return(ENOMEM); 910 } 911 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 912 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 913 r->bge_flags = htole16(BGE_RXBDFLAG_END); 914 r->bge_len = htole16(m_new->m_len); 915 r->bge_idx = htole16(i); 916 917 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 918 sc->bge_cdata.bge_rx_std_dmamap[i], 919 BUS_DMASYNC_PREREAD); 920 921 return(0); 922 } 923 924 /* 925 * Initialize a jumbo receive ring descriptor. This allocates 926 * a jumbo buffer from the pool managed internally by the driver. 927 */ 928 static int 929 bge_newbuf_jumbo(sc, i, m) 930 struct bge_softc *sc; 931 int i; 932 struct mbuf *m; 933 { 934 struct mbuf *m_new = NULL; 935 struct bge_rx_bd *r; 936 struct bge_dmamap_arg ctx; 937 int error; 938 939 if (m == NULL) { 940 caddr_t *buf = NULL; 941 942 /* Allocate the mbuf. */ 943 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 944 if (m_new == NULL) { 945 return(ENOBUFS); 946 } 947 948 /* Allocate the jumbo buffer */ 949 buf = bge_jalloc(sc); 950 if (buf == NULL) { 951 m_freem(m_new); 952 printf("bge%d: jumbo allocation failed " 953 "-- packet dropped!\n", sc->bge_unit); 954 return(ENOBUFS); 955 } 956 957 /* Attach the buffer to the mbuf. */ 958 m_new->m_data = (void *) buf; 959 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 960 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 961 (struct bge_softc *)sc, 0, EXT_NET_DRV); 962 } else { 963 m_new = m; 964 m_new->m_data = m_new->m_ext.ext_buf; 965 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 966 } 967 968 if (!sc->bge_rx_alignment_bug) 969 m_adj(m_new, ETHER_ALIGN); 970 /* Set up the descriptor. */ 971 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 972 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 973 ctx.bge_maxsegs = 1; 974 ctx.sc = sc; 975 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 976 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 977 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 978 if (error || ctx.bge_maxsegs == 0) { 979 if (m == NULL) 980 m_freem(m_new); 981 return(ENOMEM); 982 } 983 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 984 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 985 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 986 r->bge_len = htole16(m_new->m_len); 987 r->bge_idx = htole16(i); 988 989 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 990 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 991 BUS_DMASYNC_PREREAD); 992 993 return(0); 994 } 995 996 /* 997 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 998 * that's 1MB or memory, which is a lot. For now, we fill only the first 999 * 256 ring entries and hope that our CPU is fast enough to keep up with 1000 * the NIC. 1001 */ 1002 static int 1003 bge_init_rx_ring_std(sc) 1004 struct bge_softc *sc; 1005 { 1006 int i; 1007 1008 for (i = 0; i < BGE_SSLOTS; i++) { 1009 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1010 return(ENOBUFS); 1011 }; 1012 1013 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1014 sc->bge_cdata.bge_rx_std_ring_map, 1015 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1016 1017 sc->bge_std = i - 1; 1018 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1019 1020 return(0); 1021 } 1022 1023 static void 1024 bge_free_rx_ring_std(sc) 1025 struct bge_softc *sc; 1026 { 1027 int i; 1028 1029 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1030 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1031 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1032 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1033 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1034 sc->bge_cdata.bge_rx_std_dmamap[i]); 1035 } 1036 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1037 sizeof(struct bge_rx_bd)); 1038 } 1039 1040 return; 1041 } 1042 1043 static int 1044 bge_init_rx_ring_jumbo(sc) 1045 struct bge_softc *sc; 1046 { 1047 int i; 1048 struct bge_rcb *rcb; 1049 1050 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1051 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1052 return(ENOBUFS); 1053 }; 1054 1055 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1056 sc->bge_cdata.bge_rx_jumbo_ring_map, 1057 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1058 1059 sc->bge_jumbo = i - 1; 1060 1061 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1062 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1063 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1064 1065 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1066 1067 return(0); 1068 } 1069 1070 static void 1071 bge_free_rx_ring_jumbo(sc) 1072 struct bge_softc *sc; 1073 { 1074 int i; 1075 1076 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1077 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1078 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1079 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1080 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1081 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1082 } 1083 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1084 sizeof(struct bge_rx_bd)); 1085 } 1086 1087 return; 1088 } 1089 1090 static void 1091 bge_free_tx_ring(sc) 1092 struct bge_softc *sc; 1093 { 1094 int i; 1095 1096 if (sc->bge_ldata.bge_tx_ring == NULL) 1097 return; 1098 1099 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1100 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1101 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1102 sc->bge_cdata.bge_tx_chain[i] = NULL; 1103 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1104 sc->bge_cdata.bge_tx_dmamap[i]); 1105 } 1106 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1107 sizeof(struct bge_tx_bd)); 1108 } 1109 1110 return; 1111 } 1112 1113 static int 1114 bge_init_tx_ring(sc) 1115 struct bge_softc *sc; 1116 { 1117 sc->bge_txcnt = 0; 1118 sc->bge_tx_saved_considx = 0; 1119 1120 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1121 /* 5700 b2 errata */ 1122 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1123 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1124 1125 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1126 /* 5700 b2 errata */ 1127 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1128 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1129 1130 return(0); 1131 } 1132 1133 #define BGE_POLY 0xEDB88320 1134 1135 static uint32_t 1136 bge_mchash(addr) 1137 const uint8_t *addr; 1138 { 1139 uint32_t crc; 1140 int idx, bit; 1141 uint8_t data; 1142 1143 /* Compute CRC for the address value. */ 1144 crc = 0xFFFFFFFF; /* initial value */ 1145 1146 for (idx = 0; idx < 6; idx++) { 1147 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1148 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1149 } 1150 1151 return(crc & 0x7F); 1152 } 1153 1154 static void 1155 bge_setmulti(sc) 1156 struct bge_softc *sc; 1157 { 1158 struct ifnet *ifp; 1159 struct ifmultiaddr *ifma; 1160 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1161 int h, i; 1162 1163 BGE_LOCK_ASSERT(sc); 1164 1165 ifp = &sc->arpcom.ac_if; 1166 1167 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1168 for (i = 0; i < 4; i++) 1169 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1170 return; 1171 } 1172 1173 /* First, zot all the existing filters. */ 1174 for (i = 0; i < 4; i++) 1175 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1176 1177 /* Now program new ones. */ 1178 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1179 if (ifma->ifma_addr->sa_family != AF_LINK) 1180 continue; 1181 h = bge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1182 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1183 } 1184 1185 for (i = 0; i < 4; i++) 1186 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1187 1188 return; 1189 } 1190 1191 /* 1192 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1193 * self-test results. 1194 */ 1195 static int 1196 bge_chipinit(sc) 1197 struct bge_softc *sc; 1198 { 1199 int i; 1200 u_int32_t dma_rw_ctl; 1201 1202 /* Set endianness before we access any non-PCI registers. */ 1203 #if BYTE_ORDER == BIG_ENDIAN 1204 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1205 BGE_BIGENDIAN_INIT, 4); 1206 #else 1207 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1208 BGE_LITTLEENDIAN_INIT, 4); 1209 #endif 1210 1211 /* 1212 * Check the 'ROM failed' bit on the RX CPU to see if 1213 * self-tests passed. 1214 */ 1215 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1216 printf("bge%d: RX CPU self-diagnostics failed!\n", 1217 sc->bge_unit); 1218 return(ENODEV); 1219 } 1220 1221 /* Clear the MAC control register */ 1222 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1223 1224 /* 1225 * Clear the MAC statistics block in the NIC's 1226 * internal memory. 1227 */ 1228 for (i = BGE_STATS_BLOCK; 1229 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1230 BGE_MEMWIN_WRITE(sc, i, 0); 1231 1232 for (i = BGE_STATUS_BLOCK; 1233 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1234 BGE_MEMWIN_WRITE(sc, i, 0); 1235 1236 /* Set up the PCI DMA control register. */ 1237 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1238 BGE_PCISTATE_PCI_BUSMODE) { 1239 /* Conventional PCI bus */ 1240 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1241 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1242 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1243 (0x0F); 1244 } else { 1245 /* PCI-X bus */ 1246 /* 1247 * The 5704 uses a different encoding of read/write 1248 * watermarks. 1249 */ 1250 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1251 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1252 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1253 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1254 else 1255 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1256 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1257 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1258 (0x0F); 1259 1260 /* 1261 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1262 * for hardware bugs. 1263 */ 1264 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1265 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1266 u_int32_t tmp; 1267 1268 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1269 if (tmp == 0x6 || tmp == 0x7) 1270 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1271 } 1272 } 1273 1274 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1275 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1276 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1277 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1278 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1279 1280 /* 1281 * Set up general mode register. 1282 */ 1283 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1284 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1285 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1286 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1287 1288 /* 1289 * Disable memory write invalidate. Apparently it is not supported 1290 * properly by these devices. 1291 */ 1292 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1293 1294 #ifdef __brokenalpha__ 1295 /* 1296 * Must insure that we do not cross an 8K (bytes) boundary 1297 * for DMA reads. Our highest limit is 1K bytes. This is a 1298 * restriction on some ALPHA platforms with early revision 1299 * 21174 PCI chipsets, such as the AlphaPC 164lx 1300 */ 1301 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1302 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1303 #endif 1304 1305 /* Set the timer prescaler (always 66Mhz) */ 1306 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1307 1308 return(0); 1309 } 1310 1311 static int 1312 bge_blockinit(sc) 1313 struct bge_softc *sc; 1314 { 1315 struct bge_rcb *rcb; 1316 volatile struct bge_rcb *vrcb; 1317 int i; 1318 1319 /* 1320 * Initialize the memory window pointer register so that 1321 * we can access the first 32K of internal NIC RAM. This will 1322 * allow us to set up the TX send ring RCBs and the RX return 1323 * ring RCBs, plus other things which live in NIC memory. 1324 */ 1325 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1326 1327 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1328 1329 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1330 /* Configure mbuf memory pool */ 1331 if (sc->bge_extram) { 1332 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1333 BGE_EXT_SSRAM); 1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1335 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1336 else 1337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1338 } else { 1339 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1340 BGE_BUFFPOOL_1); 1341 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1343 else 1344 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1345 } 1346 1347 /* Configure DMA resource pool */ 1348 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1349 BGE_DMA_DESCRIPTORS); 1350 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1351 } 1352 1353 /* Configure mbuf pool watermarks */ 1354 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1357 } else { 1358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1360 } 1361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1362 1363 /* Configure DMA resource watermarks */ 1364 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1365 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1366 1367 /* Enable buffer manager */ 1368 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1369 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1370 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1371 1372 /* Poll for buffer manager start indication */ 1373 for (i = 0; i < BGE_TIMEOUT; i++) { 1374 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1375 break; 1376 DELAY(10); 1377 } 1378 1379 if (i == BGE_TIMEOUT) { 1380 printf("bge%d: buffer manager failed to start\n", 1381 sc->bge_unit); 1382 return(ENXIO); 1383 } 1384 } 1385 1386 /* Enable flow-through queues */ 1387 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1388 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1389 1390 /* Wait until queue initialization is complete */ 1391 for (i = 0; i < BGE_TIMEOUT; i++) { 1392 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1393 break; 1394 DELAY(10); 1395 } 1396 1397 if (i == BGE_TIMEOUT) { 1398 printf("bge%d: flow-through queue init failed\n", 1399 sc->bge_unit); 1400 return(ENXIO); 1401 } 1402 1403 /* Initialize the standard RX ring control block */ 1404 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1405 rcb->bge_hostaddr.bge_addr_lo = 1406 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1407 rcb->bge_hostaddr.bge_addr_hi = 1408 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1409 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1410 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1412 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1413 else 1414 rcb->bge_maxlen_flags = 1415 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1416 if (sc->bge_extram) 1417 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1418 else 1419 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1420 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1421 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1422 1423 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1424 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1425 1426 /* 1427 * Initialize the jumbo RX ring control block 1428 * We set the 'ring disabled' bit in the flags 1429 * field until we're actually ready to start 1430 * using this ring (i.e. once we set the MTU 1431 * high enough to require it). 1432 */ 1433 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1434 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1435 1436 rcb->bge_hostaddr.bge_addr_lo = 1437 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1438 rcb->bge_hostaddr.bge_addr_hi = 1439 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1440 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1441 sc->bge_cdata.bge_rx_jumbo_ring_map, 1442 BUS_DMASYNC_PREREAD); 1443 rcb->bge_maxlen_flags = 1444 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1445 BGE_RCB_FLAG_RING_DISABLED); 1446 if (sc->bge_extram) 1447 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1448 else 1449 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1450 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1451 rcb->bge_hostaddr.bge_addr_hi); 1452 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1453 rcb->bge_hostaddr.bge_addr_lo); 1454 1455 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1456 rcb->bge_maxlen_flags); 1457 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1458 1459 /* Set up dummy disabled mini ring RCB */ 1460 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1461 rcb->bge_maxlen_flags = 1462 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1463 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1464 rcb->bge_maxlen_flags); 1465 } 1466 1467 /* 1468 * Set the BD ring replentish thresholds. The recommended 1469 * values are 1/8th the number of descriptors allocated to 1470 * each ring. 1471 */ 1472 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1473 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1474 1475 /* 1476 * Disable all unused send rings by setting the 'ring disabled' 1477 * bit in the flags field of all the TX send ring control blocks. 1478 * These are located in NIC memory. 1479 */ 1480 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1481 BGE_SEND_RING_RCB); 1482 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1483 vrcb->bge_maxlen_flags = 1484 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1485 vrcb->bge_nicaddr = 0; 1486 vrcb++; 1487 } 1488 1489 /* Configure TX RCB 0 (we use only the first ring) */ 1490 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1491 BGE_SEND_RING_RCB); 1492 vrcb->bge_hostaddr.bge_addr_lo = 1493 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1494 vrcb->bge_hostaddr.bge_addr_hi = 1495 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1496 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1497 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1498 vrcb->bge_maxlen_flags = 1499 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1500 1501 /* Disable all unused RX return rings */ 1502 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1503 BGE_RX_RETURN_RING_RCB); 1504 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1505 vrcb->bge_hostaddr.bge_addr_hi = 0; 1506 vrcb->bge_hostaddr.bge_addr_lo = 0; 1507 vrcb->bge_maxlen_flags = 1508 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1509 BGE_RCB_FLAG_RING_DISABLED); 1510 vrcb->bge_nicaddr = 0; 1511 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1512 (i * (sizeof(u_int64_t))), 0); 1513 vrcb++; 1514 } 1515 1516 /* Initialize RX ring indexes */ 1517 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1518 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1519 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1520 1521 /* 1522 * Set up RX return ring 0 1523 * Note that the NIC address for RX return rings is 0x00000000. 1524 * The return rings live entirely within the host, so the 1525 * nicaddr field in the RCB isn't used. 1526 */ 1527 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1528 BGE_RX_RETURN_RING_RCB); 1529 vrcb->bge_hostaddr.bge_addr_lo = 1530 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1531 vrcb->bge_hostaddr.bge_addr_hi = 1532 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1533 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1534 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1535 vrcb->bge_nicaddr = 0x00000000; 1536 vrcb->bge_maxlen_flags = 1537 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1538 1539 /* Set random backoff seed for TX */ 1540 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1541 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1542 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1543 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1544 BGE_TX_BACKOFF_SEED_MASK); 1545 1546 /* Set inter-packet gap */ 1547 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1548 1549 /* 1550 * Specify which ring to use for packets that don't match 1551 * any RX rules. 1552 */ 1553 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1554 1555 /* 1556 * Configure number of RX lists. One interrupt distribution 1557 * list, sixteen active lists, one bad frames class. 1558 */ 1559 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1560 1561 /* Inialize RX list placement stats mask. */ 1562 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1563 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1564 1565 /* Disable host coalescing until we get it set up */ 1566 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1567 1568 /* Poll to make sure it's shut down. */ 1569 for (i = 0; i < BGE_TIMEOUT; i++) { 1570 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1571 break; 1572 DELAY(10); 1573 } 1574 1575 if (i == BGE_TIMEOUT) { 1576 printf("bge%d: host coalescing engine failed to idle\n", 1577 sc->bge_unit); 1578 return(ENXIO); 1579 } 1580 1581 /* Set up host coalescing defaults */ 1582 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1583 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1584 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1585 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1586 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1587 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1588 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1589 } 1590 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1591 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1592 1593 /* Set up address of statistics block */ 1594 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1595 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1596 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1597 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1598 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1599 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1600 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1601 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1602 } 1603 1604 /* Set up address of status block */ 1605 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1606 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1607 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1608 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1609 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1610 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1611 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1612 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1613 1614 /* Turn on host coalescing state machine */ 1615 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1616 1617 /* Turn on RX BD completion state machine and enable attentions */ 1618 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1619 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1620 1621 /* Turn on RX list placement state machine */ 1622 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1623 1624 /* Turn on RX list selector state machine. */ 1625 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1626 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1627 1628 /* Turn on DMA, clear stats */ 1629 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1630 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1631 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1632 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1633 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1634 1635 /* Set misc. local control, enable interrupts on attentions */ 1636 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1637 1638 #ifdef notdef 1639 /* Assert GPIO pins for PHY reset */ 1640 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1641 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1642 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1643 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1644 #endif 1645 1646 /* Turn on DMA completion state machine */ 1647 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1648 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1649 1650 /* Turn on write DMA state machine */ 1651 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1652 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1653 1654 /* Turn on read DMA state machine */ 1655 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1656 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1657 1658 /* Turn on RX data completion state machine */ 1659 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1660 1661 /* Turn on RX BD initiator state machine */ 1662 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1663 1664 /* Turn on RX data and RX BD initiator state machine */ 1665 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1666 1667 /* Turn on Mbuf cluster free state machine */ 1668 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1669 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1670 1671 /* Turn on send BD completion state machine */ 1672 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1673 1674 /* Turn on send data completion state machine */ 1675 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1676 1677 /* Turn on send data initiator state machine */ 1678 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1679 1680 /* Turn on send BD initiator state machine */ 1681 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1682 1683 /* Turn on send BD selector state machine */ 1684 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1685 1686 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1687 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1688 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1689 1690 /* ack/clear link change events */ 1691 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1692 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1693 BGE_MACSTAT_LINK_CHANGED); 1694 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1695 1696 /* Enable PHY auto polling (for MII/GMII only) */ 1697 if (sc->bge_tbi) { 1698 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1699 } else { 1700 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1701 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1702 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1703 BGE_EVTENB_MI_INTERRUPT); 1704 } 1705 1706 /* Enable link state change attentions. */ 1707 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1708 1709 return(0); 1710 } 1711 1712 /* 1713 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1714 * against our list and return its name if we find a match. Note 1715 * that since the Broadcom controller contains VPD support, we 1716 * can get the device name string from the controller itself instead 1717 * of the compiled-in string. This is a little slow, but it guarantees 1718 * we'll always announce the right product name. 1719 */ 1720 static int 1721 bge_probe(dev) 1722 device_t dev; 1723 { 1724 struct bge_type *t; 1725 struct bge_softc *sc; 1726 char *descbuf; 1727 1728 t = bge_devs; 1729 1730 sc = device_get_softc(dev); 1731 bzero(sc, sizeof(struct bge_softc)); 1732 sc->bge_unit = device_get_unit(dev); 1733 sc->bge_dev = dev; 1734 1735 while(t->bge_name != NULL) { 1736 if ((pci_get_vendor(dev) == t->bge_vid) && 1737 (pci_get_device(dev) == t->bge_did)) { 1738 #ifdef notdef 1739 bge_vpd_read(sc); 1740 device_set_desc(dev, sc->bge_vpd_prodname); 1741 #endif 1742 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1743 if (descbuf == NULL) 1744 return(ENOMEM); 1745 snprintf(descbuf, BGE_DEVDESC_MAX, 1746 "%s, ASIC rev. %#04x", t->bge_name, 1747 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1748 device_set_desc_copy(dev, descbuf); 1749 if (pci_get_subvendor(dev) == DELL_VENDORID) 1750 sc->bge_no_3_led = 1; 1751 free(descbuf, M_TEMP); 1752 return(0); 1753 } 1754 t++; 1755 } 1756 1757 return(ENXIO); 1758 } 1759 1760 static void 1761 bge_dma_free(sc) 1762 struct bge_softc *sc; 1763 { 1764 int i; 1765 1766 1767 /* Destroy DMA maps for RX buffers */ 1768 1769 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1770 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1771 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1772 sc->bge_cdata.bge_rx_std_dmamap[i]); 1773 } 1774 1775 /* Destroy DMA maps for jumbo RX buffers */ 1776 1777 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1778 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1779 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1780 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1781 } 1782 1783 /* Destroy DMA maps for TX buffers */ 1784 1785 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1786 if (sc->bge_cdata.bge_tx_dmamap[i]) 1787 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1788 sc->bge_cdata.bge_tx_dmamap[i]); 1789 } 1790 1791 if (sc->bge_cdata.bge_mtag) 1792 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1793 1794 1795 /* Destroy standard RX ring */ 1796 1797 if (sc->bge_ldata.bge_rx_std_ring) 1798 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1799 sc->bge_ldata.bge_rx_std_ring, 1800 sc->bge_cdata.bge_rx_std_ring_map); 1801 1802 if (sc->bge_cdata.bge_rx_std_ring_map) { 1803 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1804 sc->bge_cdata.bge_rx_std_ring_map); 1805 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1806 sc->bge_cdata.bge_rx_std_ring_map); 1807 } 1808 1809 if (sc->bge_cdata.bge_rx_std_ring_tag) 1810 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1811 1812 /* Destroy jumbo RX ring */ 1813 1814 if (sc->bge_ldata.bge_rx_jumbo_ring) 1815 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1816 sc->bge_ldata.bge_rx_jumbo_ring, 1817 sc->bge_cdata.bge_rx_jumbo_ring_map); 1818 1819 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1820 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1821 sc->bge_cdata.bge_rx_jumbo_ring_map); 1822 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1823 sc->bge_cdata.bge_rx_jumbo_ring_map); 1824 } 1825 1826 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1827 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1828 1829 /* Destroy RX return ring */ 1830 1831 if (sc->bge_ldata.bge_rx_return_ring) 1832 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1833 sc->bge_ldata.bge_rx_return_ring, 1834 sc->bge_cdata.bge_rx_return_ring_map); 1835 1836 if (sc->bge_cdata.bge_rx_return_ring_map) { 1837 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1838 sc->bge_cdata.bge_rx_return_ring_map); 1839 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1840 sc->bge_cdata.bge_rx_return_ring_map); 1841 } 1842 1843 if (sc->bge_cdata.bge_rx_return_ring_tag) 1844 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1845 1846 /* Destroy TX ring */ 1847 1848 if (sc->bge_ldata.bge_tx_ring) 1849 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1850 sc->bge_ldata.bge_tx_ring, 1851 sc->bge_cdata.bge_tx_ring_map); 1852 1853 if (sc->bge_cdata.bge_tx_ring_map) { 1854 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1855 sc->bge_cdata.bge_tx_ring_map); 1856 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1857 sc->bge_cdata.bge_tx_ring_map); 1858 } 1859 1860 if (sc->bge_cdata.bge_tx_ring_tag) 1861 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1862 1863 /* Destroy status block */ 1864 1865 if (sc->bge_ldata.bge_status_block) 1866 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1867 sc->bge_ldata.bge_status_block, 1868 sc->bge_cdata.bge_status_map); 1869 1870 if (sc->bge_cdata.bge_status_map) { 1871 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1872 sc->bge_cdata.bge_status_map); 1873 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1874 sc->bge_cdata.bge_status_map); 1875 } 1876 1877 if (sc->bge_cdata.bge_status_tag) 1878 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1879 1880 /* Destroy statistics block */ 1881 1882 if (sc->bge_ldata.bge_stats) 1883 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1884 sc->bge_ldata.bge_stats, 1885 sc->bge_cdata.bge_stats_map); 1886 1887 if (sc->bge_cdata.bge_stats_map) { 1888 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1889 sc->bge_cdata.bge_stats_map); 1890 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1891 sc->bge_cdata.bge_stats_map); 1892 } 1893 1894 if (sc->bge_cdata.bge_stats_tag) 1895 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1896 1897 /* Destroy the parent tag */ 1898 1899 if (sc->bge_cdata.bge_parent_tag) 1900 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1901 1902 return; 1903 } 1904 1905 static int 1906 bge_dma_alloc(dev) 1907 device_t dev; 1908 { 1909 struct bge_softc *sc; 1910 int nseg, i, error; 1911 struct bge_dmamap_arg ctx; 1912 1913 sc = device_get_softc(dev); 1914 1915 /* 1916 * Allocate the parent bus DMA tag appropriate for PCI. 1917 */ 1918 #define BGE_NSEG_NEW 32 1919 error = bus_dma_tag_create(NULL, /* parent */ 1920 PAGE_SIZE, 0, /* alignment, boundary */ 1921 BUS_SPACE_MAXADDR, /* lowaddr */ 1922 BUS_SPACE_MAXADDR_32BIT,/* highaddr */ 1923 NULL, NULL, /* filter, filterarg */ 1924 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1925 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1926 BUS_DMA_ALLOCNOW, /* flags */ 1927 NULL, NULL, /* lockfunc, lockarg */ 1928 &sc->bge_cdata.bge_parent_tag); 1929 1930 /* 1931 * Create tag for RX mbufs. 1932 */ 1933 nseg = 32; 1934 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, ETHER_ALIGN, 1935 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1936 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1937 &sc->bge_cdata.bge_mtag); 1938 1939 if (error) { 1940 device_printf(dev, "could not allocate dma tag\n"); 1941 return (ENOMEM); 1942 } 1943 1944 /* Create DMA maps for RX buffers */ 1945 1946 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1947 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1948 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1949 if (error) { 1950 device_printf(dev, "can't create DMA map for RX\n"); 1951 return(ENOMEM); 1952 } 1953 } 1954 1955 /* Create DMA maps for TX buffers */ 1956 1957 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1958 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1959 &sc->bge_cdata.bge_tx_dmamap[i]); 1960 if (error) { 1961 device_printf(dev, "can't create DMA map for RX\n"); 1962 return(ENOMEM); 1963 } 1964 } 1965 1966 /* Create tag for standard RX ring */ 1967 1968 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1969 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1970 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1971 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1972 1973 if (error) { 1974 device_printf(dev, "could not allocate dma tag\n"); 1975 return (ENOMEM); 1976 } 1977 1978 /* Allocate DMA'able memory for standard RX ring */ 1979 1980 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1981 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1982 &sc->bge_cdata.bge_rx_std_ring_map); 1983 if (error) 1984 return (ENOMEM); 1985 1986 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1987 1988 /* Load the address of the standard RX ring */ 1989 1990 ctx.bge_maxsegs = 1; 1991 ctx.sc = sc; 1992 1993 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1994 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1995 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1996 1997 if (error) 1998 return (ENOMEM); 1999 2000 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2001 2002 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2003 2004 /* 2005 * Create tag for jumbo mbufs. 2006 * This is really a bit of a kludge. We allocate a special 2007 * jumbo buffer pool which (thanks to the way our DMA 2008 * memory allocation works) will consist of contiguous 2009 * pages. This means that even though a jumbo buffer might 2010 * be larger than a page size, we don't really need to 2011 * map it into more than one DMA segment. However, the 2012 * default mbuf tag will result in multi-segment mappings, 2013 * so we have to create a special jumbo mbuf tag that 2014 * lets us get away with mapping the jumbo buffers as 2015 * a single segment. I think eventually the driver should 2016 * be changed so that it uses ordinary mbufs and cluster 2017 * buffers, i.e. jumbo frames can span multiple DMA 2018 * descriptors. But that's a project for another day. 2019 */ 2020 2021 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2022 ETHER_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2023 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2024 &sc->bge_cdata.bge_mtag_jumbo); 2025 2026 if (error) { 2027 device_printf(dev, "could not allocate dma tag\n"); 2028 return (ENOMEM); 2029 } 2030 2031 /* Create tag for jumbo RX ring */ 2032 2033 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2034 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2035 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2036 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2037 2038 if (error) { 2039 device_printf(dev, "could not allocate dma tag\n"); 2040 return (ENOMEM); 2041 } 2042 2043 /* Allocate DMA'able memory for jumbo RX ring */ 2044 2045 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2046 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2047 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2048 if (error) 2049 return (ENOMEM); 2050 2051 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2052 BGE_JUMBO_RX_RING_SZ); 2053 2054 /* Load the address of the jumbo RX ring */ 2055 2056 ctx.bge_maxsegs = 1; 2057 ctx.sc = sc; 2058 2059 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2060 sc->bge_cdata.bge_rx_jumbo_ring_map, 2061 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2062 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2063 2064 if (error) 2065 return (ENOMEM); 2066 2067 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2068 2069 /* Create DMA maps for jumbo RX buffers */ 2070 2071 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2072 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2073 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2074 if (error) { 2075 device_printf(dev, 2076 "can't create DMA map for RX\n"); 2077 return(ENOMEM); 2078 } 2079 } 2080 2081 } 2082 2083 /* Create tag for RX return ring */ 2084 2085 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2086 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2087 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2088 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2089 2090 if (error) { 2091 device_printf(dev, "could not allocate dma tag\n"); 2092 return (ENOMEM); 2093 } 2094 2095 /* Allocate DMA'able memory for RX return ring */ 2096 2097 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2098 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2099 &sc->bge_cdata.bge_rx_return_ring_map); 2100 if (error) 2101 return (ENOMEM); 2102 2103 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2104 BGE_RX_RTN_RING_SZ(sc)); 2105 2106 /* Load the address of the RX return ring */ 2107 2108 ctx.bge_maxsegs = 1; 2109 ctx.sc = sc; 2110 2111 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2112 sc->bge_cdata.bge_rx_return_ring_map, 2113 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2114 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2115 2116 if (error) 2117 return (ENOMEM); 2118 2119 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2120 2121 /* Create tag for TX ring */ 2122 2123 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2124 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2125 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2126 &sc->bge_cdata.bge_tx_ring_tag); 2127 2128 if (error) { 2129 device_printf(dev, "could not allocate dma tag\n"); 2130 return (ENOMEM); 2131 } 2132 2133 /* Allocate DMA'able memory for TX ring */ 2134 2135 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2136 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2137 &sc->bge_cdata.bge_tx_ring_map); 2138 if (error) 2139 return (ENOMEM); 2140 2141 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2142 2143 /* Load the address of the TX ring */ 2144 2145 ctx.bge_maxsegs = 1; 2146 ctx.sc = sc; 2147 2148 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2149 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2150 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2151 2152 if (error) 2153 return (ENOMEM); 2154 2155 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2156 2157 /* Create tag for status block */ 2158 2159 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2160 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2161 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2162 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2163 2164 if (error) { 2165 device_printf(dev, "could not allocate dma tag\n"); 2166 return (ENOMEM); 2167 } 2168 2169 /* Allocate DMA'able memory for status block */ 2170 2171 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2172 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2173 &sc->bge_cdata.bge_status_map); 2174 if (error) 2175 return (ENOMEM); 2176 2177 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2178 2179 /* Load the address of the status block */ 2180 2181 ctx.sc = sc; 2182 ctx.bge_maxsegs = 1; 2183 2184 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2185 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2186 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2187 2188 if (error) 2189 return (ENOMEM); 2190 2191 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2192 2193 /* Create tag for statistics block */ 2194 2195 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2196 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2197 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2198 &sc->bge_cdata.bge_stats_tag); 2199 2200 if (error) { 2201 device_printf(dev, "could not allocate dma tag\n"); 2202 return (ENOMEM); 2203 } 2204 2205 /* Allocate DMA'able memory for statistics block */ 2206 2207 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2208 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2209 &sc->bge_cdata.bge_stats_map); 2210 if (error) 2211 return (ENOMEM); 2212 2213 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2214 2215 /* Load the address of the statstics block */ 2216 2217 ctx.sc = sc; 2218 ctx.bge_maxsegs = 1; 2219 2220 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2221 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2222 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2223 2224 if (error) 2225 return (ENOMEM); 2226 2227 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2228 2229 return(0); 2230 } 2231 2232 static int 2233 bge_attach(dev) 2234 device_t dev; 2235 { 2236 struct ifnet *ifp; 2237 struct bge_softc *sc; 2238 u_int32_t hwcfg = 0; 2239 u_int32_t mac_addr = 0; 2240 int unit, error = 0, rid; 2241 2242 sc = device_get_softc(dev); 2243 unit = device_get_unit(dev); 2244 sc->bge_dev = dev; 2245 sc->bge_unit = unit; 2246 2247 /* 2248 * Map control/status registers. 2249 */ 2250 pci_enable_busmaster(dev); 2251 2252 rid = BGE_PCI_BAR0; 2253 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2254 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2255 2256 if (sc->bge_res == NULL) { 2257 printf ("bge%d: couldn't map memory\n", unit); 2258 error = ENXIO; 2259 goto fail; 2260 } 2261 2262 sc->bge_btag = rman_get_bustag(sc->bge_res); 2263 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2264 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2265 2266 /* Allocate interrupt */ 2267 rid = 0; 2268 2269 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2270 RF_SHAREABLE | RF_ACTIVE); 2271 2272 if (sc->bge_irq == NULL) { 2273 printf("bge%d: couldn't map interrupt\n", unit); 2274 error = ENXIO; 2275 goto fail; 2276 } 2277 2278 sc->bge_unit = unit; 2279 2280 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2281 2282 /* Try to reset the chip. */ 2283 bge_reset(sc); 2284 2285 if (bge_chipinit(sc)) { 2286 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2287 bge_release_resources(sc); 2288 error = ENXIO; 2289 goto fail; 2290 } 2291 2292 /* 2293 * Get station address from the EEPROM. 2294 */ 2295 mac_addr = bge_readmem_ind(sc, 0x0c14); 2296 if ((mac_addr >> 16) == 0x484b) { 2297 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2298 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2299 mac_addr = bge_readmem_ind(sc, 0x0c18); 2300 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2301 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2302 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2303 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2304 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2305 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2306 printf("bge%d: failed to read station address\n", unit); 2307 bge_release_resources(sc); 2308 error = ENXIO; 2309 goto fail; 2310 } 2311 2312 /* 2313 * A Broadcom chip was detected. Inform the world. 2314 */ 2315 printf("bge%d: Ethernet address: %6D\n", unit, 2316 sc->arpcom.ac_enaddr, ":"); 2317 2318 /* Save ASIC rev. */ 2319 2320 sc->bge_chipid = 2321 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2322 BGE_PCIMISCCTL_ASICREV; 2323 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2324 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2325 2326 /* 5705 limits RX return ring to 512 entries. */ 2327 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2328 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2329 else 2330 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2331 2332 if (bge_dma_alloc(dev)) { 2333 printf ("bge%d: failed to allocate DMA resources\n", 2334 sc->bge_unit); 2335 bge_release_resources(sc); 2336 error = ENXIO; 2337 goto fail; 2338 } 2339 2340 /* 2341 * Try to allocate memory for jumbo buffers. 2342 * The 5705 does not appear to support jumbo frames. 2343 */ 2344 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2345 if (bge_alloc_jumbo_mem(sc)) { 2346 printf("bge%d: jumbo buffer allocation " 2347 "failed\n", sc->bge_unit); 2348 bge_release_resources(sc); 2349 error = ENXIO; 2350 goto fail; 2351 } 2352 } 2353 2354 /* Set default tuneable values. */ 2355 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2356 sc->bge_rx_coal_ticks = 150; 2357 sc->bge_tx_coal_ticks = 150; 2358 sc->bge_rx_max_coal_bds = 64; 2359 sc->bge_tx_max_coal_bds = 128; 2360 2361 /* Set up ifnet structure */ 2362 ifp = &sc->arpcom.ac_if; 2363 ifp->if_softc = sc; 2364 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2365 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2366 ifp->if_ioctl = bge_ioctl; 2367 ifp->if_output = ether_output; 2368 ifp->if_start = bge_start; 2369 ifp->if_watchdog = bge_watchdog; 2370 ifp->if_init = bge_init; 2371 ifp->if_mtu = ETHERMTU; 2372 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 2373 ifp->if_hwassist = BGE_CSUM_FEATURES; 2374 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2375 IFCAP_VLAN_MTU; 2376 ifp->if_capenable = ifp->if_capabilities; 2377 2378 /* 2379 * Figure out what sort of media we have by checking the 2380 * hardware config word in the first 32k of NIC internal memory, 2381 * or fall back to examining the EEPROM if necessary. 2382 * Note: on some BCM5700 cards, this value appears to be unset. 2383 * If that's the case, we have to rely on identifying the NIC 2384 * by its PCI subsystem ID, as we do below for the SysKonnect 2385 * SK-9D41. 2386 */ 2387 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2388 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2389 else { 2390 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2391 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2392 hwcfg = ntohl(hwcfg); 2393 } 2394 2395 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2396 sc->bge_tbi = 1; 2397 2398 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2399 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2400 sc->bge_tbi = 1; 2401 2402 if (sc->bge_tbi) { 2403 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2404 bge_ifmedia_upd, bge_ifmedia_sts); 2405 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2406 ifmedia_add(&sc->bge_ifmedia, 2407 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2408 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2409 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2410 } else { 2411 /* 2412 * Do transceiver setup. 2413 */ 2414 if (mii_phy_probe(dev, &sc->bge_miibus, 2415 bge_ifmedia_upd, bge_ifmedia_sts)) { 2416 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2417 bge_release_resources(sc); 2418 bge_free_jumbo_mem(sc); 2419 error = ENXIO; 2420 goto fail; 2421 } 2422 } 2423 2424 /* 2425 * When using the BCM5701 in PCI-X mode, data corruption has 2426 * been observed in the first few bytes of some received packets. 2427 * Aligning the packet buffer in memory eliminates the corruption. 2428 * Unfortunately, this misaligns the packet payloads. On platforms 2429 * which do not support unaligned accesses, we will realign the 2430 * payloads by copying the received packets. 2431 */ 2432 switch (sc->bge_chipid) { 2433 case BGE_CHIPID_BCM5701_A0: 2434 case BGE_CHIPID_BCM5701_B0: 2435 case BGE_CHIPID_BCM5701_B2: 2436 case BGE_CHIPID_BCM5701_B5: 2437 /* If in PCI-X mode, work around the alignment bug. */ 2438 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2439 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2440 BGE_PCISTATE_PCI_BUSSPEED) 2441 sc->bge_rx_alignment_bug = 1; 2442 break; 2443 } 2444 2445 /* 2446 * Call MI attach routine. 2447 */ 2448 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2449 callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE); 2450 2451 /* 2452 * Hookup IRQ last. 2453 */ 2454 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2455 bge_intr, sc, &sc->bge_intrhand); 2456 2457 if (error) { 2458 bge_release_resources(sc); 2459 printf("bge%d: couldn't set up irq\n", unit); 2460 } 2461 2462 fail: 2463 return(error); 2464 } 2465 2466 static int 2467 bge_detach(dev) 2468 device_t dev; 2469 { 2470 struct bge_softc *sc; 2471 struct ifnet *ifp; 2472 2473 sc = device_get_softc(dev); 2474 ifp = &sc->arpcom.ac_if; 2475 2476 BGE_LOCK(sc); 2477 bge_stop(sc); 2478 bge_reset(sc); 2479 BGE_UNLOCK(sc); 2480 2481 ether_ifdetach(ifp); 2482 2483 if (sc->bge_tbi) { 2484 ifmedia_removeall(&sc->bge_ifmedia); 2485 } else { 2486 bus_generic_detach(dev); 2487 device_delete_child(dev, sc->bge_miibus); 2488 } 2489 2490 bge_release_resources(sc); 2491 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2492 bge_free_jumbo_mem(sc); 2493 2494 return(0); 2495 } 2496 2497 static void 2498 bge_release_resources(sc) 2499 struct bge_softc *sc; 2500 { 2501 device_t dev; 2502 2503 dev = sc->bge_dev; 2504 2505 if (sc->bge_vpd_prodname != NULL) 2506 free(sc->bge_vpd_prodname, M_DEVBUF); 2507 2508 if (sc->bge_vpd_readonly != NULL) 2509 free(sc->bge_vpd_readonly, M_DEVBUF); 2510 2511 if (sc->bge_intrhand != NULL) 2512 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2513 2514 if (sc->bge_irq != NULL) 2515 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2516 2517 if (sc->bge_res != NULL) 2518 bus_release_resource(dev, SYS_RES_MEMORY, 2519 BGE_PCI_BAR0, sc->bge_res); 2520 2521 bge_dma_free(sc); 2522 2523 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2524 BGE_LOCK_DESTROY(sc); 2525 2526 return; 2527 } 2528 2529 static void 2530 bge_reset(sc) 2531 struct bge_softc *sc; 2532 { 2533 device_t dev; 2534 u_int32_t cachesize, command, pcistate; 2535 int i, val = 0; 2536 2537 dev = sc->bge_dev; 2538 2539 /* Save some important PCI state. */ 2540 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2541 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2542 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2543 2544 pci_write_config(dev, BGE_PCI_MISC_CTL, 2545 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2546 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2547 2548 /* Issue global reset */ 2549 bge_writereg_ind(sc, BGE_MISC_CFG, 2550 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2551 2552 DELAY(1000); 2553 2554 /* Reset some of the PCI state that got zapped by reset */ 2555 pci_write_config(dev, BGE_PCI_MISC_CTL, 2556 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2557 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2558 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2559 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2560 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2561 2562 /* 2563 * Prevent PXE restart: write a magic number to the 2564 * general communications memory at 0xB50. 2565 */ 2566 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2567 /* 2568 * Poll the value location we just wrote until 2569 * we see the 1's complement of the magic number. 2570 * This indicates that the firmware initialization 2571 * is complete. 2572 */ 2573 for (i = 0; i < BGE_TIMEOUT; i++) { 2574 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2575 if (val == ~BGE_MAGIC_NUMBER) 2576 break; 2577 DELAY(10); 2578 } 2579 2580 if (i == BGE_TIMEOUT) { 2581 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2582 return; 2583 } 2584 2585 /* 2586 * XXX Wait for the value of the PCISTATE register to 2587 * return to its original pre-reset state. This is a 2588 * fairly good indicator of reset completion. If we don't 2589 * wait for the reset to fully complete, trying to read 2590 * from the device's non-PCI registers may yield garbage 2591 * results. 2592 */ 2593 for (i = 0; i < BGE_TIMEOUT; i++) { 2594 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2595 break; 2596 DELAY(10); 2597 } 2598 2599 /* Enable memory arbiter. */ 2600 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2601 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2602 2603 /* Fix up byte swapping */ 2604 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2605 BGE_MODECTL_BYTESWAP_DATA); 2606 2607 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2608 2609 DELAY(10000); 2610 2611 return; 2612 } 2613 2614 /* 2615 * Frame reception handling. This is called if there's a frame 2616 * on the receive return list. 2617 * 2618 * Note: we have to be able to handle two possibilities here: 2619 * 1) the frame is from the jumbo recieve ring 2620 * 2) the frame is from the standard receive ring 2621 */ 2622 2623 static void 2624 bge_rxeof(sc) 2625 struct bge_softc *sc; 2626 { 2627 struct ifnet *ifp; 2628 int stdcnt = 0, jumbocnt = 0; 2629 2630 BGE_LOCK_ASSERT(sc); 2631 2632 ifp = &sc->arpcom.ac_if; 2633 2634 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2635 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2636 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2637 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2638 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2639 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2640 sc->bge_cdata.bge_rx_jumbo_ring_map, 2641 BUS_DMASYNC_POSTREAD); 2642 } 2643 2644 while(sc->bge_rx_saved_considx != 2645 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2646 struct bge_rx_bd *cur_rx; 2647 u_int32_t rxidx; 2648 struct ether_header *eh; 2649 struct mbuf *m = NULL; 2650 u_int16_t vlan_tag = 0; 2651 int have_tag = 0; 2652 2653 cur_rx = 2654 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2655 2656 rxidx = cur_rx->bge_idx; 2657 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2658 2659 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2660 have_tag = 1; 2661 vlan_tag = cur_rx->bge_vlan_tag; 2662 } 2663 2664 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2665 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2666 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2667 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2668 BUS_DMASYNC_POSTREAD); 2669 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2670 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2671 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2672 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2673 jumbocnt++; 2674 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2675 ifp->if_ierrors++; 2676 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2677 continue; 2678 } 2679 if (bge_newbuf_jumbo(sc, 2680 sc->bge_jumbo, NULL) == ENOBUFS) { 2681 ifp->if_ierrors++; 2682 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2683 continue; 2684 } 2685 } else { 2686 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2687 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2688 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2689 BUS_DMASYNC_POSTREAD); 2690 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2691 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2692 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2693 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2694 stdcnt++; 2695 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2696 ifp->if_ierrors++; 2697 bge_newbuf_std(sc, sc->bge_std, m); 2698 continue; 2699 } 2700 if (bge_newbuf_std(sc, sc->bge_std, 2701 NULL) == ENOBUFS) { 2702 ifp->if_ierrors++; 2703 bge_newbuf_std(sc, sc->bge_std, m); 2704 continue; 2705 } 2706 } 2707 2708 ifp->if_ipackets++; 2709 #ifndef __i386__ 2710 /* 2711 * The i386 allows unaligned accesses, but for other 2712 * platforms we must make sure the payload is aligned. 2713 */ 2714 if (sc->bge_rx_alignment_bug) { 2715 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2716 cur_rx->bge_len); 2717 m->m_data += ETHER_ALIGN; 2718 } 2719 #endif 2720 eh = mtod(m, struct ether_header *); 2721 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2722 m->m_pkthdr.rcvif = ifp; 2723 2724 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2725 if (ifp->if_hwassist) { 2726 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2727 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2728 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2729 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2730 m->m_pkthdr.csum_data = 2731 cur_rx->bge_tcp_udp_csum; 2732 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2733 } 2734 } 2735 #endif 2736 2737 /* 2738 * If we received a packet with a vlan tag, 2739 * attach that information to the packet. 2740 */ 2741 if (have_tag) 2742 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2743 2744 BGE_UNLOCK(sc); 2745 (*ifp->if_input)(ifp, m); 2746 BGE_LOCK(sc); 2747 } 2748 2749 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2750 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2751 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2752 sc->bge_cdata.bge_rx_std_ring_map, 2753 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2754 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2755 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2756 sc->bge_cdata.bge_rx_jumbo_ring_map, 2757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2758 } 2759 2760 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2761 if (stdcnt) 2762 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2763 if (jumbocnt) 2764 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2765 2766 return; 2767 } 2768 2769 static void 2770 bge_txeof(sc) 2771 struct bge_softc *sc; 2772 { 2773 struct bge_tx_bd *cur_tx = NULL; 2774 struct ifnet *ifp; 2775 2776 BGE_LOCK_ASSERT(sc); 2777 2778 ifp = &sc->arpcom.ac_if; 2779 2780 /* 2781 * Go through our tx ring and free mbufs for those 2782 * frames that have been sent. 2783 */ 2784 while (sc->bge_tx_saved_considx != 2785 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2786 u_int32_t idx = 0; 2787 2788 idx = sc->bge_tx_saved_considx; 2789 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2790 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2791 ifp->if_opackets++; 2792 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2793 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2794 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2795 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2796 sc->bge_cdata.bge_tx_dmamap[idx]); 2797 } 2798 sc->bge_txcnt--; 2799 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2800 ifp->if_timer = 0; 2801 } 2802 2803 if (cur_tx != NULL) 2804 ifp->if_flags &= ~IFF_OACTIVE; 2805 2806 return; 2807 } 2808 2809 static void 2810 bge_intr(xsc) 2811 void *xsc; 2812 { 2813 struct bge_softc *sc; 2814 struct ifnet *ifp; 2815 u_int32_t statusword; 2816 u_int32_t status; 2817 2818 sc = xsc; 2819 ifp = &sc->arpcom.ac_if; 2820 2821 BGE_LOCK(sc); 2822 2823 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2824 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2825 2826 statusword = 2827 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2828 2829 #ifdef notdef 2830 /* Avoid this for now -- checking this register is expensive. */ 2831 /* Make sure this is really our interrupt. */ 2832 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2833 return; 2834 #endif 2835 /* Ack interrupt and stop others from occuring. */ 2836 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2837 2838 /* 2839 * Process link state changes. 2840 * Grrr. The link status word in the status block does 2841 * not work correctly on the BCM5700 rev AX and BX chips, 2842 * according to all available information. Hence, we have 2843 * to enable MII interrupts in order to properly obtain 2844 * async link changes. Unfortunately, this also means that 2845 * we have to read the MAC status register to detect link 2846 * changes, thereby adding an additional register access to 2847 * the interrupt handler. 2848 */ 2849 2850 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2851 2852 status = CSR_READ_4(sc, BGE_MAC_STS); 2853 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2854 sc->bge_link = 0; 2855 callout_stop(&sc->bge_stat_ch); 2856 bge_tick_locked(sc); 2857 /* Clear the interrupt */ 2858 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2859 BGE_EVTENB_MI_INTERRUPT); 2860 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2861 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2862 BRGPHY_INTRS); 2863 } 2864 } else { 2865 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2866 /* 2867 * Sometimes PCS encoding errors are detected in 2868 * TBI mode (on fiber NICs), and for some reason 2869 * the chip will signal them as link changes. 2870 * If we get a link change event, but the 'PCS 2871 * encoding error' bit in the MAC status register 2872 * is set, don't bother doing a link check. 2873 * This avoids spurious "gigabit link up" messages 2874 * that sometimes appear on fiber NICs during 2875 * periods of heavy traffic. (There should be no 2876 * effect on copper NICs.) 2877 */ 2878 status = CSR_READ_4(sc, BGE_MAC_STS); 2879 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2880 BGE_MACSTAT_MI_COMPLETE))) { 2881 sc->bge_link = 0; 2882 callout_stop(&sc->bge_stat_ch); 2883 bge_tick_locked(sc); 2884 } 2885 /* Clear the interrupt */ 2886 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2887 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2888 BGE_MACSTAT_LINK_CHANGED); 2889 2890 /* Force flush the status block cached by PCI bridge */ 2891 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2892 } 2893 } 2894 2895 if (ifp->if_flags & IFF_RUNNING) { 2896 /* Check RX return ring producer/consumer */ 2897 bge_rxeof(sc); 2898 2899 /* Check TX ring producer/consumer */ 2900 bge_txeof(sc); 2901 } 2902 2903 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2904 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2905 2906 bge_handle_events(sc); 2907 2908 /* Re-enable interrupts. */ 2909 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2910 2911 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2912 bge_start_locked(ifp); 2913 2914 BGE_UNLOCK(sc); 2915 2916 return; 2917 } 2918 2919 static void 2920 bge_tick_locked(sc) 2921 struct bge_softc *sc; 2922 { 2923 struct mii_data *mii = NULL; 2924 struct ifmedia *ifm = NULL; 2925 struct ifnet *ifp; 2926 2927 ifp = &sc->arpcom.ac_if; 2928 2929 BGE_LOCK_ASSERT(sc); 2930 2931 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2932 bge_stats_update_regs(sc); 2933 else 2934 bge_stats_update(sc); 2935 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 2936 if (sc->bge_link) 2937 return; 2938 2939 if (sc->bge_tbi) { 2940 ifm = &sc->bge_ifmedia; 2941 if (CSR_READ_4(sc, BGE_MAC_STS) & 2942 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2943 sc->bge_link++; 2944 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2945 printf("bge%d: gigabit link up\n", sc->bge_unit); 2946 if (ifp->if_snd.ifq_head != NULL) 2947 bge_start_locked(ifp); 2948 } 2949 return; 2950 } 2951 2952 mii = device_get_softc(sc->bge_miibus); 2953 mii_tick(mii); 2954 2955 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2956 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2957 sc->bge_link++; 2958 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2959 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2960 printf("bge%d: gigabit link up\n", 2961 sc->bge_unit); 2962 if (ifp->if_snd.ifq_head != NULL) 2963 bge_start_locked(ifp); 2964 } 2965 2966 return; 2967 } 2968 2969 static void 2970 bge_tick(xsc) 2971 void *xsc; 2972 { 2973 struct bge_softc *sc; 2974 2975 sc = xsc; 2976 2977 BGE_LOCK(sc); 2978 bge_tick_locked(sc); 2979 BGE_UNLOCK(sc); 2980 } 2981 2982 static void 2983 bge_stats_update_regs(sc) 2984 struct bge_softc *sc; 2985 { 2986 struct ifnet *ifp; 2987 struct bge_mac_stats_regs stats; 2988 u_int32_t *s; 2989 int i; 2990 2991 ifp = &sc->arpcom.ac_if; 2992 2993 s = (u_int32_t *)&stats; 2994 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2995 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2996 s++; 2997 } 2998 2999 ifp->if_collisions += 3000 (stats.dot3StatsSingleCollisionFrames + 3001 stats.dot3StatsMultipleCollisionFrames + 3002 stats.dot3StatsExcessiveCollisions + 3003 stats.dot3StatsLateCollisions) - 3004 ifp->if_collisions; 3005 3006 return; 3007 } 3008 3009 static void 3010 bge_stats_update(sc) 3011 struct bge_softc *sc; 3012 { 3013 struct ifnet *ifp; 3014 struct bge_stats *stats; 3015 3016 ifp = &sc->arpcom.ac_if; 3017 3018 stats = (struct bge_stats *)(sc->bge_vhandle + 3019 BGE_MEMWIN_START + BGE_STATS_BLOCK); 3020 3021 ifp->if_collisions += 3022 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3023 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3024 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3025 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3026 ifp->if_collisions; 3027 3028 #ifdef notdef 3029 ifp->if_collisions += 3030 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3031 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3032 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3033 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3034 ifp->if_collisions; 3035 #endif 3036 3037 return; 3038 } 3039 3040 /* 3041 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3042 * pointers to descriptors. 3043 */ 3044 static int 3045 bge_encap(sc, m_head, txidx) 3046 struct bge_softc *sc; 3047 struct mbuf *m_head; 3048 u_int32_t *txidx; 3049 { 3050 struct bge_tx_bd *f = NULL; 3051 u_int16_t csum_flags = 0; 3052 struct m_tag *mtag; 3053 struct bge_dmamap_arg ctx; 3054 bus_dmamap_t map; 3055 int error; 3056 3057 3058 if (m_head->m_pkthdr.csum_flags) { 3059 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3060 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3061 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3062 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3063 if (m_head->m_flags & M_LASTFRAG) 3064 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3065 else if (m_head->m_flags & M_FRAG) 3066 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3067 } 3068 3069 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3070 3071 ctx.sc = sc; 3072 ctx.bge_idx = *txidx; 3073 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3074 ctx.bge_flags = csum_flags; 3075 /* 3076 * Sanity check: avoid coming within 16 descriptors 3077 * of the end of the ring. 3078 */ 3079 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3080 3081 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3082 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3083 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3084 3085 if (error || ctx.bge_maxsegs == 0 /*|| 3086 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3087 return (ENOBUFS); 3088 3089 /* 3090 * Insure that the map for this transmission 3091 * is placed at the array index of the last descriptor 3092 * in this chain. 3093 */ 3094 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3095 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3096 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3097 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3098 sc->bge_txcnt += ctx.bge_maxsegs; 3099 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3100 if (mtag != NULL) { 3101 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3102 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3103 } else { 3104 f->bge_vlan_tag = 0; 3105 } 3106 3107 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3108 *txidx = ctx.bge_idx; 3109 3110 return(0); 3111 } 3112 3113 /* 3114 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3115 * to the mbuf data regions directly in the transmit descriptors. 3116 */ 3117 static void 3118 bge_start_locked(ifp) 3119 struct ifnet *ifp; 3120 { 3121 struct bge_softc *sc; 3122 struct mbuf *m_head = NULL; 3123 u_int32_t prodidx = 0; 3124 3125 sc = ifp->if_softc; 3126 3127 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3128 return; 3129 3130 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3131 3132 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3133 IF_DEQUEUE(&ifp->if_snd, m_head); 3134 if (m_head == NULL) 3135 break; 3136 3137 /* 3138 * XXX 3139 * safety overkill. If this is a fragmented packet chain 3140 * with delayed TCP/UDP checksums, then only encapsulate 3141 * it if we have enough descriptors to handle the entire 3142 * chain at once. 3143 * (paranoia -- may not actually be needed) 3144 */ 3145 if (m_head->m_flags & M_FIRSTFRAG && 3146 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3147 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3148 m_head->m_pkthdr.csum_data + 16) { 3149 IF_PREPEND(&ifp->if_snd, m_head); 3150 ifp->if_flags |= IFF_OACTIVE; 3151 break; 3152 } 3153 } 3154 3155 /* 3156 * Pack the data into the transmit ring. If we 3157 * don't have room, set the OACTIVE flag and wait 3158 * for the NIC to drain the ring. 3159 */ 3160 if (bge_encap(sc, m_head, &prodidx)) { 3161 IF_PREPEND(&ifp->if_snd, m_head); 3162 ifp->if_flags |= IFF_OACTIVE; 3163 break; 3164 } 3165 3166 /* 3167 * If there's a BPF listener, bounce a copy of this frame 3168 * to him. 3169 */ 3170 BPF_MTAP(ifp, m_head); 3171 } 3172 3173 /* Transmit */ 3174 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3175 /* 5700 b2 errata */ 3176 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3177 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3178 3179 /* 3180 * Set a timeout in case the chip goes out to lunch. 3181 */ 3182 ifp->if_timer = 5; 3183 3184 return; 3185 } 3186 3187 /* 3188 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3189 * to the mbuf data regions directly in the transmit descriptors. 3190 */ 3191 static void 3192 bge_start(ifp) 3193 struct ifnet *ifp; 3194 { 3195 struct bge_softc *sc; 3196 3197 sc = ifp->if_softc; 3198 BGE_LOCK(sc); 3199 bge_start_locked(ifp); 3200 BGE_UNLOCK(sc); 3201 } 3202 3203 static void 3204 bge_init_locked(sc) 3205 struct bge_softc *sc; 3206 { 3207 struct ifnet *ifp; 3208 u_int16_t *m; 3209 3210 BGE_LOCK_ASSERT(sc); 3211 3212 ifp = &sc->arpcom.ac_if; 3213 3214 if (ifp->if_flags & IFF_RUNNING) 3215 return; 3216 3217 /* Cancel pending I/O and flush buffers. */ 3218 bge_stop(sc); 3219 bge_reset(sc); 3220 bge_chipinit(sc); 3221 3222 /* 3223 * Init the various state machines, ring 3224 * control blocks and firmware. 3225 */ 3226 if (bge_blockinit(sc)) { 3227 printf("bge%d: initialization failure\n", sc->bge_unit); 3228 return; 3229 } 3230 3231 ifp = &sc->arpcom.ac_if; 3232 3233 /* Specify MTU. */ 3234 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3235 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3236 3237 /* Load our MAC address. */ 3238 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3239 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3240 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3241 3242 /* Enable or disable promiscuous mode as needed. */ 3243 if (ifp->if_flags & IFF_PROMISC) { 3244 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3245 } else { 3246 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3247 } 3248 3249 /* Program multicast filter. */ 3250 bge_setmulti(sc); 3251 3252 /* Init RX ring. */ 3253 bge_init_rx_ring_std(sc); 3254 3255 /* 3256 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3257 * memory to insure that the chip has in fact read the first 3258 * entry of the ring. 3259 */ 3260 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3261 u_int32_t v, i; 3262 for (i = 0; i < 10; i++) { 3263 DELAY(20); 3264 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3265 if (v == (MCLBYTES - ETHER_ALIGN)) 3266 break; 3267 } 3268 if (i == 10) 3269 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3270 sc->bge_unit); 3271 } 3272 3273 /* Init jumbo RX ring. */ 3274 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3275 bge_init_rx_ring_jumbo(sc); 3276 3277 /* Init our RX return ring index */ 3278 sc->bge_rx_saved_considx = 0; 3279 3280 /* Init TX ring. */ 3281 bge_init_tx_ring(sc); 3282 3283 /* Turn on transmitter */ 3284 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3285 3286 /* Turn on receiver */ 3287 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3288 3289 /* Tell firmware we're alive. */ 3290 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3291 3292 /* Enable host interrupts. */ 3293 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3294 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3295 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3296 3297 bge_ifmedia_upd(ifp); 3298 3299 ifp->if_flags |= IFF_RUNNING; 3300 ifp->if_flags &= ~IFF_OACTIVE; 3301 3302 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3303 3304 return; 3305 } 3306 3307 static void 3308 bge_init(xsc) 3309 void *xsc; 3310 { 3311 struct bge_softc *sc = xsc; 3312 3313 BGE_LOCK(sc); 3314 bge_init_locked(sc); 3315 BGE_UNLOCK(sc); 3316 3317 return; 3318 } 3319 3320 /* 3321 * Set media options. 3322 */ 3323 static int 3324 bge_ifmedia_upd(ifp) 3325 struct ifnet *ifp; 3326 { 3327 struct bge_softc *sc; 3328 struct mii_data *mii; 3329 struct ifmedia *ifm; 3330 3331 sc = ifp->if_softc; 3332 ifm = &sc->bge_ifmedia; 3333 3334 /* If this is a 1000baseX NIC, enable the TBI port. */ 3335 if (sc->bge_tbi) { 3336 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3337 return(EINVAL); 3338 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3339 case IFM_AUTO: 3340 break; 3341 case IFM_1000_SX: 3342 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3343 BGE_CLRBIT(sc, BGE_MAC_MODE, 3344 BGE_MACMODE_HALF_DUPLEX); 3345 } else { 3346 BGE_SETBIT(sc, BGE_MAC_MODE, 3347 BGE_MACMODE_HALF_DUPLEX); 3348 } 3349 break; 3350 default: 3351 return(EINVAL); 3352 } 3353 return(0); 3354 } 3355 3356 mii = device_get_softc(sc->bge_miibus); 3357 sc->bge_link = 0; 3358 if (mii->mii_instance) { 3359 struct mii_softc *miisc; 3360 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3361 miisc = LIST_NEXT(miisc, mii_list)) 3362 mii_phy_reset(miisc); 3363 } 3364 mii_mediachg(mii); 3365 3366 return(0); 3367 } 3368 3369 /* 3370 * Report current media status. 3371 */ 3372 static void 3373 bge_ifmedia_sts(ifp, ifmr) 3374 struct ifnet *ifp; 3375 struct ifmediareq *ifmr; 3376 { 3377 struct bge_softc *sc; 3378 struct mii_data *mii; 3379 3380 sc = ifp->if_softc; 3381 3382 if (sc->bge_tbi) { 3383 ifmr->ifm_status = IFM_AVALID; 3384 ifmr->ifm_active = IFM_ETHER; 3385 if (CSR_READ_4(sc, BGE_MAC_STS) & 3386 BGE_MACSTAT_TBI_PCS_SYNCHED) 3387 ifmr->ifm_status |= IFM_ACTIVE; 3388 ifmr->ifm_active |= IFM_1000_SX; 3389 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3390 ifmr->ifm_active |= IFM_HDX; 3391 else 3392 ifmr->ifm_active |= IFM_FDX; 3393 return; 3394 } 3395 3396 mii = device_get_softc(sc->bge_miibus); 3397 mii_pollstat(mii); 3398 ifmr->ifm_active = mii->mii_media_active; 3399 ifmr->ifm_status = mii->mii_media_status; 3400 3401 return; 3402 } 3403 3404 static int 3405 bge_ioctl(ifp, command, data) 3406 struct ifnet *ifp; 3407 u_long command; 3408 caddr_t data; 3409 { 3410 struct bge_softc *sc = ifp->if_softc; 3411 struct ifreq *ifr = (struct ifreq *) data; 3412 int mask, error = 0; 3413 struct mii_data *mii; 3414 3415 switch(command) { 3416 case SIOCSIFMTU: 3417 /* Disallow jumbo frames on 5705. */ 3418 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3419 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3420 error = EINVAL; 3421 else { 3422 ifp->if_mtu = ifr->ifr_mtu; 3423 ifp->if_flags &= ~IFF_RUNNING; 3424 bge_init(sc); 3425 } 3426 break; 3427 case SIOCSIFFLAGS: 3428 BGE_LOCK(sc); 3429 if (ifp->if_flags & IFF_UP) { 3430 /* 3431 * If only the state of the PROMISC flag changed, 3432 * then just use the 'set promisc mode' command 3433 * instead of reinitializing the entire NIC. Doing 3434 * a full re-init means reloading the firmware and 3435 * waiting for it to start up, which may take a 3436 * second or two. 3437 */ 3438 if (ifp->if_flags & IFF_RUNNING && 3439 ifp->if_flags & IFF_PROMISC && 3440 !(sc->bge_if_flags & IFF_PROMISC)) { 3441 BGE_SETBIT(sc, BGE_RX_MODE, 3442 BGE_RXMODE_RX_PROMISC); 3443 } else if (ifp->if_flags & IFF_RUNNING && 3444 !(ifp->if_flags & IFF_PROMISC) && 3445 sc->bge_if_flags & IFF_PROMISC) { 3446 BGE_CLRBIT(sc, BGE_RX_MODE, 3447 BGE_RXMODE_RX_PROMISC); 3448 } else 3449 bge_init_locked(sc); 3450 } else { 3451 if (ifp->if_flags & IFF_RUNNING) { 3452 bge_stop(sc); 3453 } 3454 } 3455 sc->bge_if_flags = ifp->if_flags; 3456 BGE_UNLOCK(sc); 3457 error = 0; 3458 break; 3459 case SIOCADDMULTI: 3460 case SIOCDELMULTI: 3461 if (ifp->if_flags & IFF_RUNNING) { 3462 BGE_LOCK(sc); 3463 bge_setmulti(sc); 3464 BGE_UNLOCK(sc); 3465 error = 0; 3466 } 3467 break; 3468 case SIOCSIFMEDIA: 3469 case SIOCGIFMEDIA: 3470 if (sc->bge_tbi) { 3471 error = ifmedia_ioctl(ifp, ifr, 3472 &sc->bge_ifmedia, command); 3473 } else { 3474 mii = device_get_softc(sc->bge_miibus); 3475 error = ifmedia_ioctl(ifp, ifr, 3476 &mii->mii_media, command); 3477 } 3478 break; 3479 case SIOCSIFCAP: 3480 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3481 if (mask & IFCAP_HWCSUM) { 3482 if (IFCAP_HWCSUM & ifp->if_capenable) 3483 ifp->if_capenable &= ~IFCAP_HWCSUM; 3484 else 3485 ifp->if_capenable |= IFCAP_HWCSUM; 3486 } 3487 error = 0; 3488 break; 3489 default: 3490 error = ether_ioctl(ifp, command, data); 3491 break; 3492 } 3493 3494 return(error); 3495 } 3496 3497 static void 3498 bge_watchdog(ifp) 3499 struct ifnet *ifp; 3500 { 3501 struct bge_softc *sc; 3502 3503 sc = ifp->if_softc; 3504 3505 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3506 3507 ifp->if_flags &= ~IFF_RUNNING; 3508 bge_init(sc); 3509 3510 ifp->if_oerrors++; 3511 3512 return; 3513 } 3514 3515 /* 3516 * Stop the adapter and free any mbufs allocated to the 3517 * RX and TX lists. 3518 */ 3519 static void 3520 bge_stop(sc) 3521 struct bge_softc *sc; 3522 { 3523 struct ifnet *ifp; 3524 struct ifmedia_entry *ifm; 3525 struct mii_data *mii = NULL; 3526 int mtmp, itmp; 3527 3528 BGE_LOCK_ASSERT(sc); 3529 3530 ifp = &sc->arpcom.ac_if; 3531 3532 if (!sc->bge_tbi) 3533 mii = device_get_softc(sc->bge_miibus); 3534 3535 callout_stop(&sc->bge_stat_ch); 3536 3537 /* 3538 * Disable all of the receiver blocks 3539 */ 3540 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3541 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3542 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3543 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3544 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3545 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3546 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3547 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3548 3549 /* 3550 * Disable all of the transmit blocks 3551 */ 3552 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3553 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3554 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3555 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3556 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3557 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3558 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3559 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3560 3561 /* 3562 * Shut down all of the memory managers and related 3563 * state machines. 3564 */ 3565 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3566 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3567 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3568 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3569 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3570 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3571 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 3572 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3573 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3574 } 3575 3576 /* Disable host interrupts. */ 3577 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3578 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3579 3580 /* 3581 * Tell firmware we're shutting down. 3582 */ 3583 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3584 3585 /* Free the RX lists. */ 3586 bge_free_rx_ring_std(sc); 3587 3588 /* Free jumbo RX list. */ 3589 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3590 bge_free_rx_ring_jumbo(sc); 3591 3592 /* Free TX buffers. */ 3593 bge_free_tx_ring(sc); 3594 3595 /* 3596 * Isolate/power down the PHY, but leave the media selection 3597 * unchanged so that things will be put back to normal when 3598 * we bring the interface back up. 3599 */ 3600 if (!sc->bge_tbi) { 3601 itmp = ifp->if_flags; 3602 ifp->if_flags |= IFF_UP; 3603 ifm = mii->mii_media.ifm_cur; 3604 mtmp = ifm->ifm_media; 3605 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3606 mii_mediachg(mii); 3607 ifm->ifm_media = mtmp; 3608 ifp->if_flags = itmp; 3609 } 3610 3611 sc->bge_link = 0; 3612 3613 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3614 3615 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3616 3617 return; 3618 } 3619 3620 /* 3621 * Stop all chip I/O so that the kernel's probe routines don't 3622 * get confused by errant DMAs when rebooting. 3623 */ 3624 static void 3625 bge_shutdown(dev) 3626 device_t dev; 3627 { 3628 struct bge_softc *sc; 3629 3630 sc = device_get_softc(dev); 3631 3632 BGE_LOCK(sc); 3633 bge_stop(sc); 3634 bge_reset(sc); 3635 BGE_UNLOCK(sc); 3636 3637 return; 3638 } 3639