1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 229 230 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 231 232 { TC_VENDORID, TC_DEVICEID_3C996 }, 233 234 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 235 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 236 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 237 238 { 0, 0 } 239 }; 240 241 static const struct bge_vendor { 242 uint16_t v_id; 243 const char *v_name; 244 } bge_vendors[] = { 245 { ALTEON_VENDORID, "Alteon" }, 246 { ALTIMA_VENDORID, "Altima" }, 247 { APPLE_VENDORID, "Apple" }, 248 { BCOM_VENDORID, "Broadcom" }, 249 { SK_VENDORID, "SysKonnect" }, 250 { TC_VENDORID, "3Com" }, 251 { FJTSU_VENDORID, "Fujitsu" }, 252 253 { 0, NULL } 254 }; 255 256 static const struct bge_revision { 257 uint32_t br_chipid; 258 const char *br_name; 259 } bge_revisions[] = { 260 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 261 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 262 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 263 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 264 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 265 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 266 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 267 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 268 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 269 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 270 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 271 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 272 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 273 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 274 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 275 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 276 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 277 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 278 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 279 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 280 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 281 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 282 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 283 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 284 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 285 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 286 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 287 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 288 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 289 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 290 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 291 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 292 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 293 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 294 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 295 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 296 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 297 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 298 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 299 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 300 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 301 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 302 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 303 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 304 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 305 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 306 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 307 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 308 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 309 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 310 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 311 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 312 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 313 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 314 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 315 /* 5754 and 5787 share the same ASIC ID */ 316 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 317 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 318 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 319 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 320 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 321 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 322 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 323 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 324 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 325 326 { 0, NULL } 327 }; 328 329 /* 330 * Some defaults for major revisions, so that newer steppings 331 * that we don't know about have a shot at working. 332 */ 333 static const struct bge_revision bge_majorrevs[] = { 334 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 335 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 336 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 337 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 338 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 339 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 340 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 341 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 342 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 343 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 344 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 345 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 346 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 347 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 348 /* 5754 and 5787 share the same ASIC ID */ 349 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 350 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 351 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 352 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 353 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 354 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 355 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 356 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 357 358 { 0, NULL } 359 }; 360 361 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 362 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 363 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 364 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 365 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 366 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 367 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 368 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 369 370 const struct bge_revision * bge_lookup_rev(uint32_t); 371 const struct bge_vendor * bge_lookup_vendor(uint16_t); 372 373 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 374 375 static int bge_probe(device_t); 376 static int bge_attach(device_t); 377 static int bge_detach(device_t); 378 static int bge_suspend(device_t); 379 static int bge_resume(device_t); 380 static void bge_release_resources(struct bge_softc *); 381 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 382 static int bge_dma_alloc(struct bge_softc *); 383 static void bge_dma_free(struct bge_softc *); 384 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 385 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 386 387 static void bge_devinfo(struct bge_softc *); 388 static int bge_mbox_reorder(struct bge_softc *); 389 390 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 391 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 392 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 393 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 394 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 395 396 static void bge_txeof(struct bge_softc *, uint16_t); 397 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 398 static int bge_rxeof(struct bge_softc *, uint16_t, int); 399 400 static void bge_asf_driver_up (struct bge_softc *); 401 static void bge_tick(void *); 402 static void bge_stats_clear_regs(struct bge_softc *); 403 static void bge_stats_update(struct bge_softc *); 404 static void bge_stats_update_regs(struct bge_softc *); 405 static struct mbuf *bge_check_short_dma(struct mbuf *); 406 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 407 uint16_t *, uint16_t *); 408 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 409 410 static void bge_intr(void *); 411 static int bge_msi_intr(void *); 412 static void bge_intr_task(void *, int); 413 static void bge_start_locked(struct ifnet *); 414 static void bge_start(struct ifnet *); 415 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 416 static void bge_init_locked(struct bge_softc *); 417 static void bge_init(void *); 418 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 419 static void bge_stop(struct bge_softc *); 420 static void bge_watchdog(struct bge_softc *); 421 static int bge_shutdown(device_t); 422 static int bge_ifmedia_upd_locked(struct ifnet *); 423 static int bge_ifmedia_upd(struct ifnet *); 424 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 425 426 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 427 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 428 429 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 430 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 431 432 static void bge_setpromisc(struct bge_softc *); 433 static void bge_setmulti(struct bge_softc *); 434 static void bge_setvlan(struct bge_softc *); 435 436 static __inline void bge_rxreuse_std(struct bge_softc *, int); 437 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 438 static int bge_newbuf_std(struct bge_softc *, int); 439 static int bge_newbuf_jumbo(struct bge_softc *, int); 440 static int bge_init_rx_ring_std(struct bge_softc *); 441 static void bge_free_rx_ring_std(struct bge_softc *); 442 static int bge_init_rx_ring_jumbo(struct bge_softc *); 443 static void bge_free_rx_ring_jumbo(struct bge_softc *); 444 static void bge_free_tx_ring(struct bge_softc *); 445 static int bge_init_tx_ring(struct bge_softc *); 446 447 static int bge_chipinit(struct bge_softc *); 448 static int bge_blockinit(struct bge_softc *); 449 static uint32_t bge_dma_swap_options(struct bge_softc *); 450 451 static int bge_has_eaddr(struct bge_softc *); 452 static uint32_t bge_readmem_ind(struct bge_softc *, int); 453 static void bge_writemem_ind(struct bge_softc *, int, int); 454 static void bge_writembx(struct bge_softc *, int, int); 455 #ifdef notdef 456 static uint32_t bge_readreg_ind(struct bge_softc *, int); 457 #endif 458 static void bge_writemem_direct(struct bge_softc *, int, int); 459 static void bge_writereg_ind(struct bge_softc *, int, int); 460 461 static int bge_miibus_readreg(device_t, int, int); 462 static int bge_miibus_writereg(device_t, int, int, int); 463 static void bge_miibus_statchg(device_t); 464 #ifdef DEVICE_POLLING 465 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 466 #endif 467 468 #define BGE_RESET_SHUTDOWN 0 469 #define BGE_RESET_START 1 470 #define BGE_RESET_SUSPEND 2 471 static void bge_sig_post_reset(struct bge_softc *, int); 472 static void bge_sig_legacy(struct bge_softc *, int); 473 static void bge_sig_pre_reset(struct bge_softc *, int); 474 static void bge_stop_fw(struct bge_softc *); 475 static int bge_reset(struct bge_softc *); 476 static void bge_link_upd(struct bge_softc *); 477 478 static void bge_ape_lock_init(struct bge_softc *); 479 static void bge_ape_read_fw_ver(struct bge_softc *); 480 static int bge_ape_lock(struct bge_softc *, int); 481 static void bge_ape_unlock(struct bge_softc *, int); 482 static void bge_ape_send_event(struct bge_softc *, uint32_t); 483 static void bge_ape_driver_state_change(struct bge_softc *, int); 484 485 /* 486 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 487 * leak information to untrusted users. It is also known to cause alignment 488 * traps on certain architectures. 489 */ 490 #ifdef BGE_REGISTER_DEBUG 491 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 492 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 493 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 494 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 495 #endif 496 static void bge_add_sysctls(struct bge_softc *); 497 static void bge_add_sysctl_stats_regs(struct bge_softc *, 498 struct sysctl_ctx_list *, struct sysctl_oid_list *); 499 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 500 struct sysctl_oid_list *); 501 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 502 503 static device_method_t bge_methods[] = { 504 /* Device interface */ 505 DEVMETHOD(device_probe, bge_probe), 506 DEVMETHOD(device_attach, bge_attach), 507 DEVMETHOD(device_detach, bge_detach), 508 DEVMETHOD(device_shutdown, bge_shutdown), 509 DEVMETHOD(device_suspend, bge_suspend), 510 DEVMETHOD(device_resume, bge_resume), 511 512 /* MII interface */ 513 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 514 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 515 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 516 517 DEVMETHOD_END 518 }; 519 520 static driver_t bge_driver = { 521 "bge", 522 bge_methods, 523 sizeof(struct bge_softc) 524 }; 525 526 static devclass_t bge_devclass; 527 528 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 529 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 530 531 static int bge_allow_asf = 1; 532 533 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 534 535 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 536 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 537 "Allow ASF mode if available"); 538 539 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 540 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 541 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 542 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 543 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 544 545 static int 546 bge_has_eaddr(struct bge_softc *sc) 547 { 548 #ifdef __sparc64__ 549 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 550 device_t dev; 551 uint32_t subvendor; 552 553 dev = sc->bge_dev; 554 555 /* 556 * The on-board BGEs found in sun4u machines aren't fitted with 557 * an EEPROM which means that we have to obtain the MAC address 558 * via OFW and that some tests will always fail. We distinguish 559 * such BGEs by the subvendor ID, which also has to be obtained 560 * from OFW instead of the PCI configuration space as the latter 561 * indicates Broadcom as the subvendor of the netboot interface. 562 * For early Blade 1500 and 2500 we even have to check the OFW 563 * device path as the subvendor ID always defaults to Broadcom 564 * there. 565 */ 566 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 567 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 568 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 569 return (0); 570 memset(buf, 0, sizeof(buf)); 571 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 572 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 573 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 574 return (0); 575 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 576 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 577 return (0); 578 } 579 #endif 580 return (1); 581 } 582 583 static uint32_t 584 bge_readmem_ind(struct bge_softc *sc, int off) 585 { 586 device_t dev; 587 uint32_t val; 588 589 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 590 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 591 return (0); 592 593 dev = sc->bge_dev; 594 595 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 596 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 597 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 598 return (val); 599 } 600 601 static void 602 bge_writemem_ind(struct bge_softc *sc, int off, int val) 603 { 604 device_t dev; 605 606 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 607 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 608 return; 609 610 dev = sc->bge_dev; 611 612 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 613 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 614 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 615 } 616 617 #ifdef notdef 618 static uint32_t 619 bge_readreg_ind(struct bge_softc *sc, int off) 620 { 621 device_t dev; 622 623 dev = sc->bge_dev; 624 625 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 626 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 627 } 628 #endif 629 630 static void 631 bge_writereg_ind(struct bge_softc *sc, int off, int val) 632 { 633 device_t dev; 634 635 dev = sc->bge_dev; 636 637 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 638 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 639 } 640 641 static void 642 bge_writemem_direct(struct bge_softc *sc, int off, int val) 643 { 644 CSR_WRITE_4(sc, off, val); 645 } 646 647 static void 648 bge_writembx(struct bge_softc *sc, int off, int val) 649 { 650 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 651 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 652 653 CSR_WRITE_4(sc, off, val); 654 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 655 CSR_READ_4(sc, off); 656 } 657 658 /* 659 * Clear all stale locks and select the lock for this driver instance. 660 */ 661 static void 662 bge_ape_lock_init(struct bge_softc *sc) 663 { 664 uint32_t bit, regbase; 665 int i; 666 667 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 668 regbase = BGE_APE_LOCK_GRANT; 669 else 670 regbase = BGE_APE_PER_LOCK_GRANT; 671 672 /* Clear any stale locks. */ 673 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 674 switch (i) { 675 case BGE_APE_LOCK_PHY0: 676 case BGE_APE_LOCK_PHY1: 677 case BGE_APE_LOCK_PHY2: 678 case BGE_APE_LOCK_PHY3: 679 bit = BGE_APE_LOCK_GRANT_DRIVER0; 680 break; 681 default: 682 if (sc->bge_func_addr != 0) 683 bit = BGE_APE_LOCK_GRANT_DRIVER0; 684 else 685 bit = (1 << sc->bge_func_addr); 686 } 687 APE_WRITE_4(sc, regbase + 4 * i, bit); 688 } 689 690 /* Select the PHY lock based on the device's function number. */ 691 switch (sc->bge_func_addr) { 692 case 0: 693 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 694 break; 695 case 1: 696 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 697 break; 698 case 2: 699 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 700 break; 701 case 3: 702 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 703 break; 704 default: 705 device_printf(sc->bge_dev, 706 "PHY lock not supported on this function\n"); 707 } 708 } 709 710 /* 711 * Check for APE firmware, set flags, and print version info. 712 */ 713 static void 714 bge_ape_read_fw_ver(struct bge_softc *sc) 715 { 716 const char *fwtype; 717 uint32_t apedata, features; 718 719 /* Check for a valid APE signature in shared memory. */ 720 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 721 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 722 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 723 return; 724 } 725 726 /* Check if APE firmware is running. */ 727 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 728 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 729 device_printf(sc->bge_dev, "APE signature found " 730 "but FW status not ready! 0x%08x\n", apedata); 731 return; 732 } 733 734 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 735 736 /* Fetch the APE firwmare type and version. */ 737 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 738 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 739 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 740 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 741 fwtype = "NCSI"; 742 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 743 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 744 fwtype = "DASH"; 745 } else 746 fwtype = "UNKN"; 747 748 /* Print the APE firmware version. */ 749 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 750 fwtype, 751 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 752 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 753 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 754 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 755 } 756 757 static int 758 bge_ape_lock(struct bge_softc *sc, int locknum) 759 { 760 uint32_t bit, gnt, req, status; 761 int i, off; 762 763 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 764 return (0); 765 766 /* Lock request/grant registers have different bases. */ 767 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 768 req = BGE_APE_LOCK_REQ; 769 gnt = BGE_APE_LOCK_GRANT; 770 } else { 771 req = BGE_APE_PER_LOCK_REQ; 772 gnt = BGE_APE_PER_LOCK_GRANT; 773 } 774 775 off = 4 * locknum; 776 777 switch (locknum) { 778 case BGE_APE_LOCK_GPIO: 779 /* Lock required when using GPIO. */ 780 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 781 return (0); 782 if (sc->bge_func_addr == 0) 783 bit = BGE_APE_LOCK_REQ_DRIVER0; 784 else 785 bit = (1 << sc->bge_func_addr); 786 break; 787 case BGE_APE_LOCK_GRC: 788 /* Lock required to reset the device. */ 789 if (sc->bge_func_addr == 0) 790 bit = BGE_APE_LOCK_REQ_DRIVER0; 791 else 792 bit = (1 << sc->bge_func_addr); 793 break; 794 case BGE_APE_LOCK_MEM: 795 /* Lock required when accessing certain APE memory. */ 796 if (sc->bge_func_addr == 0) 797 bit = BGE_APE_LOCK_REQ_DRIVER0; 798 else 799 bit = (1 << sc->bge_func_addr); 800 break; 801 case BGE_APE_LOCK_PHY0: 802 case BGE_APE_LOCK_PHY1: 803 case BGE_APE_LOCK_PHY2: 804 case BGE_APE_LOCK_PHY3: 805 /* Lock required when accessing PHYs. */ 806 bit = BGE_APE_LOCK_REQ_DRIVER0; 807 break; 808 default: 809 return (EINVAL); 810 } 811 812 /* Request a lock. */ 813 APE_WRITE_4(sc, req + off, bit); 814 815 /* Wait up to 1 second to acquire lock. */ 816 for (i = 0; i < 20000; i++) { 817 status = APE_READ_4(sc, gnt + off); 818 if (status == bit) 819 break; 820 DELAY(50); 821 } 822 823 /* Handle any errors. */ 824 if (status != bit) { 825 device_printf(sc->bge_dev, "APE lock %d request failed! " 826 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 827 locknum, req + off, bit & 0xFFFF, gnt + off, 828 status & 0xFFFF); 829 /* Revoke the lock request. */ 830 APE_WRITE_4(sc, gnt + off, bit); 831 return (EBUSY); 832 } 833 834 return (0); 835 } 836 837 static void 838 bge_ape_unlock(struct bge_softc *sc, int locknum) 839 { 840 uint32_t bit, gnt; 841 int off; 842 843 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 844 return; 845 846 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 847 gnt = BGE_APE_LOCK_GRANT; 848 else 849 gnt = BGE_APE_PER_LOCK_GRANT; 850 851 off = 4 * locknum; 852 853 switch (locknum) { 854 case BGE_APE_LOCK_GPIO: 855 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 856 return; 857 if (sc->bge_func_addr == 0) 858 bit = BGE_APE_LOCK_GRANT_DRIVER0; 859 else 860 bit = (1 << sc->bge_func_addr); 861 break; 862 case BGE_APE_LOCK_GRC: 863 if (sc->bge_func_addr == 0) 864 bit = BGE_APE_LOCK_GRANT_DRIVER0; 865 else 866 bit = (1 << sc->bge_func_addr); 867 break; 868 case BGE_APE_LOCK_MEM: 869 if (sc->bge_func_addr == 0) 870 bit = BGE_APE_LOCK_GRANT_DRIVER0; 871 else 872 bit = (1 << sc->bge_func_addr); 873 break; 874 case BGE_APE_LOCK_PHY0: 875 case BGE_APE_LOCK_PHY1: 876 case BGE_APE_LOCK_PHY2: 877 case BGE_APE_LOCK_PHY3: 878 bit = BGE_APE_LOCK_GRANT_DRIVER0; 879 break; 880 default: 881 return; 882 } 883 884 APE_WRITE_4(sc, gnt + off, bit); 885 } 886 887 /* 888 * Send an event to the APE firmware. 889 */ 890 static void 891 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 892 { 893 uint32_t apedata; 894 int i; 895 896 /* NCSI does not support APE events. */ 897 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 898 return; 899 900 /* Wait up to 1ms for APE to service previous event. */ 901 for (i = 10; i > 0; i--) { 902 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 903 break; 904 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 905 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 906 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 907 BGE_APE_EVENT_STATUS_EVENT_PENDING); 908 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 909 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 910 break; 911 } 912 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 913 DELAY(100); 914 } 915 if (i == 0) 916 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 917 event); 918 } 919 920 static void 921 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 922 { 923 uint32_t apedata, event; 924 925 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 926 return; 927 928 switch (kind) { 929 case BGE_RESET_START: 930 /* If this is the first load, clear the load counter. */ 931 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 932 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 933 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 934 else { 935 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 936 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 937 } 938 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 939 BGE_APE_HOST_SEG_SIG_MAGIC); 940 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 941 BGE_APE_HOST_SEG_LEN_MAGIC); 942 943 /* Add some version info if bge(4) supports it. */ 944 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 945 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 946 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 947 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 948 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 949 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 950 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 951 BGE_APE_HOST_DRVR_STATE_START); 952 event = BGE_APE_EVENT_STATUS_STATE_START; 953 break; 954 case BGE_RESET_SHUTDOWN: 955 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 956 BGE_APE_HOST_DRVR_STATE_UNLOAD); 957 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 958 break; 959 case BGE_RESET_SUSPEND: 960 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 961 break; 962 default: 963 return; 964 } 965 966 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 967 BGE_APE_EVENT_STATUS_STATE_CHNGE); 968 } 969 970 /* 971 * Map a single buffer address. 972 */ 973 974 static void 975 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 976 { 977 struct bge_dmamap_arg *ctx; 978 979 if (error) 980 return; 981 982 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 983 984 ctx = arg; 985 ctx->bge_busaddr = segs->ds_addr; 986 } 987 988 static uint8_t 989 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 990 { 991 uint32_t access, byte = 0; 992 int i; 993 994 /* Lock. */ 995 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 996 for (i = 0; i < 8000; i++) { 997 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 998 break; 999 DELAY(20); 1000 } 1001 if (i == 8000) 1002 return (1); 1003 1004 /* Enable access. */ 1005 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1006 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1007 1008 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1009 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1010 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1011 DELAY(10); 1012 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1013 DELAY(10); 1014 break; 1015 } 1016 } 1017 1018 if (i == BGE_TIMEOUT * 10) { 1019 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1020 return (1); 1021 } 1022 1023 /* Get result. */ 1024 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1025 1026 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1027 1028 /* Disable access. */ 1029 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1030 1031 /* Unlock. */ 1032 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1033 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1034 1035 return (0); 1036 } 1037 1038 /* 1039 * Read a sequence of bytes from NVRAM. 1040 */ 1041 static int 1042 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1043 { 1044 int err = 0, i; 1045 uint8_t byte = 0; 1046 1047 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1048 return (1); 1049 1050 for (i = 0; i < cnt; i++) { 1051 err = bge_nvram_getbyte(sc, off + i, &byte); 1052 if (err) 1053 break; 1054 *(dest + i) = byte; 1055 } 1056 1057 return (err ? 1 : 0); 1058 } 1059 1060 /* 1061 * Read a byte of data stored in the EEPROM at address 'addr.' The 1062 * BCM570x supports both the traditional bitbang interface and an 1063 * auto access interface for reading the EEPROM. We use the auto 1064 * access method. 1065 */ 1066 static uint8_t 1067 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1068 { 1069 int i; 1070 uint32_t byte = 0; 1071 1072 /* 1073 * Enable use of auto EEPROM access so we can avoid 1074 * having to use the bitbang method. 1075 */ 1076 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1077 1078 /* Reset the EEPROM, load the clock period. */ 1079 CSR_WRITE_4(sc, BGE_EE_ADDR, 1080 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1081 DELAY(20); 1082 1083 /* Issue the read EEPROM command. */ 1084 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1085 1086 /* Wait for completion */ 1087 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1088 DELAY(10); 1089 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1090 break; 1091 } 1092 1093 if (i == BGE_TIMEOUT * 10) { 1094 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1095 return (1); 1096 } 1097 1098 /* Get result. */ 1099 byte = CSR_READ_4(sc, BGE_EE_DATA); 1100 1101 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1102 1103 return (0); 1104 } 1105 1106 /* 1107 * Read a sequence of bytes from the EEPROM. 1108 */ 1109 static int 1110 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1111 { 1112 int i, error = 0; 1113 uint8_t byte = 0; 1114 1115 for (i = 0; i < cnt; i++) { 1116 error = bge_eeprom_getbyte(sc, off + i, &byte); 1117 if (error) 1118 break; 1119 *(dest + i) = byte; 1120 } 1121 1122 return (error ? 1 : 0); 1123 } 1124 1125 static int 1126 bge_miibus_readreg(device_t dev, int phy, int reg) 1127 { 1128 struct bge_softc *sc; 1129 uint32_t val; 1130 int i; 1131 1132 sc = device_get_softc(dev); 1133 1134 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1135 return (0); 1136 1137 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1138 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1139 CSR_WRITE_4(sc, BGE_MI_MODE, 1140 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1141 DELAY(80); 1142 } 1143 1144 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1145 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1146 1147 /* Poll for the PHY register access to complete. */ 1148 for (i = 0; i < BGE_TIMEOUT; i++) { 1149 DELAY(10); 1150 val = CSR_READ_4(sc, BGE_MI_COMM); 1151 if ((val & BGE_MICOMM_BUSY) == 0) { 1152 DELAY(5); 1153 val = CSR_READ_4(sc, BGE_MI_COMM); 1154 break; 1155 } 1156 } 1157 1158 if (i == BGE_TIMEOUT) { 1159 device_printf(sc->bge_dev, 1160 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1161 phy, reg, val); 1162 val = 0; 1163 } 1164 1165 /* Restore the autopoll bit if necessary. */ 1166 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1167 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1168 DELAY(80); 1169 } 1170 1171 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1172 1173 if (val & BGE_MICOMM_READFAIL) 1174 return (0); 1175 1176 return (val & 0xFFFF); 1177 } 1178 1179 static int 1180 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1181 { 1182 struct bge_softc *sc; 1183 int i; 1184 1185 sc = device_get_softc(dev); 1186 1187 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1188 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1189 return (0); 1190 1191 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1192 return (0); 1193 1194 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1195 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1196 CSR_WRITE_4(sc, BGE_MI_MODE, 1197 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1198 DELAY(80); 1199 } 1200 1201 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1202 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1203 1204 for (i = 0; i < BGE_TIMEOUT; i++) { 1205 DELAY(10); 1206 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1207 DELAY(5); 1208 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1209 break; 1210 } 1211 } 1212 1213 /* Restore the autopoll bit if necessary. */ 1214 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1215 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1216 DELAY(80); 1217 } 1218 1219 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1220 1221 if (i == BGE_TIMEOUT) 1222 device_printf(sc->bge_dev, 1223 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1224 phy, reg, val); 1225 1226 return (0); 1227 } 1228 1229 static void 1230 bge_miibus_statchg(device_t dev) 1231 { 1232 struct bge_softc *sc; 1233 struct mii_data *mii; 1234 uint32_t mac_mode, rx_mode, tx_mode; 1235 1236 sc = device_get_softc(dev); 1237 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1238 return; 1239 mii = device_get_softc(sc->bge_miibus); 1240 1241 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1242 (IFM_ACTIVE | IFM_AVALID)) { 1243 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1244 case IFM_10_T: 1245 case IFM_100_TX: 1246 sc->bge_link = 1; 1247 break; 1248 case IFM_1000_T: 1249 case IFM_1000_SX: 1250 case IFM_2500_SX: 1251 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1252 sc->bge_link = 1; 1253 else 1254 sc->bge_link = 0; 1255 break; 1256 default: 1257 sc->bge_link = 0; 1258 break; 1259 } 1260 } else 1261 sc->bge_link = 0; 1262 if (sc->bge_link == 0) 1263 return; 1264 1265 /* 1266 * APE firmware touches these registers to keep the MAC 1267 * connected to the outside world. Try to keep the 1268 * accesses atomic. 1269 */ 1270 1271 /* Set the port mode (MII/GMII) to match the link speed. */ 1272 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1273 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1274 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1275 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1276 1277 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1278 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1279 mac_mode |= BGE_PORTMODE_GMII; 1280 else 1281 mac_mode |= BGE_PORTMODE_MII; 1282 1283 /* Set MAC flow control behavior to match link flow control settings. */ 1284 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1285 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1286 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 1287 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1288 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1289 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1290 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1291 } else 1292 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1293 1294 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1295 DELAY(40); 1296 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1297 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1298 } 1299 1300 /* 1301 * Intialize a standard receive ring descriptor. 1302 */ 1303 static int 1304 bge_newbuf_std(struct bge_softc *sc, int i) 1305 { 1306 struct mbuf *m; 1307 struct bge_rx_bd *r; 1308 bus_dma_segment_t segs[1]; 1309 bus_dmamap_t map; 1310 int error, nsegs; 1311 1312 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1313 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1314 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1315 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1316 if (m == NULL) 1317 return (ENOBUFS); 1318 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1319 } else { 1320 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1321 if (m == NULL) 1322 return (ENOBUFS); 1323 m->m_len = m->m_pkthdr.len = MCLBYTES; 1324 } 1325 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1326 m_adj(m, ETHER_ALIGN); 1327 1328 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1329 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1330 if (error != 0) { 1331 m_freem(m); 1332 return (error); 1333 } 1334 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1335 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1336 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1337 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1338 sc->bge_cdata.bge_rx_std_dmamap[i]); 1339 } 1340 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1341 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1342 sc->bge_cdata.bge_rx_std_sparemap = map; 1343 sc->bge_cdata.bge_rx_std_chain[i] = m; 1344 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1345 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1346 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1347 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1348 r->bge_flags = BGE_RXBDFLAG_END; 1349 r->bge_len = segs[0].ds_len; 1350 r->bge_idx = i; 1351 1352 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1353 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1354 1355 return (0); 1356 } 1357 1358 /* 1359 * Initialize a jumbo receive ring descriptor. This allocates 1360 * a jumbo buffer from the pool managed internally by the driver. 1361 */ 1362 static int 1363 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1364 { 1365 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1366 bus_dmamap_t map; 1367 struct bge_extrx_bd *r; 1368 struct mbuf *m; 1369 int error, nsegs; 1370 1371 MGETHDR(m, M_NOWAIT, MT_DATA); 1372 if (m == NULL) 1373 return (ENOBUFS); 1374 1375 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1376 if (!(m->m_flags & M_EXT)) { 1377 m_freem(m); 1378 return (ENOBUFS); 1379 } 1380 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1381 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1382 m_adj(m, ETHER_ALIGN); 1383 1384 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1385 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1386 if (error != 0) { 1387 m_freem(m); 1388 return (error); 1389 } 1390 1391 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1392 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1393 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1394 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1395 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1396 } 1397 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1398 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1399 sc->bge_cdata.bge_rx_jumbo_sparemap; 1400 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1401 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1402 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1403 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1404 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1405 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1406 1407 /* 1408 * Fill in the extended RX buffer descriptor. 1409 */ 1410 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1411 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1412 r->bge_idx = i; 1413 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1414 switch (nsegs) { 1415 case 4: 1416 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1417 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1418 r->bge_len3 = segs[3].ds_len; 1419 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1420 case 3: 1421 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1422 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1423 r->bge_len2 = segs[2].ds_len; 1424 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1425 case 2: 1426 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1427 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1428 r->bge_len1 = segs[1].ds_len; 1429 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1430 case 1: 1431 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1432 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1433 r->bge_len0 = segs[0].ds_len; 1434 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1435 break; 1436 default: 1437 panic("%s: %d segments\n", __func__, nsegs); 1438 } 1439 1440 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1441 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1442 1443 return (0); 1444 } 1445 1446 static int 1447 bge_init_rx_ring_std(struct bge_softc *sc) 1448 { 1449 int error, i; 1450 1451 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1452 sc->bge_std = 0; 1453 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1454 if ((error = bge_newbuf_std(sc, i)) != 0) 1455 return (error); 1456 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1457 } 1458 1459 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1460 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1461 1462 sc->bge_std = 0; 1463 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1464 1465 return (0); 1466 } 1467 1468 static void 1469 bge_free_rx_ring_std(struct bge_softc *sc) 1470 { 1471 int i; 1472 1473 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1474 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1475 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1476 sc->bge_cdata.bge_rx_std_dmamap[i], 1477 BUS_DMASYNC_POSTREAD); 1478 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1479 sc->bge_cdata.bge_rx_std_dmamap[i]); 1480 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1481 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1482 } 1483 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1484 sizeof(struct bge_rx_bd)); 1485 } 1486 } 1487 1488 static int 1489 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1490 { 1491 struct bge_rcb *rcb; 1492 int error, i; 1493 1494 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1495 sc->bge_jumbo = 0; 1496 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1497 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1498 return (error); 1499 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1500 } 1501 1502 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1503 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1504 1505 sc->bge_jumbo = 0; 1506 1507 /* Enable the jumbo receive producer ring. */ 1508 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1509 rcb->bge_maxlen_flags = 1510 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1511 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1512 1513 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1514 1515 return (0); 1516 } 1517 1518 static void 1519 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1520 { 1521 int i; 1522 1523 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1524 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1525 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1526 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1527 BUS_DMASYNC_POSTREAD); 1528 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1529 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1530 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1531 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1532 } 1533 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1534 sizeof(struct bge_extrx_bd)); 1535 } 1536 } 1537 1538 static void 1539 bge_free_tx_ring(struct bge_softc *sc) 1540 { 1541 int i; 1542 1543 if (sc->bge_ldata.bge_tx_ring == NULL) 1544 return; 1545 1546 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1547 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1548 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1549 sc->bge_cdata.bge_tx_dmamap[i], 1550 BUS_DMASYNC_POSTWRITE); 1551 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1552 sc->bge_cdata.bge_tx_dmamap[i]); 1553 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1554 sc->bge_cdata.bge_tx_chain[i] = NULL; 1555 } 1556 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1557 sizeof(struct bge_tx_bd)); 1558 } 1559 } 1560 1561 static int 1562 bge_init_tx_ring(struct bge_softc *sc) 1563 { 1564 sc->bge_txcnt = 0; 1565 sc->bge_tx_saved_considx = 0; 1566 1567 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1568 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1569 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1570 1571 /* Initialize transmit producer index for host-memory send ring. */ 1572 sc->bge_tx_prodidx = 0; 1573 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1574 1575 /* 5700 b2 errata */ 1576 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1577 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1578 1579 /* NIC-memory send ring not used; initialize to zero. */ 1580 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1581 /* 5700 b2 errata */ 1582 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1583 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1584 1585 return (0); 1586 } 1587 1588 static void 1589 bge_setpromisc(struct bge_softc *sc) 1590 { 1591 struct ifnet *ifp; 1592 1593 BGE_LOCK_ASSERT(sc); 1594 1595 ifp = sc->bge_ifp; 1596 1597 /* Enable or disable promiscuous mode as needed. */ 1598 if (ifp->if_flags & IFF_PROMISC) 1599 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1600 else 1601 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1602 } 1603 1604 static void 1605 bge_setmulti(struct bge_softc *sc) 1606 { 1607 struct ifnet *ifp; 1608 struct ifmultiaddr *ifma; 1609 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1610 int h, i; 1611 1612 BGE_LOCK_ASSERT(sc); 1613 1614 ifp = sc->bge_ifp; 1615 1616 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1617 for (i = 0; i < 4; i++) 1618 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1619 return; 1620 } 1621 1622 /* First, zot all the existing filters. */ 1623 for (i = 0; i < 4; i++) 1624 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1625 1626 /* Now program new ones. */ 1627 if_maddr_rlock(ifp); 1628 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1629 if (ifma->ifma_addr->sa_family != AF_LINK) 1630 continue; 1631 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1632 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1633 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1634 } 1635 if_maddr_runlock(ifp); 1636 1637 for (i = 0; i < 4; i++) 1638 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1639 } 1640 1641 static void 1642 bge_setvlan(struct bge_softc *sc) 1643 { 1644 struct ifnet *ifp; 1645 1646 BGE_LOCK_ASSERT(sc); 1647 1648 ifp = sc->bge_ifp; 1649 1650 /* Enable or disable VLAN tag stripping as needed. */ 1651 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1652 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1653 else 1654 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1655 } 1656 1657 static void 1658 bge_sig_pre_reset(struct bge_softc *sc, int type) 1659 { 1660 1661 /* 1662 * Some chips don't like this so only do this if ASF is enabled 1663 */ 1664 if (sc->bge_asf_mode) 1665 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1666 1667 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1668 switch (type) { 1669 case BGE_RESET_START: 1670 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1671 BGE_FW_DRV_STATE_START); 1672 break; 1673 case BGE_RESET_SHUTDOWN: 1674 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1675 BGE_FW_DRV_STATE_UNLOAD); 1676 break; 1677 case BGE_RESET_SUSPEND: 1678 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1679 BGE_FW_DRV_STATE_SUSPEND); 1680 break; 1681 } 1682 } 1683 1684 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1685 bge_ape_driver_state_change(sc, type); 1686 } 1687 1688 static void 1689 bge_sig_post_reset(struct bge_softc *sc, int type) 1690 { 1691 1692 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1693 switch (type) { 1694 case BGE_RESET_START: 1695 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1696 BGE_FW_DRV_STATE_START_DONE); 1697 /* START DONE */ 1698 break; 1699 case BGE_RESET_SHUTDOWN: 1700 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1701 BGE_FW_DRV_STATE_UNLOAD_DONE); 1702 break; 1703 } 1704 } 1705 if (type == BGE_RESET_SHUTDOWN) 1706 bge_ape_driver_state_change(sc, type); 1707 } 1708 1709 static void 1710 bge_sig_legacy(struct bge_softc *sc, int type) 1711 { 1712 1713 if (sc->bge_asf_mode) { 1714 switch (type) { 1715 case BGE_RESET_START: 1716 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1717 BGE_FW_DRV_STATE_START); 1718 break; 1719 case BGE_RESET_SHUTDOWN: 1720 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1721 BGE_FW_DRV_STATE_UNLOAD); 1722 break; 1723 } 1724 } 1725 } 1726 1727 static void 1728 bge_stop_fw(struct bge_softc *sc) 1729 { 1730 int i; 1731 1732 if (sc->bge_asf_mode) { 1733 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1734 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1735 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1736 1737 for (i = 0; i < 100; i++ ) { 1738 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1739 BGE_RX_CPU_DRV_EVENT)) 1740 break; 1741 DELAY(10); 1742 } 1743 } 1744 } 1745 1746 static uint32_t 1747 bge_dma_swap_options(struct bge_softc *sc) 1748 { 1749 uint32_t dma_options; 1750 1751 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1752 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1753 #if BYTE_ORDER == BIG_ENDIAN 1754 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1755 #endif 1756 return (dma_options); 1757 } 1758 1759 /* 1760 * Do endian, PCI and DMA initialization. 1761 */ 1762 static int 1763 bge_chipinit(struct bge_softc *sc) 1764 { 1765 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1766 uint16_t val; 1767 int i; 1768 1769 /* Set endianness before we access any non-PCI registers. */ 1770 misc_ctl = BGE_INIT; 1771 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1772 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1773 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1774 1775 /* 1776 * Clear the MAC statistics block in the NIC's 1777 * internal memory. 1778 */ 1779 for (i = BGE_STATS_BLOCK; 1780 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1781 BGE_MEMWIN_WRITE(sc, i, 0); 1782 1783 for (i = BGE_STATUS_BLOCK; 1784 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1785 BGE_MEMWIN_WRITE(sc, i, 0); 1786 1787 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1788 /* 1789 * Fix data corruption caused by non-qword write with WB. 1790 * Fix master abort in PCI mode. 1791 * Fix PCI latency timer. 1792 */ 1793 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1794 val |= (1 << 10) | (1 << 12) | (1 << 13); 1795 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1796 } 1797 1798 /* 1799 * Set up the PCI DMA control register. 1800 */ 1801 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1802 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1803 if (sc->bge_flags & BGE_FLAG_PCIE) { 1804 if (sc->bge_mps >= 256) 1805 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1806 else 1807 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1808 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1809 if (BGE_IS_5714_FAMILY(sc)) { 1810 /* 256 bytes for read and write. */ 1811 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1812 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1813 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1814 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1815 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1816 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1817 /* 1818 * In the BCM5703, the DMA read watermark should 1819 * be set to less than or equal to the maximum 1820 * memory read byte count of the PCI-X command 1821 * register. 1822 */ 1823 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1824 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1825 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1826 /* 1536 bytes for read, 384 bytes for write. */ 1827 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1828 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1829 } else { 1830 /* 384 bytes for read and write. */ 1831 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1832 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1833 0x0F; 1834 } 1835 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1836 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1837 uint32_t tmp; 1838 1839 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1840 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1841 if (tmp == 6 || tmp == 7) 1842 dma_rw_ctl |= 1843 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1844 1845 /* Set PCI-X DMA write workaround. */ 1846 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1847 } 1848 } else { 1849 /* Conventional PCI bus: 256 bytes for read and write. */ 1850 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1851 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1852 1853 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1854 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1855 dma_rw_ctl |= 0x0F; 1856 } 1857 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1858 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1859 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1860 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1861 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1862 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1863 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1864 if (BGE_IS_5717_PLUS(sc)) { 1865 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1866 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1867 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1868 /* 1869 * Enable HW workaround for controllers that misinterpret 1870 * a status tag update and leave interrupts permanently 1871 * disabled. 1872 */ 1873 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1874 sc->bge_asicrev != BGE_ASICREV_BCM57765) 1875 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1876 } 1877 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1878 1879 /* 1880 * Set up general mode register. 1881 */ 1882 mode_ctl = bge_dma_swap_options(sc); 1883 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 1884 /* Retain Host-2-BMC settings written by APE firmware. */ 1885 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1886 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1887 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1888 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1889 } 1890 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1891 BGE_MODECTL_TX_NO_PHDR_CSUM; 1892 1893 /* 1894 * BCM5701 B5 have a bug causing data corruption when using 1895 * 64-bit DMA reads, which can be terminated early and then 1896 * completed later as 32-bit accesses, in combination with 1897 * certain bridges. 1898 */ 1899 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1900 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1901 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1902 1903 /* 1904 * Tell the firmware the driver is running 1905 */ 1906 if (sc->bge_asf_mode & ASF_STACKUP) 1907 mode_ctl |= BGE_MODECTL_STACKUP; 1908 1909 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1910 1911 /* 1912 * Disable memory write invalidate. Apparently it is not supported 1913 * properly by these devices. Also ensure that INTx isn't disabled, 1914 * as these chips need it even when using MSI. 1915 */ 1916 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1917 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1918 1919 /* Set the timer prescaler (always 66Mhz) */ 1920 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1921 1922 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1923 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1924 DELAY(40); /* XXX */ 1925 1926 /* Put PHY into ready state */ 1927 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1928 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1929 DELAY(40); 1930 } 1931 1932 return (0); 1933 } 1934 1935 static int 1936 bge_blockinit(struct bge_softc *sc) 1937 { 1938 struct bge_rcb *rcb; 1939 bus_size_t vrcb; 1940 bge_hostaddr taddr; 1941 uint32_t dmactl, val; 1942 int i, limit; 1943 1944 /* 1945 * Initialize the memory window pointer register so that 1946 * we can access the first 32K of internal NIC RAM. This will 1947 * allow us to set up the TX send ring RCBs and the RX return 1948 * ring RCBs, plus other things which live in NIC memory. 1949 */ 1950 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1951 1952 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1953 1954 if (!(BGE_IS_5705_PLUS(sc))) { 1955 /* Configure mbuf memory pool */ 1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1957 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1958 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1959 else 1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1961 1962 /* Configure DMA resource pool */ 1963 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1964 BGE_DMA_DESCRIPTORS); 1965 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1966 } 1967 1968 /* Configure mbuf pool watermarks */ 1969 if (BGE_IS_5717_PLUS(sc)) { 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1971 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1974 } else { 1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1977 } 1978 } else if (!BGE_IS_5705_PLUS(sc)) { 1979 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1982 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1986 } else { 1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1990 } 1991 1992 /* Configure DMA resource watermarks */ 1993 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1994 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1995 1996 /* Enable buffer manager */ 1997 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1998 /* 1999 * Change the arbitration algorithm of TXMBUF read request to 2000 * round-robin instead of priority based for BCM5719. When 2001 * TXFIFO is almost empty, RDMA will hold its request until 2002 * TXFIFO is not almost empty. 2003 */ 2004 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2005 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2006 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2007 2008 /* Poll for buffer manager start indication */ 2009 for (i = 0; i < BGE_TIMEOUT; i++) { 2010 DELAY(10); 2011 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2012 break; 2013 } 2014 2015 if (i == BGE_TIMEOUT) { 2016 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2017 return (ENXIO); 2018 } 2019 2020 /* Enable flow-through queues */ 2021 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2023 2024 /* Wait until queue initialization is complete */ 2025 for (i = 0; i < BGE_TIMEOUT; i++) { 2026 DELAY(10); 2027 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2028 break; 2029 } 2030 2031 if (i == BGE_TIMEOUT) { 2032 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2033 return (ENXIO); 2034 } 2035 2036 /* 2037 * Summary of rings supported by the controller: 2038 * 2039 * Standard Receive Producer Ring 2040 * - This ring is used to feed receive buffers for "standard" 2041 * sized frames (typically 1536 bytes) to the controller. 2042 * 2043 * Jumbo Receive Producer Ring 2044 * - This ring is used to feed receive buffers for jumbo sized 2045 * frames (i.e. anything bigger than the "standard" frames) 2046 * to the controller. 2047 * 2048 * Mini Receive Producer Ring 2049 * - This ring is used to feed receive buffers for "mini" 2050 * sized frames to the controller. 2051 * - This feature required external memory for the controller 2052 * but was never used in a production system. Should always 2053 * be disabled. 2054 * 2055 * Receive Return Ring 2056 * - After the controller has placed an incoming frame into a 2057 * receive buffer that buffer is moved into a receive return 2058 * ring. The driver is then responsible to passing the 2059 * buffer up to the stack. Many versions of the controller 2060 * support multiple RR rings. 2061 * 2062 * Send Ring 2063 * - This ring is used for outgoing frames. Many versions of 2064 * the controller support multiple send rings. 2065 */ 2066 2067 /* Initialize the standard receive producer ring control block. */ 2068 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2069 rcb->bge_hostaddr.bge_addr_lo = 2070 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2071 rcb->bge_hostaddr.bge_addr_hi = 2072 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2073 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2074 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2075 if (BGE_IS_5717_PLUS(sc)) { 2076 /* 2077 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2078 * Bits 15-2 : Maximum RX frame size 2079 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2080 * Bit 0 : Reserved 2081 */ 2082 rcb->bge_maxlen_flags = 2083 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2084 } else if (BGE_IS_5705_PLUS(sc)) { 2085 /* 2086 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2087 * Bits 15-2 : Reserved (should be 0) 2088 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2089 * Bit 0 : Reserved 2090 */ 2091 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2092 } else { 2093 /* 2094 * Ring size is always XXX entries 2095 * Bits 31-16: Maximum RX frame size 2096 * Bits 15-2 : Reserved (should be 0) 2097 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2098 * Bit 0 : Reserved 2099 */ 2100 rcb->bge_maxlen_flags = 2101 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2102 } 2103 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2104 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2105 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2106 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2107 else 2108 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2109 /* Write the standard receive producer ring control block. */ 2110 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2111 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2112 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2113 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2114 2115 /* Reset the standard receive producer ring producer index. */ 2116 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2117 2118 /* 2119 * Initialize the jumbo RX producer ring control 2120 * block. We set the 'ring disabled' bit in the 2121 * flags field until we're actually ready to start 2122 * using this ring (i.e. once we set the MTU 2123 * high enough to require it). 2124 */ 2125 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2126 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2127 /* Get the jumbo receive producer ring RCB parameters. */ 2128 rcb->bge_hostaddr.bge_addr_lo = 2129 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2130 rcb->bge_hostaddr.bge_addr_hi = 2131 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2132 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2133 sc->bge_cdata.bge_rx_jumbo_ring_map, 2134 BUS_DMASYNC_PREREAD); 2135 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2136 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2137 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2138 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2139 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2140 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2141 else 2142 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2143 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2144 rcb->bge_hostaddr.bge_addr_hi); 2145 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2146 rcb->bge_hostaddr.bge_addr_lo); 2147 /* Program the jumbo receive producer ring RCB parameters. */ 2148 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2149 rcb->bge_maxlen_flags); 2150 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2151 /* Reset the jumbo receive producer ring producer index. */ 2152 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2153 } 2154 2155 /* Disable the mini receive producer ring RCB. */ 2156 if (BGE_IS_5700_FAMILY(sc)) { 2157 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2158 rcb->bge_maxlen_flags = 2159 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2160 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2161 rcb->bge_maxlen_flags); 2162 /* Reset the mini receive producer ring producer index. */ 2163 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2164 } 2165 2166 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2167 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2168 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2169 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2170 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2171 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2172 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2173 } 2174 /* 2175 * The BD ring replenish thresholds control how often the 2176 * hardware fetches new BD's from the producer rings in host 2177 * memory. Setting the value too low on a busy system can 2178 * starve the hardware and recue the throughpout. 2179 * 2180 * Set the BD ring replentish thresholds. The recommended 2181 * values are 1/8th the number of descriptors allocated to 2182 * each ring. 2183 * XXX The 5754 requires a lower threshold, so it might be a 2184 * requirement of all 575x family chips. The Linux driver sets 2185 * the lower threshold for all 5705 family chips as well, but there 2186 * are reports that it might not need to be so strict. 2187 * 2188 * XXX Linux does some extra fiddling here for the 5906 parts as 2189 * well. 2190 */ 2191 if (BGE_IS_5705_PLUS(sc)) 2192 val = 8; 2193 else 2194 val = BGE_STD_RX_RING_CNT / 8; 2195 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2196 if (BGE_IS_JUMBO_CAPABLE(sc)) 2197 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2198 BGE_JUMBO_RX_RING_CNT/8); 2199 if (BGE_IS_5717_PLUS(sc)) { 2200 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2201 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2202 } 2203 2204 /* 2205 * Disable all send rings by setting the 'ring disabled' bit 2206 * in the flags field of all the TX send ring control blocks, 2207 * located in NIC memory. 2208 */ 2209 if (!BGE_IS_5705_PLUS(sc)) 2210 /* 5700 to 5704 had 16 send rings. */ 2211 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2212 else 2213 limit = 1; 2214 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2215 for (i = 0; i < limit; i++) { 2216 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2217 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2218 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2219 vrcb += sizeof(struct bge_rcb); 2220 } 2221 2222 /* Configure send ring RCB 0 (we use only the first ring) */ 2223 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2224 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2225 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2226 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2227 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2228 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2229 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2230 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2231 else 2232 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2233 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2234 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2235 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2236 2237 /* 2238 * Disable all receive return rings by setting the 2239 * 'ring diabled' bit in the flags field of all the receive 2240 * return ring control blocks, located in NIC memory. 2241 */ 2242 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2243 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2244 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2245 /* Should be 17, use 16 until we get an SRAM map. */ 2246 limit = 16; 2247 } else if (!BGE_IS_5705_PLUS(sc)) 2248 limit = BGE_RX_RINGS_MAX; 2249 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2250 BGE_IS_57765_PLUS(sc)) 2251 limit = 4; 2252 else 2253 limit = 1; 2254 /* Disable all receive return rings. */ 2255 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2256 for (i = 0; i < limit; i++) { 2257 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2259 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2260 BGE_RCB_FLAG_RING_DISABLED); 2261 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2262 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2263 (i * (sizeof(uint64_t))), 0); 2264 vrcb += sizeof(struct bge_rcb); 2265 } 2266 2267 /* 2268 * Set up receive return ring 0. Note that the NIC address 2269 * for RX return rings is 0x0. The return rings live entirely 2270 * within the host, so the nicaddr field in the RCB isn't used. 2271 */ 2272 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2273 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2274 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2275 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2276 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2277 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2278 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2279 2280 /* Set random backoff seed for TX */ 2281 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2282 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2283 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2284 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 2285 BGE_TX_BACKOFF_SEED_MASK); 2286 2287 /* Set inter-packet gap */ 2288 val = 0x2620; 2289 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 2290 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2291 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2292 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2293 2294 /* 2295 * Specify which ring to use for packets that don't match 2296 * any RX rules. 2297 */ 2298 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2299 2300 /* 2301 * Configure number of RX lists. One interrupt distribution 2302 * list, sixteen active lists, one bad frames class. 2303 */ 2304 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2305 2306 /* Inialize RX list placement stats mask. */ 2307 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2308 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2309 2310 /* Disable host coalescing until we get it set up */ 2311 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2312 2313 /* Poll to make sure it's shut down. */ 2314 for (i = 0; i < BGE_TIMEOUT; i++) { 2315 DELAY(10); 2316 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2317 break; 2318 } 2319 2320 if (i == BGE_TIMEOUT) { 2321 device_printf(sc->bge_dev, 2322 "host coalescing engine failed to idle\n"); 2323 return (ENXIO); 2324 } 2325 2326 /* Set up host coalescing defaults */ 2327 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2328 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2329 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2330 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2331 if (!(BGE_IS_5705_PLUS(sc))) { 2332 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2333 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2334 } 2335 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2336 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2337 2338 /* Set up address of statistics block */ 2339 if (!(BGE_IS_5705_PLUS(sc))) { 2340 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2341 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2342 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2343 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2344 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2345 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2346 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2347 } 2348 2349 /* Set up address of status block */ 2350 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2351 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2352 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2353 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2354 2355 /* Set up status block size. */ 2356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2357 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2358 val = BGE_STATBLKSZ_FULL; 2359 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2360 } else { 2361 val = BGE_STATBLKSZ_32BYTE; 2362 bzero(sc->bge_ldata.bge_status_block, 32); 2363 } 2364 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2365 sc->bge_cdata.bge_status_map, 2366 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2367 2368 /* Turn on host coalescing state machine */ 2369 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2370 2371 /* Turn on RX BD completion state machine and enable attentions */ 2372 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2373 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2374 2375 /* Turn on RX list placement state machine */ 2376 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2377 2378 /* Turn on RX list selector state machine. */ 2379 if (!(BGE_IS_5705_PLUS(sc))) 2380 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2381 2382 /* Turn on DMA, clear stats. */ 2383 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2384 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2385 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2386 BGE_MACMODE_FRMHDR_DMA_ENB; 2387 2388 if (sc->bge_flags & BGE_FLAG_TBI) 2389 val |= BGE_PORTMODE_TBI; 2390 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2391 val |= BGE_PORTMODE_GMII; 2392 else 2393 val |= BGE_PORTMODE_MII; 2394 2395 /* Allow APE to send/receive frames. */ 2396 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2397 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2398 2399 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2400 DELAY(40); 2401 2402 /* Set misc. local control, enable interrupts on attentions */ 2403 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2404 2405 #ifdef notdef 2406 /* Assert GPIO pins for PHY reset */ 2407 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2408 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2409 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2410 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2411 #endif 2412 2413 /* Turn on DMA completion state machine */ 2414 if (!(BGE_IS_5705_PLUS(sc))) 2415 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2416 2417 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2418 2419 /* Enable host coalescing bug fix. */ 2420 if (BGE_IS_5755_PLUS(sc)) 2421 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2422 2423 /* Request larger DMA burst size to get better performance. */ 2424 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2425 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2426 2427 /* Turn on write DMA state machine */ 2428 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2429 DELAY(40); 2430 2431 /* Turn on read DMA state machine */ 2432 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2433 2434 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2435 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2436 2437 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2438 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2439 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2440 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2441 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2442 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2443 if (sc->bge_flags & BGE_FLAG_PCIE) 2444 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2445 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2446 val |= BGE_RDMAMODE_TSO4_ENABLE; 2447 if (sc->bge_flags & BGE_FLAG_TSO3 || 2448 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2449 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2450 val |= BGE_RDMAMODE_TSO6_ENABLE; 2451 } 2452 2453 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2454 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2455 BGE_RDMAMODE_H2BNC_VLAN_DET; 2456 /* 2457 * Allow multiple outstanding read requests from 2458 * non-LSO read DMA engine. 2459 */ 2460 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2461 } 2462 2463 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2464 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2465 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2466 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2467 BGE_IS_5717_PLUS(sc)) { 2468 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2469 /* 2470 * Adjust tx margin to prevent TX data corruption and 2471 * fix internal FIFO overflow. 2472 */ 2473 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 2474 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2475 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2477 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2478 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2479 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2480 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2481 } 2482 /* 2483 * Enable fix for read DMA FIFO overruns. 2484 * The fix is to limit the number of RX BDs 2485 * the hardware would fetch at a fime. 2486 */ 2487 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2488 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2489 } 2490 2491 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2492 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2493 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2494 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2495 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2496 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2497 /* 2498 * Allow 4KB burst length reads for non-LSO frames. 2499 * Enable 512B burst length reads for buffer descriptors. 2500 */ 2501 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2502 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2503 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2504 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2505 } 2506 2507 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2508 DELAY(40); 2509 2510 /* Turn on RX data completion state machine */ 2511 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2512 2513 /* Turn on RX BD initiator state machine */ 2514 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2515 2516 /* Turn on RX data and RX BD initiator state machine */ 2517 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2518 2519 /* Turn on Mbuf cluster free state machine */ 2520 if (!(BGE_IS_5705_PLUS(sc))) 2521 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2522 2523 /* Turn on send BD completion state machine */ 2524 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2525 2526 /* Turn on send data completion state machine */ 2527 val = BGE_SDCMODE_ENABLE; 2528 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2529 val |= BGE_SDCMODE_CDELAY; 2530 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2531 2532 /* Turn on send data initiator state machine */ 2533 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2534 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2535 BGE_SDIMODE_HW_LSO_PRE_DMA); 2536 else 2537 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2538 2539 /* Turn on send BD initiator state machine */ 2540 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2541 2542 /* Turn on send BD selector state machine */ 2543 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2544 2545 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2546 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2547 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2548 2549 /* ack/clear link change events */ 2550 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2551 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2552 BGE_MACSTAT_LINK_CHANGED); 2553 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2554 2555 /* 2556 * Enable attention when the link has changed state for 2557 * devices that use auto polling. 2558 */ 2559 if (sc->bge_flags & BGE_FLAG_TBI) { 2560 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2561 } else { 2562 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2563 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2564 DELAY(80); 2565 } 2566 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2567 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2568 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2569 BGE_EVTENB_MI_INTERRUPT); 2570 } 2571 2572 /* 2573 * Clear any pending link state attention. 2574 * Otherwise some link state change events may be lost until attention 2575 * is cleared by bge_intr() -> bge_link_upd() sequence. 2576 * It's not necessary on newer BCM chips - perhaps enabling link 2577 * state change attentions implies clearing pending attention. 2578 */ 2579 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2580 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2581 BGE_MACSTAT_LINK_CHANGED); 2582 2583 /* Enable link state change attentions. */ 2584 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2585 2586 return (0); 2587 } 2588 2589 const struct bge_revision * 2590 bge_lookup_rev(uint32_t chipid) 2591 { 2592 const struct bge_revision *br; 2593 2594 for (br = bge_revisions; br->br_name != NULL; br++) { 2595 if (br->br_chipid == chipid) 2596 return (br); 2597 } 2598 2599 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2600 if (br->br_chipid == BGE_ASICREV(chipid)) 2601 return (br); 2602 } 2603 2604 return (NULL); 2605 } 2606 2607 const struct bge_vendor * 2608 bge_lookup_vendor(uint16_t vid) 2609 { 2610 const struct bge_vendor *v; 2611 2612 for (v = bge_vendors; v->v_name != NULL; v++) 2613 if (v->v_id == vid) 2614 return (v); 2615 2616 panic("%s: unknown vendor %d", __func__, vid); 2617 return (NULL); 2618 } 2619 2620 /* 2621 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2622 * against our list and return its name if we find a match. 2623 * 2624 * Note that since the Broadcom controller contains VPD support, we 2625 * try to get the device name string from the controller itself instead 2626 * of the compiled-in string. It guarantees we'll always announce the 2627 * right product name. We fall back to the compiled-in string when 2628 * VPD is unavailable or corrupt. 2629 */ 2630 static int 2631 bge_probe(device_t dev) 2632 { 2633 char buf[96]; 2634 char model[64]; 2635 const struct bge_revision *br; 2636 const char *pname; 2637 struct bge_softc *sc = device_get_softc(dev); 2638 const struct bge_type *t = bge_devs; 2639 const struct bge_vendor *v; 2640 uint32_t id; 2641 uint16_t did, vid; 2642 2643 sc->bge_dev = dev; 2644 vid = pci_get_vendor(dev); 2645 did = pci_get_device(dev); 2646 while(t->bge_vid != 0) { 2647 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2648 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2649 BGE_PCIMISCCTL_ASICREV_SHIFT; 2650 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2651 /* 2652 * Find the ASCI revision. Different chips 2653 * use different registers. 2654 */ 2655 switch (pci_get_device(dev)) { 2656 case BCOM_DEVICEID_BCM5717: 2657 case BCOM_DEVICEID_BCM5718: 2658 case BCOM_DEVICEID_BCM5719: 2659 case BCOM_DEVICEID_BCM5720: 2660 id = pci_read_config(dev, 2661 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2662 break; 2663 case BCOM_DEVICEID_BCM57761: 2664 case BCOM_DEVICEID_BCM57762: 2665 case BCOM_DEVICEID_BCM57765: 2666 case BCOM_DEVICEID_BCM57766: 2667 case BCOM_DEVICEID_BCM57781: 2668 case BCOM_DEVICEID_BCM57785: 2669 case BCOM_DEVICEID_BCM57791: 2670 case BCOM_DEVICEID_BCM57795: 2671 id = pci_read_config(dev, 2672 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2673 break; 2674 default: 2675 id = pci_read_config(dev, 2676 BGE_PCI_PRODID_ASICREV, 4); 2677 } 2678 } 2679 br = bge_lookup_rev(id); 2680 v = bge_lookup_vendor(vid); 2681 if (bge_has_eaddr(sc) && 2682 pci_get_vpd_ident(dev, &pname) == 0) 2683 snprintf(model, 64, "%s", pname); 2684 else 2685 snprintf(model, 64, "%s %s", v->v_name, 2686 br != NULL ? br->br_name : 2687 "NetXtreme Ethernet Controller"); 2688 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2689 br != NULL ? "" : "unknown ", id); 2690 device_set_desc_copy(dev, buf); 2691 return (0); 2692 } 2693 t++; 2694 } 2695 2696 return (ENXIO); 2697 } 2698 2699 static void 2700 bge_dma_free(struct bge_softc *sc) 2701 { 2702 int i; 2703 2704 /* Destroy DMA maps for RX buffers. */ 2705 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2706 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2707 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2708 sc->bge_cdata.bge_rx_std_dmamap[i]); 2709 } 2710 if (sc->bge_cdata.bge_rx_std_sparemap) 2711 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2712 sc->bge_cdata.bge_rx_std_sparemap); 2713 2714 /* Destroy DMA maps for jumbo RX buffers. */ 2715 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2716 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2717 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2718 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2719 } 2720 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2721 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2722 sc->bge_cdata.bge_rx_jumbo_sparemap); 2723 2724 /* Destroy DMA maps for TX buffers. */ 2725 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2726 if (sc->bge_cdata.bge_tx_dmamap[i]) 2727 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2728 sc->bge_cdata.bge_tx_dmamap[i]); 2729 } 2730 2731 if (sc->bge_cdata.bge_rx_mtag) 2732 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2733 if (sc->bge_cdata.bge_mtag_jumbo) 2734 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2735 if (sc->bge_cdata.bge_tx_mtag) 2736 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2737 2738 /* Destroy standard RX ring. */ 2739 if (sc->bge_cdata.bge_rx_std_ring_map) 2740 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2741 sc->bge_cdata.bge_rx_std_ring_map); 2742 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2743 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2744 sc->bge_ldata.bge_rx_std_ring, 2745 sc->bge_cdata.bge_rx_std_ring_map); 2746 2747 if (sc->bge_cdata.bge_rx_std_ring_tag) 2748 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2749 2750 /* Destroy jumbo RX ring. */ 2751 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2752 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2753 sc->bge_cdata.bge_rx_jumbo_ring_map); 2754 2755 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2756 sc->bge_ldata.bge_rx_jumbo_ring) 2757 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2758 sc->bge_ldata.bge_rx_jumbo_ring, 2759 sc->bge_cdata.bge_rx_jumbo_ring_map); 2760 2761 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2762 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2763 2764 /* Destroy RX return ring. */ 2765 if (sc->bge_cdata.bge_rx_return_ring_map) 2766 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2767 sc->bge_cdata.bge_rx_return_ring_map); 2768 2769 if (sc->bge_cdata.bge_rx_return_ring_map && 2770 sc->bge_ldata.bge_rx_return_ring) 2771 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2772 sc->bge_ldata.bge_rx_return_ring, 2773 sc->bge_cdata.bge_rx_return_ring_map); 2774 2775 if (sc->bge_cdata.bge_rx_return_ring_tag) 2776 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2777 2778 /* Destroy TX ring. */ 2779 if (sc->bge_cdata.bge_tx_ring_map) 2780 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2781 sc->bge_cdata.bge_tx_ring_map); 2782 2783 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2784 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2785 sc->bge_ldata.bge_tx_ring, 2786 sc->bge_cdata.bge_tx_ring_map); 2787 2788 if (sc->bge_cdata.bge_tx_ring_tag) 2789 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2790 2791 /* Destroy status block. */ 2792 if (sc->bge_cdata.bge_status_map) 2793 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2794 sc->bge_cdata.bge_status_map); 2795 2796 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2797 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2798 sc->bge_ldata.bge_status_block, 2799 sc->bge_cdata.bge_status_map); 2800 2801 if (sc->bge_cdata.bge_status_tag) 2802 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2803 2804 /* Destroy statistics block. */ 2805 if (sc->bge_cdata.bge_stats_map) 2806 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2807 sc->bge_cdata.bge_stats_map); 2808 2809 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2810 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2811 sc->bge_ldata.bge_stats, 2812 sc->bge_cdata.bge_stats_map); 2813 2814 if (sc->bge_cdata.bge_stats_tag) 2815 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2816 2817 if (sc->bge_cdata.bge_buffer_tag) 2818 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2819 2820 /* Destroy the parent tag. */ 2821 if (sc->bge_cdata.bge_parent_tag) 2822 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2823 } 2824 2825 static int 2826 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2827 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2828 bus_addr_t *paddr, const char *msg) 2829 { 2830 struct bge_dmamap_arg ctx; 2831 int error; 2832 2833 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2834 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2835 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2836 if (error != 0) { 2837 device_printf(sc->bge_dev, 2838 "could not create %s dma tag\n", msg); 2839 return (ENOMEM); 2840 } 2841 /* Allocate DMA'able memory for ring. */ 2842 error = bus_dmamem_alloc(*tag, (void **)ring, 2843 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2844 if (error != 0) { 2845 device_printf(sc->bge_dev, 2846 "could not allocate DMA'able memory for %s\n", msg); 2847 return (ENOMEM); 2848 } 2849 /* Load the address of the ring. */ 2850 ctx.bge_busaddr = 0; 2851 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2852 &ctx, BUS_DMA_NOWAIT); 2853 if (error != 0) { 2854 device_printf(sc->bge_dev, 2855 "could not load DMA'able memory for %s\n", msg); 2856 return (ENOMEM); 2857 } 2858 *paddr = ctx.bge_busaddr; 2859 return (0); 2860 } 2861 2862 static int 2863 bge_dma_alloc(struct bge_softc *sc) 2864 { 2865 bus_addr_t lowaddr; 2866 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2867 int i, error; 2868 2869 lowaddr = BUS_SPACE_MAXADDR; 2870 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2871 lowaddr = BGE_DMA_MAXADDR; 2872 /* 2873 * Allocate the parent bus DMA tag appropriate for PCI. 2874 */ 2875 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2876 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2877 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2878 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2879 if (error != 0) { 2880 device_printf(sc->bge_dev, 2881 "could not allocate parent dma tag\n"); 2882 return (ENOMEM); 2883 } 2884 2885 /* Create tag for standard RX ring. */ 2886 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2887 &sc->bge_cdata.bge_rx_std_ring_tag, 2888 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2889 &sc->bge_cdata.bge_rx_std_ring_map, 2890 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2891 if (error) 2892 return (error); 2893 2894 /* Create tag for RX return ring. */ 2895 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2896 &sc->bge_cdata.bge_rx_return_ring_tag, 2897 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2898 &sc->bge_cdata.bge_rx_return_ring_map, 2899 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2900 if (error) 2901 return (error); 2902 2903 /* Create tag for TX ring. */ 2904 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2905 &sc->bge_cdata.bge_tx_ring_tag, 2906 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2907 &sc->bge_cdata.bge_tx_ring_map, 2908 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2909 if (error) 2910 return (error); 2911 2912 /* 2913 * Create tag for status block. 2914 * Because we only use single Tx/Rx/Rx return ring, use 2915 * minimum status block size except BCM5700 AX/BX which 2916 * seems to want to see full status block size regardless 2917 * of configured number of ring. 2918 */ 2919 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2920 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2921 sbsz = BGE_STATUS_BLK_SZ; 2922 else 2923 sbsz = 32; 2924 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2925 &sc->bge_cdata.bge_status_tag, 2926 (uint8_t **)&sc->bge_ldata.bge_status_block, 2927 &sc->bge_cdata.bge_status_map, 2928 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2929 if (error) 2930 return (error); 2931 2932 /* Create tag for statistics block. */ 2933 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2934 &sc->bge_cdata.bge_stats_tag, 2935 (uint8_t **)&sc->bge_ldata.bge_stats, 2936 &sc->bge_cdata.bge_stats_map, 2937 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2938 if (error) 2939 return (error); 2940 2941 /* Create tag for jumbo RX ring. */ 2942 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2943 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2944 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2945 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2946 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2947 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2948 if (error) 2949 return (error); 2950 } 2951 2952 /* Create parent tag for buffers. */ 2953 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2954 /* 2955 * XXX 2956 * watchdog timeout issue was observed on BCM5704 which 2957 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2958 * Both limiting DMA address space to 32bits and flushing 2959 * mailbox write seem to address the issue. 2960 */ 2961 if (sc->bge_pcixcap != 0) 2962 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2963 } 2964 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 2965 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 2966 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 2967 &sc->bge_cdata.bge_buffer_tag); 2968 if (error != 0) { 2969 device_printf(sc->bge_dev, 2970 "could not allocate buffer dma tag\n"); 2971 return (ENOMEM); 2972 } 2973 /* Create tag for Tx mbufs. */ 2974 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2975 txsegsz = BGE_TSOSEG_SZ; 2976 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2977 } else { 2978 txsegsz = MCLBYTES; 2979 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2980 } 2981 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2982 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2983 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2984 &sc->bge_cdata.bge_tx_mtag); 2985 2986 if (error) { 2987 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2988 return (ENOMEM); 2989 } 2990 2991 /* Create tag for Rx mbufs. */ 2992 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 2993 rxmaxsegsz = MJUM9BYTES; 2994 else 2995 rxmaxsegsz = MCLBYTES; 2996 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 2998 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2999 3000 if (error) { 3001 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3002 return (ENOMEM); 3003 } 3004 3005 /* Create DMA maps for RX buffers. */ 3006 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3007 &sc->bge_cdata.bge_rx_std_sparemap); 3008 if (error) { 3009 device_printf(sc->bge_dev, 3010 "can't create spare DMA map for RX\n"); 3011 return (ENOMEM); 3012 } 3013 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3014 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3015 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3016 if (error) { 3017 device_printf(sc->bge_dev, 3018 "can't create DMA map for RX\n"); 3019 return (ENOMEM); 3020 } 3021 } 3022 3023 /* Create DMA maps for TX buffers. */ 3024 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3025 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3026 &sc->bge_cdata.bge_tx_dmamap[i]); 3027 if (error) { 3028 device_printf(sc->bge_dev, 3029 "can't create DMA map for TX\n"); 3030 return (ENOMEM); 3031 } 3032 } 3033 3034 /* Create tags for jumbo RX buffers. */ 3035 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3036 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3037 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3038 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3039 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3040 if (error) { 3041 device_printf(sc->bge_dev, 3042 "could not allocate jumbo dma tag\n"); 3043 return (ENOMEM); 3044 } 3045 /* Create DMA maps for jumbo RX buffers. */ 3046 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3047 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3048 if (error) { 3049 device_printf(sc->bge_dev, 3050 "can't create spare DMA map for jumbo RX\n"); 3051 return (ENOMEM); 3052 } 3053 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3054 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3055 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3056 if (error) { 3057 device_printf(sc->bge_dev, 3058 "can't create DMA map for jumbo RX\n"); 3059 return (ENOMEM); 3060 } 3061 } 3062 } 3063 3064 return (0); 3065 } 3066 3067 /* 3068 * Return true if this device has more than one port. 3069 */ 3070 static int 3071 bge_has_multiple_ports(struct bge_softc *sc) 3072 { 3073 device_t dev = sc->bge_dev; 3074 u_int b, d, f, fscan, s; 3075 3076 d = pci_get_domain(dev); 3077 b = pci_get_bus(dev); 3078 s = pci_get_slot(dev); 3079 f = pci_get_function(dev); 3080 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3081 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3082 return (1); 3083 return (0); 3084 } 3085 3086 /* 3087 * Return true if MSI can be used with this device. 3088 */ 3089 static int 3090 bge_can_use_msi(struct bge_softc *sc) 3091 { 3092 int can_use_msi = 0; 3093 3094 if (sc->bge_msi == 0) 3095 return (0); 3096 3097 /* Disable MSI for polling(4). */ 3098 #ifdef DEVICE_POLLING 3099 return (0); 3100 #endif 3101 switch (sc->bge_asicrev) { 3102 case BGE_ASICREV_BCM5714_A0: 3103 case BGE_ASICREV_BCM5714: 3104 /* 3105 * Apparently, MSI doesn't work when these chips are 3106 * configured in single-port mode. 3107 */ 3108 if (bge_has_multiple_ports(sc)) 3109 can_use_msi = 1; 3110 break; 3111 case BGE_ASICREV_BCM5750: 3112 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3113 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3114 can_use_msi = 1; 3115 break; 3116 default: 3117 if (BGE_IS_575X_PLUS(sc)) 3118 can_use_msi = 1; 3119 } 3120 return (can_use_msi); 3121 } 3122 3123 static int 3124 bge_mbox_reorder(struct bge_softc *sc) 3125 { 3126 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3127 static const struct mbox_reorder { 3128 const uint16_t vendor; 3129 const uint16_t device; 3130 const char *desc; 3131 } mbox_reorder_lists[] = { 3132 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3133 }; 3134 devclass_t pci, pcib; 3135 device_t bus, dev; 3136 int i; 3137 3138 pci = devclass_find("pci"); 3139 pcib = devclass_find("pcib"); 3140 dev = sc->bge_dev; 3141 bus = device_get_parent(dev); 3142 for (;;) { 3143 dev = device_get_parent(bus); 3144 bus = device_get_parent(dev); 3145 if (device_get_devclass(dev) != pcib) 3146 break; 3147 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3148 if (pci_get_vendor(dev) == 3149 mbox_reorder_lists[i].vendor && 3150 pci_get_device(dev) == 3151 mbox_reorder_lists[i].device) { 3152 device_printf(sc->bge_dev, 3153 "enabling MBOX workaround for %s\n", 3154 mbox_reorder_lists[i].desc); 3155 return (1); 3156 } 3157 } 3158 if (device_get_devclass(bus) != pci) 3159 break; 3160 } 3161 return (0); 3162 } 3163 3164 static void 3165 bge_devinfo(struct bge_softc *sc) 3166 { 3167 uint32_t cfg, clk; 3168 3169 device_printf(sc->bge_dev, 3170 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3171 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3172 if (sc->bge_flags & BGE_FLAG_PCIE) 3173 printf("PCI-E\n"); 3174 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3175 printf("PCI-X "); 3176 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3177 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3178 clk = 133; 3179 else { 3180 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3181 switch (clk) { 3182 case 0: 3183 clk = 33; 3184 break; 3185 case 2: 3186 clk = 50; 3187 break; 3188 case 4: 3189 clk = 66; 3190 break; 3191 case 6: 3192 clk = 100; 3193 break; 3194 case 7: 3195 clk = 133; 3196 break; 3197 } 3198 } 3199 printf("%u MHz\n", clk); 3200 } else { 3201 if (sc->bge_pcixcap != 0) 3202 printf("PCI on PCI-X "); 3203 else 3204 printf("PCI "); 3205 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3206 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3207 clk = 66; 3208 else 3209 clk = 33; 3210 if (cfg & BGE_PCISTATE_32BIT_BUS) 3211 printf("%u MHz; 32bit\n", clk); 3212 else 3213 printf("%u MHz; 64bit\n", clk); 3214 } 3215 } 3216 3217 static int 3218 bge_attach(device_t dev) 3219 { 3220 struct ifnet *ifp; 3221 struct bge_softc *sc; 3222 uint32_t hwcfg = 0, misccfg, pcistate; 3223 u_char eaddr[ETHER_ADDR_LEN]; 3224 int capmask, error, msicount, reg, rid, trys; 3225 3226 sc = device_get_softc(dev); 3227 sc->bge_dev = dev; 3228 3229 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3230 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3231 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3232 3233 /* 3234 * Map control/status registers. 3235 */ 3236 pci_enable_busmaster(dev); 3237 3238 rid = PCIR_BAR(0); 3239 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3240 RF_ACTIVE); 3241 3242 if (sc->bge_res == NULL) { 3243 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3244 error = ENXIO; 3245 goto fail; 3246 } 3247 3248 /* Save various chip information. */ 3249 sc->bge_func_addr = pci_get_function(dev); 3250 sc->bge_chipid = 3251 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 3252 BGE_PCIMISCCTL_ASICREV_SHIFT; 3253 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 3254 /* 3255 * Find the ASCI revision. Different chips use different 3256 * registers. 3257 */ 3258 switch (pci_get_device(dev)) { 3259 case BCOM_DEVICEID_BCM5717: 3260 case BCOM_DEVICEID_BCM5718: 3261 case BCOM_DEVICEID_BCM5719: 3262 case BCOM_DEVICEID_BCM5720: 3263 sc->bge_chipid = pci_read_config(dev, 3264 BGE_PCI_GEN2_PRODID_ASICREV, 4); 3265 break; 3266 case BCOM_DEVICEID_BCM57761: 3267 case BCOM_DEVICEID_BCM57762: 3268 case BCOM_DEVICEID_BCM57765: 3269 case BCOM_DEVICEID_BCM57766: 3270 case BCOM_DEVICEID_BCM57781: 3271 case BCOM_DEVICEID_BCM57785: 3272 case BCOM_DEVICEID_BCM57791: 3273 case BCOM_DEVICEID_BCM57795: 3274 sc->bge_chipid = pci_read_config(dev, 3275 BGE_PCI_GEN15_PRODID_ASICREV, 4); 3276 break; 3277 default: 3278 sc->bge_chipid = pci_read_config(dev, 3279 BGE_PCI_PRODID_ASICREV, 4); 3280 } 3281 } 3282 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3283 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3284 3285 /* Set default PHY address. */ 3286 sc->bge_phy_addr = 1; 3287 /* 3288 * PHY address mapping for various devices. 3289 * 3290 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3291 * ---------+-------+-------+-------+-------+ 3292 * BCM57XX | 1 | X | X | X | 3293 * BCM5704 | 1 | X | 1 | X | 3294 * BCM5717 | 1 | 8 | 2 | 9 | 3295 * BCM5719 | 1 | 8 | 2 | 9 | 3296 * BCM5720 | 1 | 8 | 2 | 9 | 3297 * 3298 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3299 * ---------+-------+-------+-------+-------+ 3300 * BCM57XX | X | X | X | X | 3301 * BCM5704 | X | X | X | X | 3302 * BCM5717 | X | X | X | X | 3303 * BCM5719 | 3 | 10 | 4 | 11 | 3304 * BCM5720 | X | X | X | X | 3305 * 3306 * Other addresses may respond but they are not 3307 * IEEE compliant PHYs and should be ignored. 3308 */ 3309 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3310 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3311 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3312 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3313 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3314 BGE_SGDIGSTS_IS_SERDES) 3315 sc->bge_phy_addr = sc->bge_func_addr + 8; 3316 else 3317 sc->bge_phy_addr = sc->bge_func_addr + 1; 3318 } else { 3319 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3320 BGE_CPMU_PHY_STRAP_IS_SERDES) 3321 sc->bge_phy_addr = sc->bge_func_addr + 8; 3322 else 3323 sc->bge_phy_addr = sc->bge_func_addr + 1; 3324 } 3325 } 3326 3327 if (bge_has_eaddr(sc)) 3328 sc->bge_flags |= BGE_FLAG_EADDR; 3329 3330 /* Save chipset family. */ 3331 switch (sc->bge_asicrev) { 3332 case BGE_ASICREV_BCM57765: 3333 case BGE_ASICREV_BCM57766: 3334 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3335 /* FALLTHROUGH */ 3336 case BGE_ASICREV_BCM5717: 3337 case BGE_ASICREV_BCM5719: 3338 case BGE_ASICREV_BCM5720: 3339 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3340 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3341 BGE_FLAG_JUMBO_FRAME; 3342 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3343 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3344 /* Jumbo frame on BCM5719 A0 does not work. */ 3345 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3346 } 3347 break; 3348 case BGE_ASICREV_BCM5755: 3349 case BGE_ASICREV_BCM5761: 3350 case BGE_ASICREV_BCM5784: 3351 case BGE_ASICREV_BCM5785: 3352 case BGE_ASICREV_BCM5787: 3353 case BGE_ASICREV_BCM57780: 3354 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3355 BGE_FLAG_5705_PLUS; 3356 break; 3357 case BGE_ASICREV_BCM5700: 3358 case BGE_ASICREV_BCM5701: 3359 case BGE_ASICREV_BCM5703: 3360 case BGE_ASICREV_BCM5704: 3361 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3362 break; 3363 case BGE_ASICREV_BCM5714_A0: 3364 case BGE_ASICREV_BCM5780: 3365 case BGE_ASICREV_BCM5714: 3366 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3367 /* FALLTHROUGH */ 3368 case BGE_ASICREV_BCM5750: 3369 case BGE_ASICREV_BCM5752: 3370 case BGE_ASICREV_BCM5906: 3371 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3372 /* FALLTHROUGH */ 3373 case BGE_ASICREV_BCM5705: 3374 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3375 break; 3376 } 3377 3378 /* Identify chips with APE processor. */ 3379 switch (sc->bge_asicrev) { 3380 case BGE_ASICREV_BCM5717: 3381 case BGE_ASICREV_BCM5719: 3382 case BGE_ASICREV_BCM5720: 3383 case BGE_ASICREV_BCM5761: 3384 sc->bge_flags |= BGE_FLAG_APE; 3385 break; 3386 } 3387 3388 /* Chips with APE need BAR2 access for APE registers/memory. */ 3389 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3390 rid = PCIR_BAR(2); 3391 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3392 RF_ACTIVE); 3393 if (sc->bge_res2 == NULL) { 3394 device_printf (sc->bge_dev, 3395 "couldn't map BAR2 memory\n"); 3396 error = ENXIO; 3397 goto fail; 3398 } 3399 3400 /* Enable APE register/memory access by host driver. */ 3401 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3402 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3403 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3404 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3405 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3406 3407 bge_ape_lock_init(sc); 3408 bge_ape_read_fw_ver(sc); 3409 } 3410 3411 /* Add SYSCTLs, requires the chipset family to be set. */ 3412 bge_add_sysctls(sc); 3413 3414 /* Identify the chips that use an CPMU. */ 3415 if (BGE_IS_5717_PLUS(sc) || 3416 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3417 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3418 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3419 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3420 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3421 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3422 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3423 else 3424 sc->bge_mi_mode = BGE_MIMODE_BASE; 3425 /* Enable auto polling for BCM570[0-5]. */ 3426 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3427 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3428 3429 /* 3430 * All Broadcom controllers have 4GB boundary DMA bug. 3431 * Whenever an address crosses a multiple of the 4GB boundary 3432 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3433 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3434 * state machine will lockup and cause the device to hang. 3435 */ 3436 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3437 3438 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3439 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3440 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3441 3442 /* 3443 * BCM5719 cannot handle DMA requests for DMA segments that 3444 * have larger than 4KB in size. However the maximum DMA 3445 * segment size created in DMA tag is 4KB for TSO, so we 3446 * wouldn't encounter the issue here. 3447 */ 3448 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3449 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3450 3451 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3452 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3453 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3454 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3455 sc->bge_flags |= BGE_FLAG_5788; 3456 } 3457 3458 capmask = BMSR_DEFCAPMASK; 3459 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3460 (misccfg == 0x4000 || misccfg == 0x8000)) || 3461 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3462 pci_get_vendor(dev) == BCOM_VENDORID && 3463 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3464 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3465 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3466 (pci_get_vendor(dev) == BCOM_VENDORID && 3467 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3468 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3469 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3470 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3471 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3472 /* These chips are 10/100 only. */ 3473 capmask &= ~BMSR_EXTSTAT; 3474 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3475 } 3476 3477 /* 3478 * Some controllers seem to require a special firmware to use 3479 * TSO. But the firmware is not available to FreeBSD and Linux 3480 * claims that the TSO performed by the firmware is slower than 3481 * hardware based TSO. Moreover the firmware based TSO has one 3482 * known bug which can't handle TSO if ethernet header + IP/TCP 3483 * header is greater than 80 bytes. The workaround for the TSO 3484 * bug exist but it seems it's too expensive than not using 3485 * TSO at all. Some hardwares also have the TSO bug so limit 3486 * the TSO to the controllers that are not affected TSO issues 3487 * (e.g. 5755 or higher). 3488 */ 3489 if (BGE_IS_5717_PLUS(sc)) { 3490 /* BCM5717 requires different TSO configuration. */ 3491 sc->bge_flags |= BGE_FLAG_TSO3; 3492 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3493 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3494 /* TSO on BCM5719 A0 does not work. */ 3495 sc->bge_flags &= ~BGE_FLAG_TSO3; 3496 } 3497 } else if (BGE_IS_5755_PLUS(sc)) { 3498 /* 3499 * BCM5754 and BCM5787 shares the same ASIC id so 3500 * explicit device id check is required. 3501 * Due to unknown reason TSO does not work on BCM5755M. 3502 */ 3503 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3504 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3505 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3506 sc->bge_flags |= BGE_FLAG_TSO; 3507 } 3508 3509 /* 3510 * Check if this is a PCI-X or PCI Express device. 3511 */ 3512 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3513 /* 3514 * Found a PCI Express capabilities register, this 3515 * must be a PCI Express device. 3516 */ 3517 sc->bge_flags |= BGE_FLAG_PCIE; 3518 sc->bge_expcap = reg; 3519 /* Extract supported maximum payload size. */ 3520 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3521 PCIER_DEVICE_CAP, 2); 3522 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3523 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3524 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3525 sc->bge_expmrq = 2048; 3526 else 3527 sc->bge_expmrq = 4096; 3528 pci_set_max_read_req(dev, sc->bge_expmrq); 3529 } else { 3530 /* 3531 * Check if the device is in PCI-X Mode. 3532 * (This bit is not valid on PCI Express controllers.) 3533 */ 3534 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3535 sc->bge_pcixcap = reg; 3536 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3537 BGE_PCISTATE_PCI_BUSMODE) == 0) 3538 sc->bge_flags |= BGE_FLAG_PCIX; 3539 } 3540 3541 /* 3542 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3543 * not actually a MAC controller bug but an issue with the embedded 3544 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3545 */ 3546 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3547 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3548 /* 3549 * Some PCI-X bridges are known to trigger write reordering to 3550 * the mailbox registers. Typical phenomena is watchdog timeouts 3551 * caused by out-of-order TX completions. Enable workaround for 3552 * PCI-X devices that live behind these bridges. 3553 * Note, PCI-X controllers can run in PCI mode so we can't use 3554 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3555 */ 3556 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3557 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3558 /* 3559 * Allocate the interrupt, using MSI if possible. These devices 3560 * support 8 MSI messages, but only the first one is used in 3561 * normal operation. 3562 */ 3563 rid = 0; 3564 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3565 sc->bge_msicap = reg; 3566 if (bge_can_use_msi(sc)) { 3567 msicount = pci_msi_count(dev); 3568 if (msicount > 1) 3569 msicount = 1; 3570 } else 3571 msicount = 0; 3572 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3573 rid = 1; 3574 sc->bge_flags |= BGE_FLAG_MSI; 3575 } 3576 } 3577 3578 /* 3579 * All controllers except BCM5700 supports tagged status but 3580 * we use tagged status only for MSI case on BCM5717. Otherwise 3581 * MSI on BCM5717 does not work. 3582 */ 3583 #ifndef DEVICE_POLLING 3584 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3585 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3586 #endif 3587 3588 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3589 RF_SHAREABLE | RF_ACTIVE); 3590 3591 if (sc->bge_irq == NULL) { 3592 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3593 error = ENXIO; 3594 goto fail; 3595 } 3596 3597 bge_devinfo(sc); 3598 3599 sc->bge_asf_mode = 0; 3600 /* No ASF if APE present. */ 3601 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3602 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3603 BGE_SRAM_DATA_SIG_MAGIC)) { 3604 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3605 BGE_HWCFG_ASF) { 3606 sc->bge_asf_mode |= ASF_ENABLE; 3607 sc->bge_asf_mode |= ASF_STACKUP; 3608 if (BGE_IS_575X_PLUS(sc)) 3609 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3610 } 3611 } 3612 } 3613 3614 bge_stop_fw(sc); 3615 bge_sig_pre_reset(sc, BGE_RESET_START); 3616 if (bge_reset(sc)) { 3617 device_printf(sc->bge_dev, "chip reset failed\n"); 3618 error = ENXIO; 3619 goto fail; 3620 } 3621 3622 bge_sig_legacy(sc, BGE_RESET_START); 3623 bge_sig_post_reset(sc, BGE_RESET_START); 3624 3625 if (bge_chipinit(sc)) { 3626 device_printf(sc->bge_dev, "chip initialization failed\n"); 3627 error = ENXIO; 3628 goto fail; 3629 } 3630 3631 error = bge_get_eaddr(sc, eaddr); 3632 if (error) { 3633 device_printf(sc->bge_dev, 3634 "failed to read station address\n"); 3635 error = ENXIO; 3636 goto fail; 3637 } 3638 3639 /* 5705 limits RX return ring to 512 entries. */ 3640 if (BGE_IS_5717_PLUS(sc)) 3641 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3642 else if (BGE_IS_5705_PLUS(sc)) 3643 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3644 else 3645 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3646 3647 if (bge_dma_alloc(sc)) { 3648 device_printf(sc->bge_dev, 3649 "failed to allocate DMA resources\n"); 3650 error = ENXIO; 3651 goto fail; 3652 } 3653 3654 /* Set default tuneable values. */ 3655 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3656 sc->bge_rx_coal_ticks = 150; 3657 sc->bge_tx_coal_ticks = 150; 3658 sc->bge_rx_max_coal_bds = 10; 3659 sc->bge_tx_max_coal_bds = 10; 3660 3661 /* Initialize checksum features to use. */ 3662 sc->bge_csum_features = BGE_CSUM_FEATURES; 3663 if (sc->bge_forced_udpcsum != 0) 3664 sc->bge_csum_features |= CSUM_UDP; 3665 3666 /* Set up ifnet structure */ 3667 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3668 if (ifp == NULL) { 3669 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3670 error = ENXIO; 3671 goto fail; 3672 } 3673 ifp->if_softc = sc; 3674 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3675 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3676 ifp->if_ioctl = bge_ioctl; 3677 ifp->if_start = bge_start; 3678 ifp->if_init = bge_init; 3679 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3680 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3681 IFQ_SET_READY(&ifp->if_snd); 3682 ifp->if_hwassist = sc->bge_csum_features; 3683 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3684 IFCAP_VLAN_MTU; 3685 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3686 ifp->if_hwassist |= CSUM_TSO; 3687 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3688 } 3689 #ifdef IFCAP_VLAN_HWCSUM 3690 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3691 #endif 3692 ifp->if_capenable = ifp->if_capabilities; 3693 #ifdef DEVICE_POLLING 3694 ifp->if_capabilities |= IFCAP_POLLING; 3695 #endif 3696 3697 /* 3698 * 5700 B0 chips do not support checksumming correctly due 3699 * to hardware bugs. 3700 */ 3701 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3702 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3703 ifp->if_capenable &= ~IFCAP_HWCSUM; 3704 ifp->if_hwassist = 0; 3705 } 3706 3707 /* 3708 * Figure out what sort of media we have by checking the 3709 * hardware config word in the first 32k of NIC internal memory, 3710 * or fall back to examining the EEPROM if necessary. 3711 * Note: on some BCM5700 cards, this value appears to be unset. 3712 * If that's the case, we have to rely on identifying the NIC 3713 * by its PCI subsystem ID, as we do below for the SysKonnect 3714 * SK-9D41. 3715 */ 3716 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3717 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3718 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3719 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3720 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3721 sizeof(hwcfg))) { 3722 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3723 error = ENXIO; 3724 goto fail; 3725 } 3726 hwcfg = ntohl(hwcfg); 3727 } 3728 3729 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3730 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3731 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3732 if (BGE_IS_5705_PLUS(sc)) { 3733 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3734 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3735 } else 3736 sc->bge_flags |= BGE_FLAG_TBI; 3737 } 3738 3739 /* Set various PHY bug flags. */ 3740 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3741 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3742 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3743 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3744 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3745 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3746 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3747 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3748 if (pci_get_subvendor(dev) == DELL_VENDORID) 3749 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3750 if ((BGE_IS_5705_PLUS(sc)) && 3751 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3752 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3753 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3754 !BGE_IS_5717_PLUS(sc)) { 3755 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3756 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3757 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3758 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3759 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3760 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3761 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3762 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3763 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3764 } else 3765 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3766 } 3767 3768 /* 3769 * Don't enable Ethernet@WireSpeed for the 5700 or the 3770 * 5705 A0 and A1 chips. 3771 */ 3772 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3773 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3774 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3775 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3776 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3777 3778 if (sc->bge_flags & BGE_FLAG_TBI) { 3779 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3780 bge_ifmedia_sts); 3781 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3782 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3783 0, NULL); 3784 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3785 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3786 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3787 } else { 3788 /* 3789 * Do transceiver setup and tell the firmware the 3790 * driver is down so we can try to get access the 3791 * probe if ASF is running. Retry a couple of times 3792 * if we get a conflict with the ASF firmware accessing 3793 * the PHY. 3794 */ 3795 trys = 0; 3796 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3797 again: 3798 bge_asf_driver_up(sc); 3799 3800 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3801 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3802 MIIF_DOPAUSE); 3803 if (error != 0) { 3804 if (trys++ < 4) { 3805 device_printf(sc->bge_dev, "Try again\n"); 3806 bge_miibus_writereg(sc->bge_dev, 3807 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3808 goto again; 3809 } 3810 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3811 goto fail; 3812 } 3813 3814 /* 3815 * Now tell the firmware we are going up after probing the PHY 3816 */ 3817 if (sc->bge_asf_mode & ASF_STACKUP) 3818 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3819 } 3820 3821 /* 3822 * When using the BCM5701 in PCI-X mode, data corruption has 3823 * been observed in the first few bytes of some received packets. 3824 * Aligning the packet buffer in memory eliminates the corruption. 3825 * Unfortunately, this misaligns the packet payloads. On platforms 3826 * which do not support unaligned accesses, we will realign the 3827 * payloads by copying the received packets. 3828 */ 3829 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3830 sc->bge_flags & BGE_FLAG_PCIX) 3831 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3832 3833 /* 3834 * Call MI attach routine. 3835 */ 3836 ether_ifattach(ifp, eaddr); 3837 3838 /* Tell upper layer we support long frames. */ 3839 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3840 3841 /* 3842 * Hookup IRQ last. 3843 */ 3844 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3845 /* Take advantage of single-shot MSI. */ 3846 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3847 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3848 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3849 taskqueue_thread_enqueue, &sc->bge_tq); 3850 if (sc->bge_tq == NULL) { 3851 device_printf(dev, "could not create taskqueue.\n"); 3852 ether_ifdetach(ifp); 3853 error = ENOMEM; 3854 goto fail; 3855 } 3856 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3857 device_get_nameunit(sc->bge_dev)); 3858 error = bus_setup_intr(dev, sc->bge_irq, 3859 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3860 &sc->bge_intrhand); 3861 } else 3862 error = bus_setup_intr(dev, sc->bge_irq, 3863 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3864 &sc->bge_intrhand); 3865 3866 if (error) { 3867 ether_ifdetach(ifp); 3868 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3869 } 3870 3871 fail: 3872 if (error) 3873 bge_detach(dev); 3874 return (error); 3875 } 3876 3877 static int 3878 bge_detach(device_t dev) 3879 { 3880 struct bge_softc *sc; 3881 struct ifnet *ifp; 3882 3883 sc = device_get_softc(dev); 3884 ifp = sc->bge_ifp; 3885 3886 #ifdef DEVICE_POLLING 3887 if (ifp->if_capenable & IFCAP_POLLING) 3888 ether_poll_deregister(ifp); 3889 #endif 3890 3891 if (device_is_attached(dev)) { 3892 ether_ifdetach(ifp); 3893 BGE_LOCK(sc); 3894 bge_stop(sc); 3895 BGE_UNLOCK(sc); 3896 callout_drain(&sc->bge_stat_ch); 3897 } 3898 3899 if (sc->bge_tq) 3900 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3901 3902 if (sc->bge_flags & BGE_FLAG_TBI) { 3903 ifmedia_removeall(&sc->bge_ifmedia); 3904 } else { 3905 bus_generic_detach(dev); 3906 device_delete_child(dev, sc->bge_miibus); 3907 } 3908 3909 bge_release_resources(sc); 3910 3911 return (0); 3912 } 3913 3914 static void 3915 bge_release_resources(struct bge_softc *sc) 3916 { 3917 device_t dev; 3918 3919 dev = sc->bge_dev; 3920 3921 if (sc->bge_tq != NULL) 3922 taskqueue_free(sc->bge_tq); 3923 3924 if (sc->bge_intrhand != NULL) 3925 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3926 3927 if (sc->bge_irq != NULL) 3928 bus_release_resource(dev, SYS_RES_IRQ, 3929 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3930 3931 if (sc->bge_flags & BGE_FLAG_MSI) 3932 pci_release_msi(dev); 3933 3934 if (sc->bge_res != NULL) 3935 bus_release_resource(dev, SYS_RES_MEMORY, 3936 PCIR_BAR(0), sc->bge_res); 3937 3938 if (sc->bge_res2 != NULL) 3939 bus_release_resource(dev, SYS_RES_MEMORY, 3940 PCIR_BAR(2), sc->bge_res2); 3941 3942 if (sc->bge_ifp != NULL) 3943 if_free(sc->bge_ifp); 3944 3945 bge_dma_free(sc); 3946 3947 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3948 BGE_LOCK_DESTROY(sc); 3949 } 3950 3951 static int 3952 bge_reset(struct bge_softc *sc) 3953 { 3954 device_t dev; 3955 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 3956 void (*write_op)(struct bge_softc *, int, int); 3957 uint16_t devctl; 3958 int i; 3959 3960 dev = sc->bge_dev; 3961 3962 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3963 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3964 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3965 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3966 3967 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3968 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3969 if (sc->bge_flags & BGE_FLAG_PCIE) 3970 write_op = bge_writemem_direct; 3971 else 3972 write_op = bge_writemem_ind; 3973 } else 3974 write_op = bge_writereg_ind; 3975 3976 /* Take APE lock when performing reset. */ 3977 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3978 3979 /* Save some important PCI state. */ 3980 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3981 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3982 3983 pci_write_config(dev, BGE_PCI_MISC_CTL, 3984 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3985 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3986 3987 /* Disable fastboot on controllers that support it. */ 3988 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3989 BGE_IS_5755_PLUS(sc)) { 3990 if (bootverbose) 3991 device_printf(dev, "Disabling fastboot\n"); 3992 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3993 } 3994 3995 /* 3996 * Write the magic number to SRAM at offset 0xB50. 3997 * When firmware finishes its initialization it will 3998 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3999 */ 4000 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4001 4002 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4003 4004 /* XXX: Broadcom Linux driver. */ 4005 if (sc->bge_flags & BGE_FLAG_PCIE) { 4006 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4007 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4008 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4009 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4010 } 4011 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4012 /* Prevent PCIE link training during global reset */ 4013 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4014 reset |= 1 << 29; 4015 } 4016 } 4017 4018 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4019 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4020 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4021 val | BGE_VCPU_STATUS_DRV_RESET); 4022 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4023 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4024 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4025 } 4026 4027 /* 4028 * Set GPHY Power Down Override to leave GPHY 4029 * powered up in D0 uninitialized. 4030 */ 4031 if (BGE_IS_5705_PLUS(sc) && 4032 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4033 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4034 4035 /* Issue global reset */ 4036 write_op(sc, BGE_MISC_CFG, reset); 4037 4038 if (sc->bge_flags & BGE_FLAG_PCIE) 4039 DELAY(100 * 1000); 4040 else 4041 DELAY(1000); 4042 4043 /* XXX: Broadcom Linux driver. */ 4044 if (sc->bge_flags & BGE_FLAG_PCIE) { 4045 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4046 DELAY(500000); /* wait for link training to complete */ 4047 val = pci_read_config(dev, 0xC4, 4); 4048 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4049 } 4050 devctl = pci_read_config(dev, 4051 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4052 /* Clear enable no snoop and disable relaxed ordering. */ 4053 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4054 PCIEM_CTL_NOSNOOP_ENABLE); 4055 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4056 devctl, 2); 4057 pci_set_max_read_req(dev, sc->bge_expmrq); 4058 /* Clear error status. */ 4059 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4060 PCIEM_STA_CORRECTABLE_ERROR | 4061 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4062 PCIEM_STA_UNSUPPORTED_REQ, 2); 4063 } 4064 4065 /* Reset some of the PCI state that got zapped by reset. */ 4066 pci_write_config(dev, BGE_PCI_MISC_CTL, 4067 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4068 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4069 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4070 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4071 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4072 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4074 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4075 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4076 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4077 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4078 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4079 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4080 /* 4081 * Disable PCI-X relaxed ordering to ensure status block update 4082 * comes first then packet buffer DMA. Otherwise driver may 4083 * read stale status block. 4084 */ 4085 if (sc->bge_flags & BGE_FLAG_PCIX) { 4086 devctl = pci_read_config(dev, 4087 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4088 devctl &= ~PCIXM_COMMAND_ERO; 4089 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4090 devctl &= ~PCIXM_COMMAND_MAX_READ; 4091 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4092 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4093 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4094 PCIXM_COMMAND_MAX_READ); 4095 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4096 } 4097 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4098 devctl, 2); 4099 } 4100 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4101 if (BGE_IS_5714_FAMILY(sc)) { 4102 /* This chip disables MSI on reset. */ 4103 if (sc->bge_flags & BGE_FLAG_MSI) { 4104 val = pci_read_config(dev, 4105 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4106 pci_write_config(dev, 4107 sc->bge_msicap + PCIR_MSI_CTRL, 4108 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4109 val = CSR_READ_4(sc, BGE_MSI_MODE); 4110 CSR_WRITE_4(sc, BGE_MSI_MODE, 4111 val | BGE_MSIMODE_ENABLE); 4112 } 4113 val = CSR_READ_4(sc, BGE_MARB_MODE); 4114 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4115 } else 4116 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4117 4118 /* Fix up byte swapping. */ 4119 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4120 4121 val = CSR_READ_4(sc, BGE_MAC_MODE); 4122 val = (val & ~mac_mode_mask) | mac_mode; 4123 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4124 DELAY(40); 4125 4126 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4127 4128 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4129 for (i = 0; i < BGE_TIMEOUT; i++) { 4130 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4131 if (val & BGE_VCPU_STATUS_INIT_DONE) 4132 break; 4133 DELAY(100); 4134 } 4135 if (i == BGE_TIMEOUT) { 4136 device_printf(dev, "reset timed out\n"); 4137 return (1); 4138 } 4139 } else { 4140 /* 4141 * Poll until we see the 1's complement of the magic number. 4142 * This indicates that the firmware initialization is complete. 4143 * We expect this to fail if no chip containing the Ethernet 4144 * address is fitted though. 4145 */ 4146 for (i = 0; i < BGE_TIMEOUT; i++) { 4147 DELAY(10); 4148 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4149 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4150 break; 4151 } 4152 4153 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4154 device_printf(dev, 4155 "firmware handshake timed out, found 0x%08x\n", 4156 val); 4157 /* BCM57765 A0 needs additional time before accessing. */ 4158 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4159 DELAY(10 * 1000); /* XXX */ 4160 } 4161 4162 /* 4163 * The 5704 in TBI mode apparently needs some special 4164 * adjustment to insure the SERDES drive level is set 4165 * to 1.2V. 4166 */ 4167 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4168 sc->bge_flags & BGE_FLAG_TBI) { 4169 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4170 val = (val & ~0xFFF) | 0x880; 4171 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4172 } 4173 4174 /* XXX: Broadcom Linux driver. */ 4175 if (sc->bge_flags & BGE_FLAG_PCIE && 4176 !BGE_IS_5717_PLUS(sc) && 4177 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4178 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4179 /* Enable Data FIFO protection. */ 4180 val = CSR_READ_4(sc, 0x7C00); 4181 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4182 } 4183 4184 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4185 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4186 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4187 4188 return (0); 4189 } 4190 4191 static __inline void 4192 bge_rxreuse_std(struct bge_softc *sc, int i) 4193 { 4194 struct bge_rx_bd *r; 4195 4196 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4197 r->bge_flags = BGE_RXBDFLAG_END; 4198 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4199 r->bge_idx = i; 4200 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4201 } 4202 4203 static __inline void 4204 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4205 { 4206 struct bge_extrx_bd *r; 4207 4208 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4209 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4210 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4211 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4212 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4213 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4214 r->bge_idx = i; 4215 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4216 } 4217 4218 /* 4219 * Frame reception handling. This is called if there's a frame 4220 * on the receive return list. 4221 * 4222 * Note: we have to be able to handle two possibilities here: 4223 * 1) the frame is from the jumbo receive ring 4224 * 2) the frame is from the standard receive ring 4225 */ 4226 4227 static int 4228 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4229 { 4230 struct ifnet *ifp; 4231 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4232 uint16_t rx_cons; 4233 4234 rx_cons = sc->bge_rx_saved_considx; 4235 4236 /* Nothing to do. */ 4237 if (rx_cons == rx_prod) 4238 return (rx_npkts); 4239 4240 ifp = sc->bge_ifp; 4241 4242 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4243 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4244 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4245 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4246 if (BGE_IS_JUMBO_CAPABLE(sc) && 4247 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4248 (MCLBYTES - ETHER_ALIGN)) 4249 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4250 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4251 4252 while (rx_cons != rx_prod) { 4253 struct bge_rx_bd *cur_rx; 4254 uint32_t rxidx; 4255 struct mbuf *m = NULL; 4256 uint16_t vlan_tag = 0; 4257 int have_tag = 0; 4258 4259 #ifdef DEVICE_POLLING 4260 if (ifp->if_capenable & IFCAP_POLLING) { 4261 if (sc->rxcycles <= 0) 4262 break; 4263 sc->rxcycles--; 4264 } 4265 #endif 4266 4267 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4268 4269 rxidx = cur_rx->bge_idx; 4270 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4271 4272 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4273 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4274 have_tag = 1; 4275 vlan_tag = cur_rx->bge_vlan_tag; 4276 } 4277 4278 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4279 jumbocnt++; 4280 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4281 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4282 bge_rxreuse_jumbo(sc, rxidx); 4283 continue; 4284 } 4285 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4286 bge_rxreuse_jumbo(sc, rxidx); 4287 ifp->if_iqdrops++; 4288 continue; 4289 } 4290 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4291 } else { 4292 stdcnt++; 4293 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4294 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4295 bge_rxreuse_std(sc, rxidx); 4296 continue; 4297 } 4298 if (bge_newbuf_std(sc, rxidx) != 0) { 4299 bge_rxreuse_std(sc, rxidx); 4300 ifp->if_iqdrops++; 4301 continue; 4302 } 4303 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4304 } 4305 4306 ifp->if_ipackets++; 4307 #ifndef __NO_STRICT_ALIGNMENT 4308 /* 4309 * For architectures with strict alignment we must make sure 4310 * the payload is aligned. 4311 */ 4312 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4313 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4314 cur_rx->bge_len); 4315 m->m_data += ETHER_ALIGN; 4316 } 4317 #endif 4318 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4319 m->m_pkthdr.rcvif = ifp; 4320 4321 if (ifp->if_capenable & IFCAP_RXCSUM) 4322 bge_rxcsum(sc, cur_rx, m); 4323 4324 /* 4325 * If we received a packet with a vlan tag, 4326 * attach that information to the packet. 4327 */ 4328 if (have_tag) { 4329 m->m_pkthdr.ether_vtag = vlan_tag; 4330 m->m_flags |= M_VLANTAG; 4331 } 4332 4333 if (holdlck != 0) { 4334 BGE_UNLOCK(sc); 4335 (*ifp->if_input)(ifp, m); 4336 BGE_LOCK(sc); 4337 } else 4338 (*ifp->if_input)(ifp, m); 4339 rx_npkts++; 4340 4341 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4342 return (rx_npkts); 4343 } 4344 4345 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4346 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4347 if (stdcnt > 0) 4348 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4349 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4350 4351 if (jumbocnt > 0) 4352 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4353 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4354 4355 sc->bge_rx_saved_considx = rx_cons; 4356 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4357 if (stdcnt) 4358 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4359 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4360 if (jumbocnt) 4361 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4362 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4363 #ifdef notyet 4364 /* 4365 * This register wraps very quickly under heavy packet drops. 4366 * If you need correct statistics, you can enable this check. 4367 */ 4368 if (BGE_IS_5705_PLUS(sc)) 4369 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4370 #endif 4371 return (rx_npkts); 4372 } 4373 4374 static void 4375 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4376 { 4377 4378 if (BGE_IS_5717_PLUS(sc)) { 4379 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4380 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4381 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4382 if ((cur_rx->bge_error_flag & 4383 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4384 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4385 } 4386 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4387 m->m_pkthdr.csum_data = 4388 cur_rx->bge_tcp_udp_csum; 4389 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4390 CSUM_PSEUDO_HDR; 4391 } 4392 } 4393 } else { 4394 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4395 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4396 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4397 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4398 } 4399 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4400 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4401 m->m_pkthdr.csum_data = 4402 cur_rx->bge_tcp_udp_csum; 4403 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4404 CSUM_PSEUDO_HDR; 4405 } 4406 } 4407 } 4408 4409 static void 4410 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4411 { 4412 struct bge_tx_bd *cur_tx; 4413 struct ifnet *ifp; 4414 4415 BGE_LOCK_ASSERT(sc); 4416 4417 /* Nothing to do. */ 4418 if (sc->bge_tx_saved_considx == tx_cons) 4419 return; 4420 4421 ifp = sc->bge_ifp; 4422 4423 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4424 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4425 /* 4426 * Go through our tx ring and free mbufs for those 4427 * frames that have been sent. 4428 */ 4429 while (sc->bge_tx_saved_considx != tx_cons) { 4430 uint32_t idx; 4431 4432 idx = sc->bge_tx_saved_considx; 4433 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4434 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4435 ifp->if_opackets++; 4436 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4437 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4438 sc->bge_cdata.bge_tx_dmamap[idx], 4439 BUS_DMASYNC_POSTWRITE); 4440 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4441 sc->bge_cdata.bge_tx_dmamap[idx]); 4442 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4443 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4444 } 4445 sc->bge_txcnt--; 4446 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4447 } 4448 4449 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4450 if (sc->bge_txcnt == 0) 4451 sc->bge_timer = 0; 4452 } 4453 4454 #ifdef DEVICE_POLLING 4455 static int 4456 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4457 { 4458 struct bge_softc *sc = ifp->if_softc; 4459 uint16_t rx_prod, tx_cons; 4460 uint32_t statusword; 4461 int rx_npkts = 0; 4462 4463 BGE_LOCK(sc); 4464 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4465 BGE_UNLOCK(sc); 4466 return (rx_npkts); 4467 } 4468 4469 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4470 sc->bge_cdata.bge_status_map, 4471 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4472 /* Fetch updates from the status block. */ 4473 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4474 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4475 4476 statusword = sc->bge_ldata.bge_status_block->bge_status; 4477 /* Clear the status so the next pass only sees the changes. */ 4478 sc->bge_ldata.bge_status_block->bge_status = 0; 4479 4480 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4481 sc->bge_cdata.bge_status_map, 4482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4483 4484 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4485 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4486 sc->bge_link_evt++; 4487 4488 if (cmd == POLL_AND_CHECK_STATUS) 4489 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4490 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4491 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4492 bge_link_upd(sc); 4493 4494 sc->rxcycles = count; 4495 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4496 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4497 BGE_UNLOCK(sc); 4498 return (rx_npkts); 4499 } 4500 bge_txeof(sc, tx_cons); 4501 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4502 bge_start_locked(ifp); 4503 4504 BGE_UNLOCK(sc); 4505 return (rx_npkts); 4506 } 4507 #endif /* DEVICE_POLLING */ 4508 4509 static int 4510 bge_msi_intr(void *arg) 4511 { 4512 struct bge_softc *sc; 4513 4514 sc = (struct bge_softc *)arg; 4515 /* 4516 * This interrupt is not shared and controller already 4517 * disabled further interrupt. 4518 */ 4519 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4520 return (FILTER_HANDLED); 4521 } 4522 4523 static void 4524 bge_intr_task(void *arg, int pending) 4525 { 4526 struct bge_softc *sc; 4527 struct ifnet *ifp; 4528 uint32_t status, status_tag; 4529 uint16_t rx_prod, tx_cons; 4530 4531 sc = (struct bge_softc *)arg; 4532 ifp = sc->bge_ifp; 4533 4534 BGE_LOCK(sc); 4535 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4536 BGE_UNLOCK(sc); 4537 return; 4538 } 4539 4540 /* Get updated status block. */ 4541 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4542 sc->bge_cdata.bge_status_map, 4543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4544 4545 /* Save producer/consumer indices. */ 4546 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4547 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4548 status = sc->bge_ldata.bge_status_block->bge_status; 4549 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4550 /* Dirty the status flag. */ 4551 sc->bge_ldata.bge_status_block->bge_status = 0; 4552 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4553 sc->bge_cdata.bge_status_map, 4554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4555 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4556 status_tag = 0; 4557 4558 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4559 bge_link_upd(sc); 4560 4561 /* Let controller work. */ 4562 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4563 4564 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4565 sc->bge_rx_saved_considx != rx_prod) { 4566 /* Check RX return ring producer/consumer. */ 4567 BGE_UNLOCK(sc); 4568 bge_rxeof(sc, rx_prod, 0); 4569 BGE_LOCK(sc); 4570 } 4571 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4572 /* Check TX ring producer/consumer. */ 4573 bge_txeof(sc, tx_cons); 4574 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4575 bge_start_locked(ifp); 4576 } 4577 BGE_UNLOCK(sc); 4578 } 4579 4580 static void 4581 bge_intr(void *xsc) 4582 { 4583 struct bge_softc *sc; 4584 struct ifnet *ifp; 4585 uint32_t statusword; 4586 uint16_t rx_prod, tx_cons; 4587 4588 sc = xsc; 4589 4590 BGE_LOCK(sc); 4591 4592 ifp = sc->bge_ifp; 4593 4594 #ifdef DEVICE_POLLING 4595 if (ifp->if_capenable & IFCAP_POLLING) { 4596 BGE_UNLOCK(sc); 4597 return; 4598 } 4599 #endif 4600 4601 /* 4602 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4603 * disable interrupts by writing nonzero like we used to, since with 4604 * our current organization this just gives complications and 4605 * pessimizations for re-enabling interrupts. We used to have races 4606 * instead of the necessary complications. Disabling interrupts 4607 * would just reduce the chance of a status update while we are 4608 * running (by switching to the interrupt-mode coalescence 4609 * parameters), but this chance is already very low so it is more 4610 * efficient to get another interrupt than prevent it. 4611 * 4612 * We do the ack first to ensure another interrupt if there is a 4613 * status update after the ack. We don't check for the status 4614 * changing later because it is more efficient to get another 4615 * interrupt than prevent it, not quite as above (not checking is 4616 * a smaller optimization than not toggling the interrupt enable, 4617 * since checking doesn't involve PCI accesses and toggling require 4618 * the status check). So toggling would probably be a pessimization 4619 * even with MSI. It would only be needed for using a task queue. 4620 */ 4621 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4622 4623 /* 4624 * Do the mandatory PCI flush as well as get the link status. 4625 */ 4626 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4627 4628 /* Make sure the descriptor ring indexes are coherent. */ 4629 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4630 sc->bge_cdata.bge_status_map, 4631 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4632 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4633 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4634 sc->bge_ldata.bge_status_block->bge_status = 0; 4635 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4636 sc->bge_cdata.bge_status_map, 4637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4638 4639 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4640 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4641 statusword || sc->bge_link_evt) 4642 bge_link_upd(sc); 4643 4644 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4645 /* Check RX return ring producer/consumer. */ 4646 bge_rxeof(sc, rx_prod, 1); 4647 } 4648 4649 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4650 /* Check TX ring producer/consumer. */ 4651 bge_txeof(sc, tx_cons); 4652 } 4653 4654 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4655 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4656 bge_start_locked(ifp); 4657 4658 BGE_UNLOCK(sc); 4659 } 4660 4661 static void 4662 bge_asf_driver_up(struct bge_softc *sc) 4663 { 4664 if (sc->bge_asf_mode & ASF_STACKUP) { 4665 /* Send ASF heartbeat aprox. every 2s */ 4666 if (sc->bge_asf_count) 4667 sc->bge_asf_count --; 4668 else { 4669 sc->bge_asf_count = 2; 4670 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4671 BGE_FW_CMD_DRV_ALIVE); 4672 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4673 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4674 BGE_FW_HB_TIMEOUT_SEC); 4675 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4676 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4677 BGE_RX_CPU_DRV_EVENT); 4678 } 4679 } 4680 } 4681 4682 static void 4683 bge_tick(void *xsc) 4684 { 4685 struct bge_softc *sc = xsc; 4686 struct mii_data *mii = NULL; 4687 4688 BGE_LOCK_ASSERT(sc); 4689 4690 /* Synchronize with possible callout reset/stop. */ 4691 if (callout_pending(&sc->bge_stat_ch) || 4692 !callout_active(&sc->bge_stat_ch)) 4693 return; 4694 4695 if (BGE_IS_5705_PLUS(sc)) 4696 bge_stats_update_regs(sc); 4697 else 4698 bge_stats_update(sc); 4699 4700 /* XXX Add APE heartbeat check here? */ 4701 4702 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4703 mii = device_get_softc(sc->bge_miibus); 4704 /* 4705 * Do not touch PHY if we have link up. This could break 4706 * IPMI/ASF mode or produce extra input errors 4707 * (extra errors was reported for bcm5701 & bcm5704). 4708 */ 4709 if (!sc->bge_link) 4710 mii_tick(mii); 4711 } else { 4712 /* 4713 * Since in TBI mode auto-polling can't be used we should poll 4714 * link status manually. Here we register pending link event 4715 * and trigger interrupt. 4716 */ 4717 #ifdef DEVICE_POLLING 4718 /* In polling mode we poll link state in bge_poll(). */ 4719 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4720 #endif 4721 { 4722 sc->bge_link_evt++; 4723 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4724 sc->bge_flags & BGE_FLAG_5788) 4725 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4726 else 4727 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4728 } 4729 } 4730 4731 bge_asf_driver_up(sc); 4732 bge_watchdog(sc); 4733 4734 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4735 } 4736 4737 static void 4738 bge_stats_update_regs(struct bge_softc *sc) 4739 { 4740 struct ifnet *ifp; 4741 struct bge_mac_stats *stats; 4742 4743 ifp = sc->bge_ifp; 4744 stats = &sc->bge_mac_stats; 4745 4746 stats->ifHCOutOctets += 4747 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4748 stats->etherStatsCollisions += 4749 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4750 stats->outXonSent += 4751 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4752 stats->outXoffSent += 4753 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4754 stats->dot3StatsInternalMacTransmitErrors += 4755 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4756 stats->dot3StatsSingleCollisionFrames += 4757 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4758 stats->dot3StatsMultipleCollisionFrames += 4759 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4760 stats->dot3StatsDeferredTransmissions += 4761 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4762 stats->dot3StatsExcessiveCollisions += 4763 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4764 stats->dot3StatsLateCollisions += 4765 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4766 stats->ifHCOutUcastPkts += 4767 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4768 stats->ifHCOutMulticastPkts += 4769 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4770 stats->ifHCOutBroadcastPkts += 4771 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4772 4773 stats->ifHCInOctets += 4774 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4775 stats->etherStatsFragments += 4776 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4777 stats->ifHCInUcastPkts += 4778 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4779 stats->ifHCInMulticastPkts += 4780 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4781 stats->ifHCInBroadcastPkts += 4782 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4783 stats->dot3StatsFCSErrors += 4784 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4785 stats->dot3StatsAlignmentErrors += 4786 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4787 stats->xonPauseFramesReceived += 4788 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4789 stats->xoffPauseFramesReceived += 4790 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4791 stats->macControlFramesReceived += 4792 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4793 stats->xoffStateEntered += 4794 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4795 stats->dot3StatsFramesTooLong += 4796 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4797 stats->etherStatsJabbers += 4798 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4799 stats->etherStatsUndersizePkts += 4800 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4801 4802 stats->FramesDroppedDueToFilters += 4803 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4804 stats->DmaWriteQueueFull += 4805 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4806 stats->DmaWriteHighPriQueueFull += 4807 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4808 stats->NoMoreRxBDs += 4809 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4810 /* 4811 * XXX 4812 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4813 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4814 * includes number of unwanted multicast frames. This comes 4815 * from silicon bug and known workaround to get rough(not 4816 * exact) counter is to enable interrupt on MBUF low water 4817 * attention. This can be accomplished by setting 4818 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4819 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4820 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4821 * However that change would generate more interrupts and 4822 * there are still possibilities of losing multiple frames 4823 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4824 * Given that the workaround still would not get correct 4825 * counter I don't think it's worth to implement it. So 4826 * ignore reading the counter on controllers that have the 4827 * silicon bug. 4828 */ 4829 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4830 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4831 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4832 stats->InputDiscards += 4833 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4834 stats->InputErrors += 4835 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4836 stats->RecvThresholdHit += 4837 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4838 4839 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4840 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4841 stats->InputErrors); 4842 } 4843 4844 static void 4845 bge_stats_clear_regs(struct bge_softc *sc) 4846 { 4847 4848 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4849 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4850 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4851 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4852 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4853 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4854 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4855 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4856 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4857 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4858 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4859 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4860 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4861 4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4876 4877 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4882 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4884 } 4885 4886 static void 4887 bge_stats_update(struct bge_softc *sc) 4888 { 4889 struct ifnet *ifp; 4890 bus_size_t stats; 4891 uint32_t cnt; /* current register value */ 4892 4893 ifp = sc->bge_ifp; 4894 4895 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4896 4897 #define READ_STAT(sc, stats, stat) \ 4898 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4899 4900 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4901 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4902 sc->bge_tx_collisions = cnt; 4903 4904 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4905 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4906 sc->bge_rx_nobds = cnt; 4907 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4908 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 4909 sc->bge_rx_inerrs = cnt; 4910 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4911 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4912 sc->bge_rx_discards = cnt; 4913 4914 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4915 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4916 sc->bge_tx_discards = cnt; 4917 4918 #undef READ_STAT 4919 } 4920 4921 /* 4922 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4923 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4924 * but when such padded frames employ the bge IP/TCP checksum offload, 4925 * the hardware checksum assist gives incorrect results (possibly 4926 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4927 * If we pad such runts with zeros, the onboard checksum comes out correct. 4928 */ 4929 static __inline int 4930 bge_cksum_pad(struct mbuf *m) 4931 { 4932 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4933 struct mbuf *last; 4934 4935 /* If there's only the packet-header and we can pad there, use it. */ 4936 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4937 M_TRAILINGSPACE(m) >= padlen) { 4938 last = m; 4939 } else { 4940 /* 4941 * Walk packet chain to find last mbuf. We will either 4942 * pad there, or append a new mbuf and pad it. 4943 */ 4944 for (last = m; last->m_next != NULL; last = last->m_next); 4945 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4946 /* Allocate new empty mbuf, pad it. Compact later. */ 4947 struct mbuf *n; 4948 4949 MGET(n, M_NOWAIT, MT_DATA); 4950 if (n == NULL) 4951 return (ENOBUFS); 4952 n->m_len = 0; 4953 last->m_next = n; 4954 last = n; 4955 } 4956 } 4957 4958 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4959 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4960 last->m_len += padlen; 4961 m->m_pkthdr.len += padlen; 4962 4963 return (0); 4964 } 4965 4966 static struct mbuf * 4967 bge_check_short_dma(struct mbuf *m) 4968 { 4969 struct mbuf *n; 4970 int found; 4971 4972 /* 4973 * If device receive two back-to-back send BDs with less than 4974 * or equal to 8 total bytes then the device may hang. The two 4975 * back-to-back send BDs must in the same frame for this failure 4976 * to occur. Scan mbuf chains and see whether two back-to-back 4977 * send BDs are there. If this is the case, allocate new mbuf 4978 * and copy the frame to workaround the silicon bug. 4979 */ 4980 for (n = m, found = 0; n != NULL; n = n->m_next) { 4981 if (n->m_len < 8) { 4982 found++; 4983 if (found > 1) 4984 break; 4985 continue; 4986 } 4987 found = 0; 4988 } 4989 4990 if (found > 1) { 4991 n = m_defrag(m, M_NOWAIT); 4992 if (n == NULL) 4993 m_freem(m); 4994 } else 4995 n = m; 4996 return (n); 4997 } 4998 4999 static struct mbuf * 5000 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5001 uint16_t *flags) 5002 { 5003 struct ip *ip; 5004 struct tcphdr *tcp; 5005 struct mbuf *n; 5006 uint16_t hlen; 5007 uint32_t poff; 5008 5009 if (M_WRITABLE(m) == 0) { 5010 /* Get a writable copy. */ 5011 n = m_dup(m, M_NOWAIT); 5012 m_freem(m); 5013 if (n == NULL) 5014 return (NULL); 5015 m = n; 5016 } 5017 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5018 if (m == NULL) 5019 return (NULL); 5020 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5021 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5022 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5023 if (m == NULL) 5024 return (NULL); 5025 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5026 m = m_pullup(m, poff + (tcp->th_off << 2)); 5027 if (m == NULL) 5028 return (NULL); 5029 /* 5030 * It seems controller doesn't modify IP length and TCP pseudo 5031 * checksum. These checksum computed by upper stack should be 0. 5032 */ 5033 *mss = m->m_pkthdr.tso_segsz; 5034 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5035 ip->ip_sum = 0; 5036 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5037 /* Clear pseudo checksum computed by TCP stack. */ 5038 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5039 tcp->th_sum = 0; 5040 /* 5041 * Broadcom controllers uses different descriptor format for 5042 * TSO depending on ASIC revision. Due to TSO-capable firmware 5043 * license issue and lower performance of firmware based TSO 5044 * we only support hardware based TSO. 5045 */ 5046 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5047 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5048 if (sc->bge_flags & BGE_FLAG_TSO3) { 5049 /* 5050 * For BCM5717 and newer controllers, hardware based TSO 5051 * uses the 14 lower bits of the bge_mss field to store the 5052 * MSS and the upper 2 bits to store the lowest 2 bits of 5053 * the IP/TCP header length. The upper 6 bits of the header 5054 * length are stored in the bge_flags[14:10,4] field. Jumbo 5055 * frames are supported. 5056 */ 5057 *mss |= ((hlen & 0x3) << 14); 5058 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5059 } else { 5060 /* 5061 * For BCM5755 and newer controllers, hardware based TSO uses 5062 * the lower 11 bits to store the MSS and the upper 5 bits to 5063 * store the IP/TCP header length. Jumbo frames are not 5064 * supported. 5065 */ 5066 *mss |= (hlen << 11); 5067 } 5068 return (m); 5069 } 5070 5071 /* 5072 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5073 * pointers to descriptors. 5074 */ 5075 static int 5076 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5077 { 5078 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5079 bus_dmamap_t map; 5080 struct bge_tx_bd *d; 5081 struct mbuf *m = *m_head; 5082 uint32_t idx = *txidx; 5083 uint16_t csum_flags, mss, vlan_tag; 5084 int nsegs, i, error; 5085 5086 csum_flags = 0; 5087 mss = 0; 5088 vlan_tag = 0; 5089 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5090 m->m_next != NULL) { 5091 *m_head = bge_check_short_dma(m); 5092 if (*m_head == NULL) 5093 return (ENOBUFS); 5094 m = *m_head; 5095 } 5096 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5097 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5098 if (*m_head == NULL) 5099 return (ENOBUFS); 5100 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5101 BGE_TXBDFLAG_CPU_POST_DMA; 5102 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5103 if (m->m_pkthdr.csum_flags & CSUM_IP) 5104 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5105 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5106 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5107 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5108 (error = bge_cksum_pad(m)) != 0) { 5109 m_freem(m); 5110 *m_head = NULL; 5111 return (error); 5112 } 5113 } 5114 } 5115 5116 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5117 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5118 m->m_pkthdr.len > ETHER_MAX_LEN) 5119 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5120 if (sc->bge_forced_collapse > 0 && 5121 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5122 /* 5123 * Forcedly collapse mbuf chains to overcome hardware 5124 * limitation which only support a single outstanding 5125 * DMA read operation. 5126 */ 5127 if (sc->bge_forced_collapse == 1) 5128 m = m_defrag(m, M_NOWAIT); 5129 else 5130 m = m_collapse(m, M_NOWAIT, 5131 sc->bge_forced_collapse); 5132 if (m == NULL) 5133 m = *m_head; 5134 *m_head = m; 5135 } 5136 } 5137 5138 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5139 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5140 &nsegs, BUS_DMA_NOWAIT); 5141 if (error == EFBIG) { 5142 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5143 if (m == NULL) { 5144 m_freem(*m_head); 5145 *m_head = NULL; 5146 return (ENOBUFS); 5147 } 5148 *m_head = m; 5149 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5150 m, segs, &nsegs, BUS_DMA_NOWAIT); 5151 if (error) { 5152 m_freem(m); 5153 *m_head = NULL; 5154 return (error); 5155 } 5156 } else if (error != 0) 5157 return (error); 5158 5159 /* Check if we have enough free send BDs. */ 5160 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5161 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5162 return (ENOBUFS); 5163 } 5164 5165 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5166 5167 if (m->m_flags & M_VLANTAG) { 5168 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5169 vlan_tag = m->m_pkthdr.ether_vtag; 5170 } 5171 for (i = 0; ; i++) { 5172 d = &sc->bge_ldata.bge_tx_ring[idx]; 5173 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5174 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5175 d->bge_len = segs[i].ds_len; 5176 d->bge_flags = csum_flags; 5177 d->bge_vlan_tag = vlan_tag; 5178 d->bge_mss = mss; 5179 if (i == nsegs - 1) 5180 break; 5181 BGE_INC(idx, BGE_TX_RING_CNT); 5182 } 5183 5184 /* Mark the last segment as end of packet... */ 5185 d->bge_flags |= BGE_TXBDFLAG_END; 5186 5187 /* 5188 * Insure that the map for this transmission 5189 * is placed at the array index of the last descriptor 5190 * in this chain. 5191 */ 5192 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5193 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5194 sc->bge_cdata.bge_tx_chain[idx] = m; 5195 sc->bge_txcnt += nsegs; 5196 5197 BGE_INC(idx, BGE_TX_RING_CNT); 5198 *txidx = idx; 5199 5200 return (0); 5201 } 5202 5203 /* 5204 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5205 * to the mbuf data regions directly in the transmit descriptors. 5206 */ 5207 static void 5208 bge_start_locked(struct ifnet *ifp) 5209 { 5210 struct bge_softc *sc; 5211 struct mbuf *m_head; 5212 uint32_t prodidx; 5213 int count; 5214 5215 sc = ifp->if_softc; 5216 BGE_LOCK_ASSERT(sc); 5217 5218 if (!sc->bge_link || 5219 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5220 IFF_DRV_RUNNING) 5221 return; 5222 5223 prodidx = sc->bge_tx_prodidx; 5224 5225 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5226 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5227 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5228 break; 5229 } 5230 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5231 if (m_head == NULL) 5232 break; 5233 5234 /* 5235 * Pack the data into the transmit ring. If we 5236 * don't have room, set the OACTIVE flag and wait 5237 * for the NIC to drain the ring. 5238 */ 5239 if (bge_encap(sc, &m_head, &prodidx)) { 5240 if (m_head == NULL) 5241 break; 5242 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5243 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5244 break; 5245 } 5246 ++count; 5247 5248 /* 5249 * If there's a BPF listener, bounce a copy of this frame 5250 * to him. 5251 */ 5252 #ifdef ETHER_BPF_MTAP 5253 ETHER_BPF_MTAP(ifp, m_head); 5254 #else 5255 BPF_MTAP(ifp, m_head); 5256 #endif 5257 } 5258 5259 if (count > 0) { 5260 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5261 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5262 /* Transmit. */ 5263 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5264 /* 5700 b2 errata */ 5265 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5266 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5267 5268 sc->bge_tx_prodidx = prodidx; 5269 5270 /* 5271 * Set a timeout in case the chip goes out to lunch. 5272 */ 5273 sc->bge_timer = 5; 5274 } 5275 } 5276 5277 /* 5278 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5279 * to the mbuf data regions directly in the transmit descriptors. 5280 */ 5281 static void 5282 bge_start(struct ifnet *ifp) 5283 { 5284 struct bge_softc *sc; 5285 5286 sc = ifp->if_softc; 5287 BGE_LOCK(sc); 5288 bge_start_locked(ifp); 5289 BGE_UNLOCK(sc); 5290 } 5291 5292 static void 5293 bge_init_locked(struct bge_softc *sc) 5294 { 5295 struct ifnet *ifp; 5296 uint16_t *m; 5297 uint32_t mode; 5298 5299 BGE_LOCK_ASSERT(sc); 5300 5301 ifp = sc->bge_ifp; 5302 5303 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5304 return; 5305 5306 /* Cancel pending I/O and flush buffers. */ 5307 bge_stop(sc); 5308 5309 bge_stop_fw(sc); 5310 bge_sig_pre_reset(sc, BGE_RESET_START); 5311 bge_reset(sc); 5312 bge_sig_legacy(sc, BGE_RESET_START); 5313 bge_sig_post_reset(sc, BGE_RESET_START); 5314 5315 bge_chipinit(sc); 5316 5317 /* 5318 * Init the various state machines, ring 5319 * control blocks and firmware. 5320 */ 5321 if (bge_blockinit(sc)) { 5322 device_printf(sc->bge_dev, "initialization failure\n"); 5323 return; 5324 } 5325 5326 ifp = sc->bge_ifp; 5327 5328 /* Specify MTU. */ 5329 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5330 ETHER_HDR_LEN + ETHER_CRC_LEN + 5331 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5332 5333 /* Load our MAC address. */ 5334 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5335 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5336 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5337 5338 /* Program promiscuous mode. */ 5339 bge_setpromisc(sc); 5340 5341 /* Program multicast filter. */ 5342 bge_setmulti(sc); 5343 5344 /* Program VLAN tag stripping. */ 5345 bge_setvlan(sc); 5346 5347 /* Override UDP checksum offloading. */ 5348 if (sc->bge_forced_udpcsum == 0) 5349 sc->bge_csum_features &= ~CSUM_UDP; 5350 else 5351 sc->bge_csum_features |= CSUM_UDP; 5352 if (ifp->if_capabilities & IFCAP_TXCSUM && 5353 ifp->if_capenable & IFCAP_TXCSUM) { 5354 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5355 ifp->if_hwassist |= sc->bge_csum_features; 5356 } 5357 5358 /* Init RX ring. */ 5359 if (bge_init_rx_ring_std(sc) != 0) { 5360 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5361 bge_stop(sc); 5362 return; 5363 } 5364 5365 /* 5366 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5367 * memory to insure that the chip has in fact read the first 5368 * entry of the ring. 5369 */ 5370 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5371 uint32_t v, i; 5372 for (i = 0; i < 10; i++) { 5373 DELAY(20); 5374 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5375 if (v == (MCLBYTES - ETHER_ALIGN)) 5376 break; 5377 } 5378 if (i == 10) 5379 device_printf (sc->bge_dev, 5380 "5705 A0 chip failed to load RX ring\n"); 5381 } 5382 5383 /* Init jumbo RX ring. */ 5384 if (BGE_IS_JUMBO_CAPABLE(sc) && 5385 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5386 (MCLBYTES - ETHER_ALIGN)) { 5387 if (bge_init_rx_ring_jumbo(sc) != 0) { 5388 device_printf(sc->bge_dev, 5389 "no memory for jumbo Rx buffers.\n"); 5390 bge_stop(sc); 5391 return; 5392 } 5393 } 5394 5395 /* Init our RX return ring index. */ 5396 sc->bge_rx_saved_considx = 0; 5397 5398 /* Init our RX/TX stat counters. */ 5399 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5400 5401 /* Init TX ring. */ 5402 bge_init_tx_ring(sc); 5403 5404 /* Enable TX MAC state machine lockup fix. */ 5405 mode = CSR_READ_4(sc, BGE_TX_MODE); 5406 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5407 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5408 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 5409 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5410 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5411 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5412 } 5413 /* Turn on transmitter. */ 5414 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5415 DELAY(100); 5416 5417 /* Turn on receiver. */ 5418 mode = CSR_READ_4(sc, BGE_RX_MODE); 5419 if (BGE_IS_5755_PLUS(sc)) 5420 mode |= BGE_RXMODE_IPV6_ENABLE; 5421 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5422 DELAY(10); 5423 5424 /* 5425 * Set the number of good frames to receive after RX MBUF 5426 * Low Watermark has been reached. After the RX MAC receives 5427 * this number of frames, it will drop subsequent incoming 5428 * frames until the MBUF High Watermark is reached. 5429 */ 5430 if (sc->bge_asicrev == BGE_ASICREV_BCM57765) 5431 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5432 else 5433 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5434 5435 /* Clear MAC statistics. */ 5436 if (BGE_IS_5705_PLUS(sc)) 5437 bge_stats_clear_regs(sc); 5438 5439 /* Tell firmware we're alive. */ 5440 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5441 5442 #ifdef DEVICE_POLLING 5443 /* Disable interrupts if we are polling. */ 5444 if (ifp->if_capenable & IFCAP_POLLING) { 5445 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5446 BGE_PCIMISCCTL_MASK_PCI_INTR); 5447 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5448 } else 5449 #endif 5450 5451 /* Enable host interrupts. */ 5452 { 5453 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5454 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5455 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5456 } 5457 5458 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5459 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5460 5461 bge_ifmedia_upd_locked(ifp); 5462 5463 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5464 } 5465 5466 static void 5467 bge_init(void *xsc) 5468 { 5469 struct bge_softc *sc = xsc; 5470 5471 BGE_LOCK(sc); 5472 bge_init_locked(sc); 5473 BGE_UNLOCK(sc); 5474 } 5475 5476 /* 5477 * Set media options. 5478 */ 5479 static int 5480 bge_ifmedia_upd(struct ifnet *ifp) 5481 { 5482 struct bge_softc *sc = ifp->if_softc; 5483 int res; 5484 5485 BGE_LOCK(sc); 5486 res = bge_ifmedia_upd_locked(ifp); 5487 BGE_UNLOCK(sc); 5488 5489 return (res); 5490 } 5491 5492 static int 5493 bge_ifmedia_upd_locked(struct ifnet *ifp) 5494 { 5495 struct bge_softc *sc = ifp->if_softc; 5496 struct mii_data *mii; 5497 struct mii_softc *miisc; 5498 struct ifmedia *ifm; 5499 5500 BGE_LOCK_ASSERT(sc); 5501 5502 ifm = &sc->bge_ifmedia; 5503 5504 /* If this is a 1000baseX NIC, enable the TBI port. */ 5505 if (sc->bge_flags & BGE_FLAG_TBI) { 5506 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5507 return (EINVAL); 5508 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5509 case IFM_AUTO: 5510 /* 5511 * The BCM5704 ASIC appears to have a special 5512 * mechanism for programming the autoneg 5513 * advertisement registers in TBI mode. 5514 */ 5515 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5516 uint32_t sgdig; 5517 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5518 if (sgdig & BGE_SGDIGSTS_DONE) { 5519 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5520 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5521 sgdig |= BGE_SGDIGCFG_AUTO | 5522 BGE_SGDIGCFG_PAUSE_CAP | 5523 BGE_SGDIGCFG_ASYM_PAUSE; 5524 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5525 sgdig | BGE_SGDIGCFG_SEND); 5526 DELAY(5); 5527 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5528 } 5529 } 5530 break; 5531 case IFM_1000_SX: 5532 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5533 BGE_CLRBIT(sc, BGE_MAC_MODE, 5534 BGE_MACMODE_HALF_DUPLEX); 5535 } else { 5536 BGE_SETBIT(sc, BGE_MAC_MODE, 5537 BGE_MACMODE_HALF_DUPLEX); 5538 } 5539 DELAY(40); 5540 break; 5541 default: 5542 return (EINVAL); 5543 } 5544 return (0); 5545 } 5546 5547 sc->bge_link_evt++; 5548 mii = device_get_softc(sc->bge_miibus); 5549 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5550 PHY_RESET(miisc); 5551 mii_mediachg(mii); 5552 5553 /* 5554 * Force an interrupt so that we will call bge_link_upd 5555 * if needed and clear any pending link state attention. 5556 * Without this we are not getting any further interrupts 5557 * for link state changes and thus will not UP the link and 5558 * not be able to send in bge_start_locked. The only 5559 * way to get things working was to receive a packet and 5560 * get an RX intr. 5561 * bge_tick should help for fiber cards and we might not 5562 * need to do this here if BGE_FLAG_TBI is set but as 5563 * we poll for fiber anyway it should not harm. 5564 */ 5565 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5566 sc->bge_flags & BGE_FLAG_5788) 5567 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5568 else 5569 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5570 5571 return (0); 5572 } 5573 5574 /* 5575 * Report current media status. 5576 */ 5577 static void 5578 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5579 { 5580 struct bge_softc *sc = ifp->if_softc; 5581 struct mii_data *mii; 5582 5583 BGE_LOCK(sc); 5584 5585 if (sc->bge_flags & BGE_FLAG_TBI) { 5586 ifmr->ifm_status = IFM_AVALID; 5587 ifmr->ifm_active = IFM_ETHER; 5588 if (CSR_READ_4(sc, BGE_MAC_STS) & 5589 BGE_MACSTAT_TBI_PCS_SYNCHED) 5590 ifmr->ifm_status |= IFM_ACTIVE; 5591 else { 5592 ifmr->ifm_active |= IFM_NONE; 5593 BGE_UNLOCK(sc); 5594 return; 5595 } 5596 ifmr->ifm_active |= IFM_1000_SX; 5597 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5598 ifmr->ifm_active |= IFM_HDX; 5599 else 5600 ifmr->ifm_active |= IFM_FDX; 5601 BGE_UNLOCK(sc); 5602 return; 5603 } 5604 5605 mii = device_get_softc(sc->bge_miibus); 5606 mii_pollstat(mii); 5607 ifmr->ifm_active = mii->mii_media_active; 5608 ifmr->ifm_status = mii->mii_media_status; 5609 5610 BGE_UNLOCK(sc); 5611 } 5612 5613 static int 5614 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5615 { 5616 struct bge_softc *sc = ifp->if_softc; 5617 struct ifreq *ifr = (struct ifreq *) data; 5618 struct mii_data *mii; 5619 int flags, mask, error = 0; 5620 5621 switch (command) { 5622 case SIOCSIFMTU: 5623 if (BGE_IS_JUMBO_CAPABLE(sc) || 5624 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5625 if (ifr->ifr_mtu < ETHERMIN || 5626 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5627 error = EINVAL; 5628 break; 5629 } 5630 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5631 error = EINVAL; 5632 break; 5633 } 5634 BGE_LOCK(sc); 5635 if (ifp->if_mtu != ifr->ifr_mtu) { 5636 ifp->if_mtu = ifr->ifr_mtu; 5637 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5638 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5639 bge_init_locked(sc); 5640 } 5641 } 5642 BGE_UNLOCK(sc); 5643 break; 5644 case SIOCSIFFLAGS: 5645 BGE_LOCK(sc); 5646 if (ifp->if_flags & IFF_UP) { 5647 /* 5648 * If only the state of the PROMISC flag changed, 5649 * then just use the 'set promisc mode' command 5650 * instead of reinitializing the entire NIC. Doing 5651 * a full re-init means reloading the firmware and 5652 * waiting for it to start up, which may take a 5653 * second or two. Similarly for ALLMULTI. 5654 */ 5655 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5656 flags = ifp->if_flags ^ sc->bge_if_flags; 5657 if (flags & IFF_PROMISC) 5658 bge_setpromisc(sc); 5659 if (flags & IFF_ALLMULTI) 5660 bge_setmulti(sc); 5661 } else 5662 bge_init_locked(sc); 5663 } else { 5664 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5665 bge_stop(sc); 5666 } 5667 } 5668 sc->bge_if_flags = ifp->if_flags; 5669 BGE_UNLOCK(sc); 5670 error = 0; 5671 break; 5672 case SIOCADDMULTI: 5673 case SIOCDELMULTI: 5674 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5675 BGE_LOCK(sc); 5676 bge_setmulti(sc); 5677 BGE_UNLOCK(sc); 5678 error = 0; 5679 } 5680 break; 5681 case SIOCSIFMEDIA: 5682 case SIOCGIFMEDIA: 5683 if (sc->bge_flags & BGE_FLAG_TBI) { 5684 error = ifmedia_ioctl(ifp, ifr, 5685 &sc->bge_ifmedia, command); 5686 } else { 5687 mii = device_get_softc(sc->bge_miibus); 5688 error = ifmedia_ioctl(ifp, ifr, 5689 &mii->mii_media, command); 5690 } 5691 break; 5692 case SIOCSIFCAP: 5693 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5694 #ifdef DEVICE_POLLING 5695 if (mask & IFCAP_POLLING) { 5696 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5697 error = ether_poll_register(bge_poll, ifp); 5698 if (error) 5699 return (error); 5700 BGE_LOCK(sc); 5701 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5702 BGE_PCIMISCCTL_MASK_PCI_INTR); 5703 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5704 ifp->if_capenable |= IFCAP_POLLING; 5705 BGE_UNLOCK(sc); 5706 } else { 5707 error = ether_poll_deregister(ifp); 5708 /* Enable interrupt even in error case */ 5709 BGE_LOCK(sc); 5710 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5711 BGE_PCIMISCCTL_MASK_PCI_INTR); 5712 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5713 ifp->if_capenable &= ~IFCAP_POLLING; 5714 BGE_UNLOCK(sc); 5715 } 5716 } 5717 #endif 5718 if ((mask & IFCAP_TXCSUM) != 0 && 5719 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5720 ifp->if_capenable ^= IFCAP_TXCSUM; 5721 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5722 ifp->if_hwassist |= sc->bge_csum_features; 5723 else 5724 ifp->if_hwassist &= ~sc->bge_csum_features; 5725 } 5726 5727 if ((mask & IFCAP_RXCSUM) != 0 && 5728 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5729 ifp->if_capenable ^= IFCAP_RXCSUM; 5730 5731 if ((mask & IFCAP_TSO4) != 0 && 5732 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5733 ifp->if_capenable ^= IFCAP_TSO4; 5734 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5735 ifp->if_hwassist |= CSUM_TSO; 5736 else 5737 ifp->if_hwassist &= ~CSUM_TSO; 5738 } 5739 5740 if (mask & IFCAP_VLAN_MTU) { 5741 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5742 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5743 bge_init(sc); 5744 } 5745 5746 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5747 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5748 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5749 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5750 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5751 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5752 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5753 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5754 BGE_LOCK(sc); 5755 bge_setvlan(sc); 5756 BGE_UNLOCK(sc); 5757 } 5758 #ifdef VLAN_CAPABILITIES 5759 VLAN_CAPABILITIES(ifp); 5760 #endif 5761 break; 5762 default: 5763 error = ether_ioctl(ifp, command, data); 5764 break; 5765 } 5766 5767 return (error); 5768 } 5769 5770 static void 5771 bge_watchdog(struct bge_softc *sc) 5772 { 5773 struct ifnet *ifp; 5774 5775 BGE_LOCK_ASSERT(sc); 5776 5777 if (sc->bge_timer == 0 || --sc->bge_timer) 5778 return; 5779 5780 ifp = sc->bge_ifp; 5781 5782 if_printf(ifp, "watchdog timeout -- resetting\n"); 5783 5784 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5785 bge_init_locked(sc); 5786 5787 ifp->if_oerrors++; 5788 } 5789 5790 static void 5791 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5792 { 5793 int i; 5794 5795 BGE_CLRBIT(sc, reg, bit); 5796 5797 for (i = 0; i < BGE_TIMEOUT; i++) { 5798 if ((CSR_READ_4(sc, reg) & bit) == 0) 5799 return; 5800 DELAY(100); 5801 } 5802 } 5803 5804 /* 5805 * Stop the adapter and free any mbufs allocated to the 5806 * RX and TX lists. 5807 */ 5808 static void 5809 bge_stop(struct bge_softc *sc) 5810 { 5811 struct ifnet *ifp; 5812 5813 BGE_LOCK_ASSERT(sc); 5814 5815 ifp = sc->bge_ifp; 5816 5817 callout_stop(&sc->bge_stat_ch); 5818 5819 /* Disable host interrupts. */ 5820 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5821 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5822 5823 /* 5824 * Tell firmware we're shutting down. 5825 */ 5826 bge_stop_fw(sc); 5827 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5828 5829 /* 5830 * Disable all of the receiver blocks. 5831 */ 5832 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5833 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5834 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5835 if (BGE_IS_5700_FAMILY(sc)) 5836 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5837 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5838 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5839 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5840 5841 /* 5842 * Disable all of the transmit blocks. 5843 */ 5844 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5845 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5846 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5847 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5848 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5849 if (BGE_IS_5700_FAMILY(sc)) 5850 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5851 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5852 5853 /* 5854 * Shut down all of the memory managers and related 5855 * state machines. 5856 */ 5857 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5858 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5859 if (BGE_IS_5700_FAMILY(sc)) 5860 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5861 5862 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5863 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5864 if (!(BGE_IS_5705_PLUS(sc))) { 5865 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5866 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5867 } 5868 /* Update MAC statistics. */ 5869 if (BGE_IS_5705_PLUS(sc)) 5870 bge_stats_update_regs(sc); 5871 5872 bge_reset(sc); 5873 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5874 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5875 5876 /* 5877 * Keep the ASF firmware running if up. 5878 */ 5879 if (sc->bge_asf_mode & ASF_STACKUP) 5880 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5881 else 5882 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5883 5884 /* Free the RX lists. */ 5885 bge_free_rx_ring_std(sc); 5886 5887 /* Free jumbo RX list. */ 5888 if (BGE_IS_JUMBO_CAPABLE(sc)) 5889 bge_free_rx_ring_jumbo(sc); 5890 5891 /* Free TX buffers. */ 5892 bge_free_tx_ring(sc); 5893 5894 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5895 5896 /* Clear MAC's link state (PHY may still have link UP). */ 5897 if (bootverbose && sc->bge_link) 5898 if_printf(sc->bge_ifp, "link DOWN\n"); 5899 sc->bge_link = 0; 5900 5901 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5902 } 5903 5904 /* 5905 * Stop all chip I/O so that the kernel's probe routines don't 5906 * get confused by errant DMAs when rebooting. 5907 */ 5908 static int 5909 bge_shutdown(device_t dev) 5910 { 5911 struct bge_softc *sc; 5912 5913 sc = device_get_softc(dev); 5914 BGE_LOCK(sc); 5915 bge_stop(sc); 5916 BGE_UNLOCK(sc); 5917 5918 return (0); 5919 } 5920 5921 static int 5922 bge_suspend(device_t dev) 5923 { 5924 struct bge_softc *sc; 5925 5926 sc = device_get_softc(dev); 5927 BGE_LOCK(sc); 5928 bge_stop(sc); 5929 BGE_UNLOCK(sc); 5930 5931 return (0); 5932 } 5933 5934 static int 5935 bge_resume(device_t dev) 5936 { 5937 struct bge_softc *sc; 5938 struct ifnet *ifp; 5939 5940 sc = device_get_softc(dev); 5941 BGE_LOCK(sc); 5942 ifp = sc->bge_ifp; 5943 if (ifp->if_flags & IFF_UP) { 5944 bge_init_locked(sc); 5945 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5946 bge_start_locked(ifp); 5947 } 5948 BGE_UNLOCK(sc); 5949 5950 return (0); 5951 } 5952 5953 static void 5954 bge_link_upd(struct bge_softc *sc) 5955 { 5956 struct mii_data *mii; 5957 uint32_t link, status; 5958 5959 BGE_LOCK_ASSERT(sc); 5960 5961 /* Clear 'pending link event' flag. */ 5962 sc->bge_link_evt = 0; 5963 5964 /* 5965 * Process link state changes. 5966 * Grrr. The link status word in the status block does 5967 * not work correctly on the BCM5700 rev AX and BX chips, 5968 * according to all available information. Hence, we have 5969 * to enable MII interrupts in order to properly obtain 5970 * async link changes. Unfortunately, this also means that 5971 * we have to read the MAC status register to detect link 5972 * changes, thereby adding an additional register access to 5973 * the interrupt handler. 5974 * 5975 * XXX: perhaps link state detection procedure used for 5976 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5977 */ 5978 5979 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5980 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5981 status = CSR_READ_4(sc, BGE_MAC_STS); 5982 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5983 mii = device_get_softc(sc->bge_miibus); 5984 mii_pollstat(mii); 5985 if (!sc->bge_link && 5986 mii->mii_media_status & IFM_ACTIVE && 5987 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5988 sc->bge_link++; 5989 if (bootverbose) 5990 if_printf(sc->bge_ifp, "link UP\n"); 5991 } else if (sc->bge_link && 5992 (!(mii->mii_media_status & IFM_ACTIVE) || 5993 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5994 sc->bge_link = 0; 5995 if (bootverbose) 5996 if_printf(sc->bge_ifp, "link DOWN\n"); 5997 } 5998 5999 /* Clear the interrupt. */ 6000 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6001 BGE_EVTENB_MI_INTERRUPT); 6002 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6003 BRGPHY_MII_ISR); 6004 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6005 BRGPHY_MII_IMR, BRGPHY_INTRS); 6006 } 6007 return; 6008 } 6009 6010 if (sc->bge_flags & BGE_FLAG_TBI) { 6011 status = CSR_READ_4(sc, BGE_MAC_STS); 6012 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6013 if (!sc->bge_link) { 6014 sc->bge_link++; 6015 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6016 BGE_CLRBIT(sc, BGE_MAC_MODE, 6017 BGE_MACMODE_TBI_SEND_CFGS); 6018 DELAY(40); 6019 } 6020 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6021 if (bootverbose) 6022 if_printf(sc->bge_ifp, "link UP\n"); 6023 if_link_state_change(sc->bge_ifp, 6024 LINK_STATE_UP); 6025 } 6026 } else if (sc->bge_link) { 6027 sc->bge_link = 0; 6028 if (bootverbose) 6029 if_printf(sc->bge_ifp, "link DOWN\n"); 6030 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6031 } 6032 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6033 /* 6034 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6035 * in status word always set. Workaround this bug by reading 6036 * PHY link status directly. 6037 */ 6038 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6039 6040 if (link != sc->bge_link || 6041 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6042 mii = device_get_softc(sc->bge_miibus); 6043 mii_pollstat(mii); 6044 if (!sc->bge_link && 6045 mii->mii_media_status & IFM_ACTIVE && 6046 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6047 sc->bge_link++; 6048 if (bootverbose) 6049 if_printf(sc->bge_ifp, "link UP\n"); 6050 } else if (sc->bge_link && 6051 (!(mii->mii_media_status & IFM_ACTIVE) || 6052 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6053 sc->bge_link = 0; 6054 if (bootverbose) 6055 if_printf(sc->bge_ifp, "link DOWN\n"); 6056 } 6057 } 6058 } else { 6059 /* 6060 * For controllers that call mii_tick, we have to poll 6061 * link status. 6062 */ 6063 mii = device_get_softc(sc->bge_miibus); 6064 mii_pollstat(mii); 6065 bge_miibus_statchg(sc->bge_dev); 6066 } 6067 6068 /* Disable MAC attention when link is up. */ 6069 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6070 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6071 BGE_MACSTAT_LINK_CHANGED); 6072 } 6073 6074 static void 6075 bge_add_sysctls(struct bge_softc *sc) 6076 { 6077 struct sysctl_ctx_list *ctx; 6078 struct sysctl_oid_list *children; 6079 char tn[32]; 6080 int unit; 6081 6082 ctx = device_get_sysctl_ctx(sc->bge_dev); 6083 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6084 6085 #ifdef BGE_REGISTER_DEBUG 6086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6087 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6088 "Debug Information"); 6089 6090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6091 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6092 "MAC Register Read"); 6093 6094 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6095 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6096 "APE Register Read"); 6097 6098 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6099 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6100 "Memory Read"); 6101 6102 #endif 6103 6104 unit = device_get_unit(sc->bge_dev); 6105 /* 6106 * A common design characteristic for many Broadcom client controllers 6107 * is that they only support a single outstanding DMA read operation 6108 * on the PCIe bus. This means that it will take twice as long to fetch 6109 * a TX frame that is split into header and payload buffers as it does 6110 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6111 * these controllers, coalescing buffers to reduce the number of memory 6112 * reads is effective way to get maximum performance(about 940Mbps). 6113 * Without collapsing TX buffers the maximum TCP bulk transfer 6114 * performance is about 850Mbps. However forcing coalescing mbufs 6115 * consumes a lot of CPU cycles, so leave it off by default. 6116 */ 6117 sc->bge_forced_collapse = 0; 6118 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6119 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6120 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6121 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6122 "Number of fragmented TX buffers of a frame allowed before " 6123 "forced collapsing"); 6124 6125 sc->bge_msi = 1; 6126 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6127 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6128 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6129 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6130 6131 /* 6132 * It seems all Broadcom controllers have a bug that can generate UDP 6133 * datagrams with checksum value 0 when TX UDP checksum offloading is 6134 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6135 * Even though the probability of generating such UDP datagrams is 6136 * low, I don't want to see FreeBSD boxes to inject such datagrams 6137 * into network so disable UDP checksum offloading by default. Users 6138 * still override this behavior by setting a sysctl variable, 6139 * dev.bge.0.forced_udpcsum. 6140 */ 6141 sc->bge_forced_udpcsum = 0; 6142 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6143 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6144 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6145 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6146 "Enable UDP checksum offloading even if controller can " 6147 "generate UDP checksum value 0"); 6148 6149 if (BGE_IS_5705_PLUS(sc)) 6150 bge_add_sysctl_stats_regs(sc, ctx, children); 6151 else 6152 bge_add_sysctl_stats(sc, ctx, children); 6153 } 6154 6155 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6156 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6157 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6158 desc) 6159 6160 static void 6161 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6162 struct sysctl_oid_list *parent) 6163 { 6164 struct sysctl_oid *tree; 6165 struct sysctl_oid_list *children, *schildren; 6166 6167 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6168 NULL, "BGE Statistics"); 6169 schildren = children = SYSCTL_CHILDREN(tree); 6170 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6171 children, COSFramesDroppedDueToFilters, 6172 "FramesDroppedDueToFilters"); 6173 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6174 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6175 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6176 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6177 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6178 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6179 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6180 children, ifInDiscards, "InputDiscards"); 6181 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6182 children, ifInErrors, "InputErrors"); 6183 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6184 children, nicRecvThresholdHit, "RecvThresholdHit"); 6185 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6186 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6187 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6188 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6189 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6190 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6191 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6192 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6193 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6194 children, nicRingStatusUpdate, "RingStatusUpdate"); 6195 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6196 children, nicInterrupts, "Interrupts"); 6197 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6198 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6199 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6200 children, nicSendThresholdHit, "SendThresholdHit"); 6201 6202 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6203 NULL, "BGE RX Statistics"); 6204 children = SYSCTL_CHILDREN(tree); 6205 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6206 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6207 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6208 children, rxstats.etherStatsFragments, "Fragments"); 6209 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6210 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6211 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6212 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6213 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6214 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6215 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6216 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6217 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6218 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6219 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6220 children, rxstats.xoffPauseFramesReceived, 6221 "xoffPauseFramesReceived"); 6222 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6223 children, rxstats.macControlFramesReceived, 6224 "ControlFramesReceived"); 6225 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6226 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6227 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6228 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6229 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6230 children, rxstats.etherStatsJabbers, "Jabbers"); 6231 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6232 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6233 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6234 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6235 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6236 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6237 6238 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6239 NULL, "BGE TX Statistics"); 6240 children = SYSCTL_CHILDREN(tree); 6241 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6242 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6243 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6244 children, txstats.etherStatsCollisions, "Collisions"); 6245 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6246 children, txstats.outXonSent, "XonSent"); 6247 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6248 children, txstats.outXoffSent, "XoffSent"); 6249 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6250 children, txstats.flowControlDone, "flowControlDone"); 6251 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6252 children, txstats.dot3StatsInternalMacTransmitErrors, 6253 "InternalMacTransmitErrors"); 6254 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6255 children, txstats.dot3StatsSingleCollisionFrames, 6256 "SingleCollisionFrames"); 6257 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6258 children, txstats.dot3StatsMultipleCollisionFrames, 6259 "MultipleCollisionFrames"); 6260 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6261 children, txstats.dot3StatsDeferredTransmissions, 6262 "DeferredTransmissions"); 6263 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6264 children, txstats.dot3StatsExcessiveCollisions, 6265 "ExcessiveCollisions"); 6266 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6267 children, txstats.dot3StatsLateCollisions, 6268 "LateCollisions"); 6269 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6270 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6271 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6272 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6273 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6274 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6275 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6276 children, txstats.dot3StatsCarrierSenseErrors, 6277 "CarrierSenseErrors"); 6278 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6279 children, txstats.ifOutDiscards, "Discards"); 6280 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6281 children, txstats.ifOutErrors, "Errors"); 6282 } 6283 6284 #undef BGE_SYSCTL_STAT 6285 6286 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6287 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6288 6289 static void 6290 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6291 struct sysctl_oid_list *parent) 6292 { 6293 struct sysctl_oid *tree; 6294 struct sysctl_oid_list *child, *schild; 6295 struct bge_mac_stats *stats; 6296 6297 stats = &sc->bge_mac_stats; 6298 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6299 NULL, "BGE Statistics"); 6300 schild = child = SYSCTL_CHILDREN(tree); 6301 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6302 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6303 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6304 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6305 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6306 &stats->DmaWriteHighPriQueueFull, 6307 "NIC DMA Write High Priority Queue Full"); 6308 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6309 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6310 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6311 &stats->InputDiscards, "Discarded Input Frames"); 6312 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6313 &stats->InputErrors, "Input Errors"); 6314 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6315 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6316 6317 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6318 NULL, "BGE RX Statistics"); 6319 child = SYSCTL_CHILDREN(tree); 6320 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6321 &stats->ifHCInOctets, "Inbound Octets"); 6322 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6323 &stats->etherStatsFragments, "Fragments"); 6324 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6325 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6326 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6327 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6328 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6329 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6330 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6331 &stats->dot3StatsFCSErrors, "FCS Errors"); 6332 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6333 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6334 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6335 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6336 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6337 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6338 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6339 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6340 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6341 &stats->xoffStateEntered, "XOFF State Entered"); 6342 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6343 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6344 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6345 &stats->etherStatsJabbers, "Jabbers"); 6346 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6347 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6348 6349 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6350 NULL, "BGE TX Statistics"); 6351 child = SYSCTL_CHILDREN(tree); 6352 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6353 &stats->ifHCOutOctets, "Outbound Octets"); 6354 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6355 &stats->etherStatsCollisions, "TX Collisions"); 6356 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6357 &stats->outXonSent, "XON Sent"); 6358 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6359 &stats->outXoffSent, "XOFF Sent"); 6360 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6361 &stats->dot3StatsInternalMacTransmitErrors, 6362 "Internal MAC TX Errors"); 6363 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6364 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6365 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6366 &stats->dot3StatsMultipleCollisionFrames, 6367 "Multiple Collision Frames"); 6368 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6369 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6370 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6371 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6372 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6373 &stats->dot3StatsLateCollisions, "Late Collisions"); 6374 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6375 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6376 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6377 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6378 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6379 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6380 } 6381 6382 #undef BGE_SYSCTL_STAT_ADD64 6383 6384 static int 6385 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6386 { 6387 struct bge_softc *sc; 6388 uint32_t result; 6389 int offset; 6390 6391 sc = (struct bge_softc *)arg1; 6392 offset = arg2; 6393 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6394 offsetof(bge_hostaddr, bge_addr_lo)); 6395 return (sysctl_handle_int(oidp, &result, 0, req)); 6396 } 6397 6398 #ifdef BGE_REGISTER_DEBUG 6399 static int 6400 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6401 { 6402 struct bge_softc *sc; 6403 uint16_t *sbdata; 6404 int error, result, sbsz; 6405 int i, j; 6406 6407 result = -1; 6408 error = sysctl_handle_int(oidp, &result, 0, req); 6409 if (error || (req->newptr == NULL)) 6410 return (error); 6411 6412 if (result == 1) { 6413 sc = (struct bge_softc *)arg1; 6414 6415 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6416 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6417 sbsz = BGE_STATUS_BLK_SZ; 6418 else 6419 sbsz = 32; 6420 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6421 printf("Status Block:\n"); 6422 BGE_LOCK(sc); 6423 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6424 sc->bge_cdata.bge_status_map, 6425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6426 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6427 printf("%06x:", i); 6428 for (j = 0; j < 8; j++) 6429 printf(" %04x", sbdata[i++]); 6430 printf("\n"); 6431 } 6432 6433 printf("Registers:\n"); 6434 for (i = 0x800; i < 0xA00; ) { 6435 printf("%06x:", i); 6436 for (j = 0; j < 8; j++) { 6437 printf(" %08x", CSR_READ_4(sc, i)); 6438 i += 4; 6439 } 6440 printf("\n"); 6441 } 6442 BGE_UNLOCK(sc); 6443 6444 printf("Hardware Flags:\n"); 6445 if (BGE_IS_5717_PLUS(sc)) 6446 printf(" - 5717 Plus\n"); 6447 if (BGE_IS_5755_PLUS(sc)) 6448 printf(" - 5755 Plus\n"); 6449 if (BGE_IS_575X_PLUS(sc)) 6450 printf(" - 575X Plus\n"); 6451 if (BGE_IS_5705_PLUS(sc)) 6452 printf(" - 5705 Plus\n"); 6453 if (BGE_IS_5714_FAMILY(sc)) 6454 printf(" - 5714 Family\n"); 6455 if (BGE_IS_5700_FAMILY(sc)) 6456 printf(" - 5700 Family\n"); 6457 if (sc->bge_flags & BGE_FLAG_JUMBO) 6458 printf(" - Supports Jumbo Frames\n"); 6459 if (sc->bge_flags & BGE_FLAG_PCIX) 6460 printf(" - PCI-X Bus\n"); 6461 if (sc->bge_flags & BGE_FLAG_PCIE) 6462 printf(" - PCI Express Bus\n"); 6463 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6464 printf(" - No 3 LEDs\n"); 6465 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6466 printf(" - RX Alignment Bug\n"); 6467 } 6468 6469 return (error); 6470 } 6471 6472 static int 6473 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6474 { 6475 struct bge_softc *sc; 6476 int error; 6477 uint16_t result; 6478 uint32_t val; 6479 6480 result = -1; 6481 error = sysctl_handle_int(oidp, &result, 0, req); 6482 if (error || (req->newptr == NULL)) 6483 return (error); 6484 6485 if (result < 0x8000) { 6486 sc = (struct bge_softc *)arg1; 6487 val = CSR_READ_4(sc, result); 6488 printf("reg 0x%06X = 0x%08X\n", result, val); 6489 } 6490 6491 return (error); 6492 } 6493 6494 static int 6495 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6496 { 6497 struct bge_softc *sc; 6498 int error; 6499 uint16_t result; 6500 uint32_t val; 6501 6502 result = -1; 6503 error = sysctl_handle_int(oidp, &result, 0, req); 6504 if (error || (req->newptr == NULL)) 6505 return (error); 6506 6507 if (result < 0x8000) { 6508 sc = (struct bge_softc *)arg1; 6509 val = APE_READ_4(sc, result); 6510 printf("reg 0x%06X = 0x%08X\n", result, val); 6511 } 6512 6513 return (error); 6514 } 6515 6516 static int 6517 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6518 { 6519 struct bge_softc *sc; 6520 int error; 6521 uint16_t result; 6522 uint32_t val; 6523 6524 result = -1; 6525 error = sysctl_handle_int(oidp, &result, 0, req); 6526 if (error || (req->newptr == NULL)) 6527 return (error); 6528 6529 if (result < 0x8000) { 6530 sc = (struct bge_softc *)arg1; 6531 val = bge_readmem_ind(sc, result); 6532 printf("mem 0x%06X = 0x%08X\n", result, val); 6533 } 6534 6535 return (error); 6536 } 6537 #endif 6538 6539 static int 6540 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6541 { 6542 6543 if (sc->bge_flags & BGE_FLAG_EADDR) 6544 return (1); 6545 6546 #ifdef __sparc64__ 6547 OF_getetheraddr(sc->bge_dev, ether_addr); 6548 return (0); 6549 #endif 6550 return (1); 6551 } 6552 6553 static int 6554 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6555 { 6556 uint32_t mac_addr; 6557 6558 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6559 if ((mac_addr >> 16) == 0x484b) { 6560 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6561 ether_addr[1] = (uint8_t)mac_addr; 6562 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6563 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6564 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6565 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6566 ether_addr[5] = (uint8_t)mac_addr; 6567 return (0); 6568 } 6569 return (1); 6570 } 6571 6572 static int 6573 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6574 { 6575 int mac_offset = BGE_EE_MAC_OFFSET; 6576 6577 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6578 mac_offset = BGE_EE_MAC_OFFSET_5906; 6579 6580 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6581 ETHER_ADDR_LEN)); 6582 } 6583 6584 static int 6585 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6586 { 6587 6588 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6589 return (1); 6590 6591 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6592 ETHER_ADDR_LEN)); 6593 } 6594 6595 static int 6596 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6597 { 6598 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6599 /* NOTE: Order is critical */ 6600 bge_get_eaddr_fw, 6601 bge_get_eaddr_mem, 6602 bge_get_eaddr_nvram, 6603 bge_get_eaddr_eeprom, 6604 NULL 6605 }; 6606 const bge_eaddr_fcn_t *func; 6607 6608 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6609 if ((*func)(sc, eaddr) == 0) 6610 break; 6611 } 6612 return (*func == NULL ? ENXIO : 0); 6613 } 6614