1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <vm/vm.h> /* for vtophys */ 98 #include <vm/pmap.h> /* for vtophys */ 99 #include <machine/clock.h> /* for DELAY */ 100 #include <machine/bus_memio.h> 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include <dev/mii/miidevs.h> 109 #include <dev/mii/brgphyreg.h> 110 111 #include <pci/pcireg.h> 112 #include <pci/pcivar.h> 113 114 #include <dev/bge/if_bgereg.h> 115 116 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 117 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #if !defined(lint) 124 static const char rcsid[] = 125 "$FreeBSD$"; 126 #endif 127 128 /* 129 * Various supported device vendors/types and their names. Note: the 130 * spec seems to indicate that the hardware still has Alteon's vendor 131 * ID burned into it, though it will always be overriden by the vendor 132 * ID in the EEPROM. Just to be safe, we cover all possibilities. 133 */ 134 135 static struct bge_type bge_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 141 "Broadcom BCM5700 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 143 "Broadcom BCM5701 Gigabit Ethernet" }, 144 { SK_VENDORID, SK_DEVICEID_ALTIMA, 145 "SysKonnect Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int bge_probe __P((device_t)); 150 static int bge_attach __P((device_t)); 151 static int bge_detach __P((device_t)); 152 static void bge_release_resources 153 __P((struct bge_softc *)); 154 static void bge_txeof __P((struct bge_softc *)); 155 static void bge_rxeof __P((struct bge_softc *)); 156 157 static void bge_tick __P((void *)); 158 static void bge_stats_update __P((struct bge_softc *)); 159 static int bge_encap __P((struct bge_softc *, struct mbuf *, 160 u_int32_t *)); 161 162 static void bge_intr __P((void *)); 163 static void bge_start __P((struct ifnet *)); 164 static int bge_ioctl __P((struct ifnet *, u_long, caddr_t)); 165 static void bge_init __P((void *)); 166 static void bge_stop __P((struct bge_softc *)); 167 static void bge_watchdog __P((struct ifnet *)); 168 static void bge_shutdown __P((device_t)); 169 static int bge_ifmedia_upd __P((struct ifnet *)); 170 static void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 171 172 static u_int8_t bge_eeprom_getbyte __P((struct bge_softc *, 173 int, u_int8_t *)); 174 static int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int)); 175 176 static u_int32_t bge_crc __P((caddr_t)); 177 static void bge_setmulti __P((struct bge_softc *)); 178 179 static void bge_handle_events __P((struct bge_softc *)); 180 static int bge_alloc_jumbo_mem __P((struct bge_softc *)); 181 static void bge_free_jumbo_mem __P((struct bge_softc *)); 182 static void *bge_jalloc __P((struct bge_softc *)); 183 static void bge_jfree __P((caddr_t, void *)); 184 static int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *)); 185 static int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *)); 186 static int bge_init_rx_ring_std __P((struct bge_softc *)); 187 static void bge_free_rx_ring_std __P((struct bge_softc *)); 188 static int bge_init_rx_ring_jumbo __P((struct bge_softc *)); 189 static void bge_free_rx_ring_jumbo __P((struct bge_softc *)); 190 static void bge_free_tx_ring __P((struct bge_softc *)); 191 static int bge_init_tx_ring __P((struct bge_softc *)); 192 193 static int bge_chipinit __P((struct bge_softc *)); 194 static int bge_blockinit __P((struct bge_softc *)); 195 196 static u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int)); 197 static void bge_vpd_read_res __P((struct bge_softc *, 198 struct vpd_res *, int)); 199 static void bge_vpd_read __P((struct bge_softc *)); 200 201 static u_int32_t bge_readmem_ind 202 __P((struct bge_softc *, int)); 203 static void bge_writemem_ind __P((struct bge_softc *, int, int)); 204 #ifdef notdef 205 static u_int32_t bge_readreg_ind 206 __P((struct bge_softc *, int)); 207 #endif 208 static void bge_writereg_ind __P((struct bge_softc *, int, int)); 209 210 static int bge_miibus_readreg __P((device_t, int, int)); 211 static int bge_miibus_writereg __P((device_t, int, int, int)); 212 static void bge_miibus_statchg __P((device_t)); 213 214 static void bge_reset __P((struct bge_softc *)); 215 static void bge_phy_hack __P((struct bge_softc *)); 216 217 static device_method_t bge_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, bge_probe), 220 DEVMETHOD(device_attach, bge_attach), 221 DEVMETHOD(device_detach, bge_detach), 222 DEVMETHOD(device_shutdown, bge_shutdown), 223 224 /* bus interface */ 225 DEVMETHOD(bus_print_child, bus_generic_print_child), 226 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 227 228 /* MII interface */ 229 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 230 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 231 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 232 233 { 0, 0 } 234 }; 235 236 static driver_t bge_driver = { 237 "bge", 238 bge_methods, 239 sizeof(struct bge_softc) 240 }; 241 242 static devclass_t bge_devclass; 243 244 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 245 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 246 247 static u_int32_t 248 bge_readmem_ind(sc, off) 249 struct bge_softc *sc; 250 int off; 251 { 252 device_t dev; 253 254 dev = sc->bge_dev; 255 256 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 257 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 258 } 259 260 static void 261 bge_writemem_ind(sc, off, val) 262 struct bge_softc *sc; 263 int off, val; 264 { 265 device_t dev; 266 267 dev = sc->bge_dev; 268 269 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 270 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 271 272 return; 273 } 274 275 #ifdef notdef 276 static u_int32_t 277 bge_readreg_ind(sc, off) 278 struct bge_softc *sc; 279 int off; 280 { 281 device_t dev; 282 283 dev = sc->bge_dev; 284 285 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 286 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 287 } 288 #endif 289 290 static void 291 bge_writereg_ind(sc, off, val) 292 struct bge_softc *sc; 293 int off, val; 294 { 295 device_t dev; 296 297 dev = sc->bge_dev; 298 299 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 300 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 301 302 return; 303 } 304 305 static u_int8_t 306 bge_vpd_readbyte(sc, addr) 307 struct bge_softc *sc; 308 int addr; 309 { 310 int i; 311 device_t dev; 312 u_int32_t val; 313 314 dev = sc->bge_dev; 315 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 316 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 317 DELAY(10); 318 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 319 break; 320 } 321 322 if (i == BGE_TIMEOUT) { 323 printf("bge%d: VPD read timed out\n", sc->bge_unit); 324 return(0); 325 } 326 327 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 328 329 return((val >> ((addr % 4) * 8)) & 0xFF); 330 } 331 332 static void 333 bge_vpd_read_res(sc, res, addr) 334 struct bge_softc *sc; 335 struct vpd_res *res; 336 int addr; 337 { 338 int i; 339 u_int8_t *ptr; 340 341 ptr = (u_int8_t *)res; 342 for (i = 0; i < sizeof(struct vpd_res); i++) 343 ptr[i] = bge_vpd_readbyte(sc, i + addr); 344 345 return; 346 } 347 348 static void 349 bge_vpd_read(sc) 350 struct bge_softc *sc; 351 { 352 int pos = 0, i; 353 struct vpd_res res; 354 355 if (sc->bge_vpd_prodname != NULL) 356 free(sc->bge_vpd_prodname, M_DEVBUF); 357 if (sc->bge_vpd_readonly != NULL) 358 free(sc->bge_vpd_readonly, M_DEVBUF); 359 sc->bge_vpd_prodname = NULL; 360 sc->bge_vpd_readonly = NULL; 361 362 bge_vpd_read_res(sc, &res, pos); 363 364 if (res.vr_id != VPD_RES_ID) { 365 printf("bge%d: bad VPD resource id: expected %x got %x\n", 366 sc->bge_unit, VPD_RES_ID, res.vr_id); 367 return; 368 } 369 370 pos += sizeof(res); 371 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 372 for (i = 0; i < res.vr_len; i++) 373 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 374 sc->bge_vpd_prodname[i] = '\0'; 375 pos += i; 376 377 bge_vpd_read_res(sc, &res, pos); 378 379 if (res.vr_id != VPD_RES_READ) { 380 printf("bge%d: bad VPD resource id: expected %x got %x\n", 381 sc->bge_unit, VPD_RES_READ, res.vr_id); 382 return; 383 } 384 385 pos += sizeof(res); 386 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 387 for (i = 0; i < res.vr_len + 1; i++) 388 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 389 390 return; 391 } 392 393 /* 394 * Read a byte of data stored in the EEPROM at address 'addr.' The 395 * BCM570x supports both the traditional bitbang interface and an 396 * auto access interface for reading the EEPROM. We use the auto 397 * access method. 398 */ 399 static u_int8_t 400 bge_eeprom_getbyte(sc, addr, dest) 401 struct bge_softc *sc; 402 int addr; 403 u_int8_t *dest; 404 { 405 int i; 406 u_int32_t byte = 0; 407 408 /* 409 * Enable use of auto EEPROM access so we can avoid 410 * having to use the bitbang method. 411 */ 412 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 413 414 /* Reset the EEPROM, load the clock period. */ 415 CSR_WRITE_4(sc, BGE_EE_ADDR, 416 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 417 DELAY(20); 418 419 /* Issue the read EEPROM command. */ 420 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 421 422 /* Wait for completion */ 423 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 424 DELAY(10); 425 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 426 break; 427 } 428 429 if (i == BGE_TIMEOUT) { 430 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 431 return(0); 432 } 433 434 /* Get result. */ 435 byte = CSR_READ_4(sc, BGE_EE_DATA); 436 437 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 438 439 return(0); 440 } 441 442 /* 443 * Read a sequence of bytes from the EEPROM. 444 */ 445 static int 446 bge_read_eeprom(sc, dest, off, cnt) 447 struct bge_softc *sc; 448 caddr_t dest; 449 int off; 450 int cnt; 451 { 452 int err = 0, i; 453 u_int8_t byte = 0; 454 455 for (i = 0; i < cnt; i++) { 456 err = bge_eeprom_getbyte(sc, off + i, &byte); 457 if (err) 458 break; 459 *(dest + i) = byte; 460 } 461 462 return(err ? 1 : 0); 463 } 464 465 static int 466 bge_miibus_readreg(dev, phy, reg) 467 device_t dev; 468 int phy, reg; 469 { 470 struct bge_softc *sc; 471 struct ifnet *ifp; 472 u_int32_t val; 473 int i; 474 475 sc = device_get_softc(dev); 476 ifp = &sc->arpcom.ac_if; 477 478 if (ifp->if_flags & IFF_RUNNING) 479 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 480 481 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 482 BGE_MIPHY(phy)|BGE_MIREG(reg)); 483 484 for (i = 0; i < BGE_TIMEOUT; i++) { 485 val = CSR_READ_4(sc, BGE_MI_COMM); 486 if (!(val & BGE_MICOMM_BUSY)) 487 break; 488 } 489 490 if (i == BGE_TIMEOUT) { 491 printf("bge%d: PHY read timed out\n", sc->bge_unit); 492 return(0); 493 } 494 495 val = CSR_READ_4(sc, BGE_MI_COMM); 496 497 if (ifp->if_flags & IFF_RUNNING) 498 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 499 500 if (val & BGE_MICOMM_READFAIL) 501 return(0); 502 503 return(val & 0xFFFF); 504 } 505 506 static int 507 bge_miibus_writereg(dev, phy, reg, val) 508 device_t dev; 509 int phy, reg, val; 510 { 511 struct bge_softc *sc; 512 int i; 513 514 sc = device_get_softc(dev); 515 516 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 517 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 518 519 for (i = 0; i < BGE_TIMEOUT; i++) { 520 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 521 break; 522 } 523 524 if (i == BGE_TIMEOUT) { 525 printf("bge%d: PHY read timed out\n", sc->bge_unit); 526 return(0); 527 } 528 529 return(0); 530 } 531 532 static void 533 bge_miibus_statchg(dev) 534 device_t dev; 535 { 536 struct bge_softc *sc; 537 struct mii_data *mii; 538 539 sc = device_get_softc(dev); 540 mii = device_get_softc(sc->bge_miibus); 541 542 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 543 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 544 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 545 } else { 546 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 547 } 548 549 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 550 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 551 } else { 552 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 553 } 554 555 bge_phy_hack(sc); 556 557 return; 558 } 559 560 /* 561 * Handle events that have triggered interrupts. 562 */ 563 static void 564 bge_handle_events(sc) 565 struct bge_softc *sc; 566 { 567 568 return; 569 } 570 571 /* 572 * Memory management for jumbo frames. 573 */ 574 575 static int 576 bge_alloc_jumbo_mem(sc) 577 struct bge_softc *sc; 578 { 579 caddr_t ptr; 580 register int i; 581 struct bge_jpool_entry *entry; 582 583 /* Grab a big chunk o' storage. */ 584 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 585 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 586 587 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 588 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 589 return(ENOBUFS); 590 } 591 592 SLIST_INIT(&sc->bge_jfree_listhead); 593 SLIST_INIT(&sc->bge_jinuse_listhead); 594 595 /* 596 * Now divide it up into 9K pieces and save the addresses 597 * in an array. 598 */ 599 ptr = sc->bge_cdata.bge_jumbo_buf; 600 for (i = 0; i < BGE_JSLOTS; i++) { 601 sc->bge_cdata.bge_jslots[i] = ptr; 602 ptr += BGE_JLEN; 603 entry = malloc(sizeof(struct bge_jpool_entry), 604 M_DEVBUF, M_NOWAIT); 605 if (entry == NULL) { 606 contigfree(sc->bge_cdata.bge_jumbo_buf, 607 BGE_JMEM, M_DEVBUF); 608 sc->bge_cdata.bge_jumbo_buf = NULL; 609 printf("bge%d: no memory for jumbo " 610 "buffer queue!\n", sc->bge_unit); 611 return(ENOBUFS); 612 } 613 entry->slot = i; 614 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 615 entry, jpool_entries); 616 } 617 618 return(0); 619 } 620 621 static void 622 bge_free_jumbo_mem(sc) 623 struct bge_softc *sc; 624 { 625 int i; 626 struct bge_jpool_entry *entry; 627 628 for (i = 0; i < BGE_JSLOTS; i++) { 629 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 630 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 631 free(entry, M_DEVBUF); 632 } 633 634 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 635 636 return; 637 } 638 639 /* 640 * Allocate a jumbo buffer. 641 */ 642 static void * 643 bge_jalloc(sc) 644 struct bge_softc *sc; 645 { 646 struct bge_jpool_entry *entry; 647 648 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 649 650 if (entry == NULL) { 651 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 652 return(NULL); 653 } 654 655 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 656 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 657 return(sc->bge_cdata.bge_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 static void 664 bge_jfree(buf, args) 665 caddr_t buf; 666 void *args; 667 { 668 struct bge_jpool_entry *entry; 669 struct bge_softc *sc; 670 int i; 671 672 /* Extract the softc struct pointer. */ 673 sc = (struct bge_softc *)args; 674 675 if (sc == NULL) 676 panic("bge_jfree: can't find softc pointer!"); 677 678 /* calculate the slot this buffer belongs to */ 679 680 i = ((vm_offset_t)buf 681 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 682 683 if ((i < 0) || (i >= BGE_JSLOTS)) 684 panic("bge_jfree: asked to free buffer that we don't manage!"); 685 686 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 687 if (entry == NULL) 688 panic("bge_jfree: buffer not in use!"); 689 entry->slot = i; 690 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 691 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 692 693 return; 694 } 695 696 697 /* 698 * Intialize a standard receive ring descriptor. 699 */ 700 static int 701 bge_newbuf_std(sc, i, m) 702 struct bge_softc *sc; 703 int i; 704 struct mbuf *m; 705 { 706 struct mbuf *m_new = NULL; 707 struct bge_rx_bd *r; 708 709 if (m == NULL) { 710 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 711 if (m_new == NULL) { 712 printf("bge%d: mbuf allocation failed " 713 "-- packet dropped!\n", sc->bge_unit); 714 return(ENOBUFS); 715 } 716 717 MCLGET(m_new, M_DONTWAIT); 718 if (!(m_new->m_flags & M_EXT)) { 719 printf("bge%d: cluster allocation failed " 720 "-- packet dropped!\n", sc->bge_unit); 721 m_freem(m_new); 722 return(ENOBUFS); 723 } 724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 725 } else { 726 m_new = m; 727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 728 m_new->m_data = m_new->m_ext.ext_buf; 729 } 730 731 m_adj(m_new, ETHER_ALIGN); 732 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 733 r = &sc->bge_rdata->bge_rx_std_ring[i]; 734 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 735 r->bge_flags = BGE_RXBDFLAG_END; 736 r->bge_len = m_new->m_len; 737 r->bge_idx = i; 738 739 return(0); 740 } 741 742 /* 743 * Initialize a jumbo receive ring descriptor. This allocates 744 * a jumbo buffer from the pool managed internally by the driver. 745 */ 746 static int 747 bge_newbuf_jumbo(sc, i, m) 748 struct bge_softc *sc; 749 int i; 750 struct mbuf *m; 751 { 752 struct mbuf *m_new = NULL; 753 struct bge_rx_bd *r; 754 755 if (m == NULL) { 756 caddr_t *buf = NULL; 757 758 /* Allocate the mbuf. */ 759 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 760 if (m_new == NULL) { 761 printf("bge%d: mbuf allocation failed " 762 "-- packet dropped!\n", sc->bge_unit); 763 return(ENOBUFS); 764 } 765 766 /* Allocate the jumbo buffer */ 767 buf = bge_jalloc(sc); 768 if (buf == NULL) { 769 m_freem(m_new); 770 printf("bge%d: jumbo allocation failed " 771 "-- packet dropped!\n", sc->bge_unit); 772 return(ENOBUFS); 773 } 774 775 /* Attach the buffer to the mbuf. */ 776 m_new->m_data = (void *) buf; 777 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 778 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 779 (struct bge_softc *)sc, 0, EXT_NET_DRV); 780 } else { 781 m_new = m; 782 m_new->m_data = m_new->m_ext.ext_buf; 783 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 784 } 785 786 m_adj(m_new, ETHER_ALIGN); 787 /* Set up the descriptor. */ 788 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 789 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 790 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 791 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 792 r->bge_len = m_new->m_len; 793 r->bge_idx = i; 794 795 return(0); 796 } 797 798 /* 799 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 800 * that's 1MB or memory, which is a lot. For now, we fill only the first 801 * 256 ring entries and hope that our CPU is fast enough to keep up with 802 * the NIC. 803 */ 804 static int 805 bge_init_rx_ring_std(sc) 806 struct bge_softc *sc; 807 { 808 int i; 809 810 for (i = 0; i < BGE_SSLOTS; i++) { 811 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 812 return(ENOBUFS); 813 }; 814 815 sc->bge_std = i - 1; 816 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 817 818 return(0); 819 } 820 821 static void 822 bge_free_rx_ring_std(sc) 823 struct bge_softc *sc; 824 { 825 int i; 826 827 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 828 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 829 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 830 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 831 } 832 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 833 sizeof(struct bge_rx_bd)); 834 } 835 836 return; 837 } 838 839 static int 840 bge_init_rx_ring_jumbo(sc) 841 struct bge_softc *sc; 842 { 843 int i; 844 struct bge_rcb *rcb; 845 struct bge_rcb_opaque *rcbo; 846 847 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 848 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 849 return(ENOBUFS); 850 }; 851 852 sc->bge_jumbo = i - 1; 853 854 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 855 rcbo = (struct bge_rcb_opaque *)rcb; 856 rcb->bge_flags = 0; 857 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 858 859 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 860 861 return(0); 862 } 863 864 static void 865 bge_free_rx_ring_jumbo(sc) 866 struct bge_softc *sc; 867 { 868 int i; 869 870 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 871 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 872 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 873 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 874 } 875 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 876 sizeof(struct bge_rx_bd)); 877 } 878 879 return; 880 } 881 882 static void 883 bge_free_tx_ring(sc) 884 struct bge_softc *sc; 885 { 886 int i; 887 888 if (sc->bge_rdata->bge_tx_ring == NULL) 889 return; 890 891 for (i = 0; i < BGE_TX_RING_CNT; i++) { 892 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 893 m_freem(sc->bge_cdata.bge_tx_chain[i]); 894 sc->bge_cdata.bge_tx_chain[i] = NULL; 895 } 896 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 897 sizeof(struct bge_tx_bd)); 898 } 899 900 return; 901 } 902 903 static int 904 bge_init_tx_ring(sc) 905 struct bge_softc *sc; 906 { 907 sc->bge_txcnt = 0; 908 sc->bge_tx_saved_considx = 0; 909 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 910 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 911 912 return(0); 913 } 914 915 #define BGE_POLY 0xEDB88320 916 917 static u_int32_t 918 bge_crc(addr) 919 caddr_t addr; 920 { 921 u_int32_t idx, bit, data, crc; 922 923 /* Compute CRC for the address value. */ 924 crc = 0xFFFFFFFF; /* initial value */ 925 926 for (idx = 0; idx < 6; idx++) { 927 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 928 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 929 } 930 931 return(crc & 0x7F); 932 } 933 934 static void 935 bge_setmulti(sc) 936 struct bge_softc *sc; 937 { 938 struct ifnet *ifp; 939 struct ifmultiaddr *ifma; 940 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 941 int h, i; 942 943 ifp = &sc->arpcom.ac_if; 944 945 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 946 for (i = 0; i < 4; i++) 947 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 948 return; 949 } 950 951 /* First, zot all the existing filters. */ 952 for (i = 0; i < 4; i++) 953 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 954 955 /* Now program new ones. */ 956 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 957 if (ifma->ifma_addr->sa_family != AF_LINK) 958 continue; 959 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 960 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 961 } 962 963 for (i = 0; i < 4; i++) 964 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 965 966 return; 967 } 968 969 /* 970 * Do endian, PCI and DMA initialization. Also check the on-board ROM 971 * self-test results. 972 */ 973 static int 974 bge_chipinit(sc) 975 struct bge_softc *sc; 976 { 977 u_int32_t cachesize; 978 int i; 979 980 /* Set endianness before we access any non-PCI registers. */ 981 #if BYTE_ORDER == BIG_ENDIAN 982 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 983 BGE_BIGENDIAN_INIT, 4); 984 #else 985 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 986 BGE_LITTLEENDIAN_INIT, 4); 987 #endif 988 989 /* 990 * Check the 'ROM failed' bit on the RX CPU to see if 991 * self-tests passed. 992 */ 993 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 994 printf("bge%d: RX CPU self-diagnostics failed!\n", 995 sc->bge_unit); 996 return(ENODEV); 997 } 998 999 /* Clear the MAC control register */ 1000 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1001 1002 /* 1003 * Clear the MAC statistics block in the NIC's 1004 * internal memory. 1005 */ 1006 for (i = BGE_STATS_BLOCK; 1007 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1008 BGE_MEMWIN_WRITE(sc, i, 0); 1009 1010 for (i = BGE_STATUS_BLOCK; 1011 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1012 BGE_MEMWIN_WRITE(sc, i, 0); 1013 1014 /* Set up the PCI DMA control register. */ 1015 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1016 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4); 1017 1018 /* 1019 * Set up general mode register. 1020 */ 1021 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1022 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1023 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1024 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1025 BGE_MODECTL_RX_NO_PHDR_CSUM); 1026 1027 /* Get cache line size. */ 1028 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); 1029 1030 /* 1031 * Avoid violating PCI spec on certain chip revs. 1032 */ 1033 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { 1034 switch(cachesize) { 1035 case 1: 1036 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1037 BGE_PCI_WRITE_BNDRY_16BYTES, 4); 1038 break; 1039 case 2: 1040 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1041 BGE_PCI_WRITE_BNDRY_32BYTES, 4); 1042 break; 1043 case 4: 1044 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1045 BGE_PCI_WRITE_BNDRY_64BYTES, 4); 1046 break; 1047 case 8: 1048 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1049 BGE_PCI_WRITE_BNDRY_128BYTES, 4); 1050 break; 1051 case 16: 1052 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1053 BGE_PCI_WRITE_BNDRY_256BYTES, 4); 1054 break; 1055 case 32: 1056 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1057 BGE_PCI_WRITE_BNDRY_512BYTES, 4); 1058 break; 1059 case 64: 1060 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1061 BGE_PCI_WRITE_BNDRY_1024BYTES, 4); 1062 break; 1063 default: 1064 /* Disable PCI memory write and invalidate. */ 1065 if (bootverbose) 1066 printf("bge%d: cache line size %d not " 1067 "supported; disabling PCI MWI\n", 1068 sc->bge_unit, cachesize); 1069 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1070 PCIM_CMD_MWIEN, 4); 1071 break; 1072 } 1073 } 1074 1075 #ifdef __brokenalpha__ 1076 /* 1077 * Must insure that we do not cross an 8K (bytes) boundary 1078 * for DMA reads. Our highest limit is 1K bytes. This is a 1079 * restriction on some ALPHA platforms with early revision 1080 * 21174 PCI chipsets, such as the AlphaPC 164lx 1081 */ 1082 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1083 #endif 1084 1085 /* Set the timer prescaler (always 66Mhz) */ 1086 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1087 1088 return(0); 1089 } 1090 1091 static int 1092 bge_blockinit(sc) 1093 struct bge_softc *sc; 1094 { 1095 struct bge_rcb *rcb; 1096 struct bge_rcb_opaque *rcbo; 1097 int i; 1098 1099 /* 1100 * Initialize the memory window pointer register so that 1101 * we can access the first 32K of internal NIC RAM. This will 1102 * allow us to set up the TX send ring RCBs and the RX return 1103 * ring RCBs, plus other things which live in NIC memory. 1104 */ 1105 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1106 1107 /* Configure mbuf memory pool */ 1108 if (sc->bge_extram) { 1109 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1111 } else { 1112 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1113 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1114 } 1115 1116 /* Configure DMA resource pool */ 1117 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1118 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1119 1120 /* Configure mbuf pool watermarks */ 1121 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1122 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1123 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1124 1125 /* Configure DMA resource watermarks */ 1126 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1127 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1128 1129 /* Enable buffer manager */ 1130 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1131 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1132 1133 /* Poll for buffer manager start indication */ 1134 for (i = 0; i < BGE_TIMEOUT; i++) { 1135 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1136 break; 1137 DELAY(10); 1138 } 1139 1140 if (i == BGE_TIMEOUT) { 1141 printf("bge%d: buffer manager failed to start\n", 1142 sc->bge_unit); 1143 return(ENXIO); 1144 } 1145 1146 /* Enable flow-through queues */ 1147 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1148 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1149 1150 /* Wait until queue initialization is complete */ 1151 for (i = 0; i < BGE_TIMEOUT; i++) { 1152 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1153 break; 1154 DELAY(10); 1155 } 1156 1157 if (i == BGE_TIMEOUT) { 1158 printf("bge%d: flow-through queue init failed\n", 1159 sc->bge_unit); 1160 return(ENXIO); 1161 } 1162 1163 /* Initialize the standard RX ring control block */ 1164 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1165 BGE_HOSTADDR(rcb->bge_hostaddr) = 1166 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1167 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1168 if (sc->bge_extram) 1169 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1170 else 1171 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1172 rcb->bge_flags = 0; 1173 rcbo = (struct bge_rcb_opaque *)rcb; 1174 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1175 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1176 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1177 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1178 1179 /* 1180 * Initialize the jumbo RX ring control block 1181 * We set the 'ring disabled' bit in the flags 1182 * field until we're actually ready to start 1183 * using this ring (i.e. once we set the MTU 1184 * high enough to require it). 1185 */ 1186 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1187 BGE_HOSTADDR(rcb->bge_hostaddr) = 1188 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1189 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1190 if (sc->bge_extram) 1191 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1192 else 1193 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1194 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1195 1196 rcbo = (struct bge_rcb_opaque *)rcb; 1197 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1198 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1199 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1200 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1201 1202 /* Set up dummy disabled mini ring RCB */ 1203 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1204 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1205 rcbo = (struct bge_rcb_opaque *)rcb; 1206 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1207 1208 /* 1209 * Set the BD ring replentish thresholds. The recommended 1210 * values are 1/8th the number of descriptors allocated to 1211 * each ring. 1212 */ 1213 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1214 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1215 1216 /* 1217 * Disable all unused send rings by setting the 'ring disabled' 1218 * bit in the flags field of all the TX send ring control blocks. 1219 * These are located in NIC memory. 1220 */ 1221 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1222 BGE_SEND_RING_RCB); 1223 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1224 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1225 rcb->bge_max_len = 0; 1226 rcb->bge_nicaddr = 0; 1227 rcb++; 1228 } 1229 1230 /* Configure TX RCB 0 (we use only the first ring) */ 1231 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1232 BGE_SEND_RING_RCB); 1233 rcb->bge_hostaddr.bge_addr_hi = 0; 1234 BGE_HOSTADDR(rcb->bge_hostaddr) = 1235 vtophys(&sc->bge_rdata->bge_tx_ring); 1236 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1237 rcb->bge_max_len = BGE_TX_RING_CNT; 1238 rcb->bge_flags = 0; 1239 1240 /* Disable all unused RX return rings */ 1241 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1242 BGE_RX_RETURN_RING_RCB); 1243 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1244 rcb->bge_hostaddr.bge_addr_hi = 0; 1245 rcb->bge_hostaddr.bge_addr_lo = 0; 1246 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1247 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1248 rcb->bge_nicaddr = 0; 1249 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1250 (i * (sizeof(u_int64_t))), 0); 1251 rcb++; 1252 } 1253 1254 /* Initialize RX ring indexes */ 1255 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1256 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1257 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1258 1259 /* 1260 * Set up RX return ring 0 1261 * Note that the NIC address for RX return rings is 0x00000000. 1262 * The return rings live entirely within the host, so the 1263 * nicaddr field in the RCB isn't used. 1264 */ 1265 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1266 BGE_RX_RETURN_RING_RCB); 1267 rcb->bge_hostaddr.bge_addr_hi = 0; 1268 BGE_HOSTADDR(rcb->bge_hostaddr) = 1269 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1270 rcb->bge_nicaddr = 0x00000000; 1271 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1272 rcb->bge_flags = 0; 1273 1274 /* Set random backoff seed for TX */ 1275 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1276 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1277 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1278 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1279 BGE_TX_BACKOFF_SEED_MASK); 1280 1281 /* Set inter-packet gap */ 1282 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1283 1284 /* 1285 * Specify which ring to use for packets that don't match 1286 * any RX rules. 1287 */ 1288 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1289 1290 /* 1291 * Configure number of RX lists. One interrupt distribution 1292 * list, sixteen active lists, one bad frames class. 1293 */ 1294 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1295 1296 /* Inialize RX list placement stats mask. */ 1297 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1298 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1299 1300 /* Disable host coalescing until we get it set up */ 1301 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1302 1303 /* Poll to make sure it's shut down. */ 1304 for (i = 0; i < BGE_TIMEOUT; i++) { 1305 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1306 break; 1307 DELAY(10); 1308 } 1309 1310 if (i == BGE_TIMEOUT) { 1311 printf("bge%d: host coalescing engine failed to idle\n", 1312 sc->bge_unit); 1313 return(ENXIO); 1314 } 1315 1316 /* Set up host coalescing defaults */ 1317 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1318 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1319 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1320 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1321 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1322 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1323 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1324 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1325 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1326 1327 /* Set up address of statistics block */ 1328 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1329 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1330 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1331 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1332 1333 /* Set up address of status block */ 1334 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1335 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1336 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1337 vtophys(&sc->bge_rdata->bge_status_block)); 1338 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1339 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1340 1341 /* Turn on host coalescing state machine */ 1342 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1343 1344 /* Turn on RX BD completion state machine and enable attentions */ 1345 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1346 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1347 1348 /* Turn on RX list placement state machine */ 1349 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1350 1351 /* Turn on RX list selector state machine. */ 1352 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1353 1354 /* Turn on DMA, clear stats */ 1355 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1356 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1357 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1358 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1359 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1360 1361 /* Set misc. local control, enable interrupts on attentions */ 1362 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1363 1364 #ifdef notdef 1365 /* Assert GPIO pins for PHY reset */ 1366 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1367 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1368 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1369 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1370 #endif 1371 1372 /* Turn on DMA completion state machine */ 1373 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1374 1375 /* Turn on write DMA state machine */ 1376 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1377 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1378 1379 /* Turn on read DMA state machine */ 1380 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1381 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1382 1383 /* Turn on RX data completion state machine */ 1384 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1385 1386 /* Turn on RX BD initiator state machine */ 1387 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1388 1389 /* Turn on RX data and RX BD initiator state machine */ 1390 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1391 1392 /* Turn on Mbuf cluster free state machine */ 1393 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1394 1395 /* Turn on send BD completion state machine */ 1396 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1397 1398 /* Turn on send data completion state machine */ 1399 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1400 1401 /* Turn on send data initiator state machine */ 1402 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1403 1404 /* Turn on send BD initiator state machine */ 1405 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1406 1407 /* Turn on send BD selector state machine */ 1408 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1409 1410 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1411 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1412 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1413 1414 /* init LED register */ 1415 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1416 1417 /* ack/clear link change events */ 1418 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1419 BGE_MACSTAT_CFG_CHANGED); 1420 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1421 1422 /* Enable PHY auto polling (for MII/GMII only) */ 1423 if (sc->bge_tbi) { 1424 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1425 } else 1426 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1427 1428 /* Enable link state change attentions. */ 1429 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1430 1431 return(0); 1432 } 1433 1434 /* 1435 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1436 * against our list and return its name if we find a match. Note 1437 * that since the Broadcom controller contains VPD support, we 1438 * can get the device name string from the controller itself instead 1439 * of the compiled-in string. This is a little slow, but it guarantees 1440 * we'll always announce the right product name. 1441 */ 1442 static int 1443 bge_probe(dev) 1444 device_t dev; 1445 { 1446 struct bge_type *t; 1447 struct bge_softc *sc; 1448 1449 t = bge_devs; 1450 1451 sc = device_get_softc(dev); 1452 bzero(sc, sizeof(struct bge_softc)); 1453 sc->bge_unit = device_get_unit(dev); 1454 sc->bge_dev = dev; 1455 1456 while(t->bge_name != NULL) { 1457 if ((pci_get_vendor(dev) == t->bge_vid) && 1458 (pci_get_device(dev) == t->bge_did)) { 1459 #ifdef notdef 1460 bge_vpd_read(sc); 1461 device_set_desc(dev, sc->bge_vpd_prodname); 1462 #endif 1463 device_set_desc(dev, t->bge_name); 1464 return(0); 1465 } 1466 t++; 1467 } 1468 1469 return(ENXIO); 1470 } 1471 1472 static int 1473 bge_attach(dev) 1474 device_t dev; 1475 { 1476 int s; 1477 u_int32_t command; 1478 struct ifnet *ifp; 1479 struct bge_softc *sc; 1480 int unit, error = 0, rid; 1481 1482 s = splimp(); 1483 1484 sc = device_get_softc(dev); 1485 unit = device_get_unit(dev); 1486 sc->bge_dev = dev; 1487 sc->bge_unit = unit; 1488 1489 /* 1490 * Map control/status registers. 1491 */ 1492 pci_enable_busmaster(dev); 1493 pci_enable_io(dev, SYS_RES_MEMORY); 1494 command = pci_read_config(dev, PCIR_COMMAND, 4); 1495 1496 if (!(command & PCIM_CMD_MEMEN)) { 1497 printf("bge%d: failed to enable memory mapping!\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 rid = BGE_PCI_BAR0; 1503 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1504 0, ~0, 1, RF_ACTIVE); 1505 1506 if (sc->bge_res == NULL) { 1507 printf ("bge%d: couldn't map memory\n", unit); 1508 error = ENXIO; 1509 goto fail; 1510 } 1511 1512 sc->bge_btag = rman_get_bustag(sc->bge_res); 1513 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1514 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1515 1516 /* 1517 * XXX FIXME: rman_get_virtual() on the alpha is currently 1518 * broken and returns a physical address instead of a kernel 1519 * virtual address. Consequently, we need to do a little 1520 * extra mangling of the vhandle on the alpha. This should 1521 * eventually be fixed! The whole idea here is to get rid 1522 * of platform dependencies. 1523 */ 1524 #ifdef __alpha__ 1525 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1526 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1527 else 1528 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1529 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1530 #endif 1531 1532 /* Allocate interrupt */ 1533 rid = 0; 1534 1535 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1536 RF_SHAREABLE | RF_ACTIVE); 1537 1538 if (sc->bge_irq == NULL) { 1539 printf("bge%d: couldn't map interrupt\n", unit); 1540 error = ENXIO; 1541 goto fail; 1542 } 1543 1544 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1545 bge_intr, sc, &sc->bge_intrhand); 1546 1547 if (error) { 1548 bge_release_resources(sc); 1549 printf("bge%d: couldn't set up irq\n", unit); 1550 goto fail; 1551 } 1552 1553 sc->bge_unit = unit; 1554 1555 /* Try to reset the chip. */ 1556 bge_reset(sc); 1557 1558 if (bge_chipinit(sc)) { 1559 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1560 bge_release_resources(sc); 1561 error = ENXIO; 1562 goto fail; 1563 } 1564 1565 /* 1566 * Get station address from the EEPROM. 1567 */ 1568 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1569 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1570 printf("bge%d: failed to read station address\n", unit); 1571 bge_release_resources(sc); 1572 error = ENXIO; 1573 goto fail; 1574 } 1575 1576 /* 1577 * A Broadcom chip was detected. Inform the world. 1578 */ 1579 printf("bge%d: Ethernet address: %6D\n", unit, 1580 sc->arpcom.ac_enaddr, ":"); 1581 1582 /* Allocate the general information block and ring buffers. */ 1583 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1584 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1585 1586 if (sc->bge_rdata == NULL) { 1587 bge_release_resources(sc); 1588 error = ENXIO; 1589 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1590 goto fail; 1591 } 1592 1593 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1594 1595 /* Try to allocate memory for jumbo buffers. */ 1596 if (bge_alloc_jumbo_mem(sc)) { 1597 printf("bge%d: jumbo buffer allocation " 1598 "failed\n", sc->bge_unit); 1599 bge_release_resources(sc); 1600 error = ENXIO; 1601 goto fail; 1602 } 1603 1604 /* Set default tuneable values. */ 1605 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1606 sc->bge_rx_coal_ticks = 150; 1607 sc->bge_tx_coal_ticks = 150; 1608 sc->bge_rx_max_coal_bds = 64; 1609 sc->bge_tx_max_coal_bds = 128; 1610 1611 /* Set up ifnet structure */ 1612 ifp = &sc->arpcom.ac_if; 1613 ifp->if_softc = sc; 1614 ifp->if_unit = sc->bge_unit; 1615 ifp->if_name = "bge"; 1616 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1617 ifp->if_ioctl = bge_ioctl; 1618 ifp->if_output = ether_output; 1619 ifp->if_start = bge_start; 1620 ifp->if_watchdog = bge_watchdog; 1621 ifp->if_init = bge_init; 1622 ifp->if_mtu = ETHERMTU; 1623 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1624 ifp->if_hwassist = BGE_CSUM_FEATURES; 1625 ifp->if_capabilities = IFCAP_HWCSUM; 1626 ifp->if_capenable = ifp->if_capabilities; 1627 1628 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1629 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1630 sc->bge_tbi = 1; 1631 1632 if (sc->bge_tbi) { 1633 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1634 bge_ifmedia_upd, bge_ifmedia_sts); 1635 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1636 ifmedia_add(&sc->bge_ifmedia, 1637 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1638 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1639 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1640 } else { 1641 /* 1642 * Do transceiver setup. 1643 */ 1644 if (mii_phy_probe(dev, &sc->bge_miibus, 1645 bge_ifmedia_upd, bge_ifmedia_sts)) { 1646 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1647 bge_release_resources(sc); 1648 bge_free_jumbo_mem(sc); 1649 error = ENXIO; 1650 goto fail; 1651 } 1652 } 1653 1654 /* 1655 * Call MI attach routine. 1656 */ 1657 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1658 callout_handle_init(&sc->bge_stat_ch); 1659 1660 fail: 1661 splx(s); 1662 1663 return(error); 1664 } 1665 1666 static int 1667 bge_detach(dev) 1668 device_t dev; 1669 { 1670 struct bge_softc *sc; 1671 struct ifnet *ifp; 1672 int s; 1673 1674 s = splimp(); 1675 1676 sc = device_get_softc(dev); 1677 ifp = &sc->arpcom.ac_if; 1678 1679 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1680 bge_stop(sc); 1681 bge_reset(sc); 1682 1683 if (sc->bge_tbi) { 1684 ifmedia_removeall(&sc->bge_ifmedia); 1685 } else { 1686 bus_generic_detach(dev); 1687 device_delete_child(dev, sc->bge_miibus); 1688 } 1689 1690 bge_release_resources(sc); 1691 bge_free_jumbo_mem(sc); 1692 1693 splx(s); 1694 1695 return(0); 1696 } 1697 1698 static void 1699 bge_release_resources(sc) 1700 struct bge_softc *sc; 1701 { 1702 device_t dev; 1703 1704 dev = sc->bge_dev; 1705 1706 if (sc->bge_vpd_prodname != NULL) 1707 free(sc->bge_vpd_prodname, M_DEVBUF); 1708 1709 if (sc->bge_vpd_readonly != NULL) 1710 free(sc->bge_vpd_readonly, M_DEVBUF); 1711 1712 if (sc->bge_intrhand != NULL) 1713 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1714 1715 if (sc->bge_irq != NULL) 1716 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1717 1718 if (sc->bge_res != NULL) 1719 bus_release_resource(dev, SYS_RES_MEMORY, 1720 BGE_PCI_BAR0, sc->bge_res); 1721 1722 if (sc->bge_rdata != NULL) 1723 contigfree(sc->bge_rdata, 1724 sizeof(struct bge_ring_data), M_DEVBUF); 1725 1726 return; 1727 } 1728 1729 static void 1730 bge_reset(sc) 1731 struct bge_softc *sc; 1732 { 1733 device_t dev; 1734 u_int32_t cachesize, command, pcistate; 1735 int i, val = 0; 1736 1737 dev = sc->bge_dev; 1738 1739 /* Save some important PCI state. */ 1740 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1741 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1742 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1743 1744 pci_write_config(dev, BGE_PCI_MISC_CTL, 1745 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1746 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1747 1748 /* Issue global reset */ 1749 bge_writereg_ind(sc, BGE_MISC_CFG, 1750 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1751 1752 DELAY(1000); 1753 1754 /* Reset some of the PCI state that got zapped by reset */ 1755 pci_write_config(dev, BGE_PCI_MISC_CTL, 1756 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1757 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1758 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1759 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1760 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1761 1762 /* 1763 * Prevent PXE restart: write a magic number to the 1764 * general communications memory at 0xB50. 1765 */ 1766 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1767 /* 1768 * Poll the value location we just wrote until 1769 * we see the 1's complement of the magic number. 1770 * This indicates that the firmware initialization 1771 * is complete. 1772 */ 1773 for (i = 0; i < BGE_TIMEOUT; i++) { 1774 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1775 if (val == ~BGE_MAGIC_NUMBER) 1776 break; 1777 DELAY(10); 1778 } 1779 1780 if (i == BGE_TIMEOUT) { 1781 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1782 return; 1783 } 1784 1785 /* 1786 * XXX Wait for the value of the PCISTATE register to 1787 * return to its original pre-reset state. This is a 1788 * fairly good indicator of reset completion. If we don't 1789 * wait for the reset to fully complete, trying to read 1790 * from the device's non-PCI registers may yield garbage 1791 * results. 1792 */ 1793 for (i = 0; i < BGE_TIMEOUT; i++) { 1794 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1795 break; 1796 DELAY(10); 1797 } 1798 1799 /* Enable memory arbiter. */ 1800 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1801 1802 /* Fix up byte swapping */ 1803 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1804 BGE_MODECTL_BYTESWAP_DATA); 1805 1806 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1807 1808 DELAY(10000); 1809 1810 return; 1811 } 1812 1813 /* 1814 * Frame reception handling. This is called if there's a frame 1815 * on the receive return list. 1816 * 1817 * Note: we have to be able to handle two possibilities here: 1818 * 1) the frame is from the jumbo recieve ring 1819 * 2) the frame is from the standard receive ring 1820 */ 1821 1822 static void 1823 bge_rxeof(sc) 1824 struct bge_softc *sc; 1825 { 1826 struct ifnet *ifp; 1827 int stdcnt = 0, jumbocnt = 0; 1828 1829 ifp = &sc->arpcom.ac_if; 1830 1831 while(sc->bge_rx_saved_considx != 1832 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1833 struct bge_rx_bd *cur_rx; 1834 u_int32_t rxidx; 1835 struct ether_header *eh; 1836 struct mbuf *m = NULL; 1837 u_int16_t vlan_tag = 0; 1838 int have_tag = 0; 1839 1840 cur_rx = 1841 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1842 1843 rxidx = cur_rx->bge_idx; 1844 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1845 1846 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1847 have_tag = 1; 1848 vlan_tag = cur_rx->bge_vlan_tag; 1849 } 1850 1851 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1852 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1853 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1854 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1855 jumbocnt++; 1856 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1857 ifp->if_ierrors++; 1858 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1859 continue; 1860 } 1861 if (bge_newbuf_jumbo(sc, 1862 sc->bge_jumbo, NULL) == ENOBUFS) { 1863 ifp->if_ierrors++; 1864 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1865 continue; 1866 } 1867 } else { 1868 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1869 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1870 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1871 stdcnt++; 1872 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1873 ifp->if_ierrors++; 1874 bge_newbuf_std(sc, sc->bge_std, m); 1875 continue; 1876 } 1877 if (bge_newbuf_std(sc, sc->bge_std, 1878 NULL) == ENOBUFS) { 1879 ifp->if_ierrors++; 1880 bge_newbuf_std(sc, sc->bge_std, m); 1881 continue; 1882 } 1883 } 1884 1885 ifp->if_ipackets++; 1886 eh = mtod(m, struct ether_header *); 1887 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1888 m->m_pkthdr.rcvif = ifp; 1889 1890 /* Remove header from mbuf and pass it on. */ 1891 m_adj(m, sizeof(struct ether_header)); 1892 1893 if (ifp->if_hwassist) { 1894 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1895 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1896 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1897 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1898 m->m_pkthdr.csum_data = 1899 cur_rx->bge_tcp_udp_csum; 1900 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1901 } 1902 } 1903 1904 /* 1905 * If we received a packet with a vlan tag, pass it 1906 * to vlan_input() instead of ether_input(). 1907 */ 1908 if (have_tag) { 1909 VLAN_INPUT_TAG(ifp, eh, m, vlan_tag); 1910 have_tag = vlan_tag = 0; 1911 continue; 1912 } 1913 1914 ether_input(ifp, eh, m); 1915 } 1916 1917 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1918 if (stdcnt) 1919 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1920 if (jumbocnt) 1921 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1922 1923 return; 1924 } 1925 1926 static void 1927 bge_txeof(sc) 1928 struct bge_softc *sc; 1929 { 1930 struct bge_tx_bd *cur_tx = NULL; 1931 struct ifnet *ifp; 1932 1933 ifp = &sc->arpcom.ac_if; 1934 1935 /* 1936 * Go through our tx ring and free mbufs for those 1937 * frames that have been sent. 1938 */ 1939 while (sc->bge_tx_saved_considx != 1940 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1941 u_int32_t idx = 0; 1942 1943 idx = sc->bge_tx_saved_considx; 1944 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1945 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1946 ifp->if_opackets++; 1947 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1948 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1949 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1950 } 1951 sc->bge_txcnt--; 1952 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1953 ifp->if_timer = 0; 1954 } 1955 1956 if (cur_tx != NULL) 1957 ifp->if_flags &= ~IFF_OACTIVE; 1958 1959 return; 1960 } 1961 1962 static void 1963 bge_intr(xsc) 1964 void *xsc; 1965 { 1966 struct bge_softc *sc; 1967 struct ifnet *ifp; 1968 1969 sc = xsc; 1970 ifp = &sc->arpcom.ac_if; 1971 1972 #ifdef notdef 1973 /* Avoid this for now -- checking this register is expensive. */ 1974 /* Make sure this is really our interrupt. */ 1975 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1976 return; 1977 #endif 1978 /* Ack interrupt and stop others from occuring. */ 1979 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 1980 1981 /* Process link state changes. */ 1982 if (sc->bge_rdata->bge_status_block.bge_status & 1983 BGE_STATFLAG_LINKSTATE_CHANGED) { 1984 sc->bge_link = 0; 1985 untimeout(bge_tick, sc, sc->bge_stat_ch); 1986 bge_tick(sc); 1987 /* ack the event to clear/reset it */ 1988 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1989 BGE_MACSTAT_CFG_CHANGED); 1990 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1991 } 1992 1993 if (ifp->if_flags & IFF_RUNNING) { 1994 /* Check RX return ring producer/consumer */ 1995 bge_rxeof(sc); 1996 1997 /* Check TX ring producer/consumer */ 1998 bge_txeof(sc); 1999 } 2000 2001 bge_handle_events(sc); 2002 2003 /* Re-enable interrupts. */ 2004 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2005 2006 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2007 bge_start(ifp); 2008 2009 return; 2010 } 2011 2012 static void 2013 bge_tick(xsc) 2014 void *xsc; 2015 { 2016 struct bge_softc *sc; 2017 struct mii_data *mii = NULL; 2018 struct ifmedia *ifm = NULL; 2019 struct ifnet *ifp; 2020 int s; 2021 2022 sc = xsc; 2023 ifp = &sc->arpcom.ac_if; 2024 2025 s = splimp(); 2026 2027 bge_stats_update(sc); 2028 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2029 if (sc->bge_link) 2030 return; 2031 2032 if (sc->bge_tbi) { 2033 ifm = &sc->bge_ifmedia; 2034 if (CSR_READ_4(sc, BGE_MAC_STS) & 2035 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2036 sc->bge_link++; 2037 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2038 printf("bge%d: gigabit link up\n", sc->bge_unit); 2039 if (ifp->if_snd.ifq_head != NULL) 2040 bge_start(ifp); 2041 } 2042 return; 2043 } 2044 2045 mii = device_get_softc(sc->bge_miibus); 2046 mii_tick(mii); 2047 2048 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2049 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2050 sc->bge_link++; 2051 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2052 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2053 printf("bge%d: gigabit link up\n", 2054 sc->bge_unit); 2055 if (ifp->if_snd.ifq_head != NULL) 2056 bge_start(ifp); 2057 } 2058 2059 splx(s); 2060 2061 return; 2062 } 2063 2064 static void 2065 bge_stats_update(sc) 2066 struct bge_softc *sc; 2067 { 2068 struct ifnet *ifp; 2069 struct bge_stats *stats; 2070 2071 ifp = &sc->arpcom.ac_if; 2072 2073 stats = (struct bge_stats *)(sc->bge_vhandle + 2074 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2075 2076 ifp->if_collisions += 2077 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2078 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2079 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2080 stats->dot3StatsLateCollisions.bge_addr_lo) - 2081 ifp->if_collisions; 2082 2083 #ifdef notdef 2084 ifp->if_collisions += 2085 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2086 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2087 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2088 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2089 ifp->if_collisions; 2090 #endif 2091 2092 return; 2093 } 2094 2095 /* 2096 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2097 * pointers to descriptors. 2098 */ 2099 static int 2100 bge_encap(sc, m_head, txidx) 2101 struct bge_softc *sc; 2102 struct mbuf *m_head; 2103 u_int32_t *txidx; 2104 { 2105 struct bge_tx_bd *f = NULL; 2106 struct mbuf *m; 2107 u_int32_t frag, cur, cnt = 0; 2108 u_int16_t csum_flags = 0; 2109 struct ifvlan *ifv = NULL; 2110 2111 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2112 m_head->m_pkthdr.rcvif != NULL && 2113 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2114 ifv = m_head->m_pkthdr.rcvif->if_softc; 2115 2116 m = m_head; 2117 cur = frag = *txidx; 2118 2119 if (m_head->m_pkthdr.csum_flags) { 2120 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2121 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2122 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2123 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2124 if (m_head->m_flags & M_LASTFRAG) 2125 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2126 else if (m_head->m_flags & M_FRAG) 2127 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2128 } 2129 2130 /* 2131 * Start packing the mbufs in this chain into 2132 * the fragment pointers. Stop when we run out 2133 * of fragments or hit the end of the mbuf chain. 2134 */ 2135 for (m = m_head; m != NULL; m = m->m_next) { 2136 if (m->m_len != 0) { 2137 f = &sc->bge_rdata->bge_tx_ring[frag]; 2138 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2139 break; 2140 BGE_HOSTADDR(f->bge_addr) = 2141 vtophys(mtod(m, vm_offset_t)); 2142 f->bge_len = m->m_len; 2143 f->bge_flags = csum_flags; 2144 if (ifv != NULL) { 2145 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2146 f->bge_vlan_tag = ifv->ifv_tag; 2147 } else { 2148 f->bge_vlan_tag = 0; 2149 } 2150 /* 2151 * Sanity check: avoid coming within 16 descriptors 2152 * of the end of the ring. 2153 */ 2154 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2155 return(ENOBUFS); 2156 cur = frag; 2157 BGE_INC(frag, BGE_TX_RING_CNT); 2158 cnt++; 2159 } 2160 } 2161 2162 if (m != NULL) 2163 return(ENOBUFS); 2164 2165 if (frag == sc->bge_tx_saved_considx) 2166 return(ENOBUFS); 2167 2168 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2169 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2170 sc->bge_txcnt += cnt; 2171 2172 *txidx = frag; 2173 2174 return(0); 2175 } 2176 2177 /* 2178 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2179 * to the mbuf data regions directly in the transmit descriptors. 2180 */ 2181 static void 2182 bge_start(ifp) 2183 struct ifnet *ifp; 2184 { 2185 struct bge_softc *sc; 2186 struct mbuf *m_head = NULL; 2187 u_int32_t prodidx = 0; 2188 2189 sc = ifp->if_softc; 2190 2191 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2192 return; 2193 2194 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2195 2196 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2197 IF_DEQUEUE(&ifp->if_snd, m_head); 2198 if (m_head == NULL) 2199 break; 2200 2201 /* 2202 * XXX 2203 * safety overkill. If this is a fragmented packet chain 2204 * with delayed TCP/UDP checksums, then only encapsulate 2205 * it if we have enough descriptors to handle the entire 2206 * chain at once. 2207 * (paranoia -- may not actually be needed) 2208 */ 2209 if (m_head->m_flags & M_FIRSTFRAG && 2210 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2211 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2212 m_head->m_pkthdr.csum_data + 16) { 2213 IF_PREPEND(&ifp->if_snd, m_head); 2214 ifp->if_flags |= IFF_OACTIVE; 2215 break; 2216 } 2217 } 2218 2219 /* 2220 * Pack the data into the transmit ring. If we 2221 * don't have room, set the OACTIVE flag and wait 2222 * for the NIC to drain the ring. 2223 */ 2224 if (bge_encap(sc, m_head, &prodidx)) { 2225 IF_PREPEND(&ifp->if_snd, m_head); 2226 ifp->if_flags |= IFF_OACTIVE; 2227 break; 2228 } 2229 2230 /* 2231 * If there's a BPF listener, bounce a copy of this frame 2232 * to him. 2233 */ 2234 if (ifp->if_bpf) 2235 bpf_mtap(ifp, m_head); 2236 } 2237 2238 /* Transmit */ 2239 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2240 2241 /* 2242 * Set a timeout in case the chip goes out to lunch. 2243 */ 2244 ifp->if_timer = 5; 2245 2246 return; 2247 } 2248 2249 /* 2250 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2251 * program its internal DSP. Failing to do this can result in 2252 * massive packet loss at 1Gb speeds. 2253 */ 2254 static void 2255 bge_phy_hack(sc) 2256 struct bge_softc *sc; 2257 { 2258 struct bge_bcom_hack bhack[] = { 2259 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2260 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2261 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2262 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2263 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2264 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2265 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2266 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2267 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2268 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2269 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2270 { 0, 0 } }; 2271 u_int16_t vid, did; 2272 int i; 2273 2274 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2275 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2276 2277 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2278 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2279 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2280 i = 0; 2281 while(bhack[i].reg) { 2282 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2283 bhack[i].val); 2284 i++; 2285 } 2286 } 2287 2288 return; 2289 } 2290 2291 static void 2292 bge_init(xsc) 2293 void *xsc; 2294 { 2295 struct bge_softc *sc = xsc; 2296 struct ifnet *ifp; 2297 u_int16_t *m; 2298 int s; 2299 2300 s = splimp(); 2301 2302 ifp = &sc->arpcom.ac_if; 2303 2304 if (ifp->if_flags & IFF_RUNNING) 2305 return; 2306 2307 /* Cancel pending I/O and flush buffers. */ 2308 bge_stop(sc); 2309 bge_reset(sc); 2310 bge_chipinit(sc); 2311 2312 /* 2313 * Init the various state machines, ring 2314 * control blocks and firmware. 2315 */ 2316 if (bge_blockinit(sc)) { 2317 printf("bge%d: initialization failure\n", sc->bge_unit); 2318 splx(s); 2319 return; 2320 } 2321 2322 ifp = &sc->arpcom.ac_if; 2323 2324 /* Specify MTU. */ 2325 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2326 ETHER_HDR_LEN + ETHER_CRC_LEN); 2327 2328 /* Load our MAC address. */ 2329 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2330 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2331 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2332 2333 /* Enable or disable promiscuous mode as needed. */ 2334 if (ifp->if_flags & IFF_PROMISC) { 2335 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2336 } else { 2337 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2338 } 2339 2340 /* Program multicast filter. */ 2341 bge_setmulti(sc); 2342 2343 /* Init RX ring. */ 2344 bge_init_rx_ring_std(sc); 2345 2346 /* Init jumbo RX ring. */ 2347 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2348 bge_init_rx_ring_jumbo(sc); 2349 2350 /* Init our RX return ring index */ 2351 sc->bge_rx_saved_considx = 0; 2352 2353 /* Init TX ring. */ 2354 bge_init_tx_ring(sc); 2355 2356 /* Turn on transmitter */ 2357 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2358 2359 /* Turn on receiver */ 2360 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2361 2362 /* Tell firmware we're alive. */ 2363 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2364 2365 /* Enable host interrupts. */ 2366 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2367 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2368 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2369 2370 bge_ifmedia_upd(ifp); 2371 2372 ifp->if_flags |= IFF_RUNNING; 2373 ifp->if_flags &= ~IFF_OACTIVE; 2374 2375 splx(s); 2376 2377 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2378 2379 return; 2380 } 2381 2382 /* 2383 * Set media options. 2384 */ 2385 static int 2386 bge_ifmedia_upd(ifp) 2387 struct ifnet *ifp; 2388 { 2389 struct bge_softc *sc; 2390 struct mii_data *mii; 2391 struct ifmedia *ifm; 2392 2393 sc = ifp->if_softc; 2394 ifm = &sc->bge_ifmedia; 2395 2396 /* If this is a 1000baseX NIC, enable the TBI port. */ 2397 if (sc->bge_tbi) { 2398 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2399 return(EINVAL); 2400 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2401 case IFM_AUTO: 2402 break; 2403 case IFM_1000_SX: 2404 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2405 BGE_CLRBIT(sc, BGE_MAC_MODE, 2406 BGE_MACMODE_HALF_DUPLEX); 2407 } else { 2408 BGE_SETBIT(sc, BGE_MAC_MODE, 2409 BGE_MACMODE_HALF_DUPLEX); 2410 } 2411 break; 2412 default: 2413 return(EINVAL); 2414 } 2415 return(0); 2416 } 2417 2418 mii = device_get_softc(sc->bge_miibus); 2419 sc->bge_link = 0; 2420 if (mii->mii_instance) { 2421 struct mii_softc *miisc; 2422 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2423 miisc = LIST_NEXT(miisc, mii_list)) 2424 mii_phy_reset(miisc); 2425 } 2426 bge_phy_hack(sc); 2427 mii_mediachg(mii); 2428 2429 return(0); 2430 } 2431 2432 /* 2433 * Report current media status. 2434 */ 2435 static void 2436 bge_ifmedia_sts(ifp, ifmr) 2437 struct ifnet *ifp; 2438 struct ifmediareq *ifmr; 2439 { 2440 struct bge_softc *sc; 2441 struct mii_data *mii; 2442 2443 sc = ifp->if_softc; 2444 2445 if (sc->bge_tbi) { 2446 ifmr->ifm_status = IFM_AVALID; 2447 ifmr->ifm_active = IFM_ETHER; 2448 if (CSR_READ_4(sc, BGE_MAC_STS) & 2449 BGE_MACSTAT_TBI_PCS_SYNCHED) 2450 ifmr->ifm_status |= IFM_ACTIVE; 2451 ifmr->ifm_active |= IFM_1000_SX; 2452 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2453 ifmr->ifm_active |= IFM_HDX; 2454 else 2455 ifmr->ifm_active |= IFM_FDX; 2456 return; 2457 } 2458 2459 mii = device_get_softc(sc->bge_miibus); 2460 mii_pollstat(mii); 2461 ifmr->ifm_active = mii->mii_media_active; 2462 ifmr->ifm_status = mii->mii_media_status; 2463 2464 return; 2465 } 2466 2467 static int 2468 bge_ioctl(ifp, command, data) 2469 struct ifnet *ifp; 2470 u_long command; 2471 caddr_t data; 2472 { 2473 struct bge_softc *sc = ifp->if_softc; 2474 struct ifreq *ifr = (struct ifreq *) data; 2475 int s, mask, error = 0; 2476 struct mii_data *mii; 2477 2478 s = splimp(); 2479 2480 switch(command) { 2481 case SIOCSIFADDR: 2482 case SIOCGIFADDR: 2483 error = ether_ioctl(ifp, command, data); 2484 break; 2485 case SIOCSIFMTU: 2486 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2487 error = EINVAL; 2488 else { 2489 ifp->if_mtu = ifr->ifr_mtu; 2490 ifp->if_flags &= ~IFF_RUNNING; 2491 bge_init(sc); 2492 } 2493 break; 2494 case SIOCSIFFLAGS: 2495 if (ifp->if_flags & IFF_UP) { 2496 /* 2497 * If only the state of the PROMISC flag changed, 2498 * then just use the 'set promisc mode' command 2499 * instead of reinitializing the entire NIC. Doing 2500 * a full re-init means reloading the firmware and 2501 * waiting for it to start up, which may take a 2502 * second or two. 2503 */ 2504 if (ifp->if_flags & IFF_RUNNING && 2505 ifp->if_flags & IFF_PROMISC && 2506 !(sc->bge_if_flags & IFF_PROMISC)) { 2507 BGE_SETBIT(sc, BGE_RX_MODE, 2508 BGE_RXMODE_RX_PROMISC); 2509 } else if (ifp->if_flags & IFF_RUNNING && 2510 !(ifp->if_flags & IFF_PROMISC) && 2511 sc->bge_if_flags & IFF_PROMISC) { 2512 BGE_CLRBIT(sc, BGE_RX_MODE, 2513 BGE_RXMODE_RX_PROMISC); 2514 } else 2515 bge_init(sc); 2516 } else { 2517 if (ifp->if_flags & IFF_RUNNING) { 2518 bge_stop(sc); 2519 } 2520 } 2521 sc->bge_if_flags = ifp->if_flags; 2522 error = 0; 2523 break; 2524 case SIOCADDMULTI: 2525 case SIOCDELMULTI: 2526 if (ifp->if_flags & IFF_RUNNING) { 2527 bge_setmulti(sc); 2528 error = 0; 2529 } 2530 break; 2531 case SIOCSIFMEDIA: 2532 case SIOCGIFMEDIA: 2533 if (sc->bge_tbi) { 2534 error = ifmedia_ioctl(ifp, ifr, 2535 &sc->bge_ifmedia, command); 2536 } else { 2537 mii = device_get_softc(sc->bge_miibus); 2538 error = ifmedia_ioctl(ifp, ifr, 2539 &mii->mii_media, command); 2540 } 2541 break; 2542 case SIOCSIFCAP: 2543 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2544 if (mask & IFCAP_HWCSUM) { 2545 if (IFCAP_HWCSUM & ifp->if_capenable) 2546 ifp->if_capenable &= ~IFCAP_HWCSUM; 2547 else 2548 ifp->if_capenable |= IFCAP_HWCSUM; 2549 } 2550 error = 0; 2551 break; 2552 default: 2553 error = EINVAL; 2554 break; 2555 } 2556 2557 (void)splx(s); 2558 2559 return(error); 2560 } 2561 2562 static void 2563 bge_watchdog(ifp) 2564 struct ifnet *ifp; 2565 { 2566 struct bge_softc *sc; 2567 2568 sc = ifp->if_softc; 2569 2570 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2571 2572 ifp->if_flags &= ~IFF_RUNNING; 2573 bge_init(sc); 2574 2575 ifp->if_oerrors++; 2576 2577 return; 2578 } 2579 2580 /* 2581 * Stop the adapter and free any mbufs allocated to the 2582 * RX and TX lists. 2583 */ 2584 static void 2585 bge_stop(sc) 2586 struct bge_softc *sc; 2587 { 2588 struct ifnet *ifp; 2589 struct ifmedia_entry *ifm; 2590 struct mii_data *mii = NULL; 2591 int mtmp, itmp; 2592 2593 ifp = &sc->arpcom.ac_if; 2594 2595 if (!sc->bge_tbi) 2596 mii = device_get_softc(sc->bge_miibus); 2597 2598 untimeout(bge_tick, sc, sc->bge_stat_ch); 2599 2600 /* 2601 * Disable all of the receiver blocks 2602 */ 2603 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2604 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2605 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2606 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2607 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2608 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2609 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2610 2611 /* 2612 * Disable all of the transmit blocks 2613 */ 2614 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2615 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2616 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2617 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2618 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2619 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2620 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2621 2622 /* 2623 * Shut down all of the memory managers and related 2624 * state machines. 2625 */ 2626 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2627 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2628 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2629 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2630 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2631 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2632 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2633 2634 /* Disable host interrupts. */ 2635 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2636 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2637 2638 /* 2639 * Tell firmware we're shutting down. 2640 */ 2641 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2642 2643 /* Free the RX lists. */ 2644 bge_free_rx_ring_std(sc); 2645 2646 /* Free jumbo RX list. */ 2647 bge_free_rx_ring_jumbo(sc); 2648 2649 /* Free TX buffers. */ 2650 bge_free_tx_ring(sc); 2651 2652 /* 2653 * Isolate/power down the PHY, but leave the media selection 2654 * unchanged so that things will be put back to normal when 2655 * we bring the interface back up. 2656 */ 2657 if (!sc->bge_tbi) { 2658 itmp = ifp->if_flags; 2659 ifp->if_flags |= IFF_UP; 2660 ifm = mii->mii_media.ifm_cur; 2661 mtmp = ifm->ifm_media; 2662 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2663 mii_mediachg(mii); 2664 ifm->ifm_media = mtmp; 2665 ifp->if_flags = itmp; 2666 } 2667 2668 sc->bge_link = 0; 2669 2670 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2671 2672 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2673 2674 return; 2675 } 2676 2677 /* 2678 * Stop all chip I/O so that the kernel's probe routines don't 2679 * get confused by errant DMAs when rebooting. 2680 */ 2681 static void 2682 bge_shutdown(dev) 2683 device_t dev; 2684 { 2685 struct bge_softc *sc; 2686 2687 sc = device_get_softc(dev); 2688 2689 bge_stop(sc); 2690 bge_reset(sc); 2691 2692 return; 2693 } 2694