1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 217 218 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 219 220 { TC_VENDORID, TC_DEVICEID_3C996 }, 221 222 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 224 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 225 226 { 0, 0 } 227 }; 228 229 static const struct bge_vendor { 230 uint16_t v_id; 231 const char *v_name; 232 } bge_vendors[] = { 233 { ALTEON_VENDORID, "Alteon" }, 234 { ALTIMA_VENDORID, "Altima" }, 235 { APPLE_VENDORID, "Apple" }, 236 { BCOM_VENDORID, "Broadcom" }, 237 { SK_VENDORID, "SysKonnect" }, 238 { TC_VENDORID, "3Com" }, 239 { FJTSU_VENDORID, "Fujitsu" }, 240 241 { 0, NULL } 242 }; 243 244 static const struct bge_revision { 245 uint32_t br_chipid; 246 const char *br_name; 247 } bge_revisions[] = { 248 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 249 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 250 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 251 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 252 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 253 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 254 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 255 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 256 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 257 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 258 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 259 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 260 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 261 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 262 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 263 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 264 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 265 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 266 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 267 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 268 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 269 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 270 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 271 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 272 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 273 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 274 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 275 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 276 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 277 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 278 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 279 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 280 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 281 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 282 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 283 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 284 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 285 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 286 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 287 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 288 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 289 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 290 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 291 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 292 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 293 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 294 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 295 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 296 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 297 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 298 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 299 /* 5754 and 5787 share the same ASIC ID */ 300 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 301 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 302 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 303 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 304 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 305 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 306 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 307 308 { 0, NULL } 309 }; 310 311 /* 312 * Some defaults for major revisions, so that newer steppings 313 * that we don't know about have a shot at working. 314 */ 315 static const struct bge_revision bge_majorrevs[] = { 316 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 317 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 318 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 319 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 320 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 321 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 322 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 323 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 324 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 325 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 326 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 327 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 328 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 329 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 330 /* 5754 and 5787 share the same ASIC ID */ 331 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 332 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 333 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 334 335 { 0, NULL } 336 }; 337 338 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 339 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 340 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 341 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 342 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 343 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 344 345 const struct bge_revision * bge_lookup_rev(uint32_t); 346 const struct bge_vendor * bge_lookup_vendor(uint16_t); 347 348 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 349 350 static int bge_probe(device_t); 351 static int bge_attach(device_t); 352 static int bge_detach(device_t); 353 static int bge_suspend(device_t); 354 static int bge_resume(device_t); 355 static void bge_release_resources(struct bge_softc *); 356 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 357 static int bge_dma_alloc(device_t); 358 static void bge_dma_free(struct bge_softc *); 359 360 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 361 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 362 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 363 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 364 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 365 366 static void bge_txeof(struct bge_softc *, uint16_t); 367 static int bge_rxeof(struct bge_softc *, uint16_t, int); 368 369 static void bge_asf_driver_up (struct bge_softc *); 370 static void bge_tick(void *); 371 static void bge_stats_update(struct bge_softc *); 372 static void bge_stats_update_regs(struct bge_softc *); 373 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 374 uint16_t *); 375 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 376 377 static void bge_intr(void *); 378 static int bge_msi_intr(void *); 379 static void bge_intr_task(void *, int); 380 static void bge_start_locked(struct ifnet *); 381 static void bge_start(struct ifnet *); 382 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 383 static void bge_init_locked(struct bge_softc *); 384 static void bge_init(void *); 385 static void bge_stop(struct bge_softc *); 386 static void bge_watchdog(struct bge_softc *); 387 static int bge_shutdown(device_t); 388 static int bge_ifmedia_upd_locked(struct ifnet *); 389 static int bge_ifmedia_upd(struct ifnet *); 390 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 391 392 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 393 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 394 395 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 396 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 397 398 static void bge_setpromisc(struct bge_softc *); 399 static void bge_setmulti(struct bge_softc *); 400 static void bge_setvlan(struct bge_softc *); 401 402 static int bge_newbuf_std(struct bge_softc *, int); 403 static int bge_newbuf_jumbo(struct bge_softc *, int); 404 static int bge_init_rx_ring_std(struct bge_softc *); 405 static void bge_free_rx_ring_std(struct bge_softc *); 406 static int bge_init_rx_ring_jumbo(struct bge_softc *); 407 static void bge_free_rx_ring_jumbo(struct bge_softc *); 408 static void bge_free_tx_ring(struct bge_softc *); 409 static int bge_init_tx_ring(struct bge_softc *); 410 411 static int bge_chipinit(struct bge_softc *); 412 static int bge_blockinit(struct bge_softc *); 413 414 static int bge_has_eaddr(struct bge_softc *); 415 static uint32_t bge_readmem_ind(struct bge_softc *, int); 416 static void bge_writemem_ind(struct bge_softc *, int, int); 417 static void bge_writembx(struct bge_softc *, int, int); 418 #ifdef notdef 419 static uint32_t bge_readreg_ind(struct bge_softc *, int); 420 #endif 421 static void bge_writemem_direct(struct bge_softc *, int, int); 422 static void bge_writereg_ind(struct bge_softc *, int, int); 423 static void bge_set_max_readrq(struct bge_softc *); 424 425 static int bge_miibus_readreg(device_t, int, int); 426 static int bge_miibus_writereg(device_t, int, int, int); 427 static void bge_miibus_statchg(device_t); 428 #ifdef DEVICE_POLLING 429 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 430 #endif 431 432 #define BGE_RESET_START 1 433 #define BGE_RESET_STOP 2 434 static void bge_sig_post_reset(struct bge_softc *, int); 435 static void bge_sig_legacy(struct bge_softc *, int); 436 static void bge_sig_pre_reset(struct bge_softc *, int); 437 static int bge_reset(struct bge_softc *); 438 static void bge_link_upd(struct bge_softc *); 439 440 /* 441 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 442 * leak information to untrusted users. It is also known to cause alignment 443 * traps on certain architectures. 444 */ 445 #ifdef BGE_REGISTER_DEBUG 446 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 447 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 448 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 449 #endif 450 static void bge_add_sysctls(struct bge_softc *); 451 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 452 453 static device_method_t bge_methods[] = { 454 /* Device interface */ 455 DEVMETHOD(device_probe, bge_probe), 456 DEVMETHOD(device_attach, bge_attach), 457 DEVMETHOD(device_detach, bge_detach), 458 DEVMETHOD(device_shutdown, bge_shutdown), 459 DEVMETHOD(device_suspend, bge_suspend), 460 DEVMETHOD(device_resume, bge_resume), 461 462 /* bus interface */ 463 DEVMETHOD(bus_print_child, bus_generic_print_child), 464 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 465 466 /* MII interface */ 467 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 468 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 469 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 470 471 { 0, 0 } 472 }; 473 474 static driver_t bge_driver = { 475 "bge", 476 bge_methods, 477 sizeof(struct bge_softc) 478 }; 479 480 static devclass_t bge_devclass; 481 482 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 483 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 484 485 static int bge_allow_asf = 1; 486 487 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 488 489 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 490 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 491 "Allow ASF mode if available"); 492 493 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 494 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 495 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 496 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 497 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 498 499 static int 500 bge_has_eaddr(struct bge_softc *sc) 501 { 502 #ifdef __sparc64__ 503 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 504 device_t dev; 505 uint32_t subvendor; 506 507 dev = sc->bge_dev; 508 509 /* 510 * The on-board BGEs found in sun4u machines aren't fitted with 511 * an EEPROM which means that we have to obtain the MAC address 512 * via OFW and that some tests will always fail. We distinguish 513 * such BGEs by the subvendor ID, which also has to be obtained 514 * from OFW instead of the PCI configuration space as the latter 515 * indicates Broadcom as the subvendor of the netboot interface. 516 * For early Blade 1500 and 2500 we even have to check the OFW 517 * device path as the subvendor ID always defaults to Broadcom 518 * there. 519 */ 520 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 521 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 522 subvendor == SUN_VENDORID) 523 return (0); 524 memset(buf, 0, sizeof(buf)); 525 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 526 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 527 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 528 return (0); 529 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 530 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 531 return (0); 532 } 533 #endif 534 return (1); 535 } 536 537 static uint32_t 538 bge_readmem_ind(struct bge_softc *sc, int off) 539 { 540 device_t dev; 541 uint32_t val; 542 543 dev = sc->bge_dev; 544 545 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 546 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 547 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 548 return (val); 549 } 550 551 static void 552 bge_writemem_ind(struct bge_softc *sc, int off, int val) 553 { 554 device_t dev; 555 556 dev = sc->bge_dev; 557 558 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 559 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 560 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 561 } 562 563 /* 564 * PCI Express only 565 */ 566 static void 567 bge_set_max_readrq(struct bge_softc *sc) 568 { 569 device_t dev; 570 uint16_t val; 571 572 dev = sc->bge_dev; 573 574 val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 575 if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) != 576 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 577 if (bootverbose) 578 device_printf(dev, "adjust device control 0x%04x ", 579 val); 580 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 581 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 582 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 583 val, 2); 584 if (bootverbose) 585 printf("-> 0x%04x\n", val); 586 } 587 } 588 589 #ifdef notdef 590 static uint32_t 591 bge_readreg_ind(struct bge_softc *sc, int off) 592 { 593 device_t dev; 594 595 dev = sc->bge_dev; 596 597 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 598 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 599 } 600 #endif 601 602 static void 603 bge_writereg_ind(struct bge_softc *sc, int off, int val) 604 { 605 device_t dev; 606 607 dev = sc->bge_dev; 608 609 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 610 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 611 } 612 613 static void 614 bge_writemem_direct(struct bge_softc *sc, int off, int val) 615 { 616 CSR_WRITE_4(sc, off, val); 617 } 618 619 static void 620 bge_writembx(struct bge_softc *sc, int off, int val) 621 { 622 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 623 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 624 625 CSR_WRITE_4(sc, off, val); 626 } 627 628 /* 629 * Map a single buffer address. 630 */ 631 632 static void 633 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 634 { 635 struct bge_dmamap_arg *ctx; 636 637 if (error) 638 return; 639 640 ctx = arg; 641 642 if (nseg > ctx->bge_maxsegs) { 643 ctx->bge_maxsegs = 0; 644 return; 645 } 646 647 ctx->bge_busaddr = segs->ds_addr; 648 } 649 650 static uint8_t 651 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 652 { 653 uint32_t access, byte = 0; 654 int i; 655 656 /* Lock. */ 657 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 658 for (i = 0; i < 8000; i++) { 659 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 660 break; 661 DELAY(20); 662 } 663 if (i == 8000) 664 return (1); 665 666 /* Enable access. */ 667 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 668 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 669 670 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 671 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 672 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 673 DELAY(10); 674 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 675 DELAY(10); 676 break; 677 } 678 } 679 680 if (i == BGE_TIMEOUT * 10) { 681 if_printf(sc->bge_ifp, "nvram read timed out\n"); 682 return (1); 683 } 684 685 /* Get result. */ 686 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 687 688 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 689 690 /* Disable access. */ 691 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 692 693 /* Unlock. */ 694 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 695 CSR_READ_4(sc, BGE_NVRAM_SWARB); 696 697 return (0); 698 } 699 700 /* 701 * Read a sequence of bytes from NVRAM. 702 */ 703 static int 704 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 705 { 706 int err = 0, i; 707 uint8_t byte = 0; 708 709 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 710 return (1); 711 712 for (i = 0; i < cnt; i++) { 713 err = bge_nvram_getbyte(sc, off + i, &byte); 714 if (err) 715 break; 716 *(dest + i) = byte; 717 } 718 719 return (err ? 1 : 0); 720 } 721 722 /* 723 * Read a byte of data stored in the EEPROM at address 'addr.' The 724 * BCM570x supports both the traditional bitbang interface and an 725 * auto access interface for reading the EEPROM. We use the auto 726 * access method. 727 */ 728 static uint8_t 729 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 730 { 731 int i; 732 uint32_t byte = 0; 733 734 /* 735 * Enable use of auto EEPROM access so we can avoid 736 * having to use the bitbang method. 737 */ 738 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 739 740 /* Reset the EEPROM, load the clock period. */ 741 CSR_WRITE_4(sc, BGE_EE_ADDR, 742 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 743 DELAY(20); 744 745 /* Issue the read EEPROM command. */ 746 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 747 748 /* Wait for completion */ 749 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 750 DELAY(10); 751 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 752 break; 753 } 754 755 if (i == BGE_TIMEOUT * 10) { 756 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 757 return (1); 758 } 759 760 /* Get result. */ 761 byte = CSR_READ_4(sc, BGE_EE_DATA); 762 763 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 764 765 return (0); 766 } 767 768 /* 769 * Read a sequence of bytes from the EEPROM. 770 */ 771 static int 772 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 773 { 774 int i, error = 0; 775 uint8_t byte = 0; 776 777 for (i = 0; i < cnt; i++) { 778 error = bge_eeprom_getbyte(sc, off + i, &byte); 779 if (error) 780 break; 781 *(dest + i) = byte; 782 } 783 784 return (error ? 1 : 0); 785 } 786 787 static int 788 bge_miibus_readreg(device_t dev, int phy, int reg) 789 { 790 struct bge_softc *sc; 791 uint32_t val, autopoll; 792 int i; 793 794 sc = device_get_softc(dev); 795 796 /* 797 * Broadcom's own driver always assumes the internal 798 * PHY is at GMII address 1. On some chips, the PHY responds 799 * to accesses at all addresses, which could cause us to 800 * bogusly attach the PHY 32 times at probe type. Always 801 * restricting the lookup to address 1 is simpler than 802 * trying to figure out which chips revisions should be 803 * special-cased. 804 */ 805 if (phy != 1) 806 return (0); 807 808 /* Reading with autopolling on may trigger PCI errors */ 809 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 810 if (autopoll & BGE_MIMODE_AUTOPOLL) { 811 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 812 DELAY(40); 813 } 814 815 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 816 BGE_MIPHY(phy) | BGE_MIREG(reg)); 817 818 for (i = 0; i < BGE_TIMEOUT; i++) { 819 DELAY(10); 820 val = CSR_READ_4(sc, BGE_MI_COMM); 821 if (!(val & BGE_MICOMM_BUSY)) 822 break; 823 } 824 825 if (i == BGE_TIMEOUT) { 826 device_printf(sc->bge_dev, 827 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 828 phy, reg, val); 829 val = 0; 830 goto done; 831 } 832 833 DELAY(5); 834 val = CSR_READ_4(sc, BGE_MI_COMM); 835 836 done: 837 if (autopoll & BGE_MIMODE_AUTOPOLL) { 838 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 839 DELAY(40); 840 } 841 842 if (val & BGE_MICOMM_READFAIL) 843 return (0); 844 845 return (val & 0xFFFF); 846 } 847 848 static int 849 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 850 { 851 struct bge_softc *sc; 852 uint32_t autopoll; 853 int i; 854 855 sc = device_get_softc(dev); 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 858 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 859 return(0); 860 861 /* Reading with autopolling on may trigger PCI errors */ 862 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 863 if (autopoll & BGE_MIMODE_AUTOPOLL) { 864 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 865 DELAY(40); 866 } 867 868 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 869 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 870 871 for (i = 0; i < BGE_TIMEOUT; i++) { 872 DELAY(10); 873 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 874 DELAY(5); 875 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 876 break; 877 } 878 } 879 880 if (i == BGE_TIMEOUT) { 881 device_printf(sc->bge_dev, 882 "PHY write timed out (phy %d, reg %d, val %d)\n", 883 phy, reg, val); 884 return (0); 885 } 886 887 if (autopoll & BGE_MIMODE_AUTOPOLL) { 888 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 889 DELAY(40); 890 } 891 892 return (0); 893 } 894 895 static void 896 bge_miibus_statchg(device_t dev) 897 { 898 struct bge_softc *sc; 899 struct mii_data *mii; 900 sc = device_get_softc(dev); 901 mii = device_get_softc(sc->bge_miibus); 902 903 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 904 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 905 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 906 else 907 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 908 909 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 910 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 911 else 912 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 913 } 914 915 /* 916 * Intialize a standard receive ring descriptor. 917 */ 918 static int 919 bge_newbuf_std(struct bge_softc *sc, int i) 920 { 921 struct mbuf *m; 922 struct bge_rx_bd *r; 923 bus_dma_segment_t segs[1]; 924 bus_dmamap_t map; 925 int error, nsegs; 926 927 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 928 if (m == NULL) 929 return (ENOBUFS); 930 m->m_len = m->m_pkthdr.len = MCLBYTES; 931 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 932 m_adj(m, ETHER_ALIGN); 933 934 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 935 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 936 if (error != 0) { 937 m_freem(m); 938 return (error); 939 } 940 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 941 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 942 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 943 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 944 sc->bge_cdata.bge_rx_std_dmamap[i]); 945 } 946 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 947 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 948 sc->bge_cdata.bge_rx_std_sparemap = map; 949 sc->bge_cdata.bge_rx_std_chain[i] = m; 950 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 951 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 952 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 953 r->bge_flags = BGE_RXBDFLAG_END; 954 r->bge_len = segs[0].ds_len; 955 r->bge_idx = i; 956 957 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 958 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 959 960 return (0); 961 } 962 963 /* 964 * Initialize a jumbo receive ring descriptor. This allocates 965 * a jumbo buffer from the pool managed internally by the driver. 966 */ 967 static int 968 bge_newbuf_jumbo(struct bge_softc *sc, int i) 969 { 970 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 971 bus_dmamap_t map; 972 struct bge_extrx_bd *r; 973 struct mbuf *m; 974 int error, nsegs; 975 976 MGETHDR(m, M_DONTWAIT, MT_DATA); 977 if (m == NULL) 978 return (ENOBUFS); 979 980 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 981 if (!(m->m_flags & M_EXT)) { 982 m_freem(m); 983 return (ENOBUFS); 984 } 985 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 986 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 987 m_adj(m, ETHER_ALIGN); 988 989 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 990 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 991 if (error != 0) { 992 m_freem(m); 993 return (error); 994 } 995 996 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 997 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 998 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 999 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1000 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1001 } 1002 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1003 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1004 sc->bge_cdata.bge_rx_jumbo_sparemap; 1005 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1006 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1007 /* 1008 * Fill in the extended RX buffer descriptor. 1009 */ 1010 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1011 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1012 r->bge_idx = i; 1013 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1014 switch (nsegs) { 1015 case 4: 1016 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1017 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1018 r->bge_len3 = segs[3].ds_len; 1019 case 3: 1020 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1021 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1022 r->bge_len2 = segs[2].ds_len; 1023 case 2: 1024 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1025 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1026 r->bge_len1 = segs[1].ds_len; 1027 case 1: 1028 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1029 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1030 r->bge_len0 = segs[0].ds_len; 1031 break; 1032 default: 1033 panic("%s: %d segments\n", __func__, nsegs); 1034 } 1035 1036 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1037 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1038 1039 return (0); 1040 } 1041 1042 /* 1043 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1044 * that's 1MB or memory, which is a lot. For now, we fill only the first 1045 * 256 ring entries and hope that our CPU is fast enough to keep up with 1046 * the NIC. 1047 */ 1048 static int 1049 bge_init_rx_ring_std(struct bge_softc *sc) 1050 { 1051 int error, i; 1052 1053 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1054 sc->bge_std = 0; 1055 for (i = 0; i < BGE_SSLOTS; i++) { 1056 if ((error = bge_newbuf_std(sc, i)) != 0) 1057 return (error); 1058 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1059 }; 1060 1061 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1062 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1063 1064 sc->bge_std = i - 1; 1065 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1066 1067 return (0); 1068 } 1069 1070 static void 1071 bge_free_rx_ring_std(struct bge_softc *sc) 1072 { 1073 int i; 1074 1075 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1076 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1077 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1078 sc->bge_cdata.bge_rx_std_dmamap[i], 1079 BUS_DMASYNC_POSTREAD); 1080 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1081 sc->bge_cdata.bge_rx_std_dmamap[i]); 1082 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1083 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1084 } 1085 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1086 sizeof(struct bge_rx_bd)); 1087 } 1088 } 1089 1090 static int 1091 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1092 { 1093 struct bge_rcb *rcb; 1094 int error, i; 1095 1096 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1097 sc->bge_jumbo = 0; 1098 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1099 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1100 return (error); 1101 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1102 }; 1103 1104 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1105 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1106 1107 sc->bge_jumbo = i - 1; 1108 1109 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1110 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1111 BGE_RCB_FLAG_USE_EXT_RX_BD); 1112 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1113 1114 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1115 1116 return (0); 1117 } 1118 1119 static void 1120 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1121 { 1122 int i; 1123 1124 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1125 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1126 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1127 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1128 BUS_DMASYNC_POSTREAD); 1129 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1130 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1131 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1132 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1133 } 1134 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1135 sizeof(struct bge_extrx_bd)); 1136 } 1137 } 1138 1139 static void 1140 bge_free_tx_ring(struct bge_softc *sc) 1141 { 1142 int i; 1143 1144 if (sc->bge_ldata.bge_tx_ring == NULL) 1145 return; 1146 1147 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1148 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1149 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1150 sc->bge_cdata.bge_tx_dmamap[i], 1151 BUS_DMASYNC_POSTWRITE); 1152 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1153 sc->bge_cdata.bge_tx_dmamap[i]); 1154 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1155 sc->bge_cdata.bge_tx_chain[i] = NULL; 1156 } 1157 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1158 sizeof(struct bge_tx_bd)); 1159 } 1160 } 1161 1162 static int 1163 bge_init_tx_ring(struct bge_softc *sc) 1164 { 1165 sc->bge_txcnt = 0; 1166 sc->bge_tx_saved_considx = 0; 1167 1168 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1169 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1170 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1171 1172 /* Initialize transmit producer index for host-memory send ring. */ 1173 sc->bge_tx_prodidx = 0; 1174 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1175 1176 /* 5700 b2 errata */ 1177 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1178 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1179 1180 /* NIC-memory send ring not used; initialize to zero. */ 1181 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1182 /* 5700 b2 errata */ 1183 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1184 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1185 1186 return (0); 1187 } 1188 1189 static void 1190 bge_setpromisc(struct bge_softc *sc) 1191 { 1192 struct ifnet *ifp; 1193 1194 BGE_LOCK_ASSERT(sc); 1195 1196 ifp = sc->bge_ifp; 1197 1198 /* Enable or disable promiscuous mode as needed. */ 1199 if (ifp->if_flags & IFF_PROMISC) 1200 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1201 else 1202 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1203 } 1204 1205 static void 1206 bge_setmulti(struct bge_softc *sc) 1207 { 1208 struct ifnet *ifp; 1209 struct ifmultiaddr *ifma; 1210 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1211 int h, i; 1212 1213 BGE_LOCK_ASSERT(sc); 1214 1215 ifp = sc->bge_ifp; 1216 1217 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1218 for (i = 0; i < 4; i++) 1219 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1220 return; 1221 } 1222 1223 /* First, zot all the existing filters. */ 1224 for (i = 0; i < 4; i++) 1225 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1226 1227 /* Now program new ones. */ 1228 if_maddr_rlock(ifp); 1229 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1230 if (ifma->ifma_addr->sa_family != AF_LINK) 1231 continue; 1232 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1233 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1234 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1235 } 1236 if_maddr_runlock(ifp); 1237 1238 for (i = 0; i < 4; i++) 1239 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1240 } 1241 1242 static void 1243 bge_setvlan(struct bge_softc *sc) 1244 { 1245 struct ifnet *ifp; 1246 1247 BGE_LOCK_ASSERT(sc); 1248 1249 ifp = sc->bge_ifp; 1250 1251 /* Enable or disable VLAN tag stripping as needed. */ 1252 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1253 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1254 else 1255 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1256 } 1257 1258 static void 1259 bge_sig_pre_reset(sc, type) 1260 struct bge_softc *sc; 1261 int type; 1262 { 1263 /* 1264 * Some chips don't like this so only do this if ASF is enabled 1265 */ 1266 if (sc->bge_asf_mode) 1267 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1268 1269 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1270 switch (type) { 1271 case BGE_RESET_START: 1272 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1273 break; 1274 case BGE_RESET_STOP: 1275 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1276 break; 1277 } 1278 } 1279 } 1280 1281 static void 1282 bge_sig_post_reset(sc, type) 1283 struct bge_softc *sc; 1284 int type; 1285 { 1286 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1287 switch (type) { 1288 case BGE_RESET_START: 1289 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1290 /* START DONE */ 1291 break; 1292 case BGE_RESET_STOP: 1293 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1294 break; 1295 } 1296 } 1297 } 1298 1299 static void 1300 bge_sig_legacy(sc, type) 1301 struct bge_softc *sc; 1302 int type; 1303 { 1304 if (sc->bge_asf_mode) { 1305 switch (type) { 1306 case BGE_RESET_START: 1307 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1308 break; 1309 case BGE_RESET_STOP: 1310 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1311 break; 1312 } 1313 } 1314 } 1315 1316 void bge_stop_fw(struct bge_softc *); 1317 void 1318 bge_stop_fw(sc) 1319 struct bge_softc *sc; 1320 { 1321 int i; 1322 1323 if (sc->bge_asf_mode) { 1324 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1325 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1326 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1327 1328 for (i = 0; i < 100; i++ ) { 1329 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1330 break; 1331 DELAY(10); 1332 } 1333 } 1334 } 1335 1336 /* 1337 * Do endian, PCI and DMA initialization. 1338 */ 1339 static int 1340 bge_chipinit(struct bge_softc *sc) 1341 { 1342 uint32_t dma_rw_ctl; 1343 int i; 1344 1345 /* Set endianness before we access any non-PCI registers. */ 1346 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1347 1348 /* Clear the MAC control register */ 1349 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1350 1351 /* 1352 * Clear the MAC statistics block in the NIC's 1353 * internal memory. 1354 */ 1355 for (i = BGE_STATS_BLOCK; 1356 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1357 BGE_MEMWIN_WRITE(sc, i, 0); 1358 1359 for (i = BGE_STATUS_BLOCK; 1360 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1361 BGE_MEMWIN_WRITE(sc, i, 0); 1362 1363 /* 1364 * Set up the PCI DMA control register. 1365 */ 1366 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1367 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1368 if (sc->bge_flags & BGE_FLAG_PCIE) { 1369 /* Read watermark not used, 128 bytes for write. */ 1370 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1371 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1372 if (BGE_IS_5714_FAMILY(sc)) { 1373 /* 256 bytes for read and write. */ 1374 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1375 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1376 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1377 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1378 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1379 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1380 /* 1536 bytes for read, 384 bytes for write. */ 1381 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1382 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1383 } else { 1384 /* 384 bytes for read and write. */ 1385 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1386 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1387 0x0F; 1388 } 1389 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1390 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1391 uint32_t tmp; 1392 1393 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1394 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1395 if (tmp == 6 || tmp == 7) 1396 dma_rw_ctl |= 1397 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1398 1399 /* Set PCI-X DMA write workaround. */ 1400 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1401 } 1402 } else { 1403 /* Conventional PCI bus: 256 bytes for read and write. */ 1404 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1405 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1406 1407 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1408 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1409 dma_rw_ctl |= 0x0F; 1410 } 1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1412 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1413 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1414 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1415 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1416 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1417 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1418 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1419 1420 /* 1421 * Set up general mode register. 1422 */ 1423 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1424 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1425 BGE_MODECTL_TX_NO_PHDR_CSUM); 1426 1427 /* 1428 * BCM5701 B5 have a bug causing data corruption when using 1429 * 64-bit DMA reads, which can be terminated early and then 1430 * completed later as 32-bit accesses, in combination with 1431 * certain bridges. 1432 */ 1433 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1435 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1436 1437 /* 1438 * Tell the firmware the driver is running 1439 */ 1440 if (sc->bge_asf_mode & ASF_STACKUP) 1441 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1442 1443 /* 1444 * Disable memory write invalidate. Apparently it is not supported 1445 * properly by these devices. Also ensure that INTx isn't disabled, 1446 * as these chips need it even when using MSI. 1447 */ 1448 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1449 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1450 1451 /* Set the timer prescaler (always 66Mhz) */ 1452 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1453 1454 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1455 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1456 DELAY(40); /* XXX */ 1457 1458 /* Put PHY into ready state */ 1459 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1460 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1461 DELAY(40); 1462 } 1463 1464 return (0); 1465 } 1466 1467 static int 1468 bge_blockinit(struct bge_softc *sc) 1469 { 1470 struct bge_rcb *rcb; 1471 bus_size_t vrcb; 1472 bge_hostaddr taddr; 1473 uint32_t val; 1474 int i; 1475 1476 /* 1477 * Initialize the memory window pointer register so that 1478 * we can access the first 32K of internal NIC RAM. This will 1479 * allow us to set up the TX send ring RCBs and the RX return 1480 * ring RCBs, plus other things which live in NIC memory. 1481 */ 1482 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1483 1484 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1485 1486 if (!(BGE_IS_5705_PLUS(sc))) { 1487 /* Configure mbuf memory pool */ 1488 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1489 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1490 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1491 else 1492 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1493 1494 /* Configure DMA resource pool */ 1495 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1496 BGE_DMA_DESCRIPTORS); 1497 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1498 } 1499 1500 /* Configure mbuf pool watermarks */ 1501 if (!BGE_IS_5705_PLUS(sc)) { 1502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1503 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1505 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1507 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1509 } else { 1510 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1511 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1513 } 1514 1515 /* Configure DMA resource watermarks */ 1516 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1517 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1518 1519 /* Enable buffer manager */ 1520 if (!(BGE_IS_5705_PLUS(sc))) { 1521 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1522 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1523 1524 /* Poll for buffer manager start indication */ 1525 for (i = 0; i < BGE_TIMEOUT; i++) { 1526 DELAY(10); 1527 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1528 break; 1529 } 1530 1531 if (i == BGE_TIMEOUT) { 1532 device_printf(sc->bge_dev, 1533 "buffer manager failed to start\n"); 1534 return (ENXIO); 1535 } 1536 } 1537 1538 /* Enable flow-through queues */ 1539 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1540 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1541 1542 /* Wait until queue initialization is complete */ 1543 for (i = 0; i < BGE_TIMEOUT; i++) { 1544 DELAY(10); 1545 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1546 break; 1547 } 1548 1549 if (i == BGE_TIMEOUT) { 1550 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1551 return (ENXIO); 1552 } 1553 1554 /* Initialize the standard RX ring control block */ 1555 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1556 rcb->bge_hostaddr.bge_addr_lo = 1557 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1558 rcb->bge_hostaddr.bge_addr_hi = 1559 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1560 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1561 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1562 if (BGE_IS_5705_PLUS(sc)) 1563 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1564 else 1565 rcb->bge_maxlen_flags = 1566 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1567 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1568 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1569 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1570 1571 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1572 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1573 1574 /* 1575 * Initialize the jumbo RX ring control block 1576 * We set the 'ring disabled' bit in the flags 1577 * field until we're actually ready to start 1578 * using this ring (i.e. once we set the MTU 1579 * high enough to require it). 1580 */ 1581 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1582 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1583 1584 rcb->bge_hostaddr.bge_addr_lo = 1585 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1586 rcb->bge_hostaddr.bge_addr_hi = 1587 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1588 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1589 sc->bge_cdata.bge_rx_jumbo_ring_map, 1590 BUS_DMASYNC_PREREAD); 1591 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1592 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1593 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1594 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1595 rcb->bge_hostaddr.bge_addr_hi); 1596 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1597 rcb->bge_hostaddr.bge_addr_lo); 1598 1599 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1600 rcb->bge_maxlen_flags); 1601 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1602 1603 /* Set up dummy disabled mini ring RCB */ 1604 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1605 rcb->bge_maxlen_flags = 1606 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1607 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1608 rcb->bge_maxlen_flags); 1609 } 1610 1611 /* 1612 * Set the BD ring replentish thresholds. The recommended 1613 * values are 1/8th the number of descriptors allocated to 1614 * each ring. 1615 * XXX The 5754 requires a lower threshold, so it might be a 1616 * requirement of all 575x family chips. The Linux driver sets 1617 * the lower threshold for all 5705 family chips as well, but there 1618 * are reports that it might not need to be so strict. 1619 * 1620 * XXX Linux does some extra fiddling here for the 5906 parts as 1621 * well. 1622 */ 1623 if (BGE_IS_5705_PLUS(sc)) 1624 val = 8; 1625 else 1626 val = BGE_STD_RX_RING_CNT / 8; 1627 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1628 if (BGE_IS_JUMBO_CAPABLE(sc)) 1629 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1630 BGE_JUMBO_RX_RING_CNT/8); 1631 1632 /* 1633 * Disable all unused send rings by setting the 'ring disabled' 1634 * bit in the flags field of all the TX send ring control blocks. 1635 * These are located in NIC memory. 1636 */ 1637 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1638 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1639 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1640 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1641 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1642 vrcb += sizeof(struct bge_rcb); 1643 } 1644 1645 /* Configure TX RCB 0 (we use only the first ring) */ 1646 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1647 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1648 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1649 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1650 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1651 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1652 if (!(BGE_IS_5705_PLUS(sc))) 1653 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1654 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1655 1656 /* Disable all unused RX return rings */ 1657 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1658 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1659 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1660 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1661 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1662 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1663 BGE_RCB_FLAG_RING_DISABLED)); 1664 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1665 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1666 (i * (sizeof(uint64_t))), 0); 1667 vrcb += sizeof(struct bge_rcb); 1668 } 1669 1670 /* Initialize RX ring indexes */ 1671 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1672 if (BGE_IS_JUMBO_CAPABLE(sc)) 1673 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1674 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1675 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1676 1677 /* 1678 * Set up RX return ring 0 1679 * Note that the NIC address for RX return rings is 0x00000000. 1680 * The return rings live entirely within the host, so the 1681 * nicaddr field in the RCB isn't used. 1682 */ 1683 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1684 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1685 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1686 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1687 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1688 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1689 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1690 1691 /* Set random backoff seed for TX */ 1692 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1693 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1694 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1695 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1696 BGE_TX_BACKOFF_SEED_MASK); 1697 1698 /* Set inter-packet gap */ 1699 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1700 1701 /* 1702 * Specify which ring to use for packets that don't match 1703 * any RX rules. 1704 */ 1705 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1706 1707 /* 1708 * Configure number of RX lists. One interrupt distribution 1709 * list, sixteen active lists, one bad frames class. 1710 */ 1711 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1712 1713 /* Inialize RX list placement stats mask. */ 1714 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1715 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1716 1717 /* Disable host coalescing until we get it set up */ 1718 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1719 1720 /* Poll to make sure it's shut down. */ 1721 for (i = 0; i < BGE_TIMEOUT; i++) { 1722 DELAY(10); 1723 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1724 break; 1725 } 1726 1727 if (i == BGE_TIMEOUT) { 1728 device_printf(sc->bge_dev, 1729 "host coalescing engine failed to idle\n"); 1730 return (ENXIO); 1731 } 1732 1733 /* Set up host coalescing defaults */ 1734 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1735 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1736 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1737 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1738 if (!(BGE_IS_5705_PLUS(sc))) { 1739 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1740 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1741 } 1742 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1743 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1744 1745 /* Set up address of statistics block */ 1746 if (!(BGE_IS_5705_PLUS(sc))) { 1747 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1748 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1749 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1750 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1751 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1752 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1753 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1754 } 1755 1756 /* Set up address of status block */ 1757 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1758 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1759 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1760 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1761 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1762 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1763 1764 /* Set up status block size. */ 1765 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1766 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 1767 val = BGE_STATBLKSZ_FULL; 1768 else 1769 val = BGE_STATBLKSZ_32BYTE; 1770 1771 /* Turn on host coalescing state machine */ 1772 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1773 1774 /* Turn on RX BD completion state machine and enable attentions */ 1775 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1776 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1777 1778 /* Turn on RX list placement state machine */ 1779 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1780 1781 /* Turn on RX list selector state machine. */ 1782 if (!(BGE_IS_5705_PLUS(sc))) 1783 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1784 1785 /* Turn on DMA, clear stats */ 1786 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1787 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1788 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1789 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1790 ((sc->bge_flags & BGE_FLAG_TBI) ? 1791 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1792 1793 /* Set misc. local control, enable interrupts on attentions */ 1794 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1795 1796 #ifdef notdef 1797 /* Assert GPIO pins for PHY reset */ 1798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1799 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1800 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1801 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1802 #endif 1803 1804 /* Turn on DMA completion state machine */ 1805 if (!(BGE_IS_5705_PLUS(sc))) 1806 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1807 1808 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1809 1810 /* Enable host coalescing bug fix. */ 1811 if (BGE_IS_5755_PLUS(sc)) 1812 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1813 1814 /* Turn on write DMA state machine */ 1815 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1816 DELAY(40); 1817 1818 /* Turn on read DMA state machine */ 1819 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1820 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1821 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1822 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1823 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1824 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1825 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1826 if (sc->bge_flags & BGE_FLAG_PCIE) 1827 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1828 if (sc->bge_flags & BGE_FLAG_TSO) 1829 val |= BGE_RDMAMODE_TSO4_ENABLE; 1830 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1831 DELAY(40); 1832 1833 /* Turn on RX data completion state machine */ 1834 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1835 1836 /* Turn on RX BD initiator state machine */ 1837 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1838 1839 /* Turn on RX data and RX BD initiator state machine */ 1840 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1841 1842 /* Turn on Mbuf cluster free state machine */ 1843 if (!(BGE_IS_5705_PLUS(sc))) 1844 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1845 1846 /* Turn on send BD completion state machine */ 1847 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1848 1849 /* Turn on send data completion state machine */ 1850 val = BGE_SDCMODE_ENABLE; 1851 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1852 val |= BGE_SDCMODE_CDELAY; 1853 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1854 1855 /* Turn on send data initiator state machine */ 1856 if (sc->bge_flags & BGE_FLAG_TSO) 1857 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1858 else 1859 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1860 1861 /* Turn on send BD initiator state machine */ 1862 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1863 1864 /* Turn on send BD selector state machine */ 1865 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1866 1867 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1868 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1869 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1870 1871 /* ack/clear link change events */ 1872 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1873 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1874 BGE_MACSTAT_LINK_CHANGED); 1875 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1876 1877 /* Enable PHY auto polling (for MII/GMII only) */ 1878 if (sc->bge_flags & BGE_FLAG_TBI) { 1879 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1880 } else { 1881 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1882 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1883 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1884 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1885 BGE_EVTENB_MI_INTERRUPT); 1886 } 1887 1888 /* 1889 * Clear any pending link state attention. 1890 * Otherwise some link state change events may be lost until attention 1891 * is cleared by bge_intr() -> bge_link_upd() sequence. 1892 * It's not necessary on newer BCM chips - perhaps enabling link 1893 * state change attentions implies clearing pending attention. 1894 */ 1895 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1896 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1897 BGE_MACSTAT_LINK_CHANGED); 1898 1899 /* Enable link state change attentions. */ 1900 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1901 1902 return (0); 1903 } 1904 1905 const struct bge_revision * 1906 bge_lookup_rev(uint32_t chipid) 1907 { 1908 const struct bge_revision *br; 1909 1910 for (br = bge_revisions; br->br_name != NULL; br++) { 1911 if (br->br_chipid == chipid) 1912 return (br); 1913 } 1914 1915 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1916 if (br->br_chipid == BGE_ASICREV(chipid)) 1917 return (br); 1918 } 1919 1920 return (NULL); 1921 } 1922 1923 const struct bge_vendor * 1924 bge_lookup_vendor(uint16_t vid) 1925 { 1926 const struct bge_vendor *v; 1927 1928 for (v = bge_vendors; v->v_name != NULL; v++) 1929 if (v->v_id == vid) 1930 return (v); 1931 1932 panic("%s: unknown vendor %d", __func__, vid); 1933 return (NULL); 1934 } 1935 1936 /* 1937 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1938 * against our list and return its name if we find a match. 1939 * 1940 * Note that since the Broadcom controller contains VPD support, we 1941 * try to get the device name string from the controller itself instead 1942 * of the compiled-in string. It guarantees we'll always announce the 1943 * right product name. We fall back to the compiled-in string when 1944 * VPD is unavailable or corrupt. 1945 */ 1946 static int 1947 bge_probe(device_t dev) 1948 { 1949 const struct bge_type *t = bge_devs; 1950 struct bge_softc *sc = device_get_softc(dev); 1951 uint16_t vid, did; 1952 1953 sc->bge_dev = dev; 1954 vid = pci_get_vendor(dev); 1955 did = pci_get_device(dev); 1956 while(t->bge_vid != 0) { 1957 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1958 char model[64], buf[96]; 1959 const struct bge_revision *br; 1960 const struct bge_vendor *v; 1961 uint32_t id; 1962 1963 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1964 BGE_PCIMISCCTL_ASICREV_SHIFT; 1965 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 1966 id = pci_read_config(dev, 1967 BGE_PCI_PRODID_ASICREV, 4); 1968 br = bge_lookup_rev(id); 1969 v = bge_lookup_vendor(vid); 1970 { 1971 #if __FreeBSD_version > 700024 1972 const char *pname; 1973 1974 if (bge_has_eaddr(sc) && 1975 pci_get_vpd_ident(dev, &pname) == 0) 1976 snprintf(model, 64, "%s", pname); 1977 else 1978 #endif 1979 snprintf(model, 64, "%s %s", 1980 v->v_name, 1981 br != NULL ? br->br_name : 1982 "NetXtreme Ethernet Controller"); 1983 } 1984 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 1985 br != NULL ? "" : "unknown ", id); 1986 device_set_desc_copy(dev, buf); 1987 if (pci_get_subvendor(dev) == DELL_VENDORID) 1988 sc->bge_flags |= BGE_FLAG_NO_3LED; 1989 if (did == BCOM_DEVICEID_BCM5755M) 1990 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1991 return (0); 1992 } 1993 t++; 1994 } 1995 1996 return (ENXIO); 1997 } 1998 1999 static void 2000 bge_dma_free(struct bge_softc *sc) 2001 { 2002 int i; 2003 2004 /* Destroy DMA maps for RX buffers. */ 2005 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2006 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2007 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2008 sc->bge_cdata.bge_rx_std_dmamap[i]); 2009 } 2010 if (sc->bge_cdata.bge_rx_std_sparemap) 2011 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2012 sc->bge_cdata.bge_rx_std_sparemap); 2013 2014 /* Destroy DMA maps for jumbo RX buffers. */ 2015 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2016 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2017 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2018 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2019 } 2020 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2021 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2022 sc->bge_cdata.bge_rx_jumbo_sparemap); 2023 2024 /* Destroy DMA maps for TX buffers. */ 2025 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2026 if (sc->bge_cdata.bge_tx_dmamap[i]) 2027 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2028 sc->bge_cdata.bge_tx_dmamap[i]); 2029 } 2030 2031 if (sc->bge_cdata.bge_rx_mtag) 2032 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2033 if (sc->bge_cdata.bge_tx_mtag) 2034 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2035 2036 2037 /* Destroy standard RX ring. */ 2038 if (sc->bge_cdata.bge_rx_std_ring_map) 2039 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2040 sc->bge_cdata.bge_rx_std_ring_map); 2041 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2042 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2043 sc->bge_ldata.bge_rx_std_ring, 2044 sc->bge_cdata.bge_rx_std_ring_map); 2045 2046 if (sc->bge_cdata.bge_rx_std_ring_tag) 2047 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2048 2049 /* Destroy jumbo RX ring. */ 2050 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2051 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2052 sc->bge_cdata.bge_rx_jumbo_ring_map); 2053 2054 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2055 sc->bge_ldata.bge_rx_jumbo_ring) 2056 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2057 sc->bge_ldata.bge_rx_jumbo_ring, 2058 sc->bge_cdata.bge_rx_jumbo_ring_map); 2059 2060 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2061 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2062 2063 /* Destroy RX return ring. */ 2064 if (sc->bge_cdata.bge_rx_return_ring_map) 2065 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2066 sc->bge_cdata.bge_rx_return_ring_map); 2067 2068 if (sc->bge_cdata.bge_rx_return_ring_map && 2069 sc->bge_ldata.bge_rx_return_ring) 2070 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2071 sc->bge_ldata.bge_rx_return_ring, 2072 sc->bge_cdata.bge_rx_return_ring_map); 2073 2074 if (sc->bge_cdata.bge_rx_return_ring_tag) 2075 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2076 2077 /* Destroy TX ring. */ 2078 if (sc->bge_cdata.bge_tx_ring_map) 2079 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2080 sc->bge_cdata.bge_tx_ring_map); 2081 2082 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2083 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2084 sc->bge_ldata.bge_tx_ring, 2085 sc->bge_cdata.bge_tx_ring_map); 2086 2087 if (sc->bge_cdata.bge_tx_ring_tag) 2088 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2089 2090 /* Destroy status block. */ 2091 if (sc->bge_cdata.bge_status_map) 2092 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2093 sc->bge_cdata.bge_status_map); 2094 2095 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2096 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2097 sc->bge_ldata.bge_status_block, 2098 sc->bge_cdata.bge_status_map); 2099 2100 if (sc->bge_cdata.bge_status_tag) 2101 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2102 2103 /* Destroy statistics block. */ 2104 if (sc->bge_cdata.bge_stats_map) 2105 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2106 sc->bge_cdata.bge_stats_map); 2107 2108 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2109 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2110 sc->bge_ldata.bge_stats, 2111 sc->bge_cdata.bge_stats_map); 2112 2113 if (sc->bge_cdata.bge_stats_tag) 2114 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2115 2116 /* Destroy the parent tag. */ 2117 if (sc->bge_cdata.bge_parent_tag) 2118 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2119 } 2120 2121 static int 2122 bge_dma_alloc(device_t dev) 2123 { 2124 struct bge_dmamap_arg ctx; 2125 struct bge_softc *sc; 2126 bus_addr_t lowaddr; 2127 bus_size_t sbsz, txsegsz, txmaxsegsz; 2128 int i, error; 2129 2130 sc = device_get_softc(dev); 2131 2132 lowaddr = BUS_SPACE_MAXADDR; 2133 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2134 lowaddr = BGE_DMA_MAXADDR; 2135 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2136 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2137 /* 2138 * Allocate the parent bus DMA tag appropriate for PCI. 2139 */ 2140 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2141 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2142 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2143 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2144 2145 if (error != 0) { 2146 device_printf(sc->bge_dev, 2147 "could not allocate parent dma tag\n"); 2148 return (ENOMEM); 2149 } 2150 2151 /* 2152 * Create tag for Tx mbufs. 2153 */ 2154 if (sc->bge_flags & BGE_FLAG_TSO) { 2155 txsegsz = BGE_TSOSEG_SZ; 2156 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2157 } else { 2158 txsegsz = MCLBYTES; 2159 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2160 } 2161 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2162 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2163 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2164 &sc->bge_cdata.bge_tx_mtag); 2165 2166 if (error) { 2167 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2168 return (ENOMEM); 2169 } 2170 2171 /* 2172 * Create tag for Rx mbufs. 2173 */ 2174 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 2175 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2176 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2177 2178 if (error) { 2179 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2180 return (ENOMEM); 2181 } 2182 2183 /* Create DMA maps for RX buffers. */ 2184 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2185 &sc->bge_cdata.bge_rx_std_sparemap); 2186 if (error) { 2187 device_printf(sc->bge_dev, 2188 "can't create spare DMA map for RX\n"); 2189 return (ENOMEM); 2190 } 2191 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2192 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2193 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2194 if (error) { 2195 device_printf(sc->bge_dev, 2196 "can't create DMA map for RX\n"); 2197 return (ENOMEM); 2198 } 2199 } 2200 2201 /* Create DMA maps for TX buffers. */ 2202 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2203 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2204 &sc->bge_cdata.bge_tx_dmamap[i]); 2205 if (error) { 2206 device_printf(sc->bge_dev, 2207 "can't create DMA map for TX\n"); 2208 return (ENOMEM); 2209 } 2210 } 2211 2212 /* Create tag for standard RX ring. */ 2213 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2214 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2215 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2216 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2217 2218 if (error) { 2219 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2220 return (ENOMEM); 2221 } 2222 2223 /* Allocate DMA'able memory for standard RX ring. */ 2224 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2225 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2226 &sc->bge_cdata.bge_rx_std_ring_map); 2227 if (error) 2228 return (ENOMEM); 2229 2230 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2231 2232 /* Load the address of the standard RX ring. */ 2233 ctx.bge_maxsegs = 1; 2234 ctx.sc = sc; 2235 2236 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2237 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2238 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2239 2240 if (error) 2241 return (ENOMEM); 2242 2243 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2244 2245 /* Create tags for jumbo mbufs. */ 2246 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2247 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2248 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2249 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2250 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2251 if (error) { 2252 device_printf(sc->bge_dev, 2253 "could not allocate jumbo dma tag\n"); 2254 return (ENOMEM); 2255 } 2256 2257 /* Create tag for jumbo RX ring. */ 2258 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2259 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2260 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2261 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2262 2263 if (error) { 2264 device_printf(sc->bge_dev, 2265 "could not allocate jumbo ring dma tag\n"); 2266 return (ENOMEM); 2267 } 2268 2269 /* Allocate DMA'able memory for jumbo RX ring. */ 2270 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2271 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2272 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2273 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2274 if (error) 2275 return (ENOMEM); 2276 2277 /* Load the address of the jumbo RX ring. */ 2278 ctx.bge_maxsegs = 1; 2279 ctx.sc = sc; 2280 2281 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2282 sc->bge_cdata.bge_rx_jumbo_ring_map, 2283 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2284 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2285 2286 if (error) 2287 return (ENOMEM); 2288 2289 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2290 2291 /* Create DMA maps for jumbo RX buffers. */ 2292 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2293 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2294 if (error) { 2295 device_printf(sc->bge_dev, 2296 "can't create spare DMA map for jumbo RX\n"); 2297 return (ENOMEM); 2298 } 2299 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2300 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2301 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2302 if (error) { 2303 device_printf(sc->bge_dev, 2304 "can't create DMA map for jumbo RX\n"); 2305 return (ENOMEM); 2306 } 2307 } 2308 2309 } 2310 2311 /* Create tag for RX return ring. */ 2312 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2313 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2314 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2315 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2316 2317 if (error) { 2318 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2319 return (ENOMEM); 2320 } 2321 2322 /* Allocate DMA'able memory for RX return ring. */ 2323 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2324 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2325 &sc->bge_cdata.bge_rx_return_ring_map); 2326 if (error) 2327 return (ENOMEM); 2328 2329 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2330 BGE_RX_RTN_RING_SZ(sc)); 2331 2332 /* Load the address of the RX return ring. */ 2333 ctx.bge_maxsegs = 1; 2334 ctx.sc = sc; 2335 2336 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2337 sc->bge_cdata.bge_rx_return_ring_map, 2338 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2339 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2340 2341 if (error) 2342 return (ENOMEM); 2343 2344 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2345 2346 /* Create tag for TX ring. */ 2347 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2348 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2349 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2350 &sc->bge_cdata.bge_tx_ring_tag); 2351 2352 if (error) { 2353 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2354 return (ENOMEM); 2355 } 2356 2357 /* Allocate DMA'able memory for TX ring. */ 2358 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2359 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2360 &sc->bge_cdata.bge_tx_ring_map); 2361 if (error) 2362 return (ENOMEM); 2363 2364 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2365 2366 /* Load the address of the TX ring. */ 2367 ctx.bge_maxsegs = 1; 2368 ctx.sc = sc; 2369 2370 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2371 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2372 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2373 2374 if (error) 2375 return (ENOMEM); 2376 2377 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2378 2379 /* 2380 * Create tag for status block. 2381 * Because we only use single Tx/Rx/Rx return ring, use 2382 * minimum status block size except BCM5700 AX/BX which 2383 * seems to want to see full status block size regardless 2384 * of configured number of ring. 2385 */ 2386 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2387 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2388 sbsz = BGE_STATUS_BLK_SZ; 2389 else 2390 sbsz = 32; 2391 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2392 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2393 NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag); 2394 2395 if (error) { 2396 device_printf(sc->bge_dev, 2397 "could not allocate status dma tag\n"); 2398 return (ENOMEM); 2399 } 2400 2401 /* Allocate DMA'able memory for status block. */ 2402 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2403 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2404 &sc->bge_cdata.bge_status_map); 2405 if (error) 2406 return (ENOMEM); 2407 2408 bzero((char *)sc->bge_ldata.bge_status_block, sbsz); 2409 2410 /* Load the address of the status block. */ 2411 ctx.sc = sc; 2412 ctx.bge_maxsegs = 1; 2413 2414 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2415 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2416 sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2417 2418 if (error) 2419 return (ENOMEM); 2420 2421 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2422 2423 /* Create tag for statistics block. */ 2424 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2425 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2426 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2427 &sc->bge_cdata.bge_stats_tag); 2428 2429 if (error) { 2430 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2431 return (ENOMEM); 2432 } 2433 2434 /* Allocate DMA'able memory for statistics block. */ 2435 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2436 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2437 &sc->bge_cdata.bge_stats_map); 2438 if (error) 2439 return (ENOMEM); 2440 2441 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2442 2443 /* Load the address of the statstics block. */ 2444 ctx.sc = sc; 2445 ctx.bge_maxsegs = 1; 2446 2447 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2448 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2449 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2450 2451 if (error) 2452 return (ENOMEM); 2453 2454 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2455 2456 return (0); 2457 } 2458 2459 /* 2460 * Return true if this device has more than one port. 2461 */ 2462 static int 2463 bge_has_multiple_ports(struct bge_softc *sc) 2464 { 2465 device_t dev = sc->bge_dev; 2466 u_int b, d, f, fscan, s; 2467 2468 d = pci_get_domain(dev); 2469 b = pci_get_bus(dev); 2470 s = pci_get_slot(dev); 2471 f = pci_get_function(dev); 2472 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2473 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2474 return (1); 2475 return (0); 2476 } 2477 2478 /* 2479 * Return true if MSI can be used with this device. 2480 */ 2481 static int 2482 bge_can_use_msi(struct bge_softc *sc) 2483 { 2484 int can_use_msi = 0; 2485 2486 switch (sc->bge_asicrev) { 2487 case BGE_ASICREV_BCM5714_A0: 2488 case BGE_ASICREV_BCM5714: 2489 /* 2490 * Apparently, MSI doesn't work when these chips are 2491 * configured in single-port mode. 2492 */ 2493 if (bge_has_multiple_ports(sc)) 2494 can_use_msi = 1; 2495 break; 2496 case BGE_ASICREV_BCM5750: 2497 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2498 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2499 can_use_msi = 1; 2500 break; 2501 default: 2502 if (BGE_IS_575X_PLUS(sc)) 2503 can_use_msi = 1; 2504 } 2505 return (can_use_msi); 2506 } 2507 2508 static int 2509 bge_attach(device_t dev) 2510 { 2511 struct ifnet *ifp; 2512 struct bge_softc *sc; 2513 uint32_t hwcfg = 0, misccfg; 2514 u_char eaddr[ETHER_ADDR_LEN]; 2515 int error, msicount, reg, rid, trys; 2516 2517 sc = device_get_softc(dev); 2518 sc->bge_dev = dev; 2519 2520 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2521 2522 /* 2523 * Map control/status registers. 2524 */ 2525 pci_enable_busmaster(dev); 2526 2527 rid = BGE_PCI_BAR0; 2528 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2529 RF_ACTIVE); 2530 2531 if (sc->bge_res == NULL) { 2532 device_printf (sc->bge_dev, "couldn't map memory\n"); 2533 error = ENXIO; 2534 goto fail; 2535 } 2536 2537 /* Save various chip information. */ 2538 sc->bge_chipid = 2539 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2540 BGE_PCIMISCCTL_ASICREV_SHIFT; 2541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2542 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2543 4); 2544 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2545 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2546 2547 /* 2548 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2549 * 5705 A0 and A1 chips. 2550 */ 2551 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2552 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2553 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2554 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2555 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2556 2557 if (bge_has_eaddr(sc)) 2558 sc->bge_flags |= BGE_FLAG_EADDR; 2559 2560 /* Save chipset family. */ 2561 switch (sc->bge_asicrev) { 2562 case BGE_ASICREV_BCM5755: 2563 case BGE_ASICREV_BCM5761: 2564 case BGE_ASICREV_BCM5784: 2565 case BGE_ASICREV_BCM5785: 2566 case BGE_ASICREV_BCM5787: 2567 case BGE_ASICREV_BCM57780: 2568 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2569 BGE_FLAG_5705_PLUS; 2570 break; 2571 case BGE_ASICREV_BCM5700: 2572 case BGE_ASICREV_BCM5701: 2573 case BGE_ASICREV_BCM5703: 2574 case BGE_ASICREV_BCM5704: 2575 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2576 break; 2577 case BGE_ASICREV_BCM5714_A0: 2578 case BGE_ASICREV_BCM5780: 2579 case BGE_ASICREV_BCM5714: 2580 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2581 /* FALLTHROUGH */ 2582 case BGE_ASICREV_BCM5750: 2583 case BGE_ASICREV_BCM5752: 2584 case BGE_ASICREV_BCM5906: 2585 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2586 /* FALLTHROUGH */ 2587 case BGE_ASICREV_BCM5705: 2588 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2589 break; 2590 } 2591 2592 /* Set various bug flags. */ 2593 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2594 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2595 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2596 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2597 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2598 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2599 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2600 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2601 if (BGE_IS_5705_PLUS(sc) && 2602 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2603 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2604 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2605 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2606 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2607 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2608 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2609 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2610 sc->bge_flags |= BGE_FLAG_BER_BUG; 2611 } 2612 2613 /* 2614 * All controllers that are not 5755 or higher have 4GB 2615 * boundary DMA bug. 2616 * Whenever an address crosses a multiple of the 4GB boundary 2617 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2618 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2619 * state machine will lockup and cause the device to hang. 2620 */ 2621 if (BGE_IS_5755_PLUS(sc) == 0) 2622 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2623 2624 /* 2625 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2626 * but I do not know the DEVICEID for the 5788M. 2627 */ 2628 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2629 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2630 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2631 sc->bge_flags |= BGE_FLAG_5788; 2632 2633 /* 2634 * Some controllers seem to require a special firmware to use 2635 * TSO. But the firmware is not available to FreeBSD and Linux 2636 * claims that the TSO performed by the firmware is slower than 2637 * hardware based TSO. Moreover the firmware based TSO has one 2638 * known bug which can't handle TSO if ethernet header + IP/TCP 2639 * header is greater than 80 bytes. The workaround for the TSO 2640 * bug exist but it seems it's too expensive than not using 2641 * TSO at all. Some hardwares also have the TSO bug so limit 2642 * the TSO to the controllers that are not affected TSO issues 2643 * (e.g. 5755 or higher). 2644 */ 2645 if (BGE_IS_5755_PLUS(sc)) { 2646 /* 2647 * BCM5754 and BCM5787 shares the same ASIC id so 2648 * explicit device id check is required. 2649 */ 2650 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2651 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M) 2652 sc->bge_flags |= BGE_FLAG_TSO; 2653 } 2654 2655 /* 2656 * Check if this is a PCI-X or PCI Express device. 2657 */ 2658 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2659 /* 2660 * Found a PCI Express capabilities register, this 2661 * must be a PCI Express device. 2662 */ 2663 sc->bge_flags |= BGE_FLAG_PCIE; 2664 sc->bge_expcap = reg; 2665 bge_set_max_readrq(sc); 2666 } else { 2667 /* 2668 * Check if the device is in PCI-X Mode. 2669 * (This bit is not valid on PCI Express controllers.) 2670 */ 2671 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 2672 sc->bge_pcixcap = reg; 2673 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2674 BGE_PCISTATE_PCI_BUSMODE) == 0) 2675 sc->bge_flags |= BGE_FLAG_PCIX; 2676 } 2677 2678 /* 2679 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2680 * not actually a MAC controller bug but an issue with the embedded 2681 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2682 */ 2683 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2684 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2685 /* 2686 * Allocate the interrupt, using MSI if possible. These devices 2687 * support 8 MSI messages, but only the first one is used in 2688 * normal operation. 2689 */ 2690 rid = 0; 2691 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { 2692 sc->bge_msicap = reg; 2693 if (bge_can_use_msi(sc)) { 2694 msicount = pci_msi_count(dev); 2695 if (msicount > 1) 2696 msicount = 1; 2697 } else 2698 msicount = 0; 2699 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2700 rid = 1; 2701 sc->bge_flags |= BGE_FLAG_MSI; 2702 } 2703 } 2704 2705 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2706 RF_SHAREABLE | RF_ACTIVE); 2707 2708 if (sc->bge_irq == NULL) { 2709 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2710 error = ENXIO; 2711 goto fail; 2712 } 2713 2714 if (bootverbose) 2715 device_printf(dev, 2716 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2717 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2718 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2719 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2720 2721 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2722 2723 /* Try to reset the chip. */ 2724 if (bge_reset(sc)) { 2725 device_printf(sc->bge_dev, "chip reset failed\n"); 2726 error = ENXIO; 2727 goto fail; 2728 } 2729 2730 sc->bge_asf_mode = 0; 2731 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2732 == BGE_MAGIC_NUMBER)) { 2733 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2734 & BGE_HWCFG_ASF) { 2735 sc->bge_asf_mode |= ASF_ENABLE; 2736 sc->bge_asf_mode |= ASF_STACKUP; 2737 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2738 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2739 } 2740 } 2741 } 2742 2743 /* Try to reset the chip again the nice way. */ 2744 bge_stop_fw(sc); 2745 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2746 if (bge_reset(sc)) { 2747 device_printf(sc->bge_dev, "chip reset failed\n"); 2748 error = ENXIO; 2749 goto fail; 2750 } 2751 2752 bge_sig_legacy(sc, BGE_RESET_STOP); 2753 bge_sig_post_reset(sc, BGE_RESET_STOP); 2754 2755 if (bge_chipinit(sc)) { 2756 device_printf(sc->bge_dev, "chip initialization failed\n"); 2757 error = ENXIO; 2758 goto fail; 2759 } 2760 2761 error = bge_get_eaddr(sc, eaddr); 2762 if (error) { 2763 device_printf(sc->bge_dev, 2764 "failed to read station address\n"); 2765 error = ENXIO; 2766 goto fail; 2767 } 2768 2769 /* 5705 limits RX return ring to 512 entries. */ 2770 if (BGE_IS_5705_PLUS(sc)) 2771 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2772 else 2773 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2774 2775 if (bge_dma_alloc(dev)) { 2776 device_printf(sc->bge_dev, 2777 "failed to allocate DMA resources\n"); 2778 error = ENXIO; 2779 goto fail; 2780 } 2781 2782 /* Set default tuneable values. */ 2783 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2784 sc->bge_rx_coal_ticks = 150; 2785 sc->bge_tx_coal_ticks = 150; 2786 sc->bge_rx_max_coal_bds = 10; 2787 sc->bge_tx_max_coal_bds = 10; 2788 2789 /* Set up ifnet structure */ 2790 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2791 if (ifp == NULL) { 2792 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2793 error = ENXIO; 2794 goto fail; 2795 } 2796 ifp->if_softc = sc; 2797 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2798 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2799 ifp->if_ioctl = bge_ioctl; 2800 ifp->if_start = bge_start; 2801 ifp->if_init = bge_init; 2802 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2803 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2804 IFQ_SET_READY(&ifp->if_snd); 2805 ifp->if_hwassist = BGE_CSUM_FEATURES; 2806 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2807 IFCAP_VLAN_MTU; 2808 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2809 ifp->if_hwassist |= CSUM_TSO; 2810 ifp->if_capabilities |= IFCAP_TSO4; 2811 } 2812 #ifdef IFCAP_VLAN_HWCSUM 2813 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2814 #endif 2815 ifp->if_capenable = ifp->if_capabilities; 2816 #ifdef DEVICE_POLLING 2817 ifp->if_capabilities |= IFCAP_POLLING; 2818 #endif 2819 2820 /* 2821 * 5700 B0 chips do not support checksumming correctly due 2822 * to hardware bugs. 2823 */ 2824 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2825 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2826 ifp->if_capenable &= ~IFCAP_HWCSUM; 2827 ifp->if_hwassist = 0; 2828 } 2829 2830 /* 2831 * Figure out what sort of media we have by checking the 2832 * hardware config word in the first 32k of NIC internal memory, 2833 * or fall back to examining the EEPROM if necessary. 2834 * Note: on some BCM5700 cards, this value appears to be unset. 2835 * If that's the case, we have to rely on identifying the NIC 2836 * by its PCI subsystem ID, as we do below for the SysKonnect 2837 * SK-9D41. 2838 */ 2839 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2840 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2841 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2842 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2843 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2844 sizeof(hwcfg))) { 2845 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2846 error = ENXIO; 2847 goto fail; 2848 } 2849 hwcfg = ntohl(hwcfg); 2850 } 2851 2852 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2853 sc->bge_flags |= BGE_FLAG_TBI; 2854 2855 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2856 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2857 sc->bge_flags |= BGE_FLAG_TBI; 2858 2859 if (sc->bge_flags & BGE_FLAG_TBI) { 2860 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2861 bge_ifmedia_sts); 2862 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2863 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2864 0, NULL); 2865 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2866 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2867 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2868 } else { 2869 /* 2870 * Do transceiver setup and tell the firmware the 2871 * driver is down so we can try to get access the 2872 * probe if ASF is running. Retry a couple of times 2873 * if we get a conflict with the ASF firmware accessing 2874 * the PHY. 2875 */ 2876 trys = 0; 2877 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2878 again: 2879 bge_asf_driver_up(sc); 2880 2881 if (mii_phy_probe(dev, &sc->bge_miibus, 2882 bge_ifmedia_upd, bge_ifmedia_sts)) { 2883 if (trys++ < 4) { 2884 device_printf(sc->bge_dev, "Try again\n"); 2885 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2886 BMCR_RESET); 2887 goto again; 2888 } 2889 2890 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2891 error = ENXIO; 2892 goto fail; 2893 } 2894 2895 /* 2896 * Now tell the firmware we are going up after probing the PHY 2897 */ 2898 if (sc->bge_asf_mode & ASF_STACKUP) 2899 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2900 } 2901 2902 /* 2903 * When using the BCM5701 in PCI-X mode, data corruption has 2904 * been observed in the first few bytes of some received packets. 2905 * Aligning the packet buffer in memory eliminates the corruption. 2906 * Unfortunately, this misaligns the packet payloads. On platforms 2907 * which do not support unaligned accesses, we will realign the 2908 * payloads by copying the received packets. 2909 */ 2910 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2911 sc->bge_flags & BGE_FLAG_PCIX) 2912 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2913 2914 /* 2915 * Call MI attach routine. 2916 */ 2917 ether_ifattach(ifp, eaddr); 2918 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2919 2920 /* Tell upper layer we support long frames. */ 2921 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2922 2923 /* 2924 * Hookup IRQ last. 2925 */ 2926 #if __FreeBSD_version > 700030 2927 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 2928 /* Take advantage of single-shot MSI. */ 2929 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 2930 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 2931 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 2932 taskqueue_thread_enqueue, &sc->bge_tq); 2933 if (sc->bge_tq == NULL) { 2934 device_printf(dev, "could not create taskqueue.\n"); 2935 ether_ifdetach(ifp); 2936 error = ENXIO; 2937 goto fail; 2938 } 2939 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 2940 device_get_nameunit(sc->bge_dev)); 2941 error = bus_setup_intr(dev, sc->bge_irq, 2942 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 2943 &sc->bge_intrhand); 2944 if (error) 2945 ether_ifdetach(ifp); 2946 } else 2947 error = bus_setup_intr(dev, sc->bge_irq, 2948 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 2949 &sc->bge_intrhand); 2950 #else 2951 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2952 bge_intr, sc, &sc->bge_intrhand); 2953 #endif 2954 2955 if (error) { 2956 bge_detach(dev); 2957 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2958 } 2959 2960 bge_add_sysctls(sc); 2961 2962 return (0); 2963 2964 fail: 2965 bge_release_resources(sc); 2966 2967 return (error); 2968 } 2969 2970 static int 2971 bge_detach(device_t dev) 2972 { 2973 struct bge_softc *sc; 2974 struct ifnet *ifp; 2975 2976 sc = device_get_softc(dev); 2977 ifp = sc->bge_ifp; 2978 2979 #ifdef DEVICE_POLLING 2980 if (ifp->if_capenable & IFCAP_POLLING) 2981 ether_poll_deregister(ifp); 2982 #endif 2983 2984 BGE_LOCK(sc); 2985 bge_stop(sc); 2986 bge_reset(sc); 2987 BGE_UNLOCK(sc); 2988 2989 callout_drain(&sc->bge_stat_ch); 2990 2991 if (sc->bge_tq) 2992 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 2993 ether_ifdetach(ifp); 2994 2995 if (sc->bge_flags & BGE_FLAG_TBI) { 2996 ifmedia_removeall(&sc->bge_ifmedia); 2997 } else { 2998 bus_generic_detach(dev); 2999 device_delete_child(dev, sc->bge_miibus); 3000 } 3001 3002 bge_release_resources(sc); 3003 3004 return (0); 3005 } 3006 3007 static void 3008 bge_release_resources(struct bge_softc *sc) 3009 { 3010 device_t dev; 3011 3012 dev = sc->bge_dev; 3013 3014 if (sc->bge_tq != NULL) 3015 taskqueue_free(sc->bge_tq); 3016 3017 if (sc->bge_intrhand != NULL) 3018 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3019 3020 if (sc->bge_irq != NULL) 3021 bus_release_resource(dev, SYS_RES_IRQ, 3022 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3023 3024 if (sc->bge_flags & BGE_FLAG_MSI) 3025 pci_release_msi(dev); 3026 3027 if (sc->bge_res != NULL) 3028 bus_release_resource(dev, SYS_RES_MEMORY, 3029 BGE_PCI_BAR0, sc->bge_res); 3030 3031 if (sc->bge_ifp != NULL) 3032 if_free(sc->bge_ifp); 3033 3034 bge_dma_free(sc); 3035 3036 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3037 BGE_LOCK_DESTROY(sc); 3038 } 3039 3040 static int 3041 bge_reset(struct bge_softc *sc) 3042 { 3043 device_t dev; 3044 uint32_t cachesize, command, pcistate, reset, val; 3045 void (*write_op)(struct bge_softc *, int, int); 3046 uint16_t devctl; 3047 int i; 3048 3049 dev = sc->bge_dev; 3050 3051 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3052 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3053 if (sc->bge_flags & BGE_FLAG_PCIE) 3054 write_op = bge_writemem_direct; 3055 else 3056 write_op = bge_writemem_ind; 3057 } else 3058 write_op = bge_writereg_ind; 3059 3060 /* Save some important PCI state. */ 3061 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3062 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3063 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3064 3065 pci_write_config(dev, BGE_PCI_MISC_CTL, 3066 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3067 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3068 3069 /* Disable fastboot on controllers that support it. */ 3070 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3071 BGE_IS_5755_PLUS(sc)) { 3072 if (bootverbose) 3073 device_printf(sc->bge_dev, "Disabling fastboot\n"); 3074 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3075 } 3076 3077 /* 3078 * Write the magic number to SRAM at offset 0xB50. 3079 * When firmware finishes its initialization it will 3080 * write ~BGE_MAGIC_NUMBER to the same location. 3081 */ 3082 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3083 3084 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3085 3086 /* XXX: Broadcom Linux driver. */ 3087 if (sc->bge_flags & BGE_FLAG_PCIE) { 3088 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3089 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3090 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3091 /* Prevent PCIE link training during global reset */ 3092 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3093 reset |= 1 << 29; 3094 } 3095 } 3096 3097 /* 3098 * Set GPHY Power Down Override to leave GPHY 3099 * powered up in D0 uninitialized. 3100 */ 3101 if (BGE_IS_5705_PLUS(sc)) 3102 reset |= 0x04000000; 3103 3104 /* Issue global reset */ 3105 write_op(sc, BGE_MISC_CFG, reset); 3106 3107 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3108 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3109 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3110 val | BGE_VCPU_STATUS_DRV_RESET); 3111 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3112 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3113 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3114 } 3115 3116 DELAY(1000); 3117 3118 /* XXX: Broadcom Linux driver. */ 3119 if (sc->bge_flags & BGE_FLAG_PCIE) { 3120 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3121 DELAY(500000); /* wait for link training to complete */ 3122 val = pci_read_config(dev, 0xC4, 4); 3123 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3124 } 3125 devctl = pci_read_config(dev, 3126 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3127 /* Clear enable no snoop and disable relaxed ordering. */ 3128 devctl &= ~(0x0010 | 0x0800); 3129 /* Set PCIE max payload size to 128. */ 3130 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3131 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3132 devctl, 2); 3133 /* Clear error status. */ 3134 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3135 0, 2); 3136 } 3137 3138 /* Reset some of the PCI state that got zapped by reset. */ 3139 pci_write_config(dev, BGE_PCI_MISC_CTL, 3140 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3141 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3142 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3143 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3144 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3145 3146 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 3147 if (BGE_IS_5714_FAMILY(sc)) { 3148 /* This chip disables MSI on reset. */ 3149 if (sc->bge_flags & BGE_FLAG_MSI) { 3150 val = pci_read_config(dev, 3151 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3152 pci_write_config(dev, 3153 sc->bge_msicap + PCIR_MSI_CTRL, 3154 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3155 val = CSR_READ_4(sc, BGE_MSI_MODE); 3156 CSR_WRITE_4(sc, BGE_MSI_MODE, 3157 val | BGE_MSIMODE_ENABLE); 3158 } 3159 val = CSR_READ_4(sc, BGE_MARB_MODE); 3160 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3161 } else 3162 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3163 3164 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3165 for (i = 0; i < BGE_TIMEOUT; i++) { 3166 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3167 if (val & BGE_VCPU_STATUS_INIT_DONE) 3168 break; 3169 DELAY(100); 3170 } 3171 if (i == BGE_TIMEOUT) { 3172 device_printf(sc->bge_dev, "reset timed out\n"); 3173 return (1); 3174 } 3175 } else { 3176 /* 3177 * Poll until we see the 1's complement of the magic number. 3178 * This indicates that the firmware initialization is complete. 3179 * We expect this to fail if no chip containing the Ethernet 3180 * address is fitted though. 3181 */ 3182 for (i = 0; i < BGE_TIMEOUT; i++) { 3183 DELAY(10); 3184 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3185 if (val == ~BGE_MAGIC_NUMBER) 3186 break; 3187 } 3188 3189 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3190 device_printf(sc->bge_dev, "firmware handshake timed out, " 3191 "found 0x%08x\n", val); 3192 } 3193 3194 /* 3195 * XXX Wait for the value of the PCISTATE register to 3196 * return to its original pre-reset state. This is a 3197 * fairly good indicator of reset completion. If we don't 3198 * wait for the reset to fully complete, trying to read 3199 * from the device's non-PCI registers may yield garbage 3200 * results. 3201 */ 3202 for (i = 0; i < BGE_TIMEOUT; i++) { 3203 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3204 break; 3205 DELAY(10); 3206 } 3207 3208 if (sc->bge_flags & BGE_FLAG_PCIE) { 3209 reset = bge_readmem_ind(sc, 0x7C00); 3210 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 3211 } 3212 3213 /* Fix up byte swapping. */ 3214 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3215 BGE_MODECTL_BYTESWAP_DATA); 3216 3217 /* Tell the ASF firmware we are up */ 3218 if (sc->bge_asf_mode & ASF_STACKUP) 3219 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3220 3221 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3222 3223 /* 3224 * The 5704 in TBI mode apparently needs some special 3225 * adjustment to insure the SERDES drive level is set 3226 * to 1.2V. 3227 */ 3228 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3229 sc->bge_flags & BGE_FLAG_TBI) { 3230 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3231 val = (val & ~0xFFF) | 0x880; 3232 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3233 } 3234 3235 /* XXX: Broadcom Linux driver. */ 3236 if (sc->bge_flags & BGE_FLAG_PCIE && 3237 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3238 val = CSR_READ_4(sc, 0x7C00); 3239 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3240 } 3241 DELAY(10000); 3242 3243 return(0); 3244 } 3245 3246 /* 3247 * Frame reception handling. This is called if there's a frame 3248 * on the receive return list. 3249 * 3250 * Note: we have to be able to handle two possibilities here: 3251 * 1) the frame is from the jumbo receive ring 3252 * 2) the frame is from the standard receive ring 3253 */ 3254 3255 static int 3256 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3257 { 3258 struct ifnet *ifp; 3259 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3260 uint16_t rx_cons; 3261 3262 rx_cons = sc->bge_rx_saved_considx; 3263 3264 /* Nothing to do. */ 3265 if (rx_cons == rx_prod) 3266 return (rx_npkts); 3267 3268 ifp = sc->bge_ifp; 3269 3270 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3271 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3272 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3273 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3274 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3275 (MCLBYTES - ETHER_ALIGN)) 3276 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3277 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3278 3279 while (rx_cons != rx_prod) { 3280 struct bge_rx_bd *cur_rx; 3281 uint32_t rxidx; 3282 struct mbuf *m = NULL; 3283 uint16_t vlan_tag = 0; 3284 int have_tag = 0; 3285 3286 #ifdef DEVICE_POLLING 3287 if (ifp->if_capenable & IFCAP_POLLING) { 3288 if (sc->rxcycles <= 0) 3289 break; 3290 sc->rxcycles--; 3291 } 3292 #endif 3293 3294 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3295 3296 rxidx = cur_rx->bge_idx; 3297 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3298 3299 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3300 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3301 have_tag = 1; 3302 vlan_tag = cur_rx->bge_vlan_tag; 3303 } 3304 3305 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3306 jumbocnt++; 3307 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3308 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3309 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3310 continue; 3311 } 3312 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3313 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3314 ifp->if_iqdrops++; 3315 continue; 3316 } 3317 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3318 } else { 3319 stdcnt++; 3320 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3321 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3322 continue; 3323 } 3324 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3325 if (bge_newbuf_std(sc, rxidx) != 0) { 3326 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3327 ifp->if_iqdrops++; 3328 continue; 3329 } 3330 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3331 } 3332 3333 ifp->if_ipackets++; 3334 #ifndef __NO_STRICT_ALIGNMENT 3335 /* 3336 * For architectures with strict alignment we must make sure 3337 * the payload is aligned. 3338 */ 3339 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3340 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3341 cur_rx->bge_len); 3342 m->m_data += ETHER_ALIGN; 3343 } 3344 #endif 3345 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3346 m->m_pkthdr.rcvif = ifp; 3347 3348 if (ifp->if_capenable & IFCAP_RXCSUM) { 3349 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3350 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3351 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3352 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3353 } 3354 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3355 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3356 m->m_pkthdr.csum_data = 3357 cur_rx->bge_tcp_udp_csum; 3358 m->m_pkthdr.csum_flags |= 3359 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3360 } 3361 } 3362 3363 /* 3364 * If we received a packet with a vlan tag, 3365 * attach that information to the packet. 3366 */ 3367 if (have_tag) { 3368 #if __FreeBSD_version > 700022 3369 m->m_pkthdr.ether_vtag = vlan_tag; 3370 m->m_flags |= M_VLANTAG; 3371 #else 3372 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3373 if (m == NULL) 3374 continue; 3375 #endif 3376 } 3377 3378 if (holdlck != 0) { 3379 BGE_UNLOCK(sc); 3380 (*ifp->if_input)(ifp, m); 3381 BGE_LOCK(sc); 3382 } else 3383 (*ifp->if_input)(ifp, m); 3384 rx_npkts++; 3385 3386 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3387 return (rx_npkts); 3388 } 3389 3390 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3391 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3392 if (stdcnt > 0) 3393 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3394 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3395 3396 if (jumbocnt > 0) 3397 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3398 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3399 3400 sc->bge_rx_saved_considx = rx_cons; 3401 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3402 if (stdcnt) 3403 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3404 if (jumbocnt) 3405 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3406 #ifdef notyet 3407 /* 3408 * This register wraps very quickly under heavy packet drops. 3409 * If you need correct statistics, you can enable this check. 3410 */ 3411 if (BGE_IS_5705_PLUS(sc)) 3412 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3413 #endif 3414 return (rx_npkts); 3415 } 3416 3417 static void 3418 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3419 { 3420 struct bge_tx_bd *cur_tx = NULL; 3421 struct ifnet *ifp; 3422 3423 BGE_LOCK_ASSERT(sc); 3424 3425 /* Nothing to do. */ 3426 if (sc->bge_tx_saved_considx == tx_cons) 3427 return; 3428 3429 ifp = sc->bge_ifp; 3430 3431 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3432 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3433 /* 3434 * Go through our tx ring and free mbufs for those 3435 * frames that have been sent. 3436 */ 3437 while (sc->bge_tx_saved_considx != tx_cons) { 3438 uint32_t idx = 0; 3439 3440 idx = sc->bge_tx_saved_considx; 3441 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3442 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3443 ifp->if_opackets++; 3444 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3445 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3446 sc->bge_cdata.bge_tx_dmamap[idx], 3447 BUS_DMASYNC_POSTWRITE); 3448 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3449 sc->bge_cdata.bge_tx_dmamap[idx]); 3450 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3451 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3452 } 3453 sc->bge_txcnt--; 3454 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3455 } 3456 3457 if (cur_tx != NULL) 3458 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3459 if (sc->bge_txcnt == 0) 3460 sc->bge_timer = 0; 3461 } 3462 3463 #ifdef DEVICE_POLLING 3464 static int 3465 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3466 { 3467 struct bge_softc *sc = ifp->if_softc; 3468 uint16_t rx_prod, tx_cons; 3469 uint32_t statusword; 3470 int rx_npkts = 0; 3471 3472 BGE_LOCK(sc); 3473 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3474 BGE_UNLOCK(sc); 3475 return (rx_npkts); 3476 } 3477 3478 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3479 sc->bge_cdata.bge_status_map, 3480 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3481 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3482 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3483 3484 statusword = atomic_readandclear_32( 3485 &sc->bge_ldata.bge_status_block->bge_status); 3486 3487 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3488 sc->bge_cdata.bge_status_map, 3489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3490 3491 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3492 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3493 sc->bge_link_evt++; 3494 3495 if (cmd == POLL_AND_CHECK_STATUS) 3496 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3497 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3498 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3499 bge_link_upd(sc); 3500 3501 sc->rxcycles = count; 3502 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3503 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3504 BGE_UNLOCK(sc); 3505 return (rx_npkts); 3506 } 3507 bge_txeof(sc, tx_cons); 3508 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3509 bge_start_locked(ifp); 3510 3511 BGE_UNLOCK(sc); 3512 return (rx_npkts); 3513 } 3514 #endif /* DEVICE_POLLING */ 3515 3516 static int 3517 bge_msi_intr(void *arg) 3518 { 3519 struct bge_softc *sc; 3520 3521 sc = (struct bge_softc *)arg; 3522 /* 3523 * This interrupt is not shared and controller already 3524 * disabled further interrupt. 3525 */ 3526 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3527 return (FILTER_HANDLED); 3528 } 3529 3530 static void 3531 bge_intr_task(void *arg, int pending) 3532 { 3533 struct bge_softc *sc; 3534 struct ifnet *ifp; 3535 uint32_t status; 3536 uint16_t rx_prod, tx_cons; 3537 3538 sc = (struct bge_softc *)arg; 3539 ifp = sc->bge_ifp; 3540 3541 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3542 return; 3543 3544 /* Get updated status block. */ 3545 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3546 sc->bge_cdata.bge_status_map, 3547 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3548 3549 /* Save producer/consumer indexess. */ 3550 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3551 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3552 status = sc->bge_ldata.bge_status_block->bge_status; 3553 sc->bge_ldata.bge_status_block->bge_status = 0; 3554 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3555 sc->bge_cdata.bge_status_map, 3556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3557 /* Let controller work. */ 3558 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3559 3560 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) { 3561 BGE_LOCK(sc); 3562 bge_link_upd(sc); 3563 BGE_UNLOCK(sc); 3564 } 3565 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3566 /* Check RX return ring producer/consumer. */ 3567 bge_rxeof(sc, rx_prod, 0); 3568 } 3569 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3570 BGE_LOCK(sc); 3571 /* Check TX ring producer/consumer. */ 3572 bge_txeof(sc, tx_cons); 3573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3574 bge_start_locked(ifp); 3575 BGE_UNLOCK(sc); 3576 } 3577 } 3578 3579 static void 3580 bge_intr(void *xsc) 3581 { 3582 struct bge_softc *sc; 3583 struct ifnet *ifp; 3584 uint32_t statusword; 3585 uint16_t rx_prod, tx_cons; 3586 3587 sc = xsc; 3588 3589 BGE_LOCK(sc); 3590 3591 ifp = sc->bge_ifp; 3592 3593 #ifdef DEVICE_POLLING 3594 if (ifp->if_capenable & IFCAP_POLLING) { 3595 BGE_UNLOCK(sc); 3596 return; 3597 } 3598 #endif 3599 3600 /* 3601 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3602 * disable interrupts by writing nonzero like we used to, since with 3603 * our current organization this just gives complications and 3604 * pessimizations for re-enabling interrupts. We used to have races 3605 * instead of the necessary complications. Disabling interrupts 3606 * would just reduce the chance of a status update while we are 3607 * running (by switching to the interrupt-mode coalescence 3608 * parameters), but this chance is already very low so it is more 3609 * efficient to get another interrupt than prevent it. 3610 * 3611 * We do the ack first to ensure another interrupt if there is a 3612 * status update after the ack. We don't check for the status 3613 * changing later because it is more efficient to get another 3614 * interrupt than prevent it, not quite as above (not checking is 3615 * a smaller optimization than not toggling the interrupt enable, 3616 * since checking doesn't involve PCI accesses and toggling require 3617 * the status check). So toggling would probably be a pessimization 3618 * even with MSI. It would only be needed for using a task queue. 3619 */ 3620 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3621 3622 /* 3623 * Do the mandatory PCI flush as well as get the link status. 3624 */ 3625 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3626 3627 /* Make sure the descriptor ring indexes are coherent. */ 3628 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3629 sc->bge_cdata.bge_status_map, 3630 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3631 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3632 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3633 sc->bge_ldata.bge_status_block->bge_status = 0; 3634 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3635 sc->bge_cdata.bge_status_map, 3636 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3637 3638 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3639 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3640 statusword || sc->bge_link_evt) 3641 bge_link_upd(sc); 3642 3643 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3644 /* Check RX return ring producer/consumer. */ 3645 bge_rxeof(sc, rx_prod, 1); 3646 } 3647 3648 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3649 /* Check TX ring producer/consumer. */ 3650 bge_txeof(sc, tx_cons); 3651 } 3652 3653 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3654 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3655 bge_start_locked(ifp); 3656 3657 BGE_UNLOCK(sc); 3658 } 3659 3660 static void 3661 bge_asf_driver_up(struct bge_softc *sc) 3662 { 3663 if (sc->bge_asf_mode & ASF_STACKUP) { 3664 /* Send ASF heartbeat aprox. every 2s */ 3665 if (sc->bge_asf_count) 3666 sc->bge_asf_count --; 3667 else { 3668 sc->bge_asf_count = 5; 3669 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3670 BGE_FW_DRV_ALIVE); 3671 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3672 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3673 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3674 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3675 } 3676 } 3677 } 3678 3679 static void 3680 bge_tick(void *xsc) 3681 { 3682 struct bge_softc *sc = xsc; 3683 struct mii_data *mii = NULL; 3684 3685 BGE_LOCK_ASSERT(sc); 3686 3687 /* Synchronize with possible callout reset/stop. */ 3688 if (callout_pending(&sc->bge_stat_ch) || 3689 !callout_active(&sc->bge_stat_ch)) 3690 return; 3691 3692 if (BGE_IS_5705_PLUS(sc)) 3693 bge_stats_update_regs(sc); 3694 else 3695 bge_stats_update(sc); 3696 3697 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3698 mii = device_get_softc(sc->bge_miibus); 3699 /* 3700 * Do not touch PHY if we have link up. This could break 3701 * IPMI/ASF mode or produce extra input errors 3702 * (extra errors was reported for bcm5701 & bcm5704). 3703 */ 3704 if (!sc->bge_link) 3705 mii_tick(mii); 3706 } else { 3707 /* 3708 * Since in TBI mode auto-polling can't be used we should poll 3709 * link status manually. Here we register pending link event 3710 * and trigger interrupt. 3711 */ 3712 #ifdef DEVICE_POLLING 3713 /* In polling mode we poll link state in bge_poll(). */ 3714 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3715 #endif 3716 { 3717 sc->bge_link_evt++; 3718 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3719 sc->bge_flags & BGE_FLAG_5788) 3720 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3721 else 3722 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3723 } 3724 } 3725 3726 bge_asf_driver_up(sc); 3727 bge_watchdog(sc); 3728 3729 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3730 } 3731 3732 static void 3733 bge_stats_update_regs(struct bge_softc *sc) 3734 { 3735 struct ifnet *ifp; 3736 3737 ifp = sc->bge_ifp; 3738 3739 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3740 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3741 3742 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3743 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3744 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3745 } 3746 3747 static void 3748 bge_stats_update(struct bge_softc *sc) 3749 { 3750 struct ifnet *ifp; 3751 bus_size_t stats; 3752 uint32_t cnt; /* current register value */ 3753 3754 ifp = sc->bge_ifp; 3755 3756 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3757 3758 #define READ_STAT(sc, stats, stat) \ 3759 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3760 3761 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3762 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3763 sc->bge_tx_collisions = cnt; 3764 3765 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3766 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3767 sc->bge_rx_discards = cnt; 3768 3769 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3770 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3771 sc->bge_tx_discards = cnt; 3772 3773 #undef READ_STAT 3774 } 3775 3776 /* 3777 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3778 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3779 * but when such padded frames employ the bge IP/TCP checksum offload, 3780 * the hardware checksum assist gives incorrect results (possibly 3781 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3782 * If we pad such runts with zeros, the onboard checksum comes out correct. 3783 */ 3784 static __inline int 3785 bge_cksum_pad(struct mbuf *m) 3786 { 3787 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3788 struct mbuf *last; 3789 3790 /* If there's only the packet-header and we can pad there, use it. */ 3791 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3792 M_TRAILINGSPACE(m) >= padlen) { 3793 last = m; 3794 } else { 3795 /* 3796 * Walk packet chain to find last mbuf. We will either 3797 * pad there, or append a new mbuf and pad it. 3798 */ 3799 for (last = m; last->m_next != NULL; last = last->m_next); 3800 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3801 /* Allocate new empty mbuf, pad it. Compact later. */ 3802 struct mbuf *n; 3803 3804 MGET(n, M_DONTWAIT, MT_DATA); 3805 if (n == NULL) 3806 return (ENOBUFS); 3807 n->m_len = 0; 3808 last->m_next = n; 3809 last = n; 3810 } 3811 } 3812 3813 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3814 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3815 last->m_len += padlen; 3816 m->m_pkthdr.len += padlen; 3817 3818 return (0); 3819 } 3820 3821 static struct mbuf * 3822 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 3823 { 3824 struct ether_header *eh; 3825 struct ip *ip; 3826 struct tcphdr *tcp; 3827 struct mbuf *n; 3828 uint16_t hlen; 3829 uint32_t ip_off, poff; 3830 3831 if (M_WRITABLE(m) == 0) { 3832 /* Get a writable copy. */ 3833 n = m_dup(m, M_DONTWAIT); 3834 m_freem(m); 3835 if (n == NULL) 3836 return (NULL); 3837 m = n; 3838 } 3839 ip_off = sizeof(struct ether_header); 3840 m = m_pullup(m, ip_off); 3841 if (m == NULL) 3842 return (NULL); 3843 eh = mtod(m, struct ether_header *); 3844 /* Check the existence of VLAN tag. */ 3845 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 3846 ip_off = sizeof(struct ether_vlan_header); 3847 m = m_pullup(m, ip_off); 3848 if (m == NULL) 3849 return (NULL); 3850 } 3851 m = m_pullup(m, ip_off + sizeof(struct ip)); 3852 if (m == NULL) 3853 return (NULL); 3854 ip = (struct ip *)(mtod(m, char *) + ip_off); 3855 poff = ip_off + (ip->ip_hl << 2); 3856 m = m_pullup(m, poff + sizeof(struct tcphdr)); 3857 if (m == NULL) 3858 return (NULL); 3859 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 3860 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 3861 if (m == NULL) 3862 return (NULL); 3863 /* 3864 * It seems controller doesn't modify IP length and TCP pseudo 3865 * checksum. These checksum computed by upper stack should be 0. 3866 */ 3867 *mss = m->m_pkthdr.tso_segsz; 3868 ip->ip_sum = 0; 3869 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 3870 /* Clear pseudo checksum computed by TCP stack. */ 3871 tcp->th_sum = 0; 3872 /* 3873 * Broadcom controllers uses different descriptor format for 3874 * TSO depending on ASIC revision. Due to TSO-capable firmware 3875 * license issue and lower performance of firmware based TSO 3876 * we only support hardware based TSO which is applicable for 3877 * BCM5755 or newer controllers. Hardware based TSO uses 11 3878 * bits to store MSS and upper 5 bits are used to store IP/TCP 3879 * header length(including IP/TCP options). The header length 3880 * is expressed as 32 bits unit. 3881 */ 3882 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 3883 *mss |= (hlen << 11); 3884 return (m); 3885 } 3886 3887 /* 3888 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3889 * pointers to descriptors. 3890 */ 3891 static int 3892 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3893 { 3894 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3895 bus_dmamap_t map; 3896 struct bge_tx_bd *d; 3897 struct mbuf *m = *m_head; 3898 uint32_t idx = *txidx; 3899 uint16_t csum_flags, mss, vlan_tag; 3900 int nsegs, i, error; 3901 3902 csum_flags = 0; 3903 mss = 0; 3904 vlan_tag = 0; 3905 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 3906 *m_head = m = bge_setup_tso(sc, m, &mss); 3907 if (*m_head == NULL) 3908 return (ENOBUFS); 3909 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 3910 BGE_TXBDFLAG_CPU_POST_DMA; 3911 } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) { 3912 if (m->m_pkthdr.csum_flags & CSUM_IP) 3913 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3914 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3915 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3916 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3917 (error = bge_cksum_pad(m)) != 0) { 3918 m_freem(m); 3919 *m_head = NULL; 3920 return (error); 3921 } 3922 } 3923 if (m->m_flags & M_LASTFRAG) 3924 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3925 else if (m->m_flags & M_FRAG) 3926 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3927 } 3928 3929 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3930 sc->bge_forced_collapse > 0 && 3931 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 3932 /* 3933 * Forcedly collapse mbuf chains to overcome hardware 3934 * limitation which only support a single outstanding 3935 * DMA read operation. 3936 */ 3937 if (sc->bge_forced_collapse == 1) 3938 m = m_defrag(m, M_DONTWAIT); 3939 else 3940 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse); 3941 if (m == NULL) { 3942 m_freem(*m_head); 3943 *m_head = NULL; 3944 return (ENOBUFS); 3945 } 3946 *m_head = m; 3947 } 3948 3949 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3950 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 3951 &nsegs, BUS_DMA_NOWAIT); 3952 if (error == EFBIG) { 3953 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3954 if (m == NULL) { 3955 m_freem(*m_head); 3956 *m_head = NULL; 3957 return (ENOBUFS); 3958 } 3959 *m_head = m; 3960 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 3961 m, segs, &nsegs, BUS_DMA_NOWAIT); 3962 if (error) { 3963 m_freem(m); 3964 *m_head = NULL; 3965 return (error); 3966 } 3967 } else if (error != 0) 3968 return (error); 3969 3970 /* Check if we have enough free send BDs. */ 3971 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 3972 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 3973 return (ENOBUFS); 3974 } 3975 3976 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3977 3978 #if __FreeBSD_version > 700022 3979 if (m->m_flags & M_VLANTAG) { 3980 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3981 vlan_tag = m->m_pkthdr.ether_vtag; 3982 } 3983 #else 3984 { 3985 struct m_tag *mtag; 3986 3987 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3988 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3989 vlan_tag = VLAN_TAG_VALUE(mtag); 3990 } 3991 } 3992 #endif 3993 for (i = 0; ; i++) { 3994 d = &sc->bge_ldata.bge_tx_ring[idx]; 3995 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3996 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3997 d->bge_len = segs[i].ds_len; 3998 d->bge_flags = csum_flags; 3999 d->bge_vlan_tag = vlan_tag; 4000 d->bge_mss = mss; 4001 if (i == nsegs - 1) 4002 break; 4003 BGE_INC(idx, BGE_TX_RING_CNT); 4004 } 4005 4006 /* Mark the last segment as end of packet... */ 4007 d->bge_flags |= BGE_TXBDFLAG_END; 4008 4009 /* 4010 * Insure that the map for this transmission 4011 * is placed at the array index of the last descriptor 4012 * in this chain. 4013 */ 4014 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4015 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4016 sc->bge_cdata.bge_tx_chain[idx] = m; 4017 sc->bge_txcnt += nsegs; 4018 4019 BGE_INC(idx, BGE_TX_RING_CNT); 4020 *txidx = idx; 4021 4022 return (0); 4023 } 4024 4025 /* 4026 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4027 * to the mbuf data regions directly in the transmit descriptors. 4028 */ 4029 static void 4030 bge_start_locked(struct ifnet *ifp) 4031 { 4032 struct bge_softc *sc; 4033 struct mbuf *m_head; 4034 uint32_t prodidx; 4035 int count; 4036 4037 sc = ifp->if_softc; 4038 BGE_LOCK_ASSERT(sc); 4039 4040 if (!sc->bge_link || 4041 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4042 IFF_DRV_RUNNING) 4043 return; 4044 4045 prodidx = sc->bge_tx_prodidx; 4046 4047 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4048 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4049 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4050 break; 4051 } 4052 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4053 if (m_head == NULL) 4054 break; 4055 4056 /* 4057 * XXX 4058 * The code inside the if() block is never reached since we 4059 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4060 * requests to checksum TCP/UDP in a fragmented packet. 4061 * 4062 * XXX 4063 * safety overkill. If this is a fragmented packet chain 4064 * with delayed TCP/UDP checksums, then only encapsulate 4065 * it if we have enough descriptors to handle the entire 4066 * chain at once. 4067 * (paranoia -- may not actually be needed) 4068 */ 4069 if (m_head->m_flags & M_FIRSTFRAG && 4070 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4071 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4072 m_head->m_pkthdr.csum_data + 16) { 4073 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4074 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4075 break; 4076 } 4077 } 4078 4079 /* 4080 * Pack the data into the transmit ring. If we 4081 * don't have room, set the OACTIVE flag and wait 4082 * for the NIC to drain the ring. 4083 */ 4084 if (bge_encap(sc, &m_head, &prodidx)) { 4085 if (m_head == NULL) 4086 break; 4087 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4088 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4089 break; 4090 } 4091 ++count; 4092 4093 /* 4094 * If there's a BPF listener, bounce a copy of this frame 4095 * to him. 4096 */ 4097 #ifdef ETHER_BPF_MTAP 4098 ETHER_BPF_MTAP(ifp, m_head); 4099 #else 4100 BPF_MTAP(ifp, m_head); 4101 #endif 4102 } 4103 4104 if (count > 0) { 4105 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4106 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4107 /* Transmit. */ 4108 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4109 /* 5700 b2 errata */ 4110 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4111 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4112 4113 sc->bge_tx_prodidx = prodidx; 4114 4115 /* 4116 * Set a timeout in case the chip goes out to lunch. 4117 */ 4118 sc->bge_timer = 5; 4119 } 4120 } 4121 4122 /* 4123 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4124 * to the mbuf data regions directly in the transmit descriptors. 4125 */ 4126 static void 4127 bge_start(struct ifnet *ifp) 4128 { 4129 struct bge_softc *sc; 4130 4131 sc = ifp->if_softc; 4132 BGE_LOCK(sc); 4133 bge_start_locked(ifp); 4134 BGE_UNLOCK(sc); 4135 } 4136 4137 static void 4138 bge_init_locked(struct bge_softc *sc) 4139 { 4140 struct ifnet *ifp; 4141 uint16_t *m; 4142 4143 BGE_LOCK_ASSERT(sc); 4144 4145 ifp = sc->bge_ifp; 4146 4147 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4148 return; 4149 4150 /* Cancel pending I/O and flush buffers. */ 4151 bge_stop(sc); 4152 4153 bge_stop_fw(sc); 4154 bge_sig_pre_reset(sc, BGE_RESET_START); 4155 bge_reset(sc); 4156 bge_sig_legacy(sc, BGE_RESET_START); 4157 bge_sig_post_reset(sc, BGE_RESET_START); 4158 4159 bge_chipinit(sc); 4160 4161 /* 4162 * Init the various state machines, ring 4163 * control blocks and firmware. 4164 */ 4165 if (bge_blockinit(sc)) { 4166 device_printf(sc->bge_dev, "initialization failure\n"); 4167 return; 4168 } 4169 4170 ifp = sc->bge_ifp; 4171 4172 /* Specify MTU. */ 4173 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4174 ETHER_HDR_LEN + ETHER_CRC_LEN + 4175 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4176 4177 /* Load our MAC address. */ 4178 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4179 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4180 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4181 4182 /* Program promiscuous mode. */ 4183 bge_setpromisc(sc); 4184 4185 /* Program multicast filter. */ 4186 bge_setmulti(sc); 4187 4188 /* Program VLAN tag stripping. */ 4189 bge_setvlan(sc); 4190 4191 /* Init RX ring. */ 4192 if (bge_init_rx_ring_std(sc) != 0) { 4193 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4194 bge_stop(sc); 4195 return; 4196 } 4197 4198 /* 4199 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4200 * memory to insure that the chip has in fact read the first 4201 * entry of the ring. 4202 */ 4203 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4204 uint32_t v, i; 4205 for (i = 0; i < 10; i++) { 4206 DELAY(20); 4207 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4208 if (v == (MCLBYTES - ETHER_ALIGN)) 4209 break; 4210 } 4211 if (i == 10) 4212 device_printf (sc->bge_dev, 4213 "5705 A0 chip failed to load RX ring\n"); 4214 } 4215 4216 /* Init jumbo RX ring. */ 4217 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4218 (MCLBYTES - ETHER_ALIGN)) { 4219 if (bge_init_rx_ring_jumbo(sc) != 0) { 4220 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4221 bge_stop(sc); 4222 return; 4223 } 4224 } 4225 4226 /* Init our RX return ring index. */ 4227 sc->bge_rx_saved_considx = 0; 4228 4229 /* Init our RX/TX stat counters. */ 4230 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4231 4232 /* Init TX ring. */ 4233 bge_init_tx_ring(sc); 4234 4235 /* Turn on transmitter. */ 4236 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4237 4238 /* Turn on receiver. */ 4239 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4240 4241 /* Tell firmware we're alive. */ 4242 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4243 4244 #ifdef DEVICE_POLLING 4245 /* Disable interrupts if we are polling. */ 4246 if (ifp->if_capenable & IFCAP_POLLING) { 4247 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4248 BGE_PCIMISCCTL_MASK_PCI_INTR); 4249 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4250 } else 4251 #endif 4252 4253 /* Enable host interrupts. */ 4254 { 4255 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4256 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4257 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4258 } 4259 4260 bge_ifmedia_upd_locked(ifp); 4261 4262 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4264 4265 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4266 } 4267 4268 static void 4269 bge_init(void *xsc) 4270 { 4271 struct bge_softc *sc = xsc; 4272 4273 BGE_LOCK(sc); 4274 bge_init_locked(sc); 4275 BGE_UNLOCK(sc); 4276 } 4277 4278 /* 4279 * Set media options. 4280 */ 4281 static int 4282 bge_ifmedia_upd(struct ifnet *ifp) 4283 { 4284 struct bge_softc *sc = ifp->if_softc; 4285 int res; 4286 4287 BGE_LOCK(sc); 4288 res = bge_ifmedia_upd_locked(ifp); 4289 BGE_UNLOCK(sc); 4290 4291 return (res); 4292 } 4293 4294 static int 4295 bge_ifmedia_upd_locked(struct ifnet *ifp) 4296 { 4297 struct bge_softc *sc = ifp->if_softc; 4298 struct mii_data *mii; 4299 struct mii_softc *miisc; 4300 struct ifmedia *ifm; 4301 4302 BGE_LOCK_ASSERT(sc); 4303 4304 ifm = &sc->bge_ifmedia; 4305 4306 /* If this is a 1000baseX NIC, enable the TBI port. */ 4307 if (sc->bge_flags & BGE_FLAG_TBI) { 4308 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4309 return (EINVAL); 4310 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4311 case IFM_AUTO: 4312 /* 4313 * The BCM5704 ASIC appears to have a special 4314 * mechanism for programming the autoneg 4315 * advertisement registers in TBI mode. 4316 */ 4317 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4318 uint32_t sgdig; 4319 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4320 if (sgdig & BGE_SGDIGSTS_DONE) { 4321 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4322 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4323 sgdig |= BGE_SGDIGCFG_AUTO | 4324 BGE_SGDIGCFG_PAUSE_CAP | 4325 BGE_SGDIGCFG_ASYM_PAUSE; 4326 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4327 sgdig | BGE_SGDIGCFG_SEND); 4328 DELAY(5); 4329 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4330 } 4331 } 4332 break; 4333 case IFM_1000_SX: 4334 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4335 BGE_CLRBIT(sc, BGE_MAC_MODE, 4336 BGE_MACMODE_HALF_DUPLEX); 4337 } else { 4338 BGE_SETBIT(sc, BGE_MAC_MODE, 4339 BGE_MACMODE_HALF_DUPLEX); 4340 } 4341 break; 4342 default: 4343 return (EINVAL); 4344 } 4345 return (0); 4346 } 4347 4348 sc->bge_link_evt++; 4349 mii = device_get_softc(sc->bge_miibus); 4350 if (mii->mii_instance) 4351 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4352 mii_phy_reset(miisc); 4353 mii_mediachg(mii); 4354 4355 /* 4356 * Force an interrupt so that we will call bge_link_upd 4357 * if needed and clear any pending link state attention. 4358 * Without this we are not getting any further interrupts 4359 * for link state changes and thus will not UP the link and 4360 * not be able to send in bge_start_locked. The only 4361 * way to get things working was to receive a packet and 4362 * get an RX intr. 4363 * bge_tick should help for fiber cards and we might not 4364 * need to do this here if BGE_FLAG_TBI is set but as 4365 * we poll for fiber anyway it should not harm. 4366 */ 4367 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4368 sc->bge_flags & BGE_FLAG_5788) 4369 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4370 else 4371 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4372 4373 return (0); 4374 } 4375 4376 /* 4377 * Report current media status. 4378 */ 4379 static void 4380 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4381 { 4382 struct bge_softc *sc = ifp->if_softc; 4383 struct mii_data *mii; 4384 4385 BGE_LOCK(sc); 4386 4387 if (sc->bge_flags & BGE_FLAG_TBI) { 4388 ifmr->ifm_status = IFM_AVALID; 4389 ifmr->ifm_active = IFM_ETHER; 4390 if (CSR_READ_4(sc, BGE_MAC_STS) & 4391 BGE_MACSTAT_TBI_PCS_SYNCHED) 4392 ifmr->ifm_status |= IFM_ACTIVE; 4393 else { 4394 ifmr->ifm_active |= IFM_NONE; 4395 BGE_UNLOCK(sc); 4396 return; 4397 } 4398 ifmr->ifm_active |= IFM_1000_SX; 4399 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4400 ifmr->ifm_active |= IFM_HDX; 4401 else 4402 ifmr->ifm_active |= IFM_FDX; 4403 BGE_UNLOCK(sc); 4404 return; 4405 } 4406 4407 mii = device_get_softc(sc->bge_miibus); 4408 mii_pollstat(mii); 4409 ifmr->ifm_active = mii->mii_media_active; 4410 ifmr->ifm_status = mii->mii_media_status; 4411 4412 BGE_UNLOCK(sc); 4413 } 4414 4415 static int 4416 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4417 { 4418 struct bge_softc *sc = ifp->if_softc; 4419 struct ifreq *ifr = (struct ifreq *) data; 4420 struct mii_data *mii; 4421 int flags, mask, error = 0; 4422 4423 switch (command) { 4424 case SIOCSIFMTU: 4425 if (ifr->ifr_mtu < ETHERMIN || 4426 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4427 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4428 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4429 ifr->ifr_mtu > ETHERMTU)) 4430 error = EINVAL; 4431 else if (ifp->if_mtu != ifr->ifr_mtu) { 4432 ifp->if_mtu = ifr->ifr_mtu; 4433 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4434 bge_init(sc); 4435 } 4436 break; 4437 case SIOCSIFFLAGS: 4438 BGE_LOCK(sc); 4439 if (ifp->if_flags & IFF_UP) { 4440 /* 4441 * If only the state of the PROMISC flag changed, 4442 * then just use the 'set promisc mode' command 4443 * instead of reinitializing the entire NIC. Doing 4444 * a full re-init means reloading the firmware and 4445 * waiting for it to start up, which may take a 4446 * second or two. Similarly for ALLMULTI. 4447 */ 4448 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4449 flags = ifp->if_flags ^ sc->bge_if_flags; 4450 if (flags & IFF_PROMISC) 4451 bge_setpromisc(sc); 4452 if (flags & IFF_ALLMULTI) 4453 bge_setmulti(sc); 4454 } else 4455 bge_init_locked(sc); 4456 } else { 4457 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4458 bge_stop(sc); 4459 } 4460 } 4461 sc->bge_if_flags = ifp->if_flags; 4462 BGE_UNLOCK(sc); 4463 error = 0; 4464 break; 4465 case SIOCADDMULTI: 4466 case SIOCDELMULTI: 4467 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4468 BGE_LOCK(sc); 4469 bge_setmulti(sc); 4470 BGE_UNLOCK(sc); 4471 error = 0; 4472 } 4473 break; 4474 case SIOCSIFMEDIA: 4475 case SIOCGIFMEDIA: 4476 if (sc->bge_flags & BGE_FLAG_TBI) { 4477 error = ifmedia_ioctl(ifp, ifr, 4478 &sc->bge_ifmedia, command); 4479 } else { 4480 mii = device_get_softc(sc->bge_miibus); 4481 error = ifmedia_ioctl(ifp, ifr, 4482 &mii->mii_media, command); 4483 } 4484 break; 4485 case SIOCSIFCAP: 4486 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4487 #ifdef DEVICE_POLLING 4488 if (mask & IFCAP_POLLING) { 4489 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4490 error = ether_poll_register(bge_poll, ifp); 4491 if (error) 4492 return (error); 4493 BGE_LOCK(sc); 4494 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4495 BGE_PCIMISCCTL_MASK_PCI_INTR); 4496 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4497 ifp->if_capenable |= IFCAP_POLLING; 4498 BGE_UNLOCK(sc); 4499 } else { 4500 error = ether_poll_deregister(ifp); 4501 /* Enable interrupt even in error case */ 4502 BGE_LOCK(sc); 4503 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4504 BGE_PCIMISCCTL_MASK_PCI_INTR); 4505 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4506 ifp->if_capenable &= ~IFCAP_POLLING; 4507 BGE_UNLOCK(sc); 4508 } 4509 } 4510 #endif 4511 if (mask & IFCAP_HWCSUM) { 4512 ifp->if_capenable ^= IFCAP_HWCSUM; 4513 if (IFCAP_HWCSUM & ifp->if_capenable && 4514 IFCAP_HWCSUM & ifp->if_capabilities) 4515 ifp->if_hwassist |= BGE_CSUM_FEATURES; 4516 else 4517 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 4518 #ifdef VLAN_CAPABILITIES 4519 VLAN_CAPABILITIES(ifp); 4520 #endif 4521 } 4522 4523 if ((mask & IFCAP_TSO4) != 0 && 4524 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4525 ifp->if_capenable ^= IFCAP_TSO4; 4526 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4527 ifp->if_hwassist |= CSUM_TSO; 4528 else 4529 ifp->if_hwassist &= ~CSUM_TSO; 4530 } 4531 4532 if (mask & IFCAP_VLAN_MTU) { 4533 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4534 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4535 bge_init(sc); 4536 } 4537 4538 if (mask & IFCAP_VLAN_HWTAGGING) { 4539 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4540 BGE_LOCK(sc); 4541 bge_setvlan(sc); 4542 BGE_UNLOCK(sc); 4543 #ifdef VLAN_CAPABILITIES 4544 VLAN_CAPABILITIES(ifp); 4545 #endif 4546 } 4547 4548 break; 4549 default: 4550 error = ether_ioctl(ifp, command, data); 4551 break; 4552 } 4553 4554 return (error); 4555 } 4556 4557 static void 4558 bge_watchdog(struct bge_softc *sc) 4559 { 4560 struct ifnet *ifp; 4561 4562 BGE_LOCK_ASSERT(sc); 4563 4564 if (sc->bge_timer == 0 || --sc->bge_timer) 4565 return; 4566 4567 ifp = sc->bge_ifp; 4568 4569 if_printf(ifp, "watchdog timeout -- resetting\n"); 4570 4571 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4572 bge_init_locked(sc); 4573 4574 ifp->if_oerrors++; 4575 } 4576 4577 /* 4578 * Stop the adapter and free any mbufs allocated to the 4579 * RX and TX lists. 4580 */ 4581 static void 4582 bge_stop(struct bge_softc *sc) 4583 { 4584 struct ifnet *ifp; 4585 4586 BGE_LOCK_ASSERT(sc); 4587 4588 ifp = sc->bge_ifp; 4589 4590 callout_stop(&sc->bge_stat_ch); 4591 4592 /* Disable host interrupts. */ 4593 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4594 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4595 4596 /* 4597 * Tell firmware we're shutting down. 4598 */ 4599 bge_stop_fw(sc); 4600 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4601 4602 /* 4603 * Disable all of the receiver blocks. 4604 */ 4605 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4606 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4607 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4608 if (!(BGE_IS_5705_PLUS(sc))) 4609 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4610 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4611 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4612 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4613 4614 /* 4615 * Disable all of the transmit blocks. 4616 */ 4617 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4618 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4619 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4620 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4621 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4622 if (!(BGE_IS_5705_PLUS(sc))) 4623 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4624 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4625 4626 /* 4627 * Shut down all of the memory managers and related 4628 * state machines. 4629 */ 4630 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4631 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4632 if (!(BGE_IS_5705_PLUS(sc))) 4633 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4634 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4635 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4636 if (!(BGE_IS_5705_PLUS(sc))) { 4637 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4638 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4639 } 4640 4641 bge_reset(sc); 4642 bge_sig_legacy(sc, BGE_RESET_STOP); 4643 bge_sig_post_reset(sc, BGE_RESET_STOP); 4644 4645 /* 4646 * Keep the ASF firmware running if up. 4647 */ 4648 if (sc->bge_asf_mode & ASF_STACKUP) 4649 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4650 else 4651 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4652 4653 /* Free the RX lists. */ 4654 bge_free_rx_ring_std(sc); 4655 4656 /* Free jumbo RX list. */ 4657 if (BGE_IS_JUMBO_CAPABLE(sc)) 4658 bge_free_rx_ring_jumbo(sc); 4659 4660 /* Free TX buffers. */ 4661 bge_free_tx_ring(sc); 4662 4663 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4664 4665 /* Clear MAC's link state (PHY may still have link UP). */ 4666 if (bootverbose && sc->bge_link) 4667 if_printf(sc->bge_ifp, "link DOWN\n"); 4668 sc->bge_link = 0; 4669 4670 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4671 } 4672 4673 /* 4674 * Stop all chip I/O so that the kernel's probe routines don't 4675 * get confused by errant DMAs when rebooting. 4676 */ 4677 static int 4678 bge_shutdown(device_t dev) 4679 { 4680 struct bge_softc *sc; 4681 4682 sc = device_get_softc(dev); 4683 BGE_LOCK(sc); 4684 bge_stop(sc); 4685 bge_reset(sc); 4686 BGE_UNLOCK(sc); 4687 4688 return (0); 4689 } 4690 4691 static int 4692 bge_suspend(device_t dev) 4693 { 4694 struct bge_softc *sc; 4695 4696 sc = device_get_softc(dev); 4697 BGE_LOCK(sc); 4698 bge_stop(sc); 4699 BGE_UNLOCK(sc); 4700 4701 return (0); 4702 } 4703 4704 static int 4705 bge_resume(device_t dev) 4706 { 4707 struct bge_softc *sc; 4708 struct ifnet *ifp; 4709 4710 sc = device_get_softc(dev); 4711 BGE_LOCK(sc); 4712 ifp = sc->bge_ifp; 4713 if (ifp->if_flags & IFF_UP) { 4714 bge_init_locked(sc); 4715 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4716 bge_start_locked(ifp); 4717 } 4718 BGE_UNLOCK(sc); 4719 4720 return (0); 4721 } 4722 4723 static void 4724 bge_link_upd(struct bge_softc *sc) 4725 { 4726 struct mii_data *mii; 4727 uint32_t link, status; 4728 4729 BGE_LOCK_ASSERT(sc); 4730 4731 /* Clear 'pending link event' flag. */ 4732 sc->bge_link_evt = 0; 4733 4734 /* 4735 * Process link state changes. 4736 * Grrr. The link status word in the status block does 4737 * not work correctly on the BCM5700 rev AX and BX chips, 4738 * according to all available information. Hence, we have 4739 * to enable MII interrupts in order to properly obtain 4740 * async link changes. Unfortunately, this also means that 4741 * we have to read the MAC status register to detect link 4742 * changes, thereby adding an additional register access to 4743 * the interrupt handler. 4744 * 4745 * XXX: perhaps link state detection procedure used for 4746 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4747 */ 4748 4749 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4750 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4751 status = CSR_READ_4(sc, BGE_MAC_STS); 4752 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4753 mii = device_get_softc(sc->bge_miibus); 4754 mii_pollstat(mii); 4755 if (!sc->bge_link && 4756 mii->mii_media_status & IFM_ACTIVE && 4757 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4758 sc->bge_link++; 4759 if (bootverbose) 4760 if_printf(sc->bge_ifp, "link UP\n"); 4761 } else if (sc->bge_link && 4762 (!(mii->mii_media_status & IFM_ACTIVE) || 4763 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4764 sc->bge_link = 0; 4765 if (bootverbose) 4766 if_printf(sc->bge_ifp, "link DOWN\n"); 4767 } 4768 4769 /* Clear the interrupt. */ 4770 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4771 BGE_EVTENB_MI_INTERRUPT); 4772 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4773 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4774 BRGPHY_INTRS); 4775 } 4776 return; 4777 } 4778 4779 if (sc->bge_flags & BGE_FLAG_TBI) { 4780 status = CSR_READ_4(sc, BGE_MAC_STS); 4781 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4782 if (!sc->bge_link) { 4783 sc->bge_link++; 4784 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4785 BGE_CLRBIT(sc, BGE_MAC_MODE, 4786 BGE_MACMODE_TBI_SEND_CFGS); 4787 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4788 if (bootverbose) 4789 if_printf(sc->bge_ifp, "link UP\n"); 4790 if_link_state_change(sc->bge_ifp, 4791 LINK_STATE_UP); 4792 } 4793 } else if (sc->bge_link) { 4794 sc->bge_link = 0; 4795 if (bootverbose) 4796 if_printf(sc->bge_ifp, "link DOWN\n"); 4797 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4798 } 4799 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4800 /* 4801 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4802 * in status word always set. Workaround this bug by reading 4803 * PHY link status directly. 4804 */ 4805 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4806 4807 if (link != sc->bge_link || 4808 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4809 mii = device_get_softc(sc->bge_miibus); 4810 mii_pollstat(mii); 4811 if (!sc->bge_link && 4812 mii->mii_media_status & IFM_ACTIVE && 4813 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4814 sc->bge_link++; 4815 if (bootverbose) 4816 if_printf(sc->bge_ifp, "link UP\n"); 4817 } else if (sc->bge_link && 4818 (!(mii->mii_media_status & IFM_ACTIVE) || 4819 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4820 sc->bge_link = 0; 4821 if (bootverbose) 4822 if_printf(sc->bge_ifp, "link DOWN\n"); 4823 } 4824 } 4825 } else { 4826 /* 4827 * Discard link events for MII/GMII controllers 4828 * if MI auto-polling is disabled. 4829 */ 4830 } 4831 4832 /* Clear the attention. */ 4833 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4834 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4835 BGE_MACSTAT_LINK_CHANGED); 4836 } 4837 4838 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4839 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4840 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4841 desc) 4842 4843 static void 4844 bge_add_sysctls(struct bge_softc *sc) 4845 { 4846 struct sysctl_ctx_list *ctx; 4847 struct sysctl_oid_list *children, *schildren; 4848 struct sysctl_oid *tree; 4849 4850 ctx = device_get_sysctl_ctx(sc->bge_dev); 4851 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4852 4853 #ifdef BGE_REGISTER_DEBUG 4854 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4855 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4856 "Debug Information"); 4857 4858 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4859 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4860 "Register Read"); 4861 4862 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4863 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4864 "Memory Read"); 4865 4866 #endif 4867 4868 /* 4869 * A common design characteristic for many Broadcom client controllers 4870 * is that they only support a single outstanding DMA read operation 4871 * on the PCIe bus. This means that it will take twice as long to fetch 4872 * a TX frame that is split into header and payload buffers as it does 4873 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 4874 * these controllers, coalescing buffers to reduce the number of memory 4875 * reads is effective way to get maximum performance(about 940Mbps). 4876 * Without collapsing TX buffers the maximum TCP bulk transfer 4877 * performance is about 850Mbps. However forcing coalescing mbufs 4878 * consumes a lot of CPU cycles, so leave it off by default. 4879 */ 4880 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 4881 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 4882 "Number of fragmented TX buffers of a frame allowed before " 4883 "forced collapsing"); 4884 resource_int_value(device_get_name(sc->bge_dev), 4885 device_get_unit(sc->bge_dev), "forced_collapse", 4886 &sc->bge_forced_collapse); 4887 4888 if (BGE_IS_5705_PLUS(sc)) 4889 return; 4890 4891 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4892 NULL, "BGE Statistics"); 4893 schildren = children = SYSCTL_CHILDREN(tree); 4894 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4895 children, COSFramesDroppedDueToFilters, 4896 "FramesDroppedDueToFilters"); 4897 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4898 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4899 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4900 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4901 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4902 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4903 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4904 children, ifInDiscards, "InputDiscards"); 4905 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4906 children, ifInErrors, "InputErrors"); 4907 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4908 children, nicRecvThresholdHit, "RecvThresholdHit"); 4909 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4910 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4911 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4912 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4913 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4914 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4915 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4916 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4917 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4918 children, nicRingStatusUpdate, "RingStatusUpdate"); 4919 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4920 children, nicInterrupts, "Interrupts"); 4921 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4922 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4923 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4924 children, nicSendThresholdHit, "SendThresholdHit"); 4925 4926 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4927 NULL, "BGE RX Statistics"); 4928 children = SYSCTL_CHILDREN(tree); 4929 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4930 children, rxstats.ifHCInOctets, "Octets"); 4931 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4932 children, rxstats.etherStatsFragments, "Fragments"); 4933 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4934 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4935 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4936 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4937 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4938 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4939 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4940 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4941 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4942 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4943 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4944 children, rxstats.xoffPauseFramesReceived, 4945 "xoffPauseFramesReceived"); 4946 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4947 children, rxstats.macControlFramesReceived, 4948 "ControlFramesReceived"); 4949 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4950 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4951 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4952 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4953 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4954 children, rxstats.etherStatsJabbers, "Jabbers"); 4955 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4956 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4957 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4958 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4959 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4960 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4961 4962 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4963 NULL, "BGE TX Statistics"); 4964 children = SYSCTL_CHILDREN(tree); 4965 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4966 children, txstats.ifHCOutOctets, "Octets"); 4967 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4968 children, txstats.etherStatsCollisions, "Collisions"); 4969 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4970 children, txstats.outXonSent, "XonSent"); 4971 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4972 children, txstats.outXoffSent, "XoffSent"); 4973 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4974 children, txstats.flowControlDone, "flowControlDone"); 4975 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4976 children, txstats.dot3StatsInternalMacTransmitErrors, 4977 "InternalMacTransmitErrors"); 4978 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4979 children, txstats.dot3StatsSingleCollisionFrames, 4980 "SingleCollisionFrames"); 4981 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4982 children, txstats.dot3StatsMultipleCollisionFrames, 4983 "MultipleCollisionFrames"); 4984 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4985 children, txstats.dot3StatsDeferredTransmissions, 4986 "DeferredTransmissions"); 4987 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4988 children, txstats.dot3StatsExcessiveCollisions, 4989 "ExcessiveCollisions"); 4990 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4991 children, txstats.dot3StatsLateCollisions, 4992 "LateCollisions"); 4993 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4994 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4995 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4996 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4997 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4998 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4999 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5000 children, txstats.dot3StatsCarrierSenseErrors, 5001 "CarrierSenseErrors"); 5002 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5003 children, txstats.ifOutDiscards, "Discards"); 5004 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5005 children, txstats.ifOutErrors, "Errors"); 5006 } 5007 5008 static int 5009 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5010 { 5011 struct bge_softc *sc; 5012 uint32_t result; 5013 int offset; 5014 5015 sc = (struct bge_softc *)arg1; 5016 offset = arg2; 5017 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5018 offsetof(bge_hostaddr, bge_addr_lo)); 5019 return (sysctl_handle_int(oidp, &result, 0, req)); 5020 } 5021 5022 #ifdef BGE_REGISTER_DEBUG 5023 static int 5024 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5025 { 5026 struct bge_softc *sc; 5027 uint16_t *sbdata; 5028 int error; 5029 int result; 5030 int i, j; 5031 5032 result = -1; 5033 error = sysctl_handle_int(oidp, &result, 0, req); 5034 if (error || (req->newptr == NULL)) 5035 return (error); 5036 5037 if (result == 1) { 5038 sc = (struct bge_softc *)arg1; 5039 5040 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5041 printf("Status Block:\n"); 5042 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5043 printf("%06x:", i); 5044 for (j = 0; j < 8; j++) { 5045 printf(" %04x", sbdata[i]); 5046 i += 4; 5047 } 5048 printf("\n"); 5049 } 5050 5051 printf("Registers:\n"); 5052 for (i = 0x800; i < 0xA00; ) { 5053 printf("%06x:", i); 5054 for (j = 0; j < 8; j++) { 5055 printf(" %08x", CSR_READ_4(sc, i)); 5056 i += 4; 5057 } 5058 printf("\n"); 5059 } 5060 5061 printf("Hardware Flags:\n"); 5062 if (BGE_IS_5755_PLUS(sc)) 5063 printf(" - 5755 Plus\n"); 5064 if (BGE_IS_575X_PLUS(sc)) 5065 printf(" - 575X Plus\n"); 5066 if (BGE_IS_5705_PLUS(sc)) 5067 printf(" - 5705 Plus\n"); 5068 if (BGE_IS_5714_FAMILY(sc)) 5069 printf(" - 5714 Family\n"); 5070 if (BGE_IS_5700_FAMILY(sc)) 5071 printf(" - 5700 Family\n"); 5072 if (sc->bge_flags & BGE_FLAG_JUMBO) 5073 printf(" - Supports Jumbo Frames\n"); 5074 if (sc->bge_flags & BGE_FLAG_PCIX) 5075 printf(" - PCI-X Bus\n"); 5076 if (sc->bge_flags & BGE_FLAG_PCIE) 5077 printf(" - PCI Express Bus\n"); 5078 if (sc->bge_flags & BGE_FLAG_NO_3LED) 5079 printf(" - No 3 LEDs\n"); 5080 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5081 printf(" - RX Alignment Bug\n"); 5082 } 5083 5084 return (error); 5085 } 5086 5087 static int 5088 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5089 { 5090 struct bge_softc *sc; 5091 int error; 5092 uint16_t result; 5093 uint32_t val; 5094 5095 result = -1; 5096 error = sysctl_handle_int(oidp, &result, 0, req); 5097 if (error || (req->newptr == NULL)) 5098 return (error); 5099 5100 if (result < 0x8000) { 5101 sc = (struct bge_softc *)arg1; 5102 val = CSR_READ_4(sc, result); 5103 printf("reg 0x%06X = 0x%08X\n", result, val); 5104 } 5105 5106 return (error); 5107 } 5108 5109 static int 5110 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5111 { 5112 struct bge_softc *sc; 5113 int error; 5114 uint16_t result; 5115 uint32_t val; 5116 5117 result = -1; 5118 error = sysctl_handle_int(oidp, &result, 0, req); 5119 if (error || (req->newptr == NULL)) 5120 return (error); 5121 5122 if (result < 0x8000) { 5123 sc = (struct bge_softc *)arg1; 5124 val = bge_readmem_ind(sc, result); 5125 printf("mem 0x%06X = 0x%08X\n", result, val); 5126 } 5127 5128 return (error); 5129 } 5130 #endif 5131 5132 static int 5133 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5134 { 5135 5136 if (sc->bge_flags & BGE_FLAG_EADDR) 5137 return (1); 5138 5139 #ifdef __sparc64__ 5140 OF_getetheraddr(sc->bge_dev, ether_addr); 5141 return (0); 5142 #endif 5143 return (1); 5144 } 5145 5146 static int 5147 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5148 { 5149 uint32_t mac_addr; 5150 5151 mac_addr = bge_readmem_ind(sc, 0x0c14); 5152 if ((mac_addr >> 16) == 0x484b) { 5153 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5154 ether_addr[1] = (uint8_t)mac_addr; 5155 mac_addr = bge_readmem_ind(sc, 0x0c18); 5156 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5157 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5158 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5159 ether_addr[5] = (uint8_t)mac_addr; 5160 return (0); 5161 } 5162 return (1); 5163 } 5164 5165 static int 5166 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5167 { 5168 int mac_offset = BGE_EE_MAC_OFFSET; 5169 5170 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5171 mac_offset = BGE_EE_MAC_OFFSET_5906; 5172 5173 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5174 ETHER_ADDR_LEN)); 5175 } 5176 5177 static int 5178 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5179 { 5180 5181 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5182 return (1); 5183 5184 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5185 ETHER_ADDR_LEN)); 5186 } 5187 5188 static int 5189 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5190 { 5191 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5192 /* NOTE: Order is critical */ 5193 bge_get_eaddr_fw, 5194 bge_get_eaddr_mem, 5195 bge_get_eaddr_nvram, 5196 bge_get_eaddr_eeprom, 5197 NULL 5198 }; 5199 const bge_eaddr_fcn_t *func; 5200 5201 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5202 if ((*func)(sc, eaddr) == 0) 5203 break; 5204 } 5205 return (*func == NULL ? ENXIO : 0); 5206 } 5207