1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 201 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 203 204 { TC_VENDORID, TC_DEVICEID_3C996 }, 205 206 { 0, 0 } 207 }; 208 209 static const struct bge_vendor { 210 uint16_t v_id; 211 const char *v_name; 212 } bge_vendors[] = { 213 { ALTEON_VENDORID, "Alteon" }, 214 { ALTIMA_VENDORID, "Altima" }, 215 { APPLE_VENDORID, "Apple" }, 216 { BCOM_VENDORID, "Broadcom" }, 217 { SK_VENDORID, "SysKonnect" }, 218 { TC_VENDORID, "3Com" }, 219 220 { 0, NULL } 221 }; 222 223 static const struct bge_revision { 224 uint32_t br_chipid; 225 const char *br_name; 226 } bge_revisions[] = { 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 274 /* 5754 and 5787 share the same ASIC ID */ 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 280 281 { 0, NULL } 282 }; 283 284 /* 285 * Some defaults for major revisions, so that newer steppings 286 * that we don't know about have a shot at working. 287 */ 288 static const struct bge_revision bge_majorrevs[] = { 289 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 290 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 291 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 292 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 293 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 294 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 296 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 297 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 298 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 303 304 { 0, NULL } 305 }; 306 307 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 308 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 309 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 310 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 311 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 312 313 const struct bge_revision * bge_lookup_rev(uint32_t); 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 318 static int bge_probe(device_t); 319 static int bge_attach(device_t); 320 static int bge_detach(device_t); 321 static int bge_suspend(device_t); 322 static int bge_resume(device_t); 323 static void bge_release_resources(struct bge_softc *); 324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 325 static int bge_dma_alloc(device_t); 326 static void bge_dma_free(struct bge_softc *); 327 328 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 329 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 332 333 static void bge_txeof(struct bge_softc *); 334 static void bge_rxeof(struct bge_softc *); 335 336 static void bge_asf_driver_up (struct bge_softc *); 337 static void bge_tick(void *); 338 static void bge_stats_update(struct bge_softc *); 339 static void bge_stats_update_regs(struct bge_softc *); 340 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 341 342 static void bge_intr(void *); 343 static void bge_start_locked(struct ifnet *); 344 static void bge_start(struct ifnet *); 345 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 346 static void bge_init_locked(struct bge_softc *); 347 static void bge_init(void *); 348 static void bge_stop(struct bge_softc *); 349 static void bge_watchdog(struct bge_softc *); 350 static void bge_shutdown(device_t); 351 static int bge_ifmedia_upd_locked(struct ifnet *); 352 static int bge_ifmedia_upd(struct ifnet *); 353 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 354 355 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 356 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 357 358 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 359 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 360 361 static void bge_setpromisc(struct bge_softc *); 362 static void bge_setmulti(struct bge_softc *); 363 static void bge_setvlan(struct bge_softc *); 364 365 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 366 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 367 static int bge_init_rx_ring_std(struct bge_softc *); 368 static void bge_free_rx_ring_std(struct bge_softc *); 369 static int bge_init_rx_ring_jumbo(struct bge_softc *); 370 static void bge_free_rx_ring_jumbo(struct bge_softc *); 371 static void bge_free_tx_ring(struct bge_softc *); 372 static int bge_init_tx_ring(struct bge_softc *); 373 374 static int bge_chipinit(struct bge_softc *); 375 static int bge_blockinit(struct bge_softc *); 376 377 static int bge_has_eeprom(struct bge_softc *); 378 static uint32_t bge_readmem_ind(struct bge_softc *, int); 379 static void bge_writemem_ind(struct bge_softc *, int, int); 380 static void bge_writembx(struct bge_softc *, int, int); 381 #ifdef notdef 382 static uint32_t bge_readreg_ind(struct bge_softc *, int); 383 #endif 384 static void bge_writemem_direct(struct bge_softc *, int, int); 385 static void bge_writereg_ind(struct bge_softc *, int, int); 386 387 static int bge_miibus_readreg(device_t, int, int); 388 static int bge_miibus_writereg(device_t, int, int, int); 389 static void bge_miibus_statchg(device_t); 390 #ifdef DEVICE_POLLING 391 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 392 #endif 393 394 #define BGE_RESET_START 1 395 #define BGE_RESET_STOP 2 396 static void bge_sig_post_reset(struct bge_softc *, int); 397 static void bge_sig_legacy(struct bge_softc *, int); 398 static void bge_sig_pre_reset(struct bge_softc *, int); 399 static int bge_reset(struct bge_softc *); 400 static void bge_link_upd(struct bge_softc *); 401 402 /* 403 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 404 * leak information to untrusted users. It is also known to cause alignment 405 * traps on certain architectures. 406 */ 407 #ifdef BGE_REGISTER_DEBUG 408 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 409 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 411 #endif 412 static void bge_add_sysctls(struct bge_softc *); 413 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 414 415 static device_method_t bge_methods[] = { 416 /* Device interface */ 417 DEVMETHOD(device_probe, bge_probe), 418 DEVMETHOD(device_attach, bge_attach), 419 DEVMETHOD(device_detach, bge_detach), 420 DEVMETHOD(device_shutdown, bge_shutdown), 421 DEVMETHOD(device_suspend, bge_suspend), 422 DEVMETHOD(device_resume, bge_resume), 423 424 /* bus interface */ 425 DEVMETHOD(bus_print_child, bus_generic_print_child), 426 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 427 428 /* MII interface */ 429 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 430 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 431 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 432 433 { 0, 0 } 434 }; 435 436 static driver_t bge_driver = { 437 "bge", 438 bge_methods, 439 sizeof(struct bge_softc) 440 }; 441 442 static devclass_t bge_devclass; 443 444 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 445 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 446 447 static int bge_allow_asf = 1; 448 449 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 450 451 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 452 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 453 "Allow ASF mode if available"); 454 455 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 456 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 457 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 458 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 459 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 460 461 static int 462 bge_has_eeprom(struct bge_softc *sc) 463 { 464 #ifdef __sparc64__ 465 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 466 device_t dev; 467 uint32_t subvendor; 468 469 dev = sc->bge_dev; 470 471 /* 472 * The on-board BGEs found in sun4u machines aren't fitted with 473 * an EEPROM which means that we have to obtain the MAC address 474 * via OFW and that some tests will always fail. We distinguish 475 * such BGEs by the subvendor ID, which also has to be obtained 476 * from OFW instead of the PCI configuration space as the latter 477 * indicates Broadcom as the subvendor of the netboot interface. 478 * For early Blade 1500 and 2500 we even have to check the OFW 479 * device path as the subvendor ID always defaults to Broadcom 480 * there. 481 */ 482 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 483 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 484 subvendor == SUN_VENDORID) 485 return (0); 486 memset(buf, 0, sizeof(buf)); 487 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 488 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 489 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 490 return (0); 491 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 492 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 493 return (0); 494 } 495 #endif 496 497 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 498 return (0); 499 500 return (1); 501 } 502 503 static uint32_t 504 bge_readmem_ind(struct bge_softc *sc, int off) 505 { 506 device_t dev; 507 uint32_t val; 508 509 dev = sc->bge_dev; 510 511 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 512 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 513 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 514 return (val); 515 } 516 517 static void 518 bge_writemem_ind(struct bge_softc *sc, int off, int val) 519 { 520 device_t dev; 521 522 dev = sc->bge_dev; 523 524 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 525 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 526 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 527 } 528 529 #ifdef notdef 530 static uint32_t 531 bge_readreg_ind(struct bge_softc *sc, int off) 532 { 533 device_t dev; 534 535 dev = sc->bge_dev; 536 537 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 538 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 539 } 540 #endif 541 542 static void 543 bge_writereg_ind(struct bge_softc *sc, int off, int val) 544 { 545 device_t dev; 546 547 dev = sc->bge_dev; 548 549 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 550 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 551 } 552 553 static void 554 bge_writemem_direct(struct bge_softc *sc, int off, int val) 555 { 556 CSR_WRITE_4(sc, off, val); 557 } 558 559 static void 560 bge_writembx(struct bge_softc *sc, int off, int val) 561 { 562 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 563 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 564 565 CSR_WRITE_4(sc, off, val); 566 } 567 568 /* 569 * Map a single buffer address. 570 */ 571 572 static void 573 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 574 { 575 struct bge_dmamap_arg *ctx; 576 577 if (error) 578 return; 579 580 ctx = arg; 581 582 if (nseg > ctx->bge_maxsegs) { 583 ctx->bge_maxsegs = 0; 584 return; 585 } 586 587 ctx->bge_busaddr = segs->ds_addr; 588 } 589 590 static uint8_t 591 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 592 { 593 uint32_t access, byte = 0; 594 int i; 595 596 /* Lock. */ 597 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 598 for (i = 0; i < 8000; i++) { 599 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 600 break; 601 DELAY(20); 602 } 603 if (i == 8000) 604 return (1); 605 606 /* Enable access. */ 607 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 608 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 609 610 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 611 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 612 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 613 DELAY(10); 614 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 615 DELAY(10); 616 break; 617 } 618 } 619 620 if (i == BGE_TIMEOUT * 10) { 621 if_printf(sc->bge_ifp, "nvram read timed out\n"); 622 return (1); 623 } 624 625 /* Get result. */ 626 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 627 628 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 629 630 /* Disable access. */ 631 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 632 633 /* Unlock. */ 634 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 635 CSR_READ_4(sc, BGE_NVRAM_SWARB); 636 637 return (0); 638 } 639 640 /* 641 * Read a sequence of bytes from NVRAM. 642 */ 643 static int 644 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 645 { 646 int err = 0, i; 647 uint8_t byte = 0; 648 649 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 650 return (1); 651 652 for (i = 0; i < cnt; i++) { 653 err = bge_nvram_getbyte(sc, off + i, &byte); 654 if (err) 655 break; 656 *(dest + i) = byte; 657 } 658 659 return (err ? 1 : 0); 660 } 661 662 /* 663 * Read a byte of data stored in the EEPROM at address 'addr.' The 664 * BCM570x supports both the traditional bitbang interface and an 665 * auto access interface for reading the EEPROM. We use the auto 666 * access method. 667 */ 668 static uint8_t 669 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 670 { 671 int i; 672 uint32_t byte = 0; 673 674 /* 675 * Enable use of auto EEPROM access so we can avoid 676 * having to use the bitbang method. 677 */ 678 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 679 680 /* Reset the EEPROM, load the clock period. */ 681 CSR_WRITE_4(sc, BGE_EE_ADDR, 682 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 683 DELAY(20); 684 685 /* Issue the read EEPROM command. */ 686 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 687 688 /* Wait for completion */ 689 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 690 DELAY(10); 691 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 692 break; 693 } 694 695 if (i == BGE_TIMEOUT * 10) { 696 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 697 return (1); 698 } 699 700 /* Get result. */ 701 byte = CSR_READ_4(sc, BGE_EE_DATA); 702 703 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 704 705 return (0); 706 } 707 708 /* 709 * Read a sequence of bytes from the EEPROM. 710 */ 711 static int 712 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 713 { 714 int i, error = 0; 715 uint8_t byte = 0; 716 717 for (i = 0; i < cnt; i++) { 718 error = bge_eeprom_getbyte(sc, off + i, &byte); 719 if (error) 720 break; 721 *(dest + i) = byte; 722 } 723 724 return (error ? 1 : 0); 725 } 726 727 static int 728 bge_miibus_readreg(device_t dev, int phy, int reg) 729 { 730 struct bge_softc *sc; 731 uint32_t val, autopoll; 732 int i; 733 734 sc = device_get_softc(dev); 735 736 /* 737 * Broadcom's own driver always assumes the internal 738 * PHY is at GMII address 1. On some chips, the PHY responds 739 * to accesses at all addresses, which could cause us to 740 * bogusly attach the PHY 32 times at probe type. Always 741 * restricting the lookup to address 1 is simpler than 742 * trying to figure out which chips revisions should be 743 * special-cased. 744 */ 745 if (phy != 1) 746 return (0); 747 748 /* Reading with autopolling on may trigger PCI errors */ 749 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 750 if (autopoll & BGE_MIMODE_AUTOPOLL) { 751 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 752 DELAY(40); 753 } 754 755 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 756 BGE_MIPHY(phy) | BGE_MIREG(reg)); 757 758 for (i = 0; i < BGE_TIMEOUT; i++) { 759 DELAY(10); 760 val = CSR_READ_4(sc, BGE_MI_COMM); 761 if (!(val & BGE_MICOMM_BUSY)) 762 break; 763 } 764 765 if (i == BGE_TIMEOUT) { 766 device_printf(sc->bge_dev, "PHY read timed out " 767 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 768 val = 0; 769 goto done; 770 } 771 772 DELAY(5); 773 val = CSR_READ_4(sc, BGE_MI_COMM); 774 775 done: 776 if (autopoll & BGE_MIMODE_AUTOPOLL) { 777 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 778 DELAY(40); 779 } 780 781 if (val & BGE_MICOMM_READFAIL) 782 return (0); 783 784 return (val & 0xFFFF); 785 } 786 787 static int 788 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 789 { 790 struct bge_softc *sc; 791 uint32_t autopoll; 792 int i; 793 794 sc = device_get_softc(dev); 795 796 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 797 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 798 return(0); 799 800 /* Reading with autopolling on may trigger PCI errors */ 801 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 802 if (autopoll & BGE_MIMODE_AUTOPOLL) { 803 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 804 DELAY(40); 805 } 806 807 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 808 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 809 810 for (i = 0; i < BGE_TIMEOUT; i++) { 811 DELAY(10); 812 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 813 DELAY(5); 814 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 815 break; 816 } 817 } 818 819 if (i == BGE_TIMEOUT) { 820 device_printf(sc->bge_dev, 821 "PHY write timed out (phy %d, reg %d, val %d)\n", 822 phy, reg, val); 823 return (0); 824 } 825 826 if (autopoll & BGE_MIMODE_AUTOPOLL) { 827 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 828 DELAY(40); 829 } 830 831 return (0); 832 } 833 834 static void 835 bge_miibus_statchg(device_t dev) 836 { 837 struct bge_softc *sc; 838 struct mii_data *mii; 839 sc = device_get_softc(dev); 840 mii = device_get_softc(sc->bge_miibus); 841 842 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 843 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 844 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 845 else 846 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 847 848 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 849 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 850 else 851 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 852 } 853 854 /* 855 * Intialize a standard receive ring descriptor. 856 */ 857 static int 858 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 859 { 860 struct mbuf *m_new = NULL; 861 struct bge_rx_bd *r; 862 struct bge_dmamap_arg ctx; 863 int error; 864 865 if (m == NULL) { 866 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 867 if (m_new == NULL) 868 return (ENOBUFS); 869 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 870 } else { 871 m_new = m; 872 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 873 m_new->m_data = m_new->m_ext.ext_buf; 874 } 875 876 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 877 m_adj(m_new, ETHER_ALIGN); 878 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 879 r = &sc->bge_ldata.bge_rx_std_ring[i]; 880 ctx.bge_maxsegs = 1; 881 ctx.sc = sc; 882 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 883 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 884 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 885 if (error || ctx.bge_maxsegs == 0) { 886 if (m == NULL) { 887 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 888 m_freem(m_new); 889 } 890 return (ENOMEM); 891 } 892 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 893 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 894 r->bge_flags = BGE_RXBDFLAG_END; 895 r->bge_len = m_new->m_len; 896 r->bge_idx = i; 897 898 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 899 sc->bge_cdata.bge_rx_std_dmamap[i], 900 BUS_DMASYNC_PREREAD); 901 902 return (0); 903 } 904 905 /* 906 * Initialize a jumbo receive ring descriptor. This allocates 907 * a jumbo buffer from the pool managed internally by the driver. 908 */ 909 static int 910 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 911 { 912 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 913 struct bge_extrx_bd *r; 914 struct mbuf *m_new = NULL; 915 int nsegs; 916 int error; 917 918 if (m == NULL) { 919 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 920 if (m_new == NULL) 921 return (ENOBUFS); 922 923 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 924 if (!(m_new->m_flags & M_EXT)) { 925 m_freem(m_new); 926 return (ENOBUFS); 927 } 928 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 929 } else { 930 m_new = m; 931 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 932 m_new->m_data = m_new->m_ext.ext_buf; 933 } 934 935 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 936 m_adj(m_new, ETHER_ALIGN); 937 938 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 939 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 940 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 941 if (error) { 942 if (m == NULL) 943 m_freem(m_new); 944 return (error); 945 } 946 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 947 948 /* 949 * Fill in the extended RX buffer descriptor. 950 */ 951 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 952 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 953 r->bge_idx = i; 954 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 955 switch (nsegs) { 956 case 4: 957 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 958 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 959 r->bge_len3 = segs[3].ds_len; 960 case 3: 961 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 962 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 963 r->bge_len2 = segs[2].ds_len; 964 case 2: 965 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 966 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 967 r->bge_len1 = segs[1].ds_len; 968 case 1: 969 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 970 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 971 r->bge_len0 = segs[0].ds_len; 972 break; 973 default: 974 panic("%s: %d segments\n", __func__, nsegs); 975 } 976 977 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 978 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 979 BUS_DMASYNC_PREREAD); 980 981 return (0); 982 } 983 984 /* 985 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 986 * that's 1MB or memory, which is a lot. For now, we fill only the first 987 * 256 ring entries and hope that our CPU is fast enough to keep up with 988 * the NIC. 989 */ 990 static int 991 bge_init_rx_ring_std(struct bge_softc *sc) 992 { 993 int i; 994 995 for (i = 0; i < BGE_SSLOTS; i++) { 996 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 997 return (ENOBUFS); 998 }; 999 1000 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1001 sc->bge_cdata.bge_rx_std_ring_map, 1002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1003 1004 sc->bge_std = i - 1; 1005 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1006 1007 return (0); 1008 } 1009 1010 static void 1011 bge_free_rx_ring_std(struct bge_softc *sc) 1012 { 1013 int i; 1014 1015 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1016 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1017 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1018 sc->bge_cdata.bge_rx_std_dmamap[i], 1019 BUS_DMASYNC_POSTREAD); 1020 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1021 sc->bge_cdata.bge_rx_std_dmamap[i]); 1022 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1023 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1024 } 1025 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1026 sizeof(struct bge_rx_bd)); 1027 } 1028 } 1029 1030 static int 1031 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1032 { 1033 struct bge_rcb *rcb; 1034 int i; 1035 1036 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1037 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1038 return (ENOBUFS); 1039 }; 1040 1041 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1042 sc->bge_cdata.bge_rx_jumbo_ring_map, 1043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1044 1045 sc->bge_jumbo = i - 1; 1046 1047 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1048 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1049 BGE_RCB_FLAG_USE_EXT_RX_BD); 1050 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1051 1052 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1053 1054 return (0); 1055 } 1056 1057 static void 1058 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1059 { 1060 int i; 1061 1062 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1063 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1064 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1065 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1066 BUS_DMASYNC_POSTREAD); 1067 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1068 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1069 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1070 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1071 } 1072 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1073 sizeof(struct bge_extrx_bd)); 1074 } 1075 } 1076 1077 static void 1078 bge_free_tx_ring(struct bge_softc *sc) 1079 { 1080 int i; 1081 1082 if (sc->bge_ldata.bge_tx_ring == NULL) 1083 return; 1084 1085 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1086 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1087 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1088 sc->bge_cdata.bge_tx_dmamap[i], 1089 BUS_DMASYNC_POSTWRITE); 1090 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1091 sc->bge_cdata.bge_tx_dmamap[i]); 1092 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1093 sc->bge_cdata.bge_tx_chain[i] = NULL; 1094 } 1095 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1096 sizeof(struct bge_tx_bd)); 1097 } 1098 } 1099 1100 static int 1101 bge_init_tx_ring(struct bge_softc *sc) 1102 { 1103 sc->bge_txcnt = 0; 1104 sc->bge_tx_saved_considx = 0; 1105 1106 /* Initialize transmit producer index for host-memory send ring. */ 1107 sc->bge_tx_prodidx = 0; 1108 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1109 1110 /* 5700 b2 errata */ 1111 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1112 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1113 1114 /* NIC-memory send ring not used; initialize to zero. */ 1115 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1116 /* 5700 b2 errata */ 1117 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1118 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1119 1120 return (0); 1121 } 1122 1123 static void 1124 bge_setpromisc(struct bge_softc *sc) 1125 { 1126 struct ifnet *ifp; 1127 1128 BGE_LOCK_ASSERT(sc); 1129 1130 ifp = sc->bge_ifp; 1131 1132 /* Enable or disable promiscuous mode as needed. */ 1133 if (ifp->if_flags & IFF_PROMISC) 1134 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1135 else 1136 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1137 } 1138 1139 static void 1140 bge_setmulti(struct bge_softc *sc) 1141 { 1142 struct ifnet *ifp; 1143 struct ifmultiaddr *ifma; 1144 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1145 int h, i; 1146 1147 BGE_LOCK_ASSERT(sc); 1148 1149 ifp = sc->bge_ifp; 1150 1151 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1152 for (i = 0; i < 4; i++) 1153 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1154 return; 1155 } 1156 1157 /* First, zot all the existing filters. */ 1158 for (i = 0; i < 4; i++) 1159 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1160 1161 /* Now program new ones. */ 1162 IF_ADDR_LOCK(ifp); 1163 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1164 if (ifma->ifma_addr->sa_family != AF_LINK) 1165 continue; 1166 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1167 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1168 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1169 } 1170 IF_ADDR_UNLOCK(ifp); 1171 1172 for (i = 0; i < 4; i++) 1173 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1174 } 1175 1176 static void 1177 bge_setvlan(struct bge_softc *sc) 1178 { 1179 struct ifnet *ifp; 1180 1181 BGE_LOCK_ASSERT(sc); 1182 1183 ifp = sc->bge_ifp; 1184 1185 /* Enable or disable VLAN tag stripping as needed. */ 1186 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1187 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1188 else 1189 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1190 } 1191 1192 static void 1193 bge_sig_pre_reset(sc, type) 1194 struct bge_softc *sc; 1195 int type; 1196 { 1197 /* 1198 * Some chips don't like this so only do this if ASF is enabled 1199 */ 1200 if (sc->bge_asf_mode) 1201 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1202 1203 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1204 switch (type) { 1205 case BGE_RESET_START: 1206 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1207 break; 1208 case BGE_RESET_STOP: 1209 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1210 break; 1211 } 1212 } 1213 } 1214 1215 static void 1216 bge_sig_post_reset(sc, type) 1217 struct bge_softc *sc; 1218 int type; 1219 { 1220 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1221 switch (type) { 1222 case BGE_RESET_START: 1223 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1224 /* START DONE */ 1225 break; 1226 case BGE_RESET_STOP: 1227 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1228 break; 1229 } 1230 } 1231 } 1232 1233 static void 1234 bge_sig_legacy(sc, type) 1235 struct bge_softc *sc; 1236 int type; 1237 { 1238 if (sc->bge_asf_mode) { 1239 switch (type) { 1240 case BGE_RESET_START: 1241 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1242 break; 1243 case BGE_RESET_STOP: 1244 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1245 break; 1246 } 1247 } 1248 } 1249 1250 void bge_stop_fw(struct bge_softc *); 1251 void 1252 bge_stop_fw(sc) 1253 struct bge_softc *sc; 1254 { 1255 int i; 1256 1257 if (sc->bge_asf_mode) { 1258 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1259 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1260 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1261 1262 for (i = 0; i < 100; i++ ) { 1263 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1264 break; 1265 DELAY(10); 1266 } 1267 } 1268 } 1269 1270 /* 1271 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1272 * self-test results. 1273 */ 1274 static int 1275 bge_chipinit(struct bge_softc *sc) 1276 { 1277 uint32_t dma_rw_ctl; 1278 int i; 1279 1280 /* Set endianness before we access any non-PCI registers. */ 1281 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1282 1283 /* 1284 * Check the 'ROM failed' bit on the RX CPU to see if 1285 * self-tests passed. Skip this check when there's no 1286 * EEPROM fitted, since in that case it will always 1287 * fail. 1288 */ 1289 if ((sc->bge_flags & BGE_FLAG_EEPROM) && 1290 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1291 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1292 return (ENODEV); 1293 } 1294 1295 /* Clear the MAC control register */ 1296 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1297 1298 /* 1299 * Clear the MAC statistics block in the NIC's 1300 * internal memory. 1301 */ 1302 for (i = BGE_STATS_BLOCK; 1303 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1304 BGE_MEMWIN_WRITE(sc, i, 0); 1305 1306 for (i = BGE_STATUS_BLOCK; 1307 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1308 BGE_MEMWIN_WRITE(sc, i, 0); 1309 1310 /* 1311 * Set up the PCI DMA control register. 1312 */ 1313 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1314 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1315 if (sc->bge_flags & BGE_FLAG_PCIE) { 1316 /* Read watermark not used, 128 bytes for write. */ 1317 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1318 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1319 if (BGE_IS_5714_FAMILY(sc)) { 1320 /* 256 bytes for read and write. */ 1321 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1322 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1323 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1324 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1325 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1326 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1327 /* 1536 bytes for read, 384 bytes for write. */ 1328 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1329 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1330 } else { 1331 /* 384 bytes for read and write. */ 1332 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1333 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1334 0x0F; 1335 } 1336 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1337 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1338 uint32_t tmp; 1339 1340 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1341 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1342 if (tmp == 6 || tmp == 7) 1343 dma_rw_ctl |= 1344 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1345 1346 /* Set PCI-X DMA write workaround. */ 1347 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1348 } 1349 } else { 1350 /* Conventional PCI bus: 256 bytes for read and write. */ 1351 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1352 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1353 1354 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1355 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1356 dma_rw_ctl |= 0x0F; 1357 } 1358 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1359 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1360 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1361 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1362 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1363 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1364 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1365 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1366 1367 /* 1368 * Set up general mode register. 1369 */ 1370 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1371 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1372 BGE_MODECTL_TX_NO_PHDR_CSUM); 1373 1374 /* 1375 * Tell the firmware the driver is running 1376 */ 1377 if (sc->bge_asf_mode & ASF_STACKUP) 1378 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1379 1380 /* 1381 * Disable memory write invalidate. Apparently it is not supported 1382 * properly by these devices. 1383 */ 1384 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1385 1386 /* Set the timer prescaler (always 66Mhz) */ 1387 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1388 1389 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1390 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1391 DELAY(40); /* XXX */ 1392 1393 /* Put PHY into ready state */ 1394 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1395 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1396 DELAY(40); 1397 } 1398 1399 return (0); 1400 } 1401 1402 static int 1403 bge_blockinit(struct bge_softc *sc) 1404 { 1405 struct bge_rcb *rcb; 1406 bus_size_t vrcb; 1407 bge_hostaddr taddr; 1408 uint32_t val; 1409 int i; 1410 1411 /* 1412 * Initialize the memory window pointer register so that 1413 * we can access the first 32K of internal NIC RAM. This will 1414 * allow us to set up the TX send ring RCBs and the RX return 1415 * ring RCBs, plus other things which live in NIC memory. 1416 */ 1417 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1418 1419 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1420 1421 if (!(BGE_IS_5705_PLUS(sc))) { 1422 /* Configure mbuf memory pool */ 1423 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1424 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1426 else 1427 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1428 1429 /* Configure DMA resource pool */ 1430 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1431 BGE_DMA_DESCRIPTORS); 1432 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1433 } 1434 1435 /* Configure mbuf pool watermarks */ 1436 if (!BGE_IS_5705_PLUS(sc)) { 1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1438 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1440 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1442 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1444 } else { 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1448 } 1449 1450 /* Configure DMA resource watermarks */ 1451 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1452 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1453 1454 /* Enable buffer manager */ 1455 if (!(BGE_IS_5705_PLUS(sc))) { 1456 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1457 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1458 1459 /* Poll for buffer manager start indication */ 1460 for (i = 0; i < BGE_TIMEOUT; i++) { 1461 DELAY(10); 1462 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1463 break; 1464 } 1465 1466 if (i == BGE_TIMEOUT) { 1467 device_printf(sc->bge_dev, 1468 "buffer manager failed to start\n"); 1469 return (ENXIO); 1470 } 1471 } 1472 1473 /* Enable flow-through queues */ 1474 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1475 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1476 1477 /* Wait until queue initialization is complete */ 1478 for (i = 0; i < BGE_TIMEOUT; i++) { 1479 DELAY(10); 1480 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1481 break; 1482 } 1483 1484 if (i == BGE_TIMEOUT) { 1485 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1486 return (ENXIO); 1487 } 1488 1489 /* Initialize the standard RX ring control block */ 1490 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1491 rcb->bge_hostaddr.bge_addr_lo = 1492 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1493 rcb->bge_hostaddr.bge_addr_hi = 1494 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1495 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1496 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1497 if (BGE_IS_5705_PLUS(sc)) 1498 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1499 else 1500 rcb->bge_maxlen_flags = 1501 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1502 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1503 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1504 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1505 1506 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1507 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1508 1509 /* 1510 * Initialize the jumbo RX ring control block 1511 * We set the 'ring disabled' bit in the flags 1512 * field until we're actually ready to start 1513 * using this ring (i.e. once we set the MTU 1514 * high enough to require it). 1515 */ 1516 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1517 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1518 1519 rcb->bge_hostaddr.bge_addr_lo = 1520 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1521 rcb->bge_hostaddr.bge_addr_hi = 1522 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1523 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1524 sc->bge_cdata.bge_rx_jumbo_ring_map, 1525 BUS_DMASYNC_PREREAD); 1526 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1527 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1528 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1529 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1530 rcb->bge_hostaddr.bge_addr_hi); 1531 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1532 rcb->bge_hostaddr.bge_addr_lo); 1533 1534 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1535 rcb->bge_maxlen_flags); 1536 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1537 1538 /* Set up dummy disabled mini ring RCB */ 1539 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1540 rcb->bge_maxlen_flags = 1541 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1542 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1543 rcb->bge_maxlen_flags); 1544 } 1545 1546 /* 1547 * Set the BD ring replentish thresholds. The recommended 1548 * values are 1/8th the number of descriptors allocated to 1549 * each ring. 1550 * XXX The 5754 requires a lower threshold, so it might be a 1551 * requirement of all 575x family chips. The Linux driver sets 1552 * the lower threshold for all 5705 family chips as well, but there 1553 * are reports that it might not need to be so strict. 1554 * 1555 * XXX Linux does some extra fiddling here for the 5906 parts as 1556 * well. 1557 */ 1558 if (BGE_IS_5705_PLUS(sc)) 1559 val = 8; 1560 else 1561 val = BGE_STD_RX_RING_CNT / 8; 1562 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1563 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1564 1565 /* 1566 * Disable all unused send rings by setting the 'ring disabled' 1567 * bit in the flags field of all the TX send ring control blocks. 1568 * These are located in NIC memory. 1569 */ 1570 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1571 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1572 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1573 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1574 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1575 vrcb += sizeof(struct bge_rcb); 1576 } 1577 1578 /* Configure TX RCB 0 (we use only the first ring) */ 1579 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1580 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1581 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1582 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1583 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1584 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1585 if (!(BGE_IS_5705_PLUS(sc))) 1586 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1587 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1588 1589 /* Disable all unused RX return rings */ 1590 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1591 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1592 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1593 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1594 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1595 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1596 BGE_RCB_FLAG_RING_DISABLED)); 1597 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1598 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1599 (i * (sizeof(uint64_t))), 0); 1600 vrcb += sizeof(struct bge_rcb); 1601 } 1602 1603 /* Initialize RX ring indexes */ 1604 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1605 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1606 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1607 1608 /* 1609 * Set up RX return ring 0 1610 * Note that the NIC address for RX return rings is 0x00000000. 1611 * The return rings live entirely within the host, so the 1612 * nicaddr field in the RCB isn't used. 1613 */ 1614 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1615 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1616 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1617 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1618 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1619 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1620 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1621 1622 /* Set random backoff seed for TX */ 1623 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1624 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1625 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1626 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1627 BGE_TX_BACKOFF_SEED_MASK); 1628 1629 /* Set inter-packet gap */ 1630 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1631 1632 /* 1633 * Specify which ring to use for packets that don't match 1634 * any RX rules. 1635 */ 1636 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1637 1638 /* 1639 * Configure number of RX lists. One interrupt distribution 1640 * list, sixteen active lists, one bad frames class. 1641 */ 1642 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1643 1644 /* Inialize RX list placement stats mask. */ 1645 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1646 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1647 1648 /* Disable host coalescing until we get it set up */ 1649 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1650 1651 /* Poll to make sure it's shut down. */ 1652 for (i = 0; i < BGE_TIMEOUT; i++) { 1653 DELAY(10); 1654 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1655 break; 1656 } 1657 1658 if (i == BGE_TIMEOUT) { 1659 device_printf(sc->bge_dev, 1660 "host coalescing engine failed to idle\n"); 1661 return (ENXIO); 1662 } 1663 1664 /* Set up host coalescing defaults */ 1665 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1666 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1667 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1668 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1669 if (!(BGE_IS_5705_PLUS(sc))) { 1670 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1671 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1672 } 1673 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1674 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1675 1676 /* Set up address of statistics block */ 1677 if (!(BGE_IS_5705_PLUS(sc))) { 1678 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1679 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1680 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1681 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1682 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1683 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1684 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1685 } 1686 1687 /* Set up address of status block */ 1688 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1689 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1690 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1691 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1692 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1693 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1694 1695 /* Turn on host coalescing state machine */ 1696 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1697 1698 /* Turn on RX BD completion state machine and enable attentions */ 1699 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1700 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1701 1702 /* Turn on RX list placement state machine */ 1703 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1704 1705 /* Turn on RX list selector state machine. */ 1706 if (!(BGE_IS_5705_PLUS(sc))) 1707 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1708 1709 /* Turn on DMA, clear stats */ 1710 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1711 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1712 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1713 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1714 ((sc->bge_flags & BGE_FLAG_TBI) ? 1715 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1716 1717 /* Set misc. local control, enable interrupts on attentions */ 1718 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1719 1720 #ifdef notdef 1721 /* Assert GPIO pins for PHY reset */ 1722 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1723 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1724 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1725 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1726 #endif 1727 1728 /* Turn on DMA completion state machine */ 1729 if (!(BGE_IS_5705_PLUS(sc))) 1730 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1731 1732 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1733 1734 /* Enable host coalescing bug fix. */ 1735 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1736 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1737 val |= 1 << 29; 1738 1739 /* Turn on write DMA state machine */ 1740 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1741 1742 /* Turn on read DMA state machine */ 1743 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1744 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1745 1746 /* Turn on RX data completion state machine */ 1747 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1748 1749 /* Turn on RX BD initiator state machine */ 1750 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1751 1752 /* Turn on RX data and RX BD initiator state machine */ 1753 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1754 1755 /* Turn on Mbuf cluster free state machine */ 1756 if (!(BGE_IS_5705_PLUS(sc))) 1757 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1758 1759 /* Turn on send BD completion state machine */ 1760 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1761 1762 /* Turn on send data completion state machine */ 1763 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1764 1765 /* Turn on send data initiator state machine */ 1766 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1767 1768 /* Turn on send BD initiator state machine */ 1769 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1770 1771 /* Turn on send BD selector state machine */ 1772 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1773 1774 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1775 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1776 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1777 1778 /* ack/clear link change events */ 1779 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1780 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1781 BGE_MACSTAT_LINK_CHANGED); 1782 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1783 1784 /* Enable PHY auto polling (for MII/GMII only) */ 1785 if (sc->bge_flags & BGE_FLAG_TBI) { 1786 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1787 } else { 1788 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1789 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1790 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1791 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1792 BGE_EVTENB_MI_INTERRUPT); 1793 } 1794 1795 /* 1796 * Clear any pending link state attention. 1797 * Otherwise some link state change events may be lost until attention 1798 * is cleared by bge_intr() -> bge_link_upd() sequence. 1799 * It's not necessary on newer BCM chips - perhaps enabling link 1800 * state change attentions implies clearing pending attention. 1801 */ 1802 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1803 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1804 BGE_MACSTAT_LINK_CHANGED); 1805 1806 /* Enable link state change attentions. */ 1807 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1808 1809 return (0); 1810 } 1811 1812 const struct bge_revision * 1813 bge_lookup_rev(uint32_t chipid) 1814 { 1815 const struct bge_revision *br; 1816 1817 for (br = bge_revisions; br->br_name != NULL; br++) { 1818 if (br->br_chipid == chipid) 1819 return (br); 1820 } 1821 1822 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1823 if (br->br_chipid == BGE_ASICREV(chipid)) 1824 return (br); 1825 } 1826 1827 return (NULL); 1828 } 1829 1830 const struct bge_vendor * 1831 bge_lookup_vendor(uint16_t vid) 1832 { 1833 const struct bge_vendor *v; 1834 1835 for (v = bge_vendors; v->v_name != NULL; v++) 1836 if (v->v_id == vid) 1837 return (v); 1838 1839 panic("%s: unknown vendor %d", __func__, vid); 1840 return (NULL); 1841 } 1842 1843 /* 1844 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1845 * against our list and return its name if we find a match. 1846 * 1847 * Note that since the Broadcom controller contains VPD support, we 1848 * try to get the device name string from the controller itself instead 1849 * of the compiled-in string. It guarantees we'll always announce the 1850 * right product name. We fall back to the compiled-in string when 1851 * VPD is unavailable or corrupt. 1852 */ 1853 static int 1854 bge_probe(device_t dev) 1855 { 1856 struct bge_type *t = bge_devs; 1857 struct bge_softc *sc = device_get_softc(dev); 1858 uint16_t vid, did; 1859 1860 sc->bge_dev = dev; 1861 vid = pci_get_vendor(dev); 1862 did = pci_get_device(dev); 1863 while(t->bge_vid != 0) { 1864 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1865 char model[64], buf[96]; 1866 const struct bge_revision *br; 1867 const struct bge_vendor *v; 1868 uint32_t id; 1869 1870 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1871 BGE_PCIMISCCTL_ASICREV; 1872 br = bge_lookup_rev(id); 1873 v = bge_lookup_vendor(vid); 1874 { 1875 #if __FreeBSD_version > 700024 1876 const char *pname; 1877 1878 if (pci_get_vpd_ident(dev, &pname) == 0) 1879 snprintf(model, 64, "%s", pname); 1880 else 1881 #endif 1882 snprintf(model, 64, "%s %s", 1883 v->v_name, 1884 br != NULL ? br->br_name : 1885 "NetXtreme Ethernet Controller"); 1886 } 1887 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1888 br != NULL ? "" : "unknown ", id >> 16); 1889 device_set_desc_copy(dev, buf); 1890 if (pci_get_subvendor(dev) == DELL_VENDORID) 1891 sc->bge_flags |= BGE_FLAG_NO_3LED; 1892 if (did == BCOM_DEVICEID_BCM5755M) 1893 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1894 return (0); 1895 } 1896 t++; 1897 } 1898 1899 return (ENXIO); 1900 } 1901 1902 static void 1903 bge_dma_free(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 /* Destroy DMA maps for RX buffers. */ 1908 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1909 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1910 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1911 sc->bge_cdata.bge_rx_std_dmamap[i]); 1912 } 1913 1914 /* Destroy DMA maps for jumbo RX buffers. */ 1915 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1916 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1917 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1918 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1919 } 1920 1921 /* Destroy DMA maps for TX buffers. */ 1922 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1923 if (sc->bge_cdata.bge_tx_dmamap[i]) 1924 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1925 sc->bge_cdata.bge_tx_dmamap[i]); 1926 } 1927 1928 if (sc->bge_cdata.bge_mtag) 1929 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1930 1931 1932 /* Destroy standard RX ring. */ 1933 if (sc->bge_cdata.bge_rx_std_ring_map) 1934 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1935 sc->bge_cdata.bge_rx_std_ring_map); 1936 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1937 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1938 sc->bge_ldata.bge_rx_std_ring, 1939 sc->bge_cdata.bge_rx_std_ring_map); 1940 1941 if (sc->bge_cdata.bge_rx_std_ring_tag) 1942 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1943 1944 /* Destroy jumbo RX ring. */ 1945 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1946 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1947 sc->bge_cdata.bge_rx_jumbo_ring_map); 1948 1949 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1950 sc->bge_ldata.bge_rx_jumbo_ring) 1951 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1952 sc->bge_ldata.bge_rx_jumbo_ring, 1953 sc->bge_cdata.bge_rx_jumbo_ring_map); 1954 1955 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1956 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1957 1958 /* Destroy RX return ring. */ 1959 if (sc->bge_cdata.bge_rx_return_ring_map) 1960 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1961 sc->bge_cdata.bge_rx_return_ring_map); 1962 1963 if (sc->bge_cdata.bge_rx_return_ring_map && 1964 sc->bge_ldata.bge_rx_return_ring) 1965 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1966 sc->bge_ldata.bge_rx_return_ring, 1967 sc->bge_cdata.bge_rx_return_ring_map); 1968 1969 if (sc->bge_cdata.bge_rx_return_ring_tag) 1970 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1971 1972 /* Destroy TX ring. */ 1973 if (sc->bge_cdata.bge_tx_ring_map) 1974 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1975 sc->bge_cdata.bge_tx_ring_map); 1976 1977 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1978 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1979 sc->bge_ldata.bge_tx_ring, 1980 sc->bge_cdata.bge_tx_ring_map); 1981 1982 if (sc->bge_cdata.bge_tx_ring_tag) 1983 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1984 1985 /* Destroy status block. */ 1986 if (sc->bge_cdata.bge_status_map) 1987 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1988 sc->bge_cdata.bge_status_map); 1989 1990 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1991 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1992 sc->bge_ldata.bge_status_block, 1993 sc->bge_cdata.bge_status_map); 1994 1995 if (sc->bge_cdata.bge_status_tag) 1996 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1997 1998 /* Destroy statistics block. */ 1999 if (sc->bge_cdata.bge_stats_map) 2000 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2001 sc->bge_cdata.bge_stats_map); 2002 2003 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2004 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2005 sc->bge_ldata.bge_stats, 2006 sc->bge_cdata.bge_stats_map); 2007 2008 if (sc->bge_cdata.bge_stats_tag) 2009 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2010 2011 /* Destroy the parent tag. */ 2012 if (sc->bge_cdata.bge_parent_tag) 2013 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2014 } 2015 2016 static int 2017 bge_dma_alloc(device_t dev) 2018 { 2019 struct bge_dmamap_arg ctx; 2020 struct bge_softc *sc; 2021 int i, error; 2022 2023 sc = device_get_softc(dev); 2024 2025 /* 2026 * Allocate the parent bus DMA tag appropriate for PCI. 2027 */ 2028 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2029 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2030 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2031 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2032 2033 if (error != 0) { 2034 device_printf(sc->bge_dev, 2035 "could not allocate parent dma tag\n"); 2036 return (ENOMEM); 2037 } 2038 2039 /* 2040 * Create tag for mbufs. 2041 */ 2042 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2043 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2044 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 2045 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 2046 2047 if (error) { 2048 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2049 return (ENOMEM); 2050 } 2051 2052 /* Create DMA maps for RX buffers. */ 2053 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2054 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2055 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2056 if (error) { 2057 device_printf(sc->bge_dev, 2058 "can't create DMA map for RX\n"); 2059 return (ENOMEM); 2060 } 2061 } 2062 2063 /* Create DMA maps for TX buffers. */ 2064 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2065 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2066 &sc->bge_cdata.bge_tx_dmamap[i]); 2067 if (error) { 2068 device_printf(sc->bge_dev, 2069 "can't create DMA map for RX\n"); 2070 return (ENOMEM); 2071 } 2072 } 2073 2074 /* Create tag for standard RX ring. */ 2075 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2076 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2077 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2078 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2079 2080 if (error) { 2081 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2082 return (ENOMEM); 2083 } 2084 2085 /* Allocate DMA'able memory for standard RX ring. */ 2086 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2087 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2088 &sc->bge_cdata.bge_rx_std_ring_map); 2089 if (error) 2090 return (ENOMEM); 2091 2092 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2093 2094 /* Load the address of the standard RX ring. */ 2095 ctx.bge_maxsegs = 1; 2096 ctx.sc = sc; 2097 2098 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2099 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2100 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2101 2102 if (error) 2103 return (ENOMEM); 2104 2105 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2106 2107 /* Create tags for jumbo mbufs. */ 2108 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2109 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2110 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2111 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2112 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2113 if (error) { 2114 device_printf(sc->bge_dev, 2115 "could not allocate jumbo dma tag\n"); 2116 return (ENOMEM); 2117 } 2118 2119 /* Create tag for jumbo RX ring. */ 2120 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2121 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2122 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2123 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2124 2125 if (error) { 2126 device_printf(sc->bge_dev, 2127 "could not allocate jumbo ring dma tag\n"); 2128 return (ENOMEM); 2129 } 2130 2131 /* Allocate DMA'able memory for jumbo RX ring. */ 2132 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2133 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2134 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2135 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2136 if (error) 2137 return (ENOMEM); 2138 2139 /* Load the address of the jumbo RX ring. */ 2140 ctx.bge_maxsegs = 1; 2141 ctx.sc = sc; 2142 2143 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2144 sc->bge_cdata.bge_rx_jumbo_ring_map, 2145 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2146 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2147 2148 if (error) 2149 return (ENOMEM); 2150 2151 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2152 2153 /* Create DMA maps for jumbo RX buffers. */ 2154 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2155 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2156 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2157 if (error) { 2158 device_printf(sc->bge_dev, 2159 "can't create DMA map for jumbo RX\n"); 2160 return (ENOMEM); 2161 } 2162 } 2163 2164 } 2165 2166 /* Create tag for RX return ring. */ 2167 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2168 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2169 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2170 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2171 2172 if (error) { 2173 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2174 return (ENOMEM); 2175 } 2176 2177 /* Allocate DMA'able memory for RX return ring. */ 2178 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2179 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2180 &sc->bge_cdata.bge_rx_return_ring_map); 2181 if (error) 2182 return (ENOMEM); 2183 2184 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2185 BGE_RX_RTN_RING_SZ(sc)); 2186 2187 /* Load the address of the RX return ring. */ 2188 ctx.bge_maxsegs = 1; 2189 ctx.sc = sc; 2190 2191 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2192 sc->bge_cdata.bge_rx_return_ring_map, 2193 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2194 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2195 2196 if (error) 2197 return (ENOMEM); 2198 2199 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2200 2201 /* Create tag for TX ring. */ 2202 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2203 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2204 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2205 &sc->bge_cdata.bge_tx_ring_tag); 2206 2207 if (error) { 2208 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2209 return (ENOMEM); 2210 } 2211 2212 /* Allocate DMA'able memory for TX ring. */ 2213 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2214 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2215 &sc->bge_cdata.bge_tx_ring_map); 2216 if (error) 2217 return (ENOMEM); 2218 2219 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2220 2221 /* Load the address of the TX ring. */ 2222 ctx.bge_maxsegs = 1; 2223 ctx.sc = sc; 2224 2225 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2226 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2227 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2228 2229 if (error) 2230 return (ENOMEM); 2231 2232 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2233 2234 /* Create tag for status block. */ 2235 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2236 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2237 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2238 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2239 2240 if (error) { 2241 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2242 return (ENOMEM); 2243 } 2244 2245 /* Allocate DMA'able memory for status block. */ 2246 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2247 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2248 &sc->bge_cdata.bge_status_map); 2249 if (error) 2250 return (ENOMEM); 2251 2252 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2253 2254 /* Load the address of the status block. */ 2255 ctx.sc = sc; 2256 ctx.bge_maxsegs = 1; 2257 2258 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2259 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2260 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2261 2262 if (error) 2263 return (ENOMEM); 2264 2265 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2266 2267 /* Create tag for statistics block. */ 2268 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2269 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2270 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2271 &sc->bge_cdata.bge_stats_tag); 2272 2273 if (error) { 2274 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2275 return (ENOMEM); 2276 } 2277 2278 /* Allocate DMA'able memory for statistics block. */ 2279 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2280 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2281 &sc->bge_cdata.bge_stats_map); 2282 if (error) 2283 return (ENOMEM); 2284 2285 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2286 2287 /* Load the address of the statstics block. */ 2288 ctx.sc = sc; 2289 ctx.bge_maxsegs = 1; 2290 2291 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2292 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2293 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2294 2295 if (error) 2296 return (ENOMEM); 2297 2298 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2299 2300 return (0); 2301 } 2302 2303 #if __FreeBSD_version > 602105 2304 /* 2305 * Return true if this device has more than one port. 2306 */ 2307 static int 2308 bge_has_multiple_ports(struct bge_softc *sc) 2309 { 2310 device_t dev = sc->bge_dev; 2311 u_int b, d, f, fscan, s; 2312 2313 d = pci_get_domain(dev); 2314 b = pci_get_bus(dev); 2315 s = pci_get_slot(dev); 2316 f = pci_get_function(dev); 2317 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2318 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2319 return (1); 2320 return (0); 2321 } 2322 2323 /* 2324 * Return true if MSI can be used with this device. 2325 */ 2326 static int 2327 bge_can_use_msi(struct bge_softc *sc) 2328 { 2329 int can_use_msi = 0; 2330 2331 switch (sc->bge_asicrev) { 2332 case BGE_ASICREV_BCM5714: 2333 /* 2334 * Apparently, MSI doesn't work when this chip is configured 2335 * in single-port mode. 2336 */ 2337 if (bge_has_multiple_ports(sc)) 2338 can_use_msi = 1; 2339 break; 2340 case BGE_ASICREV_BCM5750: 2341 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2342 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2343 can_use_msi = 1; 2344 break; 2345 case BGE_ASICREV_BCM5752: 2346 case BGE_ASICREV_BCM5780: 2347 can_use_msi = 1; 2348 break; 2349 } 2350 return (can_use_msi); 2351 } 2352 #endif 2353 2354 static int 2355 bge_attach(device_t dev) 2356 { 2357 struct ifnet *ifp; 2358 struct bge_softc *sc; 2359 uint32_t hwcfg = 0; 2360 u_char eaddr[ETHER_ADDR_LEN]; 2361 int error, reg, rid, trys; 2362 2363 sc = device_get_softc(dev); 2364 sc->bge_dev = dev; 2365 2366 /* 2367 * Map control/status registers. 2368 */ 2369 pci_enable_busmaster(dev); 2370 2371 rid = BGE_PCI_BAR0; 2372 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2373 RF_ACTIVE); 2374 2375 if (sc->bge_res == NULL) { 2376 device_printf (sc->bge_dev, "couldn't map memory\n"); 2377 error = ENXIO; 2378 goto fail; 2379 } 2380 2381 sc->bge_btag = rman_get_bustag(sc->bge_res); 2382 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2383 2384 /* Save ASIC rev. */ 2385 2386 sc->bge_chipid = 2387 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2388 BGE_PCIMISCCTL_ASICREV; 2389 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2390 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2391 2392 /* 2393 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2394 * 5705 A0 and A1 chips. 2395 */ 2396 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2397 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2398 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2399 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2400 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2401 2402 if (bge_has_eeprom(sc)) 2403 sc->bge_flags |= BGE_FLAG_EEPROM; 2404 2405 /* Save chipset family. */ 2406 switch (sc->bge_asicrev) { 2407 case BGE_ASICREV_BCM5700: 2408 case BGE_ASICREV_BCM5701: 2409 case BGE_ASICREV_BCM5703: 2410 case BGE_ASICREV_BCM5704: 2411 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2412 break; 2413 case BGE_ASICREV_BCM5714_A0: 2414 case BGE_ASICREV_BCM5780: 2415 case BGE_ASICREV_BCM5714: 2416 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2417 /* FALLTHRU */ 2418 case BGE_ASICREV_BCM5750: 2419 case BGE_ASICREV_BCM5752: 2420 case BGE_ASICREV_BCM5755: 2421 case BGE_ASICREV_BCM5787: 2422 case BGE_ASICREV_BCM5906: 2423 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2424 /* FALLTHRU */ 2425 case BGE_ASICREV_BCM5705: 2426 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2427 break; 2428 } 2429 2430 /* Set various bug flags. */ 2431 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2432 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2433 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2434 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2435 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2436 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2437 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2438 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2439 if (BGE_IS_5705_PLUS(sc) && 2440 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2441 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2442 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2443 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2444 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2445 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2446 sc->bge_flags |= BGE_FLAG_BER_BUG; 2447 } 2448 2449 /* 2450 * Check if this is a PCI-X or PCI Express device. 2451 */ 2452 #if __FreeBSD_version > 602101 2453 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2454 /* 2455 * Found a PCI Express capabilities register, this 2456 * must be a PCI Express device. 2457 */ 2458 if (reg != 0) 2459 sc->bge_flags |= BGE_FLAG_PCIE; 2460 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 2461 if (reg != 0) 2462 sc->bge_flags |= BGE_FLAG_PCIX; 2463 } 2464 2465 #else 2466 if (BGE_IS_5705_PLUS(sc)) { 2467 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2468 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2469 sc->bge_flags |= BGE_FLAG_PCIE; 2470 } else { 2471 /* 2472 * Check if the device is in PCI-X Mode. 2473 * (This bit is not valid on PCI Express controllers.) 2474 */ 2475 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2476 BGE_PCISTATE_PCI_BUSMODE) == 0) 2477 sc->bge_flags |= BGE_FLAG_PCIX; 2478 } 2479 #endif 2480 2481 #if __FreeBSD_version > 602105 2482 { 2483 int msicount; 2484 2485 /* 2486 * Allocate the interrupt, using MSI if possible. These devices 2487 * support 8 MSI messages, but only the first one is used in 2488 * normal operation. 2489 */ 2490 if (bge_can_use_msi(sc)) { 2491 msicount = pci_msi_count(dev); 2492 if (msicount > 1) 2493 msicount = 1; 2494 } else 2495 msicount = 0; 2496 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2497 rid = 1; 2498 sc->bge_flags |= BGE_FLAG_MSI; 2499 } else 2500 rid = 0; 2501 } 2502 #else 2503 rid = 0; 2504 #endif 2505 2506 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2507 RF_SHAREABLE | RF_ACTIVE); 2508 2509 if (sc->bge_irq == NULL) { 2510 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2511 error = ENXIO; 2512 goto fail; 2513 } 2514 2515 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2516 2517 /* Try to reset the chip. */ 2518 if (bge_reset(sc)) { 2519 device_printf(sc->bge_dev, "chip reset failed\n"); 2520 error = ENXIO; 2521 goto fail; 2522 } 2523 2524 sc->bge_asf_mode = 0; 2525 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2526 == BGE_MAGIC_NUMBER)) { 2527 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2528 & BGE_HWCFG_ASF) { 2529 sc->bge_asf_mode |= ASF_ENABLE; 2530 sc->bge_asf_mode |= ASF_STACKUP; 2531 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2532 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2533 } 2534 } 2535 } 2536 2537 /* Try to reset the chip again the nice way. */ 2538 bge_stop_fw(sc); 2539 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2540 if (bge_reset(sc)) { 2541 device_printf(sc->bge_dev, "chip reset failed\n"); 2542 error = ENXIO; 2543 goto fail; 2544 } 2545 2546 bge_sig_legacy(sc, BGE_RESET_STOP); 2547 bge_sig_post_reset(sc, BGE_RESET_STOP); 2548 2549 if (bge_chipinit(sc)) { 2550 device_printf(sc->bge_dev, "chip initialization failed\n"); 2551 error = ENXIO; 2552 goto fail; 2553 } 2554 2555 #ifdef __sparc64__ 2556 if (((sc->bge_flags & BGE_FLAG_EEPROM) == 0) && 2557 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) 2558 OF_getetheraddr(dev, eaddr); 2559 else 2560 #endif 2561 { 2562 error = bge_get_eaddr(sc, eaddr); 2563 if (error) { 2564 device_printf(sc->bge_dev, 2565 "failed to read station address\n"); 2566 error = ENXIO; 2567 goto fail; 2568 } 2569 } 2570 2571 /* 5705 limits RX return ring to 512 entries. */ 2572 if (BGE_IS_5705_PLUS(sc)) 2573 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2574 else 2575 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2576 2577 if (bge_dma_alloc(dev)) { 2578 device_printf(sc->bge_dev, 2579 "failed to allocate DMA resources\n"); 2580 error = ENXIO; 2581 goto fail; 2582 } 2583 2584 /* Set default tuneable values. */ 2585 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2586 sc->bge_rx_coal_ticks = 150; 2587 sc->bge_tx_coal_ticks = 150; 2588 sc->bge_rx_max_coal_bds = 10; 2589 sc->bge_tx_max_coal_bds = 10; 2590 2591 /* Set up ifnet structure */ 2592 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2593 if (ifp == NULL) { 2594 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2595 error = ENXIO; 2596 goto fail; 2597 } 2598 ifp->if_softc = sc; 2599 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2601 ifp->if_ioctl = bge_ioctl; 2602 ifp->if_start = bge_start; 2603 ifp->if_init = bge_init; 2604 ifp->if_mtu = ETHERMTU; 2605 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2606 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2607 IFQ_SET_READY(&ifp->if_snd); 2608 ifp->if_hwassist = BGE_CSUM_FEATURES; 2609 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2610 IFCAP_VLAN_MTU; 2611 #ifdef IFCAP_VLAN_HWCSUM 2612 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2613 #endif 2614 ifp->if_capenable = ifp->if_capabilities; 2615 #ifdef DEVICE_POLLING 2616 ifp->if_capabilities |= IFCAP_POLLING; 2617 #endif 2618 2619 /* 2620 * 5700 B0 chips do not support checksumming correctly due 2621 * to hardware bugs. 2622 */ 2623 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2624 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2625 ifp->if_capenable &= IFCAP_HWCSUM; 2626 ifp->if_hwassist = 0; 2627 } 2628 2629 /* 2630 * Figure out what sort of media we have by checking the 2631 * hardware config word in the first 32k of NIC internal memory, 2632 * or fall back to examining the EEPROM if necessary. 2633 * Note: on some BCM5700 cards, this value appears to be unset. 2634 * If that's the case, we have to rely on identifying the NIC 2635 * by its PCI subsystem ID, as we do below for the SysKonnect 2636 * SK-9D41. 2637 */ 2638 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2639 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2640 else if (sc->bge_flags & BGE_FLAG_EEPROM) { 2641 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2642 sizeof(hwcfg))) { 2643 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2644 error = ENXIO; 2645 goto fail; 2646 } 2647 hwcfg = ntohl(hwcfg); 2648 } 2649 2650 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2651 sc->bge_flags |= BGE_FLAG_TBI; 2652 2653 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2654 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2655 sc->bge_flags |= BGE_FLAG_TBI; 2656 2657 if (sc->bge_flags & BGE_FLAG_TBI) { 2658 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2659 bge_ifmedia_sts); 2660 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2661 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2662 0, NULL); 2663 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2664 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2665 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2666 } else { 2667 /* 2668 * Do transceiver setup and tell the firmware the 2669 * driver is down so we can try to get access the 2670 * probe if ASF is running. Retry a couple of times 2671 * if we get a conflict with the ASF firmware accessing 2672 * the PHY. 2673 */ 2674 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2675 again: 2676 bge_asf_driver_up(sc); 2677 2678 trys = 0; 2679 if (mii_phy_probe(dev, &sc->bge_miibus, 2680 bge_ifmedia_upd, bge_ifmedia_sts)) { 2681 if (trys++ < 4) { 2682 device_printf(sc->bge_dev, "Try again\n"); 2683 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2684 BMCR_RESET); 2685 goto again; 2686 } 2687 2688 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2689 error = ENXIO; 2690 goto fail; 2691 } 2692 2693 /* 2694 * Now tell the firmware we are going up after probing the PHY 2695 */ 2696 if (sc->bge_asf_mode & ASF_STACKUP) 2697 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2698 } 2699 2700 /* 2701 * When using the BCM5701 in PCI-X mode, data corruption has 2702 * been observed in the first few bytes of some received packets. 2703 * Aligning the packet buffer in memory eliminates the corruption. 2704 * Unfortunately, this misaligns the packet payloads. On platforms 2705 * which do not support unaligned accesses, we will realign the 2706 * payloads by copying the received packets. 2707 */ 2708 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2709 sc->bge_flags & BGE_FLAG_PCIX) 2710 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2711 2712 /* 2713 * Call MI attach routine. 2714 */ 2715 ether_ifattach(ifp, eaddr); 2716 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2717 2718 /* 2719 * Hookup IRQ last. 2720 */ 2721 #if __FreeBSD_version > 700030 2722 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2723 NULL, bge_intr, sc, &sc->bge_intrhand); 2724 #else 2725 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2726 bge_intr, sc, &sc->bge_intrhand); 2727 #endif 2728 2729 if (error) { 2730 bge_detach(dev); 2731 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2732 } 2733 2734 bge_add_sysctls(sc); 2735 2736 return (0); 2737 2738 fail: 2739 bge_release_resources(sc); 2740 2741 return (error); 2742 } 2743 2744 static int 2745 bge_detach(device_t dev) 2746 { 2747 struct bge_softc *sc; 2748 struct ifnet *ifp; 2749 2750 sc = device_get_softc(dev); 2751 ifp = sc->bge_ifp; 2752 2753 #ifdef DEVICE_POLLING 2754 if (ifp->if_capenable & IFCAP_POLLING) 2755 ether_poll_deregister(ifp); 2756 #endif 2757 2758 BGE_LOCK(sc); 2759 bge_stop(sc); 2760 bge_reset(sc); 2761 BGE_UNLOCK(sc); 2762 2763 callout_drain(&sc->bge_stat_ch); 2764 2765 ether_ifdetach(ifp); 2766 2767 if (sc->bge_flags & BGE_FLAG_TBI) { 2768 ifmedia_removeall(&sc->bge_ifmedia); 2769 } else { 2770 bus_generic_detach(dev); 2771 device_delete_child(dev, sc->bge_miibus); 2772 } 2773 2774 bge_release_resources(sc); 2775 2776 return (0); 2777 } 2778 2779 static void 2780 bge_release_resources(struct bge_softc *sc) 2781 { 2782 device_t dev; 2783 2784 dev = sc->bge_dev; 2785 2786 if (sc->bge_intrhand != NULL) 2787 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2788 2789 if (sc->bge_irq != NULL) 2790 bus_release_resource(dev, SYS_RES_IRQ, 2791 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2792 2793 #if __FreeBSD_version > 602105 2794 if (sc->bge_flags & BGE_FLAG_MSI) 2795 pci_release_msi(dev); 2796 #endif 2797 2798 if (sc->bge_res != NULL) 2799 bus_release_resource(dev, SYS_RES_MEMORY, 2800 BGE_PCI_BAR0, sc->bge_res); 2801 2802 if (sc->bge_ifp != NULL) 2803 if_free(sc->bge_ifp); 2804 2805 bge_dma_free(sc); 2806 2807 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2808 BGE_LOCK_DESTROY(sc); 2809 } 2810 2811 static int 2812 bge_reset(struct bge_softc *sc) 2813 { 2814 device_t dev; 2815 uint32_t cachesize, command, pcistate, reset; 2816 void (*write_op)(struct bge_softc *, int, int); 2817 int i, val = 0; 2818 2819 dev = sc->bge_dev; 2820 2821 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2822 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2823 if (sc->bge_flags & BGE_FLAG_PCIE) 2824 write_op = bge_writemem_direct; 2825 else 2826 write_op = bge_writemem_ind; 2827 } else 2828 write_op = bge_writereg_ind; 2829 2830 /* Save some important PCI state. */ 2831 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2832 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2833 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2834 2835 pci_write_config(dev, BGE_PCI_MISC_CTL, 2836 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2837 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2838 2839 /* Disable fastboot on controllers that support it. */ 2840 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2841 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2842 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2843 if (bootverbose) 2844 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2845 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2846 } 2847 2848 /* 2849 * Write the magic number to SRAM at offset 0xB50. 2850 * When firmware finishes its initialization it will 2851 * write ~BGE_MAGIC_NUMBER to the same location. 2852 */ 2853 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2854 2855 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2856 2857 /* XXX: Broadcom Linux driver. */ 2858 if (sc->bge_flags & BGE_FLAG_PCIE) { 2859 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2860 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2861 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2862 /* Prevent PCIE link training during global reset */ 2863 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2864 reset |= 1 << 29; 2865 } 2866 } 2867 2868 /* 2869 * Set GPHY Power Down Override to leave GPHY 2870 * powered up in D0 uninitialized. 2871 */ 2872 if (BGE_IS_5705_PLUS(sc)) 2873 reset |= 0x04000000; 2874 2875 /* Issue global reset */ 2876 write_op(sc, BGE_MISC_CFG, reset); 2877 2878 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2879 uint32_t status, ctrl; 2880 2881 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2882 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2883 status | BGE_VCPU_STATUS_DRV_RESET); 2884 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2885 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2886 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2887 } 2888 2889 DELAY(1000); 2890 2891 /* XXX: Broadcom Linux driver. */ 2892 if (sc->bge_flags & BGE_FLAG_PCIE) { 2893 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2894 uint32_t v; 2895 2896 DELAY(500000); /* wait for link training to complete */ 2897 v = pci_read_config(dev, 0xC4, 4); 2898 pci_write_config(dev, 0xC4, v | (1 << 15), 4); 2899 } 2900 /* 2901 * Set PCIE max payload size to 128 bytes and clear error 2902 * status. 2903 */ 2904 pci_write_config(dev, 0xD8, 0xF5000, 4); 2905 } 2906 2907 /* Reset some of the PCI state that got zapped by reset. */ 2908 pci_write_config(dev, BGE_PCI_MISC_CTL, 2909 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2910 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2911 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2912 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2913 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2914 2915 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2916 if (BGE_IS_5714_FAMILY(sc)) { 2917 uint32_t val; 2918 2919 /* This chip disables MSI on reset. */ 2920 if (sc->bge_flags & BGE_FLAG_MSI) { 2921 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2922 pci_write_config(dev, BGE_PCI_MSI_CTL, 2923 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2924 val = CSR_READ_4(sc, BGE_MSI_MODE); 2925 CSR_WRITE_4(sc, BGE_MSI_MODE, 2926 val | BGE_MSIMODE_ENABLE); 2927 } 2928 val = CSR_READ_4(sc, BGE_MARB_MODE); 2929 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2930 } else 2931 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2932 2933 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2934 for (i = 0; i < BGE_TIMEOUT; i++) { 2935 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2936 if (val & BGE_VCPU_STATUS_INIT_DONE) 2937 break; 2938 DELAY(100); 2939 } 2940 if (i == BGE_TIMEOUT) { 2941 device_printf(sc->bge_dev, "reset timed out\n"); 2942 return (1); 2943 } 2944 } else { 2945 /* 2946 * Poll until we see the 1's complement of the magic number. 2947 * This indicates that the firmware initialization is complete. 2948 * We expect this to fail if no EEPROM is fitted though. 2949 */ 2950 for (i = 0; i < BGE_TIMEOUT; i++) { 2951 DELAY(10); 2952 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2953 if (val == ~BGE_MAGIC_NUMBER) 2954 break; 2955 } 2956 2957 if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT) 2958 device_printf(sc->bge_dev, "firmware handshake timed out, " 2959 "found 0x%08x\n", val); 2960 } 2961 2962 /* 2963 * XXX Wait for the value of the PCISTATE register to 2964 * return to its original pre-reset state. This is a 2965 * fairly good indicator of reset completion. If we don't 2966 * wait for the reset to fully complete, trying to read 2967 * from the device's non-PCI registers may yield garbage 2968 * results. 2969 */ 2970 for (i = 0; i < BGE_TIMEOUT; i++) { 2971 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2972 break; 2973 DELAY(10); 2974 } 2975 2976 if (sc->bge_flags & BGE_FLAG_PCIE) { 2977 reset = bge_readmem_ind(sc, 0x7C00); 2978 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2979 } 2980 2981 /* Fix up byte swapping. */ 2982 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2983 BGE_MODECTL_BYTESWAP_DATA); 2984 2985 /* Tell the ASF firmware we are up */ 2986 if (sc->bge_asf_mode & ASF_STACKUP) 2987 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2988 2989 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2990 2991 /* 2992 * The 5704 in TBI mode apparently needs some special 2993 * adjustment to insure the SERDES drive level is set 2994 * to 1.2V. 2995 */ 2996 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2997 sc->bge_flags & BGE_FLAG_TBI) { 2998 uint32_t serdescfg; 2999 3000 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3001 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3002 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3003 } 3004 3005 /* XXX: Broadcom Linux driver. */ 3006 if (sc->bge_flags & BGE_FLAG_PCIE && 3007 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3008 uint32_t v; 3009 3010 v = CSR_READ_4(sc, 0x7C00); 3011 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 3012 } 3013 DELAY(10000); 3014 3015 return(0); 3016 } 3017 3018 /* 3019 * Frame reception handling. This is called if there's a frame 3020 * on the receive return list. 3021 * 3022 * Note: we have to be able to handle two possibilities here: 3023 * 1) the frame is from the jumbo receive ring 3024 * 2) the frame is from the standard receive ring 3025 */ 3026 3027 static void 3028 bge_rxeof(struct bge_softc *sc) 3029 { 3030 struct ifnet *ifp; 3031 int stdcnt = 0, jumbocnt = 0; 3032 3033 BGE_LOCK_ASSERT(sc); 3034 3035 /* Nothing to do. */ 3036 if (sc->bge_rx_saved_considx == 3037 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 3038 return; 3039 3040 ifp = sc->bge_ifp; 3041 3042 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3043 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3044 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3045 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 3046 if (BGE_IS_JUMBO_CAPABLE(sc)) 3047 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3048 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 3049 3050 while(sc->bge_rx_saved_considx != 3051 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 3052 struct bge_rx_bd *cur_rx; 3053 uint32_t rxidx; 3054 struct mbuf *m = NULL; 3055 uint16_t vlan_tag = 0; 3056 int have_tag = 0; 3057 3058 #ifdef DEVICE_POLLING 3059 if (ifp->if_capenable & IFCAP_POLLING) { 3060 if (sc->rxcycles <= 0) 3061 break; 3062 sc->rxcycles--; 3063 } 3064 #endif 3065 3066 cur_rx = 3067 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 3068 3069 rxidx = cur_rx->bge_idx; 3070 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3071 3072 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3073 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3074 have_tag = 1; 3075 vlan_tag = cur_rx->bge_vlan_tag; 3076 } 3077 3078 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3079 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3080 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 3081 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 3082 BUS_DMASYNC_POSTREAD); 3083 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 3084 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 3085 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3086 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3087 jumbocnt++; 3088 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3089 ifp->if_ierrors++; 3090 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3091 continue; 3092 } 3093 if (bge_newbuf_jumbo(sc, 3094 sc->bge_jumbo, NULL) == ENOBUFS) { 3095 ifp->if_ierrors++; 3096 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3097 continue; 3098 } 3099 } else { 3100 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3101 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3102 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 3103 BUS_DMASYNC_POSTREAD); 3104 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3105 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 3106 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3107 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3108 stdcnt++; 3109 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3110 ifp->if_ierrors++; 3111 bge_newbuf_std(sc, sc->bge_std, m); 3112 continue; 3113 } 3114 if (bge_newbuf_std(sc, sc->bge_std, 3115 NULL) == ENOBUFS) { 3116 ifp->if_ierrors++; 3117 bge_newbuf_std(sc, sc->bge_std, m); 3118 continue; 3119 } 3120 } 3121 3122 ifp->if_ipackets++; 3123 #ifndef __NO_STRICT_ALIGNMENT 3124 /* 3125 * For architectures with strict alignment we must make sure 3126 * the payload is aligned. 3127 */ 3128 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3129 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3130 cur_rx->bge_len); 3131 m->m_data += ETHER_ALIGN; 3132 } 3133 #endif 3134 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3135 m->m_pkthdr.rcvif = ifp; 3136 3137 if (ifp->if_capenable & IFCAP_RXCSUM) { 3138 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3139 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3140 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3141 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3142 } 3143 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3144 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3145 m->m_pkthdr.csum_data = 3146 cur_rx->bge_tcp_udp_csum; 3147 m->m_pkthdr.csum_flags |= 3148 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3149 } 3150 } 3151 3152 /* 3153 * If we received a packet with a vlan tag, 3154 * attach that information to the packet. 3155 */ 3156 if (have_tag) { 3157 #if __FreeBSD_version > 700022 3158 m->m_pkthdr.ether_vtag = vlan_tag; 3159 m->m_flags |= M_VLANTAG; 3160 #else 3161 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3162 if (m == NULL) 3163 continue; 3164 #endif 3165 } 3166 3167 BGE_UNLOCK(sc); 3168 (*ifp->if_input)(ifp, m); 3169 BGE_LOCK(sc); 3170 } 3171 3172 if (stdcnt > 0) 3173 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3174 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3175 3176 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3177 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3178 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3179 3180 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3181 if (stdcnt) 3182 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3183 if (jumbocnt) 3184 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3185 #ifdef notyet 3186 /* 3187 * This register wraps very quickly under heavy packet drops. 3188 * If you need correct statistics, you can enable this check. 3189 */ 3190 if (BGE_IS_5705_PLUS(sc)) 3191 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3192 #endif 3193 } 3194 3195 static void 3196 bge_txeof(struct bge_softc *sc) 3197 { 3198 struct bge_tx_bd *cur_tx = NULL; 3199 struct ifnet *ifp; 3200 3201 BGE_LOCK_ASSERT(sc); 3202 3203 /* Nothing to do. */ 3204 if (sc->bge_tx_saved_considx == 3205 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3206 return; 3207 3208 ifp = sc->bge_ifp; 3209 3210 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3211 sc->bge_cdata.bge_tx_ring_map, 3212 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3213 /* 3214 * Go through our tx ring and free mbufs for those 3215 * frames that have been sent. 3216 */ 3217 while (sc->bge_tx_saved_considx != 3218 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3219 uint32_t idx = 0; 3220 3221 idx = sc->bge_tx_saved_considx; 3222 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3223 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3224 ifp->if_opackets++; 3225 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3226 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3227 sc->bge_cdata.bge_tx_dmamap[idx], 3228 BUS_DMASYNC_POSTWRITE); 3229 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3230 sc->bge_cdata.bge_tx_dmamap[idx]); 3231 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3232 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3233 } 3234 sc->bge_txcnt--; 3235 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3236 } 3237 3238 if (cur_tx != NULL) 3239 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3240 if (sc->bge_txcnt == 0) 3241 sc->bge_timer = 0; 3242 } 3243 3244 #ifdef DEVICE_POLLING 3245 static void 3246 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3247 { 3248 struct bge_softc *sc = ifp->if_softc; 3249 uint32_t statusword; 3250 3251 BGE_LOCK(sc); 3252 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3253 BGE_UNLOCK(sc); 3254 return; 3255 } 3256 3257 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3258 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3259 3260 statusword = atomic_readandclear_32( 3261 &sc->bge_ldata.bge_status_block->bge_status); 3262 3263 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3264 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3265 3266 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3267 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3268 sc->bge_link_evt++; 3269 3270 if (cmd == POLL_AND_CHECK_STATUS) 3271 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3272 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3273 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3274 bge_link_upd(sc); 3275 3276 sc->rxcycles = count; 3277 bge_rxeof(sc); 3278 bge_txeof(sc); 3279 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3280 bge_start_locked(ifp); 3281 3282 BGE_UNLOCK(sc); 3283 } 3284 #endif /* DEVICE_POLLING */ 3285 3286 static void 3287 bge_intr(void *xsc) 3288 { 3289 struct bge_softc *sc; 3290 struct ifnet *ifp; 3291 uint32_t statusword; 3292 3293 sc = xsc; 3294 3295 BGE_LOCK(sc); 3296 3297 ifp = sc->bge_ifp; 3298 3299 #ifdef DEVICE_POLLING 3300 if (ifp->if_capenable & IFCAP_POLLING) { 3301 BGE_UNLOCK(sc); 3302 return; 3303 } 3304 #endif 3305 3306 /* 3307 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3308 * disable interrupts by writing nonzero like we used to, since with 3309 * our current organization this just gives complications and 3310 * pessimizations for re-enabling interrupts. We used to have races 3311 * instead of the necessary complications. Disabling interrupts 3312 * would just reduce the chance of a status update while we are 3313 * running (by switching to the interrupt-mode coalescence 3314 * parameters), but this chance is already very low so it is more 3315 * efficient to get another interrupt than prevent it. 3316 * 3317 * We do the ack first to ensure another interrupt if there is a 3318 * status update after the ack. We don't check for the status 3319 * changing later because it is more efficient to get another 3320 * interrupt than prevent it, not quite as above (not checking is 3321 * a smaller optimization than not toggling the interrupt enable, 3322 * since checking doesn't involve PCI accesses and toggling require 3323 * the status check). So toggling would probably be a pessimization 3324 * even with MSI. It would only be needed for using a task queue. 3325 */ 3326 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3327 3328 /* 3329 * Do the mandatory PCI flush as well as get the link status. 3330 */ 3331 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3332 3333 /* Make sure the descriptor ring indexes are coherent. */ 3334 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3335 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3336 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3337 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3338 3339 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3340 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3341 statusword || sc->bge_link_evt) 3342 bge_link_upd(sc); 3343 3344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3345 /* Check RX return ring producer/consumer. */ 3346 bge_rxeof(sc); 3347 3348 /* Check TX ring producer/consumer. */ 3349 bge_txeof(sc); 3350 } 3351 3352 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3353 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3354 bge_start_locked(ifp); 3355 3356 BGE_UNLOCK(sc); 3357 } 3358 3359 static void 3360 bge_asf_driver_up(struct bge_softc *sc) 3361 { 3362 if (sc->bge_asf_mode & ASF_STACKUP) { 3363 /* Send ASF heartbeat aprox. every 2s */ 3364 if (sc->bge_asf_count) 3365 sc->bge_asf_count --; 3366 else { 3367 sc->bge_asf_count = 5; 3368 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3369 BGE_FW_DRV_ALIVE); 3370 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3371 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3372 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3373 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3374 } 3375 } 3376 } 3377 3378 static void 3379 bge_tick(void *xsc) 3380 { 3381 struct bge_softc *sc = xsc; 3382 struct mii_data *mii = NULL; 3383 3384 BGE_LOCK_ASSERT(sc); 3385 3386 /* Synchronize with possible callout reset/stop. */ 3387 if (callout_pending(&sc->bge_stat_ch) || 3388 !callout_active(&sc->bge_stat_ch)) 3389 return; 3390 3391 if (BGE_IS_5705_PLUS(sc)) 3392 bge_stats_update_regs(sc); 3393 else 3394 bge_stats_update(sc); 3395 3396 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3397 mii = device_get_softc(sc->bge_miibus); 3398 /* Don't mess with the PHY in IPMI/ASF mode */ 3399 if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link))) 3400 mii_tick(mii); 3401 } else { 3402 /* 3403 * Since in TBI mode auto-polling can't be used we should poll 3404 * link status manually. Here we register pending link event 3405 * and trigger interrupt. 3406 */ 3407 #ifdef DEVICE_POLLING 3408 /* In polling mode we poll link state in bge_poll(). */ 3409 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3410 #endif 3411 { 3412 sc->bge_link_evt++; 3413 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3414 } 3415 } 3416 3417 bge_asf_driver_up(sc); 3418 bge_watchdog(sc); 3419 3420 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3421 } 3422 3423 static void 3424 bge_stats_update_regs(struct bge_softc *sc) 3425 { 3426 struct ifnet *ifp; 3427 3428 ifp = sc->bge_ifp; 3429 3430 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3431 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3432 3433 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3434 } 3435 3436 static void 3437 bge_stats_update(struct bge_softc *sc) 3438 { 3439 struct ifnet *ifp; 3440 bus_size_t stats; 3441 uint32_t cnt; /* current register value */ 3442 3443 ifp = sc->bge_ifp; 3444 3445 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3446 3447 #define READ_STAT(sc, stats, stat) \ 3448 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3449 3450 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3451 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3452 sc->bge_tx_collisions = cnt; 3453 3454 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3455 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3456 sc->bge_rx_discards = cnt; 3457 3458 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3459 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3460 sc->bge_tx_discards = cnt; 3461 3462 #undef READ_STAT 3463 } 3464 3465 /* 3466 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3467 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3468 * but when such padded frames employ the bge IP/TCP checksum offload, 3469 * the hardware checksum assist gives incorrect results (possibly 3470 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3471 * If we pad such runts with zeros, the onboard checksum comes out correct. 3472 */ 3473 static __inline int 3474 bge_cksum_pad(struct mbuf *m) 3475 { 3476 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3477 struct mbuf *last; 3478 3479 /* If there's only the packet-header and we can pad there, use it. */ 3480 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3481 M_TRAILINGSPACE(m) >= padlen) { 3482 last = m; 3483 } else { 3484 /* 3485 * Walk packet chain to find last mbuf. We will either 3486 * pad there, or append a new mbuf and pad it. 3487 */ 3488 for (last = m; last->m_next != NULL; last = last->m_next); 3489 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3490 /* Allocate new empty mbuf, pad it. Compact later. */ 3491 struct mbuf *n; 3492 3493 MGET(n, M_DONTWAIT, MT_DATA); 3494 if (n == NULL) 3495 return (ENOBUFS); 3496 n->m_len = 0; 3497 last->m_next = n; 3498 last = n; 3499 } 3500 } 3501 3502 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3503 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3504 last->m_len += padlen; 3505 m->m_pkthdr.len += padlen; 3506 3507 return (0); 3508 } 3509 3510 /* 3511 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3512 * pointers to descriptors. 3513 */ 3514 static int 3515 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3516 { 3517 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3518 bus_dmamap_t map; 3519 struct bge_tx_bd *d; 3520 struct mbuf *m = *m_head; 3521 uint32_t idx = *txidx; 3522 uint16_t csum_flags; 3523 int nsegs, i, error; 3524 3525 csum_flags = 0; 3526 if (m->m_pkthdr.csum_flags) { 3527 if (m->m_pkthdr.csum_flags & CSUM_IP) 3528 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3529 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3530 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3531 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3532 (error = bge_cksum_pad(m)) != 0) { 3533 m_freem(m); 3534 *m_head = NULL; 3535 return (error); 3536 } 3537 } 3538 if (m->m_flags & M_LASTFRAG) 3539 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3540 else if (m->m_flags & M_FRAG) 3541 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3542 } 3543 3544 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3545 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3546 &nsegs, BUS_DMA_NOWAIT); 3547 if (error == EFBIG) { 3548 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3549 if (m == NULL) { 3550 m_freem(*m_head); 3551 *m_head = NULL; 3552 return (ENOBUFS); 3553 } 3554 *m_head = m; 3555 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3556 segs, &nsegs, BUS_DMA_NOWAIT); 3557 if (error) { 3558 m_freem(m); 3559 *m_head = NULL; 3560 return (error); 3561 } 3562 } else if (error != 0) 3563 return (error); 3564 3565 /* 3566 * Sanity check: avoid coming within 16 descriptors 3567 * of the end of the ring. 3568 */ 3569 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3570 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3571 return (ENOBUFS); 3572 } 3573 3574 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3575 3576 for (i = 0; ; i++) { 3577 d = &sc->bge_ldata.bge_tx_ring[idx]; 3578 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3579 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3580 d->bge_len = segs[i].ds_len; 3581 d->bge_flags = csum_flags; 3582 if (i == nsegs - 1) 3583 break; 3584 BGE_INC(idx, BGE_TX_RING_CNT); 3585 } 3586 3587 /* Mark the last segment as end of packet... */ 3588 d->bge_flags |= BGE_TXBDFLAG_END; 3589 3590 /* ... and put VLAN tag into first segment. */ 3591 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3592 #if __FreeBSD_version > 700022 3593 if (m->m_flags & M_VLANTAG) { 3594 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3595 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3596 } else 3597 d->bge_vlan_tag = 0; 3598 #else 3599 { 3600 struct m_tag *mtag; 3601 3602 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3603 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3604 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3605 } else 3606 d->bge_vlan_tag = 0; 3607 } 3608 #endif 3609 3610 /* 3611 * Insure that the map for this transmission 3612 * is placed at the array index of the last descriptor 3613 * in this chain. 3614 */ 3615 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3616 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3617 sc->bge_cdata.bge_tx_chain[idx] = m; 3618 sc->bge_txcnt += nsegs; 3619 3620 BGE_INC(idx, BGE_TX_RING_CNT); 3621 *txidx = idx; 3622 3623 return (0); 3624 } 3625 3626 /* 3627 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3628 * to the mbuf data regions directly in the transmit descriptors. 3629 */ 3630 static void 3631 bge_start_locked(struct ifnet *ifp) 3632 { 3633 struct bge_softc *sc; 3634 struct mbuf *m_head = NULL; 3635 uint32_t prodidx; 3636 int count = 0; 3637 3638 sc = ifp->if_softc; 3639 3640 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3641 return; 3642 3643 prodidx = sc->bge_tx_prodidx; 3644 3645 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3646 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3647 if (m_head == NULL) 3648 break; 3649 3650 /* 3651 * XXX 3652 * The code inside the if() block is never reached since we 3653 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3654 * requests to checksum TCP/UDP in a fragmented packet. 3655 * 3656 * XXX 3657 * safety overkill. If this is a fragmented packet chain 3658 * with delayed TCP/UDP checksums, then only encapsulate 3659 * it if we have enough descriptors to handle the entire 3660 * chain at once. 3661 * (paranoia -- may not actually be needed) 3662 */ 3663 if (m_head->m_flags & M_FIRSTFRAG && 3664 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3665 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3666 m_head->m_pkthdr.csum_data + 16) { 3667 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3668 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3669 break; 3670 } 3671 } 3672 3673 /* 3674 * Pack the data into the transmit ring. If we 3675 * don't have room, set the OACTIVE flag and wait 3676 * for the NIC to drain the ring. 3677 */ 3678 if (bge_encap(sc, &m_head, &prodidx)) { 3679 if (m_head == NULL) 3680 break; 3681 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3682 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3683 break; 3684 } 3685 ++count; 3686 3687 /* 3688 * If there's a BPF listener, bounce a copy of this frame 3689 * to him. 3690 */ 3691 #ifdef ETHER_BPF_MTAP 3692 ETHER_BPF_MTAP(ifp, m_head); 3693 #else 3694 BPF_MTAP(ifp, m_head); 3695 #endif 3696 } 3697 3698 if (count == 0) 3699 /* No packets were dequeued. */ 3700 return; 3701 3702 /* Transmit. */ 3703 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3704 /* 5700 b2 errata */ 3705 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3706 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3707 3708 sc->bge_tx_prodidx = prodidx; 3709 3710 /* 3711 * Set a timeout in case the chip goes out to lunch. 3712 */ 3713 sc->bge_timer = 5; 3714 } 3715 3716 /* 3717 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3718 * to the mbuf data regions directly in the transmit descriptors. 3719 */ 3720 static void 3721 bge_start(struct ifnet *ifp) 3722 { 3723 struct bge_softc *sc; 3724 3725 sc = ifp->if_softc; 3726 BGE_LOCK(sc); 3727 bge_start_locked(ifp); 3728 BGE_UNLOCK(sc); 3729 } 3730 3731 static void 3732 bge_init_locked(struct bge_softc *sc) 3733 { 3734 struct ifnet *ifp; 3735 uint16_t *m; 3736 3737 BGE_LOCK_ASSERT(sc); 3738 3739 ifp = sc->bge_ifp; 3740 3741 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3742 return; 3743 3744 /* Cancel pending I/O and flush buffers. */ 3745 bge_stop(sc); 3746 3747 bge_stop_fw(sc); 3748 bge_sig_pre_reset(sc, BGE_RESET_START); 3749 bge_reset(sc); 3750 bge_sig_legacy(sc, BGE_RESET_START); 3751 bge_sig_post_reset(sc, BGE_RESET_START); 3752 3753 bge_chipinit(sc); 3754 3755 /* 3756 * Init the various state machines, ring 3757 * control blocks and firmware. 3758 */ 3759 if (bge_blockinit(sc)) { 3760 device_printf(sc->bge_dev, "initialization failure\n"); 3761 return; 3762 } 3763 3764 ifp = sc->bge_ifp; 3765 3766 /* Specify MTU. */ 3767 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3768 ETHER_HDR_LEN + ETHER_CRC_LEN + 3769 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 3770 3771 /* Load our MAC address. */ 3772 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3773 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3774 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3775 3776 /* Program promiscuous mode. */ 3777 bge_setpromisc(sc); 3778 3779 /* Program multicast filter. */ 3780 bge_setmulti(sc); 3781 3782 /* Program VLAN tag stripping. */ 3783 bge_setvlan(sc); 3784 3785 /* Init RX ring. */ 3786 bge_init_rx_ring_std(sc); 3787 3788 /* 3789 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3790 * memory to insure that the chip has in fact read the first 3791 * entry of the ring. 3792 */ 3793 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3794 uint32_t v, i; 3795 for (i = 0; i < 10; i++) { 3796 DELAY(20); 3797 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3798 if (v == (MCLBYTES - ETHER_ALIGN)) 3799 break; 3800 } 3801 if (i == 10) 3802 device_printf (sc->bge_dev, 3803 "5705 A0 chip failed to load RX ring\n"); 3804 } 3805 3806 /* Init jumbo RX ring. */ 3807 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3808 bge_init_rx_ring_jumbo(sc); 3809 3810 /* Init our RX return ring index. */ 3811 sc->bge_rx_saved_considx = 0; 3812 3813 /* Init our RX/TX stat counters. */ 3814 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3815 3816 /* Init TX ring. */ 3817 bge_init_tx_ring(sc); 3818 3819 /* Turn on transmitter. */ 3820 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3821 3822 /* Turn on receiver. */ 3823 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3824 3825 /* Tell firmware we're alive. */ 3826 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3827 3828 #ifdef DEVICE_POLLING 3829 /* Disable interrupts if we are polling. */ 3830 if (ifp->if_capenable & IFCAP_POLLING) { 3831 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3832 BGE_PCIMISCCTL_MASK_PCI_INTR); 3833 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3834 } else 3835 #endif 3836 3837 /* Enable host interrupts. */ 3838 { 3839 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3840 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3841 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3842 } 3843 3844 bge_ifmedia_upd_locked(ifp); 3845 3846 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3848 3849 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3850 } 3851 3852 static void 3853 bge_init(void *xsc) 3854 { 3855 struct bge_softc *sc = xsc; 3856 3857 BGE_LOCK(sc); 3858 bge_init_locked(sc); 3859 BGE_UNLOCK(sc); 3860 } 3861 3862 /* 3863 * Set media options. 3864 */ 3865 static int 3866 bge_ifmedia_upd(struct ifnet *ifp) 3867 { 3868 struct bge_softc *sc = ifp->if_softc; 3869 int res; 3870 3871 BGE_LOCK(sc); 3872 res = bge_ifmedia_upd_locked(ifp); 3873 BGE_UNLOCK(sc); 3874 3875 return (res); 3876 } 3877 3878 static int 3879 bge_ifmedia_upd_locked(struct ifnet *ifp) 3880 { 3881 struct bge_softc *sc = ifp->if_softc; 3882 struct mii_data *mii; 3883 struct ifmedia *ifm; 3884 3885 BGE_LOCK_ASSERT(sc); 3886 3887 ifm = &sc->bge_ifmedia; 3888 3889 /* If this is a 1000baseX NIC, enable the TBI port. */ 3890 if (sc->bge_flags & BGE_FLAG_TBI) { 3891 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3892 return (EINVAL); 3893 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3894 case IFM_AUTO: 3895 /* 3896 * The BCM5704 ASIC appears to have a special 3897 * mechanism for programming the autoneg 3898 * advertisement registers in TBI mode. 3899 */ 3900 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3901 uint32_t sgdig; 3902 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3903 if (sgdig & BGE_SGDIGSTS_DONE) { 3904 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3905 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3906 sgdig |= BGE_SGDIGCFG_AUTO | 3907 BGE_SGDIGCFG_PAUSE_CAP | 3908 BGE_SGDIGCFG_ASYM_PAUSE; 3909 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3910 sgdig | BGE_SGDIGCFG_SEND); 3911 DELAY(5); 3912 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3913 } 3914 } 3915 break; 3916 case IFM_1000_SX: 3917 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3918 BGE_CLRBIT(sc, BGE_MAC_MODE, 3919 BGE_MACMODE_HALF_DUPLEX); 3920 } else { 3921 BGE_SETBIT(sc, BGE_MAC_MODE, 3922 BGE_MACMODE_HALF_DUPLEX); 3923 } 3924 break; 3925 default: 3926 return (EINVAL); 3927 } 3928 return (0); 3929 } 3930 3931 sc->bge_link_evt++; 3932 mii = device_get_softc(sc->bge_miibus); 3933 if (mii->mii_instance) { 3934 struct mii_softc *miisc; 3935 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3936 miisc = LIST_NEXT(miisc, mii_list)) 3937 mii_phy_reset(miisc); 3938 } 3939 mii_mediachg(mii); 3940 3941 /* 3942 * Force an interrupt so that we will call bge_link_upd 3943 * if needed and clear any pending link state attention. 3944 * Without this we are not getting any further interrupts 3945 * for link state changes and thus will not UP the link and 3946 * not be able to send in bge_start_locked. The only 3947 * way to get things working was to receive a packet and 3948 * get an RX intr. 3949 * bge_tick should help for fiber cards and we might not 3950 * need to do this here if BGE_FLAG_TBI is set but as 3951 * we poll for fiber anyway it should not harm. 3952 */ 3953 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3954 #ifdef notyet 3955 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ATTN); 3956 #endif 3957 3958 return (0); 3959 } 3960 3961 /* 3962 * Report current media status. 3963 */ 3964 static void 3965 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3966 { 3967 struct bge_softc *sc = ifp->if_softc; 3968 struct mii_data *mii; 3969 3970 BGE_LOCK(sc); 3971 3972 if (sc->bge_flags & BGE_FLAG_TBI) { 3973 ifmr->ifm_status = IFM_AVALID; 3974 ifmr->ifm_active = IFM_ETHER; 3975 if (CSR_READ_4(sc, BGE_MAC_STS) & 3976 BGE_MACSTAT_TBI_PCS_SYNCHED) 3977 ifmr->ifm_status |= IFM_ACTIVE; 3978 else { 3979 ifmr->ifm_active |= IFM_NONE; 3980 BGE_UNLOCK(sc); 3981 return; 3982 } 3983 ifmr->ifm_active |= IFM_1000_SX; 3984 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3985 ifmr->ifm_active |= IFM_HDX; 3986 else 3987 ifmr->ifm_active |= IFM_FDX; 3988 BGE_UNLOCK(sc); 3989 return; 3990 } 3991 3992 mii = device_get_softc(sc->bge_miibus); 3993 mii_pollstat(mii); 3994 ifmr->ifm_active = mii->mii_media_active; 3995 ifmr->ifm_status = mii->mii_media_status; 3996 3997 BGE_UNLOCK(sc); 3998 } 3999 4000 static int 4001 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4002 { 4003 struct bge_softc *sc = ifp->if_softc; 4004 struct ifreq *ifr = (struct ifreq *) data; 4005 struct mii_data *mii; 4006 int flags, mask, error = 0; 4007 4008 switch (command) { 4009 case SIOCSIFMTU: 4010 if (ifr->ifr_mtu < ETHERMIN || 4011 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4012 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4013 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4014 ifr->ifr_mtu > ETHERMTU)) 4015 error = EINVAL; 4016 else if (ifp->if_mtu != ifr->ifr_mtu) { 4017 ifp->if_mtu = ifr->ifr_mtu; 4018 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4019 bge_init(sc); 4020 } 4021 break; 4022 case SIOCSIFFLAGS: 4023 BGE_LOCK(sc); 4024 if (ifp->if_flags & IFF_UP) { 4025 /* 4026 * If only the state of the PROMISC flag changed, 4027 * then just use the 'set promisc mode' command 4028 * instead of reinitializing the entire NIC. Doing 4029 * a full re-init means reloading the firmware and 4030 * waiting for it to start up, which may take a 4031 * second or two. Similarly for ALLMULTI. 4032 */ 4033 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4034 flags = ifp->if_flags ^ sc->bge_if_flags; 4035 if (flags & IFF_PROMISC) 4036 bge_setpromisc(sc); 4037 if (flags & IFF_ALLMULTI) 4038 bge_setmulti(sc); 4039 } else 4040 bge_init_locked(sc); 4041 } else { 4042 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4043 bge_stop(sc); 4044 } 4045 } 4046 sc->bge_if_flags = ifp->if_flags; 4047 BGE_UNLOCK(sc); 4048 error = 0; 4049 break; 4050 case SIOCADDMULTI: 4051 case SIOCDELMULTI: 4052 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4053 BGE_LOCK(sc); 4054 bge_setmulti(sc); 4055 BGE_UNLOCK(sc); 4056 error = 0; 4057 } 4058 break; 4059 case SIOCSIFMEDIA: 4060 case SIOCGIFMEDIA: 4061 if (sc->bge_flags & BGE_FLAG_TBI) { 4062 error = ifmedia_ioctl(ifp, ifr, 4063 &sc->bge_ifmedia, command); 4064 } else { 4065 mii = device_get_softc(sc->bge_miibus); 4066 error = ifmedia_ioctl(ifp, ifr, 4067 &mii->mii_media, command); 4068 } 4069 break; 4070 case SIOCSIFCAP: 4071 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4072 #ifdef DEVICE_POLLING 4073 if (mask & IFCAP_POLLING) { 4074 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4075 error = ether_poll_register(bge_poll, ifp); 4076 if (error) 4077 return (error); 4078 BGE_LOCK(sc); 4079 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4080 BGE_PCIMISCCTL_MASK_PCI_INTR); 4081 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4082 ifp->if_capenable |= IFCAP_POLLING; 4083 BGE_UNLOCK(sc); 4084 } else { 4085 error = ether_poll_deregister(ifp); 4086 /* Enable interrupt even in error case */ 4087 BGE_LOCK(sc); 4088 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4089 BGE_PCIMISCCTL_MASK_PCI_INTR); 4090 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4091 ifp->if_capenable &= ~IFCAP_POLLING; 4092 BGE_UNLOCK(sc); 4093 } 4094 } 4095 #endif 4096 if (mask & IFCAP_HWCSUM) { 4097 ifp->if_capenable ^= IFCAP_HWCSUM; 4098 if (IFCAP_HWCSUM & ifp->if_capenable && 4099 IFCAP_HWCSUM & ifp->if_capabilities) 4100 ifp->if_hwassist = BGE_CSUM_FEATURES; 4101 else 4102 ifp->if_hwassist = 0; 4103 #ifdef VLAN_CAPABILITIES 4104 VLAN_CAPABILITIES(ifp); 4105 #endif 4106 } 4107 4108 if (mask & IFCAP_VLAN_MTU) { 4109 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4110 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4111 bge_init(sc); 4112 } 4113 4114 if (mask & IFCAP_VLAN_HWTAGGING) { 4115 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4116 BGE_LOCK(sc); 4117 bge_setvlan(sc); 4118 BGE_UNLOCK(sc); 4119 #ifdef VLAN_CAPABILITIES 4120 VLAN_CAPABILITIES(ifp); 4121 #endif 4122 } 4123 4124 break; 4125 default: 4126 error = ether_ioctl(ifp, command, data); 4127 break; 4128 } 4129 4130 return (error); 4131 } 4132 4133 static void 4134 bge_watchdog(struct bge_softc *sc) 4135 { 4136 struct ifnet *ifp; 4137 4138 BGE_LOCK_ASSERT(sc); 4139 4140 if (sc->bge_timer == 0 || --sc->bge_timer) 4141 return; 4142 4143 ifp = sc->bge_ifp; 4144 4145 if_printf(ifp, "watchdog timeout -- resetting\n"); 4146 4147 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4148 bge_init_locked(sc); 4149 4150 ifp->if_oerrors++; 4151 } 4152 4153 /* 4154 * Stop the adapter and free any mbufs allocated to the 4155 * RX and TX lists. 4156 */ 4157 static void 4158 bge_stop(struct bge_softc *sc) 4159 { 4160 struct ifnet *ifp; 4161 struct ifmedia_entry *ifm; 4162 struct mii_data *mii = NULL; 4163 int mtmp, itmp; 4164 4165 BGE_LOCK_ASSERT(sc); 4166 4167 ifp = sc->bge_ifp; 4168 4169 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 4170 mii = device_get_softc(sc->bge_miibus); 4171 4172 callout_stop(&sc->bge_stat_ch); 4173 4174 /* 4175 * Disable all of the receiver blocks. 4176 */ 4177 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4178 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4179 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4180 if (!(BGE_IS_5705_PLUS(sc))) 4181 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4182 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4183 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4184 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4185 4186 /* 4187 * Disable all of the transmit blocks. 4188 */ 4189 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4190 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4191 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4192 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4193 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4194 if (!(BGE_IS_5705_PLUS(sc))) 4195 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4196 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4197 4198 /* 4199 * Shut down all of the memory managers and related 4200 * state machines. 4201 */ 4202 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4203 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4204 if (!(BGE_IS_5705_PLUS(sc))) 4205 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4206 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4207 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4208 if (!(BGE_IS_5705_PLUS(sc))) { 4209 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4210 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4211 } 4212 4213 /* Disable host interrupts. */ 4214 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4215 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4216 4217 /* 4218 * Tell firmware we're shutting down. 4219 */ 4220 4221 bge_stop_fw(sc); 4222 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4223 bge_reset(sc); 4224 bge_sig_legacy(sc, BGE_RESET_STOP); 4225 bge_sig_post_reset(sc, BGE_RESET_STOP); 4226 4227 /* 4228 * Keep the ASF firmware running if up. 4229 */ 4230 if (sc->bge_asf_mode & ASF_STACKUP) 4231 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4232 else 4233 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4234 4235 /* Free the RX lists. */ 4236 bge_free_rx_ring_std(sc); 4237 4238 /* Free jumbo RX list. */ 4239 if (BGE_IS_JUMBO_CAPABLE(sc)) 4240 bge_free_rx_ring_jumbo(sc); 4241 4242 /* Free TX buffers. */ 4243 bge_free_tx_ring(sc); 4244 4245 /* 4246 * Isolate/power down the PHY, but leave the media selection 4247 * unchanged so that things will be put back to normal when 4248 * we bring the interface back up. 4249 */ 4250 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4251 itmp = ifp->if_flags; 4252 ifp->if_flags |= IFF_UP; 4253 /* 4254 * If we are called from bge_detach(), mii is already NULL. 4255 */ 4256 if (mii != NULL) { 4257 ifm = mii->mii_media.ifm_cur; 4258 mtmp = ifm->ifm_media; 4259 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4260 mii_mediachg(mii); 4261 ifm->ifm_media = mtmp; 4262 } 4263 ifp->if_flags = itmp; 4264 } 4265 4266 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4267 4268 /* Clear MAC's link state (PHY may still have link UP). */ 4269 if (bootverbose && sc->bge_link) 4270 if_printf(sc->bge_ifp, "link DOWN\n"); 4271 sc->bge_link = 0; 4272 4273 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4274 } 4275 4276 /* 4277 * Stop all chip I/O so that the kernel's probe routines don't 4278 * get confused by errant DMAs when rebooting. 4279 */ 4280 static void 4281 bge_shutdown(device_t dev) 4282 { 4283 struct bge_softc *sc; 4284 4285 sc = device_get_softc(dev); 4286 4287 BGE_LOCK(sc); 4288 bge_stop(sc); 4289 bge_reset(sc); 4290 BGE_UNLOCK(sc); 4291 } 4292 4293 static int 4294 bge_suspend(device_t dev) 4295 { 4296 struct bge_softc *sc; 4297 4298 sc = device_get_softc(dev); 4299 BGE_LOCK(sc); 4300 bge_stop(sc); 4301 BGE_UNLOCK(sc); 4302 4303 return (0); 4304 } 4305 4306 static int 4307 bge_resume(device_t dev) 4308 { 4309 struct bge_softc *sc; 4310 struct ifnet *ifp; 4311 4312 sc = device_get_softc(dev); 4313 BGE_LOCK(sc); 4314 ifp = sc->bge_ifp; 4315 if (ifp->if_flags & IFF_UP) { 4316 bge_init_locked(sc); 4317 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4318 bge_start_locked(ifp); 4319 } 4320 BGE_UNLOCK(sc); 4321 4322 return (0); 4323 } 4324 4325 static void 4326 bge_link_upd(struct bge_softc *sc) 4327 { 4328 struct mii_data *mii; 4329 uint32_t link, status; 4330 4331 BGE_LOCK_ASSERT(sc); 4332 4333 /* Clear 'pending link event' flag. */ 4334 sc->bge_link_evt = 0; 4335 4336 /* 4337 * Process link state changes. 4338 * Grrr. The link status word in the status block does 4339 * not work correctly on the BCM5700 rev AX and BX chips, 4340 * according to all available information. Hence, we have 4341 * to enable MII interrupts in order to properly obtain 4342 * async link changes. Unfortunately, this also means that 4343 * we have to read the MAC status register to detect link 4344 * changes, thereby adding an additional register access to 4345 * the interrupt handler. 4346 * 4347 * XXX: perhaps link state detection procedure used for 4348 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4349 */ 4350 4351 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4352 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4353 status = CSR_READ_4(sc, BGE_MAC_STS); 4354 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4355 mii = device_get_softc(sc->bge_miibus); 4356 mii_pollstat(mii); 4357 if (!sc->bge_link && 4358 mii->mii_media_status & IFM_ACTIVE && 4359 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4360 sc->bge_link++; 4361 if (bootverbose) 4362 if_printf(sc->bge_ifp, "link UP\n"); 4363 } else if (sc->bge_link && 4364 (!(mii->mii_media_status & IFM_ACTIVE) || 4365 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4366 sc->bge_link = 0; 4367 if (bootverbose) 4368 if_printf(sc->bge_ifp, "link DOWN\n"); 4369 } 4370 4371 /* Clear the interrupt. */ 4372 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4373 BGE_EVTENB_MI_INTERRUPT); 4374 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4375 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4376 BRGPHY_INTRS); 4377 } 4378 return; 4379 } 4380 4381 if (sc->bge_flags & BGE_FLAG_TBI) { 4382 status = CSR_READ_4(sc, BGE_MAC_STS); 4383 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4384 if (!sc->bge_link) { 4385 sc->bge_link++; 4386 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4387 BGE_CLRBIT(sc, BGE_MAC_MODE, 4388 BGE_MACMODE_TBI_SEND_CFGS); 4389 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4390 if (bootverbose) 4391 if_printf(sc->bge_ifp, "link UP\n"); 4392 if_link_state_change(sc->bge_ifp, 4393 LINK_STATE_UP); 4394 } 4395 } else if (sc->bge_link) { 4396 sc->bge_link = 0; 4397 if (bootverbose) 4398 if_printf(sc->bge_ifp, "link DOWN\n"); 4399 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4400 } 4401 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4402 /* 4403 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4404 * in status word always set. Workaround this bug by reading 4405 * PHY link status directly. 4406 */ 4407 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4408 4409 if (link != sc->bge_link || 4410 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4411 mii = device_get_softc(sc->bge_miibus); 4412 mii_pollstat(mii); 4413 if (!sc->bge_link && 4414 mii->mii_media_status & IFM_ACTIVE && 4415 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4416 sc->bge_link++; 4417 if (bootverbose) 4418 if_printf(sc->bge_ifp, "link UP\n"); 4419 } else if (sc->bge_link && 4420 (!(mii->mii_media_status & IFM_ACTIVE) || 4421 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4422 sc->bge_link = 0; 4423 if (bootverbose) 4424 if_printf(sc->bge_ifp, "link DOWN\n"); 4425 } 4426 } 4427 } else { 4428 /* 4429 * Discard link events for MII/GMII controllers 4430 * if MI auto-polling is disabled. 4431 */ 4432 } 4433 4434 /* Clear the attention. */ 4435 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4436 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4437 BGE_MACSTAT_LINK_CHANGED); 4438 } 4439 4440 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4441 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4442 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4443 desc) 4444 4445 static void 4446 bge_add_sysctls(struct bge_softc *sc) 4447 { 4448 struct sysctl_ctx_list *ctx; 4449 struct sysctl_oid_list *children, *schildren; 4450 struct sysctl_oid *tree; 4451 4452 ctx = device_get_sysctl_ctx(sc->bge_dev); 4453 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4454 4455 #ifdef BGE_REGISTER_DEBUG 4456 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4457 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4458 "Debug Information"); 4459 4460 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4461 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4462 "Register Read"); 4463 4464 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4465 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4466 "Memory Read"); 4467 4468 #endif 4469 4470 if (BGE_IS_5705_PLUS(sc)) 4471 return; 4472 4473 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4474 NULL, "BGE Statistics"); 4475 schildren = children = SYSCTL_CHILDREN(tree); 4476 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4477 children, COSFramesDroppedDueToFilters, 4478 "FramesDroppedDueToFilters"); 4479 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4480 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4481 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4482 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4483 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4484 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4485 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4486 children, ifInDiscards, "InputDiscards"); 4487 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4488 children, ifInErrors, "InputErrors"); 4489 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4490 children, nicRecvThresholdHit, "RecvThresholdHit"); 4491 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4492 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4493 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4494 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4495 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4496 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4497 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4498 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4499 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4500 children, nicRingStatusUpdate, "RingStatusUpdate"); 4501 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4502 children, nicInterrupts, "Interrupts"); 4503 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4504 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4505 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4506 children, nicSendThresholdHit, "SendThresholdHit"); 4507 4508 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4509 NULL, "BGE RX Statistics"); 4510 children = SYSCTL_CHILDREN(tree); 4511 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4512 children, rxstats.ifHCInOctets, "Octets"); 4513 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4514 children, rxstats.etherStatsFragments, "Fragments"); 4515 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4516 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4517 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4518 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4519 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4520 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4521 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4522 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4523 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4524 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4525 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4526 children, rxstats.xoffPauseFramesReceived, 4527 "xoffPauseFramesReceived"); 4528 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4529 children, rxstats.macControlFramesReceived, 4530 "ControlFramesReceived"); 4531 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4532 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4533 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4534 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4535 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4536 children, rxstats.etherStatsJabbers, "Jabbers"); 4537 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4538 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4539 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4540 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4541 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4542 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4543 4544 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4545 NULL, "BGE TX Statistics"); 4546 children = SYSCTL_CHILDREN(tree); 4547 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4548 children, txstats.ifHCOutOctets, "Octets"); 4549 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4550 children, txstats.etherStatsCollisions, "Collisions"); 4551 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4552 children, txstats.outXonSent, "XonSent"); 4553 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4554 children, txstats.outXoffSent, "XoffSent"); 4555 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4556 children, txstats.flowControlDone, "flowControlDone"); 4557 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4558 children, txstats.dot3StatsInternalMacTransmitErrors, 4559 "InternalMacTransmitErrors"); 4560 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4561 children, txstats.dot3StatsSingleCollisionFrames, 4562 "SingleCollisionFrames"); 4563 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4564 children, txstats.dot3StatsMultipleCollisionFrames, 4565 "MultipleCollisionFrames"); 4566 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4567 children, txstats.dot3StatsDeferredTransmissions, 4568 "DeferredTransmissions"); 4569 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4570 children, txstats.dot3StatsExcessiveCollisions, 4571 "ExcessiveCollisions"); 4572 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4573 children, txstats.dot3StatsLateCollisions, 4574 "LateCollisions"); 4575 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4576 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4577 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4578 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4579 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4580 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4581 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4582 children, txstats.dot3StatsCarrierSenseErrors, 4583 "CarrierSenseErrors"); 4584 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4585 children, txstats.ifOutDiscards, "Discards"); 4586 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4587 children, txstats.ifOutErrors, "Errors"); 4588 } 4589 4590 static int 4591 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4592 { 4593 struct bge_softc *sc; 4594 uint32_t result; 4595 int offset; 4596 4597 sc = (struct bge_softc *)arg1; 4598 offset = arg2; 4599 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4600 offsetof(bge_hostaddr, bge_addr_lo)); 4601 return (sysctl_handle_int(oidp, &result, 0, req)); 4602 } 4603 4604 #ifdef BGE_REGISTER_DEBUG 4605 static int 4606 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4607 { 4608 struct bge_softc *sc; 4609 uint16_t *sbdata; 4610 int error; 4611 int result; 4612 int i, j; 4613 4614 result = -1; 4615 error = sysctl_handle_int(oidp, &result, 0, req); 4616 if (error || (req->newptr == NULL)) 4617 return (error); 4618 4619 if (result == 1) { 4620 sc = (struct bge_softc *)arg1; 4621 4622 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4623 printf("Status Block:\n"); 4624 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4625 printf("%06x:", i); 4626 for (j = 0; j < 8; j++) { 4627 printf(" %04x", sbdata[i]); 4628 i += 4; 4629 } 4630 printf("\n"); 4631 } 4632 4633 printf("Registers:\n"); 4634 for (i = 0x800; i < 0xA00; ) { 4635 printf("%06x:", i); 4636 for (j = 0; j < 8; j++) { 4637 printf(" %08x", CSR_READ_4(sc, i)); 4638 i += 4; 4639 } 4640 printf("\n"); 4641 } 4642 4643 printf("Hardware Flags:\n"); 4644 if (BGE_IS_575X_PLUS(sc)) 4645 printf(" - 575X Plus\n"); 4646 if (BGE_IS_5705_PLUS(sc)) 4647 printf(" - 5705 Plus\n"); 4648 if (BGE_IS_5714_FAMILY(sc)) 4649 printf(" - 5714 Family\n"); 4650 if (BGE_IS_5700_FAMILY(sc)) 4651 printf(" - 5700 Family\n"); 4652 if (sc->bge_flags & BGE_FLAG_JUMBO) 4653 printf(" - Supports Jumbo Frames\n"); 4654 if (sc->bge_flags & BGE_FLAG_PCIX) 4655 printf(" - PCI-X Bus\n"); 4656 if (sc->bge_flags & BGE_FLAG_PCIE) 4657 printf(" - PCI Express Bus\n"); 4658 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4659 printf(" - No 3 LEDs\n"); 4660 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4661 printf(" - RX Alignment Bug\n"); 4662 } 4663 4664 return (error); 4665 } 4666 4667 static int 4668 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4669 { 4670 struct bge_softc *sc; 4671 int error; 4672 uint16_t result; 4673 uint32_t val; 4674 4675 result = -1; 4676 error = sysctl_handle_int(oidp, &result, 0, req); 4677 if (error || (req->newptr == NULL)) 4678 return (error); 4679 4680 if (result < 0x8000) { 4681 sc = (struct bge_softc *)arg1; 4682 val = CSR_READ_4(sc, result); 4683 printf("reg 0x%06X = 0x%08X\n", result, val); 4684 } 4685 4686 return (error); 4687 } 4688 4689 static int 4690 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4691 { 4692 struct bge_softc *sc; 4693 int error; 4694 uint16_t result; 4695 uint32_t val; 4696 4697 result = -1; 4698 error = sysctl_handle_int(oidp, &result, 0, req); 4699 if (error || (req->newptr == NULL)) 4700 return (error); 4701 4702 if (result < 0x8000) { 4703 sc = (struct bge_softc *)arg1; 4704 val = bge_readmem_ind(sc, result); 4705 printf("mem 0x%06X = 0x%08X\n", result, val); 4706 } 4707 4708 return (error); 4709 } 4710 #endif 4711 4712 static int 4713 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4714 { 4715 uint32_t mac_addr; 4716 int ret = 1; 4717 4718 mac_addr = bge_readmem_ind(sc, 0x0c14); 4719 if ((mac_addr >> 16) == 0x484b) { 4720 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4721 ether_addr[1] = (uint8_t)mac_addr; 4722 mac_addr = bge_readmem_ind(sc, 0x0c18); 4723 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4724 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4725 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4726 ether_addr[5] = (uint8_t)mac_addr; 4727 ret = 0; 4728 } 4729 return ret; 4730 } 4731 4732 static int 4733 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4734 { 4735 int mac_offset = BGE_EE_MAC_OFFSET; 4736 4737 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4738 mac_offset = BGE_EE_MAC_OFFSET_5906; 4739 4740 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4741 } 4742 4743 static int 4744 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4745 { 4746 if (!(sc->bge_flags & BGE_FLAG_EEPROM)) 4747 return 1; 4748 4749 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4750 ETHER_ADDR_LEN); 4751 } 4752 4753 static int 4754 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4755 { 4756 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4757 /* NOTE: Order is critical */ 4758 bge_get_eaddr_mem, 4759 bge_get_eaddr_nvram, 4760 bge_get_eaddr_eeprom, 4761 NULL 4762 }; 4763 const bge_eaddr_fcn_t *func; 4764 4765 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4766 if ((*func)(sc, eaddr) == 0) 4767 break; 4768 } 4769 return (*func == NULL ? ENXIO : 0); 4770 } 4771