xref: /freebsd/sys/dev/bge/if_bge.c (revision 282a3889ebf826db9839be296ff1dd903f6d6d6e)
1 /*-
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36 
37 /*
38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39  *
40  * The Broadcom BCM5700 is based on technology originally developed by
41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45  * frames, highly configurable RX filtering, and 16 RX and TX queues
46  * (which, along with RX filter rules, can be used for QOS applications).
47  * Other features, such as TCP segmentation, may be available as part
48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49  * firmware images can be stored in hardware and need not be compiled
50  * into the driver.
51  *
52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54  *
55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57  * does not support external SSRAM.
58  *
59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
60  * brand name, which is functionally similar but lacks PCI-X support.
61  *
62  * Without external SSRAM, you can only have at most 4 TX rings,
63  * and the use of the mini RX ring is disabled. This seems to imply
64  * that these features are simply not available on the BCM5701. As a
65  * result, this driver does not implement any support for the mini RX
66  * ring.
67  */
68 
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72 
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 
84 #include <net/if.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
89 
90 #include <net/bpf.h>
91 
92 #include <net/if_types.h>
93 #include <net/if_vlan_var.h>
94 
95 #include <netinet/in_systm.h>
96 #include <netinet/in.h>
97 #include <netinet/ip.h>
98 
99 #include <machine/bus.h>
100 #include <machine/resource.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103 
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106 #include "miidevs.h"
107 #include <dev/mii/brgphyreg.h>
108 
109 #ifdef __sparc64__
110 #include <dev/ofw/ofw_bus.h>
111 #include <dev/ofw/openfirm.h>
112 #include <machine/ofw_machdep.h>
113 #include <machine/ver.h>
114 #endif
115 
116 #include <dev/pci/pcireg.h>
117 #include <dev/pci/pcivar.h>
118 
119 #include <dev/bge/if_bgereg.h>
120 
121 #define	BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
122 #define	ETHER_MIN_NOPAD		(ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
123 
124 MODULE_DEPEND(bge, pci, 1, 1, 1);
125 MODULE_DEPEND(bge, ether, 1, 1, 1);
126 MODULE_DEPEND(bge, miibus, 1, 1, 1);
127 
128 /* "device miibus" required.  See GENERIC if you get errors here. */
129 #include "miibus_if.h"
130 
131 /*
132  * Various supported device vendors/types and their names. Note: the
133  * spec seems to indicate that the hardware still has Alteon's vendor
134  * ID burned into it, though it will always be overriden by the vendor
135  * ID in the EEPROM. Just to be safe, we cover all possibilities.
136  */
137 static struct bge_type {
138 	uint16_t	bge_vid;
139 	uint16_t	bge_did;
140 } bge_devs[] = {
141 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5700 },
142 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5701 },
143 
144 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1000 },
145 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1002 },
146 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC9100 },
147 
148 	{ APPLE_VENDORID,	APPLE_DEVICE_BCM5701 },
149 
150 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5700 },
151 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5701 },
152 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702 },
153 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702_ALT },
154 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702X },
155 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703 },
156 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703_ALT },
157 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703X },
158 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704C },
159 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S },
160 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S_ALT },
161 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705 },
162 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705F },
163 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705K },
164 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M },
165 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M_ALT },
166 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714C },
167 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714S },
168 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715 },
169 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715S },
170 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5720 },
171 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5721 },
172 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750 },
173 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750M },
174 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751 },
175 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751F },
176 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751M },
177 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752 },
178 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752M },
179 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753 },
180 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753F },
181 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753M },
182 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754 },
183 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754M },
184 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755 },
185 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755M },
186 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780 },
187 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780S },
188 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5781 },
189 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5782 },
190 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5786 },
191 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787 },
192 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787M },
193 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5788 },
194 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5789 },
195 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901 },
196 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901A2 },
197 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5903M },
198 
199 	{ SK_VENDORID,		SK_DEVICEID_ALTIMA },
200 
201 	{ TC_VENDORID,		TC_DEVICEID_3C996 },
202 
203 	{ 0, 0 }
204 };
205 
206 static const struct bge_vendor {
207 	uint16_t	v_id;
208 	const char	*v_name;
209 } bge_vendors[] = {
210 	{ ALTEON_VENDORID,	"Alteon" },
211 	{ ALTIMA_VENDORID,	"Altima" },
212 	{ APPLE_VENDORID,	"Apple" },
213 	{ BCOM_VENDORID,	"Broadcom" },
214 	{ SK_VENDORID,		"SysKonnect" },
215 	{ TC_VENDORID,		"3Com" },
216 
217 	{ 0, NULL }
218 };
219 
220 static const struct bge_revision {
221 	uint32_t	br_chipid;
222 	const char	*br_name;
223 } bge_revisions[] = {
224 	{ BGE_CHIPID_BCM5700_A0,	"BCM5700 A0" },
225 	{ BGE_CHIPID_BCM5700_A1,	"BCM5700 A1" },
226 	{ BGE_CHIPID_BCM5700_B0,	"BCM5700 B0" },
227 	{ BGE_CHIPID_BCM5700_B1,	"BCM5700 B1" },
228 	{ BGE_CHIPID_BCM5700_B2,	"BCM5700 B2" },
229 	{ BGE_CHIPID_BCM5700_B3,	"BCM5700 B3" },
230 	{ BGE_CHIPID_BCM5700_ALTIMA,	"BCM5700 Altima" },
231 	{ BGE_CHIPID_BCM5700_C0,	"BCM5700 C0" },
232 	{ BGE_CHIPID_BCM5701_A0,	"BCM5701 A0" },
233 	{ BGE_CHIPID_BCM5701_B0,	"BCM5701 B0" },
234 	{ BGE_CHIPID_BCM5701_B2,	"BCM5701 B2" },
235 	{ BGE_CHIPID_BCM5701_B5,	"BCM5701 B5" },
236 	{ BGE_CHIPID_BCM5703_A0,	"BCM5703 A0" },
237 	{ BGE_CHIPID_BCM5703_A1,	"BCM5703 A1" },
238 	{ BGE_CHIPID_BCM5703_A2,	"BCM5703 A2" },
239 	{ BGE_CHIPID_BCM5703_A3,	"BCM5703 A3" },
240 	{ BGE_CHIPID_BCM5703_B0,	"BCM5703 B0" },
241 	{ BGE_CHIPID_BCM5704_A0,	"BCM5704 A0" },
242 	{ BGE_CHIPID_BCM5704_A1,	"BCM5704 A1" },
243 	{ BGE_CHIPID_BCM5704_A2,	"BCM5704 A2" },
244 	{ BGE_CHIPID_BCM5704_A3,	"BCM5704 A3" },
245 	{ BGE_CHIPID_BCM5704_B0,	"BCM5704 B0" },
246 	{ BGE_CHIPID_BCM5705_A0,	"BCM5705 A0" },
247 	{ BGE_CHIPID_BCM5705_A1,	"BCM5705 A1" },
248 	{ BGE_CHIPID_BCM5705_A2,	"BCM5705 A2" },
249 	{ BGE_CHIPID_BCM5705_A3,	"BCM5705 A3" },
250 	{ BGE_CHIPID_BCM5750_A0,	"BCM5750 A0" },
251 	{ BGE_CHIPID_BCM5750_A1,	"BCM5750 A1" },
252 	{ BGE_CHIPID_BCM5750_A3,	"BCM5750 A3" },
253 	{ BGE_CHIPID_BCM5750_B0,	"BCM5750 B0" },
254 	{ BGE_CHIPID_BCM5750_B1,	"BCM5750 B1" },
255 	{ BGE_CHIPID_BCM5750_C0,	"BCM5750 C0" },
256 	{ BGE_CHIPID_BCM5750_C1,	"BCM5750 C1" },
257 	{ BGE_CHIPID_BCM5750_C2,	"BCM5750 C2" },
258 	{ BGE_CHIPID_BCM5714_A0,	"BCM5714 A0" },
259 	{ BGE_CHIPID_BCM5752_A0,	"BCM5752 A0" },
260 	{ BGE_CHIPID_BCM5752_A1,	"BCM5752 A1" },
261 	{ BGE_CHIPID_BCM5752_A2,	"BCM5752 A2" },
262 	{ BGE_CHIPID_BCM5714_B0,	"BCM5714 B0" },
263 	{ BGE_CHIPID_BCM5714_B3,	"BCM5714 B3" },
264 	{ BGE_CHIPID_BCM5715_A0,	"BCM5715 A0" },
265 	{ BGE_CHIPID_BCM5715_A1,	"BCM5715 A1" },
266 	{ BGE_CHIPID_BCM5715_A3,	"BCM5715 A3" },
267 	{ BGE_CHIPID_BCM5755_A0,	"BCM5755 A0" },
268 	{ BGE_CHIPID_BCM5755_A1,	"BCM5755 A1" },
269 	{ BGE_CHIPID_BCM5755_A2,	"BCM5755 A2" },
270 	/* 5754 and 5787 share the same ASIC ID */
271 	{ BGE_CHIPID_BCM5787_A0,	"BCM5754/5787 A0" },
272 	{ BGE_CHIPID_BCM5787_A1,	"BCM5754/5787 A1" },
273 	{ BGE_CHIPID_BCM5787_A2,	"BCM5754/5787 A2" },
274 
275 	{ 0, NULL }
276 };
277 
278 /*
279  * Some defaults for major revisions, so that newer steppings
280  * that we don't know about have a shot at working.
281  */
282 static const struct bge_revision bge_majorrevs[] = {
283 	{ BGE_ASICREV_BCM5700,		"unknown BCM5700" },
284 	{ BGE_ASICREV_BCM5701,		"unknown BCM5701" },
285 	{ BGE_ASICREV_BCM5703,		"unknown BCM5703" },
286 	{ BGE_ASICREV_BCM5704,		"unknown BCM5704" },
287 	{ BGE_ASICREV_BCM5705,		"unknown BCM5705" },
288 	{ BGE_ASICREV_BCM5750,		"unknown BCM5750" },
289 	{ BGE_ASICREV_BCM5714_A0,	"unknown BCM5714" },
290 	{ BGE_ASICREV_BCM5752,		"unknown BCM5752" },
291 	{ BGE_ASICREV_BCM5780,		"unknown BCM5780" },
292 	{ BGE_ASICREV_BCM5714,		"unknown BCM5714" },
293 	{ BGE_ASICREV_BCM5755,		"unknown BCM5755" },
294 	/* 5754 and 5787 share the same ASIC ID */
295 	{ BGE_ASICREV_BCM5787,		"unknown BCM5754/5787" },
296 
297 	{ 0, NULL }
298 };
299 
300 #define	BGE_IS_JUMBO_CAPABLE(sc)	((sc)->bge_flags & BGE_FLAG_JUMBO)
301 #define	BGE_IS_5700_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
302 #define	BGE_IS_5705_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5705_PLUS)
303 #define	BGE_IS_5714_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
304 #define	BGE_IS_575X_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_575X_PLUS)
305 
306 const struct bge_revision * bge_lookup_rev(uint32_t);
307 const struct bge_vendor * bge_lookup_vendor(uint16_t);
308 static int bge_probe(device_t);
309 static int bge_attach(device_t);
310 static int bge_detach(device_t);
311 static int bge_suspend(device_t);
312 static int bge_resume(device_t);
313 static void bge_release_resources(struct bge_softc *);
314 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
315 static int bge_dma_alloc(device_t);
316 static void bge_dma_free(struct bge_softc *);
317 
318 static void bge_txeof(struct bge_softc *);
319 static void bge_rxeof(struct bge_softc *);
320 
321 static void bge_asf_driver_up (struct bge_softc *);
322 static void bge_tick(void *);
323 static void bge_stats_update(struct bge_softc *);
324 static void bge_stats_update_regs(struct bge_softc *);
325 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
326 
327 static void bge_intr(void *);
328 static void bge_start_locked(struct ifnet *);
329 static void bge_start(struct ifnet *);
330 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
331 static void bge_init_locked(struct bge_softc *);
332 static void bge_init(void *);
333 static void bge_stop(struct bge_softc *);
334 static void bge_watchdog(struct bge_softc *);
335 static void bge_shutdown(device_t);
336 static int bge_ifmedia_upd_locked(struct ifnet *);
337 static int bge_ifmedia_upd(struct ifnet *);
338 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
339 
340 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
341 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
342 
343 static void bge_setpromisc(struct bge_softc *);
344 static void bge_setmulti(struct bge_softc *);
345 static void bge_setvlan(struct bge_softc *);
346 
347 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
348 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
349 static int bge_init_rx_ring_std(struct bge_softc *);
350 static void bge_free_rx_ring_std(struct bge_softc *);
351 static int bge_init_rx_ring_jumbo(struct bge_softc *);
352 static void bge_free_rx_ring_jumbo(struct bge_softc *);
353 static void bge_free_tx_ring(struct bge_softc *);
354 static int bge_init_tx_ring(struct bge_softc *);
355 
356 static int bge_chipinit(struct bge_softc *);
357 static int bge_blockinit(struct bge_softc *);
358 
359 static int bge_has_eeprom(struct bge_softc *);
360 static uint32_t bge_readmem_ind(struct bge_softc *, int);
361 static void bge_writemem_ind(struct bge_softc *, int, int);
362 #ifdef notdef
363 static uint32_t bge_readreg_ind(struct bge_softc *, int);
364 #endif
365 static void bge_writemem_direct(struct bge_softc *, int, int);
366 static void bge_writereg_ind(struct bge_softc *, int, int);
367 
368 static int bge_miibus_readreg(device_t, int, int);
369 static int bge_miibus_writereg(device_t, int, int, int);
370 static void bge_miibus_statchg(device_t);
371 #ifdef DEVICE_POLLING
372 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
373 #endif
374 
375 #define	BGE_RESET_START 1
376 #define	BGE_RESET_STOP  2
377 static void bge_sig_post_reset(struct bge_softc *, int);
378 static void bge_sig_legacy(struct bge_softc *, int);
379 static void bge_sig_pre_reset(struct bge_softc *, int);
380 static int bge_reset(struct bge_softc *);
381 static void bge_link_upd(struct bge_softc *);
382 
383 /*
384  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
385  * leak information to untrusted users.  It is also known to cause alignment
386  * traps on certain architectures.
387  */
388 #ifdef BGE_REGISTER_DEBUG
389 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
390 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
391 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
392 #endif
393 static void bge_add_sysctls(struct bge_softc *);
394 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
395 
396 static device_method_t bge_methods[] = {
397 	/* Device interface */
398 	DEVMETHOD(device_probe,		bge_probe),
399 	DEVMETHOD(device_attach,	bge_attach),
400 	DEVMETHOD(device_detach,	bge_detach),
401 	DEVMETHOD(device_shutdown,	bge_shutdown),
402 	DEVMETHOD(device_suspend,	bge_suspend),
403 	DEVMETHOD(device_resume,	bge_resume),
404 
405 	/* bus interface */
406 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
407 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
408 
409 	/* MII interface */
410 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
411 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
412 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
413 
414 	{ 0, 0 }
415 };
416 
417 static driver_t bge_driver = {
418 	"bge",
419 	bge_methods,
420 	sizeof(struct bge_softc)
421 };
422 
423 static devclass_t bge_devclass;
424 
425 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
426 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
427 
428 static int bge_allow_asf = 1;
429 
430 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
431 
432 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
433 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
434 	"Allow ASF mode if available");
435 
436 #define	SPARC64_BLADE_1500_MODEL	"SUNW,Sun-Blade-1500"
437 #define	SPARC64_BLADE_1500_PATH_BGE	"/pci@1f,700000/network@2"
438 #define	SPARC64_BLADE_2500_MODEL	"SUNW,Sun-Blade-2500"
439 #define	SPARC64_BLADE_2500_PATH_BGE	"/pci@1c,600000/network@3"
440 #define	SPARC64_OFW_SUBVENDOR		"subsystem-vendor-id"
441 
442 static int
443 bge_has_eeprom(struct bge_softc *sc)
444 {
445 #ifdef __sparc64__
446 	char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
447 	device_t dev;
448 	uint32_t subvendor;
449 
450 	dev = sc->bge_dev;
451 
452 	/*
453 	 * The on-board BGEs found in sun4u machines aren't fitted with
454 	 * an EEPROM which means that we have to obtain the MAC address
455 	 * via OFW and that some tests will always fail. We distinguish
456 	 * such BGEs by the subvendor ID, which also has to be obtained
457 	 * from OFW instead of the PCI configuration space as the latter
458 	 * indicates Broadcom as the subvendor of the netboot interface.
459 	 * For early Blade 1500 and 2500 we even have to check the OFW
460 	 * device path as the subvendor ID always defaults to Broadcom
461 	 * there.
462 	 */
463 	if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
464 	    &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
465 	    subvendor == SUN_VENDORID)
466 		return (0);
467 	memset(buf, 0, sizeof(buf));
468 	if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
469 		if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
470 		    strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
471 			return (0);
472 		if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
473 		    strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
474 			return (0);
475 	}
476 #endif
477 	return (1);
478 }
479 
480 static uint32_t
481 bge_readmem_ind(struct bge_softc *sc, int off)
482 {
483 	device_t dev;
484 	uint32_t val;
485 
486 	dev = sc->bge_dev;
487 
488 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
489 	val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
490 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
491 	return (val);
492 }
493 
494 static void
495 bge_writemem_ind(struct bge_softc *sc, int off, int val)
496 {
497 	device_t dev;
498 
499 	dev = sc->bge_dev;
500 
501 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
502 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
503 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
504 }
505 
506 #ifdef notdef
507 static uint32_t
508 bge_readreg_ind(struct bge_softc *sc, int off)
509 {
510 	device_t dev;
511 
512 	dev = sc->bge_dev;
513 
514 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
515 	return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
516 }
517 #endif
518 
519 static void
520 bge_writereg_ind(struct bge_softc *sc, int off, int val)
521 {
522 	device_t dev;
523 
524 	dev = sc->bge_dev;
525 
526 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
527 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
528 }
529 
530 static void
531 bge_writemem_direct(struct bge_softc *sc, int off, int val)
532 {
533 	CSR_WRITE_4(sc, off, val);
534 }
535 
536 /*
537  * Map a single buffer address.
538  */
539 
540 static void
541 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
542 {
543 	struct bge_dmamap_arg *ctx;
544 
545 	if (error)
546 		return;
547 
548 	ctx = arg;
549 
550 	if (nseg > ctx->bge_maxsegs) {
551 		ctx->bge_maxsegs = 0;
552 		return;
553 	}
554 
555 	ctx->bge_busaddr = segs->ds_addr;
556 }
557 
558 /*
559  * Read a byte of data stored in the EEPROM at address 'addr.' The
560  * BCM570x supports both the traditional bitbang interface and an
561  * auto access interface for reading the EEPROM. We use the auto
562  * access method.
563  */
564 static uint8_t
565 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
566 {
567 	int i;
568 	uint32_t byte = 0;
569 
570 	/*
571 	 * Enable use of auto EEPROM access so we can avoid
572 	 * having to use the bitbang method.
573 	 */
574 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
575 
576 	/* Reset the EEPROM, load the clock period. */
577 	CSR_WRITE_4(sc, BGE_EE_ADDR,
578 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
579 	DELAY(20);
580 
581 	/* Issue the read EEPROM command. */
582 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
583 
584 	/* Wait for completion */
585 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
586 		DELAY(10);
587 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
588 			break;
589 	}
590 
591 	if (i == BGE_TIMEOUT * 10) {
592 		device_printf(sc->bge_dev, "EEPROM read timed out\n");
593 		return (1);
594 	}
595 
596 	/* Get result. */
597 	byte = CSR_READ_4(sc, BGE_EE_DATA);
598 
599 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
600 
601 	return (0);
602 }
603 
604 /*
605  * Read a sequence of bytes from the EEPROM.
606  */
607 static int
608 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
609 {
610 	int i, error = 0;
611 	uint8_t byte = 0;
612 
613 	for (i = 0; i < cnt; i++) {
614 		error = bge_eeprom_getbyte(sc, off + i, &byte);
615 		if (error)
616 			break;
617 		*(dest + i) = byte;
618 	}
619 
620 	return (error ? 1 : 0);
621 }
622 
623 static int
624 bge_miibus_readreg(device_t dev, int phy, int reg)
625 {
626 	struct bge_softc *sc;
627 	uint32_t val, autopoll;
628 	int i;
629 
630 	sc = device_get_softc(dev);
631 
632 	/*
633 	 * Broadcom's own driver always assumes the internal
634 	 * PHY is at GMII address 1. On some chips, the PHY responds
635 	 * to accesses at all addresses, which could cause us to
636 	 * bogusly attach the PHY 32 times at probe type. Always
637 	 * restricting the lookup to address 1 is simpler than
638 	 * trying to figure out which chips revisions should be
639 	 * special-cased.
640 	 */
641 	if (phy != 1)
642 		return (0);
643 
644 	/* Reading with autopolling on may trigger PCI errors */
645 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
646 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
647 		BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
648 		DELAY(40);
649 	}
650 
651 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
652 	    BGE_MIPHY(phy) | BGE_MIREG(reg));
653 
654 	for (i = 0; i < BGE_TIMEOUT; i++) {
655 		DELAY(10);
656 		val = CSR_READ_4(sc, BGE_MI_COMM);
657 		if (!(val & BGE_MICOMM_BUSY))
658 			break;
659 	}
660 
661 	if (i == BGE_TIMEOUT) {
662 		device_printf(sc->bge_dev, "PHY read timed out\n");
663 		val = 0;
664 		goto done;
665 	}
666 
667 	val = CSR_READ_4(sc, BGE_MI_COMM);
668 
669 done:
670 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
671 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
672 		DELAY(40);
673 	}
674 
675 	if (val & BGE_MICOMM_READFAIL)
676 		return (0);
677 
678 	return (val & 0xFFFF);
679 }
680 
681 static int
682 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
683 {
684 	struct bge_softc *sc;
685 	uint32_t autopoll;
686 	int i;
687 
688 	sc = device_get_softc(dev);
689 
690 	/* Reading with autopolling on may trigger PCI errors */
691 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
692 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
693 		BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
694 		DELAY(40);
695 	}
696 
697 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
698 	    BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
699 
700 	for (i = 0; i < BGE_TIMEOUT; i++) {
701 		DELAY(10);
702 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
703 			break;
704 	}
705 
706 	if (i == BGE_TIMEOUT) {
707 		device_printf(sc->bge_dev, "PHY write timed out\n");
708 		return (0);
709 	}
710 
711 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
712 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
713 		DELAY(40);
714 	}
715 
716 	return (0);
717 }
718 
719 static void
720 bge_miibus_statchg(device_t dev)
721 {
722 	struct bge_softc *sc;
723 	struct mii_data *mii;
724 	sc = device_get_softc(dev);
725 	mii = device_get_softc(sc->bge_miibus);
726 
727 	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
728 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
729 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
730 	else
731 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
732 
733 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
734 		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
735 	else
736 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
737 }
738 
739 /*
740  * Intialize a standard receive ring descriptor.
741  */
742 static int
743 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
744 {
745 	struct mbuf *m_new = NULL;
746 	struct bge_rx_bd *r;
747 	struct bge_dmamap_arg ctx;
748 	int error;
749 
750 	if (m == NULL) {
751 		m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
752 		if (m_new == NULL)
753 			return (ENOBUFS);
754 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
755 	} else {
756 		m_new = m;
757 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
758 		m_new->m_data = m_new->m_ext.ext_buf;
759 	}
760 
761 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
762 		m_adj(m_new, ETHER_ALIGN);
763 	sc->bge_cdata.bge_rx_std_chain[i] = m_new;
764 	r = &sc->bge_ldata.bge_rx_std_ring[i];
765 	ctx.bge_maxsegs = 1;
766 	ctx.sc = sc;
767 	error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
768 	    sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
769 	    m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
770 	if (error || ctx.bge_maxsegs == 0) {
771 		if (m == NULL) {
772 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
773 			m_freem(m_new);
774 		}
775 		return (ENOMEM);
776 	}
777 	r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
778 	r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
779 	r->bge_flags = BGE_RXBDFLAG_END;
780 	r->bge_len = m_new->m_len;
781 	r->bge_idx = i;
782 
783 	bus_dmamap_sync(sc->bge_cdata.bge_mtag,
784 	    sc->bge_cdata.bge_rx_std_dmamap[i],
785 	    BUS_DMASYNC_PREREAD);
786 
787 	return (0);
788 }
789 
790 /*
791  * Initialize a jumbo receive ring descriptor. This allocates
792  * a jumbo buffer from the pool managed internally by the driver.
793  */
794 static int
795 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
796 {
797 	bus_dma_segment_t segs[BGE_NSEG_JUMBO];
798 	struct bge_extrx_bd *r;
799 	struct mbuf *m_new = NULL;
800 	int nsegs;
801 	int error;
802 
803 	if (m == NULL) {
804 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
805 		if (m_new == NULL)
806 			return (ENOBUFS);
807 
808 		m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
809 		if (!(m_new->m_flags & M_EXT)) {
810 			m_freem(m_new);
811 			return (ENOBUFS);
812 		}
813 		m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
814 	} else {
815 		m_new = m;
816 		m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
817 		m_new->m_data = m_new->m_ext.ext_buf;
818 	}
819 
820 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
821 		m_adj(m_new, ETHER_ALIGN);
822 
823 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
824 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
825 	    m_new, segs, &nsegs, BUS_DMA_NOWAIT);
826 	if (error) {
827 		if (m == NULL)
828 			m_freem(m_new);
829 		return (error);
830 	}
831 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
832 
833 	/*
834 	 * Fill in the extended RX buffer descriptor.
835 	 */
836 	r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
837 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
838 	r->bge_idx = i;
839 	r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
840 	switch (nsegs) {
841 	case 4:
842 		r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
843 		r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
844 		r->bge_len3 = segs[3].ds_len;
845 	case 3:
846 		r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
847 		r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
848 		r->bge_len2 = segs[2].ds_len;
849 	case 2:
850 		r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
851 		r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
852 		r->bge_len1 = segs[1].ds_len;
853 	case 1:
854 		r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
855 		r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
856 		r->bge_len0 = segs[0].ds_len;
857 		break;
858 	default:
859 		panic("%s: %d segments\n", __func__, nsegs);
860 	}
861 
862 	bus_dmamap_sync(sc->bge_cdata.bge_mtag,
863 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
864 	    BUS_DMASYNC_PREREAD);
865 
866 	return (0);
867 }
868 
869 /*
870  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
871  * that's 1MB or memory, which is a lot. For now, we fill only the first
872  * 256 ring entries and hope that our CPU is fast enough to keep up with
873  * the NIC.
874  */
875 static int
876 bge_init_rx_ring_std(struct bge_softc *sc)
877 {
878 	int i;
879 
880 	for (i = 0; i < BGE_SSLOTS; i++) {
881 		if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
882 			return (ENOBUFS);
883 	};
884 
885 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
886 	    sc->bge_cdata.bge_rx_std_ring_map,
887 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
888 
889 	sc->bge_std = i - 1;
890 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
891 
892 	return (0);
893 }
894 
895 static void
896 bge_free_rx_ring_std(struct bge_softc *sc)
897 {
898 	int i;
899 
900 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
901 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
902 			bus_dmamap_sync(sc->bge_cdata.bge_mtag,
903 			    sc->bge_cdata.bge_rx_std_dmamap[i],
904 			    BUS_DMASYNC_POSTREAD);
905 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
906 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
907 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
908 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
909 		}
910 		bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
911 		    sizeof(struct bge_rx_bd));
912 	}
913 }
914 
915 static int
916 bge_init_rx_ring_jumbo(struct bge_softc *sc)
917 {
918 	struct bge_rcb *rcb;
919 	int i;
920 
921 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
922 		if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
923 			return (ENOBUFS);
924 	};
925 
926 	bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
927 	    sc->bge_cdata.bge_rx_jumbo_ring_map,
928 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
929 
930 	sc->bge_jumbo = i - 1;
931 
932 	rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
933 	rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
934 				    BGE_RCB_FLAG_USE_EXT_RX_BD);
935 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
936 
937 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
938 
939 	return (0);
940 }
941 
942 static void
943 bge_free_rx_ring_jumbo(struct bge_softc *sc)
944 {
945 	int i;
946 
947 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
948 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
949 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
950 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
951 			    BUS_DMASYNC_POSTREAD);
952 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
953 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
954 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
955 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
956 		}
957 		bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
958 		    sizeof(struct bge_extrx_bd));
959 	}
960 }
961 
962 static void
963 bge_free_tx_ring(struct bge_softc *sc)
964 {
965 	int i;
966 
967 	if (sc->bge_ldata.bge_tx_ring == NULL)
968 		return;
969 
970 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
971 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
972 			bus_dmamap_sync(sc->bge_cdata.bge_mtag,
973 			    sc->bge_cdata.bge_tx_dmamap[i],
974 			    BUS_DMASYNC_POSTWRITE);
975 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
976 			    sc->bge_cdata.bge_tx_dmamap[i]);
977 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
978 			sc->bge_cdata.bge_tx_chain[i] = NULL;
979 		}
980 		bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
981 		    sizeof(struct bge_tx_bd));
982 	}
983 }
984 
985 static int
986 bge_init_tx_ring(struct bge_softc *sc)
987 {
988 	sc->bge_txcnt = 0;
989 	sc->bge_tx_saved_considx = 0;
990 
991 	/* Initialize transmit producer index for host-memory send ring. */
992 	sc->bge_tx_prodidx = 0;
993 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
994 
995 	/* 5700 b2 errata */
996 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
997 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
998 
999 	/* NIC-memory send ring not used; initialize to zero. */
1000 	CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1001 	/* 5700 b2 errata */
1002 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1003 		CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1004 
1005 	return (0);
1006 }
1007 
1008 static void
1009 bge_setpromisc(struct bge_softc *sc)
1010 {
1011 	struct ifnet *ifp;
1012 
1013 	BGE_LOCK_ASSERT(sc);
1014 
1015 	ifp = sc->bge_ifp;
1016 
1017 	/* Enable or disable promiscuous mode as needed. */
1018 	if (ifp->if_flags & IFF_PROMISC)
1019 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1020 	else
1021 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1022 }
1023 
1024 static void
1025 bge_setmulti(struct bge_softc *sc)
1026 {
1027 	struct ifnet *ifp;
1028 	struct ifmultiaddr *ifma;
1029 	uint32_t hashes[4] = { 0, 0, 0, 0 };
1030 	int h, i;
1031 
1032 	BGE_LOCK_ASSERT(sc);
1033 
1034 	ifp = sc->bge_ifp;
1035 
1036 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1037 		for (i = 0; i < 4; i++)
1038 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1039 		return;
1040 	}
1041 
1042 	/* First, zot all the existing filters. */
1043 	for (i = 0; i < 4; i++)
1044 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1045 
1046 	/* Now program new ones. */
1047 	IF_ADDR_LOCK(ifp);
1048 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1049 		if (ifma->ifma_addr->sa_family != AF_LINK)
1050 			continue;
1051 		h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1052 		    ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1053 		hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1054 	}
1055 	IF_ADDR_UNLOCK(ifp);
1056 
1057 	for (i = 0; i < 4; i++)
1058 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1059 }
1060 
1061 static void
1062 bge_setvlan(struct bge_softc *sc)
1063 {
1064 	struct ifnet *ifp;
1065 
1066 	BGE_LOCK_ASSERT(sc);
1067 
1068 	ifp = sc->bge_ifp;
1069 
1070 	/* Enable or disable VLAN tag stripping as needed. */
1071 	if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1072 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1073 	else
1074 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1075 }
1076 
1077 static void
1078 bge_sig_pre_reset(sc, type)
1079 	struct bge_softc *sc;
1080 	int type;
1081 {
1082 	/*
1083 	 * Some chips don't like this so only do this if ASF is enabled
1084 	 */
1085 	if (sc->bge_asf_mode)
1086 		bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1087 
1088 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1089 		switch (type) {
1090 		case BGE_RESET_START:
1091 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1092 			break;
1093 		case BGE_RESET_STOP:
1094 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1095 			break;
1096 		}
1097 	}
1098 }
1099 
1100 static void
1101 bge_sig_post_reset(sc, type)
1102 	struct bge_softc *sc;
1103 	int type;
1104 {
1105 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1106 		switch (type) {
1107 		case BGE_RESET_START:
1108 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1109 			/* START DONE */
1110 			break;
1111 		case BGE_RESET_STOP:
1112 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1113 			break;
1114 		}
1115 	}
1116 }
1117 
1118 static void
1119 bge_sig_legacy(sc, type)
1120 	struct bge_softc *sc;
1121 	int type;
1122 {
1123 	if (sc->bge_asf_mode) {
1124 		switch (type) {
1125 		case BGE_RESET_START:
1126 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1127 			break;
1128 		case BGE_RESET_STOP:
1129 			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1130 			break;
1131 		}
1132 	}
1133 }
1134 
1135 void bge_stop_fw(struct bge_softc *);
1136 void
1137 bge_stop_fw(sc)
1138 	struct bge_softc *sc;
1139 {
1140 	int i;
1141 
1142 	if (sc->bge_asf_mode) {
1143 		bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1144 		CSR_WRITE_4(sc, BGE_CPU_EVENT,
1145 		    CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1146 
1147 		for (i = 0; i < 100; i++ ) {
1148 			if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1149 				break;
1150 			DELAY(10);
1151 		}
1152 	}
1153 }
1154 
1155 /*
1156  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1157  * self-test results.
1158  */
1159 static int
1160 bge_chipinit(struct bge_softc *sc)
1161 {
1162 	uint32_t dma_rw_ctl;
1163 	int i;
1164 
1165 	/* Set endianness before we access any non-PCI registers. */
1166 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1167 
1168 	/*
1169 	 * Check the 'ROM failed' bit on the RX CPU to see if
1170 	 * self-tests passed. Skip this check when there's no
1171 	 * EEPROM fitted, since in that case it will always
1172 	 * fail.
1173 	 */
1174 	if ((sc->bge_flags & BGE_FLAG_EEPROM) &&
1175 	    CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1176 		device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
1177 		return (ENODEV);
1178 	}
1179 
1180 	/* Clear the MAC control register */
1181 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1182 
1183 	/*
1184 	 * Clear the MAC statistics block in the NIC's
1185 	 * internal memory.
1186 	 */
1187 	for (i = BGE_STATS_BLOCK;
1188 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1189 		BGE_MEMWIN_WRITE(sc, i, 0);
1190 
1191 	for (i = BGE_STATUS_BLOCK;
1192 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1193 		BGE_MEMWIN_WRITE(sc, i, 0);
1194 
1195 	/*
1196 	 * Set up the PCI DMA control register.
1197 	 */
1198 	dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1199 	    BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1200 	if (sc->bge_flags & BGE_FLAG_PCIE) {
1201 		/* Read watermark not used, 128 bytes for write. */
1202 		dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1203 	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
1204 		if (BGE_IS_5714_FAMILY(sc)) {
1205 			/* 256 bytes for read and write. */
1206 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1207 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1208 			dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1209 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1210 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1211 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1212 			/* 1536 bytes for read, 384 bytes for write. */
1213 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1214 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1215 		} else {
1216 			/* 384 bytes for read and write. */
1217 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1218 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1219 			    0x0F;
1220 		}
1221 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1222 		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1223 			uint32_t tmp;
1224 
1225 			/* Set ONE_DMA_AT_ONCE for hardware workaround. */
1226 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1227 			if (tmp == 6 || tmp == 7)
1228 				dma_rw_ctl |=
1229 				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1230 
1231 			/* Set PCI-X DMA write workaround. */
1232 			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1233 		}
1234 	} else {
1235 		/* Conventional PCI bus: 256 bytes for read and write. */
1236 		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1237 		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1238 
1239 		if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1240 		    sc->bge_asicrev != BGE_ASICREV_BCM5750)
1241 			dma_rw_ctl |= 0x0F;
1242 	}
1243 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1244 	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
1245 		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1246 		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
1247 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1248 	    sc->bge_asicrev == BGE_ASICREV_BCM5704)
1249 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1250 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1251 
1252 	/*
1253 	 * Set up general mode register.
1254 	 */
1255 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1256 	    BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1257 	    BGE_MODECTL_TX_NO_PHDR_CSUM);
1258 
1259 	/*
1260 	 * Tell the firmware the driver is running
1261 	 */
1262 	if (sc->bge_asf_mode & ASF_STACKUP)
1263 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1264 
1265 	/*
1266 	 * Disable memory write invalidate.  Apparently it is not supported
1267 	 * properly by these devices.
1268 	 */
1269 	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1270 
1271 	/* Set the timer prescaler (always 66Mhz) */
1272 	CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1273 
1274 	return (0);
1275 }
1276 
1277 static int
1278 bge_blockinit(struct bge_softc *sc)
1279 {
1280 	struct bge_rcb *rcb;
1281 	bus_size_t vrcb;
1282 	bge_hostaddr taddr;
1283 	uint32_t val;
1284 	int i;
1285 
1286 	/*
1287 	 * Initialize the memory window pointer register so that
1288 	 * we can access the first 32K of internal NIC RAM. This will
1289 	 * allow us to set up the TX send ring RCBs and the RX return
1290 	 * ring RCBs, plus other things which live in NIC memory.
1291 	 */
1292 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1293 
1294 	/* Note: the BCM5704 has a smaller mbuf space than other chips. */
1295 
1296 	if (!(BGE_IS_5705_PLUS(sc))) {
1297 		/* Configure mbuf memory pool */
1298 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1299 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1300 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1301 		else
1302 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1303 
1304 		/* Configure DMA resource pool */
1305 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1306 		    BGE_DMA_DESCRIPTORS);
1307 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1308 	}
1309 
1310 	/* Configure mbuf pool watermarks */
1311 	if (!(BGE_IS_5705_PLUS(sc))) {
1312 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1313 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1314 	} else {
1315 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1316 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1317 	}
1318 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1319 
1320 	/* Configure DMA resource watermarks */
1321 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1322 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1323 
1324 	/* Enable buffer manager */
1325 	if (!(BGE_IS_5705_PLUS(sc))) {
1326 		CSR_WRITE_4(sc, BGE_BMAN_MODE,
1327 		    BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1328 
1329 		/* Poll for buffer manager start indication */
1330 		for (i = 0; i < BGE_TIMEOUT; i++) {
1331 			DELAY(10);
1332 			if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1333 				break;
1334 		}
1335 
1336 		if (i == BGE_TIMEOUT) {
1337 			device_printf(sc->bge_dev,
1338 			    "buffer manager failed to start\n");
1339 			return (ENXIO);
1340 		}
1341 	}
1342 
1343 	/* Enable flow-through queues */
1344 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1345 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1346 
1347 	/* Wait until queue initialization is complete */
1348 	for (i = 0; i < BGE_TIMEOUT; i++) {
1349 		DELAY(10);
1350 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1351 			break;
1352 	}
1353 
1354 	if (i == BGE_TIMEOUT) {
1355 		device_printf(sc->bge_dev, "flow-through queue init failed\n");
1356 		return (ENXIO);
1357 	}
1358 
1359 	/* Initialize the standard RX ring control block */
1360 	rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1361 	rcb->bge_hostaddr.bge_addr_lo =
1362 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1363 	rcb->bge_hostaddr.bge_addr_hi =
1364 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1365 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1366 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1367 	if (BGE_IS_5705_PLUS(sc))
1368 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1369 	else
1370 		rcb->bge_maxlen_flags =
1371 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1372 	rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1373 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1374 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1375 
1376 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1377 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1378 
1379 	/*
1380 	 * Initialize the jumbo RX ring control block
1381 	 * We set the 'ring disabled' bit in the flags
1382 	 * field until we're actually ready to start
1383 	 * using this ring (i.e. once we set the MTU
1384 	 * high enough to require it).
1385 	 */
1386 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
1387 		rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1388 
1389 		rcb->bge_hostaddr.bge_addr_lo =
1390 		    BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1391 		rcb->bge_hostaddr.bge_addr_hi =
1392 		    BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1393 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1394 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
1395 		    BUS_DMASYNC_PREREAD);
1396 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1397 		    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1398 		rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1399 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1400 		    rcb->bge_hostaddr.bge_addr_hi);
1401 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1402 		    rcb->bge_hostaddr.bge_addr_lo);
1403 
1404 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1405 		    rcb->bge_maxlen_flags);
1406 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1407 
1408 		/* Set up dummy disabled mini ring RCB */
1409 		rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1410 		rcb->bge_maxlen_flags =
1411 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1412 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1413 		    rcb->bge_maxlen_flags);
1414 	}
1415 
1416 	/*
1417 	 * Set the BD ring replentish thresholds. The recommended
1418 	 * values are 1/8th the number of descriptors allocated to
1419 	 * each ring.
1420 	 * XXX The 5754 requires a lower threshold, so it might be a
1421 	 * requirement of all 575x family chips.  The Linux driver sets
1422 	 * the lower threshold for all 5705 family chips as well, but there
1423 	 * are reports that it might not need to be so strict.
1424 	 */
1425 	if (BGE_IS_5705_PLUS(sc))
1426 		val = 8;
1427 	else
1428 		val = BGE_STD_RX_RING_CNT / 8;
1429 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1430 	CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1431 
1432 	/*
1433 	 * Disable all unused send rings by setting the 'ring disabled'
1434 	 * bit in the flags field of all the TX send ring control blocks.
1435 	 * These are located in NIC memory.
1436 	 */
1437 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1438 	for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1439 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1440 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1441 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1442 		vrcb += sizeof(struct bge_rcb);
1443 	}
1444 
1445 	/* Configure TX RCB 0 (we use only the first ring) */
1446 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1447 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1448 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1449 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1450 	RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1451 	    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1452 	if (!(BGE_IS_5705_PLUS(sc)))
1453 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1454 		    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1455 
1456 	/* Disable all unused RX return rings */
1457 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1458 	for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1459 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1460 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1461 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1462 		    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1463 		    BGE_RCB_FLAG_RING_DISABLED));
1464 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1465 		CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1466 		    (i * (sizeof(uint64_t))), 0);
1467 		vrcb += sizeof(struct bge_rcb);
1468 	}
1469 
1470 	/* Initialize RX ring indexes */
1471 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1472 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1473 	CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1474 
1475 	/*
1476 	 * Set up RX return ring 0
1477 	 * Note that the NIC address for RX return rings is 0x00000000.
1478 	 * The return rings live entirely within the host, so the
1479 	 * nicaddr field in the RCB isn't used.
1480 	 */
1481 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1482 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1483 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1484 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1485 	RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1486 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1487 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1488 
1489 	/* Set random backoff seed for TX */
1490 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1491 	    IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1492 	    IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1493 	    IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1494 	    BGE_TX_BACKOFF_SEED_MASK);
1495 
1496 	/* Set inter-packet gap */
1497 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1498 
1499 	/*
1500 	 * Specify which ring to use for packets that don't match
1501 	 * any RX rules.
1502 	 */
1503 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1504 
1505 	/*
1506 	 * Configure number of RX lists. One interrupt distribution
1507 	 * list, sixteen active lists, one bad frames class.
1508 	 */
1509 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1510 
1511 	/* Inialize RX list placement stats mask. */
1512 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1513 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1514 
1515 	/* Disable host coalescing until we get it set up */
1516 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1517 
1518 	/* Poll to make sure it's shut down. */
1519 	for (i = 0; i < BGE_TIMEOUT; i++) {
1520 		DELAY(10);
1521 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1522 			break;
1523 	}
1524 
1525 	if (i == BGE_TIMEOUT) {
1526 		device_printf(sc->bge_dev,
1527 		    "host coalescing engine failed to idle\n");
1528 		return (ENXIO);
1529 	}
1530 
1531 	/* Set up host coalescing defaults */
1532 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1533 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1534 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1535 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1536 	if (!(BGE_IS_5705_PLUS(sc))) {
1537 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1538 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1539 	}
1540 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1541 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1542 
1543 	/* Set up address of statistics block */
1544 	if (!(BGE_IS_5705_PLUS(sc))) {
1545 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1546 		    BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1547 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1548 		    BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1549 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1550 		CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1551 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1552 	}
1553 
1554 	/* Set up address of status block */
1555 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1556 	    BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1557 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1558 	    BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1559 	sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1560 	sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1561 
1562 	/* Turn on host coalescing state machine */
1563 	CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1564 
1565 	/* Turn on RX BD completion state machine and enable attentions */
1566 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
1567 	    BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1568 
1569 	/* Turn on RX list placement state machine */
1570 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1571 
1572 	/* Turn on RX list selector state machine. */
1573 	if (!(BGE_IS_5705_PLUS(sc)))
1574 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1575 
1576 	/* Turn on DMA, clear stats */
1577 	CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1578 	    BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1579 	    BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1580 	    BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1581 	    ((sc->bge_flags & BGE_FLAG_TBI) ?
1582 	    BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1583 
1584 	/* Set misc. local control, enable interrupts on attentions */
1585 	CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1586 
1587 #ifdef notdef
1588 	/* Assert GPIO pins for PHY reset */
1589 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1590 	    BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1591 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1592 	    BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1593 #endif
1594 
1595 	/* Turn on DMA completion state machine */
1596 	if (!(BGE_IS_5705_PLUS(sc)))
1597 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1598 
1599 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1600 
1601 	/* Enable host coalescing bug fix. */
1602 	if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1603 	    sc->bge_asicrev == BGE_ASICREV_BCM5787)
1604 			val |= 1 << 29;
1605 
1606 	/* Turn on write DMA state machine */
1607 	CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1608 
1609 	/* Turn on read DMA state machine */
1610 	CSR_WRITE_4(sc, BGE_RDMA_MODE,
1611 	    BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
1612 
1613 	/* Turn on RX data completion state machine */
1614 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1615 
1616 	/* Turn on RX BD initiator state machine */
1617 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1618 
1619 	/* Turn on RX data and RX BD initiator state machine */
1620 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1621 
1622 	/* Turn on Mbuf cluster free state machine */
1623 	if (!(BGE_IS_5705_PLUS(sc)))
1624 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1625 
1626 	/* Turn on send BD completion state machine */
1627 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1628 
1629 	/* Turn on send data completion state machine */
1630 	CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1631 
1632 	/* Turn on send data initiator state machine */
1633 	CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1634 
1635 	/* Turn on send BD initiator state machine */
1636 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1637 
1638 	/* Turn on send BD selector state machine */
1639 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1640 
1641 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1642 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1643 	    BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1644 
1645 	/* ack/clear link change events */
1646 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1647 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1648 	    BGE_MACSTAT_LINK_CHANGED);
1649 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
1650 
1651 	/* Enable PHY auto polling (for MII/GMII only) */
1652 	if (sc->bge_flags & BGE_FLAG_TBI) {
1653 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1654 	} else {
1655 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1656 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1657 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1658 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1659 			    BGE_EVTENB_MI_INTERRUPT);
1660 	}
1661 
1662 	/*
1663 	 * Clear any pending link state attention.
1664 	 * Otherwise some link state change events may be lost until attention
1665 	 * is cleared by bge_intr() -> bge_link_upd() sequence.
1666 	 * It's not necessary on newer BCM chips - perhaps enabling link
1667 	 * state change attentions implies clearing pending attention.
1668 	 */
1669 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1670 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1671 	    BGE_MACSTAT_LINK_CHANGED);
1672 
1673 	/* Enable link state change attentions. */
1674 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1675 
1676 	return (0);
1677 }
1678 
1679 const struct bge_revision *
1680 bge_lookup_rev(uint32_t chipid)
1681 {
1682 	const struct bge_revision *br;
1683 
1684 	for (br = bge_revisions; br->br_name != NULL; br++) {
1685 		if (br->br_chipid == chipid)
1686 			return (br);
1687 	}
1688 
1689 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
1690 		if (br->br_chipid == BGE_ASICREV(chipid))
1691 			return (br);
1692 	}
1693 
1694 	return (NULL);
1695 }
1696 
1697 const struct bge_vendor *
1698 bge_lookup_vendor(uint16_t vid)
1699 {
1700 	const struct bge_vendor *v;
1701 
1702 	for (v = bge_vendors; v->v_name != NULL; v++)
1703 		if (v->v_id == vid)
1704 			return (v);
1705 
1706 	panic("%s: unknown vendor %d", __func__, vid);
1707 	return (NULL);
1708 }
1709 
1710 /*
1711  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1712  * against our list and return its name if we find a match.
1713  *
1714  * Note that since the Broadcom controller contains VPD support, we
1715  * try to get the device name string from the controller itself instead
1716  * of the compiled-in string. It guarantees we'll always announce the
1717  * right product name. We fall back to the compiled-in string when
1718  * VPD is unavailable or corrupt.
1719  */
1720 static int
1721 bge_probe(device_t dev)
1722 {
1723 	struct bge_type *t = bge_devs;
1724 	struct bge_softc *sc = device_get_softc(dev);
1725 	uint16_t vid, did;
1726 
1727 	sc->bge_dev = dev;
1728 	vid = pci_get_vendor(dev);
1729 	did = pci_get_device(dev);
1730 	while(t->bge_vid != 0) {
1731 		if ((vid == t->bge_vid) && (did == t->bge_did)) {
1732 			char model[64], buf[96];
1733 			const struct bge_revision *br;
1734 			const struct bge_vendor *v;
1735 			uint32_t id;
1736 
1737 			id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1738 			    BGE_PCIMISCCTL_ASICREV;
1739 			br = bge_lookup_rev(id);
1740 			v = bge_lookup_vendor(vid);
1741 			{
1742 #if __FreeBSD_version > 700024
1743 				const char *pname;
1744 
1745 				if (pci_get_vpd_ident(dev, &pname) == 0)
1746 					snprintf(model, 64, "%s", pname);
1747 				else
1748 #endif
1749 					snprintf(model, 64, "%s %s",
1750 					    v->v_name,
1751 					    br != NULL ? br->br_name :
1752 					    "NetXtreme Ethernet Controller");
1753 			}
1754 			snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
1755 			    br != NULL ? "" : "unknown ", id >> 16);
1756 			device_set_desc_copy(dev, buf);
1757 			if (pci_get_subvendor(dev) == DELL_VENDORID)
1758 				sc->bge_flags |= BGE_FLAG_NO_3LED;
1759 			if (did == BCOM_DEVICEID_BCM5755M)
1760 				sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1761 			return (0);
1762 		}
1763 		t++;
1764 	}
1765 
1766 	return (ENXIO);
1767 }
1768 
1769 static void
1770 bge_dma_free(struct bge_softc *sc)
1771 {
1772 	int i;
1773 
1774 	/* Destroy DMA maps for RX buffers. */
1775 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1776 		if (sc->bge_cdata.bge_rx_std_dmamap[i])
1777 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1778 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
1779 	}
1780 
1781 	/* Destroy DMA maps for jumbo RX buffers. */
1782 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1783 		if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1784 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1785 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1786 	}
1787 
1788 	/* Destroy DMA maps for TX buffers. */
1789 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1790 		if (sc->bge_cdata.bge_tx_dmamap[i])
1791 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1792 			    sc->bge_cdata.bge_tx_dmamap[i]);
1793 	}
1794 
1795 	if (sc->bge_cdata.bge_mtag)
1796 		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1797 
1798 
1799 	/* Destroy standard RX ring. */
1800 	if (sc->bge_cdata.bge_rx_std_ring_map)
1801 		bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1802 		    sc->bge_cdata.bge_rx_std_ring_map);
1803 	if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
1804 		bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1805 		    sc->bge_ldata.bge_rx_std_ring,
1806 		    sc->bge_cdata.bge_rx_std_ring_map);
1807 
1808 	if (sc->bge_cdata.bge_rx_std_ring_tag)
1809 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1810 
1811 	/* Destroy jumbo RX ring. */
1812 	if (sc->bge_cdata.bge_rx_jumbo_ring_map)
1813 		bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1814 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
1815 
1816 	if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
1817 	    sc->bge_ldata.bge_rx_jumbo_ring)
1818 		bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1819 		    sc->bge_ldata.bge_rx_jumbo_ring,
1820 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
1821 
1822 	if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1823 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1824 
1825 	/* Destroy RX return ring. */
1826 	if (sc->bge_cdata.bge_rx_return_ring_map)
1827 		bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1828 		    sc->bge_cdata.bge_rx_return_ring_map);
1829 
1830 	if (sc->bge_cdata.bge_rx_return_ring_map &&
1831 	    sc->bge_ldata.bge_rx_return_ring)
1832 		bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1833 		    sc->bge_ldata.bge_rx_return_ring,
1834 		    sc->bge_cdata.bge_rx_return_ring_map);
1835 
1836 	if (sc->bge_cdata.bge_rx_return_ring_tag)
1837 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1838 
1839 	/* Destroy TX ring. */
1840 	if (sc->bge_cdata.bge_tx_ring_map)
1841 		bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1842 		    sc->bge_cdata.bge_tx_ring_map);
1843 
1844 	if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
1845 		bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1846 		    sc->bge_ldata.bge_tx_ring,
1847 		    sc->bge_cdata.bge_tx_ring_map);
1848 
1849 	if (sc->bge_cdata.bge_tx_ring_tag)
1850 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1851 
1852 	/* Destroy status block. */
1853 	if (sc->bge_cdata.bge_status_map)
1854 		bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1855 		    sc->bge_cdata.bge_status_map);
1856 
1857 	if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
1858 		bus_dmamem_free(sc->bge_cdata.bge_status_tag,
1859 		    sc->bge_ldata.bge_status_block,
1860 		    sc->bge_cdata.bge_status_map);
1861 
1862 	if (sc->bge_cdata.bge_status_tag)
1863 		bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
1864 
1865 	/* Destroy statistics block. */
1866 	if (sc->bge_cdata.bge_stats_map)
1867 		bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
1868 		    sc->bge_cdata.bge_stats_map);
1869 
1870 	if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
1871 		bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
1872 		    sc->bge_ldata.bge_stats,
1873 		    sc->bge_cdata.bge_stats_map);
1874 
1875 	if (sc->bge_cdata.bge_stats_tag)
1876 		bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
1877 
1878 	/* Destroy the parent tag. */
1879 	if (sc->bge_cdata.bge_parent_tag)
1880 		bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
1881 }
1882 
1883 static int
1884 bge_dma_alloc(device_t dev)
1885 {
1886 	struct bge_dmamap_arg ctx;
1887 	struct bge_softc *sc;
1888 	int i, error;
1889 
1890 	sc = device_get_softc(dev);
1891 
1892 	/*
1893 	 * Allocate the parent bus DMA tag appropriate for PCI.
1894 	 */
1895 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */
1896 			1, 0,			/* alignment, boundary */
1897 			BUS_SPACE_MAXADDR,	/* lowaddr */
1898 			BUS_SPACE_MAXADDR,	/* highaddr */
1899 			NULL, NULL,		/* filter, filterarg */
1900 			MAXBSIZE, BGE_NSEG_NEW,	/* maxsize, nsegments */
1901 			BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1902 			0,			/* flags */
1903 			NULL, NULL,		/* lockfunc, lockarg */
1904 			&sc->bge_cdata.bge_parent_tag);
1905 
1906 	if (error != 0) {
1907 		device_printf(sc->bge_dev,
1908 		    "could not allocate parent dma tag\n");
1909 		return (ENOMEM);
1910 	}
1911 
1912 	/*
1913 	 * Create tag for RX mbufs.
1914 	 */
1915 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
1916 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1917 	    NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
1918 	    BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
1919 
1920 	if (error) {
1921 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
1922 		return (ENOMEM);
1923 	}
1924 
1925 	/* Create DMA maps for RX buffers. */
1926 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1927 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1928 			    &sc->bge_cdata.bge_rx_std_dmamap[i]);
1929 		if (error) {
1930 			device_printf(sc->bge_dev,
1931 			    "can't create DMA map for RX\n");
1932 			return (ENOMEM);
1933 		}
1934 	}
1935 
1936 	/* Create DMA maps for TX buffers. */
1937 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1938 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1939 			    &sc->bge_cdata.bge_tx_dmamap[i]);
1940 		if (error) {
1941 			device_printf(sc->bge_dev,
1942 			    "can't create DMA map for RX\n");
1943 			return (ENOMEM);
1944 		}
1945 	}
1946 
1947 	/* Create tag for standard RX ring. */
1948 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1949 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1950 	    NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
1951 	    NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
1952 
1953 	if (error) {
1954 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
1955 		return (ENOMEM);
1956 	}
1957 
1958 	/* Allocate DMA'able memory for standard RX ring. */
1959 	error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
1960 	    (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
1961 	    &sc->bge_cdata.bge_rx_std_ring_map);
1962 	if (error)
1963 		return (ENOMEM);
1964 
1965 	bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1966 
1967 	/* Load the address of the standard RX ring. */
1968 	ctx.bge_maxsegs = 1;
1969 	ctx.sc = sc;
1970 
1971 	error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
1972 	    sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
1973 	    BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
1974 
1975 	if (error)
1976 		return (ENOMEM);
1977 
1978 	sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
1979 
1980 	/* Create tags for jumbo mbufs. */
1981 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
1982 		error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1983 		    1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1984 		    NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
1985 		    0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
1986 		if (error) {
1987 			device_printf(sc->bge_dev,
1988 			    "could not allocate jumbo dma tag\n");
1989 			return (ENOMEM);
1990 		}
1991 
1992 		/* Create tag for jumbo RX ring. */
1993 		error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1994 		    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1995 		    NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
1996 		    NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
1997 
1998 		if (error) {
1999 			device_printf(sc->bge_dev,
2000 			    "could not allocate jumbo ring dma tag\n");
2001 			return (ENOMEM);
2002 		}
2003 
2004 		/* Allocate DMA'able memory for jumbo RX ring. */
2005 		error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2006 		    (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2007 		    BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2008 		    &sc->bge_cdata.bge_rx_jumbo_ring_map);
2009 		if (error)
2010 			return (ENOMEM);
2011 
2012 		/* Load the address of the jumbo RX ring. */
2013 		ctx.bge_maxsegs = 1;
2014 		ctx.sc = sc;
2015 
2016 		error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2017 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2018 		    sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2019 		    bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2020 
2021 		if (error)
2022 			return (ENOMEM);
2023 
2024 		sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2025 
2026 		/* Create DMA maps for jumbo RX buffers. */
2027 		for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2028 			error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2029 				    0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2030 			if (error) {
2031 				device_printf(sc->bge_dev,
2032 				    "can't create DMA map for jumbo RX\n");
2033 				return (ENOMEM);
2034 			}
2035 		}
2036 
2037 	}
2038 
2039 	/* Create tag for RX return ring. */
2040 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2041 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2042 	    NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2043 	    NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2044 
2045 	if (error) {
2046 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
2047 		return (ENOMEM);
2048 	}
2049 
2050 	/* Allocate DMA'able memory for RX return ring. */
2051 	error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2052 	    (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2053 	    &sc->bge_cdata.bge_rx_return_ring_map);
2054 	if (error)
2055 		return (ENOMEM);
2056 
2057 	bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2058 	    BGE_RX_RTN_RING_SZ(sc));
2059 
2060 	/* Load the address of the RX return ring. */
2061 	ctx.bge_maxsegs = 1;
2062 	ctx.sc = sc;
2063 
2064 	error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2065 	    sc->bge_cdata.bge_rx_return_ring_map,
2066 	    sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2067 	    bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2068 
2069 	if (error)
2070 		return (ENOMEM);
2071 
2072 	sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2073 
2074 	/* Create tag for TX ring. */
2075 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2076 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2077 	    NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2078 	    &sc->bge_cdata.bge_tx_ring_tag);
2079 
2080 	if (error) {
2081 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
2082 		return (ENOMEM);
2083 	}
2084 
2085 	/* Allocate DMA'able memory for TX ring. */
2086 	error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2087 	    (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2088 	    &sc->bge_cdata.bge_tx_ring_map);
2089 	if (error)
2090 		return (ENOMEM);
2091 
2092 	bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2093 
2094 	/* Load the address of the TX ring. */
2095 	ctx.bge_maxsegs = 1;
2096 	ctx.sc = sc;
2097 
2098 	error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2099 	    sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2100 	    BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2101 
2102 	if (error)
2103 		return (ENOMEM);
2104 
2105 	sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2106 
2107 	/* Create tag for status block. */
2108 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2109 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2110 	    NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2111 	    NULL, NULL, &sc->bge_cdata.bge_status_tag);
2112 
2113 	if (error) {
2114 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
2115 		return (ENOMEM);
2116 	}
2117 
2118 	/* Allocate DMA'able memory for status block. */
2119 	error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2120 	    (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2121 	    &sc->bge_cdata.bge_status_map);
2122 	if (error)
2123 		return (ENOMEM);
2124 
2125 	bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2126 
2127 	/* Load the address of the status block. */
2128 	ctx.sc = sc;
2129 	ctx.bge_maxsegs = 1;
2130 
2131 	error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2132 	    sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2133 	    BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2134 
2135 	if (error)
2136 		return (ENOMEM);
2137 
2138 	sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2139 
2140 	/* Create tag for statistics block. */
2141 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2142 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2143 	    NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2144 	    &sc->bge_cdata.bge_stats_tag);
2145 
2146 	if (error) {
2147 		device_printf(sc->bge_dev, "could not allocate dma tag\n");
2148 		return (ENOMEM);
2149 	}
2150 
2151 	/* Allocate DMA'able memory for statistics block. */
2152 	error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2153 	    (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2154 	    &sc->bge_cdata.bge_stats_map);
2155 	if (error)
2156 		return (ENOMEM);
2157 
2158 	bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2159 
2160 	/* Load the address of the statstics block. */
2161 	ctx.sc = sc;
2162 	ctx.bge_maxsegs = 1;
2163 
2164 	error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2165 	    sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2166 	    BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2167 
2168 	if (error)
2169 		return (ENOMEM);
2170 
2171 	sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2172 
2173 	return (0);
2174 }
2175 
2176 #if __FreeBSD_version > 602105
2177 /*
2178  * Return true if this device has more than one port.
2179  */
2180 static int
2181 bge_has_multiple_ports(struct bge_softc *sc)
2182 {
2183 	device_t dev = sc->bge_dev;
2184 	u_int b, s, f, fscan;
2185 
2186 	b = pci_get_bus(dev);
2187 	s = pci_get_slot(dev);
2188 	f = pci_get_function(dev);
2189 	for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2190 		if (fscan != f && pci_find_bsf(b, s, fscan) != NULL)
2191 			return (1);
2192 	return (0);
2193 }
2194 
2195 /*
2196  * Return true if MSI can be used with this device.
2197  */
2198 static int
2199 bge_can_use_msi(struct bge_softc *sc)
2200 {
2201 	int can_use_msi = 0;
2202 
2203 	switch (sc->bge_asicrev) {
2204 	case BGE_ASICREV_BCM5714:
2205 		/*
2206 		 * Apparently, MSI doesn't work when this chip is configured
2207 		 * in single-port mode.
2208 		 */
2209 		if (bge_has_multiple_ports(sc))
2210 			can_use_msi = 1;
2211 		break;
2212 	case BGE_ASICREV_BCM5750:
2213 		if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2214 		    sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2215 			can_use_msi = 1;
2216 		break;
2217 	case BGE_ASICREV_BCM5752:
2218 	case BGE_ASICREV_BCM5780:
2219 		can_use_msi = 1;
2220 		break;
2221 	}
2222 	return (can_use_msi);
2223 }
2224 #endif
2225 
2226 static int
2227 bge_attach(device_t dev)
2228 {
2229 	struct ifnet *ifp;
2230 	struct bge_softc *sc;
2231 	uint32_t hwcfg = 0;
2232 	uint32_t mac_tmp = 0;
2233 	u_char eaddr[ETHER_ADDR_LEN];
2234 	int error, reg, rid, trys;
2235 
2236 	sc = device_get_softc(dev);
2237 	sc->bge_dev = dev;
2238 
2239 	/*
2240 	 * Map control/status registers.
2241 	 */
2242 	pci_enable_busmaster(dev);
2243 
2244 	rid = BGE_PCI_BAR0;
2245 	sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2246 	    RF_ACTIVE | PCI_RF_DENSE);
2247 
2248 	if (sc->bge_res == NULL) {
2249 		device_printf (sc->bge_dev, "couldn't map memory\n");
2250 		error = ENXIO;
2251 		goto fail;
2252 	}
2253 
2254 	sc->bge_btag = rman_get_bustag(sc->bge_res);
2255 	sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2256 
2257 	/* Save ASIC rev. */
2258 
2259 	sc->bge_chipid =
2260 	    pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2261 	    BGE_PCIMISCCTL_ASICREV;
2262 	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2263 	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2264 
2265 	if (bge_has_eeprom(sc))
2266 		sc->bge_flags |= BGE_FLAG_EEPROM;
2267 
2268 	/* Save chipset family. */
2269 	switch (sc->bge_asicrev) {
2270 	case BGE_ASICREV_BCM5700:
2271 	case BGE_ASICREV_BCM5701:
2272 	case BGE_ASICREV_BCM5703:
2273 	case BGE_ASICREV_BCM5704:
2274 		sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2275 		break;
2276 	case BGE_ASICREV_BCM5714_A0:
2277 	case BGE_ASICREV_BCM5780:
2278 	case BGE_ASICREV_BCM5714:
2279 		sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2280 		/* FALLTHRU */
2281 	case BGE_ASICREV_BCM5750:
2282 	case BGE_ASICREV_BCM5752:
2283 	case BGE_ASICREV_BCM5755:
2284 	case BGE_ASICREV_BCM5787:
2285 		sc->bge_flags |= BGE_FLAG_575X_PLUS;
2286 		/* FALLTHRU */
2287 	case BGE_ASICREV_BCM5705:
2288 		sc->bge_flags |= BGE_FLAG_5705_PLUS;
2289 		break;
2290 	}
2291 
2292 	/* Set various bug flags. */
2293 	if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2294 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2295 		sc->bge_flags |= BGE_FLAG_CRC_BUG;
2296 	if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2297 	    sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2298 		sc->bge_flags |= BGE_FLAG_ADC_BUG;
2299 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2300 		sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2301 	if (BGE_IS_5705_PLUS(sc) &&
2302 	    !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2303 		if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2304 		    sc->bge_asicrev == BGE_ASICREV_BCM5787)
2305 			sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2306 		else
2307 			sc->bge_flags |= BGE_FLAG_BER_BUG;
2308 	}
2309 
2310   	/*
2311 	 * Check if this is a PCI-X or PCI Express device.
2312   	 */
2313 #if __FreeBSD_version > 602101
2314 	if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2315 		/*
2316 		 * Found a PCI Express capabilities register, this
2317 		 * must be a PCI Express device.
2318 		 */
2319 		if (reg != 0)
2320 			sc->bge_flags |= BGE_FLAG_PCIE;
2321 	} else if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
2322 		if (reg != 0)
2323 			sc->bge_flags |= BGE_FLAG_PCIX;
2324 	}
2325 
2326 #else
2327 	if (BGE_IS_5705_PLUS(sc)) {
2328 		reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2329 		if ((reg & 0xFF) == BGE_PCIE_CAPID)
2330 			sc->bge_flags |= BGE_FLAG_PCIE;
2331 	} else {
2332 		/*
2333 		 * Check if the device is in PCI-X Mode.
2334 		 * (This bit is not valid on PCI Express controllers.)
2335 		 */
2336 		if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2337 		    BGE_PCISTATE_PCI_BUSMODE) == 0)
2338 			sc->bge_flags |= BGE_FLAG_PCIX;
2339 	}
2340 #endif
2341 
2342 #if __FreeBSD_version > 602105
2343 	{
2344 		int msicount;
2345 
2346 		/*
2347 		 * Allocate the interrupt, using MSI if possible.  These devices
2348 		 * support 8 MSI messages, but only the first one is used in
2349 		 * normal operation.
2350 		 */
2351 		if (bge_can_use_msi(sc)) {
2352 			msicount = pci_msi_count(dev);
2353 			if (msicount > 1)
2354 				msicount = 1;
2355 		} else
2356 			msicount = 0;
2357 		if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2358 			rid = 1;
2359 			sc->bge_flags |= BGE_FLAG_MSI;
2360 		} else
2361 			rid = 0;
2362 	}
2363 #else
2364 	rid = 0;
2365 #endif
2366 
2367 	sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2368 	    RF_SHAREABLE | RF_ACTIVE);
2369 
2370 	if (sc->bge_irq == NULL) {
2371 		device_printf(sc->bge_dev, "couldn't map interrupt\n");
2372 		error = ENXIO;
2373 		goto fail;
2374 	}
2375 
2376 	BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2377 
2378 	/* Try to reset the chip. */
2379 	if (bge_reset(sc)) {
2380 		device_printf(sc->bge_dev, "chip reset failed\n");
2381 		error = ENXIO;
2382 		goto fail;
2383 	}
2384 
2385 	sc->bge_asf_mode = 0;
2386 	if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2387 	    == BGE_MAGIC_NUMBER)) {
2388 		if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2389 		    & BGE_HWCFG_ASF) {
2390 			sc->bge_asf_mode |= ASF_ENABLE;
2391 			sc->bge_asf_mode |= ASF_STACKUP;
2392 			if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2393 				sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2394 			}
2395 		}
2396 	}
2397 
2398 	/* Try to reset the chip again the nice way. */
2399 	bge_stop_fw(sc);
2400 	bge_sig_pre_reset(sc, BGE_RESET_STOP);
2401 	if (bge_reset(sc)) {
2402 		device_printf(sc->bge_dev, "chip reset failed\n");
2403 		error = ENXIO;
2404 		goto fail;
2405 	}
2406 
2407 	bge_sig_legacy(sc, BGE_RESET_STOP);
2408 	bge_sig_post_reset(sc, BGE_RESET_STOP);
2409 
2410 	if (bge_chipinit(sc)) {
2411 		device_printf(sc->bge_dev, "chip initialization failed\n");
2412 		error = ENXIO;
2413 		goto fail;
2414 	}
2415 
2416 #ifdef __sparc64__
2417 	if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0)
2418 		OF_getetheraddr(dev, eaddr);
2419 	else
2420 #endif
2421 	{
2422 		mac_tmp = bge_readmem_ind(sc, 0x0C14);
2423 		if ((mac_tmp >> 16) == 0x484B) {
2424 			eaddr[0] = (u_char)(mac_tmp >> 8);
2425 			eaddr[1] = (u_char)mac_tmp;
2426 			mac_tmp = bge_readmem_ind(sc, 0x0C18);
2427 			eaddr[2] = (u_char)(mac_tmp >> 24);
2428 			eaddr[3] = (u_char)(mac_tmp >> 16);
2429 			eaddr[4] = (u_char)(mac_tmp >> 8);
2430 			eaddr[5] = (u_char)mac_tmp;
2431 		} else if (bge_read_eeprom(sc, eaddr,
2432 		    BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2433 			device_printf(sc->bge_dev,
2434 			    "failed to read station address\n");
2435 			error = ENXIO;
2436 			goto fail;
2437 		}
2438 	}
2439 
2440 	/* 5705 limits RX return ring to 512 entries. */
2441 	if (BGE_IS_5705_PLUS(sc))
2442 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2443 	else
2444 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2445 
2446 	if (bge_dma_alloc(dev)) {
2447 		device_printf(sc->bge_dev,
2448 		    "failed to allocate DMA resources\n");
2449 		error = ENXIO;
2450 		goto fail;
2451 	}
2452 
2453 	/* Set default tuneable values. */
2454 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2455 	sc->bge_rx_coal_ticks = 150;
2456 	sc->bge_tx_coal_ticks = 150;
2457 	sc->bge_rx_max_coal_bds = 10;
2458 	sc->bge_tx_max_coal_bds = 10;
2459 
2460 	/* Set up ifnet structure */
2461 	ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2462 	if (ifp == NULL) {
2463 		device_printf(sc->bge_dev, "failed to if_alloc()\n");
2464 		error = ENXIO;
2465 		goto fail;
2466 	}
2467 	ifp->if_softc = sc;
2468 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2469 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2470 	ifp->if_ioctl = bge_ioctl;
2471 	ifp->if_start = bge_start;
2472 	ifp->if_init = bge_init;
2473 	ifp->if_mtu = ETHERMTU;
2474 	ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2475 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2476 	IFQ_SET_READY(&ifp->if_snd);
2477 	ifp->if_hwassist = BGE_CSUM_FEATURES;
2478 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2479 	    IFCAP_VLAN_MTU;
2480 #ifdef IFCAP_VLAN_HWCSUM
2481 	ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2482 #endif
2483 	ifp->if_capenable = ifp->if_capabilities;
2484 #ifdef DEVICE_POLLING
2485 	ifp->if_capabilities |= IFCAP_POLLING;
2486 #endif
2487 
2488 	/*
2489 	 * 5700 B0 chips do not support checksumming correctly due
2490 	 * to hardware bugs.
2491 	 */
2492 	if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2493 		ifp->if_capabilities &= ~IFCAP_HWCSUM;
2494 		ifp->if_capenable &= IFCAP_HWCSUM;
2495 		ifp->if_hwassist = 0;
2496 	}
2497 
2498 	/*
2499 	 * Figure out what sort of media we have by checking the
2500 	 * hardware config word in the first 32k of NIC internal memory,
2501 	 * or fall back to examining the EEPROM if necessary.
2502 	 * Note: on some BCM5700 cards, this value appears to be unset.
2503 	 * If that's the case, we have to rely on identifying the NIC
2504 	 * by its PCI subsystem ID, as we do below for the SysKonnect
2505 	 * SK-9D41.
2506 	 */
2507 	if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2508 		hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2509 	else if (sc->bge_flags & BGE_FLAG_EEPROM) {
2510 		if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2511 		    sizeof(hwcfg))) {
2512 			device_printf(sc->bge_dev, "failed to read EEPROM\n");
2513 			error = ENXIO;
2514 			goto fail;
2515 		}
2516 		hwcfg = ntohl(hwcfg);
2517 	}
2518 
2519 	if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2520 		sc->bge_flags |= BGE_FLAG_TBI;
2521 
2522 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
2523 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2524 		sc->bge_flags |= BGE_FLAG_TBI;
2525 
2526 	if (sc->bge_flags & BGE_FLAG_TBI) {
2527 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2528 		    bge_ifmedia_sts);
2529 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2530 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2531 		    0, NULL);
2532 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2533 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2534 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2535 	} else {
2536 		/*
2537 		 * Do transceiver setup and tell the firmware the
2538 		 * driver is down so we can try to get access the
2539 		 * probe if ASF is running.  Retry a couple of times
2540 		 * if we get a conflict with the ASF firmware accessing
2541 		 * the PHY.
2542 		 */
2543 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2544 again:
2545 		bge_asf_driver_up(sc);
2546 
2547 		trys = 0;
2548 		if (mii_phy_probe(dev, &sc->bge_miibus,
2549 		    bge_ifmedia_upd, bge_ifmedia_sts)) {
2550 			if (trys++ < 4) {
2551 				device_printf(sc->bge_dev, "Try again\n");
2552 				bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2553 				    BMCR_RESET);
2554 				goto again;
2555 			}
2556 
2557 			device_printf(sc->bge_dev, "MII without any PHY!\n");
2558 			error = ENXIO;
2559 			goto fail;
2560 		}
2561 
2562 		/*
2563 		 * Now tell the firmware we are going up after probing the PHY
2564 		 */
2565 		if (sc->bge_asf_mode & ASF_STACKUP)
2566 			BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2567 	}
2568 
2569 	/*
2570 	 * When using the BCM5701 in PCI-X mode, data corruption has
2571 	 * been observed in the first few bytes of some received packets.
2572 	 * Aligning the packet buffer in memory eliminates the corruption.
2573 	 * Unfortunately, this misaligns the packet payloads.  On platforms
2574 	 * which do not support unaligned accesses, we will realign the
2575 	 * payloads by copying the received packets.
2576 	 */
2577 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2578 	    sc->bge_flags & BGE_FLAG_PCIX)
2579                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2580 
2581 	/*
2582 	 * Call MI attach routine.
2583 	 */
2584 	ether_ifattach(ifp, eaddr);
2585 	callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2586 
2587 	/*
2588 	 * Hookup IRQ last.
2589 	 */
2590 #if __FreeBSD_version > 700030
2591 	error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2592 	   NULL, bge_intr, sc, &sc->bge_intrhand);
2593 #else
2594 	error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2595 	   bge_intr, sc, &sc->bge_intrhand);
2596 #endif
2597 
2598 	if (error) {
2599 		bge_detach(dev);
2600 		device_printf(sc->bge_dev, "couldn't set up irq\n");
2601 	}
2602 
2603 	bge_add_sysctls(sc);
2604 
2605 	return (0);
2606 
2607 fail:
2608 	bge_release_resources(sc);
2609 
2610 	return (error);
2611 }
2612 
2613 static int
2614 bge_detach(device_t dev)
2615 {
2616 	struct bge_softc *sc;
2617 	struct ifnet *ifp;
2618 
2619 	sc = device_get_softc(dev);
2620 	ifp = sc->bge_ifp;
2621 
2622 #ifdef DEVICE_POLLING
2623 	if (ifp->if_capenable & IFCAP_POLLING)
2624 		ether_poll_deregister(ifp);
2625 #endif
2626 
2627 	BGE_LOCK(sc);
2628 	bge_stop(sc);
2629 	bge_reset(sc);
2630 	BGE_UNLOCK(sc);
2631 
2632 	callout_drain(&sc->bge_stat_ch);
2633 
2634 	ether_ifdetach(ifp);
2635 
2636 	if (sc->bge_flags & BGE_FLAG_TBI) {
2637 		ifmedia_removeall(&sc->bge_ifmedia);
2638 	} else {
2639 		bus_generic_detach(dev);
2640 		device_delete_child(dev, sc->bge_miibus);
2641 	}
2642 
2643 	bge_release_resources(sc);
2644 
2645 	return (0);
2646 }
2647 
2648 static void
2649 bge_release_resources(struct bge_softc *sc)
2650 {
2651 	device_t dev;
2652 
2653 	dev = sc->bge_dev;
2654 
2655 	if (sc->bge_intrhand != NULL)
2656 		bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2657 
2658 	if (sc->bge_irq != NULL)
2659 		bus_release_resource(dev, SYS_RES_IRQ,
2660 		    sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2661 
2662 #if __FreeBSD_version > 602105
2663 	if (sc->bge_flags & BGE_FLAG_MSI)
2664 		pci_release_msi(dev);
2665 #endif
2666 
2667 	if (sc->bge_res != NULL)
2668 		bus_release_resource(dev, SYS_RES_MEMORY,
2669 		    BGE_PCI_BAR0, sc->bge_res);
2670 
2671 	if (sc->bge_ifp != NULL)
2672 		if_free(sc->bge_ifp);
2673 
2674 	bge_dma_free(sc);
2675 
2676 	if (mtx_initialized(&sc->bge_mtx))	/* XXX */
2677 		BGE_LOCK_DESTROY(sc);
2678 }
2679 
2680 static int
2681 bge_reset(struct bge_softc *sc)
2682 {
2683 	device_t dev;
2684 	uint32_t cachesize, command, pcistate, reset;
2685 	void (*write_op)(struct bge_softc *, int, int);
2686 	int i, val = 0;
2687 
2688 	dev = sc->bge_dev;
2689 
2690 	if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2691 		if (sc->bge_flags & BGE_FLAG_PCIE)
2692 			write_op = bge_writemem_direct;
2693 		else
2694 			write_op = bge_writemem_ind;
2695 	} else
2696 		write_op = bge_writereg_ind;
2697 
2698 	/* Save some important PCI state. */
2699 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2700 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
2701 	pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2702 
2703 	pci_write_config(dev, BGE_PCI_MISC_CTL,
2704 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2705 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2706 
2707 	/* Disable fastboot on controllers that support it. */
2708 	if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2709 	    sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2710 	    sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2711 		if (bootverbose)
2712 			device_printf(sc->bge_dev, "Disabling fastboot\n");
2713 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2714 	}
2715 
2716 	/*
2717 	 * Write the magic number to SRAM at offset 0xB50.
2718 	 * When firmware finishes its initialization it will
2719 	 * write ~BGE_MAGIC_NUMBER to the same location.
2720 	 */
2721 	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2722 
2723 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2724 
2725 	/* XXX: Broadcom Linux driver. */
2726 	if (sc->bge_flags & BGE_FLAG_PCIE) {
2727 		if (CSR_READ_4(sc, 0x7E2C) == 0x60)	/* PCIE 1.0 */
2728 			CSR_WRITE_4(sc, 0x7E2C, 0x20);
2729 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2730 			/* Prevent PCIE link training during global reset */
2731 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2732 			reset |= 1 << 29;
2733 		}
2734 	}
2735 
2736 	/*
2737 	 * Set GPHY Power Down Override to leave GPHY
2738 	 * powered up in D0 uninitialized.
2739 	 */
2740 	if (BGE_IS_5705_PLUS(sc))
2741 		reset |= 0x04000000;
2742 
2743 	/* Issue global reset */
2744 	write_op(sc, BGE_MISC_CFG, reset);
2745 
2746 	DELAY(1000);
2747 
2748 	/* XXX: Broadcom Linux driver. */
2749 	if (sc->bge_flags & BGE_FLAG_PCIE) {
2750 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2751 			uint32_t v;
2752 
2753 			DELAY(500000); /* wait for link training to complete */
2754 			v = pci_read_config(dev, 0xC4, 4);
2755 			pci_write_config(dev, 0xC4, v | (1 << 15), 4);
2756 		}
2757 		/*
2758 		 * Set PCIE max payload size to 128 bytes and clear error
2759 		 * status.
2760 		 */
2761 		pci_write_config(dev, 0xD8, 0xF5000, 4);
2762 	}
2763 
2764 	/* Reset some of the PCI state that got zapped by reset. */
2765 	pci_write_config(dev, BGE_PCI_MISC_CTL,
2766 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2767 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2768 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2769 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
2770 	write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2771 
2772 	/* Re-enable MSI, if neccesary, and enable the memory arbiter. */
2773 	if (BGE_IS_5714_FAMILY(sc)) {
2774 		uint32_t val;
2775 
2776 		/* This chip disables MSI on reset. */
2777 		if (sc->bge_flags & BGE_FLAG_MSI) {
2778 			val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
2779 			pci_write_config(dev, BGE_PCI_MSI_CTL,
2780 			    val | PCIM_MSICTRL_MSI_ENABLE, 2);
2781 			val = CSR_READ_4(sc, BGE_MSI_MODE);
2782 			CSR_WRITE_4(sc, BGE_MSI_MODE,
2783 			    val | BGE_MSIMODE_ENABLE);
2784 		}
2785 		val = CSR_READ_4(sc, BGE_MARB_MODE);
2786 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2787 	} else
2788 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2789 
2790 	/*
2791 	 * Poll until we see the 1's complement of the magic number.
2792 	 * This indicates that the firmware initialization is complete.
2793 	 * We expect this to fail if no EEPROM is fitted though.
2794 	 */
2795 	for (i = 0; i < BGE_TIMEOUT; i++) {
2796 		DELAY(10);
2797 		val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2798 		if (val == ~BGE_MAGIC_NUMBER)
2799 			break;
2800 	}
2801 
2802 	if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT)
2803 		device_printf(sc->bge_dev, "firmware handshake timed out, "
2804 		    "found 0x%08x\n", val);
2805 
2806 	/*
2807 	 * XXX Wait for the value of the PCISTATE register to
2808 	 * return to its original pre-reset state. This is a
2809 	 * fairly good indicator of reset completion. If we don't
2810 	 * wait for the reset to fully complete, trying to read
2811 	 * from the device's non-PCI registers may yield garbage
2812 	 * results.
2813 	 */
2814 	for (i = 0; i < BGE_TIMEOUT; i++) {
2815 		if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2816 			break;
2817 		DELAY(10);
2818 	}
2819 
2820 	if (sc->bge_flags & BGE_FLAG_PCIE) {
2821 		reset = bge_readmem_ind(sc, 0x7C00);
2822 		bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
2823 	}
2824 
2825 	/* Fix up byte swapping. */
2826 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2827 	    BGE_MODECTL_BYTESWAP_DATA);
2828 
2829 	/* Tell the ASF firmware we are up */
2830 	if (sc->bge_asf_mode & ASF_STACKUP)
2831 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2832 
2833 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2834 
2835 	/*
2836 	 * The 5704 in TBI mode apparently needs some special
2837 	 * adjustment to insure the SERDES drive level is set
2838 	 * to 1.2V.
2839 	 */
2840 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2841 	    sc->bge_flags & BGE_FLAG_TBI) {
2842 		uint32_t serdescfg;
2843 
2844 		serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2845 		serdescfg = (serdescfg & ~0xFFF) | 0x880;
2846 		CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2847 	}
2848 
2849 	/* XXX: Broadcom Linux driver. */
2850 	if (sc->bge_flags & BGE_FLAG_PCIE &&
2851 	    sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2852 		uint32_t v;
2853 
2854 		v = CSR_READ_4(sc, 0x7C00);
2855 		CSR_WRITE_4(sc, 0x7C00, v | (1 << 25));
2856 	}
2857 	DELAY(10000);
2858 
2859 	return(0);
2860 }
2861 
2862 /*
2863  * Frame reception handling. This is called if there's a frame
2864  * on the receive return list.
2865  *
2866  * Note: we have to be able to handle two possibilities here:
2867  * 1) the frame is from the jumbo receive ring
2868  * 2) the frame is from the standard receive ring
2869  */
2870 
2871 static void
2872 bge_rxeof(struct bge_softc *sc)
2873 {
2874 	struct ifnet *ifp;
2875 	int stdcnt = 0, jumbocnt = 0;
2876 
2877 	BGE_LOCK_ASSERT(sc);
2878 
2879 	/* Nothing to do. */
2880 	if (sc->bge_rx_saved_considx ==
2881 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2882 		return;
2883 
2884 	ifp = sc->bge_ifp;
2885 
2886 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2887 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2888 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2889 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
2890 	if (BGE_IS_JUMBO_CAPABLE(sc))
2891 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2892 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
2893 
2894 	while(sc->bge_rx_saved_considx !=
2895 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2896 		struct bge_rx_bd	*cur_rx;
2897 		uint32_t		rxidx;
2898 		struct mbuf		*m = NULL;
2899 		uint16_t		vlan_tag = 0;
2900 		int			have_tag = 0;
2901 
2902 #ifdef DEVICE_POLLING
2903 		if (ifp->if_capenable & IFCAP_POLLING) {
2904 			if (sc->rxcycles <= 0)
2905 				break;
2906 			sc->rxcycles--;
2907 		}
2908 #endif
2909 
2910 		cur_rx =
2911 	    &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2912 
2913 		rxidx = cur_rx->bge_idx;
2914 		BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2915 
2916 		if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
2917 		    cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2918 			have_tag = 1;
2919 			vlan_tag = cur_rx->bge_vlan_tag;
2920 		}
2921 
2922 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2923 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2924 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
2925 			    sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
2926 			    BUS_DMASYNC_POSTREAD);
2927 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
2928 			    sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
2929 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2930 			sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2931 			jumbocnt++;
2932 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2933 				ifp->if_ierrors++;
2934 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2935 				continue;
2936 			}
2937 			if (bge_newbuf_jumbo(sc,
2938 			    sc->bge_jumbo, NULL) == ENOBUFS) {
2939 				ifp->if_ierrors++;
2940 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2941 				continue;
2942 			}
2943 		} else {
2944 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2945 			bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2946 			    sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2947 			    BUS_DMASYNC_POSTREAD);
2948 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2949 			    sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2950 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2951 			sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2952 			stdcnt++;
2953 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2954 				ifp->if_ierrors++;
2955 				bge_newbuf_std(sc, sc->bge_std, m);
2956 				continue;
2957 			}
2958 			if (bge_newbuf_std(sc, sc->bge_std,
2959 			    NULL) == ENOBUFS) {
2960 				ifp->if_ierrors++;
2961 				bge_newbuf_std(sc, sc->bge_std, m);
2962 				continue;
2963 			}
2964 		}
2965 
2966 		ifp->if_ipackets++;
2967 #ifndef __NO_STRICT_ALIGNMENT
2968 		/*
2969 		 * For architectures with strict alignment we must make sure
2970 		 * the payload is aligned.
2971 		 */
2972 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2973 			bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2974 			    cur_rx->bge_len);
2975 			m->m_data += ETHER_ALIGN;
2976 		}
2977 #endif
2978 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2979 		m->m_pkthdr.rcvif = ifp;
2980 
2981 		if (ifp->if_capenable & IFCAP_RXCSUM) {
2982 			if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2983 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2984 				if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
2985 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2986 			}
2987 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2988 			    m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
2989 				m->m_pkthdr.csum_data =
2990 				    cur_rx->bge_tcp_udp_csum;
2991 				m->m_pkthdr.csum_flags |=
2992 				    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2993 			}
2994 		}
2995 
2996 		/*
2997 		 * If we received a packet with a vlan tag,
2998 		 * attach that information to the packet.
2999 		 */
3000 		if (have_tag) {
3001 #if __FreeBSD_version > 700022
3002 			m->m_pkthdr.ether_vtag = vlan_tag;
3003 			m->m_flags |= M_VLANTAG;
3004 #else
3005 			VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3006 			if (m == NULL)
3007 				continue;
3008 #endif
3009 		}
3010 
3011 		BGE_UNLOCK(sc);
3012 		(*ifp->if_input)(ifp, m);
3013 		BGE_LOCK(sc);
3014 	}
3015 
3016 	if (stdcnt > 0)
3017 		bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3018 		    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3019 
3020 	if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
3021 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3022 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3023 
3024 	CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3025 	if (stdcnt)
3026 		CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3027 	if (jumbocnt)
3028 		CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3029 #ifdef notyet
3030 	/*
3031 	 * This register wraps very quickly under heavy packet drops.
3032 	 * If you need correct statistics, you can enable this check.
3033 	 */
3034 	if (BGE_IS_5705_PLUS(sc))
3035 		ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3036 #endif
3037 }
3038 
3039 static void
3040 bge_txeof(struct bge_softc *sc)
3041 {
3042 	struct bge_tx_bd *cur_tx = NULL;
3043 	struct ifnet *ifp;
3044 
3045 	BGE_LOCK_ASSERT(sc);
3046 
3047 	/* Nothing to do. */
3048 	if (sc->bge_tx_saved_considx ==
3049 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
3050 		return;
3051 
3052 	ifp = sc->bge_ifp;
3053 
3054 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3055 	    sc->bge_cdata.bge_tx_ring_map,
3056 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3057 	/*
3058 	 * Go through our tx ring and free mbufs for those
3059 	 * frames that have been sent.
3060 	 */
3061 	while (sc->bge_tx_saved_considx !=
3062 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
3063 		uint32_t		idx = 0;
3064 
3065 		idx = sc->bge_tx_saved_considx;
3066 		cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3067 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3068 			ifp->if_opackets++;
3069 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3070 			bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3071 			    sc->bge_cdata.bge_tx_dmamap[idx],
3072 			    BUS_DMASYNC_POSTWRITE);
3073 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3074 			    sc->bge_cdata.bge_tx_dmamap[idx]);
3075 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3076 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
3077 		}
3078 		sc->bge_txcnt--;
3079 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3080 	}
3081 
3082 	if (cur_tx != NULL)
3083 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3084 	if (sc->bge_txcnt == 0)
3085 		sc->bge_timer = 0;
3086 }
3087 
3088 #ifdef DEVICE_POLLING
3089 static void
3090 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3091 {
3092 	struct bge_softc *sc = ifp->if_softc;
3093 	uint32_t statusword;
3094 
3095 	BGE_LOCK(sc);
3096 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3097 		BGE_UNLOCK(sc);
3098 		return;
3099 	}
3100 
3101 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3102 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3103 
3104 	statusword = atomic_readandclear_32(
3105 	    &sc->bge_ldata.bge_status_block->bge_status);
3106 
3107 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3108 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3109 
3110 	/* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3111 	if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3112 		sc->bge_link_evt++;
3113 
3114 	if (cmd == POLL_AND_CHECK_STATUS)
3115 		if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3116 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3117 		    sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3118 			bge_link_upd(sc);
3119 
3120 	sc->rxcycles = count;
3121 	bge_rxeof(sc);
3122 	bge_txeof(sc);
3123 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3124 		bge_start_locked(ifp);
3125 
3126 	BGE_UNLOCK(sc);
3127 }
3128 #endif /* DEVICE_POLLING */
3129 
3130 static void
3131 bge_intr(void *xsc)
3132 {
3133 	struct bge_softc *sc;
3134 	struct ifnet *ifp;
3135 	uint32_t statusword;
3136 
3137 	sc = xsc;
3138 
3139 	BGE_LOCK(sc);
3140 
3141 	ifp = sc->bge_ifp;
3142 
3143 #ifdef DEVICE_POLLING
3144 	if (ifp->if_capenable & IFCAP_POLLING) {
3145 		BGE_UNLOCK(sc);
3146 		return;
3147 	}
3148 #endif
3149 
3150 	/*
3151 	 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3152 	 * disable interrupts by writing nonzero like we used to, since with
3153 	 * our current organization this just gives complications and
3154 	 * pessimizations for re-enabling interrupts.  We used to have races
3155 	 * instead of the necessary complications.  Disabling interrupts
3156 	 * would just reduce the chance of a status update while we are
3157 	 * running (by switching to the interrupt-mode coalescence
3158 	 * parameters), but this chance is already very low so it is more
3159 	 * efficient to get another interrupt than prevent it.
3160 	 *
3161 	 * We do the ack first to ensure another interrupt if there is a
3162 	 * status update after the ack.  We don't check for the status
3163 	 * changing later because it is more efficient to get another
3164 	 * interrupt than prevent it, not quite as above (not checking is
3165 	 * a smaller optimization than not toggling the interrupt enable,
3166 	 * since checking doesn't involve PCI accesses and toggling require
3167 	 * the status check).  So toggling would probably be a pessimization
3168 	 * even with MSI.  It would only be needed for using a task queue.
3169 	 */
3170 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3171 
3172 	/*
3173 	 * Do the mandatory PCI flush as well as get the link status.
3174 	 */
3175 	statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3176 
3177 	/* Make sure the descriptor ring indexes are coherent. */
3178 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3179 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3180 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3181 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3182 
3183 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3184 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3185 	    statusword || sc->bge_link_evt)
3186 		bge_link_upd(sc);
3187 
3188 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3189 		/* Check RX return ring producer/consumer. */
3190 		bge_rxeof(sc);
3191 
3192 		/* Check TX ring producer/consumer. */
3193 		bge_txeof(sc);
3194 	}
3195 
3196 	if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3197 	    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3198 		bge_start_locked(ifp);
3199 
3200 	BGE_UNLOCK(sc);
3201 }
3202 
3203 static void
3204 bge_asf_driver_up(struct bge_softc *sc)
3205 {
3206 	if (sc->bge_asf_mode & ASF_STACKUP) {
3207 		/* Send ASF heartbeat aprox. every 2s */
3208 		if (sc->bge_asf_count)
3209 			sc->bge_asf_count --;
3210 		else {
3211 			sc->bge_asf_count = 5;
3212 			bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3213 			    BGE_FW_DRV_ALIVE);
3214 			bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3215 			bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3216 			CSR_WRITE_4(sc, BGE_CPU_EVENT,
3217 			    CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3218 		}
3219 	}
3220 }
3221 
3222 static void
3223 bge_tick(void *xsc)
3224 {
3225 	struct bge_softc *sc = xsc;
3226 	struct mii_data *mii = NULL;
3227 
3228 	BGE_LOCK_ASSERT(sc);
3229 
3230 	/* Synchronize with possible callout reset/stop. */
3231 	if (callout_pending(&sc->bge_stat_ch) ||
3232 	    !callout_active(&sc->bge_stat_ch))
3233 	    	return;
3234 
3235 	if (BGE_IS_5705_PLUS(sc))
3236 		bge_stats_update_regs(sc);
3237 	else
3238 		bge_stats_update(sc);
3239 
3240 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3241 		mii = device_get_softc(sc->bge_miibus);
3242 		/* Don't mess with the PHY in IPMI/ASF mode */
3243 		if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link)))
3244 			mii_tick(mii);
3245 	} else {
3246 		/*
3247 		 * Since in TBI mode auto-polling can't be used we should poll
3248 		 * link status manually. Here we register pending link event
3249 		 * and trigger interrupt.
3250 		 */
3251 #ifdef DEVICE_POLLING
3252 		/* In polling mode we poll link state in bge_poll(). */
3253 		if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3254 #endif
3255 		{
3256 		sc->bge_link_evt++;
3257 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3258 		}
3259 	}
3260 
3261 	bge_asf_driver_up(sc);
3262 	bge_watchdog(sc);
3263 
3264 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3265 }
3266 
3267 static void
3268 bge_stats_update_regs(struct bge_softc *sc)
3269 {
3270 	struct ifnet *ifp;
3271 
3272 	ifp = sc->bge_ifp;
3273 
3274 	ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3275 	    offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3276 
3277 	ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3278 }
3279 
3280 static void
3281 bge_stats_update(struct bge_softc *sc)
3282 {
3283 	struct ifnet *ifp;
3284 	bus_size_t stats;
3285 	uint32_t cnt;	/* current register value */
3286 
3287 	ifp = sc->bge_ifp;
3288 
3289 	stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3290 
3291 #define	READ_STAT(sc, stats, stat) \
3292 	CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3293 
3294 	cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3295 	ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3296 	sc->bge_tx_collisions = cnt;
3297 
3298 	cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3299 	ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3300 	sc->bge_rx_discards = cnt;
3301 
3302 	cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3303 	ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3304 	sc->bge_tx_discards = cnt;
3305 
3306 #undef	READ_STAT
3307 }
3308 
3309 /*
3310  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3311  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3312  * but when such padded frames employ the bge IP/TCP checksum offload,
3313  * the hardware checksum assist gives incorrect results (possibly
3314  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3315  * If we pad such runts with zeros, the onboard checksum comes out correct.
3316  */
3317 static __inline int
3318 bge_cksum_pad(struct mbuf *m)
3319 {
3320 	int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3321 	struct mbuf *last;
3322 
3323 	/* If there's only the packet-header and we can pad there, use it. */
3324 	if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3325 	    M_TRAILINGSPACE(m) >= padlen) {
3326 		last = m;
3327 	} else {
3328 		/*
3329 		 * Walk packet chain to find last mbuf. We will either
3330 		 * pad there, or append a new mbuf and pad it.
3331 		 */
3332 		for (last = m; last->m_next != NULL; last = last->m_next);
3333 		if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3334 			/* Allocate new empty mbuf, pad it. Compact later. */
3335 			struct mbuf *n;
3336 
3337 			MGET(n, M_DONTWAIT, MT_DATA);
3338 			if (n == NULL)
3339 				return (ENOBUFS);
3340 			n->m_len = 0;
3341 			last->m_next = n;
3342 			last = n;
3343 		}
3344 	}
3345 
3346 	/* Now zero the pad area, to avoid the bge cksum-assist bug. */
3347 	memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3348 	last->m_len += padlen;
3349 	m->m_pkthdr.len += padlen;
3350 
3351 	return (0);
3352 }
3353 
3354 /*
3355  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3356  * pointers to descriptors.
3357  */
3358 static int
3359 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3360 {
3361 	bus_dma_segment_t	segs[BGE_NSEG_NEW];
3362 	bus_dmamap_t		map;
3363 	struct bge_tx_bd	*d;
3364 	struct mbuf		*m = *m_head;
3365 	uint32_t		idx = *txidx;
3366 	uint16_t		csum_flags;
3367 	int			nsegs, i, error;
3368 
3369 	csum_flags = 0;
3370 	if (m->m_pkthdr.csum_flags) {
3371 		if (m->m_pkthdr.csum_flags & CSUM_IP)
3372 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3373 		if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3374 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3375 			if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3376 			    (error = bge_cksum_pad(m)) != 0) {
3377 				m_freem(m);
3378 				*m_head = NULL;
3379 				return (error);
3380 			}
3381 		}
3382 		if (m->m_flags & M_LASTFRAG)
3383 			csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3384 		else if (m->m_flags & M_FRAG)
3385 			csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3386 	}
3387 
3388 	map = sc->bge_cdata.bge_tx_dmamap[idx];
3389 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
3390 	    &nsegs, BUS_DMA_NOWAIT);
3391 	if (error == EFBIG) {
3392 		m = m_defrag(m, M_DONTWAIT);
3393 		if (m == NULL) {
3394 			m_freem(*m_head);
3395 			*m_head = NULL;
3396 			return (ENOBUFS);
3397 		}
3398 		*m_head = m;
3399 		error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
3400 		    segs, &nsegs, BUS_DMA_NOWAIT);
3401 		if (error) {
3402 			m_freem(m);
3403 			*m_head = NULL;
3404 			return (error);
3405 		}
3406 	} else if (error != 0)
3407 		return (error);
3408 
3409 	/*
3410 	 * Sanity check: avoid coming within 16 descriptors
3411 	 * of the end of the ring.
3412 	 */
3413 	if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3414 		bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
3415 		return (ENOBUFS);
3416 	}
3417 
3418 	bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
3419 
3420 	for (i = 0; ; i++) {
3421 		d = &sc->bge_ldata.bge_tx_ring[idx];
3422 		d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3423 		d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3424 		d->bge_len = segs[i].ds_len;
3425 		d->bge_flags = csum_flags;
3426 		if (i == nsegs - 1)
3427 			break;
3428 		BGE_INC(idx, BGE_TX_RING_CNT);
3429 	}
3430 
3431 	/* Mark the last segment as end of packet... */
3432 	d->bge_flags |= BGE_TXBDFLAG_END;
3433 
3434 	/* ... and put VLAN tag into first segment.  */
3435 	d = &sc->bge_ldata.bge_tx_ring[*txidx];
3436 #if __FreeBSD_version > 700022
3437 	if (m->m_flags & M_VLANTAG) {
3438 		d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3439 		d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3440 	} else
3441 		d->bge_vlan_tag = 0;
3442 #else
3443 	{
3444 		struct m_tag		*mtag;
3445 
3446 		if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3447 			d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3448 			d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3449 		} else
3450 			d->bge_vlan_tag = 0;
3451 	}
3452 #endif
3453 
3454 	/*
3455 	 * Insure that the map for this transmission
3456 	 * is placed at the array index of the last descriptor
3457 	 * in this chain.
3458 	 */
3459 	sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3460 	sc->bge_cdata.bge_tx_dmamap[idx] = map;
3461 	sc->bge_cdata.bge_tx_chain[idx] = m;
3462 	sc->bge_txcnt += nsegs;
3463 
3464 	BGE_INC(idx, BGE_TX_RING_CNT);
3465 	*txidx = idx;
3466 
3467 	return (0);
3468 }
3469 
3470 /*
3471  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3472  * to the mbuf data regions directly in the transmit descriptors.
3473  */
3474 static void
3475 bge_start_locked(struct ifnet *ifp)
3476 {
3477 	struct bge_softc *sc;
3478 	struct mbuf *m_head = NULL;
3479 	uint32_t prodidx;
3480 	int count = 0;
3481 
3482 	sc = ifp->if_softc;
3483 
3484 	if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3485 		return;
3486 
3487 	prodidx = sc->bge_tx_prodidx;
3488 
3489 	while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3490 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3491 		if (m_head == NULL)
3492 			break;
3493 
3494 		/*
3495 		 * XXX
3496 		 * The code inside the if() block is never reached since we
3497 		 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3498 		 * requests to checksum TCP/UDP in a fragmented packet.
3499 		 *
3500 		 * XXX
3501 		 * safety overkill.  If this is a fragmented packet chain
3502 		 * with delayed TCP/UDP checksums, then only encapsulate
3503 		 * it if we have enough descriptors to handle the entire
3504 		 * chain at once.
3505 		 * (paranoia -- may not actually be needed)
3506 		 */
3507 		if (m_head->m_flags & M_FIRSTFRAG &&
3508 		    m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3509 			if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3510 			    m_head->m_pkthdr.csum_data + 16) {
3511 				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3512 				ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3513 				break;
3514 			}
3515 		}
3516 
3517 		/*
3518 		 * Pack the data into the transmit ring. If we
3519 		 * don't have room, set the OACTIVE flag and wait
3520 		 * for the NIC to drain the ring.
3521 		 */
3522 		if (bge_encap(sc, &m_head, &prodidx)) {
3523 			if (m_head == NULL)
3524 				break;
3525 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3526 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3527 			break;
3528 		}
3529 		++count;
3530 
3531 		/*
3532 		 * If there's a BPF listener, bounce a copy of this frame
3533 		 * to him.
3534 		 */
3535 #ifdef ETHER_BPF_MTAP
3536 		ETHER_BPF_MTAP(ifp, m_head);
3537 #else
3538 		BPF_MTAP(ifp, m_head);
3539 #endif
3540 	}
3541 
3542 	if (count == 0)
3543 		/* No packets were dequeued. */
3544 		return;
3545 
3546 	/* Transmit. */
3547 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3548 	/* 5700 b2 errata */
3549 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3550 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3551 
3552 	sc->bge_tx_prodidx = prodidx;
3553 
3554 	/*
3555 	 * Set a timeout in case the chip goes out to lunch.
3556 	 */
3557 	sc->bge_timer = 5;
3558 }
3559 
3560 /*
3561  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3562  * to the mbuf data regions directly in the transmit descriptors.
3563  */
3564 static void
3565 bge_start(struct ifnet *ifp)
3566 {
3567 	struct bge_softc *sc;
3568 
3569 	sc = ifp->if_softc;
3570 	BGE_LOCK(sc);
3571 	bge_start_locked(ifp);
3572 	BGE_UNLOCK(sc);
3573 }
3574 
3575 static void
3576 bge_init_locked(struct bge_softc *sc)
3577 {
3578 	struct ifnet *ifp;
3579 	uint16_t *m;
3580 
3581 	BGE_LOCK_ASSERT(sc);
3582 
3583 	ifp = sc->bge_ifp;
3584 
3585 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3586 		return;
3587 
3588 	/* Cancel pending I/O and flush buffers. */
3589 	bge_stop(sc);
3590 
3591 	bge_stop_fw(sc);
3592 	bge_sig_pre_reset(sc, BGE_RESET_START);
3593 	bge_reset(sc);
3594 	bge_sig_legacy(sc, BGE_RESET_START);
3595 	bge_sig_post_reset(sc, BGE_RESET_START);
3596 
3597 	bge_chipinit(sc);
3598 
3599 	/*
3600 	 * Init the various state machines, ring
3601 	 * control blocks and firmware.
3602 	 */
3603 	if (bge_blockinit(sc)) {
3604 		device_printf(sc->bge_dev, "initialization failure\n");
3605 		return;
3606 	}
3607 
3608 	ifp = sc->bge_ifp;
3609 
3610 	/* Specify MTU. */
3611 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3612 	    ETHER_HDR_LEN + ETHER_CRC_LEN +
3613 	    (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
3614 
3615 	/* Load our MAC address. */
3616 	m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3617 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3618 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3619 
3620 	/* Program promiscuous mode. */
3621 	bge_setpromisc(sc);
3622 
3623 	/* Program multicast filter. */
3624 	bge_setmulti(sc);
3625 
3626 	/* Program VLAN tag stripping. */
3627 	bge_setvlan(sc);
3628 
3629 	/* Init RX ring. */
3630 	bge_init_rx_ring_std(sc);
3631 
3632 	/*
3633 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3634 	 * memory to insure that the chip has in fact read the first
3635 	 * entry of the ring.
3636 	 */
3637 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3638 		uint32_t		v, i;
3639 		for (i = 0; i < 10; i++) {
3640 			DELAY(20);
3641 			v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3642 			if (v == (MCLBYTES - ETHER_ALIGN))
3643 				break;
3644 		}
3645 		if (i == 10)
3646 			device_printf (sc->bge_dev,
3647 			    "5705 A0 chip failed to load RX ring\n");
3648 	}
3649 
3650 	/* Init jumbo RX ring. */
3651 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3652 		bge_init_rx_ring_jumbo(sc);
3653 
3654 	/* Init our RX return ring index. */
3655 	sc->bge_rx_saved_considx = 0;
3656 
3657 	/* Init our RX/TX stat counters. */
3658 	sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3659 
3660 	/* Init TX ring. */
3661 	bge_init_tx_ring(sc);
3662 
3663 	/* Turn on transmitter. */
3664 	BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3665 
3666 	/* Turn on receiver. */
3667 	BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3668 
3669 	/* Tell firmware we're alive. */
3670 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3671 
3672 #ifdef DEVICE_POLLING
3673 	/* Disable interrupts if we are polling. */
3674 	if (ifp->if_capenable & IFCAP_POLLING) {
3675 		BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3676 		    BGE_PCIMISCCTL_MASK_PCI_INTR);
3677 		CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3678 	} else
3679 #endif
3680 
3681 	/* Enable host interrupts. */
3682 	{
3683 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3684 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3685 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3686 	}
3687 
3688 	bge_ifmedia_upd_locked(ifp);
3689 
3690 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3691 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3692 
3693 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3694 }
3695 
3696 static void
3697 bge_init(void *xsc)
3698 {
3699 	struct bge_softc *sc = xsc;
3700 
3701 	BGE_LOCK(sc);
3702 	bge_init_locked(sc);
3703 	BGE_UNLOCK(sc);
3704 }
3705 
3706 /*
3707  * Set media options.
3708  */
3709 static int
3710 bge_ifmedia_upd(struct ifnet *ifp)
3711 {
3712 	struct bge_softc *sc = ifp->if_softc;
3713 	int res;
3714 
3715 	BGE_LOCK(sc);
3716 	res = bge_ifmedia_upd_locked(ifp);
3717 	BGE_UNLOCK(sc);
3718 
3719 	return (res);
3720 }
3721 
3722 static int
3723 bge_ifmedia_upd_locked(struct ifnet *ifp)
3724 {
3725 	struct bge_softc *sc = ifp->if_softc;
3726 	struct mii_data *mii;
3727 	struct ifmedia *ifm;
3728 
3729 	BGE_LOCK_ASSERT(sc);
3730 
3731 	ifm = &sc->bge_ifmedia;
3732 
3733 	/* If this is a 1000baseX NIC, enable the TBI port. */
3734 	if (sc->bge_flags & BGE_FLAG_TBI) {
3735 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3736 			return (EINVAL);
3737 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
3738 		case IFM_AUTO:
3739 			/*
3740 			 * The BCM5704 ASIC appears to have a special
3741 			 * mechanism for programming the autoneg
3742 			 * advertisement registers in TBI mode.
3743 			 */
3744 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3745 				uint32_t sgdig;
3746 				sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
3747 				if (sgdig & BGE_SGDIGSTS_DONE) {
3748 					CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3749 					sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3750 					sgdig |= BGE_SGDIGCFG_AUTO |
3751 					    BGE_SGDIGCFG_PAUSE_CAP |
3752 					    BGE_SGDIGCFG_ASYM_PAUSE;
3753 					CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3754 					    sgdig | BGE_SGDIGCFG_SEND);
3755 					DELAY(5);
3756 					CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3757 				}
3758 			}
3759 			break;
3760 		case IFM_1000_SX:
3761 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3762 				BGE_CLRBIT(sc, BGE_MAC_MODE,
3763 				    BGE_MACMODE_HALF_DUPLEX);
3764 			} else {
3765 				BGE_SETBIT(sc, BGE_MAC_MODE,
3766 				    BGE_MACMODE_HALF_DUPLEX);
3767 			}
3768 			break;
3769 		default:
3770 			return (EINVAL);
3771 		}
3772 		return (0);
3773 	}
3774 
3775 	sc->bge_link_evt++;
3776 	mii = device_get_softc(sc->bge_miibus);
3777 	if (mii->mii_instance) {
3778 		struct mii_softc *miisc;
3779 		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3780 		    miisc = LIST_NEXT(miisc, mii_list))
3781 			mii_phy_reset(miisc);
3782 	}
3783 	mii_mediachg(mii);
3784 
3785 	return (0);
3786 }
3787 
3788 /*
3789  * Report current media status.
3790  */
3791 static void
3792 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3793 {
3794 	struct bge_softc *sc = ifp->if_softc;
3795 	struct mii_data *mii;
3796 
3797 	BGE_LOCK(sc);
3798 
3799 	if (sc->bge_flags & BGE_FLAG_TBI) {
3800 		ifmr->ifm_status = IFM_AVALID;
3801 		ifmr->ifm_active = IFM_ETHER;
3802 		if (CSR_READ_4(sc, BGE_MAC_STS) &
3803 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
3804 			ifmr->ifm_status |= IFM_ACTIVE;
3805 		else {
3806 			ifmr->ifm_active |= IFM_NONE;
3807 			BGE_UNLOCK(sc);
3808 			return;
3809 		}
3810 		ifmr->ifm_active |= IFM_1000_SX;
3811 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3812 			ifmr->ifm_active |= IFM_HDX;
3813 		else
3814 			ifmr->ifm_active |= IFM_FDX;
3815 		BGE_UNLOCK(sc);
3816 		return;
3817 	}
3818 
3819 	mii = device_get_softc(sc->bge_miibus);
3820 	mii_pollstat(mii);
3821 	ifmr->ifm_active = mii->mii_media_active;
3822 	ifmr->ifm_status = mii->mii_media_status;
3823 
3824 	BGE_UNLOCK(sc);
3825 }
3826 
3827 static int
3828 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3829 {
3830 	struct bge_softc *sc = ifp->if_softc;
3831 	struct ifreq *ifr = (struct ifreq *) data;
3832 	struct mii_data *mii;
3833 	int flags, mask, error = 0;
3834 
3835 	switch (command) {
3836 	case SIOCSIFMTU:
3837 		if (ifr->ifr_mtu < ETHERMIN ||
3838 		    ((BGE_IS_JUMBO_CAPABLE(sc)) &&
3839 		    ifr->ifr_mtu > BGE_JUMBO_MTU) ||
3840 		    ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
3841 		    ifr->ifr_mtu > ETHERMTU))
3842 			error = EINVAL;
3843 		else if (ifp->if_mtu != ifr->ifr_mtu) {
3844 			ifp->if_mtu = ifr->ifr_mtu;
3845 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3846 			bge_init(sc);
3847 		}
3848 		break;
3849 	case SIOCSIFFLAGS:
3850 		BGE_LOCK(sc);
3851 		if (ifp->if_flags & IFF_UP) {
3852 			/*
3853 			 * If only the state of the PROMISC flag changed,
3854 			 * then just use the 'set promisc mode' command
3855 			 * instead of reinitializing the entire NIC. Doing
3856 			 * a full re-init means reloading the firmware and
3857 			 * waiting for it to start up, which may take a
3858 			 * second or two.  Similarly for ALLMULTI.
3859 			 */
3860 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3861 				flags = ifp->if_flags ^ sc->bge_if_flags;
3862 				if (flags & IFF_PROMISC)
3863 					bge_setpromisc(sc);
3864 				if (flags & IFF_ALLMULTI)
3865 					bge_setmulti(sc);
3866 			} else
3867 				bge_init_locked(sc);
3868 		} else {
3869 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3870 				bge_stop(sc);
3871 			}
3872 		}
3873 		sc->bge_if_flags = ifp->if_flags;
3874 		BGE_UNLOCK(sc);
3875 		error = 0;
3876 		break;
3877 	case SIOCADDMULTI:
3878 	case SIOCDELMULTI:
3879 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3880 			BGE_LOCK(sc);
3881 			bge_setmulti(sc);
3882 			BGE_UNLOCK(sc);
3883 			error = 0;
3884 		}
3885 		break;
3886 	case SIOCSIFMEDIA:
3887 	case SIOCGIFMEDIA:
3888 		if (sc->bge_flags & BGE_FLAG_TBI) {
3889 			error = ifmedia_ioctl(ifp, ifr,
3890 			    &sc->bge_ifmedia, command);
3891 		} else {
3892 			mii = device_get_softc(sc->bge_miibus);
3893 			error = ifmedia_ioctl(ifp, ifr,
3894 			    &mii->mii_media, command);
3895 		}
3896 		break;
3897 	case SIOCSIFCAP:
3898 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3899 #ifdef DEVICE_POLLING
3900 		if (mask & IFCAP_POLLING) {
3901 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
3902 				error = ether_poll_register(bge_poll, ifp);
3903 				if (error)
3904 					return (error);
3905 				BGE_LOCK(sc);
3906 				BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3907 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
3908 				CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3909 				ifp->if_capenable |= IFCAP_POLLING;
3910 				BGE_UNLOCK(sc);
3911 			} else {
3912 				error = ether_poll_deregister(ifp);
3913 				/* Enable interrupt even in error case */
3914 				BGE_LOCK(sc);
3915 				BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
3916 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
3917 				CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3918 				ifp->if_capenable &= ~IFCAP_POLLING;
3919 				BGE_UNLOCK(sc);
3920 			}
3921 		}
3922 #endif
3923 		if (mask & IFCAP_HWCSUM) {
3924 			ifp->if_capenable ^= IFCAP_HWCSUM;
3925 			if (IFCAP_HWCSUM & ifp->if_capenable &&
3926 			    IFCAP_HWCSUM & ifp->if_capabilities)
3927 				ifp->if_hwassist = BGE_CSUM_FEATURES;
3928 			else
3929 				ifp->if_hwassist = 0;
3930 #ifdef VLAN_CAPABILITIES
3931 			VLAN_CAPABILITIES(ifp);
3932 #endif
3933 		}
3934 
3935 		if (mask & IFCAP_VLAN_MTU) {
3936 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
3937 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3938 			bge_init(sc);
3939 		}
3940 
3941 		if (mask & IFCAP_VLAN_HWTAGGING) {
3942 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3943 			BGE_LOCK(sc);
3944 			bge_setvlan(sc);
3945 			BGE_UNLOCK(sc);
3946 #ifdef VLAN_CAPABILITIES
3947 			VLAN_CAPABILITIES(ifp);
3948 #endif
3949 		}
3950 
3951 		break;
3952 	default:
3953 		error = ether_ioctl(ifp, command, data);
3954 		break;
3955 	}
3956 
3957 	return (error);
3958 }
3959 
3960 static void
3961 bge_watchdog(struct bge_softc *sc)
3962 {
3963 	struct ifnet *ifp;
3964 
3965 	BGE_LOCK_ASSERT(sc);
3966 
3967 	if (sc->bge_timer == 0 || --sc->bge_timer)
3968 		return;
3969 
3970 	ifp = sc->bge_ifp;
3971 
3972 	if_printf(ifp, "watchdog timeout -- resetting\n");
3973 
3974 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3975 	bge_init_locked(sc);
3976 
3977 	ifp->if_oerrors++;
3978 }
3979 
3980 /*
3981  * Stop the adapter and free any mbufs allocated to the
3982  * RX and TX lists.
3983  */
3984 static void
3985 bge_stop(struct bge_softc *sc)
3986 {
3987 	struct ifnet *ifp;
3988 	struct ifmedia_entry *ifm;
3989 	struct mii_data *mii = NULL;
3990 	int mtmp, itmp;
3991 
3992 	BGE_LOCK_ASSERT(sc);
3993 
3994 	ifp = sc->bge_ifp;
3995 
3996 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3997 		mii = device_get_softc(sc->bge_miibus);
3998 
3999 	callout_stop(&sc->bge_stat_ch);
4000 
4001 	/*
4002 	 * Disable all of the receiver blocks.
4003 	 */
4004 	BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4005 	BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4006 	BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4007 	if (!(BGE_IS_5705_PLUS(sc)))
4008 		BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4009 	BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4010 	BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4011 	BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4012 
4013 	/*
4014 	 * Disable all of the transmit blocks.
4015 	 */
4016 	BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4017 	BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4018 	BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4019 	BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4020 	BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4021 	if (!(BGE_IS_5705_PLUS(sc)))
4022 		BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4023 	BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4024 
4025 	/*
4026 	 * Shut down all of the memory managers and related
4027 	 * state machines.
4028 	 */
4029 	BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4030 	BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4031 	if (!(BGE_IS_5705_PLUS(sc)))
4032 		BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4033 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4034 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4035 	if (!(BGE_IS_5705_PLUS(sc))) {
4036 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4037 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4038 	}
4039 
4040 	/* Disable host interrupts. */
4041 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4042 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
4043 
4044 	/*
4045 	 * Tell firmware we're shutting down.
4046 	 */
4047 
4048 	bge_stop_fw(sc);
4049 	bge_sig_pre_reset(sc, BGE_RESET_STOP);
4050 	bge_reset(sc);
4051 	bge_sig_legacy(sc, BGE_RESET_STOP);
4052 	bge_sig_post_reset(sc, BGE_RESET_STOP);
4053 
4054 	/*
4055 	 * Keep the ASF firmware running if up.
4056 	 */
4057 	if (sc->bge_asf_mode & ASF_STACKUP)
4058 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4059 	else
4060 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4061 
4062 	/* Free the RX lists. */
4063 	bge_free_rx_ring_std(sc);
4064 
4065 	/* Free jumbo RX list. */
4066 	if (BGE_IS_JUMBO_CAPABLE(sc))
4067 		bge_free_rx_ring_jumbo(sc);
4068 
4069 	/* Free TX buffers. */
4070 	bge_free_tx_ring(sc);
4071 
4072 	/*
4073 	 * Isolate/power down the PHY, but leave the media selection
4074 	 * unchanged so that things will be put back to normal when
4075 	 * we bring the interface back up.
4076 	 */
4077 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4078 		itmp = ifp->if_flags;
4079 		ifp->if_flags |= IFF_UP;
4080 		/*
4081 		 * If we are called from bge_detach(), mii is already NULL.
4082 		 */
4083 		if (mii != NULL) {
4084 			ifm = mii->mii_media.ifm_cur;
4085 			mtmp = ifm->ifm_media;
4086 			ifm->ifm_media = IFM_ETHER | IFM_NONE;
4087 			mii_mediachg(mii);
4088 			ifm->ifm_media = mtmp;
4089 		}
4090 		ifp->if_flags = itmp;
4091 	}
4092 
4093 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4094 
4095 	/* Clear MAC's link state (PHY may still have link UP). */
4096 	if (bootverbose && sc->bge_link)
4097 		if_printf(sc->bge_ifp, "link DOWN\n");
4098 	sc->bge_link = 0;
4099 
4100 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4101 }
4102 
4103 /*
4104  * Stop all chip I/O so that the kernel's probe routines don't
4105  * get confused by errant DMAs when rebooting.
4106  */
4107 static void
4108 bge_shutdown(device_t dev)
4109 {
4110 	struct bge_softc *sc;
4111 
4112 	sc = device_get_softc(dev);
4113 
4114 	BGE_LOCK(sc);
4115 	bge_stop(sc);
4116 	bge_reset(sc);
4117 	BGE_UNLOCK(sc);
4118 }
4119 
4120 static int
4121 bge_suspend(device_t dev)
4122 {
4123 	struct bge_softc *sc;
4124 
4125 	sc = device_get_softc(dev);
4126 	BGE_LOCK(sc);
4127 	bge_stop(sc);
4128 	BGE_UNLOCK(sc);
4129 
4130 	return (0);
4131 }
4132 
4133 static int
4134 bge_resume(device_t dev)
4135 {
4136 	struct bge_softc *sc;
4137 	struct ifnet *ifp;
4138 
4139 	sc = device_get_softc(dev);
4140 	BGE_LOCK(sc);
4141 	ifp = sc->bge_ifp;
4142 	if (ifp->if_flags & IFF_UP) {
4143 		bge_init_locked(sc);
4144 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4145 			bge_start_locked(ifp);
4146 	}
4147 	BGE_UNLOCK(sc);
4148 
4149 	return (0);
4150 }
4151 
4152 static void
4153 bge_link_upd(struct bge_softc *sc)
4154 {
4155 	struct mii_data *mii;
4156 	uint32_t link, status;
4157 
4158 	BGE_LOCK_ASSERT(sc);
4159 
4160 	/* Clear 'pending link event' flag. */
4161 	sc->bge_link_evt = 0;
4162 
4163 	/*
4164 	 * Process link state changes.
4165 	 * Grrr. The link status word in the status block does
4166 	 * not work correctly on the BCM5700 rev AX and BX chips,
4167 	 * according to all available information. Hence, we have
4168 	 * to enable MII interrupts in order to properly obtain
4169 	 * async link changes. Unfortunately, this also means that
4170 	 * we have to read the MAC status register to detect link
4171 	 * changes, thereby adding an additional register access to
4172 	 * the interrupt handler.
4173 	 *
4174 	 * XXX: perhaps link state detection procedure used for
4175 	 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4176 	 */
4177 
4178 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4179 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4180 		status = CSR_READ_4(sc, BGE_MAC_STS);
4181 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
4182 			mii = device_get_softc(sc->bge_miibus);
4183 			mii_pollstat(mii);
4184 			if (!sc->bge_link &&
4185 			    mii->mii_media_status & IFM_ACTIVE &&
4186 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4187 				sc->bge_link++;
4188 				if (bootverbose)
4189 					if_printf(sc->bge_ifp, "link UP\n");
4190 			} else if (sc->bge_link &&
4191 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
4192 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4193 				sc->bge_link = 0;
4194 				if (bootverbose)
4195 					if_printf(sc->bge_ifp, "link DOWN\n");
4196 			}
4197 
4198 			/* Clear the interrupt. */
4199 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4200 			    BGE_EVTENB_MI_INTERRUPT);
4201 			bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4202 			bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4203 			    BRGPHY_INTRS);
4204 		}
4205 		return;
4206 	}
4207 
4208 	if (sc->bge_flags & BGE_FLAG_TBI) {
4209 		status = CSR_READ_4(sc, BGE_MAC_STS);
4210 		if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4211 			if (!sc->bge_link) {
4212 				sc->bge_link++;
4213 				if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4214 					BGE_CLRBIT(sc, BGE_MAC_MODE,
4215 					    BGE_MACMODE_TBI_SEND_CFGS);
4216 				CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4217 				if (bootverbose)
4218 					if_printf(sc->bge_ifp, "link UP\n");
4219 				if_link_state_change(sc->bge_ifp,
4220 				    LINK_STATE_UP);
4221 			}
4222 		} else if (sc->bge_link) {
4223 			sc->bge_link = 0;
4224 			if (bootverbose)
4225 				if_printf(sc->bge_ifp, "link DOWN\n");
4226 			if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4227 		}
4228 	} else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4229 		/*
4230 		 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4231 		 * in status word always set. Workaround this bug by reading
4232 		 * PHY link status directly.
4233 		 */
4234 		link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4235 
4236 		if (link != sc->bge_link ||
4237 		    sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4238 			mii = device_get_softc(sc->bge_miibus);
4239 			mii_pollstat(mii);
4240 			if (!sc->bge_link &&
4241 			    mii->mii_media_status & IFM_ACTIVE &&
4242 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4243 				sc->bge_link++;
4244 				if (bootverbose)
4245 					if_printf(sc->bge_ifp, "link UP\n");
4246 			} else if (sc->bge_link &&
4247 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
4248 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4249 				sc->bge_link = 0;
4250 				if (bootverbose)
4251 					if_printf(sc->bge_ifp, "link DOWN\n");
4252 			}
4253 		}
4254 	} else {
4255 		/*
4256 		 * Discard link events for MII/GMII controllers
4257 		 * if MI auto-polling is disabled.
4258 		 */
4259 	}
4260 
4261 	/* Clear the attention. */
4262 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4263 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4264 	    BGE_MACSTAT_LINK_CHANGED);
4265 }
4266 
4267 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4268 	SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4269 	    sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4270 	    desc)
4271 
4272 static void
4273 bge_add_sysctls(struct bge_softc *sc)
4274 {
4275 	struct sysctl_ctx_list *ctx;
4276 	struct sysctl_oid_list *children, *schildren;
4277 	struct sysctl_oid *tree;
4278 
4279 	ctx = device_get_sysctl_ctx(sc->bge_dev);
4280 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4281 
4282 #ifdef BGE_REGISTER_DEBUG
4283 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4284 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4285 	    "Debug Information");
4286 
4287 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4288 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4289 	    "Register Read");
4290 
4291 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4292 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4293 	    "Memory Read");
4294 
4295 #endif
4296 
4297 	tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4298 	    NULL, "BGE Statistics");
4299 	schildren = children = SYSCTL_CHILDREN(tree);
4300 	BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4301 	    children, COSFramesDroppedDueToFilters,
4302 	    "FramesDroppedDueToFilters");
4303 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4304 	    children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4305 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4306 	    children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4307 	BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4308 	    children, nicNoMoreRxBDs, "NoMoreRxBDs");
4309 	BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4310 	    children, ifInDiscards, "InputDiscards");
4311 	BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4312 	    children, ifInErrors, "InputErrors");
4313 	BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4314 	    children, nicRecvThresholdHit, "RecvThresholdHit");
4315 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4316 	    children, nicDmaReadQueueFull, "DmaReadQueueFull");
4317 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4318 	    children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4319 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4320 	    children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4321 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4322 	    children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4323 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4324 	    children, nicRingStatusUpdate, "RingStatusUpdate");
4325 	BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4326 	    children, nicInterrupts, "Interrupts");
4327 	BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4328 	    children, nicAvoidedInterrupts, "AvoidedInterrupts");
4329 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4330 	    children, nicSendThresholdHit, "SendThresholdHit");
4331 
4332 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4333 	    NULL, "BGE RX Statistics");
4334 	children = SYSCTL_CHILDREN(tree);
4335 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4336 	    children, rxstats.ifHCInOctets, "Octets");
4337 	BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4338 	    children, rxstats.etherStatsFragments, "Fragments");
4339 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4340 	    children, rxstats.ifHCInUcastPkts, "UcastPkts");
4341 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4342 	    children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4343 	BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4344 	    children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4345 	BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4346 	    children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4347 	BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4348 	    children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4349 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4350 	    children, rxstats.xoffPauseFramesReceived,
4351 	    "xoffPauseFramesReceived");
4352 	BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4353 	    children, rxstats.macControlFramesReceived,
4354 	    "ControlFramesReceived");
4355 	BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4356 	    children, rxstats.xoffStateEntered, "xoffStateEntered");
4357 	BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4358 	    children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4359 	BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4360 	    children, rxstats.etherStatsJabbers, "Jabbers");
4361 	BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4362 	    children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4363 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4364 	    children, rxstats.inRangeLengthError, "inRangeLengthError");
4365 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4366 	    children, rxstats.outRangeLengthError, "outRangeLengthError");
4367 
4368 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4369 	    NULL, "BGE TX Statistics");
4370 	children = SYSCTL_CHILDREN(tree);
4371 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4372 	    children, txstats.ifHCOutOctets, "Octets");
4373 	BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4374 	    children, txstats.etherStatsCollisions, "Collisions");
4375 	BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4376 	    children, txstats.outXonSent, "XonSent");
4377 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4378 	    children, txstats.outXoffSent, "XoffSent");
4379 	BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4380 	    children, txstats.flowControlDone, "flowControlDone");
4381 	BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4382 	    children, txstats.dot3StatsInternalMacTransmitErrors,
4383 	    "InternalMacTransmitErrors");
4384 	BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4385 	    children, txstats.dot3StatsSingleCollisionFrames,
4386 	    "SingleCollisionFrames");
4387 	BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4388 	    children, txstats.dot3StatsMultipleCollisionFrames,
4389 	    "MultipleCollisionFrames");
4390 	BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4391 	    children, txstats.dot3StatsDeferredTransmissions,
4392 	    "DeferredTransmissions");
4393 	BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4394 	    children, txstats.dot3StatsExcessiveCollisions,
4395 	    "ExcessiveCollisions");
4396 	BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4397 	    children, txstats.dot3StatsLateCollisions,
4398 	    "LateCollisions");
4399 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4400 	    children, txstats.ifHCOutUcastPkts, "UcastPkts");
4401 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4402 	    children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4403 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4404 	    children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4405 	BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4406 	    children, txstats.dot3StatsCarrierSenseErrors,
4407 	    "CarrierSenseErrors");
4408 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4409 	    children, txstats.ifOutDiscards, "Discards");
4410 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4411 	    children, txstats.ifOutErrors, "Errors");
4412 }
4413 
4414 static int
4415 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4416 {
4417 	struct bge_softc *sc;
4418 	uint32_t result;
4419 	int base, offset;
4420 
4421 	sc = (struct bge_softc *)arg1;
4422 	offset = arg2;
4423 	if (BGE_IS_5705_PLUS(sc))
4424 		base = BGE_MAC_STATS;
4425 	else
4426 		base = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4427 	result = CSR_READ_4(sc, base + offset + offsetof(bge_hostaddr,
4428 	    bge_addr_lo));
4429 	return (sysctl_handle_int(oidp, &result, 0, req));
4430 }
4431 
4432 #ifdef BGE_REGISTER_DEBUG
4433 static int
4434 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4435 {
4436 	struct bge_softc *sc;
4437 	uint16_t *sbdata;
4438 	int error;
4439 	int result;
4440 	int i, j;
4441 
4442 	result = -1;
4443 	error = sysctl_handle_int(oidp, &result, 0, req);
4444 	if (error || (req->newptr == NULL))
4445 		return (error);
4446 
4447 	if (result == 1) {
4448 		sc = (struct bge_softc *)arg1;
4449 
4450 		sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4451 		printf("Status Block:\n");
4452 		for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4453 			printf("%06x:", i);
4454 			for (j = 0; j < 8; j++) {
4455 				printf(" %04x", sbdata[i]);
4456 				i += 4;
4457 			}
4458 			printf("\n");
4459 		}
4460 
4461 		printf("Registers:\n");
4462 		for (i = 0x800; i < 0xA00; ) {
4463 			printf("%06x:", i);
4464 			for (j = 0; j < 8; j++) {
4465 				printf(" %08x", CSR_READ_4(sc, i));
4466 				i += 4;
4467 			}
4468 			printf("\n");
4469 		}
4470 
4471 		printf("Hardware Flags:\n");
4472 		if (BGE_IS_575X_PLUS(sc))
4473 			printf(" - 575X Plus\n");
4474 		if (BGE_IS_5705_PLUS(sc))
4475 			printf(" - 5705 Plus\n");
4476 		if (BGE_IS_5714_FAMILY(sc))
4477 			printf(" - 5714 Family\n");
4478 		if (BGE_IS_5700_FAMILY(sc))
4479 			printf(" - 5700 Family\n");
4480 		if (sc->bge_flags & BGE_FLAG_JUMBO)
4481 			printf(" - Supports Jumbo Frames\n");
4482 		if (sc->bge_flags & BGE_FLAG_PCIX)
4483 			printf(" - PCI-X Bus\n");
4484 		if (sc->bge_flags & BGE_FLAG_PCIE)
4485 			printf(" - PCI Express Bus\n");
4486 		if (sc->bge_flags & BGE_FLAG_NO_3LED)
4487 			printf(" - No 3 LEDs\n");
4488 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4489 			printf(" - RX Alignment Bug\n");
4490 	}
4491 
4492 	return (error);
4493 }
4494 
4495 static int
4496 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4497 {
4498 	struct bge_softc *sc;
4499 	int error;
4500 	uint16_t result;
4501 	uint32_t val;
4502 
4503 	result = -1;
4504 	error = sysctl_handle_int(oidp, &result, 0, req);
4505 	if (error || (req->newptr == NULL))
4506 		return (error);
4507 
4508 	if (result < 0x8000) {
4509 		sc = (struct bge_softc *)arg1;
4510 		val = CSR_READ_4(sc, result);
4511 		printf("reg 0x%06X = 0x%08X\n", result, val);
4512 	}
4513 
4514 	return (error);
4515 }
4516 
4517 static int
4518 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4519 {
4520 	struct bge_softc *sc;
4521 	int error;
4522 	uint16_t result;
4523 	uint32_t val;
4524 
4525 	result = -1;
4526 	error = sysctl_handle_int(oidp, &result, 0, req);
4527 	if (error || (req->newptr == NULL))
4528 		return (error);
4529 
4530 	if (result < 0x8000) {
4531 		sc = (struct bge_softc *)arg1;
4532 		val = bge_readmem_ind(sc, result);
4533 		printf("mem 0x%06X = 0x%08X\n", result, val);
4534 	}
4535 
4536 	return (error);
4537 }
4538 #endif
4539