1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 200 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 201 202 { TC_VENDORID, TC_DEVICEID_3C996 }, 203 204 { 0, 0 } 205 }; 206 207 static const struct bge_vendor { 208 uint16_t v_id; 209 const char *v_name; 210 } bge_vendors[] = { 211 { ALTEON_VENDORID, "Alteon" }, 212 { ALTIMA_VENDORID, "Altima" }, 213 { APPLE_VENDORID, "Apple" }, 214 { BCOM_VENDORID, "Broadcom" }, 215 { SK_VENDORID, "SysKonnect" }, 216 { TC_VENDORID, "3Com" }, 217 218 { 0, NULL } 219 }; 220 221 static const struct bge_revision { 222 uint32_t br_chipid; 223 const char *br_name; 224 } bge_revisions[] = { 225 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 226 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 227 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 228 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 229 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 230 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 231 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 232 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 233 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 234 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 235 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 236 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 237 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 238 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 239 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 240 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 241 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 242 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 243 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 244 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 245 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 246 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 247 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 248 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 249 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 250 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 251 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 252 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 253 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 254 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 255 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 256 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 257 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 258 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 259 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 260 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 261 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 262 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 263 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 264 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 265 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 266 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 267 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 268 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 269 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 270 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 271 /* 5754 and 5787 share the same ASIC ID */ 272 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 273 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 274 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 275 276 { 0, NULL } 277 }; 278 279 /* 280 * Some defaults for major revisions, so that newer steppings 281 * that we don't know about have a shot at working. 282 */ 283 static const struct bge_revision bge_majorrevs[] = { 284 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 285 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 286 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 287 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 288 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 289 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 290 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 291 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 292 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 293 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 294 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 295 /* 5754 and 5787 share the same ASIC ID */ 296 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 297 298 { 0, NULL } 299 }; 300 301 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 302 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 303 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 304 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 305 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 306 307 const struct bge_revision * bge_lookup_rev(uint32_t); 308 const struct bge_vendor * bge_lookup_vendor(uint16_t); 309 static int bge_probe(device_t); 310 static int bge_attach(device_t); 311 static int bge_detach(device_t); 312 static int bge_suspend(device_t); 313 static int bge_resume(device_t); 314 static void bge_release_resources(struct bge_softc *); 315 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 316 static int bge_dma_alloc(device_t); 317 static void bge_dma_free(struct bge_softc *); 318 319 static void bge_txeof(struct bge_softc *); 320 static void bge_rxeof(struct bge_softc *); 321 322 static void bge_asf_driver_up (struct bge_softc *); 323 static void bge_tick(void *); 324 static void bge_stats_update(struct bge_softc *); 325 static void bge_stats_update_regs(struct bge_softc *); 326 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 327 328 static void bge_intr(void *); 329 static void bge_start_locked(struct ifnet *); 330 static void bge_start(struct ifnet *); 331 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 332 static void bge_init_locked(struct bge_softc *); 333 static void bge_init(void *); 334 static void bge_stop(struct bge_softc *); 335 static void bge_watchdog(struct bge_softc *); 336 static void bge_shutdown(device_t); 337 static int bge_ifmedia_upd_locked(struct ifnet *); 338 static int bge_ifmedia_upd(struct ifnet *); 339 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 340 341 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 342 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 343 344 static void bge_setpromisc(struct bge_softc *); 345 static void bge_setmulti(struct bge_softc *); 346 static void bge_setvlan(struct bge_softc *); 347 348 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 349 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 350 static int bge_init_rx_ring_std(struct bge_softc *); 351 static void bge_free_rx_ring_std(struct bge_softc *); 352 static int bge_init_rx_ring_jumbo(struct bge_softc *); 353 static void bge_free_rx_ring_jumbo(struct bge_softc *); 354 static void bge_free_tx_ring(struct bge_softc *); 355 static int bge_init_tx_ring(struct bge_softc *); 356 357 static int bge_chipinit(struct bge_softc *); 358 static int bge_blockinit(struct bge_softc *); 359 360 static int bge_has_eeprom(struct bge_softc *); 361 static uint32_t bge_readmem_ind(struct bge_softc *, int); 362 static void bge_writemem_ind(struct bge_softc *, int, int); 363 #ifdef notdef 364 static uint32_t bge_readreg_ind(struct bge_softc *, int); 365 #endif 366 static void bge_writemem_direct(struct bge_softc *, int, int); 367 static void bge_writereg_ind(struct bge_softc *, int, int); 368 369 static int bge_miibus_readreg(device_t, int, int); 370 static int bge_miibus_writereg(device_t, int, int, int); 371 static void bge_miibus_statchg(device_t); 372 #ifdef DEVICE_POLLING 373 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 374 #endif 375 376 #define BGE_RESET_START 1 377 #define BGE_RESET_STOP 2 378 static void bge_sig_post_reset(struct bge_softc *, int); 379 static void bge_sig_legacy(struct bge_softc *, int); 380 static void bge_sig_pre_reset(struct bge_softc *, int); 381 static int bge_reset(struct bge_softc *); 382 static void bge_link_upd(struct bge_softc *); 383 384 /* 385 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 386 * leak information to untrusted users. It is also known to cause alignment 387 * traps on certain architectures. 388 */ 389 #ifdef BGE_REGISTER_DEBUG 390 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 391 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 392 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 393 #endif 394 static void bge_add_sysctls(struct bge_softc *); 395 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 396 397 static device_method_t bge_methods[] = { 398 /* Device interface */ 399 DEVMETHOD(device_probe, bge_probe), 400 DEVMETHOD(device_attach, bge_attach), 401 DEVMETHOD(device_detach, bge_detach), 402 DEVMETHOD(device_shutdown, bge_shutdown), 403 DEVMETHOD(device_suspend, bge_suspend), 404 DEVMETHOD(device_resume, bge_resume), 405 406 /* bus interface */ 407 DEVMETHOD(bus_print_child, bus_generic_print_child), 408 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 409 410 /* MII interface */ 411 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 412 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 413 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 414 415 { 0, 0 } 416 }; 417 418 static driver_t bge_driver = { 419 "bge", 420 bge_methods, 421 sizeof(struct bge_softc) 422 }; 423 424 static devclass_t bge_devclass; 425 426 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 427 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 428 429 static int bge_allow_asf = 1; 430 431 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 432 433 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 434 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 435 "Allow ASF mode if available"); 436 437 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 438 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 439 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 440 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 441 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 442 443 static int 444 bge_has_eeprom(struct bge_softc *sc) 445 { 446 #ifdef __sparc64__ 447 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 448 device_t dev; 449 uint32_t subvendor; 450 451 dev = sc->bge_dev; 452 453 /* 454 * The on-board BGEs found in sun4u machines aren't fitted with 455 * an EEPROM which means that we have to obtain the MAC address 456 * via OFW and that some tests will always fail. We distinguish 457 * such BGEs by the subvendor ID, which also has to be obtained 458 * from OFW instead of the PCI configuration space as the latter 459 * indicates Broadcom as the subvendor of the netboot interface. 460 * For early Blade 1500 and 2500 we even have to check the OFW 461 * device path as the subvendor ID always defaults to Broadcom 462 * there. 463 */ 464 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 465 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 466 subvendor == SUN_VENDORID) 467 return (0); 468 memset(buf, 0, sizeof(buf)); 469 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 470 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 471 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 472 return (0); 473 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 474 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 475 return (0); 476 } 477 #endif 478 return (1); 479 } 480 481 static uint32_t 482 bge_readmem_ind(struct bge_softc *sc, int off) 483 { 484 device_t dev; 485 uint32_t val; 486 487 dev = sc->bge_dev; 488 489 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 490 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 491 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 492 return (val); 493 } 494 495 static void 496 bge_writemem_ind(struct bge_softc *sc, int off, int val) 497 { 498 device_t dev; 499 500 dev = sc->bge_dev; 501 502 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 503 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 504 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 505 } 506 507 #ifdef notdef 508 static uint32_t 509 bge_readreg_ind(struct bge_softc *sc, int off) 510 { 511 device_t dev; 512 513 dev = sc->bge_dev; 514 515 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 516 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 517 } 518 #endif 519 520 static void 521 bge_writereg_ind(struct bge_softc *sc, int off, int val) 522 { 523 device_t dev; 524 525 dev = sc->bge_dev; 526 527 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 528 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 529 } 530 531 static void 532 bge_writemem_direct(struct bge_softc *sc, int off, int val) 533 { 534 CSR_WRITE_4(sc, off, val); 535 } 536 537 /* 538 * Map a single buffer address. 539 */ 540 541 static void 542 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 543 { 544 struct bge_dmamap_arg *ctx; 545 546 if (error) 547 return; 548 549 ctx = arg; 550 551 if (nseg > ctx->bge_maxsegs) { 552 ctx->bge_maxsegs = 0; 553 return; 554 } 555 556 ctx->bge_busaddr = segs->ds_addr; 557 } 558 559 /* 560 * Read a byte of data stored in the EEPROM at address 'addr.' The 561 * BCM570x supports both the traditional bitbang interface and an 562 * auto access interface for reading the EEPROM. We use the auto 563 * access method. 564 */ 565 static uint8_t 566 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 567 { 568 int i; 569 uint32_t byte = 0; 570 571 /* 572 * Enable use of auto EEPROM access so we can avoid 573 * having to use the bitbang method. 574 */ 575 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 576 577 /* Reset the EEPROM, load the clock period. */ 578 CSR_WRITE_4(sc, BGE_EE_ADDR, 579 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 580 DELAY(20); 581 582 /* Issue the read EEPROM command. */ 583 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 584 585 /* Wait for completion */ 586 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 587 DELAY(10); 588 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 589 break; 590 } 591 592 if (i == BGE_TIMEOUT * 10) { 593 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 594 return (1); 595 } 596 597 /* Get result. */ 598 byte = CSR_READ_4(sc, BGE_EE_DATA); 599 600 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 601 602 return (0); 603 } 604 605 /* 606 * Read a sequence of bytes from the EEPROM. 607 */ 608 static int 609 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 610 { 611 int i, error = 0; 612 uint8_t byte = 0; 613 614 for (i = 0; i < cnt; i++) { 615 error = bge_eeprom_getbyte(sc, off + i, &byte); 616 if (error) 617 break; 618 *(dest + i) = byte; 619 } 620 621 return (error ? 1 : 0); 622 } 623 624 static int 625 bge_miibus_readreg(device_t dev, int phy, int reg) 626 { 627 struct bge_softc *sc; 628 uint32_t val, autopoll; 629 int i; 630 631 sc = device_get_softc(dev); 632 633 /* 634 * Broadcom's own driver always assumes the internal 635 * PHY is at GMII address 1. On some chips, the PHY responds 636 * to accesses at all addresses, which could cause us to 637 * bogusly attach the PHY 32 times at probe type. Always 638 * restricting the lookup to address 1 is simpler than 639 * trying to figure out which chips revisions should be 640 * special-cased. 641 */ 642 if (phy != 1) 643 return (0); 644 645 /* Reading with autopolling on may trigger PCI errors */ 646 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 647 if (autopoll & BGE_MIMODE_AUTOPOLL) { 648 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 649 DELAY(40); 650 } 651 652 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 653 BGE_MIPHY(phy) | BGE_MIREG(reg)); 654 655 for (i = 0; i < BGE_TIMEOUT; i++) { 656 DELAY(10); 657 val = CSR_READ_4(sc, BGE_MI_COMM); 658 if (!(val & BGE_MICOMM_BUSY)) 659 break; 660 } 661 662 if (i == BGE_TIMEOUT) { 663 device_printf(sc->bge_dev, "PHY read timed out\n"); 664 val = 0; 665 goto done; 666 } 667 668 val = CSR_READ_4(sc, BGE_MI_COMM); 669 670 done: 671 if (autopoll & BGE_MIMODE_AUTOPOLL) { 672 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 673 DELAY(40); 674 } 675 676 if (val & BGE_MICOMM_READFAIL) 677 return (0); 678 679 return (val & 0xFFFF); 680 } 681 682 static int 683 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 684 { 685 struct bge_softc *sc; 686 uint32_t autopoll; 687 int i; 688 689 sc = device_get_softc(dev); 690 691 /* Reading with autopolling on may trigger PCI errors */ 692 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 693 if (autopoll & BGE_MIMODE_AUTOPOLL) { 694 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 695 DELAY(40); 696 } 697 698 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 699 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 700 701 for (i = 0; i < BGE_TIMEOUT; i++) { 702 DELAY(10); 703 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 704 break; 705 } 706 707 if (i == BGE_TIMEOUT) { 708 device_printf(sc->bge_dev, "PHY write timed out\n"); 709 return (0); 710 } 711 712 if (autopoll & BGE_MIMODE_AUTOPOLL) { 713 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 714 DELAY(40); 715 } 716 717 return (0); 718 } 719 720 static void 721 bge_miibus_statchg(device_t dev) 722 { 723 struct bge_softc *sc; 724 struct mii_data *mii; 725 sc = device_get_softc(dev); 726 mii = device_get_softc(sc->bge_miibus); 727 728 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 729 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 730 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 731 else 732 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 733 734 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 735 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 736 else 737 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 738 } 739 740 /* 741 * Intialize a standard receive ring descriptor. 742 */ 743 static int 744 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 745 { 746 struct mbuf *m_new = NULL; 747 struct bge_rx_bd *r; 748 struct bge_dmamap_arg ctx; 749 int error; 750 751 if (m == NULL) { 752 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 753 if (m_new == NULL) 754 return (ENOBUFS); 755 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 756 } else { 757 m_new = m; 758 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 759 m_new->m_data = m_new->m_ext.ext_buf; 760 } 761 762 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 763 m_adj(m_new, ETHER_ALIGN); 764 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 765 r = &sc->bge_ldata.bge_rx_std_ring[i]; 766 ctx.bge_maxsegs = 1; 767 ctx.sc = sc; 768 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 769 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 770 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 771 if (error || ctx.bge_maxsegs == 0) { 772 if (m == NULL) { 773 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 774 m_freem(m_new); 775 } 776 return (ENOMEM); 777 } 778 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 779 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 780 r->bge_flags = BGE_RXBDFLAG_END; 781 r->bge_len = m_new->m_len; 782 r->bge_idx = i; 783 784 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 785 sc->bge_cdata.bge_rx_std_dmamap[i], 786 BUS_DMASYNC_PREREAD); 787 788 return (0); 789 } 790 791 /* 792 * Initialize a jumbo receive ring descriptor. This allocates 793 * a jumbo buffer from the pool managed internally by the driver. 794 */ 795 static int 796 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 797 { 798 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 799 struct bge_extrx_bd *r; 800 struct mbuf *m_new = NULL; 801 int nsegs; 802 int error; 803 804 if (m == NULL) { 805 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 806 if (m_new == NULL) 807 return (ENOBUFS); 808 809 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 810 if (!(m_new->m_flags & M_EXT)) { 811 m_freem(m_new); 812 return (ENOBUFS); 813 } 814 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 815 } else { 816 m_new = m; 817 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 818 m_new->m_data = m_new->m_ext.ext_buf; 819 } 820 821 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 822 m_adj(m_new, ETHER_ALIGN); 823 824 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 825 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 826 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 827 if (error) { 828 if (m == NULL) 829 m_freem(m_new); 830 return (error); 831 } 832 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 833 834 /* 835 * Fill in the extended RX buffer descriptor. 836 */ 837 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 838 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 839 r->bge_idx = i; 840 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 841 switch (nsegs) { 842 case 4: 843 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 844 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 845 r->bge_len3 = segs[3].ds_len; 846 case 3: 847 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 848 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 849 r->bge_len2 = segs[2].ds_len; 850 case 2: 851 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 852 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 853 r->bge_len1 = segs[1].ds_len; 854 case 1: 855 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 856 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 857 r->bge_len0 = segs[0].ds_len; 858 break; 859 default: 860 panic("%s: %d segments\n", __func__, nsegs); 861 } 862 863 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 864 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 865 BUS_DMASYNC_PREREAD); 866 867 return (0); 868 } 869 870 /* 871 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 872 * that's 1MB or memory, which is a lot. For now, we fill only the first 873 * 256 ring entries and hope that our CPU is fast enough to keep up with 874 * the NIC. 875 */ 876 static int 877 bge_init_rx_ring_std(struct bge_softc *sc) 878 { 879 int i; 880 881 for (i = 0; i < BGE_SSLOTS; i++) { 882 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 883 return (ENOBUFS); 884 }; 885 886 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 887 sc->bge_cdata.bge_rx_std_ring_map, 888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 889 890 sc->bge_std = i - 1; 891 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 892 893 return (0); 894 } 895 896 static void 897 bge_free_rx_ring_std(struct bge_softc *sc) 898 { 899 int i; 900 901 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 902 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 903 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 904 sc->bge_cdata.bge_rx_std_dmamap[i], 905 BUS_DMASYNC_POSTREAD); 906 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 907 sc->bge_cdata.bge_rx_std_dmamap[i]); 908 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 909 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 910 } 911 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 912 sizeof(struct bge_rx_bd)); 913 } 914 } 915 916 static int 917 bge_init_rx_ring_jumbo(struct bge_softc *sc) 918 { 919 struct bge_rcb *rcb; 920 int i; 921 922 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 923 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 924 return (ENOBUFS); 925 }; 926 927 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 928 sc->bge_cdata.bge_rx_jumbo_ring_map, 929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 930 931 sc->bge_jumbo = i - 1; 932 933 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 934 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 935 BGE_RCB_FLAG_USE_EXT_RX_BD); 936 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 937 938 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 939 940 return (0); 941 } 942 943 static void 944 bge_free_rx_ring_jumbo(struct bge_softc *sc) 945 { 946 int i; 947 948 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 949 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 950 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 951 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 952 BUS_DMASYNC_POSTREAD); 953 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 954 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 955 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 956 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 957 } 958 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 959 sizeof(struct bge_extrx_bd)); 960 } 961 } 962 963 static void 964 bge_free_tx_ring(struct bge_softc *sc) 965 { 966 int i; 967 968 if (sc->bge_ldata.bge_tx_ring == NULL) 969 return; 970 971 for (i = 0; i < BGE_TX_RING_CNT; i++) { 972 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 973 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 974 sc->bge_cdata.bge_tx_dmamap[i], 975 BUS_DMASYNC_POSTWRITE); 976 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 977 sc->bge_cdata.bge_tx_dmamap[i]); 978 m_freem(sc->bge_cdata.bge_tx_chain[i]); 979 sc->bge_cdata.bge_tx_chain[i] = NULL; 980 } 981 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 982 sizeof(struct bge_tx_bd)); 983 } 984 } 985 986 static int 987 bge_init_tx_ring(struct bge_softc *sc) 988 { 989 sc->bge_txcnt = 0; 990 sc->bge_tx_saved_considx = 0; 991 992 /* Initialize transmit producer index for host-memory send ring. */ 993 sc->bge_tx_prodidx = 0; 994 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 995 996 /* 5700 b2 errata */ 997 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 998 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 999 1000 /* NIC-memory send ring not used; initialize to zero. */ 1001 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1002 /* 5700 b2 errata */ 1003 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1004 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1005 1006 return (0); 1007 } 1008 1009 static void 1010 bge_setpromisc(struct bge_softc *sc) 1011 { 1012 struct ifnet *ifp; 1013 1014 BGE_LOCK_ASSERT(sc); 1015 1016 ifp = sc->bge_ifp; 1017 1018 /* Enable or disable promiscuous mode as needed. */ 1019 if (ifp->if_flags & IFF_PROMISC) 1020 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1021 else 1022 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1023 } 1024 1025 static void 1026 bge_setmulti(struct bge_softc *sc) 1027 { 1028 struct ifnet *ifp; 1029 struct ifmultiaddr *ifma; 1030 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1031 int h, i; 1032 1033 BGE_LOCK_ASSERT(sc); 1034 1035 ifp = sc->bge_ifp; 1036 1037 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1038 for (i = 0; i < 4; i++) 1039 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1040 return; 1041 } 1042 1043 /* First, zot all the existing filters. */ 1044 for (i = 0; i < 4; i++) 1045 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1046 1047 /* Now program new ones. */ 1048 IF_ADDR_LOCK(ifp); 1049 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1050 if (ifma->ifma_addr->sa_family != AF_LINK) 1051 continue; 1052 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1053 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1054 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1055 } 1056 IF_ADDR_UNLOCK(ifp); 1057 1058 for (i = 0; i < 4; i++) 1059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1060 } 1061 1062 static void 1063 bge_setvlan(struct bge_softc *sc) 1064 { 1065 struct ifnet *ifp; 1066 1067 BGE_LOCK_ASSERT(sc); 1068 1069 ifp = sc->bge_ifp; 1070 1071 /* Enable or disable VLAN tag stripping as needed. */ 1072 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1073 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1074 else 1075 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1076 } 1077 1078 static void 1079 bge_sig_pre_reset(sc, type) 1080 struct bge_softc *sc; 1081 int type; 1082 { 1083 /* 1084 * Some chips don't like this so only do this if ASF is enabled 1085 */ 1086 if (sc->bge_asf_mode) 1087 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1088 1089 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1090 switch (type) { 1091 case BGE_RESET_START: 1092 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1093 break; 1094 case BGE_RESET_STOP: 1095 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1096 break; 1097 } 1098 } 1099 } 1100 1101 static void 1102 bge_sig_post_reset(sc, type) 1103 struct bge_softc *sc; 1104 int type; 1105 { 1106 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1107 switch (type) { 1108 case BGE_RESET_START: 1109 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1110 /* START DONE */ 1111 break; 1112 case BGE_RESET_STOP: 1113 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1114 break; 1115 } 1116 } 1117 } 1118 1119 static void 1120 bge_sig_legacy(sc, type) 1121 struct bge_softc *sc; 1122 int type; 1123 { 1124 if (sc->bge_asf_mode) { 1125 switch (type) { 1126 case BGE_RESET_START: 1127 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1128 break; 1129 case BGE_RESET_STOP: 1130 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1131 break; 1132 } 1133 } 1134 } 1135 1136 void bge_stop_fw(struct bge_softc *); 1137 void 1138 bge_stop_fw(sc) 1139 struct bge_softc *sc; 1140 { 1141 int i; 1142 1143 if (sc->bge_asf_mode) { 1144 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1145 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1146 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1147 1148 for (i = 0; i < 100; i++ ) { 1149 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1150 break; 1151 DELAY(10); 1152 } 1153 } 1154 } 1155 1156 /* 1157 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1158 * self-test results. 1159 */ 1160 static int 1161 bge_chipinit(struct bge_softc *sc) 1162 { 1163 uint32_t dma_rw_ctl; 1164 int i; 1165 1166 /* Set endianness before we access any non-PCI registers. */ 1167 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1168 1169 /* 1170 * Check the 'ROM failed' bit on the RX CPU to see if 1171 * self-tests passed. Skip this check when there's no 1172 * EEPROM fitted, since in that case it will always 1173 * fail. 1174 */ 1175 if ((sc->bge_flags & BGE_FLAG_EEPROM) && 1176 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1177 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1178 return (ENODEV); 1179 } 1180 1181 /* Clear the MAC control register */ 1182 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1183 1184 /* 1185 * Clear the MAC statistics block in the NIC's 1186 * internal memory. 1187 */ 1188 for (i = BGE_STATS_BLOCK; 1189 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1190 BGE_MEMWIN_WRITE(sc, i, 0); 1191 1192 for (i = BGE_STATUS_BLOCK; 1193 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1194 BGE_MEMWIN_WRITE(sc, i, 0); 1195 1196 /* 1197 * Set up the PCI DMA control register. 1198 */ 1199 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1200 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1201 if (sc->bge_flags & BGE_FLAG_PCIE) { 1202 /* Read watermark not used, 128 bytes for write. */ 1203 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1204 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1205 if (BGE_IS_5714_FAMILY(sc)) { 1206 /* 256 bytes for read and write. */ 1207 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1208 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1209 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1210 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1211 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1212 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1213 /* 1536 bytes for read, 384 bytes for write. */ 1214 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1215 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1216 } else { 1217 /* 384 bytes for read and write. */ 1218 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1219 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1220 0x0F; 1221 } 1222 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1223 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1224 uint32_t tmp; 1225 1226 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1227 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1228 if (tmp == 6 || tmp == 7) 1229 dma_rw_ctl |= 1230 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1231 1232 /* Set PCI-X DMA write workaround. */ 1233 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1234 } 1235 } else { 1236 /* Conventional PCI bus: 256 bytes for read and write. */ 1237 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1238 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1239 1240 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1241 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1242 dma_rw_ctl |= 0x0F; 1243 } 1244 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1245 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1246 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1247 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1248 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1249 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1250 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1251 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1252 1253 /* 1254 * Set up general mode register. 1255 */ 1256 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1257 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1258 BGE_MODECTL_TX_NO_PHDR_CSUM); 1259 1260 /* 1261 * Tell the firmware the driver is running 1262 */ 1263 if (sc->bge_asf_mode & ASF_STACKUP) 1264 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1265 1266 /* 1267 * Disable memory write invalidate. Apparently it is not supported 1268 * properly by these devices. 1269 */ 1270 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1271 1272 /* Set the timer prescaler (always 66Mhz) */ 1273 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1274 1275 return (0); 1276 } 1277 1278 static int 1279 bge_blockinit(struct bge_softc *sc) 1280 { 1281 struct bge_rcb *rcb; 1282 bus_size_t vrcb; 1283 bge_hostaddr taddr; 1284 uint32_t val; 1285 int i; 1286 1287 /* 1288 * Initialize the memory window pointer register so that 1289 * we can access the first 32K of internal NIC RAM. This will 1290 * allow us to set up the TX send ring RCBs and the RX return 1291 * ring RCBs, plus other things which live in NIC memory. 1292 */ 1293 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1294 1295 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1296 1297 if (!(BGE_IS_5705_PLUS(sc))) { 1298 /* Configure mbuf memory pool */ 1299 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1300 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1301 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1302 else 1303 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1304 1305 /* Configure DMA resource pool */ 1306 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1307 BGE_DMA_DESCRIPTORS); 1308 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1309 } 1310 1311 /* Configure mbuf pool watermarks */ 1312 if (!(BGE_IS_5705_PLUS(sc))) { 1313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1314 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1315 } else { 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1318 } 1319 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1320 1321 /* Configure DMA resource watermarks */ 1322 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1323 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1324 1325 /* Enable buffer manager */ 1326 if (!(BGE_IS_5705_PLUS(sc))) { 1327 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1328 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1329 1330 /* Poll for buffer manager start indication */ 1331 for (i = 0; i < BGE_TIMEOUT; i++) { 1332 DELAY(10); 1333 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1334 break; 1335 } 1336 1337 if (i == BGE_TIMEOUT) { 1338 device_printf(sc->bge_dev, 1339 "buffer manager failed to start\n"); 1340 return (ENXIO); 1341 } 1342 } 1343 1344 /* Enable flow-through queues */ 1345 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1346 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1347 1348 /* Wait until queue initialization is complete */ 1349 for (i = 0; i < BGE_TIMEOUT; i++) { 1350 DELAY(10); 1351 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1352 break; 1353 } 1354 1355 if (i == BGE_TIMEOUT) { 1356 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1357 return (ENXIO); 1358 } 1359 1360 /* Initialize the standard RX ring control block */ 1361 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1362 rcb->bge_hostaddr.bge_addr_lo = 1363 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1364 rcb->bge_hostaddr.bge_addr_hi = 1365 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1366 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1367 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1368 if (BGE_IS_5705_PLUS(sc)) 1369 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1370 else 1371 rcb->bge_maxlen_flags = 1372 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1373 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1374 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1375 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1376 1377 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1378 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1379 1380 /* 1381 * Initialize the jumbo RX ring control block 1382 * We set the 'ring disabled' bit in the flags 1383 * field until we're actually ready to start 1384 * using this ring (i.e. once we set the MTU 1385 * high enough to require it). 1386 */ 1387 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1388 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1389 1390 rcb->bge_hostaddr.bge_addr_lo = 1391 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1392 rcb->bge_hostaddr.bge_addr_hi = 1393 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1394 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1395 sc->bge_cdata.bge_rx_jumbo_ring_map, 1396 BUS_DMASYNC_PREREAD); 1397 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1398 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1399 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1400 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1401 rcb->bge_hostaddr.bge_addr_hi); 1402 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1403 rcb->bge_hostaddr.bge_addr_lo); 1404 1405 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1406 rcb->bge_maxlen_flags); 1407 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1408 1409 /* Set up dummy disabled mini ring RCB */ 1410 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1411 rcb->bge_maxlen_flags = 1412 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1413 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1414 rcb->bge_maxlen_flags); 1415 } 1416 1417 /* 1418 * Set the BD ring replentish thresholds. The recommended 1419 * values are 1/8th the number of descriptors allocated to 1420 * each ring. 1421 * XXX The 5754 requires a lower threshold, so it might be a 1422 * requirement of all 575x family chips. The Linux driver sets 1423 * the lower threshold for all 5705 family chips as well, but there 1424 * are reports that it might not need to be so strict. 1425 */ 1426 if (BGE_IS_5705_PLUS(sc)) 1427 val = 8; 1428 else 1429 val = BGE_STD_RX_RING_CNT / 8; 1430 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1431 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1432 1433 /* 1434 * Disable all unused send rings by setting the 'ring disabled' 1435 * bit in the flags field of all the TX send ring control blocks. 1436 * These are located in NIC memory. 1437 */ 1438 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1439 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1440 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1441 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1442 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1443 vrcb += sizeof(struct bge_rcb); 1444 } 1445 1446 /* Configure TX RCB 0 (we use only the first ring) */ 1447 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1448 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1449 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1450 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1451 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1452 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1453 if (!(BGE_IS_5705_PLUS(sc))) 1454 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1455 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1456 1457 /* Disable all unused RX return rings */ 1458 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1459 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1460 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1461 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1462 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1463 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1464 BGE_RCB_FLAG_RING_DISABLED)); 1465 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1466 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1467 (i * (sizeof(uint64_t))), 0); 1468 vrcb += sizeof(struct bge_rcb); 1469 } 1470 1471 /* Initialize RX ring indexes */ 1472 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1473 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1474 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1475 1476 /* 1477 * Set up RX return ring 0 1478 * Note that the NIC address for RX return rings is 0x00000000. 1479 * The return rings live entirely within the host, so the 1480 * nicaddr field in the RCB isn't used. 1481 */ 1482 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1483 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1484 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1485 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1486 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1487 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1488 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1489 1490 /* Set random backoff seed for TX */ 1491 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1492 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1493 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1494 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1495 BGE_TX_BACKOFF_SEED_MASK); 1496 1497 /* Set inter-packet gap */ 1498 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1499 1500 /* 1501 * Specify which ring to use for packets that don't match 1502 * any RX rules. 1503 */ 1504 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1505 1506 /* 1507 * Configure number of RX lists. One interrupt distribution 1508 * list, sixteen active lists, one bad frames class. 1509 */ 1510 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1511 1512 /* Inialize RX list placement stats mask. */ 1513 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1514 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1515 1516 /* Disable host coalescing until we get it set up */ 1517 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1518 1519 /* Poll to make sure it's shut down. */ 1520 for (i = 0; i < BGE_TIMEOUT; i++) { 1521 DELAY(10); 1522 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1523 break; 1524 } 1525 1526 if (i == BGE_TIMEOUT) { 1527 device_printf(sc->bge_dev, 1528 "host coalescing engine failed to idle\n"); 1529 return (ENXIO); 1530 } 1531 1532 /* Set up host coalescing defaults */ 1533 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1534 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1535 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1536 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1537 if (!(BGE_IS_5705_PLUS(sc))) { 1538 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1539 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1540 } 1541 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1542 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1543 1544 /* Set up address of statistics block */ 1545 if (!(BGE_IS_5705_PLUS(sc))) { 1546 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1547 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1548 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1549 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1550 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1551 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1552 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1553 } 1554 1555 /* Set up address of status block */ 1556 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1557 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1558 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1559 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1560 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1561 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1562 1563 /* Turn on host coalescing state machine */ 1564 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1565 1566 /* Turn on RX BD completion state machine and enable attentions */ 1567 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1568 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1569 1570 /* Turn on RX list placement state machine */ 1571 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1572 1573 /* Turn on RX list selector state machine. */ 1574 if (!(BGE_IS_5705_PLUS(sc))) 1575 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1576 1577 /* Turn on DMA, clear stats */ 1578 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1579 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1580 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1581 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1582 ((sc->bge_flags & BGE_FLAG_TBI) ? 1583 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1584 1585 /* Set misc. local control, enable interrupts on attentions */ 1586 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1587 1588 #ifdef notdef 1589 /* Assert GPIO pins for PHY reset */ 1590 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1591 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1592 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1593 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1594 #endif 1595 1596 /* Turn on DMA completion state machine */ 1597 if (!(BGE_IS_5705_PLUS(sc))) 1598 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1599 1600 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1601 1602 /* Enable host coalescing bug fix. */ 1603 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1604 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1605 val |= 1 << 29; 1606 1607 /* Turn on write DMA state machine */ 1608 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1609 1610 /* Turn on read DMA state machine */ 1611 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1612 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1613 1614 /* Turn on RX data completion state machine */ 1615 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1616 1617 /* Turn on RX BD initiator state machine */ 1618 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1619 1620 /* Turn on RX data and RX BD initiator state machine */ 1621 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1622 1623 /* Turn on Mbuf cluster free state machine */ 1624 if (!(BGE_IS_5705_PLUS(sc))) 1625 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1626 1627 /* Turn on send BD completion state machine */ 1628 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1629 1630 /* Turn on send data completion state machine */ 1631 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1632 1633 /* Turn on send data initiator state machine */ 1634 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1635 1636 /* Turn on send BD initiator state machine */ 1637 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1638 1639 /* Turn on send BD selector state machine */ 1640 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1641 1642 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1643 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1644 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1645 1646 /* ack/clear link change events */ 1647 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1648 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1649 BGE_MACSTAT_LINK_CHANGED); 1650 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1651 1652 /* Enable PHY auto polling (for MII/GMII only) */ 1653 if (sc->bge_flags & BGE_FLAG_TBI) { 1654 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1655 } else { 1656 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1657 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1658 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1659 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1660 BGE_EVTENB_MI_INTERRUPT); 1661 } 1662 1663 /* 1664 * Clear any pending link state attention. 1665 * Otherwise some link state change events may be lost until attention 1666 * is cleared by bge_intr() -> bge_link_upd() sequence. 1667 * It's not necessary on newer BCM chips - perhaps enabling link 1668 * state change attentions implies clearing pending attention. 1669 */ 1670 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1671 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1672 BGE_MACSTAT_LINK_CHANGED); 1673 1674 /* Enable link state change attentions. */ 1675 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1676 1677 return (0); 1678 } 1679 1680 const struct bge_revision * 1681 bge_lookup_rev(uint32_t chipid) 1682 { 1683 const struct bge_revision *br; 1684 1685 for (br = bge_revisions; br->br_name != NULL; br++) { 1686 if (br->br_chipid == chipid) 1687 return (br); 1688 } 1689 1690 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1691 if (br->br_chipid == BGE_ASICREV(chipid)) 1692 return (br); 1693 } 1694 1695 return (NULL); 1696 } 1697 1698 const struct bge_vendor * 1699 bge_lookup_vendor(uint16_t vid) 1700 { 1701 const struct bge_vendor *v; 1702 1703 for (v = bge_vendors; v->v_name != NULL; v++) 1704 if (v->v_id == vid) 1705 return (v); 1706 1707 panic("%s: unknown vendor %d", __func__, vid); 1708 return (NULL); 1709 } 1710 1711 /* 1712 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1713 * against our list and return its name if we find a match. 1714 * 1715 * Note that since the Broadcom controller contains VPD support, we 1716 * try to get the device name string from the controller itself instead 1717 * of the compiled-in string. It guarantees we'll always announce the 1718 * right product name. We fall back to the compiled-in string when 1719 * VPD is unavailable or corrupt. 1720 */ 1721 static int 1722 bge_probe(device_t dev) 1723 { 1724 struct bge_type *t = bge_devs; 1725 struct bge_softc *sc = device_get_softc(dev); 1726 uint16_t vid, did; 1727 1728 sc->bge_dev = dev; 1729 vid = pci_get_vendor(dev); 1730 did = pci_get_device(dev); 1731 while(t->bge_vid != 0) { 1732 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1733 char model[64], buf[96]; 1734 const struct bge_revision *br; 1735 const struct bge_vendor *v; 1736 uint32_t id; 1737 1738 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1739 BGE_PCIMISCCTL_ASICREV; 1740 br = bge_lookup_rev(id); 1741 v = bge_lookup_vendor(vid); 1742 { 1743 #if __FreeBSD_version > 700024 1744 const char *pname; 1745 1746 if (pci_get_vpd_ident(dev, &pname) == 0) 1747 snprintf(model, 64, "%s", pname); 1748 else 1749 #endif 1750 snprintf(model, 64, "%s %s", 1751 v->v_name, 1752 br != NULL ? br->br_name : 1753 "NetXtreme Ethernet Controller"); 1754 } 1755 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1756 br != NULL ? "" : "unknown ", id >> 16); 1757 device_set_desc_copy(dev, buf); 1758 if (pci_get_subvendor(dev) == DELL_VENDORID) 1759 sc->bge_flags |= BGE_FLAG_NO_3LED; 1760 if (did == BCOM_DEVICEID_BCM5755M) 1761 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1762 return (0); 1763 } 1764 t++; 1765 } 1766 1767 return (ENXIO); 1768 } 1769 1770 static void 1771 bge_dma_free(struct bge_softc *sc) 1772 { 1773 int i; 1774 1775 /* Destroy DMA maps for RX buffers. */ 1776 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1777 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1778 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1779 sc->bge_cdata.bge_rx_std_dmamap[i]); 1780 } 1781 1782 /* Destroy DMA maps for jumbo RX buffers. */ 1783 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1784 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1785 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1786 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1787 } 1788 1789 /* Destroy DMA maps for TX buffers. */ 1790 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1791 if (sc->bge_cdata.bge_tx_dmamap[i]) 1792 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1793 sc->bge_cdata.bge_tx_dmamap[i]); 1794 } 1795 1796 if (sc->bge_cdata.bge_mtag) 1797 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1798 1799 1800 /* Destroy standard RX ring. */ 1801 if (sc->bge_cdata.bge_rx_std_ring_map) 1802 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1803 sc->bge_cdata.bge_rx_std_ring_map); 1804 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1805 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1806 sc->bge_ldata.bge_rx_std_ring, 1807 sc->bge_cdata.bge_rx_std_ring_map); 1808 1809 if (sc->bge_cdata.bge_rx_std_ring_tag) 1810 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1811 1812 /* Destroy jumbo RX ring. */ 1813 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1814 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1815 sc->bge_cdata.bge_rx_jumbo_ring_map); 1816 1817 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1818 sc->bge_ldata.bge_rx_jumbo_ring) 1819 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1820 sc->bge_ldata.bge_rx_jumbo_ring, 1821 sc->bge_cdata.bge_rx_jumbo_ring_map); 1822 1823 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1824 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1825 1826 /* Destroy RX return ring. */ 1827 if (sc->bge_cdata.bge_rx_return_ring_map) 1828 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1829 sc->bge_cdata.bge_rx_return_ring_map); 1830 1831 if (sc->bge_cdata.bge_rx_return_ring_map && 1832 sc->bge_ldata.bge_rx_return_ring) 1833 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1834 sc->bge_ldata.bge_rx_return_ring, 1835 sc->bge_cdata.bge_rx_return_ring_map); 1836 1837 if (sc->bge_cdata.bge_rx_return_ring_tag) 1838 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1839 1840 /* Destroy TX ring. */ 1841 if (sc->bge_cdata.bge_tx_ring_map) 1842 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1843 sc->bge_cdata.bge_tx_ring_map); 1844 1845 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1846 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1847 sc->bge_ldata.bge_tx_ring, 1848 sc->bge_cdata.bge_tx_ring_map); 1849 1850 if (sc->bge_cdata.bge_tx_ring_tag) 1851 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1852 1853 /* Destroy status block. */ 1854 if (sc->bge_cdata.bge_status_map) 1855 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1856 sc->bge_cdata.bge_status_map); 1857 1858 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1859 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1860 sc->bge_ldata.bge_status_block, 1861 sc->bge_cdata.bge_status_map); 1862 1863 if (sc->bge_cdata.bge_status_tag) 1864 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1865 1866 /* Destroy statistics block. */ 1867 if (sc->bge_cdata.bge_stats_map) 1868 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1869 sc->bge_cdata.bge_stats_map); 1870 1871 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 1872 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1873 sc->bge_ldata.bge_stats, 1874 sc->bge_cdata.bge_stats_map); 1875 1876 if (sc->bge_cdata.bge_stats_tag) 1877 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1878 1879 /* Destroy the parent tag. */ 1880 if (sc->bge_cdata.bge_parent_tag) 1881 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1882 } 1883 1884 static int 1885 bge_dma_alloc(device_t dev) 1886 { 1887 struct bge_dmamap_arg ctx; 1888 struct bge_softc *sc; 1889 int i, error; 1890 1891 sc = device_get_softc(dev); 1892 1893 /* 1894 * Allocate the parent bus DMA tag appropriate for PCI. 1895 */ 1896 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1897 1, 0, /* alignment, boundary */ 1898 BUS_SPACE_MAXADDR, /* lowaddr */ 1899 BUS_SPACE_MAXADDR, /* highaddr */ 1900 NULL, NULL, /* filter, filterarg */ 1901 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1902 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1903 0, /* flags */ 1904 NULL, NULL, /* lockfunc, lockarg */ 1905 &sc->bge_cdata.bge_parent_tag); 1906 1907 if (error != 0) { 1908 device_printf(sc->bge_dev, 1909 "could not allocate parent dma tag\n"); 1910 return (ENOMEM); 1911 } 1912 1913 /* 1914 * Create tag for RX mbufs. 1915 */ 1916 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1917 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1918 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 1919 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 1920 1921 if (error) { 1922 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1923 return (ENOMEM); 1924 } 1925 1926 /* Create DMA maps for RX buffers. */ 1927 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1928 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1929 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1930 if (error) { 1931 device_printf(sc->bge_dev, 1932 "can't create DMA map for RX\n"); 1933 return (ENOMEM); 1934 } 1935 } 1936 1937 /* Create DMA maps for TX buffers. */ 1938 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1939 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1940 &sc->bge_cdata.bge_tx_dmamap[i]); 1941 if (error) { 1942 device_printf(sc->bge_dev, 1943 "can't create DMA map for RX\n"); 1944 return (ENOMEM); 1945 } 1946 } 1947 1948 /* Create tag for standard RX ring. */ 1949 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1950 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1951 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1952 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1953 1954 if (error) { 1955 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1956 return (ENOMEM); 1957 } 1958 1959 /* Allocate DMA'able memory for standard RX ring. */ 1960 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1961 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1962 &sc->bge_cdata.bge_rx_std_ring_map); 1963 if (error) 1964 return (ENOMEM); 1965 1966 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1967 1968 /* Load the address of the standard RX ring. */ 1969 ctx.bge_maxsegs = 1; 1970 ctx.sc = sc; 1971 1972 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1973 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1974 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1975 1976 if (error) 1977 return (ENOMEM); 1978 1979 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1980 1981 /* Create tags for jumbo mbufs. */ 1982 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1983 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1984 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1985 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 1986 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 1987 if (error) { 1988 device_printf(sc->bge_dev, 1989 "could not allocate jumbo dma tag\n"); 1990 return (ENOMEM); 1991 } 1992 1993 /* Create tag for jumbo RX ring. */ 1994 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1995 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1996 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 1997 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 1998 1999 if (error) { 2000 device_printf(sc->bge_dev, 2001 "could not allocate jumbo ring dma tag\n"); 2002 return (ENOMEM); 2003 } 2004 2005 /* Allocate DMA'able memory for jumbo RX ring. */ 2006 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2007 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2008 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2009 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2010 if (error) 2011 return (ENOMEM); 2012 2013 /* Load the address of the jumbo RX ring. */ 2014 ctx.bge_maxsegs = 1; 2015 ctx.sc = sc; 2016 2017 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2018 sc->bge_cdata.bge_rx_jumbo_ring_map, 2019 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2020 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2021 2022 if (error) 2023 return (ENOMEM); 2024 2025 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2026 2027 /* Create DMA maps for jumbo RX buffers. */ 2028 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2029 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2030 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2031 if (error) { 2032 device_printf(sc->bge_dev, 2033 "can't create DMA map for jumbo RX\n"); 2034 return (ENOMEM); 2035 } 2036 } 2037 2038 } 2039 2040 /* Create tag for RX return ring. */ 2041 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2042 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2043 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2044 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2045 2046 if (error) { 2047 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2048 return (ENOMEM); 2049 } 2050 2051 /* Allocate DMA'able memory for RX return ring. */ 2052 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2053 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2054 &sc->bge_cdata.bge_rx_return_ring_map); 2055 if (error) 2056 return (ENOMEM); 2057 2058 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2059 BGE_RX_RTN_RING_SZ(sc)); 2060 2061 /* Load the address of the RX return ring. */ 2062 ctx.bge_maxsegs = 1; 2063 ctx.sc = sc; 2064 2065 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2066 sc->bge_cdata.bge_rx_return_ring_map, 2067 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2068 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2069 2070 if (error) 2071 return (ENOMEM); 2072 2073 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2074 2075 /* Create tag for TX ring. */ 2076 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2077 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2078 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2079 &sc->bge_cdata.bge_tx_ring_tag); 2080 2081 if (error) { 2082 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2083 return (ENOMEM); 2084 } 2085 2086 /* Allocate DMA'able memory for TX ring. */ 2087 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2088 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2089 &sc->bge_cdata.bge_tx_ring_map); 2090 if (error) 2091 return (ENOMEM); 2092 2093 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2094 2095 /* Load the address of the TX ring. */ 2096 ctx.bge_maxsegs = 1; 2097 ctx.sc = sc; 2098 2099 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2100 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2101 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2102 2103 if (error) 2104 return (ENOMEM); 2105 2106 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2107 2108 /* Create tag for status block. */ 2109 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2110 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2111 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2112 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2113 2114 if (error) { 2115 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2116 return (ENOMEM); 2117 } 2118 2119 /* Allocate DMA'able memory for status block. */ 2120 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2121 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2122 &sc->bge_cdata.bge_status_map); 2123 if (error) 2124 return (ENOMEM); 2125 2126 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2127 2128 /* Load the address of the status block. */ 2129 ctx.sc = sc; 2130 ctx.bge_maxsegs = 1; 2131 2132 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2133 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2134 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2135 2136 if (error) 2137 return (ENOMEM); 2138 2139 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2140 2141 /* Create tag for statistics block. */ 2142 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2143 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2144 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2145 &sc->bge_cdata.bge_stats_tag); 2146 2147 if (error) { 2148 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2149 return (ENOMEM); 2150 } 2151 2152 /* Allocate DMA'able memory for statistics block. */ 2153 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2154 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2155 &sc->bge_cdata.bge_stats_map); 2156 if (error) 2157 return (ENOMEM); 2158 2159 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2160 2161 /* Load the address of the statstics block. */ 2162 ctx.sc = sc; 2163 ctx.bge_maxsegs = 1; 2164 2165 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2166 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2167 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2168 2169 if (error) 2170 return (ENOMEM); 2171 2172 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2173 2174 return (0); 2175 } 2176 2177 #if __FreeBSD_version > 602105 2178 /* 2179 * Return true if this device has more than one port. 2180 */ 2181 static int 2182 bge_has_multiple_ports(struct bge_softc *sc) 2183 { 2184 device_t dev = sc->bge_dev; 2185 u_int b, d, f, fscan, s; 2186 2187 d = pci_get_domain(dev); 2188 b = pci_get_bus(dev); 2189 s = pci_get_slot(dev); 2190 f = pci_get_function(dev); 2191 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2192 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2193 return (1); 2194 return (0); 2195 } 2196 2197 /* 2198 * Return true if MSI can be used with this device. 2199 */ 2200 static int 2201 bge_can_use_msi(struct bge_softc *sc) 2202 { 2203 int can_use_msi = 0; 2204 2205 switch (sc->bge_asicrev) { 2206 case BGE_ASICREV_BCM5714: 2207 /* 2208 * Apparently, MSI doesn't work when this chip is configured 2209 * in single-port mode. 2210 */ 2211 if (bge_has_multiple_ports(sc)) 2212 can_use_msi = 1; 2213 break; 2214 case BGE_ASICREV_BCM5750: 2215 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2216 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2217 can_use_msi = 1; 2218 break; 2219 case BGE_ASICREV_BCM5752: 2220 case BGE_ASICREV_BCM5780: 2221 can_use_msi = 1; 2222 break; 2223 } 2224 return (can_use_msi); 2225 } 2226 #endif 2227 2228 static int 2229 bge_attach(device_t dev) 2230 { 2231 struct ifnet *ifp; 2232 struct bge_softc *sc; 2233 uint32_t hwcfg = 0; 2234 uint32_t mac_tmp = 0; 2235 u_char eaddr[ETHER_ADDR_LEN]; 2236 int error, reg, rid, trys; 2237 2238 sc = device_get_softc(dev); 2239 sc->bge_dev = dev; 2240 2241 /* 2242 * Map control/status registers. 2243 */ 2244 pci_enable_busmaster(dev); 2245 2246 rid = BGE_PCI_BAR0; 2247 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2248 RF_ACTIVE | PCI_RF_DENSE); 2249 2250 if (sc->bge_res == NULL) { 2251 device_printf (sc->bge_dev, "couldn't map memory\n"); 2252 error = ENXIO; 2253 goto fail; 2254 } 2255 2256 sc->bge_btag = rman_get_bustag(sc->bge_res); 2257 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2258 2259 /* Save ASIC rev. */ 2260 2261 sc->bge_chipid = 2262 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2263 BGE_PCIMISCCTL_ASICREV; 2264 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2265 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2266 2267 if (bge_has_eeprom(sc)) 2268 sc->bge_flags |= BGE_FLAG_EEPROM; 2269 2270 /* Save chipset family. */ 2271 switch (sc->bge_asicrev) { 2272 case BGE_ASICREV_BCM5700: 2273 case BGE_ASICREV_BCM5701: 2274 case BGE_ASICREV_BCM5703: 2275 case BGE_ASICREV_BCM5704: 2276 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2277 break; 2278 case BGE_ASICREV_BCM5714_A0: 2279 case BGE_ASICREV_BCM5780: 2280 case BGE_ASICREV_BCM5714: 2281 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2282 /* FALLTHRU */ 2283 case BGE_ASICREV_BCM5750: 2284 case BGE_ASICREV_BCM5752: 2285 case BGE_ASICREV_BCM5755: 2286 case BGE_ASICREV_BCM5787: 2287 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2288 /* FALLTHRU */ 2289 case BGE_ASICREV_BCM5705: 2290 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2291 break; 2292 } 2293 2294 /* Set various bug flags. */ 2295 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2296 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2297 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2298 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2299 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2300 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2301 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2302 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2303 if (BGE_IS_5705_PLUS(sc) && 2304 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2305 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2306 sc->bge_asicrev == BGE_ASICREV_BCM5787) 2307 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2308 else 2309 sc->bge_flags |= BGE_FLAG_BER_BUG; 2310 } 2311 2312 /* 2313 * Check if this is a PCI-X or PCI Express device. 2314 */ 2315 #if __FreeBSD_version > 602101 2316 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2317 /* 2318 * Found a PCI Express capabilities register, this 2319 * must be a PCI Express device. 2320 */ 2321 if (reg != 0) 2322 sc->bge_flags |= BGE_FLAG_PCIE; 2323 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 2324 if (reg != 0) 2325 sc->bge_flags |= BGE_FLAG_PCIX; 2326 } 2327 2328 #else 2329 if (BGE_IS_5705_PLUS(sc)) { 2330 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2331 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2332 sc->bge_flags |= BGE_FLAG_PCIE; 2333 } else { 2334 /* 2335 * Check if the device is in PCI-X Mode. 2336 * (This bit is not valid on PCI Express controllers.) 2337 */ 2338 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2339 BGE_PCISTATE_PCI_BUSMODE) == 0) 2340 sc->bge_flags |= BGE_FLAG_PCIX; 2341 } 2342 #endif 2343 2344 #if __FreeBSD_version > 602105 2345 { 2346 int msicount; 2347 2348 /* 2349 * Allocate the interrupt, using MSI if possible. These devices 2350 * support 8 MSI messages, but only the first one is used in 2351 * normal operation. 2352 */ 2353 if (bge_can_use_msi(sc)) { 2354 msicount = pci_msi_count(dev); 2355 if (msicount > 1) 2356 msicount = 1; 2357 } else 2358 msicount = 0; 2359 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2360 rid = 1; 2361 sc->bge_flags |= BGE_FLAG_MSI; 2362 } else 2363 rid = 0; 2364 } 2365 #else 2366 rid = 0; 2367 #endif 2368 2369 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2370 RF_SHAREABLE | RF_ACTIVE); 2371 2372 if (sc->bge_irq == NULL) { 2373 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2374 error = ENXIO; 2375 goto fail; 2376 } 2377 2378 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2379 2380 /* Try to reset the chip. */ 2381 if (bge_reset(sc)) { 2382 device_printf(sc->bge_dev, "chip reset failed\n"); 2383 error = ENXIO; 2384 goto fail; 2385 } 2386 2387 sc->bge_asf_mode = 0; 2388 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2389 == BGE_MAGIC_NUMBER)) { 2390 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2391 & BGE_HWCFG_ASF) { 2392 sc->bge_asf_mode |= ASF_ENABLE; 2393 sc->bge_asf_mode |= ASF_STACKUP; 2394 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2395 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2396 } 2397 } 2398 } 2399 2400 /* Try to reset the chip again the nice way. */ 2401 bge_stop_fw(sc); 2402 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2403 if (bge_reset(sc)) { 2404 device_printf(sc->bge_dev, "chip reset failed\n"); 2405 error = ENXIO; 2406 goto fail; 2407 } 2408 2409 bge_sig_legacy(sc, BGE_RESET_STOP); 2410 bge_sig_post_reset(sc, BGE_RESET_STOP); 2411 2412 if (bge_chipinit(sc)) { 2413 device_printf(sc->bge_dev, "chip initialization failed\n"); 2414 error = ENXIO; 2415 goto fail; 2416 } 2417 2418 #ifdef __sparc64__ 2419 if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0) 2420 OF_getetheraddr(dev, eaddr); 2421 else 2422 #endif 2423 { 2424 mac_tmp = bge_readmem_ind(sc, 0x0C14); 2425 if ((mac_tmp >> 16) == 0x484B) { 2426 eaddr[0] = (u_char)(mac_tmp >> 8); 2427 eaddr[1] = (u_char)mac_tmp; 2428 mac_tmp = bge_readmem_ind(sc, 0x0C18); 2429 eaddr[2] = (u_char)(mac_tmp >> 24); 2430 eaddr[3] = (u_char)(mac_tmp >> 16); 2431 eaddr[4] = (u_char)(mac_tmp >> 8); 2432 eaddr[5] = (u_char)mac_tmp; 2433 } else if (bge_read_eeprom(sc, eaddr, 2434 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2435 device_printf(sc->bge_dev, 2436 "failed to read station address\n"); 2437 error = ENXIO; 2438 goto fail; 2439 } 2440 } 2441 2442 /* 5705 limits RX return ring to 512 entries. */ 2443 if (BGE_IS_5705_PLUS(sc)) 2444 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2445 else 2446 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2447 2448 if (bge_dma_alloc(dev)) { 2449 device_printf(sc->bge_dev, 2450 "failed to allocate DMA resources\n"); 2451 error = ENXIO; 2452 goto fail; 2453 } 2454 2455 /* Set default tuneable values. */ 2456 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2457 sc->bge_rx_coal_ticks = 150; 2458 sc->bge_tx_coal_ticks = 150; 2459 sc->bge_rx_max_coal_bds = 10; 2460 sc->bge_tx_max_coal_bds = 10; 2461 2462 /* Set up ifnet structure */ 2463 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2464 if (ifp == NULL) { 2465 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2466 error = ENXIO; 2467 goto fail; 2468 } 2469 ifp->if_softc = sc; 2470 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2471 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2472 ifp->if_ioctl = bge_ioctl; 2473 ifp->if_start = bge_start; 2474 ifp->if_init = bge_init; 2475 ifp->if_mtu = ETHERMTU; 2476 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2477 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2478 IFQ_SET_READY(&ifp->if_snd); 2479 ifp->if_hwassist = BGE_CSUM_FEATURES; 2480 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2481 IFCAP_VLAN_MTU; 2482 #ifdef IFCAP_VLAN_HWCSUM 2483 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2484 #endif 2485 ifp->if_capenable = ifp->if_capabilities; 2486 #ifdef DEVICE_POLLING 2487 ifp->if_capabilities |= IFCAP_POLLING; 2488 #endif 2489 2490 /* 2491 * 5700 B0 chips do not support checksumming correctly due 2492 * to hardware bugs. 2493 */ 2494 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2495 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2496 ifp->if_capenable &= IFCAP_HWCSUM; 2497 ifp->if_hwassist = 0; 2498 } 2499 2500 /* 2501 * Figure out what sort of media we have by checking the 2502 * hardware config word in the first 32k of NIC internal memory, 2503 * or fall back to examining the EEPROM if necessary. 2504 * Note: on some BCM5700 cards, this value appears to be unset. 2505 * If that's the case, we have to rely on identifying the NIC 2506 * by its PCI subsystem ID, as we do below for the SysKonnect 2507 * SK-9D41. 2508 */ 2509 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2510 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2511 else if (sc->bge_flags & BGE_FLAG_EEPROM) { 2512 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2513 sizeof(hwcfg))) { 2514 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2515 error = ENXIO; 2516 goto fail; 2517 } 2518 hwcfg = ntohl(hwcfg); 2519 } 2520 2521 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2522 sc->bge_flags |= BGE_FLAG_TBI; 2523 2524 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2525 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2526 sc->bge_flags |= BGE_FLAG_TBI; 2527 2528 if (sc->bge_flags & BGE_FLAG_TBI) { 2529 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2530 bge_ifmedia_sts); 2531 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2532 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2533 0, NULL); 2534 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2535 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2536 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2537 } else { 2538 /* 2539 * Do transceiver setup and tell the firmware the 2540 * driver is down so we can try to get access the 2541 * probe if ASF is running. Retry a couple of times 2542 * if we get a conflict with the ASF firmware accessing 2543 * the PHY. 2544 */ 2545 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2546 again: 2547 bge_asf_driver_up(sc); 2548 2549 trys = 0; 2550 if (mii_phy_probe(dev, &sc->bge_miibus, 2551 bge_ifmedia_upd, bge_ifmedia_sts)) { 2552 if (trys++ < 4) { 2553 device_printf(sc->bge_dev, "Try again\n"); 2554 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2555 BMCR_RESET); 2556 goto again; 2557 } 2558 2559 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2560 error = ENXIO; 2561 goto fail; 2562 } 2563 2564 /* 2565 * Now tell the firmware we are going up after probing the PHY 2566 */ 2567 if (sc->bge_asf_mode & ASF_STACKUP) 2568 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2569 } 2570 2571 /* 2572 * When using the BCM5701 in PCI-X mode, data corruption has 2573 * been observed in the first few bytes of some received packets. 2574 * Aligning the packet buffer in memory eliminates the corruption. 2575 * Unfortunately, this misaligns the packet payloads. On platforms 2576 * which do not support unaligned accesses, we will realign the 2577 * payloads by copying the received packets. 2578 */ 2579 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2580 sc->bge_flags & BGE_FLAG_PCIX) 2581 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2582 2583 /* 2584 * Call MI attach routine. 2585 */ 2586 ether_ifattach(ifp, eaddr); 2587 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2588 2589 /* 2590 * Hookup IRQ last. 2591 */ 2592 #if __FreeBSD_version > 700030 2593 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2594 NULL, bge_intr, sc, &sc->bge_intrhand); 2595 #else 2596 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2597 bge_intr, sc, &sc->bge_intrhand); 2598 #endif 2599 2600 if (error) { 2601 bge_detach(dev); 2602 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2603 } 2604 2605 bge_add_sysctls(sc); 2606 2607 return (0); 2608 2609 fail: 2610 bge_release_resources(sc); 2611 2612 return (error); 2613 } 2614 2615 static int 2616 bge_detach(device_t dev) 2617 { 2618 struct bge_softc *sc; 2619 struct ifnet *ifp; 2620 2621 sc = device_get_softc(dev); 2622 ifp = sc->bge_ifp; 2623 2624 #ifdef DEVICE_POLLING 2625 if (ifp->if_capenable & IFCAP_POLLING) 2626 ether_poll_deregister(ifp); 2627 #endif 2628 2629 BGE_LOCK(sc); 2630 bge_stop(sc); 2631 bge_reset(sc); 2632 BGE_UNLOCK(sc); 2633 2634 callout_drain(&sc->bge_stat_ch); 2635 2636 ether_ifdetach(ifp); 2637 2638 if (sc->bge_flags & BGE_FLAG_TBI) { 2639 ifmedia_removeall(&sc->bge_ifmedia); 2640 } else { 2641 bus_generic_detach(dev); 2642 device_delete_child(dev, sc->bge_miibus); 2643 } 2644 2645 bge_release_resources(sc); 2646 2647 return (0); 2648 } 2649 2650 static void 2651 bge_release_resources(struct bge_softc *sc) 2652 { 2653 device_t dev; 2654 2655 dev = sc->bge_dev; 2656 2657 if (sc->bge_intrhand != NULL) 2658 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2659 2660 if (sc->bge_irq != NULL) 2661 bus_release_resource(dev, SYS_RES_IRQ, 2662 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2663 2664 #if __FreeBSD_version > 602105 2665 if (sc->bge_flags & BGE_FLAG_MSI) 2666 pci_release_msi(dev); 2667 #endif 2668 2669 if (sc->bge_res != NULL) 2670 bus_release_resource(dev, SYS_RES_MEMORY, 2671 BGE_PCI_BAR0, sc->bge_res); 2672 2673 if (sc->bge_ifp != NULL) 2674 if_free(sc->bge_ifp); 2675 2676 bge_dma_free(sc); 2677 2678 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2679 BGE_LOCK_DESTROY(sc); 2680 } 2681 2682 static int 2683 bge_reset(struct bge_softc *sc) 2684 { 2685 device_t dev; 2686 uint32_t cachesize, command, pcistate, reset; 2687 void (*write_op)(struct bge_softc *, int, int); 2688 int i, val = 0; 2689 2690 dev = sc->bge_dev; 2691 2692 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { 2693 if (sc->bge_flags & BGE_FLAG_PCIE) 2694 write_op = bge_writemem_direct; 2695 else 2696 write_op = bge_writemem_ind; 2697 } else 2698 write_op = bge_writereg_ind; 2699 2700 /* Save some important PCI state. */ 2701 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2702 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2703 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2704 2705 pci_write_config(dev, BGE_PCI_MISC_CTL, 2706 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2707 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2708 2709 /* Disable fastboot on controllers that support it. */ 2710 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2711 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2712 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2713 if (bootverbose) 2714 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2715 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2716 } 2717 2718 /* 2719 * Write the magic number to SRAM at offset 0xB50. 2720 * When firmware finishes its initialization it will 2721 * write ~BGE_MAGIC_NUMBER to the same location. 2722 */ 2723 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2724 2725 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2726 2727 /* XXX: Broadcom Linux driver. */ 2728 if (sc->bge_flags & BGE_FLAG_PCIE) { 2729 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2730 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2731 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2732 /* Prevent PCIE link training during global reset */ 2733 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2734 reset |= 1 << 29; 2735 } 2736 } 2737 2738 /* 2739 * Set GPHY Power Down Override to leave GPHY 2740 * powered up in D0 uninitialized. 2741 */ 2742 if (BGE_IS_5705_PLUS(sc)) 2743 reset |= 0x04000000; 2744 2745 /* Issue global reset */ 2746 write_op(sc, BGE_MISC_CFG, reset); 2747 2748 DELAY(1000); 2749 2750 /* XXX: Broadcom Linux driver. */ 2751 if (sc->bge_flags & BGE_FLAG_PCIE) { 2752 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2753 uint32_t v; 2754 2755 DELAY(500000); /* wait for link training to complete */ 2756 v = pci_read_config(dev, 0xC4, 4); 2757 pci_write_config(dev, 0xC4, v | (1 << 15), 4); 2758 } 2759 /* 2760 * Set PCIE max payload size to 128 bytes and clear error 2761 * status. 2762 */ 2763 pci_write_config(dev, 0xD8, 0xF5000, 4); 2764 } 2765 2766 /* Reset some of the PCI state that got zapped by reset. */ 2767 pci_write_config(dev, BGE_PCI_MISC_CTL, 2768 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2769 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2770 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2771 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2772 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2773 2774 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2775 if (BGE_IS_5714_FAMILY(sc)) { 2776 uint32_t val; 2777 2778 /* This chip disables MSI on reset. */ 2779 if (sc->bge_flags & BGE_FLAG_MSI) { 2780 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2781 pci_write_config(dev, BGE_PCI_MSI_CTL, 2782 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2783 val = CSR_READ_4(sc, BGE_MSI_MODE); 2784 CSR_WRITE_4(sc, BGE_MSI_MODE, 2785 val | BGE_MSIMODE_ENABLE); 2786 } 2787 val = CSR_READ_4(sc, BGE_MARB_MODE); 2788 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2789 } else 2790 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2791 2792 /* 2793 * Poll until we see the 1's complement of the magic number. 2794 * This indicates that the firmware initialization is complete. 2795 * We expect this to fail if no EEPROM is fitted though. 2796 */ 2797 for (i = 0; i < BGE_TIMEOUT; i++) { 2798 DELAY(10); 2799 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2800 if (val == ~BGE_MAGIC_NUMBER) 2801 break; 2802 } 2803 2804 if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT) 2805 device_printf(sc->bge_dev, "firmware handshake timed out, " 2806 "found 0x%08x\n", val); 2807 2808 /* 2809 * XXX Wait for the value of the PCISTATE register to 2810 * return to its original pre-reset state. This is a 2811 * fairly good indicator of reset completion. If we don't 2812 * wait for the reset to fully complete, trying to read 2813 * from the device's non-PCI registers may yield garbage 2814 * results. 2815 */ 2816 for (i = 0; i < BGE_TIMEOUT; i++) { 2817 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2818 break; 2819 DELAY(10); 2820 } 2821 2822 if (sc->bge_flags & BGE_FLAG_PCIE) { 2823 reset = bge_readmem_ind(sc, 0x7C00); 2824 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2825 } 2826 2827 /* Fix up byte swapping. */ 2828 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2829 BGE_MODECTL_BYTESWAP_DATA); 2830 2831 /* Tell the ASF firmware we are up */ 2832 if (sc->bge_asf_mode & ASF_STACKUP) 2833 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2834 2835 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2836 2837 /* 2838 * The 5704 in TBI mode apparently needs some special 2839 * adjustment to insure the SERDES drive level is set 2840 * to 1.2V. 2841 */ 2842 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2843 sc->bge_flags & BGE_FLAG_TBI) { 2844 uint32_t serdescfg; 2845 2846 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2847 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2848 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2849 } 2850 2851 /* XXX: Broadcom Linux driver. */ 2852 if (sc->bge_flags & BGE_FLAG_PCIE && 2853 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2854 uint32_t v; 2855 2856 v = CSR_READ_4(sc, 0x7C00); 2857 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 2858 } 2859 DELAY(10000); 2860 2861 return(0); 2862 } 2863 2864 /* 2865 * Frame reception handling. This is called if there's a frame 2866 * on the receive return list. 2867 * 2868 * Note: we have to be able to handle two possibilities here: 2869 * 1) the frame is from the jumbo receive ring 2870 * 2) the frame is from the standard receive ring 2871 */ 2872 2873 static void 2874 bge_rxeof(struct bge_softc *sc) 2875 { 2876 struct ifnet *ifp; 2877 int stdcnt = 0, jumbocnt = 0; 2878 2879 BGE_LOCK_ASSERT(sc); 2880 2881 /* Nothing to do. */ 2882 if (sc->bge_rx_saved_considx == 2883 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 2884 return; 2885 2886 ifp = sc->bge_ifp; 2887 2888 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2889 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2890 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2891 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2892 if (BGE_IS_JUMBO_CAPABLE(sc)) 2893 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2894 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 2895 2896 while(sc->bge_rx_saved_considx != 2897 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2898 struct bge_rx_bd *cur_rx; 2899 uint32_t rxidx; 2900 struct mbuf *m = NULL; 2901 uint16_t vlan_tag = 0; 2902 int have_tag = 0; 2903 2904 #ifdef DEVICE_POLLING 2905 if (ifp->if_capenable & IFCAP_POLLING) { 2906 if (sc->rxcycles <= 0) 2907 break; 2908 sc->rxcycles--; 2909 } 2910 #endif 2911 2912 cur_rx = 2913 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2914 2915 rxidx = cur_rx->bge_idx; 2916 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2917 2918 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 2919 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2920 have_tag = 1; 2921 vlan_tag = cur_rx->bge_vlan_tag; 2922 } 2923 2924 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2925 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2926 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2927 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2928 BUS_DMASYNC_POSTREAD); 2929 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2930 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2931 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2932 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2933 jumbocnt++; 2934 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2935 ifp->if_ierrors++; 2936 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2937 continue; 2938 } 2939 if (bge_newbuf_jumbo(sc, 2940 sc->bge_jumbo, NULL) == ENOBUFS) { 2941 ifp->if_ierrors++; 2942 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2943 continue; 2944 } 2945 } else { 2946 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2947 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2948 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2949 BUS_DMASYNC_POSTREAD); 2950 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2951 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2952 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2953 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2954 stdcnt++; 2955 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2956 ifp->if_ierrors++; 2957 bge_newbuf_std(sc, sc->bge_std, m); 2958 continue; 2959 } 2960 if (bge_newbuf_std(sc, sc->bge_std, 2961 NULL) == ENOBUFS) { 2962 ifp->if_ierrors++; 2963 bge_newbuf_std(sc, sc->bge_std, m); 2964 continue; 2965 } 2966 } 2967 2968 ifp->if_ipackets++; 2969 #ifndef __NO_STRICT_ALIGNMENT 2970 /* 2971 * For architectures with strict alignment we must make sure 2972 * the payload is aligned. 2973 */ 2974 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 2975 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2976 cur_rx->bge_len); 2977 m->m_data += ETHER_ALIGN; 2978 } 2979 #endif 2980 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2981 m->m_pkthdr.rcvif = ifp; 2982 2983 if (ifp->if_capenable & IFCAP_RXCSUM) { 2984 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2985 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2986 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 2987 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2988 } 2989 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2990 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 2991 m->m_pkthdr.csum_data = 2992 cur_rx->bge_tcp_udp_csum; 2993 m->m_pkthdr.csum_flags |= 2994 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2995 } 2996 } 2997 2998 /* 2999 * If we received a packet with a vlan tag, 3000 * attach that information to the packet. 3001 */ 3002 if (have_tag) { 3003 #if __FreeBSD_version > 700022 3004 m->m_pkthdr.ether_vtag = vlan_tag; 3005 m->m_flags |= M_VLANTAG; 3006 #else 3007 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3008 if (m == NULL) 3009 continue; 3010 #endif 3011 } 3012 3013 BGE_UNLOCK(sc); 3014 (*ifp->if_input)(ifp, m); 3015 BGE_LOCK(sc); 3016 } 3017 3018 if (stdcnt > 0) 3019 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3020 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3021 3022 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3023 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3024 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3025 3026 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3027 if (stdcnt) 3028 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3029 if (jumbocnt) 3030 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3031 #ifdef notyet 3032 /* 3033 * This register wraps very quickly under heavy packet drops. 3034 * If you need correct statistics, you can enable this check. 3035 */ 3036 if (BGE_IS_5705_PLUS(sc)) 3037 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3038 #endif 3039 } 3040 3041 static void 3042 bge_txeof(struct bge_softc *sc) 3043 { 3044 struct bge_tx_bd *cur_tx = NULL; 3045 struct ifnet *ifp; 3046 3047 BGE_LOCK_ASSERT(sc); 3048 3049 /* Nothing to do. */ 3050 if (sc->bge_tx_saved_considx == 3051 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3052 return; 3053 3054 ifp = sc->bge_ifp; 3055 3056 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3057 sc->bge_cdata.bge_tx_ring_map, 3058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3059 /* 3060 * Go through our tx ring and free mbufs for those 3061 * frames that have been sent. 3062 */ 3063 while (sc->bge_tx_saved_considx != 3064 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3065 uint32_t idx = 0; 3066 3067 idx = sc->bge_tx_saved_considx; 3068 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3069 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3070 ifp->if_opackets++; 3071 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3072 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3073 sc->bge_cdata.bge_tx_dmamap[idx], 3074 BUS_DMASYNC_POSTWRITE); 3075 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3076 sc->bge_cdata.bge_tx_dmamap[idx]); 3077 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3078 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3079 } 3080 sc->bge_txcnt--; 3081 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3082 } 3083 3084 if (cur_tx != NULL) 3085 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3086 if (sc->bge_txcnt == 0) 3087 sc->bge_timer = 0; 3088 } 3089 3090 #ifdef DEVICE_POLLING 3091 static void 3092 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3093 { 3094 struct bge_softc *sc = ifp->if_softc; 3095 uint32_t statusword; 3096 3097 BGE_LOCK(sc); 3098 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3099 BGE_UNLOCK(sc); 3100 return; 3101 } 3102 3103 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3104 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3105 3106 statusword = atomic_readandclear_32( 3107 &sc->bge_ldata.bge_status_block->bge_status); 3108 3109 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3110 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3111 3112 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3113 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3114 sc->bge_link_evt++; 3115 3116 if (cmd == POLL_AND_CHECK_STATUS) 3117 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3118 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3119 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3120 bge_link_upd(sc); 3121 3122 sc->rxcycles = count; 3123 bge_rxeof(sc); 3124 bge_txeof(sc); 3125 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3126 bge_start_locked(ifp); 3127 3128 BGE_UNLOCK(sc); 3129 } 3130 #endif /* DEVICE_POLLING */ 3131 3132 static void 3133 bge_intr(void *xsc) 3134 { 3135 struct bge_softc *sc; 3136 struct ifnet *ifp; 3137 uint32_t statusword; 3138 3139 sc = xsc; 3140 3141 BGE_LOCK(sc); 3142 3143 ifp = sc->bge_ifp; 3144 3145 #ifdef DEVICE_POLLING 3146 if (ifp->if_capenable & IFCAP_POLLING) { 3147 BGE_UNLOCK(sc); 3148 return; 3149 } 3150 #endif 3151 3152 /* 3153 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3154 * disable interrupts by writing nonzero like we used to, since with 3155 * our current organization this just gives complications and 3156 * pessimizations for re-enabling interrupts. We used to have races 3157 * instead of the necessary complications. Disabling interrupts 3158 * would just reduce the chance of a status update while we are 3159 * running (by switching to the interrupt-mode coalescence 3160 * parameters), but this chance is already very low so it is more 3161 * efficient to get another interrupt than prevent it. 3162 * 3163 * We do the ack first to ensure another interrupt if there is a 3164 * status update after the ack. We don't check for the status 3165 * changing later because it is more efficient to get another 3166 * interrupt than prevent it, not quite as above (not checking is 3167 * a smaller optimization than not toggling the interrupt enable, 3168 * since checking doesn't involve PCI accesses and toggling require 3169 * the status check). So toggling would probably be a pessimization 3170 * even with MSI. It would only be needed for using a task queue. 3171 */ 3172 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3173 3174 /* 3175 * Do the mandatory PCI flush as well as get the link status. 3176 */ 3177 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3178 3179 /* Make sure the descriptor ring indexes are coherent. */ 3180 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3181 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3182 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3183 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3184 3185 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3186 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3187 statusword || sc->bge_link_evt) 3188 bge_link_upd(sc); 3189 3190 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3191 /* Check RX return ring producer/consumer. */ 3192 bge_rxeof(sc); 3193 3194 /* Check TX ring producer/consumer. */ 3195 bge_txeof(sc); 3196 } 3197 3198 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3199 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3200 bge_start_locked(ifp); 3201 3202 BGE_UNLOCK(sc); 3203 } 3204 3205 static void 3206 bge_asf_driver_up(struct bge_softc *sc) 3207 { 3208 if (sc->bge_asf_mode & ASF_STACKUP) { 3209 /* Send ASF heartbeat aprox. every 2s */ 3210 if (sc->bge_asf_count) 3211 sc->bge_asf_count --; 3212 else { 3213 sc->bge_asf_count = 5; 3214 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3215 BGE_FW_DRV_ALIVE); 3216 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3217 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3218 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3219 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3220 } 3221 } 3222 } 3223 3224 static void 3225 bge_tick(void *xsc) 3226 { 3227 struct bge_softc *sc = xsc; 3228 struct mii_data *mii = NULL; 3229 3230 BGE_LOCK_ASSERT(sc); 3231 3232 /* Synchronize with possible callout reset/stop. */ 3233 if (callout_pending(&sc->bge_stat_ch) || 3234 !callout_active(&sc->bge_stat_ch)) 3235 return; 3236 3237 if (BGE_IS_5705_PLUS(sc)) 3238 bge_stats_update_regs(sc); 3239 else 3240 bge_stats_update(sc); 3241 3242 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3243 mii = device_get_softc(sc->bge_miibus); 3244 /* Don't mess with the PHY in IPMI/ASF mode */ 3245 if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link))) 3246 mii_tick(mii); 3247 } else { 3248 /* 3249 * Since in TBI mode auto-polling can't be used we should poll 3250 * link status manually. Here we register pending link event 3251 * and trigger interrupt. 3252 */ 3253 #ifdef DEVICE_POLLING 3254 /* In polling mode we poll link state in bge_poll(). */ 3255 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3256 #endif 3257 { 3258 sc->bge_link_evt++; 3259 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3260 } 3261 } 3262 3263 bge_asf_driver_up(sc); 3264 bge_watchdog(sc); 3265 3266 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3267 } 3268 3269 static void 3270 bge_stats_update_regs(struct bge_softc *sc) 3271 { 3272 struct ifnet *ifp; 3273 3274 ifp = sc->bge_ifp; 3275 3276 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3277 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3278 3279 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3280 } 3281 3282 static void 3283 bge_stats_update(struct bge_softc *sc) 3284 { 3285 struct ifnet *ifp; 3286 bus_size_t stats; 3287 uint32_t cnt; /* current register value */ 3288 3289 ifp = sc->bge_ifp; 3290 3291 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3292 3293 #define READ_STAT(sc, stats, stat) \ 3294 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3295 3296 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3297 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3298 sc->bge_tx_collisions = cnt; 3299 3300 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3301 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3302 sc->bge_rx_discards = cnt; 3303 3304 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3305 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3306 sc->bge_tx_discards = cnt; 3307 3308 #undef READ_STAT 3309 } 3310 3311 /* 3312 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3313 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3314 * but when such padded frames employ the bge IP/TCP checksum offload, 3315 * the hardware checksum assist gives incorrect results (possibly 3316 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3317 * If we pad such runts with zeros, the onboard checksum comes out correct. 3318 */ 3319 static __inline int 3320 bge_cksum_pad(struct mbuf *m) 3321 { 3322 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3323 struct mbuf *last; 3324 3325 /* If there's only the packet-header and we can pad there, use it. */ 3326 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3327 M_TRAILINGSPACE(m) >= padlen) { 3328 last = m; 3329 } else { 3330 /* 3331 * Walk packet chain to find last mbuf. We will either 3332 * pad there, or append a new mbuf and pad it. 3333 */ 3334 for (last = m; last->m_next != NULL; last = last->m_next); 3335 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3336 /* Allocate new empty mbuf, pad it. Compact later. */ 3337 struct mbuf *n; 3338 3339 MGET(n, M_DONTWAIT, MT_DATA); 3340 if (n == NULL) 3341 return (ENOBUFS); 3342 n->m_len = 0; 3343 last->m_next = n; 3344 last = n; 3345 } 3346 } 3347 3348 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3349 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3350 last->m_len += padlen; 3351 m->m_pkthdr.len += padlen; 3352 3353 return (0); 3354 } 3355 3356 /* 3357 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3358 * pointers to descriptors. 3359 */ 3360 static int 3361 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3362 { 3363 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3364 bus_dmamap_t map; 3365 struct bge_tx_bd *d; 3366 struct mbuf *m = *m_head; 3367 uint32_t idx = *txidx; 3368 uint16_t csum_flags; 3369 int nsegs, i, error; 3370 3371 csum_flags = 0; 3372 if (m->m_pkthdr.csum_flags) { 3373 if (m->m_pkthdr.csum_flags & CSUM_IP) 3374 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3375 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3376 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3377 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3378 (error = bge_cksum_pad(m)) != 0) { 3379 m_freem(m); 3380 *m_head = NULL; 3381 return (error); 3382 } 3383 } 3384 if (m->m_flags & M_LASTFRAG) 3385 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3386 else if (m->m_flags & M_FRAG) 3387 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3388 } 3389 3390 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3391 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3392 &nsegs, BUS_DMA_NOWAIT); 3393 if (error == EFBIG) { 3394 m = m_defrag(m, M_DONTWAIT); 3395 if (m == NULL) { 3396 m_freem(*m_head); 3397 *m_head = NULL; 3398 return (ENOBUFS); 3399 } 3400 *m_head = m; 3401 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3402 segs, &nsegs, BUS_DMA_NOWAIT); 3403 if (error) { 3404 m_freem(m); 3405 *m_head = NULL; 3406 return (error); 3407 } 3408 } else if (error != 0) 3409 return (error); 3410 3411 /* 3412 * Sanity check: avoid coming within 16 descriptors 3413 * of the end of the ring. 3414 */ 3415 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3416 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3417 return (ENOBUFS); 3418 } 3419 3420 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3421 3422 for (i = 0; ; i++) { 3423 d = &sc->bge_ldata.bge_tx_ring[idx]; 3424 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3425 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3426 d->bge_len = segs[i].ds_len; 3427 d->bge_flags = csum_flags; 3428 if (i == nsegs - 1) 3429 break; 3430 BGE_INC(idx, BGE_TX_RING_CNT); 3431 } 3432 3433 /* Mark the last segment as end of packet... */ 3434 d->bge_flags |= BGE_TXBDFLAG_END; 3435 3436 /* ... and put VLAN tag into first segment. */ 3437 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3438 #if __FreeBSD_version > 700022 3439 if (m->m_flags & M_VLANTAG) { 3440 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3441 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3442 } else 3443 d->bge_vlan_tag = 0; 3444 #else 3445 { 3446 struct m_tag *mtag; 3447 3448 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3449 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3450 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3451 } else 3452 d->bge_vlan_tag = 0; 3453 } 3454 #endif 3455 3456 /* 3457 * Insure that the map for this transmission 3458 * is placed at the array index of the last descriptor 3459 * in this chain. 3460 */ 3461 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3462 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3463 sc->bge_cdata.bge_tx_chain[idx] = m; 3464 sc->bge_txcnt += nsegs; 3465 3466 BGE_INC(idx, BGE_TX_RING_CNT); 3467 *txidx = idx; 3468 3469 return (0); 3470 } 3471 3472 /* 3473 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3474 * to the mbuf data regions directly in the transmit descriptors. 3475 */ 3476 static void 3477 bge_start_locked(struct ifnet *ifp) 3478 { 3479 struct bge_softc *sc; 3480 struct mbuf *m_head = NULL; 3481 uint32_t prodidx; 3482 int count = 0; 3483 3484 sc = ifp->if_softc; 3485 3486 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3487 return; 3488 3489 prodidx = sc->bge_tx_prodidx; 3490 3491 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3492 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3493 if (m_head == NULL) 3494 break; 3495 3496 /* 3497 * XXX 3498 * The code inside the if() block is never reached since we 3499 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3500 * requests to checksum TCP/UDP in a fragmented packet. 3501 * 3502 * XXX 3503 * safety overkill. If this is a fragmented packet chain 3504 * with delayed TCP/UDP checksums, then only encapsulate 3505 * it if we have enough descriptors to handle the entire 3506 * chain at once. 3507 * (paranoia -- may not actually be needed) 3508 */ 3509 if (m_head->m_flags & M_FIRSTFRAG && 3510 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3511 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3512 m_head->m_pkthdr.csum_data + 16) { 3513 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3514 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3515 break; 3516 } 3517 } 3518 3519 /* 3520 * Pack the data into the transmit ring. If we 3521 * don't have room, set the OACTIVE flag and wait 3522 * for the NIC to drain the ring. 3523 */ 3524 if (bge_encap(sc, &m_head, &prodidx)) { 3525 if (m_head == NULL) 3526 break; 3527 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3528 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3529 break; 3530 } 3531 ++count; 3532 3533 /* 3534 * If there's a BPF listener, bounce a copy of this frame 3535 * to him. 3536 */ 3537 #ifdef ETHER_BPF_MTAP 3538 ETHER_BPF_MTAP(ifp, m_head); 3539 #else 3540 BPF_MTAP(ifp, m_head); 3541 #endif 3542 } 3543 3544 if (count == 0) 3545 /* No packets were dequeued. */ 3546 return; 3547 3548 /* Transmit. */ 3549 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3550 /* 5700 b2 errata */ 3551 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3552 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3553 3554 sc->bge_tx_prodidx = prodidx; 3555 3556 /* 3557 * Set a timeout in case the chip goes out to lunch. 3558 */ 3559 sc->bge_timer = 5; 3560 } 3561 3562 /* 3563 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3564 * to the mbuf data regions directly in the transmit descriptors. 3565 */ 3566 static void 3567 bge_start(struct ifnet *ifp) 3568 { 3569 struct bge_softc *sc; 3570 3571 sc = ifp->if_softc; 3572 BGE_LOCK(sc); 3573 bge_start_locked(ifp); 3574 BGE_UNLOCK(sc); 3575 } 3576 3577 static void 3578 bge_init_locked(struct bge_softc *sc) 3579 { 3580 struct ifnet *ifp; 3581 uint16_t *m; 3582 3583 BGE_LOCK_ASSERT(sc); 3584 3585 ifp = sc->bge_ifp; 3586 3587 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3588 return; 3589 3590 /* Cancel pending I/O and flush buffers. */ 3591 bge_stop(sc); 3592 3593 bge_stop_fw(sc); 3594 bge_sig_pre_reset(sc, BGE_RESET_START); 3595 bge_reset(sc); 3596 bge_sig_legacy(sc, BGE_RESET_START); 3597 bge_sig_post_reset(sc, BGE_RESET_START); 3598 3599 bge_chipinit(sc); 3600 3601 /* 3602 * Init the various state machines, ring 3603 * control blocks and firmware. 3604 */ 3605 if (bge_blockinit(sc)) { 3606 device_printf(sc->bge_dev, "initialization failure\n"); 3607 return; 3608 } 3609 3610 ifp = sc->bge_ifp; 3611 3612 /* Specify MTU. */ 3613 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3614 ETHER_HDR_LEN + ETHER_CRC_LEN + 3615 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 3616 3617 /* Load our MAC address. */ 3618 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3619 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3620 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3621 3622 /* Program promiscuous mode. */ 3623 bge_setpromisc(sc); 3624 3625 /* Program multicast filter. */ 3626 bge_setmulti(sc); 3627 3628 /* Program VLAN tag stripping. */ 3629 bge_setvlan(sc); 3630 3631 /* Init RX ring. */ 3632 bge_init_rx_ring_std(sc); 3633 3634 /* 3635 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3636 * memory to insure that the chip has in fact read the first 3637 * entry of the ring. 3638 */ 3639 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3640 uint32_t v, i; 3641 for (i = 0; i < 10; i++) { 3642 DELAY(20); 3643 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3644 if (v == (MCLBYTES - ETHER_ALIGN)) 3645 break; 3646 } 3647 if (i == 10) 3648 device_printf (sc->bge_dev, 3649 "5705 A0 chip failed to load RX ring\n"); 3650 } 3651 3652 /* Init jumbo RX ring. */ 3653 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3654 bge_init_rx_ring_jumbo(sc); 3655 3656 /* Init our RX return ring index. */ 3657 sc->bge_rx_saved_considx = 0; 3658 3659 /* Init our RX/TX stat counters. */ 3660 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3661 3662 /* Init TX ring. */ 3663 bge_init_tx_ring(sc); 3664 3665 /* Turn on transmitter. */ 3666 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3667 3668 /* Turn on receiver. */ 3669 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3670 3671 /* Tell firmware we're alive. */ 3672 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3673 3674 #ifdef DEVICE_POLLING 3675 /* Disable interrupts if we are polling. */ 3676 if (ifp->if_capenable & IFCAP_POLLING) { 3677 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3678 BGE_PCIMISCCTL_MASK_PCI_INTR); 3679 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3680 } else 3681 #endif 3682 3683 /* Enable host interrupts. */ 3684 { 3685 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3686 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3687 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3688 } 3689 3690 bge_ifmedia_upd_locked(ifp); 3691 3692 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3693 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3694 3695 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3696 } 3697 3698 static void 3699 bge_init(void *xsc) 3700 { 3701 struct bge_softc *sc = xsc; 3702 3703 BGE_LOCK(sc); 3704 bge_init_locked(sc); 3705 BGE_UNLOCK(sc); 3706 } 3707 3708 /* 3709 * Set media options. 3710 */ 3711 static int 3712 bge_ifmedia_upd(struct ifnet *ifp) 3713 { 3714 struct bge_softc *sc = ifp->if_softc; 3715 int res; 3716 3717 BGE_LOCK(sc); 3718 res = bge_ifmedia_upd_locked(ifp); 3719 BGE_UNLOCK(sc); 3720 3721 return (res); 3722 } 3723 3724 static int 3725 bge_ifmedia_upd_locked(struct ifnet *ifp) 3726 { 3727 struct bge_softc *sc = ifp->if_softc; 3728 struct mii_data *mii; 3729 struct ifmedia *ifm; 3730 3731 BGE_LOCK_ASSERT(sc); 3732 3733 ifm = &sc->bge_ifmedia; 3734 3735 /* If this is a 1000baseX NIC, enable the TBI port. */ 3736 if (sc->bge_flags & BGE_FLAG_TBI) { 3737 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3738 return (EINVAL); 3739 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3740 case IFM_AUTO: 3741 /* 3742 * The BCM5704 ASIC appears to have a special 3743 * mechanism for programming the autoneg 3744 * advertisement registers in TBI mode. 3745 */ 3746 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3747 uint32_t sgdig; 3748 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3749 if (sgdig & BGE_SGDIGSTS_DONE) { 3750 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3751 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3752 sgdig |= BGE_SGDIGCFG_AUTO | 3753 BGE_SGDIGCFG_PAUSE_CAP | 3754 BGE_SGDIGCFG_ASYM_PAUSE; 3755 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3756 sgdig | BGE_SGDIGCFG_SEND); 3757 DELAY(5); 3758 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3759 } 3760 } 3761 break; 3762 case IFM_1000_SX: 3763 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3764 BGE_CLRBIT(sc, BGE_MAC_MODE, 3765 BGE_MACMODE_HALF_DUPLEX); 3766 } else { 3767 BGE_SETBIT(sc, BGE_MAC_MODE, 3768 BGE_MACMODE_HALF_DUPLEX); 3769 } 3770 break; 3771 default: 3772 return (EINVAL); 3773 } 3774 return (0); 3775 } 3776 3777 sc->bge_link_evt++; 3778 mii = device_get_softc(sc->bge_miibus); 3779 if (mii->mii_instance) { 3780 struct mii_softc *miisc; 3781 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3782 miisc = LIST_NEXT(miisc, mii_list)) 3783 mii_phy_reset(miisc); 3784 } 3785 mii_mediachg(mii); 3786 3787 return (0); 3788 } 3789 3790 /* 3791 * Report current media status. 3792 */ 3793 static void 3794 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3795 { 3796 struct bge_softc *sc = ifp->if_softc; 3797 struct mii_data *mii; 3798 3799 BGE_LOCK(sc); 3800 3801 if (sc->bge_flags & BGE_FLAG_TBI) { 3802 ifmr->ifm_status = IFM_AVALID; 3803 ifmr->ifm_active = IFM_ETHER; 3804 if (CSR_READ_4(sc, BGE_MAC_STS) & 3805 BGE_MACSTAT_TBI_PCS_SYNCHED) 3806 ifmr->ifm_status |= IFM_ACTIVE; 3807 else { 3808 ifmr->ifm_active |= IFM_NONE; 3809 BGE_UNLOCK(sc); 3810 return; 3811 } 3812 ifmr->ifm_active |= IFM_1000_SX; 3813 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3814 ifmr->ifm_active |= IFM_HDX; 3815 else 3816 ifmr->ifm_active |= IFM_FDX; 3817 BGE_UNLOCK(sc); 3818 return; 3819 } 3820 3821 mii = device_get_softc(sc->bge_miibus); 3822 mii_pollstat(mii); 3823 ifmr->ifm_active = mii->mii_media_active; 3824 ifmr->ifm_status = mii->mii_media_status; 3825 3826 BGE_UNLOCK(sc); 3827 } 3828 3829 static int 3830 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3831 { 3832 struct bge_softc *sc = ifp->if_softc; 3833 struct ifreq *ifr = (struct ifreq *) data; 3834 struct mii_data *mii; 3835 int flags, mask, error = 0; 3836 3837 switch (command) { 3838 case SIOCSIFMTU: 3839 if (ifr->ifr_mtu < ETHERMIN || 3840 ((BGE_IS_JUMBO_CAPABLE(sc)) && 3841 ifr->ifr_mtu > BGE_JUMBO_MTU) || 3842 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 3843 ifr->ifr_mtu > ETHERMTU)) 3844 error = EINVAL; 3845 else if (ifp->if_mtu != ifr->ifr_mtu) { 3846 ifp->if_mtu = ifr->ifr_mtu; 3847 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3848 bge_init(sc); 3849 } 3850 break; 3851 case SIOCSIFFLAGS: 3852 BGE_LOCK(sc); 3853 if (ifp->if_flags & IFF_UP) { 3854 /* 3855 * If only the state of the PROMISC flag changed, 3856 * then just use the 'set promisc mode' command 3857 * instead of reinitializing the entire NIC. Doing 3858 * a full re-init means reloading the firmware and 3859 * waiting for it to start up, which may take a 3860 * second or two. Similarly for ALLMULTI. 3861 */ 3862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3863 flags = ifp->if_flags ^ sc->bge_if_flags; 3864 if (flags & IFF_PROMISC) 3865 bge_setpromisc(sc); 3866 if (flags & IFF_ALLMULTI) 3867 bge_setmulti(sc); 3868 } else 3869 bge_init_locked(sc); 3870 } else { 3871 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3872 bge_stop(sc); 3873 } 3874 } 3875 sc->bge_if_flags = ifp->if_flags; 3876 BGE_UNLOCK(sc); 3877 error = 0; 3878 break; 3879 case SIOCADDMULTI: 3880 case SIOCDELMULTI: 3881 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3882 BGE_LOCK(sc); 3883 bge_setmulti(sc); 3884 BGE_UNLOCK(sc); 3885 error = 0; 3886 } 3887 break; 3888 case SIOCSIFMEDIA: 3889 case SIOCGIFMEDIA: 3890 if (sc->bge_flags & BGE_FLAG_TBI) { 3891 error = ifmedia_ioctl(ifp, ifr, 3892 &sc->bge_ifmedia, command); 3893 } else { 3894 mii = device_get_softc(sc->bge_miibus); 3895 error = ifmedia_ioctl(ifp, ifr, 3896 &mii->mii_media, command); 3897 } 3898 break; 3899 case SIOCSIFCAP: 3900 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3901 #ifdef DEVICE_POLLING 3902 if (mask & IFCAP_POLLING) { 3903 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3904 error = ether_poll_register(bge_poll, ifp); 3905 if (error) 3906 return (error); 3907 BGE_LOCK(sc); 3908 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3909 BGE_PCIMISCCTL_MASK_PCI_INTR); 3910 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3911 ifp->if_capenable |= IFCAP_POLLING; 3912 BGE_UNLOCK(sc); 3913 } else { 3914 error = ether_poll_deregister(ifp); 3915 /* Enable interrupt even in error case */ 3916 BGE_LOCK(sc); 3917 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 3918 BGE_PCIMISCCTL_MASK_PCI_INTR); 3919 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3920 ifp->if_capenable &= ~IFCAP_POLLING; 3921 BGE_UNLOCK(sc); 3922 } 3923 } 3924 #endif 3925 if (mask & IFCAP_HWCSUM) { 3926 ifp->if_capenable ^= IFCAP_HWCSUM; 3927 if (IFCAP_HWCSUM & ifp->if_capenable && 3928 IFCAP_HWCSUM & ifp->if_capabilities) 3929 ifp->if_hwassist = BGE_CSUM_FEATURES; 3930 else 3931 ifp->if_hwassist = 0; 3932 #ifdef VLAN_CAPABILITIES 3933 VLAN_CAPABILITIES(ifp); 3934 #endif 3935 } 3936 3937 if (mask & IFCAP_VLAN_MTU) { 3938 ifp->if_capenable ^= IFCAP_VLAN_MTU; 3939 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3940 bge_init(sc); 3941 } 3942 3943 if (mask & IFCAP_VLAN_HWTAGGING) { 3944 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3945 BGE_LOCK(sc); 3946 bge_setvlan(sc); 3947 BGE_UNLOCK(sc); 3948 #ifdef VLAN_CAPABILITIES 3949 VLAN_CAPABILITIES(ifp); 3950 #endif 3951 } 3952 3953 break; 3954 default: 3955 error = ether_ioctl(ifp, command, data); 3956 break; 3957 } 3958 3959 return (error); 3960 } 3961 3962 static void 3963 bge_watchdog(struct bge_softc *sc) 3964 { 3965 struct ifnet *ifp; 3966 3967 BGE_LOCK_ASSERT(sc); 3968 3969 if (sc->bge_timer == 0 || --sc->bge_timer) 3970 return; 3971 3972 ifp = sc->bge_ifp; 3973 3974 if_printf(ifp, "watchdog timeout -- resetting\n"); 3975 3976 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3977 bge_init_locked(sc); 3978 3979 ifp->if_oerrors++; 3980 } 3981 3982 /* 3983 * Stop the adapter and free any mbufs allocated to the 3984 * RX and TX lists. 3985 */ 3986 static void 3987 bge_stop(struct bge_softc *sc) 3988 { 3989 struct ifnet *ifp; 3990 struct ifmedia_entry *ifm; 3991 struct mii_data *mii = NULL; 3992 int mtmp, itmp; 3993 3994 BGE_LOCK_ASSERT(sc); 3995 3996 ifp = sc->bge_ifp; 3997 3998 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 3999 mii = device_get_softc(sc->bge_miibus); 4000 4001 callout_stop(&sc->bge_stat_ch); 4002 4003 /* 4004 * Disable all of the receiver blocks. 4005 */ 4006 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4007 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4008 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4009 if (!(BGE_IS_5705_PLUS(sc))) 4010 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4011 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4012 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4013 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4014 4015 /* 4016 * Disable all of the transmit blocks. 4017 */ 4018 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4019 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4020 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4021 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4022 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4023 if (!(BGE_IS_5705_PLUS(sc))) 4024 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4025 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4026 4027 /* 4028 * Shut down all of the memory managers and related 4029 * state machines. 4030 */ 4031 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4032 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4033 if (!(BGE_IS_5705_PLUS(sc))) 4034 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4035 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4036 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4037 if (!(BGE_IS_5705_PLUS(sc))) { 4038 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4039 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4040 } 4041 4042 /* Disable host interrupts. */ 4043 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4044 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4045 4046 /* 4047 * Tell firmware we're shutting down. 4048 */ 4049 4050 bge_stop_fw(sc); 4051 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4052 bge_reset(sc); 4053 bge_sig_legacy(sc, BGE_RESET_STOP); 4054 bge_sig_post_reset(sc, BGE_RESET_STOP); 4055 4056 /* 4057 * Keep the ASF firmware running if up. 4058 */ 4059 if (sc->bge_asf_mode & ASF_STACKUP) 4060 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4061 else 4062 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4063 4064 /* Free the RX lists. */ 4065 bge_free_rx_ring_std(sc); 4066 4067 /* Free jumbo RX list. */ 4068 if (BGE_IS_JUMBO_CAPABLE(sc)) 4069 bge_free_rx_ring_jumbo(sc); 4070 4071 /* Free TX buffers. */ 4072 bge_free_tx_ring(sc); 4073 4074 /* 4075 * Isolate/power down the PHY, but leave the media selection 4076 * unchanged so that things will be put back to normal when 4077 * we bring the interface back up. 4078 */ 4079 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4080 itmp = ifp->if_flags; 4081 ifp->if_flags |= IFF_UP; 4082 /* 4083 * If we are called from bge_detach(), mii is already NULL. 4084 */ 4085 if (mii != NULL) { 4086 ifm = mii->mii_media.ifm_cur; 4087 mtmp = ifm->ifm_media; 4088 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4089 mii_mediachg(mii); 4090 ifm->ifm_media = mtmp; 4091 } 4092 ifp->if_flags = itmp; 4093 } 4094 4095 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4096 4097 /* Clear MAC's link state (PHY may still have link UP). */ 4098 if (bootverbose && sc->bge_link) 4099 if_printf(sc->bge_ifp, "link DOWN\n"); 4100 sc->bge_link = 0; 4101 4102 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4103 } 4104 4105 /* 4106 * Stop all chip I/O so that the kernel's probe routines don't 4107 * get confused by errant DMAs when rebooting. 4108 */ 4109 static void 4110 bge_shutdown(device_t dev) 4111 { 4112 struct bge_softc *sc; 4113 4114 sc = device_get_softc(dev); 4115 4116 BGE_LOCK(sc); 4117 bge_stop(sc); 4118 bge_reset(sc); 4119 BGE_UNLOCK(sc); 4120 } 4121 4122 static int 4123 bge_suspend(device_t dev) 4124 { 4125 struct bge_softc *sc; 4126 4127 sc = device_get_softc(dev); 4128 BGE_LOCK(sc); 4129 bge_stop(sc); 4130 BGE_UNLOCK(sc); 4131 4132 return (0); 4133 } 4134 4135 static int 4136 bge_resume(device_t dev) 4137 { 4138 struct bge_softc *sc; 4139 struct ifnet *ifp; 4140 4141 sc = device_get_softc(dev); 4142 BGE_LOCK(sc); 4143 ifp = sc->bge_ifp; 4144 if (ifp->if_flags & IFF_UP) { 4145 bge_init_locked(sc); 4146 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4147 bge_start_locked(ifp); 4148 } 4149 BGE_UNLOCK(sc); 4150 4151 return (0); 4152 } 4153 4154 static void 4155 bge_link_upd(struct bge_softc *sc) 4156 { 4157 struct mii_data *mii; 4158 uint32_t link, status; 4159 4160 BGE_LOCK_ASSERT(sc); 4161 4162 /* Clear 'pending link event' flag. */ 4163 sc->bge_link_evt = 0; 4164 4165 /* 4166 * Process link state changes. 4167 * Grrr. The link status word in the status block does 4168 * not work correctly on the BCM5700 rev AX and BX chips, 4169 * according to all available information. Hence, we have 4170 * to enable MII interrupts in order to properly obtain 4171 * async link changes. Unfortunately, this also means that 4172 * we have to read the MAC status register to detect link 4173 * changes, thereby adding an additional register access to 4174 * the interrupt handler. 4175 * 4176 * XXX: perhaps link state detection procedure used for 4177 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4178 */ 4179 4180 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4181 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4182 status = CSR_READ_4(sc, BGE_MAC_STS); 4183 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4184 mii = device_get_softc(sc->bge_miibus); 4185 mii_pollstat(mii); 4186 if (!sc->bge_link && 4187 mii->mii_media_status & IFM_ACTIVE && 4188 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4189 sc->bge_link++; 4190 if (bootverbose) 4191 if_printf(sc->bge_ifp, "link UP\n"); 4192 } else if (sc->bge_link && 4193 (!(mii->mii_media_status & IFM_ACTIVE) || 4194 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4195 sc->bge_link = 0; 4196 if (bootverbose) 4197 if_printf(sc->bge_ifp, "link DOWN\n"); 4198 } 4199 4200 /* Clear the interrupt. */ 4201 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4202 BGE_EVTENB_MI_INTERRUPT); 4203 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4204 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4205 BRGPHY_INTRS); 4206 } 4207 return; 4208 } 4209 4210 if (sc->bge_flags & BGE_FLAG_TBI) { 4211 status = CSR_READ_4(sc, BGE_MAC_STS); 4212 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4213 if (!sc->bge_link) { 4214 sc->bge_link++; 4215 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4216 BGE_CLRBIT(sc, BGE_MAC_MODE, 4217 BGE_MACMODE_TBI_SEND_CFGS); 4218 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4219 if (bootverbose) 4220 if_printf(sc->bge_ifp, "link UP\n"); 4221 if_link_state_change(sc->bge_ifp, 4222 LINK_STATE_UP); 4223 } 4224 } else if (sc->bge_link) { 4225 sc->bge_link = 0; 4226 if (bootverbose) 4227 if_printf(sc->bge_ifp, "link DOWN\n"); 4228 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4229 } 4230 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4231 /* 4232 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4233 * in status word always set. Workaround this bug by reading 4234 * PHY link status directly. 4235 */ 4236 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4237 4238 if (link != sc->bge_link || 4239 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4240 mii = device_get_softc(sc->bge_miibus); 4241 mii_pollstat(mii); 4242 if (!sc->bge_link && 4243 mii->mii_media_status & IFM_ACTIVE && 4244 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4245 sc->bge_link++; 4246 if (bootverbose) 4247 if_printf(sc->bge_ifp, "link UP\n"); 4248 } else if (sc->bge_link && 4249 (!(mii->mii_media_status & IFM_ACTIVE) || 4250 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4251 sc->bge_link = 0; 4252 if (bootverbose) 4253 if_printf(sc->bge_ifp, "link DOWN\n"); 4254 } 4255 } 4256 } else { 4257 /* 4258 * Discard link events for MII/GMII controllers 4259 * if MI auto-polling is disabled. 4260 */ 4261 } 4262 4263 /* Clear the attention. */ 4264 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4265 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4266 BGE_MACSTAT_LINK_CHANGED); 4267 } 4268 4269 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4270 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4271 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4272 desc) 4273 4274 static void 4275 bge_add_sysctls(struct bge_softc *sc) 4276 { 4277 struct sysctl_ctx_list *ctx; 4278 struct sysctl_oid_list *children, *schildren; 4279 struct sysctl_oid *tree; 4280 4281 ctx = device_get_sysctl_ctx(sc->bge_dev); 4282 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4283 4284 #ifdef BGE_REGISTER_DEBUG 4285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4286 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4287 "Debug Information"); 4288 4289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4290 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4291 "Register Read"); 4292 4293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4294 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4295 "Memory Read"); 4296 4297 #endif 4298 4299 if (BGE_IS_5705_PLUS(sc)) 4300 return; 4301 4302 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4303 NULL, "BGE Statistics"); 4304 schildren = children = SYSCTL_CHILDREN(tree); 4305 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4306 children, COSFramesDroppedDueToFilters, 4307 "FramesDroppedDueToFilters"); 4308 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4309 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4310 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4311 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4312 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4313 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4314 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4315 children, ifInDiscards, "InputDiscards"); 4316 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4317 children, ifInErrors, "InputErrors"); 4318 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4319 children, nicRecvThresholdHit, "RecvThresholdHit"); 4320 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4321 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4322 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4323 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4324 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4325 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4326 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4327 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4328 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4329 children, nicRingStatusUpdate, "RingStatusUpdate"); 4330 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4331 children, nicInterrupts, "Interrupts"); 4332 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4333 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4334 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4335 children, nicSendThresholdHit, "SendThresholdHit"); 4336 4337 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4338 NULL, "BGE RX Statistics"); 4339 children = SYSCTL_CHILDREN(tree); 4340 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4341 children, rxstats.ifHCInOctets, "Octets"); 4342 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4343 children, rxstats.etherStatsFragments, "Fragments"); 4344 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4345 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4346 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4347 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4348 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4349 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4350 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4351 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4352 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4353 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4354 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4355 children, rxstats.xoffPauseFramesReceived, 4356 "xoffPauseFramesReceived"); 4357 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4358 children, rxstats.macControlFramesReceived, 4359 "ControlFramesReceived"); 4360 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4361 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4362 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4363 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4364 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4365 children, rxstats.etherStatsJabbers, "Jabbers"); 4366 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4367 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4368 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4369 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4370 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4371 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4372 4373 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4374 NULL, "BGE TX Statistics"); 4375 children = SYSCTL_CHILDREN(tree); 4376 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4377 children, txstats.ifHCOutOctets, "Octets"); 4378 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4379 children, txstats.etherStatsCollisions, "Collisions"); 4380 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4381 children, txstats.outXonSent, "XonSent"); 4382 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4383 children, txstats.outXoffSent, "XoffSent"); 4384 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4385 children, txstats.flowControlDone, "flowControlDone"); 4386 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4387 children, txstats.dot3StatsInternalMacTransmitErrors, 4388 "InternalMacTransmitErrors"); 4389 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4390 children, txstats.dot3StatsSingleCollisionFrames, 4391 "SingleCollisionFrames"); 4392 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4393 children, txstats.dot3StatsMultipleCollisionFrames, 4394 "MultipleCollisionFrames"); 4395 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4396 children, txstats.dot3StatsDeferredTransmissions, 4397 "DeferredTransmissions"); 4398 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4399 children, txstats.dot3StatsExcessiveCollisions, 4400 "ExcessiveCollisions"); 4401 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4402 children, txstats.dot3StatsLateCollisions, 4403 "LateCollisions"); 4404 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4405 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4406 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4407 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4408 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4409 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4410 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4411 children, txstats.dot3StatsCarrierSenseErrors, 4412 "CarrierSenseErrors"); 4413 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4414 children, txstats.ifOutDiscards, "Discards"); 4415 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4416 children, txstats.ifOutErrors, "Errors"); 4417 } 4418 4419 static int 4420 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4421 { 4422 struct bge_softc *sc; 4423 uint32_t result; 4424 int offset; 4425 4426 sc = (struct bge_softc *)arg1; 4427 offset = arg2; 4428 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4429 offsetof(bge_hostaddr, bge_addr_lo)); 4430 return (sysctl_handle_int(oidp, &result, 0, req)); 4431 } 4432 4433 #ifdef BGE_REGISTER_DEBUG 4434 static int 4435 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4436 { 4437 struct bge_softc *sc; 4438 uint16_t *sbdata; 4439 int error; 4440 int result; 4441 int i, j; 4442 4443 result = -1; 4444 error = sysctl_handle_int(oidp, &result, 0, req); 4445 if (error || (req->newptr == NULL)) 4446 return (error); 4447 4448 if (result == 1) { 4449 sc = (struct bge_softc *)arg1; 4450 4451 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4452 printf("Status Block:\n"); 4453 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4454 printf("%06x:", i); 4455 for (j = 0; j < 8; j++) { 4456 printf(" %04x", sbdata[i]); 4457 i += 4; 4458 } 4459 printf("\n"); 4460 } 4461 4462 printf("Registers:\n"); 4463 for (i = 0x800; i < 0xA00; ) { 4464 printf("%06x:", i); 4465 for (j = 0; j < 8; j++) { 4466 printf(" %08x", CSR_READ_4(sc, i)); 4467 i += 4; 4468 } 4469 printf("\n"); 4470 } 4471 4472 printf("Hardware Flags:\n"); 4473 if (BGE_IS_575X_PLUS(sc)) 4474 printf(" - 575X Plus\n"); 4475 if (BGE_IS_5705_PLUS(sc)) 4476 printf(" - 5705 Plus\n"); 4477 if (BGE_IS_5714_FAMILY(sc)) 4478 printf(" - 5714 Family\n"); 4479 if (BGE_IS_5700_FAMILY(sc)) 4480 printf(" - 5700 Family\n"); 4481 if (sc->bge_flags & BGE_FLAG_JUMBO) 4482 printf(" - Supports Jumbo Frames\n"); 4483 if (sc->bge_flags & BGE_FLAG_PCIX) 4484 printf(" - PCI-X Bus\n"); 4485 if (sc->bge_flags & BGE_FLAG_PCIE) 4486 printf(" - PCI Express Bus\n"); 4487 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4488 printf(" - No 3 LEDs\n"); 4489 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4490 printf(" - RX Alignment Bug\n"); 4491 } 4492 4493 return (error); 4494 } 4495 4496 static int 4497 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4498 { 4499 struct bge_softc *sc; 4500 int error; 4501 uint16_t result; 4502 uint32_t val; 4503 4504 result = -1; 4505 error = sysctl_handle_int(oidp, &result, 0, req); 4506 if (error || (req->newptr == NULL)) 4507 return (error); 4508 4509 if (result < 0x8000) { 4510 sc = (struct bge_softc *)arg1; 4511 val = CSR_READ_4(sc, result); 4512 printf("reg 0x%06X = 0x%08X\n", result, val); 4513 } 4514 4515 return (error); 4516 } 4517 4518 static int 4519 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4520 { 4521 struct bge_softc *sc; 4522 int error; 4523 uint16_t result; 4524 uint32_t val; 4525 4526 result = -1; 4527 error = sysctl_handle_int(oidp, &result, 0, req); 4528 if (error || (req->newptr == NULL)) 4529 return (error); 4530 4531 if (result < 0x8000) { 4532 sc = (struct bge_softc *)arg1; 4533 val = bge_readmem_ind(sc, result); 4534 printf("mem 0x%06X = 0x%08X\n", result, val); 4535 } 4536 4537 return (error); 4538 } 4539 #endif 4540