xref: /freebsd/sys/dev/bge/if_bge.c (revision 13de33a5dc2304b13d595d75d48c51793958474f)
1 /*-
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36 
37 /*
38  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
39  *
40  * The Broadcom BCM5700 is based on technology originally developed by
41  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45  * frames, highly configurable RX filtering, and 16 RX and TX queues
46  * (which, along with RX filter rules, can be used for QOS applications).
47  * Other features, such as TCP segmentation, may be available as part
48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49  * firmware images can be stored in hardware and need not be compiled
50  * into the driver.
51  *
52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54  *
55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57  * does not support external SSRAM.
58  *
59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
60  * brand name, which is functionally similar but lacks PCI-X support.
61  *
62  * Without external SSRAM, you can only have at most 4 TX rings,
63  * and the use of the mini RX ring is disabled. This seems to imply
64  * that these features are simply not available on the BCM5701. As a
65  * result, this driver does not implement any support for the mini RX
66  * ring.
67  */
68 
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72 
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
84 
85 #include <net/if.h>
86 #include <net/if_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
91 
92 #include <net/bpf.h>
93 
94 #include <net/if_types.h>
95 #include <net/if_vlan_var.h>
96 
97 #include <netinet/in_systm.h>
98 #include <netinet/in.h>
99 #include <netinet/ip.h>
100 #include <netinet/tcp.h>
101 
102 #include <machine/bus.h>
103 #include <machine/resource.h>
104 #include <sys/bus.h>
105 #include <sys/rman.h>
106 
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109 #include "miidevs.h"
110 #include <dev/mii/brgphyreg.h>
111 
112 #ifdef __sparc64__
113 #include <dev/ofw/ofw_bus.h>
114 #include <dev/ofw/openfirm.h>
115 #include <machine/ofw_machdep.h>
116 #include <machine/ver.h>
117 #endif
118 
119 #include <dev/pci/pcireg.h>
120 #include <dev/pci/pcivar.h>
121 
122 #include <dev/bge/if_bgereg.h>
123 
124 #define	BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP)
125 #define	ETHER_MIN_NOPAD		(ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126 
127 MODULE_DEPEND(bge, pci, 1, 1, 1);
128 MODULE_DEPEND(bge, ether, 1, 1, 1);
129 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130 
131 /* "device miibus" required.  See GENERIC if you get errors here. */
132 #include "miibus_if.h"
133 
134 /*
135  * Various supported device vendors/types and their names. Note: the
136  * spec seems to indicate that the hardware still has Alteon's vendor
137  * ID burned into it, though it will always be overriden by the vendor
138  * ID in the EEPROM. Just to be safe, we cover all possibilities.
139  */
140 static const struct bge_type {
141 	uint16_t	bge_vid;
142 	uint16_t	bge_did;
143 } bge_devs[] = {
144 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5700 },
145 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5701 },
146 
147 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1000 },
148 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1002 },
149 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC9100 },
150 
151 	{ APPLE_VENDORID,	APPLE_DEVICE_BCM5701 },
152 
153 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5700 },
154 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5701 },
155 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702 },
156 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702_ALT },
157 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702X },
158 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703 },
159 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703_ALT },
160 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703X },
161 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704C },
162 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S },
163 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S_ALT },
164 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705 },
165 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705F },
166 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705K },
167 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M },
168 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M_ALT },
169 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714C },
170 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714S },
171 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715 },
172 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715S },
173 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5717 },
174 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5718 },
175 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5719 },
176 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5720 },
177 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5721 },
178 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5722 },
179 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5723 },
180 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5725 },
181 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5727 },
182 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750 },
183 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750M },
184 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751 },
185 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751F },
186 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751M },
187 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752 },
188 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752M },
189 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753 },
190 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753F },
191 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753M },
192 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754 },
193 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754M },
194 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755 },
195 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755M },
196 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5756 },
197 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761 },
198 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761E },
199 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761S },
200 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761SE },
201 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5762 },
202 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5764 },
203 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780 },
204 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780S },
205 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5781 },
206 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5782 },
207 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5784 },
208 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785F },
209 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785G },
210 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5786 },
211 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787 },
212 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787F },
213 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787M },
214 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5788 },
215 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5789 },
216 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901 },
217 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901A2 },
218 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5903M },
219 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906 },
220 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906M },
221 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57760 },
222 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57761 },
223 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57762 },
224 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57764 },
225 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57765 },
226 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57766 },
227 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57767 },
228 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57780 },
229 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57781 },
230 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57782 },
231 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57785 },
232 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57786 },
233 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57787 },
234 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57788 },
235 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57790 },
236 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57791 },
237 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57795 },
238 
239 	{ SK_VENDORID,		SK_DEVICEID_ALTIMA },
240 
241 	{ TC_VENDORID,		TC_DEVICEID_3C996 },
242 
243 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE4 },
244 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE5 },
245 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PP250450 },
246 
247 	{ 0, 0 }
248 };
249 
250 static const struct bge_vendor {
251 	uint16_t	v_id;
252 	const char	*v_name;
253 } bge_vendors[] = {
254 	{ ALTEON_VENDORID,	"Alteon" },
255 	{ ALTIMA_VENDORID,	"Altima" },
256 	{ APPLE_VENDORID,	"Apple" },
257 	{ BCOM_VENDORID,	"Broadcom" },
258 	{ SK_VENDORID,		"SysKonnect" },
259 	{ TC_VENDORID,		"3Com" },
260 	{ FJTSU_VENDORID,	"Fujitsu" },
261 
262 	{ 0, NULL }
263 };
264 
265 static const struct bge_revision {
266 	uint32_t	br_chipid;
267 	const char	*br_name;
268 } bge_revisions[] = {
269 	{ BGE_CHIPID_BCM5700_A0,	"BCM5700 A0" },
270 	{ BGE_CHIPID_BCM5700_A1,	"BCM5700 A1" },
271 	{ BGE_CHIPID_BCM5700_B0,	"BCM5700 B0" },
272 	{ BGE_CHIPID_BCM5700_B1,	"BCM5700 B1" },
273 	{ BGE_CHIPID_BCM5700_B2,	"BCM5700 B2" },
274 	{ BGE_CHIPID_BCM5700_B3,	"BCM5700 B3" },
275 	{ BGE_CHIPID_BCM5700_ALTIMA,	"BCM5700 Altima" },
276 	{ BGE_CHIPID_BCM5700_C0,	"BCM5700 C0" },
277 	{ BGE_CHIPID_BCM5701_A0,	"BCM5701 A0" },
278 	{ BGE_CHIPID_BCM5701_B0,	"BCM5701 B0" },
279 	{ BGE_CHIPID_BCM5701_B2,	"BCM5701 B2" },
280 	{ BGE_CHIPID_BCM5701_B5,	"BCM5701 B5" },
281 	{ BGE_CHIPID_BCM5703_A0,	"BCM5703 A0" },
282 	{ BGE_CHIPID_BCM5703_A1,	"BCM5703 A1" },
283 	{ BGE_CHIPID_BCM5703_A2,	"BCM5703 A2" },
284 	{ BGE_CHIPID_BCM5703_A3,	"BCM5703 A3" },
285 	{ BGE_CHIPID_BCM5703_B0,	"BCM5703 B0" },
286 	{ BGE_CHIPID_BCM5704_A0,	"BCM5704 A0" },
287 	{ BGE_CHIPID_BCM5704_A1,	"BCM5704 A1" },
288 	{ BGE_CHIPID_BCM5704_A2,	"BCM5704 A2" },
289 	{ BGE_CHIPID_BCM5704_A3,	"BCM5704 A3" },
290 	{ BGE_CHIPID_BCM5704_B0,	"BCM5704 B0" },
291 	{ BGE_CHIPID_BCM5705_A0,	"BCM5705 A0" },
292 	{ BGE_CHIPID_BCM5705_A1,	"BCM5705 A1" },
293 	{ BGE_CHIPID_BCM5705_A2,	"BCM5705 A2" },
294 	{ BGE_CHIPID_BCM5705_A3,	"BCM5705 A3" },
295 	{ BGE_CHIPID_BCM5750_A0,	"BCM5750 A0" },
296 	{ BGE_CHIPID_BCM5750_A1,	"BCM5750 A1" },
297 	{ BGE_CHIPID_BCM5750_A3,	"BCM5750 A3" },
298 	{ BGE_CHIPID_BCM5750_B0,	"BCM5750 B0" },
299 	{ BGE_CHIPID_BCM5750_B1,	"BCM5750 B1" },
300 	{ BGE_CHIPID_BCM5750_C0,	"BCM5750 C0" },
301 	{ BGE_CHIPID_BCM5750_C1,	"BCM5750 C1" },
302 	{ BGE_CHIPID_BCM5750_C2,	"BCM5750 C2" },
303 	{ BGE_CHIPID_BCM5714_A0,	"BCM5714 A0" },
304 	{ BGE_CHIPID_BCM5752_A0,	"BCM5752 A0" },
305 	{ BGE_CHIPID_BCM5752_A1,	"BCM5752 A1" },
306 	{ BGE_CHIPID_BCM5752_A2,	"BCM5752 A2" },
307 	{ BGE_CHIPID_BCM5714_B0,	"BCM5714 B0" },
308 	{ BGE_CHIPID_BCM5714_B3,	"BCM5714 B3" },
309 	{ BGE_CHIPID_BCM5715_A0,	"BCM5715 A0" },
310 	{ BGE_CHIPID_BCM5715_A1,	"BCM5715 A1" },
311 	{ BGE_CHIPID_BCM5715_A3,	"BCM5715 A3" },
312 	{ BGE_CHIPID_BCM5717_A0,	"BCM5717 A0" },
313 	{ BGE_CHIPID_BCM5717_B0,	"BCM5717 B0" },
314 	{ BGE_CHIPID_BCM5719_A0,	"BCM5719 A0" },
315 	{ BGE_CHIPID_BCM5720_A0,	"BCM5720 A0" },
316 	{ BGE_CHIPID_BCM5755_A0,	"BCM5755 A0" },
317 	{ BGE_CHIPID_BCM5755_A1,	"BCM5755 A1" },
318 	{ BGE_CHIPID_BCM5755_A2,	"BCM5755 A2" },
319 	{ BGE_CHIPID_BCM5722_A0,	"BCM5722 A0" },
320 	{ BGE_CHIPID_BCM5761_A0,	"BCM5761 A0" },
321 	{ BGE_CHIPID_BCM5761_A1,	"BCM5761 A1" },
322 	{ BGE_CHIPID_BCM5762_A0,	"BCM5762 A0" },
323 	{ BGE_CHIPID_BCM5784_A0,	"BCM5784 A0" },
324 	{ BGE_CHIPID_BCM5784_A1,	"BCM5784 A1" },
325 	/* 5754 and 5787 share the same ASIC ID */
326 	{ BGE_CHIPID_BCM5787_A0,	"BCM5754/5787 A0" },
327 	{ BGE_CHIPID_BCM5787_A1,	"BCM5754/5787 A1" },
328 	{ BGE_CHIPID_BCM5787_A2,	"BCM5754/5787 A2" },
329 	{ BGE_CHIPID_BCM5906_A1,	"BCM5906 A1" },
330 	{ BGE_CHIPID_BCM5906_A2,	"BCM5906 A2" },
331 	{ BGE_CHIPID_BCM57765_A0,	"BCM57765 A0" },
332 	{ BGE_CHIPID_BCM57765_B0,	"BCM57765 B0" },
333 	{ BGE_CHIPID_BCM57780_A0,	"BCM57780 A0" },
334 	{ BGE_CHIPID_BCM57780_A1,	"BCM57780 A1" },
335 
336 	{ 0, NULL }
337 };
338 
339 /*
340  * Some defaults for major revisions, so that newer steppings
341  * that we don't know about have a shot at working.
342  */
343 static const struct bge_revision bge_majorrevs[] = {
344 	{ BGE_ASICREV_BCM5700,		"unknown BCM5700" },
345 	{ BGE_ASICREV_BCM5701,		"unknown BCM5701" },
346 	{ BGE_ASICREV_BCM5703,		"unknown BCM5703" },
347 	{ BGE_ASICREV_BCM5704,		"unknown BCM5704" },
348 	{ BGE_ASICREV_BCM5705,		"unknown BCM5705" },
349 	{ BGE_ASICREV_BCM5750,		"unknown BCM5750" },
350 	{ BGE_ASICREV_BCM5714_A0,	"unknown BCM5714" },
351 	{ BGE_ASICREV_BCM5752,		"unknown BCM5752" },
352 	{ BGE_ASICREV_BCM5780,		"unknown BCM5780" },
353 	{ BGE_ASICREV_BCM5714,		"unknown BCM5714" },
354 	{ BGE_ASICREV_BCM5755,		"unknown BCM5755" },
355 	{ BGE_ASICREV_BCM5761,		"unknown BCM5761" },
356 	{ BGE_ASICREV_BCM5784,		"unknown BCM5784" },
357 	{ BGE_ASICREV_BCM5785,		"unknown BCM5785" },
358 	/* 5754 and 5787 share the same ASIC ID */
359 	{ BGE_ASICREV_BCM5787,		"unknown BCM5754/5787" },
360 	{ BGE_ASICREV_BCM5906,		"unknown BCM5906" },
361 	{ BGE_ASICREV_BCM57765,		"unknown BCM57765" },
362 	{ BGE_ASICREV_BCM57766,		"unknown BCM57766" },
363 	{ BGE_ASICREV_BCM57780,		"unknown BCM57780" },
364 	{ BGE_ASICREV_BCM5717,		"unknown BCM5717" },
365 	{ BGE_ASICREV_BCM5719,		"unknown BCM5719" },
366 	{ BGE_ASICREV_BCM5720,		"unknown BCM5720" },
367 	{ BGE_ASICREV_BCM5762,		"unknown BCM5762" },
368 
369 	{ 0, NULL }
370 };
371 
372 #define	BGE_IS_JUMBO_CAPABLE(sc)	((sc)->bge_flags & BGE_FLAG_JUMBO)
373 #define	BGE_IS_5700_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
374 #define	BGE_IS_5705_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5705_PLUS)
375 #define	BGE_IS_5714_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
376 #define	BGE_IS_575X_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_575X_PLUS)
377 #define	BGE_IS_5755_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5755_PLUS)
378 #define	BGE_IS_5717_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5717_PLUS)
379 #define	BGE_IS_57765_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_57765_PLUS)
380 
381 static uint32_t bge_chipid(device_t);
382 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
383 static const struct bge_revision * bge_lookup_rev(uint32_t);
384 
385 typedef int	(*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
386 
387 static int bge_probe(device_t);
388 static int bge_attach(device_t);
389 static int bge_detach(device_t);
390 static int bge_suspend(device_t);
391 static int bge_resume(device_t);
392 static void bge_release_resources(struct bge_softc *);
393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
394 static int bge_dma_alloc(struct bge_softc *);
395 static void bge_dma_free(struct bge_softc *);
396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
397     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
398 
399 static void bge_devinfo(struct bge_softc *);
400 static int bge_mbox_reorder(struct bge_softc *);
401 
402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
407 
408 static void bge_txeof(struct bge_softc *, uint16_t);
409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
410 static int bge_rxeof(struct bge_softc *, uint16_t, int);
411 
412 static void bge_asf_driver_up (struct bge_softc *);
413 static void bge_tick(void *);
414 static void bge_stats_clear_regs(struct bge_softc *);
415 static void bge_stats_update(struct bge_softc *);
416 static void bge_stats_update_regs(struct bge_softc *);
417 static struct mbuf *bge_check_short_dma(struct mbuf *);
418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
419     uint16_t *, uint16_t *);
420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
421 
422 static void bge_intr(void *);
423 static int bge_msi_intr(void *);
424 static void bge_intr_task(void *, int);
425 static void bge_start_locked(struct ifnet *);
426 static void bge_start(struct ifnet *);
427 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
428 static void bge_init_locked(struct bge_softc *);
429 static void bge_init(void *);
430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
431 static void bge_stop(struct bge_softc *);
432 static void bge_watchdog(struct bge_softc *);
433 static int bge_shutdown(device_t);
434 static int bge_ifmedia_upd_locked(struct ifnet *);
435 static int bge_ifmedia_upd(struct ifnet *);
436 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
437 
438 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
439 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
440 
441 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
442 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
443 
444 static void bge_setpromisc(struct bge_softc *);
445 static void bge_setmulti(struct bge_softc *);
446 static void bge_setvlan(struct bge_softc *);
447 
448 static __inline void bge_rxreuse_std(struct bge_softc *, int);
449 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
450 static int bge_newbuf_std(struct bge_softc *, int);
451 static int bge_newbuf_jumbo(struct bge_softc *, int);
452 static int bge_init_rx_ring_std(struct bge_softc *);
453 static void bge_free_rx_ring_std(struct bge_softc *);
454 static int bge_init_rx_ring_jumbo(struct bge_softc *);
455 static void bge_free_rx_ring_jumbo(struct bge_softc *);
456 static void bge_free_tx_ring(struct bge_softc *);
457 static int bge_init_tx_ring(struct bge_softc *);
458 
459 static int bge_chipinit(struct bge_softc *);
460 static int bge_blockinit(struct bge_softc *);
461 static uint32_t bge_dma_swap_options(struct bge_softc *);
462 
463 static int bge_has_eaddr(struct bge_softc *);
464 static uint32_t bge_readmem_ind(struct bge_softc *, int);
465 static void bge_writemem_ind(struct bge_softc *, int, int);
466 static void bge_writembx(struct bge_softc *, int, int);
467 #ifdef notdef
468 static uint32_t bge_readreg_ind(struct bge_softc *, int);
469 #endif
470 static void bge_writemem_direct(struct bge_softc *, int, int);
471 static void bge_writereg_ind(struct bge_softc *, int, int);
472 
473 static int bge_miibus_readreg(device_t, int, int);
474 static int bge_miibus_writereg(device_t, int, int, int);
475 static void bge_miibus_statchg(device_t);
476 #ifdef DEVICE_POLLING
477 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
478 #endif
479 
480 #define	BGE_RESET_SHUTDOWN	0
481 #define	BGE_RESET_START		1
482 #define	BGE_RESET_SUSPEND	2
483 static void bge_sig_post_reset(struct bge_softc *, int);
484 static void bge_sig_legacy(struct bge_softc *, int);
485 static void bge_sig_pre_reset(struct bge_softc *, int);
486 static void bge_stop_fw(struct bge_softc *);
487 static int bge_reset(struct bge_softc *);
488 static void bge_link_upd(struct bge_softc *);
489 
490 static void bge_ape_lock_init(struct bge_softc *);
491 static void bge_ape_read_fw_ver(struct bge_softc *);
492 static int bge_ape_lock(struct bge_softc *, int);
493 static void bge_ape_unlock(struct bge_softc *, int);
494 static void bge_ape_send_event(struct bge_softc *, uint32_t);
495 static void bge_ape_driver_state_change(struct bge_softc *, int);
496 
497 /*
498  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
499  * leak information to untrusted users.  It is also known to cause alignment
500  * traps on certain architectures.
501  */
502 #ifdef BGE_REGISTER_DEBUG
503 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
504 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
505 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
506 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
507 #endif
508 static void bge_add_sysctls(struct bge_softc *);
509 static void bge_add_sysctl_stats_regs(struct bge_softc *,
510     struct sysctl_ctx_list *, struct sysctl_oid_list *);
511 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
512     struct sysctl_oid_list *);
513 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
514 
515 static device_method_t bge_methods[] = {
516 	/* Device interface */
517 	DEVMETHOD(device_probe,		bge_probe),
518 	DEVMETHOD(device_attach,	bge_attach),
519 	DEVMETHOD(device_detach,	bge_detach),
520 	DEVMETHOD(device_shutdown,	bge_shutdown),
521 	DEVMETHOD(device_suspend,	bge_suspend),
522 	DEVMETHOD(device_resume,	bge_resume),
523 
524 	/* MII interface */
525 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
526 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
527 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
528 
529 	DEVMETHOD_END
530 };
531 
532 static driver_t bge_driver = {
533 	"bge",
534 	bge_methods,
535 	sizeof(struct bge_softc)
536 };
537 
538 static devclass_t bge_devclass;
539 
540 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
541 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
542 
543 static int bge_allow_asf = 1;
544 
545 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
546 
547 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
548 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
549 	"Allow ASF mode if available");
550 
551 #define	SPARC64_BLADE_1500_MODEL	"SUNW,Sun-Blade-1500"
552 #define	SPARC64_BLADE_1500_PATH_BGE	"/pci@1f,700000/network@2"
553 #define	SPARC64_BLADE_2500_MODEL	"SUNW,Sun-Blade-2500"
554 #define	SPARC64_BLADE_2500_PATH_BGE	"/pci@1c,600000/network@3"
555 #define	SPARC64_OFW_SUBVENDOR		"subsystem-vendor-id"
556 
557 static int
558 bge_has_eaddr(struct bge_softc *sc)
559 {
560 #ifdef __sparc64__
561 	char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
562 	device_t dev;
563 	uint32_t subvendor;
564 
565 	dev = sc->bge_dev;
566 
567 	/*
568 	 * The on-board BGEs found in sun4u machines aren't fitted with
569 	 * an EEPROM which means that we have to obtain the MAC address
570 	 * via OFW and that some tests will always fail.  We distinguish
571 	 * such BGEs by the subvendor ID, which also has to be obtained
572 	 * from OFW instead of the PCI configuration space as the latter
573 	 * indicates Broadcom as the subvendor of the netboot interface.
574 	 * For early Blade 1500 and 2500 we even have to check the OFW
575 	 * device path as the subvendor ID always defaults to Broadcom
576 	 * there.
577 	 */
578 	if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
579 	    &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
580 	    (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
581 		return (0);
582 	memset(buf, 0, sizeof(buf));
583 	if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
584 		if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
585 		    strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
586 			return (0);
587 		if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
588 		    strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
589 			return (0);
590 	}
591 #endif
592 	return (1);
593 }
594 
595 static uint32_t
596 bge_readmem_ind(struct bge_softc *sc, int off)
597 {
598 	device_t dev;
599 	uint32_t val;
600 
601 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
602 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
603 		return (0);
604 
605 	dev = sc->bge_dev;
606 
607 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
608 	val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
609 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
610 	return (val);
611 }
612 
613 static void
614 bge_writemem_ind(struct bge_softc *sc, int off, int val)
615 {
616 	device_t dev;
617 
618 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
619 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
620 		return;
621 
622 	dev = sc->bge_dev;
623 
624 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
625 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
626 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
627 }
628 
629 #ifdef notdef
630 static uint32_t
631 bge_readreg_ind(struct bge_softc *sc, int off)
632 {
633 	device_t dev;
634 
635 	dev = sc->bge_dev;
636 
637 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
638 	return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
639 }
640 #endif
641 
642 static void
643 bge_writereg_ind(struct bge_softc *sc, int off, int val)
644 {
645 	device_t dev;
646 
647 	dev = sc->bge_dev;
648 
649 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
650 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
651 }
652 
653 static void
654 bge_writemem_direct(struct bge_softc *sc, int off, int val)
655 {
656 	CSR_WRITE_4(sc, off, val);
657 }
658 
659 static void
660 bge_writembx(struct bge_softc *sc, int off, int val)
661 {
662 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
663 		off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
664 
665 	CSR_WRITE_4(sc, off, val);
666 	if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
667 		CSR_READ_4(sc, off);
668 }
669 
670 /*
671  * Clear all stale locks and select the lock for this driver instance.
672  */
673 static void
674 bge_ape_lock_init(struct bge_softc *sc)
675 {
676 	uint32_t bit, regbase;
677 	int i;
678 
679 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
680 		regbase = BGE_APE_LOCK_GRANT;
681 	else
682 		regbase = BGE_APE_PER_LOCK_GRANT;
683 
684 	/* Clear any stale locks. */
685 	for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
686 		switch (i) {
687 		case BGE_APE_LOCK_PHY0:
688 		case BGE_APE_LOCK_PHY1:
689 		case BGE_APE_LOCK_PHY2:
690 		case BGE_APE_LOCK_PHY3:
691 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
692 			break;
693 		default:
694 			if (sc->bge_func_addr == 0)
695 				bit = BGE_APE_LOCK_GRANT_DRIVER0;
696 			else
697 				bit = (1 << sc->bge_func_addr);
698 		}
699 		APE_WRITE_4(sc, regbase + 4 * i, bit);
700 	}
701 
702 	/* Select the PHY lock based on the device's function number. */
703 	switch (sc->bge_func_addr) {
704 	case 0:
705 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
706 		break;
707 	case 1:
708 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
709 		break;
710 	case 2:
711 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
712 		break;
713 	case 3:
714 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
715 		break;
716 	default:
717 		device_printf(sc->bge_dev,
718 		    "PHY lock not supported on this function\n");
719 	}
720 }
721 
722 /*
723  * Check for APE firmware, set flags, and print version info.
724  */
725 static void
726 bge_ape_read_fw_ver(struct bge_softc *sc)
727 {
728 	const char *fwtype;
729 	uint32_t apedata, features;
730 
731 	/* Check for a valid APE signature in shared memory. */
732 	apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
733 	if (apedata != BGE_APE_SEG_SIG_MAGIC) {
734 		sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
735 		return;
736 	}
737 
738 	/* Check if APE firmware is running. */
739 	apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
740 	if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
741 		device_printf(sc->bge_dev, "APE signature found "
742 		    "but FW status not ready! 0x%08x\n", apedata);
743 		return;
744 	}
745 
746 	sc->bge_mfw_flags |= BGE_MFW_ON_APE;
747 
748 	/* Fetch the APE firwmare type and version. */
749 	apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
750 	features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
751 	if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
752 		sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
753 		fwtype = "NCSI";
754 	} else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
755 		sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
756 		fwtype = "DASH";
757 	} else
758 		fwtype = "UNKN";
759 
760 	/* Print the APE firmware version. */
761 	device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
762 	    fwtype,
763 	    (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
764 	    (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
765 	    (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
766 	    (apedata & BGE_APE_FW_VERSION_BLDMSK));
767 }
768 
769 static int
770 bge_ape_lock(struct bge_softc *sc, int locknum)
771 {
772 	uint32_t bit, gnt, req, status;
773 	int i, off;
774 
775 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
776 		return (0);
777 
778 	/* Lock request/grant registers have different bases. */
779 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
780 		req = BGE_APE_LOCK_REQ;
781 		gnt = BGE_APE_LOCK_GRANT;
782 	} else {
783 		req = BGE_APE_PER_LOCK_REQ;
784 		gnt = BGE_APE_PER_LOCK_GRANT;
785 	}
786 
787 	off = 4 * locknum;
788 
789 	switch (locknum) {
790 	case BGE_APE_LOCK_GPIO:
791 		/* Lock required when using GPIO. */
792 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
793 			return (0);
794 		if (sc->bge_func_addr == 0)
795 			bit = BGE_APE_LOCK_REQ_DRIVER0;
796 		else
797 			bit = (1 << sc->bge_func_addr);
798 		break;
799 	case BGE_APE_LOCK_GRC:
800 		/* Lock required to reset the device. */
801 		if (sc->bge_func_addr == 0)
802 			bit = BGE_APE_LOCK_REQ_DRIVER0;
803 		else
804 			bit = (1 << sc->bge_func_addr);
805 		break;
806 	case BGE_APE_LOCK_MEM:
807 		/* Lock required when accessing certain APE memory. */
808 		if (sc->bge_func_addr == 0)
809 			bit = BGE_APE_LOCK_REQ_DRIVER0;
810 		else
811 			bit = (1 << sc->bge_func_addr);
812 		break;
813 	case BGE_APE_LOCK_PHY0:
814 	case BGE_APE_LOCK_PHY1:
815 	case BGE_APE_LOCK_PHY2:
816 	case BGE_APE_LOCK_PHY3:
817 		/* Lock required when accessing PHYs. */
818 		bit = BGE_APE_LOCK_REQ_DRIVER0;
819 		break;
820 	default:
821 		return (EINVAL);
822 	}
823 
824 	/* Request a lock. */
825 	APE_WRITE_4(sc, req + off, bit);
826 
827 	/* Wait up to 1 second to acquire lock. */
828 	for (i = 0; i < 20000; i++) {
829 		status = APE_READ_4(sc, gnt + off);
830 		if (status == bit)
831 			break;
832 		DELAY(50);
833 	}
834 
835 	/* Handle any errors. */
836 	if (status != bit) {
837 		device_printf(sc->bge_dev, "APE lock %d request failed! "
838 		    "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
839 		    locknum, req + off, bit & 0xFFFF, gnt + off,
840 		    status & 0xFFFF);
841 		/* Revoke the lock request. */
842 		APE_WRITE_4(sc, gnt + off, bit);
843 		return (EBUSY);
844 	}
845 
846 	return (0);
847 }
848 
849 static void
850 bge_ape_unlock(struct bge_softc *sc, int locknum)
851 {
852 	uint32_t bit, gnt;
853 	int off;
854 
855 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
856 		return;
857 
858 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
859 		gnt = BGE_APE_LOCK_GRANT;
860 	else
861 		gnt = BGE_APE_PER_LOCK_GRANT;
862 
863 	off = 4 * locknum;
864 
865 	switch (locknum) {
866 	case BGE_APE_LOCK_GPIO:
867 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
868 			return;
869 		if (sc->bge_func_addr == 0)
870 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
871 		else
872 			bit = (1 << sc->bge_func_addr);
873 		break;
874 	case BGE_APE_LOCK_GRC:
875 		if (sc->bge_func_addr == 0)
876 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
877 		else
878 			bit = (1 << sc->bge_func_addr);
879 		break;
880 	case BGE_APE_LOCK_MEM:
881 		if (sc->bge_func_addr == 0)
882 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
883 		else
884 			bit = (1 << sc->bge_func_addr);
885 		break;
886 	case BGE_APE_LOCK_PHY0:
887 	case BGE_APE_LOCK_PHY1:
888 	case BGE_APE_LOCK_PHY2:
889 	case BGE_APE_LOCK_PHY3:
890 		bit = BGE_APE_LOCK_GRANT_DRIVER0;
891 		break;
892 	default:
893 		return;
894 	}
895 
896 	APE_WRITE_4(sc, gnt + off, bit);
897 }
898 
899 /*
900  * Send an event to the APE firmware.
901  */
902 static void
903 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
904 {
905 	uint32_t apedata;
906 	int i;
907 
908 	/* NCSI does not support APE events. */
909 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
910 		return;
911 
912 	/* Wait up to 1ms for APE to service previous event. */
913 	for (i = 10; i > 0; i--) {
914 		if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
915 			break;
916 		apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
917 		if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
918 			APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
919 			    BGE_APE_EVENT_STATUS_EVENT_PENDING);
920 			bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
921 			APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
922 			break;
923 		}
924 		bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
925 		DELAY(100);
926 	}
927 	if (i == 0)
928 		device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
929 		    event);
930 }
931 
932 static void
933 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
934 {
935 	uint32_t apedata, event;
936 
937 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
938 		return;
939 
940 	switch (kind) {
941 	case BGE_RESET_START:
942 		/* If this is the first load, clear the load counter. */
943 		apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
944 		if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
945 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
946 		else {
947 			apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
948 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
949 		}
950 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
951 		    BGE_APE_HOST_SEG_SIG_MAGIC);
952 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
953 		    BGE_APE_HOST_SEG_LEN_MAGIC);
954 
955 		/* Add some version info if bge(4) supports it. */
956 		APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
957 		    BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
958 		APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
959 		    BGE_APE_HOST_BEHAV_NO_PHYLOCK);
960 		APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
961 		    BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
962 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
963 		    BGE_APE_HOST_DRVR_STATE_START);
964 		event = BGE_APE_EVENT_STATUS_STATE_START;
965 		break;
966 	case BGE_RESET_SHUTDOWN:
967 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
968 		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
969 		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
970 		break;
971 	case BGE_RESET_SUSPEND:
972 		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
973 		break;
974 	default:
975 		return;
976 	}
977 
978 	bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
979 	    BGE_APE_EVENT_STATUS_STATE_CHNGE);
980 }
981 
982 /*
983  * Map a single buffer address.
984  */
985 
986 static void
987 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
988 {
989 	struct bge_dmamap_arg *ctx;
990 
991 	if (error)
992 		return;
993 
994 	KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
995 
996 	ctx = arg;
997 	ctx->bge_busaddr = segs->ds_addr;
998 }
999 
1000 static uint8_t
1001 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1002 {
1003 	uint32_t access, byte = 0;
1004 	int i;
1005 
1006 	/* Lock. */
1007 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1008 	for (i = 0; i < 8000; i++) {
1009 		if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1010 			break;
1011 		DELAY(20);
1012 	}
1013 	if (i == 8000)
1014 		return (1);
1015 
1016 	/* Enable access. */
1017 	access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1018 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1019 
1020 	CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1021 	CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1022 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1023 		DELAY(10);
1024 		if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1025 			DELAY(10);
1026 			break;
1027 		}
1028 	}
1029 
1030 	if (i == BGE_TIMEOUT * 10) {
1031 		if_printf(sc->bge_ifp, "nvram read timed out\n");
1032 		return (1);
1033 	}
1034 
1035 	/* Get result. */
1036 	byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1037 
1038 	*dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1039 
1040 	/* Disable access. */
1041 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1042 
1043 	/* Unlock. */
1044 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1045 	CSR_READ_4(sc, BGE_NVRAM_SWARB);
1046 
1047 	return (0);
1048 }
1049 
1050 /*
1051  * Read a sequence of bytes from NVRAM.
1052  */
1053 static int
1054 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1055 {
1056 	int err = 0, i;
1057 	uint8_t byte = 0;
1058 
1059 	if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1060 		return (1);
1061 
1062 	for (i = 0; i < cnt; i++) {
1063 		err = bge_nvram_getbyte(sc, off + i, &byte);
1064 		if (err)
1065 			break;
1066 		*(dest + i) = byte;
1067 	}
1068 
1069 	return (err ? 1 : 0);
1070 }
1071 
1072 /*
1073  * Read a byte of data stored in the EEPROM at address 'addr.' The
1074  * BCM570x supports both the traditional bitbang interface and an
1075  * auto access interface for reading the EEPROM. We use the auto
1076  * access method.
1077  */
1078 static uint8_t
1079 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1080 {
1081 	int i;
1082 	uint32_t byte = 0;
1083 
1084 	/*
1085 	 * Enable use of auto EEPROM access so we can avoid
1086 	 * having to use the bitbang method.
1087 	 */
1088 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1089 
1090 	/* Reset the EEPROM, load the clock period. */
1091 	CSR_WRITE_4(sc, BGE_EE_ADDR,
1092 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1093 	DELAY(20);
1094 
1095 	/* Issue the read EEPROM command. */
1096 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1097 
1098 	/* Wait for completion */
1099 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1100 		DELAY(10);
1101 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1102 			break;
1103 	}
1104 
1105 	if (i == BGE_TIMEOUT * 10) {
1106 		device_printf(sc->bge_dev, "EEPROM read timed out\n");
1107 		return (1);
1108 	}
1109 
1110 	/* Get result. */
1111 	byte = CSR_READ_4(sc, BGE_EE_DATA);
1112 
1113 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1114 
1115 	return (0);
1116 }
1117 
1118 /*
1119  * Read a sequence of bytes from the EEPROM.
1120  */
1121 static int
1122 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1123 {
1124 	int i, error = 0;
1125 	uint8_t byte = 0;
1126 
1127 	for (i = 0; i < cnt; i++) {
1128 		error = bge_eeprom_getbyte(sc, off + i, &byte);
1129 		if (error)
1130 			break;
1131 		*(dest + i) = byte;
1132 	}
1133 
1134 	return (error ? 1 : 0);
1135 }
1136 
1137 static int
1138 bge_miibus_readreg(device_t dev, int phy, int reg)
1139 {
1140 	struct bge_softc *sc;
1141 	uint32_t val;
1142 	int i;
1143 
1144 	sc = device_get_softc(dev);
1145 
1146 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1147 		return (0);
1148 
1149 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1150 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1151 		CSR_WRITE_4(sc, BGE_MI_MODE,
1152 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1153 		DELAY(80);
1154 	}
1155 
1156 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1157 	    BGE_MIPHY(phy) | BGE_MIREG(reg));
1158 
1159 	/* Poll for the PHY register access to complete. */
1160 	for (i = 0; i < BGE_TIMEOUT; i++) {
1161 		DELAY(10);
1162 		val = CSR_READ_4(sc, BGE_MI_COMM);
1163 		if ((val & BGE_MICOMM_BUSY) == 0) {
1164 			DELAY(5);
1165 			val = CSR_READ_4(sc, BGE_MI_COMM);
1166 			break;
1167 		}
1168 	}
1169 
1170 	if (i == BGE_TIMEOUT) {
1171 		device_printf(sc->bge_dev,
1172 		    "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1173 		    phy, reg, val);
1174 		val = 0;
1175 	}
1176 
1177 	/* Restore the autopoll bit if necessary. */
1178 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1179 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1180 		DELAY(80);
1181 	}
1182 
1183 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1184 
1185 	if (val & BGE_MICOMM_READFAIL)
1186 		return (0);
1187 
1188 	return (val & 0xFFFF);
1189 }
1190 
1191 static int
1192 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1193 {
1194 	struct bge_softc *sc;
1195 	int i;
1196 
1197 	sc = device_get_softc(dev);
1198 
1199 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1200 	    (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1201 		return (0);
1202 
1203 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1204 		return (0);
1205 
1206 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1207 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1208 		CSR_WRITE_4(sc, BGE_MI_MODE,
1209 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1210 		DELAY(80);
1211 	}
1212 
1213 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1214 	    BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1215 
1216 	for (i = 0; i < BGE_TIMEOUT; i++) {
1217 		DELAY(10);
1218 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1219 			DELAY(5);
1220 			CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1221 			break;
1222 		}
1223 	}
1224 
1225 	/* Restore the autopoll bit if necessary. */
1226 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1227 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1228 		DELAY(80);
1229 	}
1230 
1231 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1232 
1233 	if (i == BGE_TIMEOUT)
1234 		device_printf(sc->bge_dev,
1235 		    "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1236 		    phy, reg, val);
1237 
1238 	return (0);
1239 }
1240 
1241 static void
1242 bge_miibus_statchg(device_t dev)
1243 {
1244 	struct bge_softc *sc;
1245 	struct mii_data *mii;
1246 	uint32_t mac_mode, rx_mode, tx_mode;
1247 
1248 	sc = device_get_softc(dev);
1249 	if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1250 		return;
1251 	mii = device_get_softc(sc->bge_miibus);
1252 
1253 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1254 	    (IFM_ACTIVE | IFM_AVALID)) {
1255 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
1256 		case IFM_10_T:
1257 		case IFM_100_TX:
1258 			sc->bge_link = 1;
1259 			break;
1260 		case IFM_1000_T:
1261 		case IFM_1000_SX:
1262 		case IFM_2500_SX:
1263 			if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1264 				sc->bge_link = 1;
1265 			else
1266 				sc->bge_link = 0;
1267 			break;
1268 		default:
1269 			sc->bge_link = 0;
1270 			break;
1271 		}
1272 	} else
1273 		sc->bge_link = 0;
1274 	if (sc->bge_link == 0)
1275 		return;
1276 
1277 	/*
1278 	 * APE firmware touches these registers to keep the MAC
1279 	 * connected to the outside world.  Try to keep the
1280 	 * accesses atomic.
1281 	 */
1282 
1283 	/* Set the port mode (MII/GMII) to match the link speed. */
1284 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1285 	    ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1286 	tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1287 	rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1288 
1289 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1290 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1291 		mac_mode |= BGE_PORTMODE_GMII;
1292 	else
1293 		mac_mode |= BGE_PORTMODE_MII;
1294 
1295 	/* Set MAC flow control behavior to match link flow control settings. */
1296 	tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1297 	rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1298 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1299 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1300 			tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1301 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1302 			rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1303 	} else
1304 		mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1305 
1306 	CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1307 	DELAY(40);
1308 	CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1309 	CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1310 }
1311 
1312 /*
1313  * Intialize a standard receive ring descriptor.
1314  */
1315 static int
1316 bge_newbuf_std(struct bge_softc *sc, int i)
1317 {
1318 	struct mbuf *m;
1319 	struct bge_rx_bd *r;
1320 	bus_dma_segment_t segs[1];
1321 	bus_dmamap_t map;
1322 	int error, nsegs;
1323 
1324 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1325 	    (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1326 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1327 		m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1328 		if (m == NULL)
1329 			return (ENOBUFS);
1330 		m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1331 	} else {
1332 		m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1333 		if (m == NULL)
1334 			return (ENOBUFS);
1335 		m->m_len = m->m_pkthdr.len = MCLBYTES;
1336 	}
1337 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1338 		m_adj(m, ETHER_ALIGN);
1339 
1340 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1341 	    sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1342 	if (error != 0) {
1343 		m_freem(m);
1344 		return (error);
1345 	}
1346 	if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1347 		bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1348 		    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1349 		bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1350 		    sc->bge_cdata.bge_rx_std_dmamap[i]);
1351 	}
1352 	map = sc->bge_cdata.bge_rx_std_dmamap[i];
1353 	sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1354 	sc->bge_cdata.bge_rx_std_sparemap = map;
1355 	sc->bge_cdata.bge_rx_std_chain[i] = m;
1356 	sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1357 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1358 	r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1359 	r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1360 	r->bge_flags = BGE_RXBDFLAG_END;
1361 	r->bge_len = segs[0].ds_len;
1362 	r->bge_idx = i;
1363 
1364 	bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1365 	    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1366 
1367 	return (0);
1368 }
1369 
1370 /*
1371  * Initialize a jumbo receive ring descriptor. This allocates
1372  * a jumbo buffer from the pool managed internally by the driver.
1373  */
1374 static int
1375 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1376 {
1377 	bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1378 	bus_dmamap_t map;
1379 	struct bge_extrx_bd *r;
1380 	struct mbuf *m;
1381 	int error, nsegs;
1382 
1383 	MGETHDR(m, M_NOWAIT, MT_DATA);
1384 	if (m == NULL)
1385 		return (ENOBUFS);
1386 
1387 	m_cljget(m, M_NOWAIT, MJUM9BYTES);
1388 	if (!(m->m_flags & M_EXT)) {
1389 		m_freem(m);
1390 		return (ENOBUFS);
1391 	}
1392 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1393 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1394 		m_adj(m, ETHER_ALIGN);
1395 
1396 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1397 	    sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1398 	if (error != 0) {
1399 		m_freem(m);
1400 		return (error);
1401 	}
1402 
1403 	if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1404 		bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1405 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1406 		bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1407 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1408 	}
1409 	map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1410 	sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1411 	    sc->bge_cdata.bge_rx_jumbo_sparemap;
1412 	sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1413 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1414 	sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1415 	sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1416 	sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1417 	sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1418 
1419 	/*
1420 	 * Fill in the extended RX buffer descriptor.
1421 	 */
1422 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1423 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1424 	r->bge_idx = i;
1425 	r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1426 	switch (nsegs) {
1427 	case 4:
1428 		r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1429 		r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1430 		r->bge_len3 = segs[3].ds_len;
1431 		sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1432 	case 3:
1433 		r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1434 		r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1435 		r->bge_len2 = segs[2].ds_len;
1436 		sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1437 	case 2:
1438 		r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1439 		r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1440 		r->bge_len1 = segs[1].ds_len;
1441 		sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1442 	case 1:
1443 		r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1444 		r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1445 		r->bge_len0 = segs[0].ds_len;
1446 		sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1447 		break;
1448 	default:
1449 		panic("%s: %d segments\n", __func__, nsegs);
1450 	}
1451 
1452 	bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1453 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1454 
1455 	return (0);
1456 }
1457 
1458 static int
1459 bge_init_rx_ring_std(struct bge_softc *sc)
1460 {
1461 	int error, i;
1462 
1463 	bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1464 	sc->bge_std = 0;
1465 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1466 		if ((error = bge_newbuf_std(sc, i)) != 0)
1467 			return (error);
1468 		BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1469 	}
1470 
1471 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1472 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1473 
1474 	sc->bge_std = 0;
1475 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1476 
1477 	return (0);
1478 }
1479 
1480 static void
1481 bge_free_rx_ring_std(struct bge_softc *sc)
1482 {
1483 	int i;
1484 
1485 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1486 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1487 			bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1488 			    sc->bge_cdata.bge_rx_std_dmamap[i],
1489 			    BUS_DMASYNC_POSTREAD);
1490 			bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1491 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
1492 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1493 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1494 		}
1495 		bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1496 		    sizeof(struct bge_rx_bd));
1497 	}
1498 }
1499 
1500 static int
1501 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1502 {
1503 	struct bge_rcb *rcb;
1504 	int error, i;
1505 
1506 	bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1507 	sc->bge_jumbo = 0;
1508 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1509 		if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1510 			return (error);
1511 		BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1512 	}
1513 
1514 	bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1515 	    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1516 
1517 	sc->bge_jumbo = 0;
1518 
1519 	/* Enable the jumbo receive producer ring. */
1520 	rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1521 	rcb->bge_maxlen_flags =
1522 	    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1523 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1524 
1525 	bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1526 
1527 	return (0);
1528 }
1529 
1530 static void
1531 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1532 {
1533 	int i;
1534 
1535 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1536 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1537 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1538 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1539 			    BUS_DMASYNC_POSTREAD);
1540 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1541 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1542 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1543 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1544 		}
1545 		bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1546 		    sizeof(struct bge_extrx_bd));
1547 	}
1548 }
1549 
1550 static void
1551 bge_free_tx_ring(struct bge_softc *sc)
1552 {
1553 	int i;
1554 
1555 	if (sc->bge_ldata.bge_tx_ring == NULL)
1556 		return;
1557 
1558 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1559 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1560 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1561 			    sc->bge_cdata.bge_tx_dmamap[i],
1562 			    BUS_DMASYNC_POSTWRITE);
1563 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1564 			    sc->bge_cdata.bge_tx_dmamap[i]);
1565 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
1566 			sc->bge_cdata.bge_tx_chain[i] = NULL;
1567 		}
1568 		bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1569 		    sizeof(struct bge_tx_bd));
1570 	}
1571 }
1572 
1573 static int
1574 bge_init_tx_ring(struct bge_softc *sc)
1575 {
1576 	sc->bge_txcnt = 0;
1577 	sc->bge_tx_saved_considx = 0;
1578 
1579 	bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1580 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1581 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1582 
1583 	/* Initialize transmit producer index for host-memory send ring. */
1584 	sc->bge_tx_prodidx = 0;
1585 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1586 
1587 	/* 5700 b2 errata */
1588 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1589 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1590 
1591 	/* NIC-memory send ring not used; initialize to zero. */
1592 	bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1593 	/* 5700 b2 errata */
1594 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1595 		bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1596 
1597 	return (0);
1598 }
1599 
1600 static void
1601 bge_setpromisc(struct bge_softc *sc)
1602 {
1603 	struct ifnet *ifp;
1604 
1605 	BGE_LOCK_ASSERT(sc);
1606 
1607 	ifp = sc->bge_ifp;
1608 
1609 	/* Enable or disable promiscuous mode as needed. */
1610 	if (ifp->if_flags & IFF_PROMISC)
1611 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1612 	else
1613 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1614 }
1615 
1616 static void
1617 bge_setmulti(struct bge_softc *sc)
1618 {
1619 	struct ifnet *ifp;
1620 	struct ifmultiaddr *ifma;
1621 	uint32_t hashes[4] = { 0, 0, 0, 0 };
1622 	int h, i;
1623 
1624 	BGE_LOCK_ASSERT(sc);
1625 
1626 	ifp = sc->bge_ifp;
1627 
1628 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1629 		for (i = 0; i < 4; i++)
1630 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1631 		return;
1632 	}
1633 
1634 	/* First, zot all the existing filters. */
1635 	for (i = 0; i < 4; i++)
1636 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1637 
1638 	/* Now program new ones. */
1639 	if_maddr_rlock(ifp);
1640 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1641 		if (ifma->ifma_addr->sa_family != AF_LINK)
1642 			continue;
1643 		h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1644 		    ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1645 		hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1646 	}
1647 	if_maddr_runlock(ifp);
1648 
1649 	for (i = 0; i < 4; i++)
1650 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1651 }
1652 
1653 static void
1654 bge_setvlan(struct bge_softc *sc)
1655 {
1656 	struct ifnet *ifp;
1657 
1658 	BGE_LOCK_ASSERT(sc);
1659 
1660 	ifp = sc->bge_ifp;
1661 
1662 	/* Enable or disable VLAN tag stripping as needed. */
1663 	if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1664 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1665 	else
1666 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1667 }
1668 
1669 static void
1670 bge_sig_pre_reset(struct bge_softc *sc, int type)
1671 {
1672 
1673 	/*
1674 	 * Some chips don't like this so only do this if ASF is enabled
1675 	 */
1676 	if (sc->bge_asf_mode)
1677 		bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1678 
1679 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1680 		switch (type) {
1681 		case BGE_RESET_START:
1682 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1683 			    BGE_FW_DRV_STATE_START);
1684 			break;
1685 		case BGE_RESET_SHUTDOWN:
1686 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1687 			    BGE_FW_DRV_STATE_UNLOAD);
1688 			break;
1689 		case BGE_RESET_SUSPEND:
1690 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1691 			    BGE_FW_DRV_STATE_SUSPEND);
1692 			break;
1693 		}
1694 	}
1695 
1696 	if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1697 		bge_ape_driver_state_change(sc, type);
1698 }
1699 
1700 static void
1701 bge_sig_post_reset(struct bge_softc *sc, int type)
1702 {
1703 
1704 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1705 		switch (type) {
1706 		case BGE_RESET_START:
1707 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1708 			    BGE_FW_DRV_STATE_START_DONE);
1709 			/* START DONE */
1710 			break;
1711 		case BGE_RESET_SHUTDOWN:
1712 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1713 			    BGE_FW_DRV_STATE_UNLOAD_DONE);
1714 			break;
1715 		}
1716 	}
1717 	if (type == BGE_RESET_SHUTDOWN)
1718 		bge_ape_driver_state_change(sc, type);
1719 }
1720 
1721 static void
1722 bge_sig_legacy(struct bge_softc *sc, int type)
1723 {
1724 
1725 	if (sc->bge_asf_mode) {
1726 		switch (type) {
1727 		case BGE_RESET_START:
1728 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1729 			    BGE_FW_DRV_STATE_START);
1730 			break;
1731 		case BGE_RESET_SHUTDOWN:
1732 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1733 			    BGE_FW_DRV_STATE_UNLOAD);
1734 			break;
1735 		}
1736 	}
1737 }
1738 
1739 static void
1740 bge_stop_fw(struct bge_softc *sc)
1741 {
1742 	int i;
1743 
1744 	if (sc->bge_asf_mode) {
1745 		bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1746 		CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1747 		    CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1748 
1749 		for (i = 0; i < 100; i++ ) {
1750 			if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1751 			    BGE_RX_CPU_DRV_EVENT))
1752 				break;
1753 			DELAY(10);
1754 		}
1755 	}
1756 }
1757 
1758 static uint32_t
1759 bge_dma_swap_options(struct bge_softc *sc)
1760 {
1761 	uint32_t dma_options;
1762 
1763 	dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1764 	    BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1765 #if BYTE_ORDER == BIG_ENDIAN
1766 	dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1767 #endif
1768 	return (dma_options);
1769 }
1770 
1771 /*
1772  * Do endian, PCI and DMA initialization.
1773  */
1774 static int
1775 bge_chipinit(struct bge_softc *sc)
1776 {
1777 	uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1778 	uint16_t val;
1779 	int i;
1780 
1781 	/* Set endianness before we access any non-PCI registers. */
1782 	misc_ctl = BGE_INIT;
1783 	if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1784 		misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1785 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1786 
1787 	/*
1788 	 * Clear the MAC statistics block in the NIC's
1789 	 * internal memory.
1790 	 */
1791 	for (i = BGE_STATS_BLOCK;
1792 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1793 		BGE_MEMWIN_WRITE(sc, i, 0);
1794 
1795 	for (i = BGE_STATUS_BLOCK;
1796 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1797 		BGE_MEMWIN_WRITE(sc, i, 0);
1798 
1799 	if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1800 		/*
1801 		 *  Fix data corruption caused by non-qword write with WB.
1802 		 *  Fix master abort in PCI mode.
1803 		 *  Fix PCI latency timer.
1804 		 */
1805 		val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1806 		val |= (1 << 10) | (1 << 12) | (1 << 13);
1807 		pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1808 	}
1809 
1810 	if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1811 	    sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1812 		/*
1813 		 * For the 57766 and non Ax versions of 57765, bootcode
1814 		 * needs to setup the PCIE Fast Training Sequence (FTS)
1815 		 * value to prevent transmit hangs.
1816 		 */
1817 		if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1818 			CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1819 			    CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1820 			    BGE_CPMU_PADRNG_CTL_RDIV2);
1821 		}
1822 	}
1823 
1824 	/*
1825 	 * Set up the PCI DMA control register.
1826 	 */
1827 	dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1828 	    BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1829 	if (sc->bge_flags & BGE_FLAG_PCIE) {
1830 		if (sc->bge_mps >= 256)
1831 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1832 		else
1833 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1834 	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
1835 		if (BGE_IS_5714_FAMILY(sc)) {
1836 			/* 256 bytes for read and write. */
1837 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1838 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1839 			dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1840 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1841 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1842 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1843 			/*
1844 			 * In the BCM5703, the DMA read watermark should
1845 			 * be set to less than or equal to the maximum
1846 			 * memory read byte count of the PCI-X command
1847 			 * register.
1848 			 */
1849 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1850 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1851 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1852 			/* 1536 bytes for read, 384 bytes for write. */
1853 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1854 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1855 		} else {
1856 			/* 384 bytes for read and write. */
1857 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1858 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1859 			    0x0F;
1860 		}
1861 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1862 		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1863 			uint32_t tmp;
1864 
1865 			/* Set ONE_DMA_AT_ONCE for hardware workaround. */
1866 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1867 			if (tmp == 6 || tmp == 7)
1868 				dma_rw_ctl |=
1869 				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1870 
1871 			/* Set PCI-X DMA write workaround. */
1872 			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1873 		}
1874 	} else {
1875 		/* Conventional PCI bus: 256 bytes for read and write. */
1876 		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1877 		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1878 
1879 		if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1880 		    sc->bge_asicrev != BGE_ASICREV_BCM5750)
1881 			dma_rw_ctl |= 0x0F;
1882 	}
1883 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1884 	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
1885 		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1886 		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
1887 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1888 	    sc->bge_asicrev == BGE_ASICREV_BCM5704)
1889 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1890 	if (BGE_IS_5717_PLUS(sc)) {
1891 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1892 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1893 			dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1894 		/*
1895 		 * Enable HW workaround for controllers that misinterpret
1896 		 * a status tag update and leave interrupts permanently
1897 		 * disabled.
1898 		 */
1899 		if (!BGE_IS_57765_PLUS(sc) &&
1900 		    sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1901 		    sc->bge_asicrev != BGE_ASICREV_BCM5762)
1902 			dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1903 	}
1904 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1905 
1906 	/*
1907 	 * Set up general mode register.
1908 	 */
1909 	mode_ctl = bge_dma_swap_options(sc);
1910 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1911 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1912 		/* Retain Host-2-BMC settings written by APE firmware. */
1913 		mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1914 		    (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1915 		    BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1916 		    BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1917 	}
1918 	mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1919 	    BGE_MODECTL_TX_NO_PHDR_CSUM;
1920 
1921 	/*
1922 	 * BCM5701 B5 have a bug causing data corruption when using
1923 	 * 64-bit DMA reads, which can be terminated early and then
1924 	 * completed later as 32-bit accesses, in combination with
1925 	 * certain bridges.
1926 	 */
1927 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1928 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1929 		mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1930 
1931 	/*
1932 	 * Tell the firmware the driver is running
1933 	 */
1934 	if (sc->bge_asf_mode & ASF_STACKUP)
1935 		mode_ctl |= BGE_MODECTL_STACKUP;
1936 
1937 	CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1938 
1939 	/*
1940 	 * Disable memory write invalidate.  Apparently it is not supported
1941 	 * properly by these devices.  Also ensure that INTx isn't disabled,
1942 	 * as these chips need it even when using MSI.
1943 	 */
1944 	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1945 	    PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1946 
1947 	/* Set the timer prescaler (always 66 MHz). */
1948 	CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1949 
1950 	/* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1951 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1952 		DELAY(40);	/* XXX */
1953 
1954 		/* Put PHY into ready state */
1955 		BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1956 		CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1957 		DELAY(40);
1958 	}
1959 
1960 	return (0);
1961 }
1962 
1963 static int
1964 bge_blockinit(struct bge_softc *sc)
1965 {
1966 	struct bge_rcb *rcb;
1967 	bus_size_t vrcb;
1968 	bge_hostaddr taddr;
1969 	uint32_t dmactl, rdmareg, val;
1970 	int i, limit;
1971 
1972 	/*
1973 	 * Initialize the memory window pointer register so that
1974 	 * we can access the first 32K of internal NIC RAM. This will
1975 	 * allow us to set up the TX send ring RCBs and the RX return
1976 	 * ring RCBs, plus other things which live in NIC memory.
1977 	 */
1978 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1979 
1980 	/* Note: the BCM5704 has a smaller mbuf space than other chips. */
1981 
1982 	if (!(BGE_IS_5705_PLUS(sc))) {
1983 		/* Configure mbuf memory pool */
1984 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1985 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1986 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1987 		else
1988 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1989 
1990 		/* Configure DMA resource pool */
1991 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1992 		    BGE_DMA_DESCRIPTORS);
1993 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1994 	}
1995 
1996 	/* Configure mbuf pool watermarks */
1997 	if (BGE_IS_5717_PLUS(sc)) {
1998 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1999 		if (sc->bge_ifp->if_mtu > ETHERMTU) {
2000 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2001 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2002 		} else {
2003 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2004 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2005 		}
2006 	} else if (!BGE_IS_5705_PLUS(sc)) {
2007 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2008 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2009 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2010 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2011 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2012 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2013 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2014 	} else {
2015 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2016 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2017 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2018 	}
2019 
2020 	/* Configure DMA resource watermarks */
2021 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2022 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2023 
2024 	/* Enable buffer manager */
2025 	val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2026 	/*
2027 	 * Change the arbitration algorithm of TXMBUF read request to
2028 	 * round-robin instead of priority based for BCM5719.  When
2029 	 * TXFIFO is almost empty, RDMA will hold its request until
2030 	 * TXFIFO is not almost empty.
2031 	 */
2032 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2033 		val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2034 	CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2035 
2036 	/* Poll for buffer manager start indication */
2037 	for (i = 0; i < BGE_TIMEOUT; i++) {
2038 		DELAY(10);
2039 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2040 			break;
2041 	}
2042 
2043 	if (i == BGE_TIMEOUT) {
2044 		device_printf(sc->bge_dev, "buffer manager failed to start\n");
2045 		return (ENXIO);
2046 	}
2047 
2048 	/* Enable flow-through queues */
2049 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2050 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2051 
2052 	/* Wait until queue initialization is complete */
2053 	for (i = 0; i < BGE_TIMEOUT; i++) {
2054 		DELAY(10);
2055 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2056 			break;
2057 	}
2058 
2059 	if (i == BGE_TIMEOUT) {
2060 		device_printf(sc->bge_dev, "flow-through queue init failed\n");
2061 		return (ENXIO);
2062 	}
2063 
2064 	/*
2065 	 * Summary of rings supported by the controller:
2066 	 *
2067 	 * Standard Receive Producer Ring
2068 	 * - This ring is used to feed receive buffers for "standard"
2069 	 *   sized frames (typically 1536 bytes) to the controller.
2070 	 *
2071 	 * Jumbo Receive Producer Ring
2072 	 * - This ring is used to feed receive buffers for jumbo sized
2073 	 *   frames (i.e. anything bigger than the "standard" frames)
2074 	 *   to the controller.
2075 	 *
2076 	 * Mini Receive Producer Ring
2077 	 * - This ring is used to feed receive buffers for "mini"
2078 	 *   sized frames to the controller.
2079 	 * - This feature required external memory for the controller
2080 	 *   but was never used in a production system.  Should always
2081 	 *   be disabled.
2082 	 *
2083 	 * Receive Return Ring
2084 	 * - After the controller has placed an incoming frame into a
2085 	 *   receive buffer that buffer is moved into a receive return
2086 	 *   ring.  The driver is then responsible to passing the
2087 	 *   buffer up to the stack.  Many versions of the controller
2088 	 *   support multiple RR rings.
2089 	 *
2090 	 * Send Ring
2091 	 * - This ring is used for outgoing frames.  Many versions of
2092 	 *   the controller support multiple send rings.
2093 	 */
2094 
2095 	/* Initialize the standard receive producer ring control block. */
2096 	rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2097 	rcb->bge_hostaddr.bge_addr_lo =
2098 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2099 	rcb->bge_hostaddr.bge_addr_hi =
2100 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2101 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2102 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2103 	if (BGE_IS_5717_PLUS(sc)) {
2104 		/*
2105 		 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2106 		 * Bits 15-2 : Maximum RX frame size
2107 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2108 		 * Bit 0     : Reserved
2109 		 */
2110 		rcb->bge_maxlen_flags =
2111 		    BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2112 	} else if (BGE_IS_5705_PLUS(sc)) {
2113 		/*
2114 		 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2115 		 * Bits 15-2 : Reserved (should be 0)
2116 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2117 		 * Bit 0     : Reserved
2118 		 */
2119 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2120 	} else {
2121 		/*
2122 		 * Ring size is always XXX entries
2123 		 * Bits 31-16: Maximum RX frame size
2124 		 * Bits 15-2 : Reserved (should be 0)
2125 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2126 		 * Bit 0     : Reserved
2127 		 */
2128 		rcb->bge_maxlen_flags =
2129 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2130 	}
2131 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2132 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2133 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2134 		rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2135 	else
2136 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2137 	/* Write the standard receive producer ring control block. */
2138 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2139 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2140 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2141 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2142 
2143 	/* Reset the standard receive producer ring producer index. */
2144 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2145 
2146 	/*
2147 	 * Initialize the jumbo RX producer ring control
2148 	 * block.  We set the 'ring disabled' bit in the
2149 	 * flags field until we're actually ready to start
2150 	 * using this ring (i.e. once we set the MTU
2151 	 * high enough to require it).
2152 	 */
2153 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
2154 		rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2155 		/* Get the jumbo receive producer ring RCB parameters. */
2156 		rcb->bge_hostaddr.bge_addr_lo =
2157 		    BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2158 		rcb->bge_hostaddr.bge_addr_hi =
2159 		    BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2160 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2161 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2162 		    BUS_DMASYNC_PREREAD);
2163 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2164 		    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2165 		if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2166 		    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2167 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2168 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2169 		else
2170 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2171 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2172 		    rcb->bge_hostaddr.bge_addr_hi);
2173 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2174 		    rcb->bge_hostaddr.bge_addr_lo);
2175 		/* Program the jumbo receive producer ring RCB parameters. */
2176 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2177 		    rcb->bge_maxlen_flags);
2178 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2179 		/* Reset the jumbo receive producer ring producer index. */
2180 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2181 	}
2182 
2183 	/* Disable the mini receive producer ring RCB. */
2184 	if (BGE_IS_5700_FAMILY(sc)) {
2185 		rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2186 		rcb->bge_maxlen_flags =
2187 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2188 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2189 		    rcb->bge_maxlen_flags);
2190 		/* Reset the mini receive producer ring producer index. */
2191 		bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2192 	}
2193 
2194 	/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2195 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2196 		if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2197 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2198 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2199 			CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2200 			    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2201 	}
2202 	/*
2203 	 * The BD ring replenish thresholds control how often the
2204 	 * hardware fetches new BD's from the producer rings in host
2205 	 * memory.  Setting the value too low on a busy system can
2206 	 * starve the hardware and recue the throughpout.
2207 	 *
2208 	 * Set the BD ring replentish thresholds. The recommended
2209 	 * values are 1/8th the number of descriptors allocated to
2210 	 * each ring.
2211 	 * XXX The 5754 requires a lower threshold, so it might be a
2212 	 * requirement of all 575x family chips.  The Linux driver sets
2213 	 * the lower threshold for all 5705 family chips as well, but there
2214 	 * are reports that it might not need to be so strict.
2215 	 *
2216 	 * XXX Linux does some extra fiddling here for the 5906 parts as
2217 	 * well.
2218 	 */
2219 	if (BGE_IS_5705_PLUS(sc))
2220 		val = 8;
2221 	else
2222 		val = BGE_STD_RX_RING_CNT / 8;
2223 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2224 	if (BGE_IS_JUMBO_CAPABLE(sc))
2225 		CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2226 		    BGE_JUMBO_RX_RING_CNT/8);
2227 	if (BGE_IS_5717_PLUS(sc)) {
2228 		CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2229 		CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2230 	}
2231 
2232 	/*
2233 	 * Disable all send rings by setting the 'ring disabled' bit
2234 	 * in the flags field of all the TX send ring control blocks,
2235 	 * located in NIC memory.
2236 	 */
2237 	if (!BGE_IS_5705_PLUS(sc))
2238 		/* 5700 to 5704 had 16 send rings. */
2239 		limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2240 	else if (BGE_IS_57765_PLUS(sc) ||
2241 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2242 		limit = 2;
2243 	else if (BGE_IS_5717_PLUS(sc))
2244 		limit = 4;
2245 	else
2246 		limit = 1;
2247 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2248 	for (i = 0; i < limit; i++) {
2249 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2250 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2251 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2252 		vrcb += sizeof(struct bge_rcb);
2253 	}
2254 
2255 	/* Configure send ring RCB 0 (we use only the first ring) */
2256 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2257 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2258 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2259 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2260 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2261 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2262 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2263 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2264 	else
2265 		RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2266 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2267 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2268 	    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2269 
2270 	/*
2271 	 * Disable all receive return rings by setting the
2272 	 * 'ring diabled' bit in the flags field of all the receive
2273 	 * return ring control blocks, located in NIC memory.
2274 	 */
2275 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2276 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2277 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2278 		/* Should be 17, use 16 until we get an SRAM map. */
2279 		limit = 16;
2280 	} else if (!BGE_IS_5705_PLUS(sc))
2281 		limit = BGE_RX_RINGS_MAX;
2282 	else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2283 	    sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2284 	    BGE_IS_57765_PLUS(sc))
2285 		limit = 4;
2286 	else
2287 		limit = 1;
2288 	/* Disable all receive return rings. */
2289 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2290 	for (i = 0; i < limit; i++) {
2291 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2292 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2293 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2294 		    BGE_RCB_FLAG_RING_DISABLED);
2295 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2296 		bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2297 		    (i * (sizeof(uint64_t))), 0);
2298 		vrcb += sizeof(struct bge_rcb);
2299 	}
2300 
2301 	/*
2302 	 * Set up receive return ring 0.  Note that the NIC address
2303 	 * for RX return rings is 0x0.  The return rings live entirely
2304 	 * within the host, so the nicaddr field in the RCB isn't used.
2305 	 */
2306 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2307 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2308 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2309 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2310 	RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2311 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2312 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2313 
2314 	/* Set random backoff seed for TX */
2315 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2316 	    (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2317 	    IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2318 	    IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2319 	    BGE_TX_BACKOFF_SEED_MASK);
2320 
2321 	/* Set inter-packet gap */
2322 	val = 0x2620;
2323 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2324 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2325 		val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2326 		    (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2327 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2328 
2329 	/*
2330 	 * Specify which ring to use for packets that don't match
2331 	 * any RX rules.
2332 	 */
2333 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2334 
2335 	/*
2336 	 * Configure number of RX lists. One interrupt distribution
2337 	 * list, sixteen active lists, one bad frames class.
2338 	 */
2339 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2340 
2341 	/* Inialize RX list placement stats mask. */
2342 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2343 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2344 
2345 	/* Disable host coalescing until we get it set up */
2346 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2347 
2348 	/* Poll to make sure it's shut down. */
2349 	for (i = 0; i < BGE_TIMEOUT; i++) {
2350 		DELAY(10);
2351 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2352 			break;
2353 	}
2354 
2355 	if (i == BGE_TIMEOUT) {
2356 		device_printf(sc->bge_dev,
2357 		    "host coalescing engine failed to idle\n");
2358 		return (ENXIO);
2359 	}
2360 
2361 	/* Set up host coalescing defaults */
2362 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2363 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2364 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2365 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2366 	if (!(BGE_IS_5705_PLUS(sc))) {
2367 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2368 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2369 	}
2370 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2371 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2372 
2373 	/* Set up address of statistics block */
2374 	if (!(BGE_IS_5705_PLUS(sc))) {
2375 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2376 		    BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2377 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2378 		    BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2379 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2380 		CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2381 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2382 	}
2383 
2384 	/* Set up address of status block */
2385 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2386 	    BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2387 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2388 	    BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2389 
2390 	/* Set up status block size. */
2391 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2392 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2393 		val = BGE_STATBLKSZ_FULL;
2394 		bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2395 	} else {
2396 		val = BGE_STATBLKSZ_32BYTE;
2397 		bzero(sc->bge_ldata.bge_status_block, 32);
2398 	}
2399 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2400 	    sc->bge_cdata.bge_status_map,
2401 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2402 
2403 	/* Turn on host coalescing state machine */
2404 	CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2405 
2406 	/* Turn on RX BD completion state machine and enable attentions */
2407 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
2408 	    BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2409 
2410 	/* Turn on RX list placement state machine */
2411 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2412 
2413 	/* Turn on RX list selector state machine. */
2414 	if (!(BGE_IS_5705_PLUS(sc)))
2415 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2416 
2417 	/* Turn on DMA, clear stats. */
2418 	val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2419 	    BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2420 	    BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2421 	    BGE_MACMODE_FRMHDR_DMA_ENB;
2422 
2423 	if (sc->bge_flags & BGE_FLAG_TBI)
2424 		val |= BGE_PORTMODE_TBI;
2425 	else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2426 		val |= BGE_PORTMODE_GMII;
2427 	else
2428 		val |= BGE_PORTMODE_MII;
2429 
2430 	/* Allow APE to send/receive frames. */
2431 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2432 		val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2433 
2434 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2435 	DELAY(40);
2436 
2437 	/* Set misc. local control, enable interrupts on attentions */
2438 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2439 
2440 #ifdef notdef
2441 	/* Assert GPIO pins for PHY reset */
2442 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2443 	    BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2444 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2445 	    BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2446 #endif
2447 
2448 	/* Turn on DMA completion state machine */
2449 	if (!(BGE_IS_5705_PLUS(sc)))
2450 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2451 
2452 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2453 
2454 	/* Enable host coalescing bug fix. */
2455 	if (BGE_IS_5755_PLUS(sc))
2456 		val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2457 
2458 	/* Request larger DMA burst size to get better performance. */
2459 	if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2460 		val |= BGE_WDMAMODE_BURST_ALL_DATA;
2461 
2462 	/* Turn on write DMA state machine */
2463 	CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2464 	DELAY(40);
2465 
2466 	/* Turn on read DMA state machine */
2467 	val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2468 
2469 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2470 		val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2471 
2472 	if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2473 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2474 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2475 		val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2476 		    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2477 		    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2478 	if (sc->bge_flags & BGE_FLAG_PCIE)
2479 		val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2480 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2481 		val |= BGE_RDMAMODE_TSO4_ENABLE;
2482 		if (sc->bge_flags & BGE_FLAG_TSO3 ||
2483 		    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2484 		    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2485 			val |= BGE_RDMAMODE_TSO6_ENABLE;
2486 	}
2487 
2488 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2489 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2490 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2491 			BGE_RDMAMODE_H2BNC_VLAN_DET;
2492 		/*
2493 		 * Allow multiple outstanding read requests from
2494 		 * non-LSO read DMA engine.
2495 		 */
2496 		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2497 	}
2498 
2499 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2500 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2501 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2502 	    sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2503 	    BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2504 		if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2505 			rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2506 		else
2507 			rdmareg = BGE_RDMA_RSRVCTRL;
2508 		dmactl = CSR_READ_4(sc, rdmareg);
2509 		/*
2510 		 * Adjust tx margin to prevent TX data corruption and
2511 		 * fix internal FIFO overflow.
2512 		 */
2513 		if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2514 		    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2515 			dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2516 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2517 			    BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2518 			dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2519 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2520 			    BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2521 		}
2522 		/*
2523 		 * Enable fix for read DMA FIFO overruns.
2524 		 * The fix is to limit the number of RX BDs
2525 		 * the hardware would fetch at a fime.
2526 		 */
2527 		CSR_WRITE_4(sc, rdmareg, dmactl |
2528 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2529 	}
2530 
2531 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2532 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2533 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2534 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2535 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2536 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2537 		/*
2538 		 * Allow 4KB burst length reads for non-LSO frames.
2539 		 * Enable 512B burst length reads for buffer descriptors.
2540 		 */
2541 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2542 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2543 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2544 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2545 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2546 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2547 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2548 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2549 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2550 	}
2551 
2552 	CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2553 	DELAY(40);
2554 
2555 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2556 		for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2557 			val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2558 			if ((val & 0xFFFF) > BGE_FRAMELEN)
2559 				break;
2560 			if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2561 				break;
2562 		}
2563 		if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2564 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2565 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2566 				val |= BGE_RDMA_TX_LENGTH_WA_5719;
2567 			else
2568 				val |= BGE_RDMA_TX_LENGTH_WA_5720;
2569 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2570 		}
2571 	}
2572 
2573 	/* Turn on RX data completion state machine */
2574 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2575 
2576 	/* Turn on RX BD initiator state machine */
2577 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2578 
2579 	/* Turn on RX data and RX BD initiator state machine */
2580 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2581 
2582 	/* Turn on Mbuf cluster free state machine */
2583 	if (!(BGE_IS_5705_PLUS(sc)))
2584 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2585 
2586 	/* Turn on send BD completion state machine */
2587 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2588 
2589 	/* Turn on send data completion state machine */
2590 	val = BGE_SDCMODE_ENABLE;
2591 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2592 		val |= BGE_SDCMODE_CDELAY;
2593 	CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2594 
2595 	/* Turn on send data initiator state machine */
2596 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2597 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2598 		    BGE_SDIMODE_HW_LSO_PRE_DMA);
2599 	else
2600 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2601 
2602 	/* Turn on send BD initiator state machine */
2603 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2604 
2605 	/* Turn on send BD selector state machine */
2606 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2607 
2608 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2609 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2610 	    BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2611 
2612 	/* ack/clear link change events */
2613 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2614 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2615 	    BGE_MACSTAT_LINK_CHANGED);
2616 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
2617 
2618 	/*
2619 	 * Enable attention when the link has changed state for
2620 	 * devices that use auto polling.
2621 	 */
2622 	if (sc->bge_flags & BGE_FLAG_TBI) {
2623 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2624 	} else {
2625 		if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2626 			CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2627 			DELAY(80);
2628 		}
2629 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2630 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2631 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2632 			    BGE_EVTENB_MI_INTERRUPT);
2633 	}
2634 
2635 	/*
2636 	 * Clear any pending link state attention.
2637 	 * Otherwise some link state change events may be lost until attention
2638 	 * is cleared by bge_intr() -> bge_link_upd() sequence.
2639 	 * It's not necessary on newer BCM chips - perhaps enabling link
2640 	 * state change attentions implies clearing pending attention.
2641 	 */
2642 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2643 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2644 	    BGE_MACSTAT_LINK_CHANGED);
2645 
2646 	/* Enable link state change attentions. */
2647 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2648 
2649 	return (0);
2650 }
2651 
2652 static const struct bge_revision *
2653 bge_lookup_rev(uint32_t chipid)
2654 {
2655 	const struct bge_revision *br;
2656 
2657 	for (br = bge_revisions; br->br_name != NULL; br++) {
2658 		if (br->br_chipid == chipid)
2659 			return (br);
2660 	}
2661 
2662 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
2663 		if (br->br_chipid == BGE_ASICREV(chipid))
2664 			return (br);
2665 	}
2666 
2667 	return (NULL);
2668 }
2669 
2670 static const struct bge_vendor *
2671 bge_lookup_vendor(uint16_t vid)
2672 {
2673 	const struct bge_vendor *v;
2674 
2675 	for (v = bge_vendors; v->v_name != NULL; v++)
2676 		if (v->v_id == vid)
2677 			return (v);
2678 
2679 	return (NULL);
2680 }
2681 
2682 static uint32_t
2683 bge_chipid(device_t dev)
2684 {
2685 	uint32_t id;
2686 
2687 	id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2688 	    BGE_PCIMISCCTL_ASICREV_SHIFT;
2689 	if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2690 		/*
2691 		 * Find the ASCI revision.  Different chips use different
2692 		 * registers.
2693 		 */
2694 		switch (pci_get_device(dev)) {
2695 		case BCOM_DEVICEID_BCM5717:
2696 		case BCOM_DEVICEID_BCM5718:
2697 		case BCOM_DEVICEID_BCM5719:
2698 		case BCOM_DEVICEID_BCM5720:
2699 		case BCOM_DEVICEID_BCM5725:
2700 		case BCOM_DEVICEID_BCM5727:
2701 		case BCOM_DEVICEID_BCM5762:
2702 		case BCOM_DEVICEID_BCM57764:
2703 		case BCOM_DEVICEID_BCM57767:
2704 		case BCOM_DEVICEID_BCM57787:
2705 			id = pci_read_config(dev,
2706 			    BGE_PCI_GEN2_PRODID_ASICREV, 4);
2707 			break;
2708 		case BCOM_DEVICEID_BCM57761:
2709 		case BCOM_DEVICEID_BCM57762:
2710 		case BCOM_DEVICEID_BCM57765:
2711 		case BCOM_DEVICEID_BCM57766:
2712 		case BCOM_DEVICEID_BCM57781:
2713 		case BCOM_DEVICEID_BCM57782:
2714 		case BCOM_DEVICEID_BCM57785:
2715 		case BCOM_DEVICEID_BCM57786:
2716 		case BCOM_DEVICEID_BCM57791:
2717 		case BCOM_DEVICEID_BCM57795:
2718 			id = pci_read_config(dev,
2719 			    BGE_PCI_GEN15_PRODID_ASICREV, 4);
2720 			break;
2721 		default:
2722 			id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2723 		}
2724 	}
2725 	return (id);
2726 }
2727 
2728 /*
2729  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2730  * against our list and return its name if we find a match.
2731  *
2732  * Note that since the Broadcom controller contains VPD support, we
2733  * try to get the device name string from the controller itself instead
2734  * of the compiled-in string. It guarantees we'll always announce the
2735  * right product name. We fall back to the compiled-in string when
2736  * VPD is unavailable or corrupt.
2737  */
2738 static int
2739 bge_probe(device_t dev)
2740 {
2741 	char buf[96];
2742 	char model[64];
2743 	const struct bge_revision *br;
2744 	const char *pname;
2745 	struct bge_softc *sc;
2746 	const struct bge_type *t = bge_devs;
2747 	const struct bge_vendor *v;
2748 	uint32_t id;
2749 	uint16_t did, vid;
2750 
2751 	sc = device_get_softc(dev);
2752 	sc->bge_dev = dev;
2753 	vid = pci_get_vendor(dev);
2754 	did = pci_get_device(dev);
2755 	while(t->bge_vid != 0) {
2756 		if ((vid == t->bge_vid) && (did == t->bge_did)) {
2757 			id = bge_chipid(dev);
2758 			br = bge_lookup_rev(id);
2759 			if (bge_has_eaddr(sc) &&
2760 			    pci_get_vpd_ident(dev, &pname) == 0)
2761 				snprintf(model, sizeof(model), "%s", pname);
2762 			else {
2763 				v = bge_lookup_vendor(vid);
2764 				snprintf(model, sizeof(model), "%s %s",
2765 				    v != NULL ? v->v_name : "Unknown",
2766 				    br != NULL ? br->br_name :
2767 				    "NetXtreme/NetLink Ethernet Controller");
2768 			}
2769 			snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2770 			    model, br != NULL ? "" : "unknown ", id);
2771 			device_set_desc_copy(dev, buf);
2772 			return (BUS_PROBE_DEFAULT);
2773 		}
2774 		t++;
2775 	}
2776 
2777 	return (ENXIO);
2778 }
2779 
2780 static void
2781 bge_dma_free(struct bge_softc *sc)
2782 {
2783 	int i;
2784 
2785 	/* Destroy DMA maps for RX buffers. */
2786 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2787 		if (sc->bge_cdata.bge_rx_std_dmamap[i])
2788 			bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2789 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
2790 	}
2791 	if (sc->bge_cdata.bge_rx_std_sparemap)
2792 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2793 		    sc->bge_cdata.bge_rx_std_sparemap);
2794 
2795 	/* Destroy DMA maps for jumbo RX buffers. */
2796 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2797 		if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2798 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2799 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2800 	}
2801 	if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2802 		bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2803 		    sc->bge_cdata.bge_rx_jumbo_sparemap);
2804 
2805 	/* Destroy DMA maps for TX buffers. */
2806 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
2807 		if (sc->bge_cdata.bge_tx_dmamap[i])
2808 			bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2809 			    sc->bge_cdata.bge_tx_dmamap[i]);
2810 	}
2811 
2812 	if (sc->bge_cdata.bge_rx_mtag)
2813 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2814 	if (sc->bge_cdata.bge_mtag_jumbo)
2815 		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2816 	if (sc->bge_cdata.bge_tx_mtag)
2817 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2818 
2819 	/* Destroy standard RX ring. */
2820 	if (sc->bge_cdata.bge_rx_std_ring_map)
2821 		bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2822 		    sc->bge_cdata.bge_rx_std_ring_map);
2823 	if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2824 		bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2825 		    sc->bge_ldata.bge_rx_std_ring,
2826 		    sc->bge_cdata.bge_rx_std_ring_map);
2827 
2828 	if (sc->bge_cdata.bge_rx_std_ring_tag)
2829 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2830 
2831 	/* Destroy jumbo RX ring. */
2832 	if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2833 		bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2834 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2835 
2836 	if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2837 	    sc->bge_ldata.bge_rx_jumbo_ring)
2838 		bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2839 		    sc->bge_ldata.bge_rx_jumbo_ring,
2840 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2841 
2842 	if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2843 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2844 
2845 	/* Destroy RX return ring. */
2846 	if (sc->bge_cdata.bge_rx_return_ring_map)
2847 		bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2848 		    sc->bge_cdata.bge_rx_return_ring_map);
2849 
2850 	if (sc->bge_cdata.bge_rx_return_ring_map &&
2851 	    sc->bge_ldata.bge_rx_return_ring)
2852 		bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2853 		    sc->bge_ldata.bge_rx_return_ring,
2854 		    sc->bge_cdata.bge_rx_return_ring_map);
2855 
2856 	if (sc->bge_cdata.bge_rx_return_ring_tag)
2857 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2858 
2859 	/* Destroy TX ring. */
2860 	if (sc->bge_cdata.bge_tx_ring_map)
2861 		bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2862 		    sc->bge_cdata.bge_tx_ring_map);
2863 
2864 	if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2865 		bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2866 		    sc->bge_ldata.bge_tx_ring,
2867 		    sc->bge_cdata.bge_tx_ring_map);
2868 
2869 	if (sc->bge_cdata.bge_tx_ring_tag)
2870 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2871 
2872 	/* Destroy status block. */
2873 	if (sc->bge_cdata.bge_status_map)
2874 		bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2875 		    sc->bge_cdata.bge_status_map);
2876 
2877 	if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2878 		bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2879 		    sc->bge_ldata.bge_status_block,
2880 		    sc->bge_cdata.bge_status_map);
2881 
2882 	if (sc->bge_cdata.bge_status_tag)
2883 		bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2884 
2885 	/* Destroy statistics block. */
2886 	if (sc->bge_cdata.bge_stats_map)
2887 		bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2888 		    sc->bge_cdata.bge_stats_map);
2889 
2890 	if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2891 		bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2892 		    sc->bge_ldata.bge_stats,
2893 		    sc->bge_cdata.bge_stats_map);
2894 
2895 	if (sc->bge_cdata.bge_stats_tag)
2896 		bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2897 
2898 	if (sc->bge_cdata.bge_buffer_tag)
2899 		bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2900 
2901 	/* Destroy the parent tag. */
2902 	if (sc->bge_cdata.bge_parent_tag)
2903 		bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2904 }
2905 
2906 static int
2907 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2908     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2909     bus_addr_t *paddr, const char *msg)
2910 {
2911 	struct bge_dmamap_arg ctx;
2912 	int error;
2913 
2914 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2915 	    alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2916 	    NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2917 	if (error != 0) {
2918 		device_printf(sc->bge_dev,
2919 		    "could not create %s dma tag\n", msg);
2920 		return (ENOMEM);
2921 	}
2922 	/* Allocate DMA'able memory for ring. */
2923 	error = bus_dmamem_alloc(*tag, (void **)ring,
2924 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2925 	if (error != 0) {
2926 		device_printf(sc->bge_dev,
2927 		    "could not allocate DMA'able memory for %s\n", msg);
2928 		return (ENOMEM);
2929 	}
2930 	/* Load the address of the ring. */
2931 	ctx.bge_busaddr = 0;
2932 	error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2933 	    &ctx, BUS_DMA_NOWAIT);
2934 	if (error != 0) {
2935 		device_printf(sc->bge_dev,
2936 		    "could not load DMA'able memory for %s\n", msg);
2937 		return (ENOMEM);
2938 	}
2939 	*paddr = ctx.bge_busaddr;
2940 	return (0);
2941 }
2942 
2943 static int
2944 bge_dma_alloc(struct bge_softc *sc)
2945 {
2946 	bus_addr_t lowaddr;
2947 	bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2948 	int i, error;
2949 
2950 	lowaddr = BUS_SPACE_MAXADDR;
2951 	if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2952 		lowaddr = BGE_DMA_MAXADDR;
2953 	/*
2954 	 * Allocate the parent bus DMA tag appropriate for PCI.
2955 	 */
2956 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2957 	    1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2958 	    NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2959 	    0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2960 	if (error != 0) {
2961 		device_printf(sc->bge_dev,
2962 		    "could not allocate parent dma tag\n");
2963 		return (ENOMEM);
2964 	}
2965 
2966 	/* Create tag for standard RX ring. */
2967 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2968 	    &sc->bge_cdata.bge_rx_std_ring_tag,
2969 	    (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2970 	    &sc->bge_cdata.bge_rx_std_ring_map,
2971 	    &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2972 	if (error)
2973 		return (error);
2974 
2975 	/* Create tag for RX return ring. */
2976 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2977 	    &sc->bge_cdata.bge_rx_return_ring_tag,
2978 	    (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2979 	    &sc->bge_cdata.bge_rx_return_ring_map,
2980 	    &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2981 	if (error)
2982 		return (error);
2983 
2984 	/* Create tag for TX ring. */
2985 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2986 	    &sc->bge_cdata.bge_tx_ring_tag,
2987 	    (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2988 	    &sc->bge_cdata.bge_tx_ring_map,
2989 	    &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2990 	if (error)
2991 		return (error);
2992 
2993 	/*
2994 	 * Create tag for status block.
2995 	 * Because we only use single Tx/Rx/Rx return ring, use
2996 	 * minimum status block size except BCM5700 AX/BX which
2997 	 * seems to want to see full status block size regardless
2998 	 * of configured number of ring.
2999 	 */
3000 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3001 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3002 		sbsz = BGE_STATUS_BLK_SZ;
3003 	else
3004 		sbsz = 32;
3005 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3006 	    &sc->bge_cdata.bge_status_tag,
3007 	    (uint8_t **)&sc->bge_ldata.bge_status_block,
3008 	    &sc->bge_cdata.bge_status_map,
3009 	    &sc->bge_ldata.bge_status_block_paddr, "status block");
3010 	if (error)
3011 		return (error);
3012 
3013 	/* Create tag for statistics block. */
3014 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3015 	    &sc->bge_cdata.bge_stats_tag,
3016 	    (uint8_t **)&sc->bge_ldata.bge_stats,
3017 	    &sc->bge_cdata.bge_stats_map,
3018 	    &sc->bge_ldata.bge_stats_paddr, "statistics block");
3019 	if (error)
3020 		return (error);
3021 
3022 	/* Create tag for jumbo RX ring. */
3023 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3024 		error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3025 		    &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3026 		    (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3027 		    &sc->bge_cdata.bge_rx_jumbo_ring_map,
3028 		    &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3029 		if (error)
3030 			return (error);
3031 	}
3032 
3033 	/* Create parent tag for buffers. */
3034 	if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3035 		/*
3036 		 * XXX
3037 		 * watchdog timeout issue was observed on BCM5704 which
3038 		 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3039 		 * Both limiting DMA address space to 32bits and flushing
3040 		 * mailbox write seem to address the issue.
3041 		 */
3042 		if (sc->bge_pcixcap != 0)
3043 			lowaddr = BUS_SPACE_MAXADDR_32BIT;
3044 	}
3045 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3046 	    BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3047 	    BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3048 	    &sc->bge_cdata.bge_buffer_tag);
3049 	if (error != 0) {
3050 		device_printf(sc->bge_dev,
3051 		    "could not allocate buffer dma tag\n");
3052 		return (ENOMEM);
3053 	}
3054 	/* Create tag for Tx mbufs. */
3055 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3056 		txsegsz = BGE_TSOSEG_SZ;
3057 		txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3058 	} else {
3059 		txsegsz = MCLBYTES;
3060 		txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3061 	}
3062 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3063 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3064 	    txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3065 	    &sc->bge_cdata.bge_tx_mtag);
3066 
3067 	if (error) {
3068 		device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3069 		return (ENOMEM);
3070 	}
3071 
3072 	/* Create tag for Rx mbufs. */
3073 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3074 		rxmaxsegsz = MJUM9BYTES;
3075 	else
3076 		rxmaxsegsz = MCLBYTES;
3077 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3078 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3079 	    rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3080 
3081 	if (error) {
3082 		device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3083 		return (ENOMEM);
3084 	}
3085 
3086 	/* Create DMA maps for RX buffers. */
3087 	error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3088 	    &sc->bge_cdata.bge_rx_std_sparemap);
3089 	if (error) {
3090 		device_printf(sc->bge_dev,
3091 		    "can't create spare DMA map for RX\n");
3092 		return (ENOMEM);
3093 	}
3094 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3095 		error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3096 			    &sc->bge_cdata.bge_rx_std_dmamap[i]);
3097 		if (error) {
3098 			device_printf(sc->bge_dev,
3099 			    "can't create DMA map for RX\n");
3100 			return (ENOMEM);
3101 		}
3102 	}
3103 
3104 	/* Create DMA maps for TX buffers. */
3105 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
3106 		error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3107 			    &sc->bge_cdata.bge_tx_dmamap[i]);
3108 		if (error) {
3109 			device_printf(sc->bge_dev,
3110 			    "can't create DMA map for TX\n");
3111 			return (ENOMEM);
3112 		}
3113 	}
3114 
3115 	/* Create tags for jumbo RX buffers. */
3116 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3117 		error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3118 		    1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3119 		    NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3120 		    0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3121 		if (error) {
3122 			device_printf(sc->bge_dev,
3123 			    "could not allocate jumbo dma tag\n");
3124 			return (ENOMEM);
3125 		}
3126 		/* Create DMA maps for jumbo RX buffers. */
3127 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3128 		    0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3129 		if (error) {
3130 			device_printf(sc->bge_dev,
3131 			    "can't create spare DMA map for jumbo RX\n");
3132 			return (ENOMEM);
3133 		}
3134 		for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3135 			error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3136 				    0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3137 			if (error) {
3138 				device_printf(sc->bge_dev,
3139 				    "can't create DMA map for jumbo RX\n");
3140 				return (ENOMEM);
3141 			}
3142 		}
3143 	}
3144 
3145 	return (0);
3146 }
3147 
3148 /*
3149  * Return true if this device has more than one port.
3150  */
3151 static int
3152 bge_has_multiple_ports(struct bge_softc *sc)
3153 {
3154 	device_t dev = sc->bge_dev;
3155 	u_int b, d, f, fscan, s;
3156 
3157 	d = pci_get_domain(dev);
3158 	b = pci_get_bus(dev);
3159 	s = pci_get_slot(dev);
3160 	f = pci_get_function(dev);
3161 	for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3162 		if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3163 			return (1);
3164 	return (0);
3165 }
3166 
3167 /*
3168  * Return true if MSI can be used with this device.
3169  */
3170 static int
3171 bge_can_use_msi(struct bge_softc *sc)
3172 {
3173 	int can_use_msi = 0;
3174 
3175 	if (sc->bge_msi == 0)
3176 		return (0);
3177 
3178 	/* Disable MSI for polling(4). */
3179 #ifdef DEVICE_POLLING
3180 	return (0);
3181 #endif
3182 	switch (sc->bge_asicrev) {
3183 	case BGE_ASICREV_BCM5714_A0:
3184 	case BGE_ASICREV_BCM5714:
3185 		/*
3186 		 * Apparently, MSI doesn't work when these chips are
3187 		 * configured in single-port mode.
3188 		 */
3189 		if (bge_has_multiple_ports(sc))
3190 			can_use_msi = 1;
3191 		break;
3192 	case BGE_ASICREV_BCM5750:
3193 		if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3194 		    sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3195 			can_use_msi = 1;
3196 		break;
3197 	default:
3198 		if (BGE_IS_575X_PLUS(sc))
3199 			can_use_msi = 1;
3200 	}
3201 	return (can_use_msi);
3202 }
3203 
3204 static int
3205 bge_mbox_reorder(struct bge_softc *sc)
3206 {
3207 	/* Lists of PCI bridges that are known to reorder mailbox writes. */
3208 	static const struct mbox_reorder {
3209 		const uint16_t vendor;
3210 		const uint16_t device;
3211 		const char *desc;
3212 	} mbox_reorder_lists[] = {
3213 		{ 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3214 	};
3215 	devclass_t pci, pcib;
3216 	device_t bus, dev;
3217 	int i;
3218 
3219 	pci = devclass_find("pci");
3220 	pcib = devclass_find("pcib");
3221 	dev = sc->bge_dev;
3222 	bus = device_get_parent(dev);
3223 	for (;;) {
3224 		dev = device_get_parent(bus);
3225 		bus = device_get_parent(dev);
3226 		if (device_get_devclass(dev) != pcib)
3227 			break;
3228 		for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3229 			if (pci_get_vendor(dev) ==
3230 			    mbox_reorder_lists[i].vendor &&
3231 			    pci_get_device(dev) ==
3232 			    mbox_reorder_lists[i].device) {
3233 				device_printf(sc->bge_dev,
3234 				    "enabling MBOX workaround for %s\n",
3235 				    mbox_reorder_lists[i].desc);
3236 				return (1);
3237 			}
3238 		}
3239 		if (device_get_devclass(bus) != pci)
3240 			break;
3241 	}
3242 	return (0);
3243 }
3244 
3245 static void
3246 bge_devinfo(struct bge_softc *sc)
3247 {
3248 	uint32_t cfg, clk;
3249 
3250 	device_printf(sc->bge_dev,
3251 	    "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3252 	    sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3253 	if (sc->bge_flags & BGE_FLAG_PCIE)
3254 		printf("PCI-E\n");
3255 	else if (sc->bge_flags & BGE_FLAG_PCIX) {
3256 		printf("PCI-X ");
3257 		cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3258 		if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3259 			clk = 133;
3260 		else {
3261 			clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3262 			switch (clk) {
3263 			case 0:
3264 				clk = 33;
3265 				break;
3266 			case 2:
3267 				clk = 50;
3268 				break;
3269 			case 4:
3270 				clk = 66;
3271 				break;
3272 			case 6:
3273 				clk = 100;
3274 				break;
3275 			case 7:
3276 				clk = 133;
3277 				break;
3278 			}
3279 		}
3280 		printf("%u MHz\n", clk);
3281 	} else {
3282 		if (sc->bge_pcixcap != 0)
3283 			printf("PCI on PCI-X ");
3284 		else
3285 			printf("PCI ");
3286 		cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3287 		if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3288 			clk = 66;
3289 		else
3290 			clk = 33;
3291 		if (cfg & BGE_PCISTATE_32BIT_BUS)
3292 			printf("%u MHz; 32bit\n", clk);
3293 		else
3294 			printf("%u MHz; 64bit\n", clk);
3295 	}
3296 }
3297 
3298 static int
3299 bge_attach(device_t dev)
3300 {
3301 	struct ifnet *ifp;
3302 	struct bge_softc *sc;
3303 	uint32_t hwcfg = 0, misccfg, pcistate;
3304 	u_char eaddr[ETHER_ADDR_LEN];
3305 	int capmask, error, msicount, reg, rid, trys;
3306 
3307 	sc = device_get_softc(dev);
3308 	sc->bge_dev = dev;
3309 
3310 	BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3311 	TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3312 	callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3313 
3314 	/*
3315 	 * Map control/status registers.
3316 	 */
3317 	pci_enable_busmaster(dev);
3318 
3319 	rid = PCIR_BAR(0);
3320 	sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3321 	    RF_ACTIVE);
3322 
3323 	if (sc->bge_res == NULL) {
3324 		device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3325 		error = ENXIO;
3326 		goto fail;
3327 	}
3328 
3329 	/* Save various chip information. */
3330 	sc->bge_func_addr = pci_get_function(dev);
3331 	sc->bge_chipid = bge_chipid(dev);
3332 	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3333 	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3334 
3335 	/* Set default PHY address. */
3336 	sc->bge_phy_addr = 1;
3337 	 /*
3338 	  * PHY address mapping for various devices.
3339 	  *
3340 	  *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3341 	  * ---------+-------+-------+-------+-------+
3342 	  * BCM57XX  |   1   |   X   |   X   |   X   |
3343 	  * BCM5704  |   1   |   X   |   1   |   X   |
3344 	  * BCM5717  |   1   |   8   |   2   |   9   |
3345 	  * BCM5719  |   1   |   8   |   2   |   9   |
3346 	  * BCM5720  |   1   |   8   |   2   |   9   |
3347 	  *
3348 	  *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3349 	  * ---------+-------+-------+-------+-------+
3350 	  * BCM57XX  |   X   |   X   |   X   |   X   |
3351 	  * BCM5704  |   X   |   X   |   X   |   X   |
3352 	  * BCM5717  |   X   |   X   |   X   |   X   |
3353 	  * BCM5719  |   3   |   10  |   4   |   11  |
3354 	  * BCM5720  |   X   |   X   |   X   |   X   |
3355 	  *
3356 	  * Other addresses may respond but they are not
3357 	  * IEEE compliant PHYs and should be ignored.
3358 	  */
3359 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3360 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3361 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3362 		if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3363 			if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3364 			    BGE_SGDIGSTS_IS_SERDES)
3365 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3366 			else
3367 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3368 		} else {
3369 			if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3370 			    BGE_CPMU_PHY_STRAP_IS_SERDES)
3371 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3372 			else
3373 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3374 		}
3375 	}
3376 
3377 	if (bge_has_eaddr(sc))
3378 		sc->bge_flags |= BGE_FLAG_EADDR;
3379 
3380 	/* Save chipset family. */
3381 	switch (sc->bge_asicrev) {
3382 	case BGE_ASICREV_BCM5762:
3383 	case BGE_ASICREV_BCM57765:
3384 	case BGE_ASICREV_BCM57766:
3385 		sc->bge_flags |= BGE_FLAG_57765_PLUS;
3386 		/* FALLTHROUGH */
3387 	case BGE_ASICREV_BCM5717:
3388 	case BGE_ASICREV_BCM5719:
3389 	case BGE_ASICREV_BCM5720:
3390 		sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3391 		    BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3392 		    BGE_FLAG_JUMBO_FRAME;
3393 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3394 		    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3395 			/*
3396 			 * Enable work around for DMA engine miscalculation
3397 			 * of TXMBUF available space.
3398 			 */
3399 			sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3400 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3401 			    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3402 				/* Jumbo frame on BCM5719 A0 does not work. */
3403 				sc->bge_flags &= ~BGE_FLAG_JUMBO;
3404 			}
3405 		}
3406 		break;
3407 	case BGE_ASICREV_BCM5755:
3408 	case BGE_ASICREV_BCM5761:
3409 	case BGE_ASICREV_BCM5784:
3410 	case BGE_ASICREV_BCM5785:
3411 	case BGE_ASICREV_BCM5787:
3412 	case BGE_ASICREV_BCM57780:
3413 		sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3414 		    BGE_FLAG_5705_PLUS;
3415 		break;
3416 	case BGE_ASICREV_BCM5700:
3417 	case BGE_ASICREV_BCM5701:
3418 	case BGE_ASICREV_BCM5703:
3419 	case BGE_ASICREV_BCM5704:
3420 		sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3421 		break;
3422 	case BGE_ASICREV_BCM5714_A0:
3423 	case BGE_ASICREV_BCM5780:
3424 	case BGE_ASICREV_BCM5714:
3425 		sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3426 		/* FALLTHROUGH */
3427 	case BGE_ASICREV_BCM5750:
3428 	case BGE_ASICREV_BCM5752:
3429 	case BGE_ASICREV_BCM5906:
3430 		sc->bge_flags |= BGE_FLAG_575X_PLUS;
3431 		/* FALLTHROUGH */
3432 	case BGE_ASICREV_BCM5705:
3433 		sc->bge_flags |= BGE_FLAG_5705_PLUS;
3434 		break;
3435 	}
3436 
3437 	/* Identify chips with APE processor. */
3438 	switch (sc->bge_asicrev) {
3439 	case BGE_ASICREV_BCM5717:
3440 	case BGE_ASICREV_BCM5719:
3441 	case BGE_ASICREV_BCM5720:
3442 	case BGE_ASICREV_BCM5761:
3443 	case BGE_ASICREV_BCM5762:
3444 		sc->bge_flags |= BGE_FLAG_APE;
3445 		break;
3446 	}
3447 
3448 	/* Chips with APE need BAR2 access for APE registers/memory. */
3449 	if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3450 		rid = PCIR_BAR(2);
3451 		sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3452 		    RF_ACTIVE);
3453 		if (sc->bge_res2 == NULL) {
3454 			device_printf (sc->bge_dev,
3455 			    "couldn't map BAR2 memory\n");
3456 			error = ENXIO;
3457 			goto fail;
3458 		}
3459 
3460 		/* Enable APE register/memory access by host driver. */
3461 		pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3462 		pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3463 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3464 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3465 		pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3466 
3467 		bge_ape_lock_init(sc);
3468 		bge_ape_read_fw_ver(sc);
3469 	}
3470 
3471 	/* Add SYSCTLs, requires the chipset family to be set. */
3472 	bge_add_sysctls(sc);
3473 
3474 	/* Identify the chips that use an CPMU. */
3475 	if (BGE_IS_5717_PLUS(sc) ||
3476 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3477 	    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3478 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3479 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
3480 		sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3481 	if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3482 		sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3483 	else
3484 		sc->bge_mi_mode = BGE_MIMODE_BASE;
3485 	/* Enable auto polling for BCM570[0-5]. */
3486 	if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3487 		sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3488 
3489 	/*
3490 	 * All Broadcom controllers have 4GB boundary DMA bug.
3491 	 * Whenever an address crosses a multiple of the 4GB boundary
3492 	 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3493 	 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3494 	 * state machine will lockup and cause the device to hang.
3495 	 */
3496 	sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3497 
3498 	/* BCM5755 or higher and BCM5906 have short DMA bug. */
3499 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3500 		sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3501 
3502 	/*
3503 	 * BCM5719 cannot handle DMA requests for DMA segments that
3504 	 * have larger than 4KB in size.  However the maximum DMA
3505 	 * segment size created in DMA tag is 4KB for TSO, so we
3506 	 * wouldn't encounter the issue here.
3507 	 */
3508 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3509 		sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3510 
3511 	misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3512 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3513 		if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3514 		    misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3515 			sc->bge_flags |= BGE_FLAG_5788;
3516 	}
3517 
3518 	capmask = BMSR_DEFCAPMASK;
3519 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3520 	    (misccfg == 0x4000 || misccfg == 0x8000)) ||
3521 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3522 	    pci_get_vendor(dev) == BCOM_VENDORID &&
3523 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3524 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3525 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3526 	    (pci_get_vendor(dev) == BCOM_VENDORID &&
3527 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3528 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3529 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3530 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3531 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3532 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3533 	    sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3534 		/* These chips are 10/100 only. */
3535 		capmask &= ~BMSR_EXTSTAT;
3536 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3537 	}
3538 
3539 	/*
3540 	 * Some controllers seem to require a special firmware to use
3541 	 * TSO. But the firmware is not available to FreeBSD and Linux
3542 	 * claims that the TSO performed by the firmware is slower than
3543 	 * hardware based TSO. Moreover the firmware based TSO has one
3544 	 * known bug which can't handle TSO if Ethernet header + IP/TCP
3545 	 * header is greater than 80 bytes. A workaround for the TSO
3546 	 * bug exist but it seems it's too expensive than not using
3547 	 * TSO at all. Some hardwares also have the TSO bug so limit
3548 	 * the TSO to the controllers that are not affected TSO issues
3549 	 * (e.g. 5755 or higher).
3550 	 */
3551 	if (BGE_IS_5717_PLUS(sc)) {
3552 		/* BCM5717 requires different TSO configuration. */
3553 		sc->bge_flags |= BGE_FLAG_TSO3;
3554 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3555 		    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3556 			/* TSO on BCM5719 A0 does not work. */
3557 			sc->bge_flags &= ~BGE_FLAG_TSO3;
3558 		}
3559 	} else if (BGE_IS_5755_PLUS(sc)) {
3560 		/*
3561 		 * BCM5754 and BCM5787 shares the same ASIC id so
3562 		 * explicit device id check is required.
3563 		 * Due to unknown reason TSO does not work on BCM5755M.
3564 		 */
3565 		if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3566 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3567 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3568 			sc->bge_flags |= BGE_FLAG_TSO;
3569 	}
3570 
3571 	/*
3572 	 * Check if this is a PCI-X or PCI Express device.
3573 	 */
3574 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3575 		/*
3576 		 * Found a PCI Express capabilities register, this
3577 		 * must be a PCI Express device.
3578 		 */
3579 		sc->bge_flags |= BGE_FLAG_PCIE;
3580 		sc->bge_expcap = reg;
3581 		/* Extract supported maximum payload size. */
3582 		sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3583 		    PCIER_DEVICE_CAP, 2);
3584 		sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3585 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3586 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
3587 			sc->bge_expmrq = 2048;
3588 		else
3589 			sc->bge_expmrq = 4096;
3590 		pci_set_max_read_req(dev, sc->bge_expmrq);
3591 	} else {
3592 		/*
3593 		 * Check if the device is in PCI-X Mode.
3594 		 * (This bit is not valid on PCI Express controllers.)
3595 		 */
3596 		if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3597 			sc->bge_pcixcap = reg;
3598 		if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3599 		    BGE_PCISTATE_PCI_BUSMODE) == 0)
3600 			sc->bge_flags |= BGE_FLAG_PCIX;
3601 	}
3602 
3603 	/*
3604 	 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3605 	 * not actually a MAC controller bug but an issue with the embedded
3606 	 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3607 	 */
3608 	if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3609 		sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3610 	/*
3611 	 * Some PCI-X bridges are known to trigger write reordering to
3612 	 * the mailbox registers. Typical phenomena is watchdog timeouts
3613 	 * caused by out-of-order TX completions.  Enable workaround for
3614 	 * PCI-X devices that live behind these bridges.
3615 	 * Note, PCI-X controllers can run in PCI mode so we can't use
3616 	 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3617 	 */
3618 	if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3619 		sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3620 	/*
3621 	 * Allocate the interrupt, using MSI if possible.  These devices
3622 	 * support 8 MSI messages, but only the first one is used in
3623 	 * normal operation.
3624 	 */
3625 	rid = 0;
3626 	if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3627 		sc->bge_msicap = reg;
3628 		if (bge_can_use_msi(sc)) {
3629 			msicount = pci_msi_count(dev);
3630 			if (msicount > 1)
3631 				msicount = 1;
3632 		} else
3633 			msicount = 0;
3634 		if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3635 			rid = 1;
3636 			sc->bge_flags |= BGE_FLAG_MSI;
3637 		}
3638 	}
3639 
3640 	/*
3641 	 * All controllers except BCM5700 supports tagged status but
3642 	 * we use tagged status only for MSI case on BCM5717. Otherwise
3643 	 * MSI on BCM5717 does not work.
3644 	 */
3645 #ifndef DEVICE_POLLING
3646 	if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3647 		sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3648 #endif
3649 
3650 	sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3651 	    RF_SHAREABLE | RF_ACTIVE);
3652 
3653 	if (sc->bge_irq == NULL) {
3654 		device_printf(sc->bge_dev, "couldn't map interrupt\n");
3655 		error = ENXIO;
3656 		goto fail;
3657 	}
3658 
3659 	bge_devinfo(sc);
3660 
3661 	sc->bge_asf_mode = 0;
3662 	/* No ASF if APE present. */
3663 	if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3664 		if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3665 		    BGE_SRAM_DATA_SIG_MAGIC)) {
3666 			if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3667 			    BGE_HWCFG_ASF) {
3668 				sc->bge_asf_mode |= ASF_ENABLE;
3669 				sc->bge_asf_mode |= ASF_STACKUP;
3670 				if (BGE_IS_575X_PLUS(sc))
3671 					sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3672 			}
3673 		}
3674 	}
3675 
3676 	bge_stop_fw(sc);
3677 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3678 	if (bge_reset(sc)) {
3679 		device_printf(sc->bge_dev, "chip reset failed\n");
3680 		error = ENXIO;
3681 		goto fail;
3682 	}
3683 
3684 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3685 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3686 
3687 	if (bge_chipinit(sc)) {
3688 		device_printf(sc->bge_dev, "chip initialization failed\n");
3689 		error = ENXIO;
3690 		goto fail;
3691 	}
3692 
3693 	error = bge_get_eaddr(sc, eaddr);
3694 	if (error) {
3695 		device_printf(sc->bge_dev,
3696 		    "failed to read station address\n");
3697 		error = ENXIO;
3698 		goto fail;
3699 	}
3700 
3701 	/* 5705 limits RX return ring to 512 entries. */
3702 	if (BGE_IS_5717_PLUS(sc))
3703 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3704 	else if (BGE_IS_5705_PLUS(sc))
3705 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3706 	else
3707 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3708 
3709 	if (bge_dma_alloc(sc)) {
3710 		device_printf(sc->bge_dev,
3711 		    "failed to allocate DMA resources\n");
3712 		error = ENXIO;
3713 		goto fail;
3714 	}
3715 
3716 	/* Set default tuneable values. */
3717 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3718 	sc->bge_rx_coal_ticks = 150;
3719 	sc->bge_tx_coal_ticks = 150;
3720 	sc->bge_rx_max_coal_bds = 10;
3721 	sc->bge_tx_max_coal_bds = 10;
3722 
3723 	/* Initialize checksum features to use. */
3724 	sc->bge_csum_features = BGE_CSUM_FEATURES;
3725 	if (sc->bge_forced_udpcsum != 0)
3726 		sc->bge_csum_features |= CSUM_UDP;
3727 
3728 	/* Set up ifnet structure */
3729 	ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3730 	if (ifp == NULL) {
3731 		device_printf(sc->bge_dev, "failed to if_alloc()\n");
3732 		error = ENXIO;
3733 		goto fail;
3734 	}
3735 	ifp->if_softc = sc;
3736 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3737 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3738 	ifp->if_ioctl = bge_ioctl;
3739 	ifp->if_start = bge_start;
3740 	ifp->if_init = bge_init;
3741 	ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3742 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3743 	IFQ_SET_READY(&ifp->if_snd);
3744 	ifp->if_hwassist = sc->bge_csum_features;
3745 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3746 	    IFCAP_VLAN_MTU;
3747 	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3748 		ifp->if_hwassist |= CSUM_TSO;
3749 		ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3750 	}
3751 #ifdef IFCAP_VLAN_HWCSUM
3752 	ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3753 #endif
3754 	ifp->if_capenable = ifp->if_capabilities;
3755 #ifdef DEVICE_POLLING
3756 	ifp->if_capabilities |= IFCAP_POLLING;
3757 #endif
3758 
3759 	/*
3760 	 * 5700 B0 chips do not support checksumming correctly due
3761 	 * to hardware bugs.
3762 	 */
3763 	if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3764 		ifp->if_capabilities &= ~IFCAP_HWCSUM;
3765 		ifp->if_capenable &= ~IFCAP_HWCSUM;
3766 		ifp->if_hwassist = 0;
3767 	}
3768 
3769 	/*
3770 	 * Figure out what sort of media we have by checking the
3771 	 * hardware config word in the first 32k of NIC internal memory,
3772 	 * or fall back to examining the EEPROM if necessary.
3773 	 * Note: on some BCM5700 cards, this value appears to be unset.
3774 	 * If that's the case, we have to rely on identifying the NIC
3775 	 * by its PCI subsystem ID, as we do below for the SysKonnect
3776 	 * SK-9D41.
3777 	 */
3778 	if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3779 		hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3780 	else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3781 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3782 		if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3783 		    sizeof(hwcfg))) {
3784 			device_printf(sc->bge_dev, "failed to read EEPROM\n");
3785 			error = ENXIO;
3786 			goto fail;
3787 		}
3788 		hwcfg = ntohl(hwcfg);
3789 	}
3790 
3791 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
3792 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3793 	    SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3794 		if (BGE_IS_5705_PLUS(sc)) {
3795 			sc->bge_flags |= BGE_FLAG_MII_SERDES;
3796 			sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3797 		} else
3798 			sc->bge_flags |= BGE_FLAG_TBI;
3799 	}
3800 
3801 	/* Set various PHY bug flags. */
3802 	if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3803 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3804 		sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3805 	if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3806 	    sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3807 		sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3808 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3809 		sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3810 	if (pci_get_subvendor(dev) == DELL_VENDORID)
3811 		sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3812 	if ((BGE_IS_5705_PLUS(sc)) &&
3813 	    sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3814 	    sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3815 	    sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3816 	    !BGE_IS_5717_PLUS(sc)) {
3817 		if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3818 		    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3819 		    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3820 		    sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3821 			if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3822 			    pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3823 				sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3824 			if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3825 				sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3826 		} else
3827 			sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3828 	}
3829 
3830 	/*
3831 	 * Don't enable Ethernet@WireSpeed for the 5700 or the
3832 	 * 5705 A0 and A1 chips.
3833 	 */
3834 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3835 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3836 	    (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3837 	    sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3838 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3839 
3840 	if (sc->bge_flags & BGE_FLAG_TBI) {
3841 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3842 		    bge_ifmedia_sts);
3843 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3844 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3845 		    0, NULL);
3846 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3847 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3848 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3849 	} else {
3850 		/*
3851 		 * Do transceiver setup and tell the firmware the
3852 		 * driver is down so we can try to get access the
3853 		 * probe if ASF is running.  Retry a couple of times
3854 		 * if we get a conflict with the ASF firmware accessing
3855 		 * the PHY.
3856 		 */
3857 		trys = 0;
3858 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3859 again:
3860 		bge_asf_driver_up(sc);
3861 
3862 		error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3863 		    bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3864 		    MIIF_DOPAUSE);
3865 		if (error != 0) {
3866 			if (trys++ < 4) {
3867 				device_printf(sc->bge_dev, "Try again\n");
3868 				bge_miibus_writereg(sc->bge_dev,
3869 				    sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3870 				goto again;
3871 			}
3872 			device_printf(sc->bge_dev, "attaching PHYs failed\n");
3873 			goto fail;
3874 		}
3875 
3876 		/*
3877 		 * Now tell the firmware we are going up after probing the PHY
3878 		 */
3879 		if (sc->bge_asf_mode & ASF_STACKUP)
3880 			BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3881 	}
3882 
3883 	/*
3884 	 * When using the BCM5701 in PCI-X mode, data corruption has
3885 	 * been observed in the first few bytes of some received packets.
3886 	 * Aligning the packet buffer in memory eliminates the corruption.
3887 	 * Unfortunately, this misaligns the packet payloads.  On platforms
3888 	 * which do not support unaligned accesses, we will realign the
3889 	 * payloads by copying the received packets.
3890 	 */
3891 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3892 	    sc->bge_flags & BGE_FLAG_PCIX)
3893                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3894 
3895 	/*
3896 	 * Call MI attach routine.
3897 	 */
3898 	ether_ifattach(ifp, eaddr);
3899 
3900 	/* Tell upper layer we support long frames. */
3901 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3902 
3903 	/*
3904 	 * Hookup IRQ last.
3905 	 */
3906 	if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3907 		/* Take advantage of single-shot MSI. */
3908 		CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3909 		    ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3910 		sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3911 		    taskqueue_thread_enqueue, &sc->bge_tq);
3912 		if (sc->bge_tq == NULL) {
3913 			device_printf(dev, "could not create taskqueue.\n");
3914 			ether_ifdetach(ifp);
3915 			error = ENOMEM;
3916 			goto fail;
3917 		}
3918 		error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3919 		    "%s taskq", device_get_nameunit(sc->bge_dev));
3920 		if (error != 0) {
3921 			device_printf(dev, "could not start threads.\n");
3922 			ether_ifdetach(ifp);
3923 			goto fail;
3924 		}
3925 		error = bus_setup_intr(dev, sc->bge_irq,
3926 		    INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3927 		    &sc->bge_intrhand);
3928 	} else
3929 		error = bus_setup_intr(dev, sc->bge_irq,
3930 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3931 		    &sc->bge_intrhand);
3932 
3933 	if (error) {
3934 		ether_ifdetach(ifp);
3935 		device_printf(sc->bge_dev, "couldn't set up irq\n");
3936 	}
3937 
3938 fail:
3939 	if (error)
3940 		bge_detach(dev);
3941 	return (error);
3942 }
3943 
3944 static int
3945 bge_detach(device_t dev)
3946 {
3947 	struct bge_softc *sc;
3948 	struct ifnet *ifp;
3949 
3950 	sc = device_get_softc(dev);
3951 	ifp = sc->bge_ifp;
3952 
3953 #ifdef DEVICE_POLLING
3954 	if (ifp->if_capenable & IFCAP_POLLING)
3955 		ether_poll_deregister(ifp);
3956 #endif
3957 
3958 	if (device_is_attached(dev)) {
3959 		ether_ifdetach(ifp);
3960 		BGE_LOCK(sc);
3961 		bge_stop(sc);
3962 		BGE_UNLOCK(sc);
3963 		callout_drain(&sc->bge_stat_ch);
3964 	}
3965 
3966 	if (sc->bge_tq)
3967 		taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3968 
3969 	if (sc->bge_flags & BGE_FLAG_TBI)
3970 		ifmedia_removeall(&sc->bge_ifmedia);
3971 	else if (sc->bge_miibus != NULL) {
3972 		bus_generic_detach(dev);
3973 		device_delete_child(dev, sc->bge_miibus);
3974 	}
3975 
3976 	bge_release_resources(sc);
3977 
3978 	return (0);
3979 }
3980 
3981 static void
3982 bge_release_resources(struct bge_softc *sc)
3983 {
3984 	device_t dev;
3985 
3986 	dev = sc->bge_dev;
3987 
3988 	if (sc->bge_tq != NULL)
3989 		taskqueue_free(sc->bge_tq);
3990 
3991 	if (sc->bge_intrhand != NULL)
3992 		bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3993 
3994 	if (sc->bge_irq != NULL)
3995 		bus_release_resource(dev, SYS_RES_IRQ,
3996 		    sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3997 
3998 	if (sc->bge_flags & BGE_FLAG_MSI)
3999 		pci_release_msi(dev);
4000 
4001 	if (sc->bge_res != NULL)
4002 		bus_release_resource(dev, SYS_RES_MEMORY,
4003 		    PCIR_BAR(0), sc->bge_res);
4004 
4005 	if (sc->bge_res2 != NULL)
4006 		bus_release_resource(dev, SYS_RES_MEMORY,
4007 		    PCIR_BAR(2), sc->bge_res2);
4008 
4009 	if (sc->bge_ifp != NULL)
4010 		if_free(sc->bge_ifp);
4011 
4012 	bge_dma_free(sc);
4013 
4014 	if (mtx_initialized(&sc->bge_mtx))	/* XXX */
4015 		BGE_LOCK_DESTROY(sc);
4016 }
4017 
4018 static int
4019 bge_reset(struct bge_softc *sc)
4020 {
4021 	device_t dev;
4022 	uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4023 	void (*write_op)(struct bge_softc *, int, int);
4024 	uint16_t devctl;
4025 	int i;
4026 
4027 	dev = sc->bge_dev;
4028 
4029 	mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4030 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4031 		mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4032 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4033 
4034 	if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4035 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4036 		if (sc->bge_flags & BGE_FLAG_PCIE)
4037 			write_op = bge_writemem_direct;
4038 		else
4039 			write_op = bge_writemem_ind;
4040 	} else
4041 		write_op = bge_writereg_ind;
4042 
4043 	if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4044 	    sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4045 		CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4046 		for (i = 0; i < 8000; i++) {
4047 			if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4048 			    BGE_NVRAMSWARB_GNT1)
4049 				break;
4050 			DELAY(20);
4051 		}
4052 		if (i == 8000) {
4053 			if (bootverbose)
4054 				device_printf(dev, "NVRAM lock timedout!\n");
4055 		}
4056 	}
4057 	/* Take APE lock when performing reset. */
4058 	bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4059 
4060 	/* Save some important PCI state. */
4061 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4062 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
4063 
4064 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4065 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4066 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4067 
4068 	/* Disable fastboot on controllers that support it. */
4069 	if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4070 	    BGE_IS_5755_PLUS(sc)) {
4071 		if (bootverbose)
4072 			device_printf(dev, "Disabling fastboot\n");
4073 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4074 	}
4075 
4076 	/*
4077 	 * Write the magic number to SRAM at offset 0xB50.
4078 	 * When firmware finishes its initialization it will
4079 	 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4080 	 */
4081 	bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4082 
4083 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4084 
4085 	/* XXX: Broadcom Linux driver. */
4086 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4087 		if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4088 		    (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4089 			if (CSR_READ_4(sc, 0x7E2C) == 0x60)	/* PCIE 1.0 */
4090 				CSR_WRITE_4(sc, 0x7E2C, 0x20);
4091 		}
4092 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4093 			/* Prevent PCIE link training during global reset */
4094 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4095 			reset |= 1 << 29;
4096 		}
4097 	}
4098 
4099 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4100 		val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4101 		CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4102 		    val | BGE_VCPU_STATUS_DRV_RESET);
4103 		val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4104 		CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4105 		    val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4106 	}
4107 
4108 	/*
4109 	 * Set GPHY Power Down Override to leave GPHY
4110 	 * powered up in D0 uninitialized.
4111 	 */
4112 	if (BGE_IS_5705_PLUS(sc) &&
4113 	    (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4114 		reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4115 
4116 	/* Issue global reset */
4117 	write_op(sc, BGE_MISC_CFG, reset);
4118 
4119 	if (sc->bge_flags & BGE_FLAG_PCIE)
4120 		DELAY(100 * 1000);
4121 	else
4122 		DELAY(1000);
4123 
4124 	/* XXX: Broadcom Linux driver. */
4125 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4126 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4127 			DELAY(500000); /* wait for link training to complete */
4128 			val = pci_read_config(dev, 0xC4, 4);
4129 			pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4130 		}
4131 		devctl = pci_read_config(dev,
4132 		    sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4133 		/* Clear enable no snoop and disable relaxed ordering. */
4134 		devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4135 		    PCIEM_CTL_NOSNOOP_ENABLE);
4136 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4137 		    devctl, 2);
4138 		pci_set_max_read_req(dev, sc->bge_expmrq);
4139 		/* Clear error status. */
4140 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4141 		    PCIEM_STA_CORRECTABLE_ERROR |
4142 		    PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4143 		    PCIEM_STA_UNSUPPORTED_REQ, 2);
4144 	}
4145 
4146 	/* Reset some of the PCI state that got zapped by reset. */
4147 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4148 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4149 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4150 	val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4151 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4152 	    (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4153 		val |= BGE_PCISTATE_RETRY_SAME_DMA;
4154 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4155 		val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4156 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4157 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4158 	pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4159 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4160 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
4161 	/*
4162 	 * Disable PCI-X relaxed ordering to ensure status block update
4163 	 * comes first then packet buffer DMA. Otherwise driver may
4164 	 * read stale status block.
4165 	 */
4166 	if (sc->bge_flags & BGE_FLAG_PCIX) {
4167 		devctl = pci_read_config(dev,
4168 		    sc->bge_pcixcap + PCIXR_COMMAND, 2);
4169 		devctl &= ~PCIXM_COMMAND_ERO;
4170 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4171 			devctl &= ~PCIXM_COMMAND_MAX_READ;
4172 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4173 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4174 			devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4175 			    PCIXM_COMMAND_MAX_READ);
4176 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4177 		}
4178 		pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4179 		    devctl, 2);
4180 	}
4181 	/* Re-enable MSI, if necessary, and enable the memory arbiter. */
4182 	if (BGE_IS_5714_FAMILY(sc)) {
4183 		/* This chip disables MSI on reset. */
4184 		if (sc->bge_flags & BGE_FLAG_MSI) {
4185 			val = pci_read_config(dev,
4186 			    sc->bge_msicap + PCIR_MSI_CTRL, 2);
4187 			pci_write_config(dev,
4188 			    sc->bge_msicap + PCIR_MSI_CTRL,
4189 			    val | PCIM_MSICTRL_MSI_ENABLE, 2);
4190 			val = CSR_READ_4(sc, BGE_MSI_MODE);
4191 			CSR_WRITE_4(sc, BGE_MSI_MODE,
4192 			    val | BGE_MSIMODE_ENABLE);
4193 		}
4194 		val = CSR_READ_4(sc, BGE_MARB_MODE);
4195 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4196 	} else
4197 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4198 
4199 	/* Fix up byte swapping. */
4200 	CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4201 
4202 	val = CSR_READ_4(sc, BGE_MAC_MODE);
4203 	val = (val & ~mac_mode_mask) | mac_mode;
4204 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4205 	DELAY(40);
4206 
4207 	bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4208 
4209 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4210 		for (i = 0; i < BGE_TIMEOUT; i++) {
4211 			val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4212 			if (val & BGE_VCPU_STATUS_INIT_DONE)
4213 				break;
4214 			DELAY(100);
4215 		}
4216 		if (i == BGE_TIMEOUT) {
4217 			device_printf(dev, "reset timed out\n");
4218 			return (1);
4219 		}
4220 	} else {
4221 		/*
4222 		 * Poll until we see the 1's complement of the magic number.
4223 		 * This indicates that the firmware initialization is complete.
4224 		 * We expect this to fail if no chip containing the Ethernet
4225 		 * address is fitted though.
4226 		 */
4227 		for (i = 0; i < BGE_TIMEOUT; i++) {
4228 			DELAY(10);
4229 			val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4230 			if (val == ~BGE_SRAM_FW_MB_MAGIC)
4231 				break;
4232 		}
4233 
4234 		if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4235 			device_printf(dev,
4236 			    "firmware handshake timed out, found 0x%08x\n",
4237 			    val);
4238 		/* BCM57765 A0 needs additional time before accessing. */
4239 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4240 			DELAY(10 * 1000);	/* XXX */
4241 	}
4242 
4243 	/*
4244 	 * The 5704 in TBI mode apparently needs some special
4245 	 * adjustment to insure the SERDES drive level is set
4246 	 * to 1.2V.
4247 	 */
4248 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4249 	    sc->bge_flags & BGE_FLAG_TBI) {
4250 		val = CSR_READ_4(sc, BGE_SERDES_CFG);
4251 		val = (val & ~0xFFF) | 0x880;
4252 		CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4253 	}
4254 
4255 	/* XXX: Broadcom Linux driver. */
4256 	if (sc->bge_flags & BGE_FLAG_PCIE &&
4257 	    !BGE_IS_5717_PLUS(sc) &&
4258 	    sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4259 	    sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4260 		/* Enable Data FIFO protection. */
4261 		val = CSR_READ_4(sc, 0x7C00);
4262 		CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4263 	}
4264 
4265 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4266 		BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4267 		    CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4268 
4269 	return (0);
4270 }
4271 
4272 static __inline void
4273 bge_rxreuse_std(struct bge_softc *sc, int i)
4274 {
4275 	struct bge_rx_bd *r;
4276 
4277 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4278 	r->bge_flags = BGE_RXBDFLAG_END;
4279 	r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4280 	r->bge_idx = i;
4281 	BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4282 }
4283 
4284 static __inline void
4285 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4286 {
4287 	struct bge_extrx_bd *r;
4288 
4289 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4290 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4291 	r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4292 	r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4293 	r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4294 	r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4295 	r->bge_idx = i;
4296 	BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4297 }
4298 
4299 /*
4300  * Frame reception handling. This is called if there's a frame
4301  * on the receive return list.
4302  *
4303  * Note: we have to be able to handle two possibilities here:
4304  * 1) the frame is from the jumbo receive ring
4305  * 2) the frame is from the standard receive ring
4306  */
4307 
4308 static int
4309 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4310 {
4311 	struct ifnet *ifp;
4312 	int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4313 	uint16_t rx_cons;
4314 
4315 	rx_cons = sc->bge_rx_saved_considx;
4316 
4317 	/* Nothing to do. */
4318 	if (rx_cons == rx_prod)
4319 		return (rx_npkts);
4320 
4321 	ifp = sc->bge_ifp;
4322 
4323 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4324 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4325 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4326 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4327 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
4328 	    ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4329 	    (MCLBYTES - ETHER_ALIGN))
4330 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4331 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4332 
4333 	while (rx_cons != rx_prod) {
4334 		struct bge_rx_bd	*cur_rx;
4335 		uint32_t		rxidx;
4336 		struct mbuf		*m = NULL;
4337 		uint16_t		vlan_tag = 0;
4338 		int			have_tag = 0;
4339 
4340 #ifdef DEVICE_POLLING
4341 		if (ifp->if_capenable & IFCAP_POLLING) {
4342 			if (sc->rxcycles <= 0)
4343 				break;
4344 			sc->rxcycles--;
4345 		}
4346 #endif
4347 
4348 		cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4349 
4350 		rxidx = cur_rx->bge_idx;
4351 		BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4352 
4353 		if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4354 		    cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4355 			have_tag = 1;
4356 			vlan_tag = cur_rx->bge_vlan_tag;
4357 		}
4358 
4359 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4360 			jumbocnt++;
4361 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4362 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4363 				bge_rxreuse_jumbo(sc, rxidx);
4364 				continue;
4365 			}
4366 			if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4367 				bge_rxreuse_jumbo(sc, rxidx);
4368 				ifp->if_iqdrops++;
4369 				continue;
4370 			}
4371 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4372 		} else {
4373 			stdcnt++;
4374 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4375 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4376 				bge_rxreuse_std(sc, rxidx);
4377 				continue;
4378 			}
4379 			if (bge_newbuf_std(sc, rxidx) != 0) {
4380 				bge_rxreuse_std(sc, rxidx);
4381 				ifp->if_iqdrops++;
4382 				continue;
4383 			}
4384 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4385 		}
4386 
4387 		ifp->if_ipackets++;
4388 #ifndef __NO_STRICT_ALIGNMENT
4389 		/*
4390 		 * For architectures with strict alignment we must make sure
4391 		 * the payload is aligned.
4392 		 */
4393 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4394 			bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4395 			    cur_rx->bge_len);
4396 			m->m_data += ETHER_ALIGN;
4397 		}
4398 #endif
4399 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4400 		m->m_pkthdr.rcvif = ifp;
4401 
4402 		if (ifp->if_capenable & IFCAP_RXCSUM)
4403 			bge_rxcsum(sc, cur_rx, m);
4404 
4405 		/*
4406 		 * If we received a packet with a vlan tag,
4407 		 * attach that information to the packet.
4408 		 */
4409 		if (have_tag) {
4410 			m->m_pkthdr.ether_vtag = vlan_tag;
4411 			m->m_flags |= M_VLANTAG;
4412 		}
4413 
4414 		if (holdlck != 0) {
4415 			BGE_UNLOCK(sc);
4416 			(*ifp->if_input)(ifp, m);
4417 			BGE_LOCK(sc);
4418 		} else
4419 			(*ifp->if_input)(ifp, m);
4420 		rx_npkts++;
4421 
4422 		if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4423 			return (rx_npkts);
4424 	}
4425 
4426 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4427 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4428 	if (stdcnt > 0)
4429 		bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4430 		    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4431 
4432 	if (jumbocnt > 0)
4433 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4434 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4435 
4436 	sc->bge_rx_saved_considx = rx_cons;
4437 	bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4438 	if (stdcnt)
4439 		bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4440 		    BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4441 	if (jumbocnt)
4442 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4443 		    BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4444 #ifdef notyet
4445 	/*
4446 	 * This register wraps very quickly under heavy packet drops.
4447 	 * If you need correct statistics, you can enable this check.
4448 	 */
4449 	if (BGE_IS_5705_PLUS(sc))
4450 		ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4451 #endif
4452 	return (rx_npkts);
4453 }
4454 
4455 static void
4456 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4457 {
4458 
4459 	if (BGE_IS_5717_PLUS(sc)) {
4460 		if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4461 			if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4462 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4463 				if ((cur_rx->bge_error_flag &
4464 				    BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4465 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4466 			}
4467 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4468 				m->m_pkthdr.csum_data =
4469 				    cur_rx->bge_tcp_udp_csum;
4470 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4471 				    CSUM_PSEUDO_HDR;
4472 			}
4473 		}
4474 	} else {
4475 		if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4476 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4477 			if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4478 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4479 		}
4480 		if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4481 		    m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4482 			m->m_pkthdr.csum_data =
4483 			    cur_rx->bge_tcp_udp_csum;
4484 			m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4485 			    CSUM_PSEUDO_HDR;
4486 		}
4487 	}
4488 }
4489 
4490 static void
4491 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4492 {
4493 	struct bge_tx_bd *cur_tx;
4494 	struct ifnet *ifp;
4495 
4496 	BGE_LOCK_ASSERT(sc);
4497 
4498 	/* Nothing to do. */
4499 	if (sc->bge_tx_saved_considx == tx_cons)
4500 		return;
4501 
4502 	ifp = sc->bge_ifp;
4503 
4504 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4505 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4506 	/*
4507 	 * Go through our tx ring and free mbufs for those
4508 	 * frames that have been sent.
4509 	 */
4510 	while (sc->bge_tx_saved_considx != tx_cons) {
4511 		uint32_t		idx;
4512 
4513 		idx = sc->bge_tx_saved_considx;
4514 		cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4515 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4516 			ifp->if_opackets++;
4517 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4518 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4519 			    sc->bge_cdata.bge_tx_dmamap[idx],
4520 			    BUS_DMASYNC_POSTWRITE);
4521 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4522 			    sc->bge_cdata.bge_tx_dmamap[idx]);
4523 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4524 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
4525 		}
4526 		sc->bge_txcnt--;
4527 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4528 	}
4529 
4530 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4531 	if (sc->bge_txcnt == 0)
4532 		sc->bge_timer = 0;
4533 }
4534 
4535 #ifdef DEVICE_POLLING
4536 static int
4537 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4538 {
4539 	struct bge_softc *sc = ifp->if_softc;
4540 	uint16_t rx_prod, tx_cons;
4541 	uint32_t statusword;
4542 	int rx_npkts = 0;
4543 
4544 	BGE_LOCK(sc);
4545 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4546 		BGE_UNLOCK(sc);
4547 		return (rx_npkts);
4548 	}
4549 
4550 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4551 	    sc->bge_cdata.bge_status_map,
4552 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4553 	/* Fetch updates from the status block. */
4554 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4555 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4556 
4557 	statusword = sc->bge_ldata.bge_status_block->bge_status;
4558 	/* Clear the status so the next pass only sees the changes. */
4559 	sc->bge_ldata.bge_status_block->bge_status = 0;
4560 
4561 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4562 	    sc->bge_cdata.bge_status_map,
4563 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4564 
4565 	/* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4566 	if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4567 		sc->bge_link_evt++;
4568 
4569 	if (cmd == POLL_AND_CHECK_STATUS)
4570 		if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4571 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4572 		    sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4573 			bge_link_upd(sc);
4574 
4575 	sc->rxcycles = count;
4576 	rx_npkts = bge_rxeof(sc, rx_prod, 1);
4577 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4578 		BGE_UNLOCK(sc);
4579 		return (rx_npkts);
4580 	}
4581 	bge_txeof(sc, tx_cons);
4582 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4583 		bge_start_locked(ifp);
4584 
4585 	BGE_UNLOCK(sc);
4586 	return (rx_npkts);
4587 }
4588 #endif /* DEVICE_POLLING */
4589 
4590 static int
4591 bge_msi_intr(void *arg)
4592 {
4593 	struct bge_softc *sc;
4594 
4595 	sc = (struct bge_softc *)arg;
4596 	/*
4597 	 * This interrupt is not shared and controller already
4598 	 * disabled further interrupt.
4599 	 */
4600 	taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4601 	return (FILTER_HANDLED);
4602 }
4603 
4604 static void
4605 bge_intr_task(void *arg, int pending)
4606 {
4607 	struct bge_softc *sc;
4608 	struct ifnet *ifp;
4609 	uint32_t status, status_tag;
4610 	uint16_t rx_prod, tx_cons;
4611 
4612 	sc = (struct bge_softc *)arg;
4613 	ifp = sc->bge_ifp;
4614 
4615 	BGE_LOCK(sc);
4616 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4617 		BGE_UNLOCK(sc);
4618 		return;
4619 	}
4620 
4621 	/* Get updated status block. */
4622 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4623 	    sc->bge_cdata.bge_status_map,
4624 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4625 
4626 	/* Save producer/consumer indices. */
4627 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4628 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4629 	status = sc->bge_ldata.bge_status_block->bge_status;
4630 	status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4631 	/* Dirty the status flag. */
4632 	sc->bge_ldata.bge_status_block->bge_status = 0;
4633 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4634 	    sc->bge_cdata.bge_status_map,
4635 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4636 	if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4637 		status_tag = 0;
4638 
4639 	if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4640 		bge_link_upd(sc);
4641 
4642 	/* Let controller work. */
4643 	bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4644 
4645 	if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4646 	    sc->bge_rx_saved_considx != rx_prod) {
4647 		/* Check RX return ring producer/consumer. */
4648 		BGE_UNLOCK(sc);
4649 		bge_rxeof(sc, rx_prod, 0);
4650 		BGE_LOCK(sc);
4651 	}
4652 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4653 		/* Check TX ring producer/consumer. */
4654 		bge_txeof(sc, tx_cons);
4655 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4656 			bge_start_locked(ifp);
4657 	}
4658 	BGE_UNLOCK(sc);
4659 }
4660 
4661 static void
4662 bge_intr(void *xsc)
4663 {
4664 	struct bge_softc *sc;
4665 	struct ifnet *ifp;
4666 	uint32_t statusword;
4667 	uint16_t rx_prod, tx_cons;
4668 
4669 	sc = xsc;
4670 
4671 	BGE_LOCK(sc);
4672 
4673 	ifp = sc->bge_ifp;
4674 
4675 #ifdef DEVICE_POLLING
4676 	if (ifp->if_capenable & IFCAP_POLLING) {
4677 		BGE_UNLOCK(sc);
4678 		return;
4679 	}
4680 #endif
4681 
4682 	/*
4683 	 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4684 	 * disable interrupts by writing nonzero like we used to, since with
4685 	 * our current organization this just gives complications and
4686 	 * pessimizations for re-enabling interrupts.  We used to have races
4687 	 * instead of the necessary complications.  Disabling interrupts
4688 	 * would just reduce the chance of a status update while we are
4689 	 * running (by switching to the interrupt-mode coalescence
4690 	 * parameters), but this chance is already very low so it is more
4691 	 * efficient to get another interrupt than prevent it.
4692 	 *
4693 	 * We do the ack first to ensure another interrupt if there is a
4694 	 * status update after the ack.  We don't check for the status
4695 	 * changing later because it is more efficient to get another
4696 	 * interrupt than prevent it, not quite as above (not checking is
4697 	 * a smaller optimization than not toggling the interrupt enable,
4698 	 * since checking doesn't involve PCI accesses and toggling require
4699 	 * the status check).  So toggling would probably be a pessimization
4700 	 * even with MSI.  It would only be needed for using a task queue.
4701 	 */
4702 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4703 
4704 	/*
4705 	 * Do the mandatory PCI flush as well as get the link status.
4706 	 */
4707 	statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4708 
4709 	/* Make sure the descriptor ring indexes are coherent. */
4710 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4711 	    sc->bge_cdata.bge_status_map,
4712 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4713 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4714 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4715 	sc->bge_ldata.bge_status_block->bge_status = 0;
4716 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4717 	    sc->bge_cdata.bge_status_map,
4718 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4719 
4720 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4721 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4722 	    statusword || sc->bge_link_evt)
4723 		bge_link_upd(sc);
4724 
4725 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4726 		/* Check RX return ring producer/consumer. */
4727 		bge_rxeof(sc, rx_prod, 1);
4728 	}
4729 
4730 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4731 		/* Check TX ring producer/consumer. */
4732 		bge_txeof(sc, tx_cons);
4733 	}
4734 
4735 	if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4736 	    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4737 		bge_start_locked(ifp);
4738 
4739 	BGE_UNLOCK(sc);
4740 }
4741 
4742 static void
4743 bge_asf_driver_up(struct bge_softc *sc)
4744 {
4745 	if (sc->bge_asf_mode & ASF_STACKUP) {
4746 		/* Send ASF heartbeat aprox. every 2s */
4747 		if (sc->bge_asf_count)
4748 			sc->bge_asf_count --;
4749 		else {
4750 			sc->bge_asf_count = 2;
4751 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4752 			    BGE_FW_CMD_DRV_ALIVE);
4753 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4754 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4755 			    BGE_FW_HB_TIMEOUT_SEC);
4756 			CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4757 			    CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4758 			    BGE_RX_CPU_DRV_EVENT);
4759 		}
4760 	}
4761 }
4762 
4763 static void
4764 bge_tick(void *xsc)
4765 {
4766 	struct bge_softc *sc = xsc;
4767 	struct mii_data *mii = NULL;
4768 
4769 	BGE_LOCK_ASSERT(sc);
4770 
4771 	/* Synchronize with possible callout reset/stop. */
4772 	if (callout_pending(&sc->bge_stat_ch) ||
4773 	    !callout_active(&sc->bge_stat_ch))
4774 		return;
4775 
4776 	if (BGE_IS_5705_PLUS(sc))
4777 		bge_stats_update_regs(sc);
4778 	else
4779 		bge_stats_update(sc);
4780 
4781 	/* XXX Add APE heartbeat check here? */
4782 
4783 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4784 		mii = device_get_softc(sc->bge_miibus);
4785 		/*
4786 		 * Do not touch PHY if we have link up. This could break
4787 		 * IPMI/ASF mode or produce extra input errors
4788 		 * (extra errors was reported for bcm5701 & bcm5704).
4789 		 */
4790 		if (!sc->bge_link)
4791 			mii_tick(mii);
4792 	} else {
4793 		/*
4794 		 * Since in TBI mode auto-polling can't be used we should poll
4795 		 * link status manually. Here we register pending link event
4796 		 * and trigger interrupt.
4797 		 */
4798 #ifdef DEVICE_POLLING
4799 		/* In polling mode we poll link state in bge_poll(). */
4800 		if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4801 #endif
4802 		{
4803 		sc->bge_link_evt++;
4804 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4805 		    sc->bge_flags & BGE_FLAG_5788)
4806 			BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4807 		else
4808 			BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4809 		}
4810 	}
4811 
4812 	bge_asf_driver_up(sc);
4813 	bge_watchdog(sc);
4814 
4815 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4816 }
4817 
4818 static void
4819 bge_stats_update_regs(struct bge_softc *sc)
4820 {
4821 	struct ifnet *ifp;
4822 	struct bge_mac_stats *stats;
4823 	uint32_t val;
4824 
4825 	ifp = sc->bge_ifp;
4826 	stats = &sc->bge_mac_stats;
4827 
4828 	stats->ifHCOutOctets +=
4829 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4830 	stats->etherStatsCollisions +=
4831 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4832 	stats->outXonSent +=
4833 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4834 	stats->outXoffSent +=
4835 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4836 	stats->dot3StatsInternalMacTransmitErrors +=
4837 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4838 	stats->dot3StatsSingleCollisionFrames +=
4839 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4840 	stats->dot3StatsMultipleCollisionFrames +=
4841 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4842 	stats->dot3StatsDeferredTransmissions +=
4843 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4844 	stats->dot3StatsExcessiveCollisions +=
4845 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4846 	stats->dot3StatsLateCollisions +=
4847 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4848 	stats->ifHCOutUcastPkts +=
4849 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4850 	stats->ifHCOutMulticastPkts +=
4851 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4852 	stats->ifHCOutBroadcastPkts +=
4853 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4854 
4855 	stats->ifHCInOctets +=
4856 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4857 	stats->etherStatsFragments +=
4858 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4859 	stats->ifHCInUcastPkts +=
4860 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4861 	stats->ifHCInMulticastPkts +=
4862 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4863 	stats->ifHCInBroadcastPkts +=
4864 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4865 	stats->dot3StatsFCSErrors +=
4866 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4867 	stats->dot3StatsAlignmentErrors +=
4868 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4869 	stats->xonPauseFramesReceived +=
4870 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4871 	stats->xoffPauseFramesReceived +=
4872 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4873 	stats->macControlFramesReceived +=
4874 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4875 	stats->xoffStateEntered +=
4876 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4877 	stats->dot3StatsFramesTooLong +=
4878 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4879 	stats->etherStatsJabbers +=
4880 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4881 	stats->etherStatsUndersizePkts +=
4882 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4883 
4884 	stats->FramesDroppedDueToFilters +=
4885 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4886 	stats->DmaWriteQueueFull +=
4887 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4888 	stats->DmaWriteHighPriQueueFull +=
4889 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4890 	stats->NoMoreRxBDs +=
4891 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4892 	/*
4893 	 * XXX
4894 	 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4895 	 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4896 	 * includes number of unwanted multicast frames.  This comes
4897 	 * from silicon bug and known workaround to get rough(not
4898 	 * exact) counter is to enable interrupt on MBUF low water
4899 	 * attention.  This can be accomplished by setting
4900 	 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4901 	 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4902 	 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4903 	 * However that change would generate more interrupts and
4904 	 * there are still possibilities of losing multiple frames
4905 	 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4906 	 * Given that the workaround still would not get correct
4907 	 * counter I don't think it's worth to implement it.  So
4908 	 * ignore reading the counter on controllers that have the
4909 	 * silicon bug.
4910 	 */
4911 	if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4912 	    sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4913 	    sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4914 		stats->InputDiscards +=
4915 		    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4916 	stats->InputErrors +=
4917 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4918 	stats->RecvThresholdHit +=
4919 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4920 
4921 	ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4922 	ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4923 	    stats->InputErrors);
4924 
4925 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4926 		/*
4927 		 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4928 		 * frames, it's safe to disable workaround for DMA engine's
4929 		 * miscalculation of TXMBUF space.
4930 		 */
4931 		if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4932 		    stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4933 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4934 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4935 				val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4936 			else
4937 				val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4938 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4939 			sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4940 		}
4941 	}
4942 }
4943 
4944 static void
4945 bge_stats_clear_regs(struct bge_softc *sc)
4946 {
4947 
4948 	CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4949 	CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4950 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4951 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4952 	CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4953 	CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4954 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4955 	CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4956 	CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4957 	CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4958 	CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4959 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4960 	CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4961 
4962 	CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4963 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4964 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4965 	CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4966 	CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4967 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4968 	CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4969 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4970 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4971 	CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4972 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4973 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4974 	CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4975 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4976 
4977 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4978 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4979 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4980 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4981 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4982 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4983 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4984 }
4985 
4986 static void
4987 bge_stats_update(struct bge_softc *sc)
4988 {
4989 	struct ifnet *ifp;
4990 	bus_size_t stats;
4991 	uint32_t cnt;	/* current register value */
4992 
4993 	ifp = sc->bge_ifp;
4994 
4995 	stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4996 
4997 #define	READ_STAT(sc, stats, stat) \
4998 	CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4999 
5000 	cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5001 	ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
5002 	sc->bge_tx_collisions = cnt;
5003 
5004 	cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5005 	ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
5006 	sc->bge_rx_nobds = cnt;
5007 	cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5008 	ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
5009 	sc->bge_rx_inerrs = cnt;
5010 	cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5011 	ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
5012 	sc->bge_rx_discards = cnt;
5013 
5014 	cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5015 	ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
5016 	sc->bge_tx_discards = cnt;
5017 
5018 #undef	READ_STAT
5019 }
5020 
5021 /*
5022  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5023  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5024  * but when such padded frames employ the bge IP/TCP checksum offload,
5025  * the hardware checksum assist gives incorrect results (possibly
5026  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5027  * If we pad such runts with zeros, the onboard checksum comes out correct.
5028  */
5029 static __inline int
5030 bge_cksum_pad(struct mbuf *m)
5031 {
5032 	int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5033 	struct mbuf *last;
5034 
5035 	/* If there's only the packet-header and we can pad there, use it. */
5036 	if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5037 	    M_TRAILINGSPACE(m) >= padlen) {
5038 		last = m;
5039 	} else {
5040 		/*
5041 		 * Walk packet chain to find last mbuf. We will either
5042 		 * pad there, or append a new mbuf and pad it.
5043 		 */
5044 		for (last = m; last->m_next != NULL; last = last->m_next);
5045 		if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5046 			/* Allocate new empty mbuf, pad it. Compact later. */
5047 			struct mbuf *n;
5048 
5049 			MGET(n, M_NOWAIT, MT_DATA);
5050 			if (n == NULL)
5051 				return (ENOBUFS);
5052 			n->m_len = 0;
5053 			last->m_next = n;
5054 			last = n;
5055 		}
5056 	}
5057 
5058 	/* Now zero the pad area, to avoid the bge cksum-assist bug. */
5059 	memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5060 	last->m_len += padlen;
5061 	m->m_pkthdr.len += padlen;
5062 
5063 	return (0);
5064 }
5065 
5066 static struct mbuf *
5067 bge_check_short_dma(struct mbuf *m)
5068 {
5069 	struct mbuf *n;
5070 	int found;
5071 
5072 	/*
5073 	 * If device receive two back-to-back send BDs with less than
5074 	 * or equal to 8 total bytes then the device may hang.  The two
5075 	 * back-to-back send BDs must in the same frame for this failure
5076 	 * to occur.  Scan mbuf chains and see whether two back-to-back
5077 	 * send BDs are there. If this is the case, allocate new mbuf
5078 	 * and copy the frame to workaround the silicon bug.
5079 	 */
5080 	for (n = m, found = 0; n != NULL; n = n->m_next) {
5081 		if (n->m_len < 8) {
5082 			found++;
5083 			if (found > 1)
5084 				break;
5085 			continue;
5086 		}
5087 		found = 0;
5088 	}
5089 
5090 	if (found > 1) {
5091 		n = m_defrag(m, M_NOWAIT);
5092 		if (n == NULL)
5093 			m_freem(m);
5094 	} else
5095 		n = m;
5096 	return (n);
5097 }
5098 
5099 static struct mbuf *
5100 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5101     uint16_t *flags)
5102 {
5103 	struct ip *ip;
5104 	struct tcphdr *tcp;
5105 	struct mbuf *n;
5106 	uint16_t hlen;
5107 	uint32_t poff;
5108 
5109 	if (M_WRITABLE(m) == 0) {
5110 		/* Get a writable copy. */
5111 		n = m_dup(m, M_NOWAIT);
5112 		m_freem(m);
5113 		if (n == NULL)
5114 			return (NULL);
5115 		m = n;
5116 	}
5117 	m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5118 	if (m == NULL)
5119 		return (NULL);
5120 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5121 	poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5122 	m = m_pullup(m, poff + sizeof(struct tcphdr));
5123 	if (m == NULL)
5124 		return (NULL);
5125 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5126 	m = m_pullup(m, poff + (tcp->th_off << 2));
5127 	if (m == NULL)
5128 		return (NULL);
5129 	/*
5130 	 * It seems controller doesn't modify IP length and TCP pseudo
5131 	 * checksum. These checksum computed by upper stack should be 0.
5132 	 */
5133 	*mss = m->m_pkthdr.tso_segsz;
5134 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5135 	ip->ip_sum = 0;
5136 	ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5137 	/* Clear pseudo checksum computed by TCP stack. */
5138 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5139 	tcp->th_sum = 0;
5140 	/*
5141 	 * Broadcom controllers uses different descriptor format for
5142 	 * TSO depending on ASIC revision. Due to TSO-capable firmware
5143 	 * license issue and lower performance of firmware based TSO
5144 	 * we only support hardware based TSO.
5145 	 */
5146 	/* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5147 	hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5148 	if (sc->bge_flags & BGE_FLAG_TSO3) {
5149 		/*
5150 		 * For BCM5717 and newer controllers, hardware based TSO
5151 		 * uses the 14 lower bits of the bge_mss field to store the
5152 		 * MSS and the upper 2 bits to store the lowest 2 bits of
5153 		 * the IP/TCP header length.  The upper 6 bits of the header
5154 		 * length are stored in the bge_flags[14:10,4] field.  Jumbo
5155 		 * frames are supported.
5156 		 */
5157 		*mss |= ((hlen & 0x3) << 14);
5158 		*flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5159 	} else {
5160 		/*
5161 		 * For BCM5755 and newer controllers, hardware based TSO uses
5162 		 * the lower 11	bits to store the MSS and the upper 5 bits to
5163 		 * store the IP/TCP header length. Jumbo frames are not
5164 		 * supported.
5165 		 */
5166 		*mss |= (hlen << 11);
5167 	}
5168 	return (m);
5169 }
5170 
5171 /*
5172  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5173  * pointers to descriptors.
5174  */
5175 static int
5176 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5177 {
5178 	bus_dma_segment_t	segs[BGE_NSEG_NEW];
5179 	bus_dmamap_t		map;
5180 	struct bge_tx_bd	*d;
5181 	struct mbuf		*m = *m_head;
5182 	uint32_t		idx = *txidx;
5183 	uint16_t		csum_flags, mss, vlan_tag;
5184 	int			nsegs, i, error;
5185 
5186 	csum_flags = 0;
5187 	mss = 0;
5188 	vlan_tag = 0;
5189 	if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5190 	    m->m_next != NULL) {
5191 		*m_head = bge_check_short_dma(m);
5192 		if (*m_head == NULL)
5193 			return (ENOBUFS);
5194 		m = *m_head;
5195 	}
5196 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5197 		*m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5198 		if (*m_head == NULL)
5199 			return (ENOBUFS);
5200 		csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5201 		    BGE_TXBDFLAG_CPU_POST_DMA;
5202 	} else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5203 		if (m->m_pkthdr.csum_flags & CSUM_IP)
5204 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5205 		if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5206 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5207 			if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5208 			    (error = bge_cksum_pad(m)) != 0) {
5209 				m_freem(m);
5210 				*m_head = NULL;
5211 				return (error);
5212 			}
5213 		}
5214 	}
5215 
5216 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5217 		if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5218 		    m->m_pkthdr.len > ETHER_MAX_LEN)
5219 			csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5220 		if (sc->bge_forced_collapse > 0 &&
5221 		    (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5222 			/*
5223 			 * Forcedly collapse mbuf chains to overcome hardware
5224 			 * limitation which only support a single outstanding
5225 			 * DMA read operation.
5226 			 */
5227 			if (sc->bge_forced_collapse == 1)
5228 				m = m_defrag(m, M_NOWAIT);
5229 			else
5230 				m = m_collapse(m, M_NOWAIT,
5231 				    sc->bge_forced_collapse);
5232 			if (m == NULL)
5233 				m = *m_head;
5234 			*m_head = m;
5235 		}
5236 	}
5237 
5238 	map = sc->bge_cdata.bge_tx_dmamap[idx];
5239 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5240 	    &nsegs, BUS_DMA_NOWAIT);
5241 	if (error == EFBIG) {
5242 		m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5243 		if (m == NULL) {
5244 			m_freem(*m_head);
5245 			*m_head = NULL;
5246 			return (ENOBUFS);
5247 		}
5248 		*m_head = m;
5249 		error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5250 		    m, segs, &nsegs, BUS_DMA_NOWAIT);
5251 		if (error) {
5252 			m_freem(m);
5253 			*m_head = NULL;
5254 			return (error);
5255 		}
5256 	} else if (error != 0)
5257 		return (error);
5258 
5259 	/* Check if we have enough free send BDs. */
5260 	if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5261 		bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5262 		return (ENOBUFS);
5263 	}
5264 
5265 	bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5266 
5267 	if (m->m_flags & M_VLANTAG) {
5268 		csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5269 		vlan_tag = m->m_pkthdr.ether_vtag;
5270 	}
5271 
5272 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5273 	    (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5274 		/*
5275 		 * 5725 family of devices corrupts TSO packets when TSO DMA
5276 		 * buffers cross into regions which are within MSS bytes of
5277 		 * a 4GB boundary.  If we encounter the condition, drop the
5278 		 * packet.
5279 		 */
5280 		for (i = 0; ; i++) {
5281 			d = &sc->bge_ldata.bge_tx_ring[idx];
5282 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5283 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5284 			d->bge_len = segs[i].ds_len;
5285 			if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5286 			    d->bge_addr.bge_addr_lo)
5287 				break;
5288 			d->bge_flags = csum_flags;
5289 			d->bge_vlan_tag = vlan_tag;
5290 			d->bge_mss = mss;
5291 			if (i == nsegs - 1)
5292 				break;
5293 			BGE_INC(idx, BGE_TX_RING_CNT);
5294 		}
5295 		if (i != nsegs - 1) {
5296 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5297 			    BUS_DMASYNC_POSTWRITE);
5298 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5299 			m_freem(*m_head);
5300 			*m_head = NULL;
5301 			return (EIO);
5302 		}
5303 	} else {
5304 		for (i = 0; ; i++) {
5305 			d = &sc->bge_ldata.bge_tx_ring[idx];
5306 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5307 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5308 			d->bge_len = segs[i].ds_len;
5309 			d->bge_flags = csum_flags;
5310 			d->bge_vlan_tag = vlan_tag;
5311 			d->bge_mss = mss;
5312 			if (i == nsegs - 1)
5313 				break;
5314 			BGE_INC(idx, BGE_TX_RING_CNT);
5315 		}
5316 	}
5317 
5318 	/* Mark the last segment as end of packet... */
5319 	d->bge_flags |= BGE_TXBDFLAG_END;
5320 
5321 	/*
5322 	 * Insure that the map for this transmission
5323 	 * is placed at the array index of the last descriptor
5324 	 * in this chain.
5325 	 */
5326 	sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5327 	sc->bge_cdata.bge_tx_dmamap[idx] = map;
5328 	sc->bge_cdata.bge_tx_chain[idx] = m;
5329 	sc->bge_txcnt += nsegs;
5330 
5331 	BGE_INC(idx, BGE_TX_RING_CNT);
5332 	*txidx = idx;
5333 
5334 	return (0);
5335 }
5336 
5337 /*
5338  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5339  * to the mbuf data regions directly in the transmit descriptors.
5340  */
5341 static void
5342 bge_start_locked(struct ifnet *ifp)
5343 {
5344 	struct bge_softc *sc;
5345 	struct mbuf *m_head;
5346 	uint32_t prodidx;
5347 	int count;
5348 
5349 	sc = ifp->if_softc;
5350 	BGE_LOCK_ASSERT(sc);
5351 
5352 	if (!sc->bge_link ||
5353 	    (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5354 	    IFF_DRV_RUNNING)
5355 		return;
5356 
5357 	prodidx = sc->bge_tx_prodidx;
5358 
5359 	for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5360 		if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5361 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5362 			break;
5363 		}
5364 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5365 		if (m_head == NULL)
5366 			break;
5367 
5368 		/*
5369 		 * Pack the data into the transmit ring. If we
5370 		 * don't have room, set the OACTIVE flag and wait
5371 		 * for the NIC to drain the ring.
5372 		 */
5373 		if (bge_encap(sc, &m_head, &prodidx)) {
5374 			if (m_head == NULL)
5375 				break;
5376 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5377 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5378 			break;
5379 		}
5380 		++count;
5381 
5382 		/*
5383 		 * If there's a BPF listener, bounce a copy of this frame
5384 		 * to him.
5385 		 */
5386 #ifdef ETHER_BPF_MTAP
5387 		ETHER_BPF_MTAP(ifp, m_head);
5388 #else
5389 		BPF_MTAP(ifp, m_head);
5390 #endif
5391 	}
5392 
5393 	if (count > 0) {
5394 		bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5395 		    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5396 		/* Transmit. */
5397 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5398 		/* 5700 b2 errata */
5399 		if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5400 			bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5401 
5402 		sc->bge_tx_prodidx = prodidx;
5403 
5404 		/*
5405 		 * Set a timeout in case the chip goes out to lunch.
5406 		 */
5407 		sc->bge_timer = BGE_TX_TIMEOUT;
5408 	}
5409 }
5410 
5411 /*
5412  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5413  * to the mbuf data regions directly in the transmit descriptors.
5414  */
5415 static void
5416 bge_start(struct ifnet *ifp)
5417 {
5418 	struct bge_softc *sc;
5419 
5420 	sc = ifp->if_softc;
5421 	BGE_LOCK(sc);
5422 	bge_start_locked(ifp);
5423 	BGE_UNLOCK(sc);
5424 }
5425 
5426 static void
5427 bge_init_locked(struct bge_softc *sc)
5428 {
5429 	struct ifnet *ifp;
5430 	uint16_t *m;
5431 	uint32_t mode;
5432 
5433 	BGE_LOCK_ASSERT(sc);
5434 
5435 	ifp = sc->bge_ifp;
5436 
5437 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5438 		return;
5439 
5440 	/* Cancel pending I/O and flush buffers. */
5441 	bge_stop(sc);
5442 
5443 	bge_stop_fw(sc);
5444 	bge_sig_pre_reset(sc, BGE_RESET_START);
5445 	bge_reset(sc);
5446 	bge_sig_legacy(sc, BGE_RESET_START);
5447 	bge_sig_post_reset(sc, BGE_RESET_START);
5448 
5449 	bge_chipinit(sc);
5450 
5451 	/*
5452 	 * Init the various state machines, ring
5453 	 * control blocks and firmware.
5454 	 */
5455 	if (bge_blockinit(sc)) {
5456 		device_printf(sc->bge_dev, "initialization failure\n");
5457 		return;
5458 	}
5459 
5460 	ifp = sc->bge_ifp;
5461 
5462 	/* Specify MTU. */
5463 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5464 	    ETHER_HDR_LEN + ETHER_CRC_LEN +
5465 	    (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5466 
5467 	/* Load our MAC address. */
5468 	m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5469 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5470 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5471 
5472 	/* Program promiscuous mode. */
5473 	bge_setpromisc(sc);
5474 
5475 	/* Program multicast filter. */
5476 	bge_setmulti(sc);
5477 
5478 	/* Program VLAN tag stripping. */
5479 	bge_setvlan(sc);
5480 
5481 	/* Override UDP checksum offloading. */
5482 	if (sc->bge_forced_udpcsum == 0)
5483 		sc->bge_csum_features &= ~CSUM_UDP;
5484 	else
5485 		sc->bge_csum_features |= CSUM_UDP;
5486 	if (ifp->if_capabilities & IFCAP_TXCSUM &&
5487 	    ifp->if_capenable & IFCAP_TXCSUM) {
5488 		ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5489 		ifp->if_hwassist |= sc->bge_csum_features;
5490 	}
5491 
5492 	/* Init RX ring. */
5493 	if (bge_init_rx_ring_std(sc) != 0) {
5494 		device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5495 		bge_stop(sc);
5496 		return;
5497 	}
5498 
5499 	/*
5500 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5501 	 * memory to insure that the chip has in fact read the first
5502 	 * entry of the ring.
5503 	 */
5504 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5505 		uint32_t		v, i;
5506 		for (i = 0; i < 10; i++) {
5507 			DELAY(20);
5508 			v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5509 			if (v == (MCLBYTES - ETHER_ALIGN))
5510 				break;
5511 		}
5512 		if (i == 10)
5513 			device_printf (sc->bge_dev,
5514 			    "5705 A0 chip failed to load RX ring\n");
5515 	}
5516 
5517 	/* Init jumbo RX ring. */
5518 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
5519 	    ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5520 	    (MCLBYTES - ETHER_ALIGN)) {
5521 		if (bge_init_rx_ring_jumbo(sc) != 0) {
5522 			device_printf(sc->bge_dev,
5523 			    "no memory for jumbo Rx buffers.\n");
5524 			bge_stop(sc);
5525 			return;
5526 		}
5527 	}
5528 
5529 	/* Init our RX return ring index. */
5530 	sc->bge_rx_saved_considx = 0;
5531 
5532 	/* Init our RX/TX stat counters. */
5533 	sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5534 
5535 	/* Init TX ring. */
5536 	bge_init_tx_ring(sc);
5537 
5538 	/* Enable TX MAC state machine lockup fix. */
5539 	mode = CSR_READ_4(sc, BGE_TX_MODE);
5540 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5541 		mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5542 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5543 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5544 		mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5545 		mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5546 		    (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5547 	}
5548 	/* Turn on transmitter. */
5549 	CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5550 	DELAY(100);
5551 
5552 	/* Turn on receiver. */
5553 	mode = CSR_READ_4(sc, BGE_RX_MODE);
5554 	if (BGE_IS_5755_PLUS(sc))
5555 		mode |= BGE_RXMODE_IPV6_ENABLE;
5556 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5557 		mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5558 	CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5559 	DELAY(10);
5560 
5561 	/*
5562 	 * Set the number of good frames to receive after RX MBUF
5563 	 * Low Watermark has been reached. After the RX MAC receives
5564 	 * this number of frames, it will drop subsequent incoming
5565 	 * frames until the MBUF High Watermark is reached.
5566 	 */
5567 	if (BGE_IS_57765_PLUS(sc))
5568 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5569 	else
5570 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5571 
5572 	/* Clear MAC statistics. */
5573 	if (BGE_IS_5705_PLUS(sc))
5574 		bge_stats_clear_regs(sc);
5575 
5576 	/* Tell firmware we're alive. */
5577 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5578 
5579 #ifdef DEVICE_POLLING
5580 	/* Disable interrupts if we are polling. */
5581 	if (ifp->if_capenable & IFCAP_POLLING) {
5582 		BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5583 		    BGE_PCIMISCCTL_MASK_PCI_INTR);
5584 		bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5585 	} else
5586 #endif
5587 
5588 	/* Enable host interrupts. */
5589 	{
5590 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5591 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5592 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5593 	}
5594 
5595 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
5596 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5597 
5598 	bge_ifmedia_upd_locked(ifp);
5599 
5600 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5601 }
5602 
5603 static void
5604 bge_init(void *xsc)
5605 {
5606 	struct bge_softc *sc = xsc;
5607 
5608 	BGE_LOCK(sc);
5609 	bge_init_locked(sc);
5610 	BGE_UNLOCK(sc);
5611 }
5612 
5613 /*
5614  * Set media options.
5615  */
5616 static int
5617 bge_ifmedia_upd(struct ifnet *ifp)
5618 {
5619 	struct bge_softc *sc = ifp->if_softc;
5620 	int res;
5621 
5622 	BGE_LOCK(sc);
5623 	res = bge_ifmedia_upd_locked(ifp);
5624 	BGE_UNLOCK(sc);
5625 
5626 	return (res);
5627 }
5628 
5629 static int
5630 bge_ifmedia_upd_locked(struct ifnet *ifp)
5631 {
5632 	struct bge_softc *sc = ifp->if_softc;
5633 	struct mii_data *mii;
5634 	struct mii_softc *miisc;
5635 	struct ifmedia *ifm;
5636 
5637 	BGE_LOCK_ASSERT(sc);
5638 
5639 	ifm = &sc->bge_ifmedia;
5640 
5641 	/* If this is a 1000baseX NIC, enable the TBI port. */
5642 	if (sc->bge_flags & BGE_FLAG_TBI) {
5643 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5644 			return (EINVAL);
5645 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
5646 		case IFM_AUTO:
5647 			/*
5648 			 * The BCM5704 ASIC appears to have a special
5649 			 * mechanism for programming the autoneg
5650 			 * advertisement registers in TBI mode.
5651 			 */
5652 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5653 				uint32_t sgdig;
5654 				sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5655 				if (sgdig & BGE_SGDIGSTS_DONE) {
5656 					CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5657 					sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5658 					sgdig |= BGE_SGDIGCFG_AUTO |
5659 					    BGE_SGDIGCFG_PAUSE_CAP |
5660 					    BGE_SGDIGCFG_ASYM_PAUSE;
5661 					CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5662 					    sgdig | BGE_SGDIGCFG_SEND);
5663 					DELAY(5);
5664 					CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5665 				}
5666 			}
5667 			break;
5668 		case IFM_1000_SX:
5669 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5670 				BGE_CLRBIT(sc, BGE_MAC_MODE,
5671 				    BGE_MACMODE_HALF_DUPLEX);
5672 			} else {
5673 				BGE_SETBIT(sc, BGE_MAC_MODE,
5674 				    BGE_MACMODE_HALF_DUPLEX);
5675 			}
5676 			DELAY(40);
5677 			break;
5678 		default:
5679 			return (EINVAL);
5680 		}
5681 		return (0);
5682 	}
5683 
5684 	sc->bge_link_evt++;
5685 	mii = device_get_softc(sc->bge_miibus);
5686 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5687 		PHY_RESET(miisc);
5688 	mii_mediachg(mii);
5689 
5690 	/*
5691 	 * Force an interrupt so that we will call bge_link_upd
5692 	 * if needed and clear any pending link state attention.
5693 	 * Without this we are not getting any further interrupts
5694 	 * for link state changes and thus will not UP the link and
5695 	 * not be able to send in bge_start_locked. The only
5696 	 * way to get things working was to receive a packet and
5697 	 * get an RX intr.
5698 	 * bge_tick should help for fiber cards and we might not
5699 	 * need to do this here if BGE_FLAG_TBI is set but as
5700 	 * we poll for fiber anyway it should not harm.
5701 	 */
5702 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5703 	    sc->bge_flags & BGE_FLAG_5788)
5704 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5705 	else
5706 		BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5707 
5708 	return (0);
5709 }
5710 
5711 /*
5712  * Report current media status.
5713  */
5714 static void
5715 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5716 {
5717 	struct bge_softc *sc = ifp->if_softc;
5718 	struct mii_data *mii;
5719 
5720 	BGE_LOCK(sc);
5721 
5722 	if ((ifp->if_flags & IFF_UP) == 0) {
5723 		BGE_UNLOCK(sc);
5724 		return;
5725 	}
5726 	if (sc->bge_flags & BGE_FLAG_TBI) {
5727 		ifmr->ifm_status = IFM_AVALID;
5728 		ifmr->ifm_active = IFM_ETHER;
5729 		if (CSR_READ_4(sc, BGE_MAC_STS) &
5730 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
5731 			ifmr->ifm_status |= IFM_ACTIVE;
5732 		else {
5733 			ifmr->ifm_active |= IFM_NONE;
5734 			BGE_UNLOCK(sc);
5735 			return;
5736 		}
5737 		ifmr->ifm_active |= IFM_1000_SX;
5738 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5739 			ifmr->ifm_active |= IFM_HDX;
5740 		else
5741 			ifmr->ifm_active |= IFM_FDX;
5742 		BGE_UNLOCK(sc);
5743 		return;
5744 	}
5745 
5746 	mii = device_get_softc(sc->bge_miibus);
5747 	mii_pollstat(mii);
5748 	ifmr->ifm_active = mii->mii_media_active;
5749 	ifmr->ifm_status = mii->mii_media_status;
5750 
5751 	BGE_UNLOCK(sc);
5752 }
5753 
5754 static int
5755 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5756 {
5757 	struct bge_softc *sc = ifp->if_softc;
5758 	struct ifreq *ifr = (struct ifreq *) data;
5759 	struct mii_data *mii;
5760 	int flags, mask, error = 0;
5761 
5762 	switch (command) {
5763 	case SIOCSIFMTU:
5764 		if (BGE_IS_JUMBO_CAPABLE(sc) ||
5765 		    (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5766 			if (ifr->ifr_mtu < ETHERMIN ||
5767 			    ifr->ifr_mtu > BGE_JUMBO_MTU) {
5768 				error = EINVAL;
5769 				break;
5770 			}
5771 		} else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5772 			error = EINVAL;
5773 			break;
5774 		}
5775 		BGE_LOCK(sc);
5776 		if (ifp->if_mtu != ifr->ifr_mtu) {
5777 			ifp->if_mtu = ifr->ifr_mtu;
5778 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5779 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5780 				bge_init_locked(sc);
5781 			}
5782 		}
5783 		BGE_UNLOCK(sc);
5784 		break;
5785 	case SIOCSIFFLAGS:
5786 		BGE_LOCK(sc);
5787 		if (ifp->if_flags & IFF_UP) {
5788 			/*
5789 			 * If only the state of the PROMISC flag changed,
5790 			 * then just use the 'set promisc mode' command
5791 			 * instead of reinitializing the entire NIC. Doing
5792 			 * a full re-init means reloading the firmware and
5793 			 * waiting for it to start up, which may take a
5794 			 * second or two.  Similarly for ALLMULTI.
5795 			 */
5796 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5797 				flags = ifp->if_flags ^ sc->bge_if_flags;
5798 				if (flags & IFF_PROMISC)
5799 					bge_setpromisc(sc);
5800 				if (flags & IFF_ALLMULTI)
5801 					bge_setmulti(sc);
5802 			} else
5803 				bge_init_locked(sc);
5804 		} else {
5805 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5806 				bge_stop(sc);
5807 			}
5808 		}
5809 		sc->bge_if_flags = ifp->if_flags;
5810 		BGE_UNLOCK(sc);
5811 		error = 0;
5812 		break;
5813 	case SIOCADDMULTI:
5814 	case SIOCDELMULTI:
5815 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5816 			BGE_LOCK(sc);
5817 			bge_setmulti(sc);
5818 			BGE_UNLOCK(sc);
5819 			error = 0;
5820 		}
5821 		break;
5822 	case SIOCSIFMEDIA:
5823 	case SIOCGIFMEDIA:
5824 		if (sc->bge_flags & BGE_FLAG_TBI) {
5825 			error = ifmedia_ioctl(ifp, ifr,
5826 			    &sc->bge_ifmedia, command);
5827 		} else {
5828 			mii = device_get_softc(sc->bge_miibus);
5829 			error = ifmedia_ioctl(ifp, ifr,
5830 			    &mii->mii_media, command);
5831 		}
5832 		break;
5833 	case SIOCSIFCAP:
5834 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5835 #ifdef DEVICE_POLLING
5836 		if (mask & IFCAP_POLLING) {
5837 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
5838 				error = ether_poll_register(bge_poll, ifp);
5839 				if (error)
5840 					return (error);
5841 				BGE_LOCK(sc);
5842 				BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5843 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5844 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5845 				ifp->if_capenable |= IFCAP_POLLING;
5846 				BGE_UNLOCK(sc);
5847 			} else {
5848 				error = ether_poll_deregister(ifp);
5849 				/* Enable interrupt even in error case */
5850 				BGE_LOCK(sc);
5851 				BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5852 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5853 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5854 				ifp->if_capenable &= ~IFCAP_POLLING;
5855 				BGE_UNLOCK(sc);
5856 			}
5857 		}
5858 #endif
5859 		if ((mask & IFCAP_TXCSUM) != 0 &&
5860 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5861 			ifp->if_capenable ^= IFCAP_TXCSUM;
5862 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5863 				ifp->if_hwassist |= sc->bge_csum_features;
5864 			else
5865 				ifp->if_hwassist &= ~sc->bge_csum_features;
5866 		}
5867 
5868 		if ((mask & IFCAP_RXCSUM) != 0 &&
5869 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5870 			ifp->if_capenable ^= IFCAP_RXCSUM;
5871 
5872 		if ((mask & IFCAP_TSO4) != 0 &&
5873 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5874 			ifp->if_capenable ^= IFCAP_TSO4;
5875 			if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5876 				ifp->if_hwassist |= CSUM_TSO;
5877 			else
5878 				ifp->if_hwassist &= ~CSUM_TSO;
5879 		}
5880 
5881 		if (mask & IFCAP_VLAN_MTU) {
5882 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
5883 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5884 			bge_init(sc);
5885 		}
5886 
5887 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5888 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5889 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5890 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5891 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5892 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5893 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5894 				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5895 			BGE_LOCK(sc);
5896 			bge_setvlan(sc);
5897 			BGE_UNLOCK(sc);
5898 		}
5899 #ifdef VLAN_CAPABILITIES
5900 		VLAN_CAPABILITIES(ifp);
5901 #endif
5902 		break;
5903 	default:
5904 		error = ether_ioctl(ifp, command, data);
5905 		break;
5906 	}
5907 
5908 	return (error);
5909 }
5910 
5911 static void
5912 bge_watchdog(struct bge_softc *sc)
5913 {
5914 	struct ifnet *ifp;
5915 	uint32_t status;
5916 
5917 	BGE_LOCK_ASSERT(sc);
5918 
5919 	if (sc->bge_timer == 0 || --sc->bge_timer)
5920 		return;
5921 
5922 	/* If pause frames are active then don't reset the hardware. */
5923 	if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5924 		status = CSR_READ_4(sc, BGE_RX_STS);
5925 		if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5926 			/*
5927 			 * If link partner has us in XOFF state then wait for
5928 			 * the condition to clear.
5929 			 */
5930 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5931 			sc->bge_timer = BGE_TX_TIMEOUT;
5932 			return;
5933 		} else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5934 		    (status & BGE_RXSTAT_RCVD_XON) != 0) {
5935 			/*
5936 			 * If link partner has us in XOFF state then wait for
5937 			 * the condition to clear.
5938 			 */
5939 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5940 			sc->bge_timer = BGE_TX_TIMEOUT;
5941 			return;
5942 		}
5943 		/*
5944 		 * Any other condition is unexpected and the controller
5945 		 * should be reset.
5946 		 */
5947 	}
5948 
5949 	ifp = sc->bge_ifp;
5950 
5951 	if_printf(ifp, "watchdog timeout -- resetting\n");
5952 
5953 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5954 	bge_init_locked(sc);
5955 
5956 	ifp->if_oerrors++;
5957 }
5958 
5959 static void
5960 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5961 {
5962 	int i;
5963 
5964 	BGE_CLRBIT(sc, reg, bit);
5965 
5966 	for (i = 0; i < BGE_TIMEOUT; i++) {
5967 		if ((CSR_READ_4(sc, reg) & bit) == 0)
5968 			return;
5969 		DELAY(100);
5970         }
5971 }
5972 
5973 /*
5974  * Stop the adapter and free any mbufs allocated to the
5975  * RX and TX lists.
5976  */
5977 static void
5978 bge_stop(struct bge_softc *sc)
5979 {
5980 	struct ifnet *ifp;
5981 
5982 	BGE_LOCK_ASSERT(sc);
5983 
5984 	ifp = sc->bge_ifp;
5985 
5986 	callout_stop(&sc->bge_stat_ch);
5987 
5988 	/* Disable host interrupts. */
5989 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5990 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5991 
5992 	/*
5993 	 * Tell firmware we're shutting down.
5994 	 */
5995 	bge_stop_fw(sc);
5996 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5997 
5998 	/*
5999 	 * Disable all of the receiver blocks.
6000 	 */
6001 	bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6002 	bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6003 	bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6004 	if (BGE_IS_5700_FAMILY(sc))
6005 		bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6006 	bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6007 	bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6008 	bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6009 
6010 	/*
6011 	 * Disable all of the transmit blocks.
6012 	 */
6013 	bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6014 	bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6015 	bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6016 	bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6017 	bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6018 	if (BGE_IS_5700_FAMILY(sc))
6019 		bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6020 	bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6021 
6022 	/*
6023 	 * Shut down all of the memory managers and related
6024 	 * state machines.
6025 	 */
6026 	bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6027 	bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6028 	if (BGE_IS_5700_FAMILY(sc))
6029 		bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6030 
6031 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6032 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6033 	if (!(BGE_IS_5705_PLUS(sc))) {
6034 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6035 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6036 	}
6037 	/* Update MAC statistics. */
6038 	if (BGE_IS_5705_PLUS(sc))
6039 		bge_stats_update_regs(sc);
6040 
6041 	bge_reset(sc);
6042 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6043 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6044 
6045 	/*
6046 	 * Keep the ASF firmware running if up.
6047 	 */
6048 	if (sc->bge_asf_mode & ASF_STACKUP)
6049 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6050 	else
6051 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6052 
6053 	/* Free the RX lists. */
6054 	bge_free_rx_ring_std(sc);
6055 
6056 	/* Free jumbo RX list. */
6057 	if (BGE_IS_JUMBO_CAPABLE(sc))
6058 		bge_free_rx_ring_jumbo(sc);
6059 
6060 	/* Free TX buffers. */
6061 	bge_free_tx_ring(sc);
6062 
6063 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6064 
6065 	/* Clear MAC's link state (PHY may still have link UP). */
6066 	if (bootverbose && sc->bge_link)
6067 		if_printf(sc->bge_ifp, "link DOWN\n");
6068 	sc->bge_link = 0;
6069 
6070 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6071 }
6072 
6073 /*
6074  * Stop all chip I/O so that the kernel's probe routines don't
6075  * get confused by errant DMAs when rebooting.
6076  */
6077 static int
6078 bge_shutdown(device_t dev)
6079 {
6080 	struct bge_softc *sc;
6081 
6082 	sc = device_get_softc(dev);
6083 	BGE_LOCK(sc);
6084 	bge_stop(sc);
6085 	BGE_UNLOCK(sc);
6086 
6087 	return (0);
6088 }
6089 
6090 static int
6091 bge_suspend(device_t dev)
6092 {
6093 	struct bge_softc *sc;
6094 
6095 	sc = device_get_softc(dev);
6096 	BGE_LOCK(sc);
6097 	bge_stop(sc);
6098 	BGE_UNLOCK(sc);
6099 
6100 	return (0);
6101 }
6102 
6103 static int
6104 bge_resume(device_t dev)
6105 {
6106 	struct bge_softc *sc;
6107 	struct ifnet *ifp;
6108 
6109 	sc = device_get_softc(dev);
6110 	BGE_LOCK(sc);
6111 	ifp = sc->bge_ifp;
6112 	if (ifp->if_flags & IFF_UP) {
6113 		bge_init_locked(sc);
6114 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6115 			bge_start_locked(ifp);
6116 	}
6117 	BGE_UNLOCK(sc);
6118 
6119 	return (0);
6120 }
6121 
6122 static void
6123 bge_link_upd(struct bge_softc *sc)
6124 {
6125 	struct mii_data *mii;
6126 	uint32_t link, status;
6127 
6128 	BGE_LOCK_ASSERT(sc);
6129 
6130 	/* Clear 'pending link event' flag. */
6131 	sc->bge_link_evt = 0;
6132 
6133 	/*
6134 	 * Process link state changes.
6135 	 * Grrr. The link status word in the status block does
6136 	 * not work correctly on the BCM5700 rev AX and BX chips,
6137 	 * according to all available information. Hence, we have
6138 	 * to enable MII interrupts in order to properly obtain
6139 	 * async link changes. Unfortunately, this also means that
6140 	 * we have to read the MAC status register to detect link
6141 	 * changes, thereby adding an additional register access to
6142 	 * the interrupt handler.
6143 	 *
6144 	 * XXX: perhaps link state detection procedure used for
6145 	 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6146 	 */
6147 
6148 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6149 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6150 		status = CSR_READ_4(sc, BGE_MAC_STS);
6151 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
6152 			mii = device_get_softc(sc->bge_miibus);
6153 			mii_pollstat(mii);
6154 			if (!sc->bge_link &&
6155 			    mii->mii_media_status & IFM_ACTIVE &&
6156 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6157 				sc->bge_link++;
6158 				if (bootverbose)
6159 					if_printf(sc->bge_ifp, "link UP\n");
6160 			} else if (sc->bge_link &&
6161 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6162 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6163 				sc->bge_link = 0;
6164 				if (bootverbose)
6165 					if_printf(sc->bge_ifp, "link DOWN\n");
6166 			}
6167 
6168 			/* Clear the interrupt. */
6169 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6170 			    BGE_EVTENB_MI_INTERRUPT);
6171 			bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6172 			    BRGPHY_MII_ISR);
6173 			bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6174 			    BRGPHY_MII_IMR, BRGPHY_INTRS);
6175 		}
6176 		return;
6177 	}
6178 
6179 	if (sc->bge_flags & BGE_FLAG_TBI) {
6180 		status = CSR_READ_4(sc, BGE_MAC_STS);
6181 		if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6182 			if (!sc->bge_link) {
6183 				sc->bge_link++;
6184 				if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6185 					BGE_CLRBIT(sc, BGE_MAC_MODE,
6186 					    BGE_MACMODE_TBI_SEND_CFGS);
6187 					DELAY(40);
6188 				}
6189 				CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6190 				if (bootverbose)
6191 					if_printf(sc->bge_ifp, "link UP\n");
6192 				if_link_state_change(sc->bge_ifp,
6193 				    LINK_STATE_UP);
6194 			}
6195 		} else if (sc->bge_link) {
6196 			sc->bge_link = 0;
6197 			if (bootverbose)
6198 				if_printf(sc->bge_ifp, "link DOWN\n");
6199 			if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6200 		}
6201 	} else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6202 		/*
6203 		 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6204 		 * in status word always set. Workaround this bug by reading
6205 		 * PHY link status directly.
6206 		 */
6207 		link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6208 
6209 		if (link != sc->bge_link ||
6210 		    sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6211 			mii = device_get_softc(sc->bge_miibus);
6212 			mii_pollstat(mii);
6213 			if (!sc->bge_link &&
6214 			    mii->mii_media_status & IFM_ACTIVE &&
6215 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6216 				sc->bge_link++;
6217 				if (bootverbose)
6218 					if_printf(sc->bge_ifp, "link UP\n");
6219 			} else if (sc->bge_link &&
6220 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6221 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6222 				sc->bge_link = 0;
6223 				if (bootverbose)
6224 					if_printf(sc->bge_ifp, "link DOWN\n");
6225 			}
6226 		}
6227 	} else {
6228 		/*
6229 		 * For controllers that call mii_tick, we have to poll
6230 		 * link status.
6231 		 */
6232 		mii = device_get_softc(sc->bge_miibus);
6233 		mii_pollstat(mii);
6234 		bge_miibus_statchg(sc->bge_dev);
6235 	}
6236 
6237 	/* Disable MAC attention when link is up. */
6238 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6239 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6240 	    BGE_MACSTAT_LINK_CHANGED);
6241 }
6242 
6243 static void
6244 bge_add_sysctls(struct bge_softc *sc)
6245 {
6246 	struct sysctl_ctx_list *ctx;
6247 	struct sysctl_oid_list *children;
6248 	char tn[32];
6249 	int unit;
6250 
6251 	ctx = device_get_sysctl_ctx(sc->bge_dev);
6252 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6253 
6254 #ifdef BGE_REGISTER_DEBUG
6255 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6256 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6257 	    "Debug Information");
6258 
6259 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6260 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6261 	    "MAC Register Read");
6262 
6263 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6264 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6265 	    "APE Register Read");
6266 
6267 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6268 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6269 	    "Memory Read");
6270 
6271 #endif
6272 
6273 	unit = device_get_unit(sc->bge_dev);
6274 	/*
6275 	 * A common design characteristic for many Broadcom client controllers
6276 	 * is that they only support a single outstanding DMA read operation
6277 	 * on the PCIe bus. This means that it will take twice as long to fetch
6278 	 * a TX frame that is split into header and payload buffers as it does
6279 	 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6280 	 * these controllers, coalescing buffers to reduce the number of memory
6281 	 * reads is effective way to get maximum performance(about 940Mbps).
6282 	 * Without collapsing TX buffers the maximum TCP bulk transfer
6283 	 * performance is about 850Mbps. However forcing coalescing mbufs
6284 	 * consumes a lot of CPU cycles, so leave it off by default.
6285 	 */
6286 	sc->bge_forced_collapse = 0;
6287 	snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6288 	TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6289 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6290 	    CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6291 	    "Number of fragmented TX buffers of a frame allowed before "
6292 	    "forced collapsing");
6293 
6294 	sc->bge_msi = 1;
6295 	snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6296 	TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6297 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6298 	    CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6299 
6300 	/*
6301 	 * It seems all Broadcom controllers have a bug that can generate UDP
6302 	 * datagrams with checksum value 0 when TX UDP checksum offloading is
6303 	 * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6304 	 * Even though the probability of generating such UDP datagrams is
6305 	 * low, I don't want to see FreeBSD boxes to inject such datagrams
6306 	 * into network so disable UDP checksum offloading by default.  Users
6307 	 * still override this behavior by setting a sysctl variable,
6308 	 * dev.bge.0.forced_udpcsum.
6309 	 */
6310 	sc->bge_forced_udpcsum = 0;
6311 	snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6312 	TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6313 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6314 	    CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6315 	    "Enable UDP checksum offloading even if controller can "
6316 	    "generate UDP checksum value 0");
6317 
6318 	if (BGE_IS_5705_PLUS(sc))
6319 		bge_add_sysctl_stats_regs(sc, ctx, children);
6320 	else
6321 		bge_add_sysctl_stats(sc, ctx, children);
6322 }
6323 
6324 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6325 	SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6326 	    sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6327 	    desc)
6328 
6329 static void
6330 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6331     struct sysctl_oid_list *parent)
6332 {
6333 	struct sysctl_oid *tree;
6334 	struct sysctl_oid_list *children, *schildren;
6335 
6336 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6337 	    NULL, "BGE Statistics");
6338 	schildren = children = SYSCTL_CHILDREN(tree);
6339 	BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6340 	    children, COSFramesDroppedDueToFilters,
6341 	    "FramesDroppedDueToFilters");
6342 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6343 	    children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6344 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6345 	    children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6346 	BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6347 	    children, nicNoMoreRxBDs, "NoMoreRxBDs");
6348 	BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6349 	    children, ifInDiscards, "InputDiscards");
6350 	BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6351 	    children, ifInErrors, "InputErrors");
6352 	BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6353 	    children, nicRecvThresholdHit, "RecvThresholdHit");
6354 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6355 	    children, nicDmaReadQueueFull, "DmaReadQueueFull");
6356 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6357 	    children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6358 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6359 	    children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6360 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6361 	    children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6362 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6363 	    children, nicRingStatusUpdate, "RingStatusUpdate");
6364 	BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6365 	    children, nicInterrupts, "Interrupts");
6366 	BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6367 	    children, nicAvoidedInterrupts, "AvoidedInterrupts");
6368 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6369 	    children, nicSendThresholdHit, "SendThresholdHit");
6370 
6371 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6372 	    NULL, "BGE RX Statistics");
6373 	children = SYSCTL_CHILDREN(tree);
6374 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6375 	    children, rxstats.ifHCInOctets, "ifHCInOctets");
6376 	BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6377 	    children, rxstats.etherStatsFragments, "Fragments");
6378 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6379 	    children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6380 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6381 	    children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6382 	BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6383 	    children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6384 	BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6385 	    children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6386 	BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6387 	    children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6388 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6389 	    children, rxstats.xoffPauseFramesReceived,
6390 	    "xoffPauseFramesReceived");
6391 	BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6392 	    children, rxstats.macControlFramesReceived,
6393 	    "ControlFramesReceived");
6394 	BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6395 	    children, rxstats.xoffStateEntered, "xoffStateEntered");
6396 	BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6397 	    children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6398 	BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6399 	    children, rxstats.etherStatsJabbers, "Jabbers");
6400 	BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6401 	    children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6402 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6403 	    children, rxstats.inRangeLengthError, "inRangeLengthError");
6404 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6405 	    children, rxstats.outRangeLengthError, "outRangeLengthError");
6406 
6407 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6408 	    NULL, "BGE TX Statistics");
6409 	children = SYSCTL_CHILDREN(tree);
6410 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6411 	    children, txstats.ifHCOutOctets, "ifHCOutOctets");
6412 	BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6413 	    children, txstats.etherStatsCollisions, "Collisions");
6414 	BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6415 	    children, txstats.outXonSent, "XonSent");
6416 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6417 	    children, txstats.outXoffSent, "XoffSent");
6418 	BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6419 	    children, txstats.flowControlDone, "flowControlDone");
6420 	BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6421 	    children, txstats.dot3StatsInternalMacTransmitErrors,
6422 	    "InternalMacTransmitErrors");
6423 	BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6424 	    children, txstats.dot3StatsSingleCollisionFrames,
6425 	    "SingleCollisionFrames");
6426 	BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6427 	    children, txstats.dot3StatsMultipleCollisionFrames,
6428 	    "MultipleCollisionFrames");
6429 	BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6430 	    children, txstats.dot3StatsDeferredTransmissions,
6431 	    "DeferredTransmissions");
6432 	BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6433 	    children, txstats.dot3StatsExcessiveCollisions,
6434 	    "ExcessiveCollisions");
6435 	BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6436 	    children, txstats.dot3StatsLateCollisions,
6437 	    "LateCollisions");
6438 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6439 	    children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6440 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6441 	    children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6442 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6443 	    children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6444 	BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6445 	    children, txstats.dot3StatsCarrierSenseErrors,
6446 	    "CarrierSenseErrors");
6447 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6448 	    children, txstats.ifOutDiscards, "Discards");
6449 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6450 	    children, txstats.ifOutErrors, "Errors");
6451 }
6452 
6453 #undef BGE_SYSCTL_STAT
6454 
6455 #define	BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
6456 	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6457 
6458 static void
6459 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6460     struct sysctl_oid_list *parent)
6461 {
6462 	struct sysctl_oid *tree;
6463 	struct sysctl_oid_list *child, *schild;
6464 	struct bge_mac_stats *stats;
6465 
6466 	stats = &sc->bge_mac_stats;
6467 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6468 	    NULL, "BGE Statistics");
6469 	schild = child = SYSCTL_CHILDREN(tree);
6470 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6471 	    &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6472 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6473 	    &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6474 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6475 	    &stats->DmaWriteHighPriQueueFull,
6476 	    "NIC DMA Write High Priority Queue Full");
6477 	BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6478 	    &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6479 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6480 	    &stats->InputDiscards, "Discarded Input Frames");
6481 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6482 	    &stats->InputErrors, "Input Errors");
6483 	BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6484 	    &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6485 
6486 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6487 	    NULL, "BGE RX Statistics");
6488 	child = SYSCTL_CHILDREN(tree);
6489 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6490 	    &stats->ifHCInOctets, "Inbound Octets");
6491 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6492 	    &stats->etherStatsFragments, "Fragments");
6493 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6494 	    &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6495 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6496 	    &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6497 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6498 	    &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6499 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6500 	    &stats->dot3StatsFCSErrors, "FCS Errors");
6501 	BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6502 	    &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6503 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6504 	    &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6505 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6506 	    &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6507 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6508 	    &stats->macControlFramesReceived, "MAC Control Frames Received");
6509 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6510 	    &stats->xoffStateEntered, "XOFF State Entered");
6511 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6512 	    &stats->dot3StatsFramesTooLong, "Frames Too Long");
6513 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6514 	    &stats->etherStatsJabbers, "Jabbers");
6515 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6516 	    &stats->etherStatsUndersizePkts, "Undersized Packets");
6517 
6518 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6519 	    NULL, "BGE TX Statistics");
6520 	child = SYSCTL_CHILDREN(tree);
6521 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6522 	    &stats->ifHCOutOctets, "Outbound Octets");
6523 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6524 	    &stats->etherStatsCollisions, "TX Collisions");
6525 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6526 	    &stats->outXonSent, "XON Sent");
6527 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6528 	    &stats->outXoffSent, "XOFF Sent");
6529 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6530 	    &stats->dot3StatsInternalMacTransmitErrors,
6531 	    "Internal MAC TX Errors");
6532 	BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6533 	    &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6534 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6535 	    &stats->dot3StatsMultipleCollisionFrames,
6536 	    "Multiple Collision Frames");
6537 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6538 	    &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6539 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6540 	    &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6541 	BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6542 	    &stats->dot3StatsLateCollisions, "Late Collisions");
6543 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6544 	    &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6545 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6546 	    &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6547 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6548 	    &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6549 }
6550 
6551 #undef	BGE_SYSCTL_STAT_ADD64
6552 
6553 static int
6554 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6555 {
6556 	struct bge_softc *sc;
6557 	uint32_t result;
6558 	int offset;
6559 
6560 	sc = (struct bge_softc *)arg1;
6561 	offset = arg2;
6562 	result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6563 	    offsetof(bge_hostaddr, bge_addr_lo));
6564 	return (sysctl_handle_int(oidp, &result, 0, req));
6565 }
6566 
6567 #ifdef BGE_REGISTER_DEBUG
6568 static int
6569 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6570 {
6571 	struct bge_softc *sc;
6572 	uint16_t *sbdata;
6573 	int error, result, sbsz;
6574 	int i, j;
6575 
6576 	result = -1;
6577 	error = sysctl_handle_int(oidp, &result, 0, req);
6578 	if (error || (req->newptr == NULL))
6579 		return (error);
6580 
6581 	if (result == 1) {
6582 		sc = (struct bge_softc *)arg1;
6583 
6584 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6585 		    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6586 			sbsz = BGE_STATUS_BLK_SZ;
6587 		else
6588 			sbsz = 32;
6589 		sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6590 		printf("Status Block:\n");
6591 		BGE_LOCK(sc);
6592 		bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6593 		    sc->bge_cdata.bge_status_map,
6594 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6595 		for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6596 			printf("%06x:", i);
6597 			for (j = 0; j < 8; j++)
6598 				printf(" %04x", sbdata[i++]);
6599 			printf("\n");
6600 		}
6601 
6602 		printf("Registers:\n");
6603 		for (i = 0x800; i < 0xA00; ) {
6604 			printf("%06x:", i);
6605 			for (j = 0; j < 8; j++) {
6606 				printf(" %08x", CSR_READ_4(sc, i));
6607 				i += 4;
6608 			}
6609 			printf("\n");
6610 		}
6611 		BGE_UNLOCK(sc);
6612 
6613 		printf("Hardware Flags:\n");
6614 		if (BGE_IS_5717_PLUS(sc))
6615 			printf(" - 5717 Plus\n");
6616 		if (BGE_IS_5755_PLUS(sc))
6617 			printf(" - 5755 Plus\n");
6618 		if (BGE_IS_575X_PLUS(sc))
6619 			printf(" - 575X Plus\n");
6620 		if (BGE_IS_5705_PLUS(sc))
6621 			printf(" - 5705 Plus\n");
6622 		if (BGE_IS_5714_FAMILY(sc))
6623 			printf(" - 5714 Family\n");
6624 		if (BGE_IS_5700_FAMILY(sc))
6625 			printf(" - 5700 Family\n");
6626 		if (sc->bge_flags & BGE_FLAG_JUMBO)
6627 			printf(" - Supports Jumbo Frames\n");
6628 		if (sc->bge_flags & BGE_FLAG_PCIX)
6629 			printf(" - PCI-X Bus\n");
6630 		if (sc->bge_flags & BGE_FLAG_PCIE)
6631 			printf(" - PCI Express Bus\n");
6632 		if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6633 			printf(" - No 3 LEDs\n");
6634 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6635 			printf(" - RX Alignment Bug\n");
6636 	}
6637 
6638 	return (error);
6639 }
6640 
6641 static int
6642 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6643 {
6644 	struct bge_softc *sc;
6645 	int error;
6646 	uint16_t result;
6647 	uint32_t val;
6648 
6649 	result = -1;
6650 	error = sysctl_handle_int(oidp, &result, 0, req);
6651 	if (error || (req->newptr == NULL))
6652 		return (error);
6653 
6654 	if (result < 0x8000) {
6655 		sc = (struct bge_softc *)arg1;
6656 		val = CSR_READ_4(sc, result);
6657 		printf("reg 0x%06X = 0x%08X\n", result, val);
6658 	}
6659 
6660 	return (error);
6661 }
6662 
6663 static int
6664 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6665 {
6666 	struct bge_softc *sc;
6667 	int error;
6668 	uint16_t result;
6669 	uint32_t val;
6670 
6671 	result = -1;
6672 	error = sysctl_handle_int(oidp, &result, 0, req);
6673 	if (error || (req->newptr == NULL))
6674 		return (error);
6675 
6676 	if (result < 0x8000) {
6677 		sc = (struct bge_softc *)arg1;
6678 		val = APE_READ_4(sc, result);
6679 		printf("reg 0x%06X = 0x%08X\n", result, val);
6680 	}
6681 
6682 	return (error);
6683 }
6684 
6685 static int
6686 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6687 {
6688 	struct bge_softc *sc;
6689 	int error;
6690 	uint16_t result;
6691 	uint32_t val;
6692 
6693 	result = -1;
6694 	error = sysctl_handle_int(oidp, &result, 0, req);
6695 	if (error || (req->newptr == NULL))
6696 		return (error);
6697 
6698 	if (result < 0x8000) {
6699 		sc = (struct bge_softc *)arg1;
6700 		val = bge_readmem_ind(sc, result);
6701 		printf("mem 0x%06X = 0x%08X\n", result, val);
6702 	}
6703 
6704 	return (error);
6705 }
6706 #endif
6707 
6708 static int
6709 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6710 {
6711 
6712 	if (sc->bge_flags & BGE_FLAG_EADDR)
6713 		return (1);
6714 
6715 #ifdef __sparc64__
6716 	OF_getetheraddr(sc->bge_dev, ether_addr);
6717 	return (0);
6718 #endif
6719 	return (1);
6720 }
6721 
6722 static int
6723 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6724 {
6725 	uint32_t mac_addr;
6726 
6727 	mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6728 	if ((mac_addr >> 16) == 0x484b) {
6729 		ether_addr[0] = (uint8_t)(mac_addr >> 8);
6730 		ether_addr[1] = (uint8_t)mac_addr;
6731 		mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6732 		ether_addr[2] = (uint8_t)(mac_addr >> 24);
6733 		ether_addr[3] = (uint8_t)(mac_addr >> 16);
6734 		ether_addr[4] = (uint8_t)(mac_addr >> 8);
6735 		ether_addr[5] = (uint8_t)mac_addr;
6736 		return (0);
6737 	}
6738 	return (1);
6739 }
6740 
6741 static int
6742 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6743 {
6744 	int mac_offset = BGE_EE_MAC_OFFSET;
6745 
6746 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6747 		mac_offset = BGE_EE_MAC_OFFSET_5906;
6748 
6749 	return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6750 	    ETHER_ADDR_LEN));
6751 }
6752 
6753 static int
6754 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6755 {
6756 
6757 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6758 		return (1);
6759 
6760 	return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6761 	   ETHER_ADDR_LEN));
6762 }
6763 
6764 static int
6765 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6766 {
6767 	static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6768 		/* NOTE: Order is critical */
6769 		bge_get_eaddr_fw,
6770 		bge_get_eaddr_mem,
6771 		bge_get_eaddr_nvram,
6772 		bge_get_eaddr_eeprom,
6773 		NULL
6774 	};
6775 	const bge_eaddr_fcn_t *func;
6776 
6777 	for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6778 		if ((*func)(sc, eaddr) == 0)
6779 			break;
6780 	}
6781 	return (*func == NULL ? ENXIO : 0);
6782 }
6783