195d67482SBill Paul /* 295d67482SBill Paul * Copyright (c) 2001 Wind River Systems 395d67482SBill Paul * Copyright (c) 1997, 1998, 1999, 2001 495d67482SBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 595d67482SBill Paul * 695d67482SBill Paul * Redistribution and use in source and binary forms, with or without 795d67482SBill Paul * modification, are permitted provided that the following conditions 895d67482SBill Paul * are met: 995d67482SBill Paul * 1. Redistributions of source code must retain the above copyright 1095d67482SBill Paul * notice, this list of conditions and the following disclaimer. 1195d67482SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1295d67482SBill Paul * notice, this list of conditions and the following disclaimer in the 1395d67482SBill Paul * documentation and/or other materials provided with the distribution. 1495d67482SBill Paul * 3. All advertising materials mentioning features or use of this software 1595d67482SBill Paul * must display the following acknowledgement: 1695d67482SBill Paul * This product includes software developed by Bill Paul. 1795d67482SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1895d67482SBill Paul * may be used to endorse or promote products derived from this software 1995d67482SBill Paul * without specific prior written permission. 2095d67482SBill Paul * 2195d67482SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2295d67482SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2395d67482SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2495d67482SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2595d67482SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2695d67482SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2795d67482SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2895d67482SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2995d67482SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3095d67482SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3195d67482SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3295d67482SBill Paul * 3395d67482SBill Paul * $FreeBSD$ 3495d67482SBill Paul */ 3595d67482SBill Paul 3695d67482SBill Paul /* 3795d67482SBill Paul * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 3895d67482SBill Paul * 3995d67482SBill Paul * Written by Bill Paul <wpaul@windriver.com> 4095d67482SBill Paul * Senior Engineer, Wind River Systems 4195d67482SBill Paul */ 4295d67482SBill Paul 4395d67482SBill Paul /* 4495d67482SBill Paul * The Broadcom BCM5700 is based on technology originally developed by 4595d67482SBill Paul * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 4695d67482SBill Paul * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 4795d67482SBill Paul * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 4895d67482SBill Paul * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 4995d67482SBill Paul * frames, highly configurable RX filtering, and 16 RX and TX queues 5095d67482SBill Paul * (which, along with RX filter rules, can be used for QOS applications). 5195d67482SBill Paul * Other features, such as TCP segmentation, may be available as part 5295d67482SBill Paul * of value-added firmware updates. Unlike the Tigon I and Tigon II, 5395d67482SBill Paul * firmware images can be stored in hardware and need not be compiled 5495d67482SBill Paul * into the driver. 5595d67482SBill Paul * 5695d67482SBill Paul * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 5795d67482SBill Paul * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 5895d67482SBill Paul * 5995d67482SBill Paul * The BCM5701 is a single-chip solution incorporating both the BCM5700 6095d67482SBill Paul * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 6195d67482SBill Paul * does not support external SSRAM. 6295d67482SBill Paul * 6395d67482SBill Paul * Broadcom also produces a variation of the BCM5700 under the "Altima" 6495d67482SBill Paul * brand name, which is functionally similar but lacks PCI-X support. 6595d67482SBill Paul * 6695d67482SBill Paul * Without external SSRAM, you can only have at most 4 TX rings, 6795d67482SBill Paul * and the use of the mini RX ring is disabled. This seems to imply 6895d67482SBill Paul * that these features are simply not available on the BCM5701. As a 6995d67482SBill Paul * result, this driver does not implement any support for the mini RX 7095d67482SBill Paul * ring. 7195d67482SBill Paul */ 7295d67482SBill Paul 7395d67482SBill Paul #include <sys/param.h> 7495d67482SBill Paul #include <sys/systm.h> 7595d67482SBill Paul #include <sys/sockio.h> 7695d67482SBill Paul #include <sys/mbuf.h> 7795d67482SBill Paul #include <sys/malloc.h> 7895d67482SBill Paul #include <sys/kernel.h> 7995d67482SBill Paul #include <sys/socket.h> 8095d67482SBill Paul #include <sys/queue.h> 8195d67482SBill Paul 8295d67482SBill Paul #include <net/if.h> 8395d67482SBill Paul #include <net/if_arp.h> 8495d67482SBill Paul #include <net/ethernet.h> 8595d67482SBill Paul #include <net/if_dl.h> 8695d67482SBill Paul #include <net/if_media.h> 8795d67482SBill Paul 8895d67482SBill Paul #include <net/bpf.h> 8995d67482SBill Paul 9095d67482SBill Paul #include <net/if_types.h> 9195d67482SBill Paul #include <net/if_vlan_var.h> 9295d67482SBill Paul 9395d67482SBill Paul #include <netinet/in_systm.h> 9495d67482SBill Paul #include <netinet/in.h> 9595d67482SBill Paul #include <netinet/ip.h> 9695d67482SBill Paul 9795d67482SBill Paul #include <vm/vm.h> /* for vtophys */ 9895d67482SBill Paul #include <vm/pmap.h> /* for vtophys */ 9995d67482SBill Paul #include <machine/clock.h> /* for DELAY */ 10095d67482SBill Paul #include <machine/bus_memio.h> 10195d67482SBill Paul #include <machine/bus.h> 10295d67482SBill Paul #include <machine/resource.h> 10395d67482SBill Paul #include <sys/bus.h> 10495d67482SBill Paul #include <sys/rman.h> 10595d67482SBill Paul 10695d67482SBill Paul #include <dev/mii/mii.h> 10795d67482SBill Paul #include <dev/mii/miivar.h> 10895d67482SBill Paul #include <dev/mii/miidevs.h> 10995d67482SBill Paul #include <dev/mii/brgphyreg.h> 11095d67482SBill Paul 11195d67482SBill Paul #include <pci/pcireg.h> 11295d67482SBill Paul #include <pci/pcivar.h> 11395d67482SBill Paul 11495d67482SBill Paul #include <dev/bge/if_bgereg.h> 11595d67482SBill Paul 11695d67482SBill Paul #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 11795d67482SBill Paul 11895d67482SBill Paul MODULE_DEPEND(bge, miibus, 1, 1, 1); 11995d67482SBill Paul 12095d67482SBill Paul /* "controller miibus0" required. See GENERIC if you get errors here. */ 12195d67482SBill Paul #include "miibus_if.h" 12295d67482SBill Paul 12395d67482SBill Paul #if !defined(lint) 12495d67482SBill Paul static const char rcsid[] = 12595d67482SBill Paul "$FreeBSD$"; 12695d67482SBill Paul #endif 12795d67482SBill Paul 12895d67482SBill Paul /* 12995d67482SBill Paul * Various supported device vendors/types and their names. Note: the 13095d67482SBill Paul * spec seems to indicate that the hardware still has Alteon's vendor 13195d67482SBill Paul * ID burned into it, though it will always be overriden by the vendor 13295d67482SBill Paul * ID in the EEPROM. Just to be safe, we cover all possibilities. 13395d67482SBill Paul */ 13495d67482SBill Paul 13595d67482SBill Paul static struct bge_type bge_devs[] = { 13695d67482SBill Paul { ALT_VENDORID, ALT_DEVICEID_BCM5700, 13795d67482SBill Paul "Broadcom BCM5700 Gigabit Ethernet" }, 13895d67482SBill Paul { ALT_VENDORID, ALT_DEVICEID_BCM5701, 13995d67482SBill Paul "Broadcom BCM5701 Gigabit Ethernet" }, 14095d67482SBill Paul { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 14195d67482SBill Paul "Broadcom BCM5700 Gigabit Ethernet" }, 14295d67482SBill Paul { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 14395d67482SBill Paul "Broadcom BCM5701 Gigabit Ethernet" }, 14495d67482SBill Paul { SK_VENDORID, SK_DEVICEID_ALTIMA, 14595d67482SBill Paul "SysKonnect Gigabit Ethernet" }, 146586d7c2eSJohn Polstra { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 147586d7c2eSJohn Polstra "Altima AC1000 Gigabit Ethernet" }, 14895d67482SBill Paul { 0, 0, NULL } 14995d67482SBill Paul }; 15095d67482SBill Paul 151e51a25f8SAlfred Perlstein static int bge_probe (device_t); 152e51a25f8SAlfred Perlstein static int bge_attach (device_t); 153e51a25f8SAlfred Perlstein static int bge_detach (device_t); 15495d67482SBill Paul static void bge_release_resources 155e51a25f8SAlfred Perlstein (struct bge_softc *); 156e51a25f8SAlfred Perlstein static void bge_txeof (struct bge_softc *); 157e51a25f8SAlfred Perlstein static void bge_rxeof (struct bge_softc *); 15895d67482SBill Paul 159e51a25f8SAlfred Perlstein static void bge_tick (void *); 160e51a25f8SAlfred Perlstein static void bge_stats_update (struct bge_softc *); 161e51a25f8SAlfred Perlstein static int bge_encap (struct bge_softc *, struct mbuf *, 162e51a25f8SAlfred Perlstein u_int32_t *); 16395d67482SBill Paul 164e51a25f8SAlfred Perlstein static void bge_intr (void *); 165e51a25f8SAlfred Perlstein static void bge_start (struct ifnet *); 166e51a25f8SAlfred Perlstein static int bge_ioctl (struct ifnet *, u_long, caddr_t); 167e51a25f8SAlfred Perlstein static void bge_init (void *); 168e51a25f8SAlfred Perlstein static void bge_stop (struct bge_softc *); 169e51a25f8SAlfred Perlstein static void bge_watchdog (struct ifnet *); 170e51a25f8SAlfred Perlstein static void bge_shutdown (device_t); 171e51a25f8SAlfred Perlstein static int bge_ifmedia_upd (struct ifnet *); 172e51a25f8SAlfred Perlstein static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 17395d67482SBill Paul 174e51a25f8SAlfred Perlstein static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 175e51a25f8SAlfred Perlstein static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 17695d67482SBill Paul 177e51a25f8SAlfred Perlstein static u_int32_t bge_crc (caddr_t); 178e51a25f8SAlfred Perlstein static void bge_setmulti (struct bge_softc *); 17995d67482SBill Paul 180e51a25f8SAlfred Perlstein static void bge_handle_events (struct bge_softc *); 181e51a25f8SAlfred Perlstein static int bge_alloc_jumbo_mem (struct bge_softc *); 182e51a25f8SAlfred Perlstein static void bge_free_jumbo_mem (struct bge_softc *); 183e51a25f8SAlfred Perlstein static void *bge_jalloc (struct bge_softc *); 184e51a25f8SAlfred Perlstein static void bge_jfree (caddr_t, void *); 185e51a25f8SAlfred Perlstein static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 186e51a25f8SAlfred Perlstein static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 187e51a25f8SAlfred Perlstein static int bge_init_rx_ring_std (struct bge_softc *); 188e51a25f8SAlfred Perlstein static void bge_free_rx_ring_std (struct bge_softc *); 189e51a25f8SAlfred Perlstein static int bge_init_rx_ring_jumbo (struct bge_softc *); 190e51a25f8SAlfred Perlstein static void bge_free_rx_ring_jumbo (struct bge_softc *); 191e51a25f8SAlfred Perlstein static void bge_free_tx_ring (struct bge_softc *); 192e51a25f8SAlfred Perlstein static int bge_init_tx_ring (struct bge_softc *); 19395d67482SBill Paul 194e51a25f8SAlfred Perlstein static int bge_chipinit (struct bge_softc *); 195e51a25f8SAlfred Perlstein static int bge_blockinit (struct bge_softc *); 19695d67482SBill Paul 1971b4a3b2fSPeter Wemm #ifdef notdef 198e51a25f8SAlfred Perlstein static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 199e51a25f8SAlfred Perlstein static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 200e51a25f8SAlfred Perlstein static void bge_vpd_read (struct bge_softc *); 2011b4a3b2fSPeter Wemm #endif 20295d67482SBill Paul 20395d67482SBill Paul static u_int32_t bge_readmem_ind 204e51a25f8SAlfred Perlstein (struct bge_softc *, int); 205e51a25f8SAlfred Perlstein static void bge_writemem_ind (struct bge_softc *, int, int); 20695d67482SBill Paul #ifdef notdef 20795d67482SBill Paul static u_int32_t bge_readreg_ind 208e51a25f8SAlfred Perlstein (struct bge_softc *, int); 20995d67482SBill Paul #endif 210e51a25f8SAlfred Perlstein static void bge_writereg_ind (struct bge_softc *, int, int); 21195d67482SBill Paul 212e51a25f8SAlfred Perlstein static int bge_miibus_readreg (device_t, int, int); 213e51a25f8SAlfred Perlstein static int bge_miibus_writereg (device_t, int, int, int); 214e51a25f8SAlfred Perlstein static void bge_miibus_statchg (device_t); 21595d67482SBill Paul 216e51a25f8SAlfred Perlstein static void bge_reset (struct bge_softc *); 217e51a25f8SAlfred Perlstein static void bge_phy_hack (struct bge_softc *); 21895d67482SBill Paul 21995d67482SBill Paul static device_method_t bge_methods[] = { 22095d67482SBill Paul /* Device interface */ 22195d67482SBill Paul DEVMETHOD(device_probe, bge_probe), 22295d67482SBill Paul DEVMETHOD(device_attach, bge_attach), 22395d67482SBill Paul DEVMETHOD(device_detach, bge_detach), 22495d67482SBill Paul DEVMETHOD(device_shutdown, bge_shutdown), 22595d67482SBill Paul 22695d67482SBill Paul /* bus interface */ 22795d67482SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 22895d67482SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22995d67482SBill Paul 23095d67482SBill Paul /* MII interface */ 23195d67482SBill Paul DEVMETHOD(miibus_readreg, bge_miibus_readreg), 23295d67482SBill Paul DEVMETHOD(miibus_writereg, bge_miibus_writereg), 23395d67482SBill Paul DEVMETHOD(miibus_statchg, bge_miibus_statchg), 23495d67482SBill Paul 23595d67482SBill Paul { 0, 0 } 23695d67482SBill Paul }; 23795d67482SBill Paul 23895d67482SBill Paul static driver_t bge_driver = { 23995d67482SBill Paul "bge", 24095d67482SBill Paul bge_methods, 24195d67482SBill Paul sizeof(struct bge_softc) 24295d67482SBill Paul }; 24395d67482SBill Paul 24495d67482SBill Paul static devclass_t bge_devclass; 24595d67482SBill Paul 24695d67482SBill Paul DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 24795d67482SBill Paul DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 24895d67482SBill Paul 24995d67482SBill Paul static u_int32_t 25095d67482SBill Paul bge_readmem_ind(sc, off) 25195d67482SBill Paul struct bge_softc *sc; 25295d67482SBill Paul int off; 25395d67482SBill Paul { 25495d67482SBill Paul device_t dev; 25595d67482SBill Paul 25695d67482SBill Paul dev = sc->bge_dev; 25795d67482SBill Paul 25895d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 25995d67482SBill Paul return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 26095d67482SBill Paul } 26195d67482SBill Paul 26295d67482SBill Paul static void 26395d67482SBill Paul bge_writemem_ind(sc, off, val) 26495d67482SBill Paul struct bge_softc *sc; 26595d67482SBill Paul int off, val; 26695d67482SBill Paul { 26795d67482SBill Paul device_t dev; 26895d67482SBill Paul 26995d67482SBill Paul dev = sc->bge_dev; 27095d67482SBill Paul 27195d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 27295d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 27395d67482SBill Paul 27495d67482SBill Paul return; 27595d67482SBill Paul } 27695d67482SBill Paul 27795d67482SBill Paul #ifdef notdef 27895d67482SBill Paul static u_int32_t 27995d67482SBill Paul bge_readreg_ind(sc, off) 28095d67482SBill Paul struct bge_softc *sc; 28195d67482SBill Paul int off; 28295d67482SBill Paul { 28395d67482SBill Paul device_t dev; 28495d67482SBill Paul 28595d67482SBill Paul dev = sc->bge_dev; 28695d67482SBill Paul 28795d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 28895d67482SBill Paul return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 28995d67482SBill Paul } 29095d67482SBill Paul #endif 29195d67482SBill Paul 29295d67482SBill Paul static void 29395d67482SBill Paul bge_writereg_ind(sc, off, val) 29495d67482SBill Paul struct bge_softc *sc; 29595d67482SBill Paul int off, val; 29695d67482SBill Paul { 29795d67482SBill Paul device_t dev; 29895d67482SBill Paul 29995d67482SBill Paul dev = sc->bge_dev; 30095d67482SBill Paul 30195d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 30295d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 30395d67482SBill Paul 30495d67482SBill Paul return; 30595d67482SBill Paul } 30695d67482SBill Paul 3071b4a3b2fSPeter Wemm #ifdef notdef 30895d67482SBill Paul static u_int8_t 30995d67482SBill Paul bge_vpd_readbyte(sc, addr) 31095d67482SBill Paul struct bge_softc *sc; 31195d67482SBill Paul int addr; 31295d67482SBill Paul { 31395d67482SBill Paul int i; 31495d67482SBill Paul device_t dev; 31595d67482SBill Paul u_int32_t val; 31695d67482SBill Paul 31795d67482SBill Paul dev = sc->bge_dev; 31895d67482SBill Paul pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 31995d67482SBill Paul for (i = 0; i < BGE_TIMEOUT * 10; i++) { 32095d67482SBill Paul DELAY(10); 32195d67482SBill Paul if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 32295d67482SBill Paul break; 32395d67482SBill Paul } 32495d67482SBill Paul 32595d67482SBill Paul if (i == BGE_TIMEOUT) { 32695d67482SBill Paul printf("bge%d: VPD read timed out\n", sc->bge_unit); 32795d67482SBill Paul return(0); 32895d67482SBill Paul } 32995d67482SBill Paul 33095d67482SBill Paul val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 33195d67482SBill Paul 33295d67482SBill Paul return((val >> ((addr % 4) * 8)) & 0xFF); 33395d67482SBill Paul } 33495d67482SBill Paul 33595d67482SBill Paul static void 33695d67482SBill Paul bge_vpd_read_res(sc, res, addr) 33795d67482SBill Paul struct bge_softc *sc; 33895d67482SBill Paul struct vpd_res *res; 33995d67482SBill Paul int addr; 34095d67482SBill Paul { 34195d67482SBill Paul int i; 34295d67482SBill Paul u_int8_t *ptr; 34395d67482SBill Paul 34495d67482SBill Paul ptr = (u_int8_t *)res; 34595d67482SBill Paul for (i = 0; i < sizeof(struct vpd_res); i++) 34695d67482SBill Paul ptr[i] = bge_vpd_readbyte(sc, i + addr); 34795d67482SBill Paul 34895d67482SBill Paul return; 34995d67482SBill Paul } 35095d67482SBill Paul 35195d67482SBill Paul static void 35295d67482SBill Paul bge_vpd_read(sc) 35395d67482SBill Paul struct bge_softc *sc; 35495d67482SBill Paul { 35595d67482SBill Paul int pos = 0, i; 35695d67482SBill Paul struct vpd_res res; 35795d67482SBill Paul 35895d67482SBill Paul if (sc->bge_vpd_prodname != NULL) 35995d67482SBill Paul free(sc->bge_vpd_prodname, M_DEVBUF); 36095d67482SBill Paul if (sc->bge_vpd_readonly != NULL) 36195d67482SBill Paul free(sc->bge_vpd_readonly, M_DEVBUF); 36295d67482SBill Paul sc->bge_vpd_prodname = NULL; 36395d67482SBill Paul sc->bge_vpd_readonly = NULL; 36495d67482SBill Paul 36595d67482SBill Paul bge_vpd_read_res(sc, &res, pos); 36695d67482SBill Paul 36795d67482SBill Paul if (res.vr_id != VPD_RES_ID) { 36895d67482SBill Paul printf("bge%d: bad VPD resource id: expected %x got %x\n", 36995d67482SBill Paul sc->bge_unit, VPD_RES_ID, res.vr_id); 37095d67482SBill Paul return; 37195d67482SBill Paul } 37295d67482SBill Paul 37395d67482SBill Paul pos += sizeof(res); 37495d67482SBill Paul sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 37595d67482SBill Paul for (i = 0; i < res.vr_len; i++) 37695d67482SBill Paul sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 37795d67482SBill Paul sc->bge_vpd_prodname[i] = '\0'; 37895d67482SBill Paul pos += i; 37995d67482SBill Paul 38095d67482SBill Paul bge_vpd_read_res(sc, &res, pos); 38195d67482SBill Paul 38295d67482SBill Paul if (res.vr_id != VPD_RES_READ) { 38395d67482SBill Paul printf("bge%d: bad VPD resource id: expected %x got %x\n", 38495d67482SBill Paul sc->bge_unit, VPD_RES_READ, res.vr_id); 38595d67482SBill Paul return; 38695d67482SBill Paul } 38795d67482SBill Paul 38895d67482SBill Paul pos += sizeof(res); 38995d67482SBill Paul sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 39095d67482SBill Paul for (i = 0; i < res.vr_len + 1; i++) 39195d67482SBill Paul sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 39295d67482SBill Paul 39395d67482SBill Paul return; 39495d67482SBill Paul } 3951b4a3b2fSPeter Wemm #endif 39695d67482SBill Paul 39795d67482SBill Paul /* 39895d67482SBill Paul * Read a byte of data stored in the EEPROM at address 'addr.' The 39995d67482SBill Paul * BCM570x supports both the traditional bitbang interface and an 40095d67482SBill Paul * auto access interface for reading the EEPROM. We use the auto 40195d67482SBill Paul * access method. 40295d67482SBill Paul */ 40395d67482SBill Paul static u_int8_t 40495d67482SBill Paul bge_eeprom_getbyte(sc, addr, dest) 40595d67482SBill Paul struct bge_softc *sc; 40695d67482SBill Paul int addr; 40795d67482SBill Paul u_int8_t *dest; 40895d67482SBill Paul { 40995d67482SBill Paul int i; 41095d67482SBill Paul u_int32_t byte = 0; 41195d67482SBill Paul 41295d67482SBill Paul /* 41395d67482SBill Paul * Enable use of auto EEPROM access so we can avoid 41495d67482SBill Paul * having to use the bitbang method. 41595d67482SBill Paul */ 41695d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 41795d67482SBill Paul 41895d67482SBill Paul /* Reset the EEPROM, load the clock period. */ 41995d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, 42095d67482SBill Paul BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 42195d67482SBill Paul DELAY(20); 42295d67482SBill Paul 42395d67482SBill Paul /* Issue the read EEPROM command. */ 42495d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 42595d67482SBill Paul 42695d67482SBill Paul /* Wait for completion */ 42795d67482SBill Paul for(i = 0; i < BGE_TIMEOUT * 10; i++) { 42895d67482SBill Paul DELAY(10); 42995d67482SBill Paul if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 43095d67482SBill Paul break; 43195d67482SBill Paul } 43295d67482SBill Paul 43395d67482SBill Paul if (i == BGE_TIMEOUT) { 43495d67482SBill Paul printf("bge%d: eeprom read timed out\n", sc->bge_unit); 43595d67482SBill Paul return(0); 43695d67482SBill Paul } 43795d67482SBill Paul 43895d67482SBill Paul /* Get result. */ 43995d67482SBill Paul byte = CSR_READ_4(sc, BGE_EE_DATA); 44095d67482SBill Paul 44195d67482SBill Paul *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 44295d67482SBill Paul 44395d67482SBill Paul return(0); 44495d67482SBill Paul } 44595d67482SBill Paul 44695d67482SBill Paul /* 44795d67482SBill Paul * Read a sequence of bytes from the EEPROM. 44895d67482SBill Paul */ 44995d67482SBill Paul static int 45095d67482SBill Paul bge_read_eeprom(sc, dest, off, cnt) 45195d67482SBill Paul struct bge_softc *sc; 45295d67482SBill Paul caddr_t dest; 45395d67482SBill Paul int off; 45495d67482SBill Paul int cnt; 45595d67482SBill Paul { 45695d67482SBill Paul int err = 0, i; 45795d67482SBill Paul u_int8_t byte = 0; 45895d67482SBill Paul 45995d67482SBill Paul for (i = 0; i < cnt; i++) { 46095d67482SBill Paul err = bge_eeprom_getbyte(sc, off + i, &byte); 46195d67482SBill Paul if (err) 46295d67482SBill Paul break; 46395d67482SBill Paul *(dest + i) = byte; 46495d67482SBill Paul } 46595d67482SBill Paul 46695d67482SBill Paul return(err ? 1 : 0); 46795d67482SBill Paul } 46895d67482SBill Paul 46995d67482SBill Paul static int 47095d67482SBill Paul bge_miibus_readreg(dev, phy, reg) 47195d67482SBill Paul device_t dev; 47295d67482SBill Paul int phy, reg; 47395d67482SBill Paul { 47495d67482SBill Paul struct bge_softc *sc; 47595d67482SBill Paul struct ifnet *ifp; 47695d67482SBill Paul u_int32_t val; 47795d67482SBill Paul int i; 47895d67482SBill Paul 47995d67482SBill Paul sc = device_get_softc(dev); 48095d67482SBill Paul ifp = &sc->arpcom.ac_if; 48195d67482SBill Paul 48295d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) 48395d67482SBill Paul BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 48495d67482SBill Paul 48595d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 48695d67482SBill Paul BGE_MIPHY(phy)|BGE_MIREG(reg)); 48795d67482SBill Paul 48895d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 48995d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 49095d67482SBill Paul if (!(val & BGE_MICOMM_BUSY)) 49195d67482SBill Paul break; 49295d67482SBill Paul } 49395d67482SBill Paul 49495d67482SBill Paul if (i == BGE_TIMEOUT) { 49595d67482SBill Paul printf("bge%d: PHY read timed out\n", sc->bge_unit); 49695d67482SBill Paul return(0); 49795d67482SBill Paul } 49895d67482SBill Paul 49995d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 50095d67482SBill Paul 50195d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) 50295d67482SBill Paul BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 50395d67482SBill Paul 50495d67482SBill Paul if (val & BGE_MICOMM_READFAIL) 50595d67482SBill Paul return(0); 50695d67482SBill Paul 50795d67482SBill Paul return(val & 0xFFFF); 50895d67482SBill Paul } 50995d67482SBill Paul 51095d67482SBill Paul static int 51195d67482SBill Paul bge_miibus_writereg(dev, phy, reg, val) 51295d67482SBill Paul device_t dev; 51395d67482SBill Paul int phy, reg, val; 51495d67482SBill Paul { 51595d67482SBill Paul struct bge_softc *sc; 51695d67482SBill Paul int i; 51795d67482SBill Paul 51895d67482SBill Paul sc = device_get_softc(dev); 51995d67482SBill Paul 52095d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 52195d67482SBill Paul BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 52295d67482SBill Paul 52395d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 52495d67482SBill Paul if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 52595d67482SBill Paul break; 52695d67482SBill Paul } 52795d67482SBill Paul 52895d67482SBill Paul if (i == BGE_TIMEOUT) { 52995d67482SBill Paul printf("bge%d: PHY read timed out\n", sc->bge_unit); 53095d67482SBill Paul return(0); 53195d67482SBill Paul } 53295d67482SBill Paul 53395d67482SBill Paul return(0); 53495d67482SBill Paul } 53595d67482SBill Paul 53695d67482SBill Paul static void 53795d67482SBill Paul bge_miibus_statchg(dev) 53895d67482SBill Paul device_t dev; 53995d67482SBill Paul { 54095d67482SBill Paul struct bge_softc *sc; 54195d67482SBill Paul struct mii_data *mii; 54295d67482SBill Paul 54395d67482SBill Paul sc = device_get_softc(dev); 54495d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 54595d67482SBill Paul 54695d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 54795d67482SBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 54895d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 54995d67482SBill Paul } else { 55095d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 55195d67482SBill Paul } 55295d67482SBill Paul 55395d67482SBill Paul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 55495d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 55595d67482SBill Paul } else { 55695d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 55795d67482SBill Paul } 55895d67482SBill Paul 55995d67482SBill Paul bge_phy_hack(sc); 56095d67482SBill Paul 56195d67482SBill Paul return; 56295d67482SBill Paul } 56395d67482SBill Paul 56495d67482SBill Paul /* 56595d67482SBill Paul * Handle events that have triggered interrupts. 56695d67482SBill Paul */ 56795d67482SBill Paul static void 56895d67482SBill Paul bge_handle_events(sc) 56995d67482SBill Paul struct bge_softc *sc; 57095d67482SBill Paul { 57195d67482SBill Paul 57295d67482SBill Paul return; 57395d67482SBill Paul } 57495d67482SBill Paul 57595d67482SBill Paul /* 57695d67482SBill Paul * Memory management for jumbo frames. 57795d67482SBill Paul */ 57895d67482SBill Paul 57995d67482SBill Paul static int 58095d67482SBill Paul bge_alloc_jumbo_mem(sc) 58195d67482SBill Paul struct bge_softc *sc; 58295d67482SBill Paul { 58395d67482SBill Paul caddr_t ptr; 58495d67482SBill Paul register int i; 58595d67482SBill Paul struct bge_jpool_entry *entry; 58695d67482SBill Paul 58795d67482SBill Paul /* Grab a big chunk o' storage. */ 58895d67482SBill Paul sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 58995d67482SBill Paul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 59095d67482SBill Paul 59195d67482SBill Paul if (sc->bge_cdata.bge_jumbo_buf == NULL) { 59295d67482SBill Paul printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 59395d67482SBill Paul return(ENOBUFS); 59495d67482SBill Paul } 59595d67482SBill Paul 59695d67482SBill Paul SLIST_INIT(&sc->bge_jfree_listhead); 59795d67482SBill Paul SLIST_INIT(&sc->bge_jinuse_listhead); 59895d67482SBill Paul 59995d67482SBill Paul /* 60095d67482SBill Paul * Now divide it up into 9K pieces and save the addresses 60195d67482SBill Paul * in an array. 60295d67482SBill Paul */ 60395d67482SBill Paul ptr = sc->bge_cdata.bge_jumbo_buf; 60495d67482SBill Paul for (i = 0; i < BGE_JSLOTS; i++) { 60595d67482SBill Paul sc->bge_cdata.bge_jslots[i] = ptr; 60695d67482SBill Paul ptr += BGE_JLEN; 60795d67482SBill Paul entry = malloc(sizeof(struct bge_jpool_entry), 60895d67482SBill Paul M_DEVBUF, M_NOWAIT); 60995d67482SBill Paul if (entry == NULL) { 61095d67482SBill Paul contigfree(sc->bge_cdata.bge_jumbo_buf, 61195d67482SBill Paul BGE_JMEM, M_DEVBUF); 61295d67482SBill Paul sc->bge_cdata.bge_jumbo_buf = NULL; 61395d67482SBill Paul printf("bge%d: no memory for jumbo " 61495d67482SBill Paul "buffer queue!\n", sc->bge_unit); 61595d67482SBill Paul return(ENOBUFS); 61695d67482SBill Paul } 61795d67482SBill Paul entry->slot = i; 61895d67482SBill Paul SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 61995d67482SBill Paul entry, jpool_entries); 62095d67482SBill Paul } 62195d67482SBill Paul 62295d67482SBill Paul return(0); 62395d67482SBill Paul } 62495d67482SBill Paul 62595d67482SBill Paul static void 62695d67482SBill Paul bge_free_jumbo_mem(sc) 62795d67482SBill Paul struct bge_softc *sc; 62895d67482SBill Paul { 62995d67482SBill Paul int i; 63095d67482SBill Paul struct bge_jpool_entry *entry; 63195d67482SBill Paul 63295d67482SBill Paul for (i = 0; i < BGE_JSLOTS; i++) { 63395d67482SBill Paul entry = SLIST_FIRST(&sc->bge_jfree_listhead); 63495d67482SBill Paul SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 63595d67482SBill Paul free(entry, M_DEVBUF); 63695d67482SBill Paul } 63795d67482SBill Paul 63895d67482SBill Paul contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 63995d67482SBill Paul 64095d67482SBill Paul return; 64195d67482SBill Paul } 64295d67482SBill Paul 64395d67482SBill Paul /* 64495d67482SBill Paul * Allocate a jumbo buffer. 64595d67482SBill Paul */ 64695d67482SBill Paul static void * 64795d67482SBill Paul bge_jalloc(sc) 64895d67482SBill Paul struct bge_softc *sc; 64995d67482SBill Paul { 65095d67482SBill Paul struct bge_jpool_entry *entry; 65195d67482SBill Paul 65295d67482SBill Paul entry = SLIST_FIRST(&sc->bge_jfree_listhead); 65395d67482SBill Paul 65495d67482SBill Paul if (entry == NULL) { 65595d67482SBill Paul printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 65695d67482SBill Paul return(NULL); 65795d67482SBill Paul } 65895d67482SBill Paul 65995d67482SBill Paul SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 66095d67482SBill Paul SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 66195d67482SBill Paul return(sc->bge_cdata.bge_jslots[entry->slot]); 66295d67482SBill Paul } 66395d67482SBill Paul 66495d67482SBill Paul /* 66595d67482SBill Paul * Release a jumbo buffer. 66695d67482SBill Paul */ 66795d67482SBill Paul static void 66895d67482SBill Paul bge_jfree(buf, args) 66995d67482SBill Paul caddr_t buf; 67095d67482SBill Paul void *args; 67195d67482SBill Paul { 67295d67482SBill Paul struct bge_jpool_entry *entry; 67395d67482SBill Paul struct bge_softc *sc; 67495d67482SBill Paul int i; 67595d67482SBill Paul 67695d67482SBill Paul /* Extract the softc struct pointer. */ 67795d67482SBill Paul sc = (struct bge_softc *)args; 67895d67482SBill Paul 67995d67482SBill Paul if (sc == NULL) 68095d67482SBill Paul panic("bge_jfree: can't find softc pointer!"); 68195d67482SBill Paul 68295d67482SBill Paul /* calculate the slot this buffer belongs to */ 68395d67482SBill Paul 68495d67482SBill Paul i = ((vm_offset_t)buf 68595d67482SBill Paul - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 68695d67482SBill Paul 68795d67482SBill Paul if ((i < 0) || (i >= BGE_JSLOTS)) 68895d67482SBill Paul panic("bge_jfree: asked to free buffer that we don't manage!"); 68995d67482SBill Paul 69095d67482SBill Paul entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 69195d67482SBill Paul if (entry == NULL) 69295d67482SBill Paul panic("bge_jfree: buffer not in use!"); 69395d67482SBill Paul entry->slot = i; 69495d67482SBill Paul SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 69595d67482SBill Paul SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 69695d67482SBill Paul 69795d67482SBill Paul return; 69895d67482SBill Paul } 69995d67482SBill Paul 70095d67482SBill Paul 70195d67482SBill Paul /* 70295d67482SBill Paul * Intialize a standard receive ring descriptor. 70395d67482SBill Paul */ 70495d67482SBill Paul static int 70595d67482SBill Paul bge_newbuf_std(sc, i, m) 70695d67482SBill Paul struct bge_softc *sc; 70795d67482SBill Paul int i; 70895d67482SBill Paul struct mbuf *m; 70995d67482SBill Paul { 71095d67482SBill Paul struct mbuf *m_new = NULL; 71195d67482SBill Paul struct bge_rx_bd *r; 71295d67482SBill Paul 71395d67482SBill Paul if (m == NULL) { 71495d67482SBill Paul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 71595d67482SBill Paul if (m_new == NULL) { 71695d67482SBill Paul return(ENOBUFS); 71795d67482SBill Paul } 71895d67482SBill Paul 71995d67482SBill Paul MCLGET(m_new, M_DONTWAIT); 72095d67482SBill Paul if (!(m_new->m_flags & M_EXT)) { 72195d67482SBill Paul m_freem(m_new); 72295d67482SBill Paul return(ENOBUFS); 72395d67482SBill Paul } 72495d67482SBill Paul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 72595d67482SBill Paul } else { 72695d67482SBill Paul m_new = m; 72795d67482SBill Paul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 72895d67482SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 72995d67482SBill Paul } 73095d67482SBill Paul 73195d67482SBill Paul m_adj(m_new, ETHER_ALIGN); 73295d67482SBill Paul sc->bge_cdata.bge_rx_std_chain[i] = m_new; 73395d67482SBill Paul r = &sc->bge_rdata->bge_rx_std_ring[i]; 73495d67482SBill Paul BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 73595d67482SBill Paul r->bge_flags = BGE_RXBDFLAG_END; 73695d67482SBill Paul r->bge_len = m_new->m_len; 73795d67482SBill Paul r->bge_idx = i; 73895d67482SBill Paul 73995d67482SBill Paul return(0); 74095d67482SBill Paul } 74195d67482SBill Paul 74295d67482SBill Paul /* 74395d67482SBill Paul * Initialize a jumbo receive ring descriptor. This allocates 74495d67482SBill Paul * a jumbo buffer from the pool managed internally by the driver. 74595d67482SBill Paul */ 74695d67482SBill Paul static int 74795d67482SBill Paul bge_newbuf_jumbo(sc, i, m) 74895d67482SBill Paul struct bge_softc *sc; 74995d67482SBill Paul int i; 75095d67482SBill Paul struct mbuf *m; 75195d67482SBill Paul { 75295d67482SBill Paul struct mbuf *m_new = NULL; 75395d67482SBill Paul struct bge_rx_bd *r; 75495d67482SBill Paul 75595d67482SBill Paul if (m == NULL) { 75695d67482SBill Paul caddr_t *buf = NULL; 75795d67482SBill Paul 75895d67482SBill Paul /* Allocate the mbuf. */ 75995d67482SBill Paul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 76095d67482SBill Paul if (m_new == NULL) { 76195d67482SBill Paul return(ENOBUFS); 76295d67482SBill Paul } 76395d67482SBill Paul 76495d67482SBill Paul /* Allocate the jumbo buffer */ 76595d67482SBill Paul buf = bge_jalloc(sc); 76695d67482SBill Paul if (buf == NULL) { 76795d67482SBill Paul m_freem(m_new); 76895d67482SBill Paul printf("bge%d: jumbo allocation failed " 76995d67482SBill Paul "-- packet dropped!\n", sc->bge_unit); 77095d67482SBill Paul return(ENOBUFS); 77195d67482SBill Paul } 77295d67482SBill Paul 77395d67482SBill Paul /* Attach the buffer to the mbuf. */ 77495d67482SBill Paul m_new->m_data = (void *) buf; 77595d67482SBill Paul m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 77695d67482SBill Paul MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 77795d67482SBill Paul (struct bge_softc *)sc, 0, EXT_NET_DRV); 77895d67482SBill Paul } else { 77995d67482SBill Paul m_new = m; 78095d67482SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 78195d67482SBill Paul m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 78295d67482SBill Paul } 78395d67482SBill Paul 78495d67482SBill Paul m_adj(m_new, ETHER_ALIGN); 78595d67482SBill Paul /* Set up the descriptor. */ 78695d67482SBill Paul r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 78795d67482SBill Paul sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 78895d67482SBill Paul BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 78995d67482SBill Paul r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 79095d67482SBill Paul r->bge_len = m_new->m_len; 79195d67482SBill Paul r->bge_idx = i; 79295d67482SBill Paul 79395d67482SBill Paul return(0); 79495d67482SBill Paul } 79595d67482SBill Paul 79695d67482SBill Paul /* 79795d67482SBill Paul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 79895d67482SBill Paul * that's 1MB or memory, which is a lot. For now, we fill only the first 79995d67482SBill Paul * 256 ring entries and hope that our CPU is fast enough to keep up with 80095d67482SBill Paul * the NIC. 80195d67482SBill Paul */ 80295d67482SBill Paul static int 80395d67482SBill Paul bge_init_rx_ring_std(sc) 80495d67482SBill Paul struct bge_softc *sc; 80595d67482SBill Paul { 80695d67482SBill Paul int i; 80795d67482SBill Paul 80895d67482SBill Paul for (i = 0; i < BGE_SSLOTS; i++) { 80995d67482SBill Paul if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 81095d67482SBill Paul return(ENOBUFS); 81195d67482SBill Paul }; 81295d67482SBill Paul 81395d67482SBill Paul sc->bge_std = i - 1; 81495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 81595d67482SBill Paul 81695d67482SBill Paul return(0); 81795d67482SBill Paul } 81895d67482SBill Paul 81995d67482SBill Paul static void 82095d67482SBill Paul bge_free_rx_ring_std(sc) 82195d67482SBill Paul struct bge_softc *sc; 82295d67482SBill Paul { 82395d67482SBill Paul int i; 82495d67482SBill Paul 82595d67482SBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 82695d67482SBill Paul if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 82795d67482SBill Paul m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 82895d67482SBill Paul sc->bge_cdata.bge_rx_std_chain[i] = NULL; 82995d67482SBill Paul } 83095d67482SBill Paul bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 83195d67482SBill Paul sizeof(struct bge_rx_bd)); 83295d67482SBill Paul } 83395d67482SBill Paul 83495d67482SBill Paul return; 83595d67482SBill Paul } 83695d67482SBill Paul 83795d67482SBill Paul static int 83895d67482SBill Paul bge_init_rx_ring_jumbo(sc) 83995d67482SBill Paul struct bge_softc *sc; 84095d67482SBill Paul { 84195d67482SBill Paul int i; 84295d67482SBill Paul struct bge_rcb *rcb; 84395d67482SBill Paul struct bge_rcb_opaque *rcbo; 84495d67482SBill Paul 84595d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 84695d67482SBill Paul if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 84795d67482SBill Paul return(ENOBUFS); 84895d67482SBill Paul }; 84995d67482SBill Paul 85095d67482SBill Paul sc->bge_jumbo = i - 1; 85195d67482SBill Paul 85295d67482SBill Paul rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 85395d67482SBill Paul rcbo = (struct bge_rcb_opaque *)rcb; 85495d67482SBill Paul rcb->bge_flags = 0; 85595d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 85695d67482SBill Paul 85795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 85895d67482SBill Paul 85995d67482SBill Paul return(0); 86095d67482SBill Paul } 86195d67482SBill Paul 86295d67482SBill Paul static void 86395d67482SBill Paul bge_free_rx_ring_jumbo(sc) 86495d67482SBill Paul struct bge_softc *sc; 86595d67482SBill Paul { 86695d67482SBill Paul int i; 86795d67482SBill Paul 86895d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 86995d67482SBill Paul if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 87095d67482SBill Paul m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 87195d67482SBill Paul sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 87295d67482SBill Paul } 87395d67482SBill Paul bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 87495d67482SBill Paul sizeof(struct bge_rx_bd)); 87595d67482SBill Paul } 87695d67482SBill Paul 87795d67482SBill Paul return; 87895d67482SBill Paul } 87995d67482SBill Paul 88095d67482SBill Paul static void 88195d67482SBill Paul bge_free_tx_ring(sc) 88295d67482SBill Paul struct bge_softc *sc; 88395d67482SBill Paul { 88495d67482SBill Paul int i; 88595d67482SBill Paul 88695d67482SBill Paul if (sc->bge_rdata->bge_tx_ring == NULL) 88795d67482SBill Paul return; 88895d67482SBill Paul 88995d67482SBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 89095d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 89195d67482SBill Paul m_freem(sc->bge_cdata.bge_tx_chain[i]); 89295d67482SBill Paul sc->bge_cdata.bge_tx_chain[i] = NULL; 89395d67482SBill Paul } 89495d67482SBill Paul bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 89595d67482SBill Paul sizeof(struct bge_tx_bd)); 89695d67482SBill Paul } 89795d67482SBill Paul 89895d67482SBill Paul return; 89995d67482SBill Paul } 90095d67482SBill Paul 90195d67482SBill Paul static int 90295d67482SBill Paul bge_init_tx_ring(sc) 90395d67482SBill Paul struct bge_softc *sc; 90495d67482SBill Paul { 90595d67482SBill Paul sc->bge_txcnt = 0; 90695d67482SBill Paul sc->bge_tx_saved_considx = 0; 90795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 90895d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 90995d67482SBill Paul 91095d67482SBill Paul return(0); 91195d67482SBill Paul } 91295d67482SBill Paul 91395d67482SBill Paul #define BGE_POLY 0xEDB88320 91495d67482SBill Paul 91595d67482SBill Paul static u_int32_t 91695d67482SBill Paul bge_crc(addr) 91795d67482SBill Paul caddr_t addr; 91895d67482SBill Paul { 91995d67482SBill Paul u_int32_t idx, bit, data, crc; 92095d67482SBill Paul 92195d67482SBill Paul /* Compute CRC for the address value. */ 92295d67482SBill Paul crc = 0xFFFFFFFF; /* initial value */ 92395d67482SBill Paul 92495d67482SBill Paul for (idx = 0; idx < 6; idx++) { 92595d67482SBill Paul for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 92695d67482SBill Paul crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 92795d67482SBill Paul } 92895d67482SBill Paul 92995d67482SBill Paul return(crc & 0x7F); 93095d67482SBill Paul } 93195d67482SBill Paul 93295d67482SBill Paul static void 93395d67482SBill Paul bge_setmulti(sc) 93495d67482SBill Paul struct bge_softc *sc; 93595d67482SBill Paul { 93695d67482SBill Paul struct ifnet *ifp; 93795d67482SBill Paul struct ifmultiaddr *ifma; 93895d67482SBill Paul u_int32_t hashes[4] = { 0, 0, 0, 0 }; 93995d67482SBill Paul int h, i; 94095d67482SBill Paul 94195d67482SBill Paul ifp = &sc->arpcom.ac_if; 94295d67482SBill Paul 94395d67482SBill Paul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 94495d67482SBill Paul for (i = 0; i < 4; i++) 94595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 94695d67482SBill Paul return; 94795d67482SBill Paul } 94895d67482SBill Paul 94995d67482SBill Paul /* First, zot all the existing filters. */ 95095d67482SBill Paul for (i = 0; i < 4; i++) 95195d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 95295d67482SBill Paul 95395d67482SBill Paul /* Now program new ones. */ 95495d67482SBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 95595d67482SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 95695d67482SBill Paul continue; 95795d67482SBill Paul h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 95895d67482SBill Paul hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 95995d67482SBill Paul } 96095d67482SBill Paul 96195d67482SBill Paul for (i = 0; i < 4; i++) 96295d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 96395d67482SBill Paul 96495d67482SBill Paul return; 96595d67482SBill Paul } 96695d67482SBill Paul 96795d67482SBill Paul /* 96895d67482SBill Paul * Do endian, PCI and DMA initialization. Also check the on-board ROM 96995d67482SBill Paul * self-test results. 97095d67482SBill Paul */ 97195d67482SBill Paul static int 97295d67482SBill Paul bge_chipinit(sc) 97395d67482SBill Paul struct bge_softc *sc; 97495d67482SBill Paul { 97595d67482SBill Paul u_int32_t cachesize; 97695d67482SBill Paul int i; 97795d67482SBill Paul 97895d67482SBill Paul /* Set endianness before we access any non-PCI registers. */ 97995d67482SBill Paul #if BYTE_ORDER == BIG_ENDIAN 98095d67482SBill Paul pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 98195d67482SBill Paul BGE_BIGENDIAN_INIT, 4); 98295d67482SBill Paul #else 98395d67482SBill Paul pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 98495d67482SBill Paul BGE_LITTLEENDIAN_INIT, 4); 98595d67482SBill Paul #endif 98695d67482SBill Paul 98795d67482SBill Paul /* 98895d67482SBill Paul * Check the 'ROM failed' bit on the RX CPU to see if 98995d67482SBill Paul * self-tests passed. 99095d67482SBill Paul */ 99195d67482SBill Paul if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 99295d67482SBill Paul printf("bge%d: RX CPU self-diagnostics failed!\n", 99395d67482SBill Paul sc->bge_unit); 99495d67482SBill Paul return(ENODEV); 99595d67482SBill Paul } 99695d67482SBill Paul 99795d67482SBill Paul /* Clear the MAC control register */ 99895d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 99995d67482SBill Paul 100095d67482SBill Paul /* 100195d67482SBill Paul * Clear the MAC statistics block in the NIC's 100295d67482SBill Paul * internal memory. 100395d67482SBill Paul */ 100495d67482SBill Paul for (i = BGE_STATS_BLOCK; 100595d67482SBill Paul i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 100695d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 100795d67482SBill Paul 100895d67482SBill Paul for (i = BGE_STATUS_BLOCK; 100995d67482SBill Paul i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 101095d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 101195d67482SBill Paul 101295d67482SBill Paul /* Set up the PCI DMA control register. */ 101395d67482SBill Paul pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 101495d67482SBill Paul BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4); 101595d67482SBill Paul 101695d67482SBill Paul /* 101795d67482SBill Paul * Set up general mode register. 101895d67482SBill Paul */ 101995d67482SBill Paul CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 102095d67482SBill Paul BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 102195d67482SBill Paul BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 10220189c944SBill Paul BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 10230189c944SBill Paul BGE_MODECTL_RX_NO_PHDR_CSUM); 102495d67482SBill Paul 102595d67482SBill Paul /* Get cache line size. */ 102695d67482SBill Paul cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); 102795d67482SBill Paul 102895d67482SBill Paul /* 102995d67482SBill Paul * Avoid violating PCI spec on certain chip revs. 103095d67482SBill Paul */ 103195d67482SBill Paul if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { 103295d67482SBill Paul switch(cachesize) { 103395d67482SBill Paul case 1: 103495d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 103595d67482SBill Paul BGE_PCI_WRITE_BNDRY_16BYTES, 4); 103695d67482SBill Paul break; 103795d67482SBill Paul case 2: 103895d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 103995d67482SBill Paul BGE_PCI_WRITE_BNDRY_32BYTES, 4); 104095d67482SBill Paul break; 104195d67482SBill Paul case 4: 104295d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 104395d67482SBill Paul BGE_PCI_WRITE_BNDRY_64BYTES, 4); 104495d67482SBill Paul break; 104595d67482SBill Paul case 8: 104695d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 104795d67482SBill Paul BGE_PCI_WRITE_BNDRY_128BYTES, 4); 104895d67482SBill Paul break; 104995d67482SBill Paul case 16: 105095d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 105195d67482SBill Paul BGE_PCI_WRITE_BNDRY_256BYTES, 4); 105295d67482SBill Paul break; 105395d67482SBill Paul case 32: 105495d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 105595d67482SBill Paul BGE_PCI_WRITE_BNDRY_512BYTES, 4); 105695d67482SBill Paul break; 105795d67482SBill Paul case 64: 105895d67482SBill Paul PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 105995d67482SBill Paul BGE_PCI_WRITE_BNDRY_1024BYTES, 4); 106095d67482SBill Paul break; 106195d67482SBill Paul default: 106295d67482SBill Paul /* Disable PCI memory write and invalidate. */ 106395d67482SBill Paul if (bootverbose) 106495d67482SBill Paul printf("bge%d: cache line size %d not " 106595d67482SBill Paul "supported; disabling PCI MWI\n", 106695d67482SBill Paul sc->bge_unit, cachesize); 106795d67482SBill Paul PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 106895d67482SBill Paul PCIM_CMD_MWIEN, 4); 106995d67482SBill Paul break; 107095d67482SBill Paul } 107195d67482SBill Paul } 107295d67482SBill Paul 107395d67482SBill Paul #ifdef __brokenalpha__ 107495d67482SBill Paul /* 107595d67482SBill Paul * Must insure that we do not cross an 8K (bytes) boundary 107695d67482SBill Paul * for DMA reads. Our highest limit is 1K bytes. This is a 107795d67482SBill Paul * restriction on some ALPHA platforms with early revision 107895d67482SBill Paul * 21174 PCI chipsets, such as the AlphaPC 164lx 107995d67482SBill Paul */ 108095d67482SBill Paul PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 108195d67482SBill Paul #endif 108295d67482SBill Paul 108395d67482SBill Paul /* Set the timer prescaler (always 66Mhz) */ 108495d67482SBill Paul CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 108595d67482SBill Paul 108695d67482SBill Paul return(0); 108795d67482SBill Paul } 108895d67482SBill Paul 108995d67482SBill Paul static int 109095d67482SBill Paul bge_blockinit(sc) 109195d67482SBill Paul struct bge_softc *sc; 109295d67482SBill Paul { 109395d67482SBill Paul struct bge_rcb *rcb; 109495d67482SBill Paul struct bge_rcb_opaque *rcbo; 109595d67482SBill Paul int i; 109695d67482SBill Paul 109795d67482SBill Paul /* 109895d67482SBill Paul * Initialize the memory window pointer register so that 109995d67482SBill Paul * we can access the first 32K of internal NIC RAM. This will 110095d67482SBill Paul * allow us to set up the TX send ring RCBs and the RX return 110195d67482SBill Paul * ring RCBs, plus other things which live in NIC memory. 110295d67482SBill Paul */ 110395d67482SBill Paul CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 110495d67482SBill Paul 110595d67482SBill Paul /* Configure mbuf memory pool */ 110695d67482SBill Paul if (sc->bge_extram) { 110795d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 110895d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 110995d67482SBill Paul } else { 111095d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 111195d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 111295d67482SBill Paul } 111395d67482SBill Paul 111495d67482SBill Paul /* Configure DMA resource pool */ 111595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 111695d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 111795d67482SBill Paul 111895d67482SBill Paul /* Configure mbuf pool watermarks */ 111995d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 112095d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 112195d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 112295d67482SBill Paul 112395d67482SBill Paul /* Configure DMA resource watermarks */ 112495d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 112595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 112695d67482SBill Paul 112795d67482SBill Paul /* Enable buffer manager */ 112895d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MODE, 112995d67482SBill Paul BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 113095d67482SBill Paul 113195d67482SBill Paul /* Poll for buffer manager start indication */ 113295d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 113395d67482SBill Paul if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 113495d67482SBill Paul break; 113595d67482SBill Paul DELAY(10); 113695d67482SBill Paul } 113795d67482SBill Paul 113895d67482SBill Paul if (i == BGE_TIMEOUT) { 113995d67482SBill Paul printf("bge%d: buffer manager failed to start\n", 114095d67482SBill Paul sc->bge_unit); 114195d67482SBill Paul return(ENXIO); 114295d67482SBill Paul } 114395d67482SBill Paul 114495d67482SBill Paul /* Enable flow-through queues */ 114595d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 114695d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 114795d67482SBill Paul 114895d67482SBill Paul /* Wait until queue initialization is complete */ 114995d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 115095d67482SBill Paul if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 115195d67482SBill Paul break; 115295d67482SBill Paul DELAY(10); 115395d67482SBill Paul } 115495d67482SBill Paul 115595d67482SBill Paul if (i == BGE_TIMEOUT) { 115695d67482SBill Paul printf("bge%d: flow-through queue init failed\n", 115795d67482SBill Paul sc->bge_unit); 115895d67482SBill Paul return(ENXIO); 115995d67482SBill Paul } 116095d67482SBill Paul 116195d67482SBill Paul /* Initialize the standard RX ring control block */ 116295d67482SBill Paul rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 116395d67482SBill Paul BGE_HOSTADDR(rcb->bge_hostaddr) = 116495d67482SBill Paul vtophys(&sc->bge_rdata->bge_rx_std_ring); 116595d67482SBill Paul rcb->bge_max_len = BGE_MAX_FRAMELEN; 116695d67482SBill Paul if (sc->bge_extram) 116795d67482SBill Paul rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 116895d67482SBill Paul else 116995d67482SBill Paul rcb->bge_nicaddr = BGE_STD_RX_RINGS; 117095d67482SBill Paul rcb->bge_flags = 0; 117195d67482SBill Paul rcbo = (struct bge_rcb_opaque *)rcb; 117295d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 117395d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 117495d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 117595d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 117695d67482SBill Paul 117795d67482SBill Paul /* 117895d67482SBill Paul * Initialize the jumbo RX ring control block 117995d67482SBill Paul * We set the 'ring disabled' bit in the flags 118095d67482SBill Paul * field until we're actually ready to start 118195d67482SBill Paul * using this ring (i.e. once we set the MTU 118295d67482SBill Paul * high enough to require it). 118395d67482SBill Paul */ 118495d67482SBill Paul rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 118595d67482SBill Paul BGE_HOSTADDR(rcb->bge_hostaddr) = 118695d67482SBill Paul vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 118795d67482SBill Paul rcb->bge_max_len = BGE_MAX_FRAMELEN; 118895d67482SBill Paul if (sc->bge_extram) 118995d67482SBill Paul rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 119095d67482SBill Paul else 119195d67482SBill Paul rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 119295d67482SBill Paul rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 119395d67482SBill Paul 119495d67482SBill Paul rcbo = (struct bge_rcb_opaque *)rcb; 119595d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 119695d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 119795d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 119895d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 119995d67482SBill Paul 120095d67482SBill Paul /* Set up dummy disabled mini ring RCB */ 120195d67482SBill Paul rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 120295d67482SBill Paul rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 120395d67482SBill Paul rcbo = (struct bge_rcb_opaque *)rcb; 120495d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 120595d67482SBill Paul 120695d67482SBill Paul /* 120795d67482SBill Paul * Set the BD ring replentish thresholds. The recommended 120895d67482SBill Paul * values are 1/8th the number of descriptors allocated to 120995d67482SBill Paul * each ring. 121095d67482SBill Paul */ 121195d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 121295d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 121395d67482SBill Paul 121495d67482SBill Paul /* 121595d67482SBill Paul * Disable all unused send rings by setting the 'ring disabled' 121695d67482SBill Paul * bit in the flags field of all the TX send ring control blocks. 121795d67482SBill Paul * These are located in NIC memory. 121895d67482SBill Paul */ 121995d67482SBill Paul rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 122095d67482SBill Paul BGE_SEND_RING_RCB); 122195d67482SBill Paul for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 122295d67482SBill Paul rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 122395d67482SBill Paul rcb->bge_max_len = 0; 122495d67482SBill Paul rcb->bge_nicaddr = 0; 122595d67482SBill Paul rcb++; 122695d67482SBill Paul } 122795d67482SBill Paul 122895d67482SBill Paul /* Configure TX RCB 0 (we use only the first ring) */ 122995d67482SBill Paul rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 123095d67482SBill Paul BGE_SEND_RING_RCB); 123195d67482SBill Paul rcb->bge_hostaddr.bge_addr_hi = 0; 123295d67482SBill Paul BGE_HOSTADDR(rcb->bge_hostaddr) = 123395d67482SBill Paul vtophys(&sc->bge_rdata->bge_tx_ring); 123495d67482SBill Paul rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 123595d67482SBill Paul rcb->bge_max_len = BGE_TX_RING_CNT; 123695d67482SBill Paul rcb->bge_flags = 0; 123795d67482SBill Paul 123895d67482SBill Paul /* Disable all unused RX return rings */ 123995d67482SBill Paul rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 124095d67482SBill Paul BGE_RX_RETURN_RING_RCB); 124195d67482SBill Paul for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 124295d67482SBill Paul rcb->bge_hostaddr.bge_addr_hi = 0; 124395d67482SBill Paul rcb->bge_hostaddr.bge_addr_lo = 0; 124495d67482SBill Paul rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 124595d67482SBill Paul rcb->bge_max_len = BGE_RETURN_RING_CNT; 124695d67482SBill Paul rcb->bge_nicaddr = 0; 124795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 124895d67482SBill Paul (i * (sizeof(u_int64_t))), 0); 124995d67482SBill Paul rcb++; 125095d67482SBill Paul } 125195d67482SBill Paul 125295d67482SBill Paul /* Initialize RX ring indexes */ 125395d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 125495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 125595d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 125695d67482SBill Paul 125795d67482SBill Paul /* 125895d67482SBill Paul * Set up RX return ring 0 125995d67482SBill Paul * Note that the NIC address for RX return rings is 0x00000000. 126095d67482SBill Paul * The return rings live entirely within the host, so the 126195d67482SBill Paul * nicaddr field in the RCB isn't used. 126295d67482SBill Paul */ 126395d67482SBill Paul rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 126495d67482SBill Paul BGE_RX_RETURN_RING_RCB); 126595d67482SBill Paul rcb->bge_hostaddr.bge_addr_hi = 0; 126695d67482SBill Paul BGE_HOSTADDR(rcb->bge_hostaddr) = 126795d67482SBill Paul vtophys(&sc->bge_rdata->bge_rx_return_ring); 126895d67482SBill Paul rcb->bge_nicaddr = 0x00000000; 126995d67482SBill Paul rcb->bge_max_len = BGE_RETURN_RING_CNT; 127095d67482SBill Paul rcb->bge_flags = 0; 127195d67482SBill Paul 127295d67482SBill Paul /* Set random backoff seed for TX */ 127395d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 127495d67482SBill Paul sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 127595d67482SBill Paul sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 127695d67482SBill Paul sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 127795d67482SBill Paul BGE_TX_BACKOFF_SEED_MASK); 127895d67482SBill Paul 127995d67482SBill Paul /* Set inter-packet gap */ 128095d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 128195d67482SBill Paul 128295d67482SBill Paul /* 128395d67482SBill Paul * Specify which ring to use for packets that don't match 128495d67482SBill Paul * any RX rules. 128595d67482SBill Paul */ 128695d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 128795d67482SBill Paul 128895d67482SBill Paul /* 128995d67482SBill Paul * Configure number of RX lists. One interrupt distribution 129095d67482SBill Paul * list, sixteen active lists, one bad frames class. 129195d67482SBill Paul */ 129295d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 129395d67482SBill Paul 129495d67482SBill Paul /* Inialize RX list placement stats mask. */ 129595d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 129695d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 129795d67482SBill Paul 129895d67482SBill Paul /* Disable host coalescing until we get it set up */ 129995d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 130095d67482SBill Paul 130195d67482SBill Paul /* Poll to make sure it's shut down. */ 130295d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 130395d67482SBill Paul if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 130495d67482SBill Paul break; 130595d67482SBill Paul DELAY(10); 130695d67482SBill Paul } 130795d67482SBill Paul 130895d67482SBill Paul if (i == BGE_TIMEOUT) { 130995d67482SBill Paul printf("bge%d: host coalescing engine failed to idle\n", 131095d67482SBill Paul sc->bge_unit); 131195d67482SBill Paul return(ENXIO); 131295d67482SBill Paul } 131395d67482SBill Paul 131495d67482SBill Paul /* Set up host coalescing defaults */ 131595d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 131695d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 131795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 131895d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 131995d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 132095d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 132195d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 132295d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 132395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 132495d67482SBill Paul 132595d67482SBill Paul /* Set up address of statistics block */ 132695d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 132795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 132895d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 132995d67482SBill Paul vtophys(&sc->bge_rdata->bge_info.bge_stats)); 133095d67482SBill Paul 133195d67482SBill Paul /* Set up address of status block */ 133295d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 133395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 133495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 133595d67482SBill Paul vtophys(&sc->bge_rdata->bge_status_block)); 133695d67482SBill Paul sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 133795d67482SBill Paul sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 133895d67482SBill Paul 133995d67482SBill Paul /* Turn on host coalescing state machine */ 134095d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 134195d67482SBill Paul 134295d67482SBill Paul /* Turn on RX BD completion state machine and enable attentions */ 134395d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDC_MODE, 134495d67482SBill Paul BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 134595d67482SBill Paul 134695d67482SBill Paul /* Turn on RX list placement state machine */ 134795d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 134895d67482SBill Paul 134995d67482SBill Paul /* Turn on RX list selector state machine. */ 135095d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 135195d67482SBill Paul 135295d67482SBill Paul /* Turn on DMA, clear stats */ 135395d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 135495d67482SBill Paul BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 135595d67482SBill Paul BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 135695d67482SBill Paul BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 135795d67482SBill Paul (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 135895d67482SBill Paul 135995d67482SBill Paul /* Set misc. local control, enable interrupts on attentions */ 136095d67482SBill Paul CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 136195d67482SBill Paul 136295d67482SBill Paul #ifdef notdef 136395d67482SBill Paul /* Assert GPIO pins for PHY reset */ 136495d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 136595d67482SBill Paul BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 136695d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 136795d67482SBill Paul BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 136895d67482SBill Paul #endif 136995d67482SBill Paul 137095d67482SBill Paul /* Turn on DMA completion state machine */ 137195d67482SBill Paul CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 137295d67482SBill Paul 137395d67482SBill Paul /* Turn on write DMA state machine */ 137495d67482SBill Paul CSR_WRITE_4(sc, BGE_WDMA_MODE, 137595d67482SBill Paul BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 137695d67482SBill Paul 137795d67482SBill Paul /* Turn on read DMA state machine */ 137895d67482SBill Paul CSR_WRITE_4(sc, BGE_RDMA_MODE, 137995d67482SBill Paul BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 138095d67482SBill Paul 138195d67482SBill Paul /* Turn on RX data completion state machine */ 138295d67482SBill Paul CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 138395d67482SBill Paul 138495d67482SBill Paul /* Turn on RX BD initiator state machine */ 138595d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 138695d67482SBill Paul 138795d67482SBill Paul /* Turn on RX data and RX BD initiator state machine */ 138895d67482SBill Paul CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 138995d67482SBill Paul 139095d67482SBill Paul /* Turn on Mbuf cluster free state machine */ 139195d67482SBill Paul CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 139295d67482SBill Paul 139395d67482SBill Paul /* Turn on send BD completion state machine */ 139495d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 139595d67482SBill Paul 139695d67482SBill Paul /* Turn on send data completion state machine */ 139795d67482SBill Paul CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 139895d67482SBill Paul 139995d67482SBill Paul /* Turn on send data initiator state machine */ 140095d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 140195d67482SBill Paul 140295d67482SBill Paul /* Turn on send BD initiator state machine */ 140395d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 140495d67482SBill Paul 140595d67482SBill Paul /* Turn on send BD selector state machine */ 140695d67482SBill Paul CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 140795d67482SBill Paul 140895d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 140995d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 141095d67482SBill Paul BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 141195d67482SBill Paul 141295d67482SBill Paul /* init LED register */ 141395d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 141495d67482SBill Paul 141595d67482SBill Paul /* ack/clear link change events */ 141695d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 141795d67482SBill Paul BGE_MACSTAT_CFG_CHANGED); 141895d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, 0); 141995d67482SBill Paul 142095d67482SBill Paul /* Enable PHY auto polling (for MII/GMII only) */ 142195d67482SBill Paul if (sc->bge_tbi) { 142295d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 142395d67482SBill Paul } else 142495d67482SBill Paul BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 142595d67482SBill Paul 142695d67482SBill Paul /* Enable link state change attentions. */ 142795d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 142895d67482SBill Paul 142995d67482SBill Paul return(0); 143095d67482SBill Paul } 143195d67482SBill Paul 143295d67482SBill Paul /* 143395d67482SBill Paul * Probe for a Broadcom chip. Check the PCI vendor and device IDs 143495d67482SBill Paul * against our list and return its name if we find a match. Note 143595d67482SBill Paul * that since the Broadcom controller contains VPD support, we 143695d67482SBill Paul * can get the device name string from the controller itself instead 143795d67482SBill Paul * of the compiled-in string. This is a little slow, but it guarantees 143895d67482SBill Paul * we'll always announce the right product name. 143995d67482SBill Paul */ 144095d67482SBill Paul static int 144195d67482SBill Paul bge_probe(dev) 144295d67482SBill Paul device_t dev; 144395d67482SBill Paul { 144495d67482SBill Paul struct bge_type *t; 144595d67482SBill Paul struct bge_softc *sc; 144695d67482SBill Paul 144795d67482SBill Paul t = bge_devs; 144895d67482SBill Paul 144995d67482SBill Paul sc = device_get_softc(dev); 145095d67482SBill Paul bzero(sc, sizeof(struct bge_softc)); 145195d67482SBill Paul sc->bge_unit = device_get_unit(dev); 145295d67482SBill Paul sc->bge_dev = dev; 145395d67482SBill Paul 145495d67482SBill Paul while(t->bge_name != NULL) { 145595d67482SBill Paul if ((pci_get_vendor(dev) == t->bge_vid) && 145695d67482SBill Paul (pci_get_device(dev) == t->bge_did)) { 145795d67482SBill Paul #ifdef notdef 145895d67482SBill Paul bge_vpd_read(sc); 145995d67482SBill Paul device_set_desc(dev, sc->bge_vpd_prodname); 146095d67482SBill Paul #endif 146195d67482SBill Paul device_set_desc(dev, t->bge_name); 146295d67482SBill Paul return(0); 146395d67482SBill Paul } 146495d67482SBill Paul t++; 146595d67482SBill Paul } 146695d67482SBill Paul 146795d67482SBill Paul return(ENXIO); 146895d67482SBill Paul } 146995d67482SBill Paul 147095d67482SBill Paul static int 147195d67482SBill Paul bge_attach(dev) 147295d67482SBill Paul device_t dev; 147395d67482SBill Paul { 147495d67482SBill Paul int s; 147595d67482SBill Paul u_int32_t command; 147695d67482SBill Paul struct ifnet *ifp; 147795d67482SBill Paul struct bge_softc *sc; 147895d67482SBill Paul int unit, error = 0, rid; 147995d67482SBill Paul 148095d67482SBill Paul s = splimp(); 148195d67482SBill Paul 148295d67482SBill Paul sc = device_get_softc(dev); 148395d67482SBill Paul unit = device_get_unit(dev); 148495d67482SBill Paul sc->bge_dev = dev; 148595d67482SBill Paul sc->bge_unit = unit; 148695d67482SBill Paul 148795d67482SBill Paul /* 148895d67482SBill Paul * Map control/status registers. 148995d67482SBill Paul */ 149095d67482SBill Paul pci_enable_busmaster(dev); 149195d67482SBill Paul pci_enable_io(dev, SYS_RES_MEMORY); 149295d67482SBill Paul command = pci_read_config(dev, PCIR_COMMAND, 4); 149395d67482SBill Paul 149495d67482SBill Paul if (!(command & PCIM_CMD_MEMEN)) { 149595d67482SBill Paul printf("bge%d: failed to enable memory mapping!\n", unit); 149695d67482SBill Paul error = ENXIO; 149795d67482SBill Paul goto fail; 149895d67482SBill Paul } 149995d67482SBill Paul 150095d67482SBill Paul rid = BGE_PCI_BAR0; 150195d67482SBill Paul sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 150295d67482SBill Paul 0, ~0, 1, RF_ACTIVE); 150395d67482SBill Paul 150495d67482SBill Paul if (sc->bge_res == NULL) { 150595d67482SBill Paul printf ("bge%d: couldn't map memory\n", unit); 150695d67482SBill Paul error = ENXIO; 150795d67482SBill Paul goto fail; 150895d67482SBill Paul } 150995d67482SBill Paul 151095d67482SBill Paul sc->bge_btag = rman_get_bustag(sc->bge_res); 151195d67482SBill Paul sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 151295d67482SBill Paul sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 151395d67482SBill Paul 151495d67482SBill Paul /* 151595d67482SBill Paul * XXX FIXME: rman_get_virtual() on the alpha is currently 151695d67482SBill Paul * broken and returns a physical address instead of a kernel 151795d67482SBill Paul * virtual address. Consequently, we need to do a little 151895d67482SBill Paul * extra mangling of the vhandle on the alpha. This should 151995d67482SBill Paul * eventually be fixed! The whole idea here is to get rid 152095d67482SBill Paul * of platform dependencies. 152195d67482SBill Paul */ 152295d67482SBill Paul #ifdef __alpha__ 152395d67482SBill Paul if (pci_cvt_to_bwx(sc->bge_vhandle)) 152495d67482SBill Paul sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 152595d67482SBill Paul else 152695d67482SBill Paul sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 152795d67482SBill Paul sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 152895d67482SBill Paul #endif 152995d67482SBill Paul 153095d67482SBill Paul /* Allocate interrupt */ 153195d67482SBill Paul rid = 0; 153295d67482SBill Paul 153395d67482SBill Paul sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 153495d67482SBill Paul RF_SHAREABLE | RF_ACTIVE); 153595d67482SBill Paul 153695d67482SBill Paul if (sc->bge_irq == NULL) { 153795d67482SBill Paul printf("bge%d: couldn't map interrupt\n", unit); 153895d67482SBill Paul error = ENXIO; 153995d67482SBill Paul goto fail; 154095d67482SBill Paul } 154195d67482SBill Paul 154295d67482SBill Paul error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 154395d67482SBill Paul bge_intr, sc, &sc->bge_intrhand); 154495d67482SBill Paul 154595d67482SBill Paul if (error) { 154695d67482SBill Paul bge_release_resources(sc); 154795d67482SBill Paul printf("bge%d: couldn't set up irq\n", unit); 154895d67482SBill Paul goto fail; 154995d67482SBill Paul } 155095d67482SBill Paul 155195d67482SBill Paul sc->bge_unit = unit; 155295d67482SBill Paul 155395d67482SBill Paul /* Try to reset the chip. */ 155495d67482SBill Paul bge_reset(sc); 155595d67482SBill Paul 155695d67482SBill Paul if (bge_chipinit(sc)) { 155795d67482SBill Paul printf("bge%d: chip initialization failed\n", sc->bge_unit); 155895d67482SBill Paul bge_release_resources(sc); 155995d67482SBill Paul error = ENXIO; 156095d67482SBill Paul goto fail; 156195d67482SBill Paul } 156295d67482SBill Paul 156395d67482SBill Paul /* 156495d67482SBill Paul * Get station address from the EEPROM. 156595d67482SBill Paul */ 156695d67482SBill Paul if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 156795d67482SBill Paul BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 156895d67482SBill Paul printf("bge%d: failed to read station address\n", unit); 156995d67482SBill Paul bge_release_resources(sc); 157095d67482SBill Paul error = ENXIO; 157195d67482SBill Paul goto fail; 157295d67482SBill Paul } 157395d67482SBill Paul 157495d67482SBill Paul /* 157595d67482SBill Paul * A Broadcom chip was detected. Inform the world. 157695d67482SBill Paul */ 157795d67482SBill Paul printf("bge%d: Ethernet address: %6D\n", unit, 157895d67482SBill Paul sc->arpcom.ac_enaddr, ":"); 157995d67482SBill Paul 158095d67482SBill Paul /* Allocate the general information block and ring buffers. */ 158195d67482SBill Paul sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 158295d67482SBill Paul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 158395d67482SBill Paul 158495d67482SBill Paul if (sc->bge_rdata == NULL) { 158595d67482SBill Paul bge_release_resources(sc); 158695d67482SBill Paul error = ENXIO; 158795d67482SBill Paul printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 158895d67482SBill Paul goto fail; 158995d67482SBill Paul } 159095d67482SBill Paul 159195d67482SBill Paul bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 159295d67482SBill Paul 159395d67482SBill Paul /* Try to allocate memory for jumbo buffers. */ 159495d67482SBill Paul if (bge_alloc_jumbo_mem(sc)) { 159595d67482SBill Paul printf("bge%d: jumbo buffer allocation " 159695d67482SBill Paul "failed\n", sc->bge_unit); 159795d67482SBill Paul bge_release_resources(sc); 159895d67482SBill Paul error = ENXIO; 159995d67482SBill Paul goto fail; 160095d67482SBill Paul } 160195d67482SBill Paul 160295d67482SBill Paul /* Set default tuneable values. */ 160395d67482SBill Paul sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 160495d67482SBill Paul sc->bge_rx_coal_ticks = 150; 160595d67482SBill Paul sc->bge_tx_coal_ticks = 150; 160695d67482SBill Paul sc->bge_rx_max_coal_bds = 64; 160795d67482SBill Paul sc->bge_tx_max_coal_bds = 128; 160895d67482SBill Paul 160995d67482SBill Paul /* Set up ifnet structure */ 161095d67482SBill Paul ifp = &sc->arpcom.ac_if; 161195d67482SBill Paul ifp->if_softc = sc; 161295d67482SBill Paul ifp->if_unit = sc->bge_unit; 161395d67482SBill Paul ifp->if_name = "bge"; 161495d67482SBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 161595d67482SBill Paul ifp->if_ioctl = bge_ioctl; 161695d67482SBill Paul ifp->if_output = ether_output; 161795d67482SBill Paul ifp->if_start = bge_start; 161895d67482SBill Paul ifp->if_watchdog = bge_watchdog; 161995d67482SBill Paul ifp->if_init = bge_init; 162095d67482SBill Paul ifp->if_mtu = ETHERMTU; 162195d67482SBill Paul ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 162295d67482SBill Paul ifp->if_hwassist = BGE_CSUM_FEATURES; 162395d67482SBill Paul ifp->if_capabilities = IFCAP_HWCSUM; 162495d67482SBill Paul ifp->if_capenable = ifp->if_capabilities; 162595d67482SBill Paul 162695d67482SBill Paul /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 162795d67482SBill Paul if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 162895d67482SBill Paul sc->bge_tbi = 1; 162995d67482SBill Paul 163095d67482SBill Paul if (sc->bge_tbi) { 163195d67482SBill Paul ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 163295d67482SBill Paul bge_ifmedia_upd, bge_ifmedia_sts); 163395d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 163495d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, 163595d67482SBill Paul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 163695d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 163795d67482SBill Paul ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 163895d67482SBill Paul } else { 163995d67482SBill Paul /* 164095d67482SBill Paul * Do transceiver setup. 164195d67482SBill Paul */ 164295d67482SBill Paul if (mii_phy_probe(dev, &sc->bge_miibus, 164395d67482SBill Paul bge_ifmedia_upd, bge_ifmedia_sts)) { 164495d67482SBill Paul printf("bge%d: MII without any PHY!\n", sc->bge_unit); 164595d67482SBill Paul bge_release_resources(sc); 164695d67482SBill Paul bge_free_jumbo_mem(sc); 164795d67482SBill Paul error = ENXIO; 164895d67482SBill Paul goto fail; 164995d67482SBill Paul } 165095d67482SBill Paul } 165195d67482SBill Paul 165295d67482SBill Paul /* 165395d67482SBill Paul * Call MI attach routine. 165495d67482SBill Paul */ 165595d67482SBill Paul ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 165695d67482SBill Paul callout_handle_init(&sc->bge_stat_ch); 165795d67482SBill Paul 165895d67482SBill Paul fail: 165995d67482SBill Paul splx(s); 166095d67482SBill Paul 166195d67482SBill Paul return(error); 166295d67482SBill Paul } 166395d67482SBill Paul 166495d67482SBill Paul static int 166595d67482SBill Paul bge_detach(dev) 166695d67482SBill Paul device_t dev; 166795d67482SBill Paul { 166895d67482SBill Paul struct bge_softc *sc; 166995d67482SBill Paul struct ifnet *ifp; 167095d67482SBill Paul int s; 167195d67482SBill Paul 167295d67482SBill Paul s = splimp(); 167395d67482SBill Paul 167495d67482SBill Paul sc = device_get_softc(dev); 167595d67482SBill Paul ifp = &sc->arpcom.ac_if; 167695d67482SBill Paul 167795d67482SBill Paul ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 167895d67482SBill Paul bge_stop(sc); 167995d67482SBill Paul bge_reset(sc); 168095d67482SBill Paul 168195d67482SBill Paul if (sc->bge_tbi) { 168295d67482SBill Paul ifmedia_removeall(&sc->bge_ifmedia); 168395d67482SBill Paul } else { 168495d67482SBill Paul bus_generic_detach(dev); 168595d67482SBill Paul device_delete_child(dev, sc->bge_miibus); 168695d67482SBill Paul } 168795d67482SBill Paul 168895d67482SBill Paul bge_release_resources(sc); 168995d67482SBill Paul bge_free_jumbo_mem(sc); 169095d67482SBill Paul 169195d67482SBill Paul splx(s); 169295d67482SBill Paul 169395d67482SBill Paul return(0); 169495d67482SBill Paul } 169595d67482SBill Paul 169695d67482SBill Paul static void 169795d67482SBill Paul bge_release_resources(sc) 169895d67482SBill Paul struct bge_softc *sc; 169995d67482SBill Paul { 170095d67482SBill Paul device_t dev; 170195d67482SBill Paul 170295d67482SBill Paul dev = sc->bge_dev; 170395d67482SBill Paul 170495d67482SBill Paul if (sc->bge_vpd_prodname != NULL) 170595d67482SBill Paul free(sc->bge_vpd_prodname, M_DEVBUF); 170695d67482SBill Paul 170795d67482SBill Paul if (sc->bge_vpd_readonly != NULL) 170895d67482SBill Paul free(sc->bge_vpd_readonly, M_DEVBUF); 170995d67482SBill Paul 171095d67482SBill Paul if (sc->bge_intrhand != NULL) 171195d67482SBill Paul bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 171295d67482SBill Paul 171395d67482SBill Paul if (sc->bge_irq != NULL) 171495d67482SBill Paul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 171595d67482SBill Paul 171695d67482SBill Paul if (sc->bge_res != NULL) 171795d67482SBill Paul bus_release_resource(dev, SYS_RES_MEMORY, 171895d67482SBill Paul BGE_PCI_BAR0, sc->bge_res); 171995d67482SBill Paul 172095d67482SBill Paul if (sc->bge_rdata != NULL) 172195d67482SBill Paul contigfree(sc->bge_rdata, 172295d67482SBill Paul sizeof(struct bge_ring_data), M_DEVBUF); 172395d67482SBill Paul 172495d67482SBill Paul return; 172595d67482SBill Paul } 172695d67482SBill Paul 172795d67482SBill Paul static void 172895d67482SBill Paul bge_reset(sc) 172995d67482SBill Paul struct bge_softc *sc; 173095d67482SBill Paul { 173195d67482SBill Paul device_t dev; 173295d67482SBill Paul u_int32_t cachesize, command, pcistate; 173395d67482SBill Paul int i, val = 0; 173495d67482SBill Paul 173595d67482SBill Paul dev = sc->bge_dev; 173695d67482SBill Paul 173795d67482SBill Paul /* Save some important PCI state. */ 173895d67482SBill Paul cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 173995d67482SBill Paul command = pci_read_config(dev, BGE_PCI_CMD, 4); 174095d67482SBill Paul pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 174195d67482SBill Paul 174295d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 174395d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 174495d67482SBill Paul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 174595d67482SBill Paul 174695d67482SBill Paul /* Issue global reset */ 174795d67482SBill Paul bge_writereg_ind(sc, BGE_MISC_CFG, 174895d67482SBill Paul BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 174995d67482SBill Paul 175095d67482SBill Paul DELAY(1000); 175195d67482SBill Paul 175295d67482SBill Paul /* Reset some of the PCI state that got zapped by reset */ 175395d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 175495d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 175595d67482SBill Paul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 175695d67482SBill Paul pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 175795d67482SBill Paul pci_write_config(dev, BGE_PCI_CMD, command, 4); 175895d67482SBill Paul bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 175995d67482SBill Paul 176095d67482SBill Paul /* 176195d67482SBill Paul * Prevent PXE restart: write a magic number to the 176295d67482SBill Paul * general communications memory at 0xB50. 176395d67482SBill Paul */ 176495d67482SBill Paul bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 176595d67482SBill Paul /* 176695d67482SBill Paul * Poll the value location we just wrote until 176795d67482SBill Paul * we see the 1's complement of the magic number. 176895d67482SBill Paul * This indicates that the firmware initialization 176995d67482SBill Paul * is complete. 177095d67482SBill Paul */ 177195d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 177295d67482SBill Paul val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 177395d67482SBill Paul if (val == ~BGE_MAGIC_NUMBER) 177495d67482SBill Paul break; 177595d67482SBill Paul DELAY(10); 177695d67482SBill Paul } 177795d67482SBill Paul 177895d67482SBill Paul if (i == BGE_TIMEOUT) { 177995d67482SBill Paul printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 178095d67482SBill Paul return; 178195d67482SBill Paul } 178295d67482SBill Paul 178395d67482SBill Paul /* 178495d67482SBill Paul * XXX Wait for the value of the PCISTATE register to 178595d67482SBill Paul * return to its original pre-reset state. This is a 178695d67482SBill Paul * fairly good indicator of reset completion. If we don't 178795d67482SBill Paul * wait for the reset to fully complete, trying to read 178895d67482SBill Paul * from the device's non-PCI registers may yield garbage 178995d67482SBill Paul * results. 179095d67482SBill Paul */ 179195d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 179295d67482SBill Paul if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 179395d67482SBill Paul break; 179495d67482SBill Paul DELAY(10); 179595d67482SBill Paul } 179695d67482SBill Paul 179795d67482SBill Paul /* Enable memory arbiter. */ 179895d67482SBill Paul CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 179995d67482SBill Paul 180095d67482SBill Paul /* Fix up byte swapping */ 180195d67482SBill Paul CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 180295d67482SBill Paul BGE_MODECTL_BYTESWAP_DATA); 180395d67482SBill Paul 180495d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 180595d67482SBill Paul 180695d67482SBill Paul DELAY(10000); 180795d67482SBill Paul 180895d67482SBill Paul return; 180995d67482SBill Paul } 181095d67482SBill Paul 181195d67482SBill Paul /* 181295d67482SBill Paul * Frame reception handling. This is called if there's a frame 181395d67482SBill Paul * on the receive return list. 181495d67482SBill Paul * 181595d67482SBill Paul * Note: we have to be able to handle two possibilities here: 181695d67482SBill Paul * 1) the frame is from the jumbo recieve ring 181795d67482SBill Paul * 2) the frame is from the standard receive ring 181895d67482SBill Paul */ 181995d67482SBill Paul 182095d67482SBill Paul static void 182195d67482SBill Paul bge_rxeof(sc) 182295d67482SBill Paul struct bge_softc *sc; 182395d67482SBill Paul { 182495d67482SBill Paul struct ifnet *ifp; 182595d67482SBill Paul int stdcnt = 0, jumbocnt = 0; 182695d67482SBill Paul 182795d67482SBill Paul ifp = &sc->arpcom.ac_if; 182895d67482SBill Paul 182995d67482SBill Paul while(sc->bge_rx_saved_considx != 183095d67482SBill Paul sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 183195d67482SBill Paul struct bge_rx_bd *cur_rx; 183295d67482SBill Paul u_int32_t rxidx; 183395d67482SBill Paul struct ether_header *eh; 183495d67482SBill Paul struct mbuf *m = NULL; 183595d67482SBill Paul u_int16_t vlan_tag = 0; 183695d67482SBill Paul int have_tag = 0; 183795d67482SBill Paul 183895d67482SBill Paul cur_rx = 183995d67482SBill Paul &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 184095d67482SBill Paul 184195d67482SBill Paul rxidx = cur_rx->bge_idx; 184295d67482SBill Paul BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 184395d67482SBill Paul 184495d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 184595d67482SBill Paul have_tag = 1; 184695d67482SBill Paul vlan_tag = cur_rx->bge_vlan_tag; 184795d67482SBill Paul } 184895d67482SBill Paul 184995d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 185095d67482SBill Paul BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 185195d67482SBill Paul m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 185295d67482SBill Paul sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 185395d67482SBill Paul jumbocnt++; 185495d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 185595d67482SBill Paul ifp->if_ierrors++; 185695d67482SBill Paul bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 185795d67482SBill Paul continue; 185895d67482SBill Paul } 185995d67482SBill Paul if (bge_newbuf_jumbo(sc, 186095d67482SBill Paul sc->bge_jumbo, NULL) == ENOBUFS) { 186195d67482SBill Paul ifp->if_ierrors++; 186295d67482SBill Paul bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 186395d67482SBill Paul continue; 186495d67482SBill Paul } 186595d67482SBill Paul } else { 186695d67482SBill Paul BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 186795d67482SBill Paul m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 186895d67482SBill Paul sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 186995d67482SBill Paul stdcnt++; 187095d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 187195d67482SBill Paul ifp->if_ierrors++; 187295d67482SBill Paul bge_newbuf_std(sc, sc->bge_std, m); 187395d67482SBill Paul continue; 187495d67482SBill Paul } 187595d67482SBill Paul if (bge_newbuf_std(sc, sc->bge_std, 187695d67482SBill Paul NULL) == ENOBUFS) { 187795d67482SBill Paul ifp->if_ierrors++; 187895d67482SBill Paul bge_newbuf_std(sc, sc->bge_std, m); 187995d67482SBill Paul continue; 188095d67482SBill Paul } 188195d67482SBill Paul } 188295d67482SBill Paul 188395d67482SBill Paul ifp->if_ipackets++; 188495d67482SBill Paul eh = mtod(m, struct ether_header *); 188595d67482SBill Paul m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 188695d67482SBill Paul m->m_pkthdr.rcvif = ifp; 188795d67482SBill Paul 188895d67482SBill Paul /* Remove header from mbuf and pass it on. */ 188995d67482SBill Paul m_adj(m, sizeof(struct ether_header)); 189095d67482SBill Paul 1891eb48892eSDavid Greenman #if 0 /* currently broken for some packets, possibly related to TCP options */ 189295d67482SBill Paul if (ifp->if_hwassist) { 189395d67482SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 189495d67482SBill Paul if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 189595d67482SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 189695d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 189795d67482SBill Paul m->m_pkthdr.csum_data = 189895d67482SBill Paul cur_rx->bge_tcp_udp_csum; 18990189c944SBill Paul m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 190095d67482SBill Paul } 190195d67482SBill Paul } 1902eb48892eSDavid Greenman #endif 190395d67482SBill Paul 190495d67482SBill Paul /* 190595d67482SBill Paul * If we received a packet with a vlan tag, pass it 190695d67482SBill Paul * to vlan_input() instead of ether_input(). 190795d67482SBill Paul */ 190895d67482SBill Paul if (have_tag) { 1909437e48e9SBrooks Davis VLAN_INPUT_TAG(eh, m, vlan_tag); 191095d67482SBill Paul have_tag = vlan_tag = 0; 191195d67482SBill Paul continue; 191295d67482SBill Paul } 191395d67482SBill Paul 191495d67482SBill Paul ether_input(ifp, eh, m); 191595d67482SBill Paul } 191695d67482SBill Paul 191795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 191895d67482SBill Paul if (stdcnt) 191995d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 192095d67482SBill Paul if (jumbocnt) 192195d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 192295d67482SBill Paul 192395d67482SBill Paul return; 192495d67482SBill Paul } 192595d67482SBill Paul 192695d67482SBill Paul static void 192795d67482SBill Paul bge_txeof(sc) 192895d67482SBill Paul struct bge_softc *sc; 192995d67482SBill Paul { 193095d67482SBill Paul struct bge_tx_bd *cur_tx = NULL; 193195d67482SBill Paul struct ifnet *ifp; 193295d67482SBill Paul 193395d67482SBill Paul ifp = &sc->arpcom.ac_if; 193495d67482SBill Paul 193595d67482SBill Paul /* 193695d67482SBill Paul * Go through our tx ring and free mbufs for those 193795d67482SBill Paul * frames that have been sent. 193895d67482SBill Paul */ 193995d67482SBill Paul while (sc->bge_tx_saved_considx != 194095d67482SBill Paul sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 194195d67482SBill Paul u_int32_t idx = 0; 194295d67482SBill Paul 194395d67482SBill Paul idx = sc->bge_tx_saved_considx; 194495d67482SBill Paul cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 194595d67482SBill Paul if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 194695d67482SBill Paul ifp->if_opackets++; 194795d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 194895d67482SBill Paul m_freem(sc->bge_cdata.bge_tx_chain[idx]); 194995d67482SBill Paul sc->bge_cdata.bge_tx_chain[idx] = NULL; 195095d67482SBill Paul } 195195d67482SBill Paul sc->bge_txcnt--; 195295d67482SBill Paul BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 195395d67482SBill Paul ifp->if_timer = 0; 195495d67482SBill Paul } 195595d67482SBill Paul 195695d67482SBill Paul if (cur_tx != NULL) 195795d67482SBill Paul ifp->if_flags &= ~IFF_OACTIVE; 195895d67482SBill Paul 195995d67482SBill Paul return; 196095d67482SBill Paul } 196195d67482SBill Paul 196295d67482SBill Paul static void 196395d67482SBill Paul bge_intr(xsc) 196495d67482SBill Paul void *xsc; 196595d67482SBill Paul { 196695d67482SBill Paul struct bge_softc *sc; 196795d67482SBill Paul struct ifnet *ifp; 196895d67482SBill Paul 196995d67482SBill Paul sc = xsc; 197095d67482SBill Paul ifp = &sc->arpcom.ac_if; 197195d67482SBill Paul 197295d67482SBill Paul #ifdef notdef 197395d67482SBill Paul /* Avoid this for now -- checking this register is expensive. */ 197495d67482SBill Paul /* Make sure this is really our interrupt. */ 197595d67482SBill Paul if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 197695d67482SBill Paul return; 197795d67482SBill Paul #endif 197895d67482SBill Paul /* Ack interrupt and stop others from occuring. */ 197995d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 198095d67482SBill Paul 198195d67482SBill Paul /* Process link state changes. */ 198295d67482SBill Paul if (sc->bge_rdata->bge_status_block.bge_status & 198395d67482SBill Paul BGE_STATFLAG_LINKSTATE_CHANGED) { 198495d67482SBill Paul sc->bge_link = 0; 198595d67482SBill Paul untimeout(bge_tick, sc, sc->bge_stat_ch); 198695d67482SBill Paul bge_tick(sc); 198795d67482SBill Paul /* ack the event to clear/reset it */ 198895d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 198995d67482SBill Paul BGE_MACSTAT_CFG_CHANGED); 199095d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, 0); 199195d67482SBill Paul } 199295d67482SBill Paul 199395d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) { 199495d67482SBill Paul /* Check RX return ring producer/consumer */ 199595d67482SBill Paul bge_rxeof(sc); 199695d67482SBill Paul 199795d67482SBill Paul /* Check TX ring producer/consumer */ 199895d67482SBill Paul bge_txeof(sc); 199995d67482SBill Paul } 200095d67482SBill Paul 200195d67482SBill Paul bge_handle_events(sc); 200295d67482SBill Paul 200395d67482SBill Paul /* Re-enable interrupts. */ 200495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 200595d67482SBill Paul 200695d67482SBill Paul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 200795d67482SBill Paul bge_start(ifp); 200895d67482SBill Paul 200995d67482SBill Paul return; 201095d67482SBill Paul } 201195d67482SBill Paul 201295d67482SBill Paul static void 201395d67482SBill Paul bge_tick(xsc) 201495d67482SBill Paul void *xsc; 201595d67482SBill Paul { 201695d67482SBill Paul struct bge_softc *sc; 201795d67482SBill Paul struct mii_data *mii = NULL; 201895d67482SBill Paul struct ifmedia *ifm = NULL; 201995d67482SBill Paul struct ifnet *ifp; 202095d67482SBill Paul int s; 202195d67482SBill Paul 202295d67482SBill Paul sc = xsc; 202395d67482SBill Paul ifp = &sc->arpcom.ac_if; 202495d67482SBill Paul 202595d67482SBill Paul s = splimp(); 202695d67482SBill Paul 202795d67482SBill Paul bge_stats_update(sc); 202895d67482SBill Paul sc->bge_stat_ch = timeout(bge_tick, sc, hz); 202995d67482SBill Paul if (sc->bge_link) 203095d67482SBill Paul return; 203195d67482SBill Paul 203295d67482SBill Paul if (sc->bge_tbi) { 203395d67482SBill Paul ifm = &sc->bge_ifmedia; 203495d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_STS) & 203595d67482SBill Paul BGE_MACSTAT_TBI_PCS_SYNCHED) { 203695d67482SBill Paul sc->bge_link++; 203795d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 203895d67482SBill Paul printf("bge%d: gigabit link up\n", sc->bge_unit); 203995d67482SBill Paul if (ifp->if_snd.ifq_head != NULL) 204095d67482SBill Paul bge_start(ifp); 204195d67482SBill Paul } 204295d67482SBill Paul return; 204395d67482SBill Paul } 204495d67482SBill Paul 204595d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 204695d67482SBill Paul mii_tick(mii); 204795d67482SBill Paul 2048b2561871SJonathan Lemon if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 204995d67482SBill Paul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 205095d67482SBill Paul sc->bge_link++; 205195d67482SBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 205295d67482SBill Paul IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 205395d67482SBill Paul printf("bge%d: gigabit link up\n", 205495d67482SBill Paul sc->bge_unit); 205595d67482SBill Paul if (ifp->if_snd.ifq_head != NULL) 205695d67482SBill Paul bge_start(ifp); 205795d67482SBill Paul } 205895d67482SBill Paul 205995d67482SBill Paul splx(s); 206095d67482SBill Paul 206195d67482SBill Paul return; 206295d67482SBill Paul } 206395d67482SBill Paul 206495d67482SBill Paul static void 206595d67482SBill Paul bge_stats_update(sc) 206695d67482SBill Paul struct bge_softc *sc; 206795d67482SBill Paul { 206895d67482SBill Paul struct ifnet *ifp; 206995d67482SBill Paul struct bge_stats *stats; 207095d67482SBill Paul 207195d67482SBill Paul ifp = &sc->arpcom.ac_if; 207295d67482SBill Paul 207395d67482SBill Paul stats = (struct bge_stats *)(sc->bge_vhandle + 207495d67482SBill Paul BGE_MEMWIN_START + BGE_STATS_BLOCK); 207595d67482SBill Paul 207695d67482SBill Paul ifp->if_collisions += 207795d67482SBill Paul (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 207895d67482SBill Paul stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 207995d67482SBill Paul stats->dot3StatsExcessiveCollisions.bge_addr_lo + 208095d67482SBill Paul stats->dot3StatsLateCollisions.bge_addr_lo) - 208195d67482SBill Paul ifp->if_collisions; 208295d67482SBill Paul 208395d67482SBill Paul #ifdef notdef 208495d67482SBill Paul ifp->if_collisions += 208595d67482SBill Paul (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 208695d67482SBill Paul sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 208795d67482SBill Paul sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 208895d67482SBill Paul sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 208995d67482SBill Paul ifp->if_collisions; 209095d67482SBill Paul #endif 209195d67482SBill Paul 209295d67482SBill Paul return; 209395d67482SBill Paul } 209495d67482SBill Paul 209595d67482SBill Paul /* 209695d67482SBill Paul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 209795d67482SBill Paul * pointers to descriptors. 209895d67482SBill Paul */ 209995d67482SBill Paul static int 210095d67482SBill Paul bge_encap(sc, m_head, txidx) 210195d67482SBill Paul struct bge_softc *sc; 210295d67482SBill Paul struct mbuf *m_head; 210395d67482SBill Paul u_int32_t *txidx; 210495d67482SBill Paul { 210595d67482SBill Paul struct bge_tx_bd *f = NULL; 210695d67482SBill Paul struct mbuf *m; 210795d67482SBill Paul u_int32_t frag, cur, cnt = 0; 210895d67482SBill Paul u_int16_t csum_flags = 0; 210995d67482SBill Paul struct ifvlan *ifv = NULL; 211095d67482SBill Paul 211195d67482SBill Paul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 211295d67482SBill Paul m_head->m_pkthdr.rcvif != NULL && 211395d67482SBill Paul m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 211495d67482SBill Paul ifv = m_head->m_pkthdr.rcvif->if_softc; 211595d67482SBill Paul 211695d67482SBill Paul m = m_head; 211795d67482SBill Paul cur = frag = *txidx; 211895d67482SBill Paul 211995d67482SBill Paul if (m_head->m_pkthdr.csum_flags) { 212095d67482SBill Paul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 212195d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_CSUM; 212295d67482SBill Paul if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 212395d67482SBill Paul csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 212495d67482SBill Paul if (m_head->m_flags & M_LASTFRAG) 212595d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 212695d67482SBill Paul else if (m_head->m_flags & M_FRAG) 212795d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_FRAG; 212895d67482SBill Paul } 212995d67482SBill Paul 213095d67482SBill Paul /* 213195d67482SBill Paul * Start packing the mbufs in this chain into 213295d67482SBill Paul * the fragment pointers. Stop when we run out 213395d67482SBill Paul * of fragments or hit the end of the mbuf chain. 213495d67482SBill Paul */ 213595d67482SBill Paul for (m = m_head; m != NULL; m = m->m_next) { 213695d67482SBill Paul if (m->m_len != 0) { 213795d67482SBill Paul f = &sc->bge_rdata->bge_tx_ring[frag]; 213895d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 213995d67482SBill Paul break; 214095d67482SBill Paul BGE_HOSTADDR(f->bge_addr) = 214195d67482SBill Paul vtophys(mtod(m, vm_offset_t)); 214295d67482SBill Paul f->bge_len = m->m_len; 214395d67482SBill Paul f->bge_flags = csum_flags; 214495d67482SBill Paul if (ifv != NULL) { 214595d67482SBill Paul f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 214695d67482SBill Paul f->bge_vlan_tag = ifv->ifv_tag; 214795d67482SBill Paul } else { 214895d67482SBill Paul f->bge_vlan_tag = 0; 214995d67482SBill Paul } 215095d67482SBill Paul /* 215195d67482SBill Paul * Sanity check: avoid coming within 16 descriptors 215295d67482SBill Paul * of the end of the ring. 215395d67482SBill Paul */ 215495d67482SBill Paul if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 215595d67482SBill Paul return(ENOBUFS); 215695d67482SBill Paul cur = frag; 215795d67482SBill Paul BGE_INC(frag, BGE_TX_RING_CNT); 215895d67482SBill Paul cnt++; 215995d67482SBill Paul } 216095d67482SBill Paul } 216195d67482SBill Paul 216295d67482SBill Paul if (m != NULL) 216395d67482SBill Paul return(ENOBUFS); 216495d67482SBill Paul 216595d67482SBill Paul if (frag == sc->bge_tx_saved_considx) 216695d67482SBill Paul return(ENOBUFS); 216795d67482SBill Paul 216895d67482SBill Paul sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 216995d67482SBill Paul sc->bge_cdata.bge_tx_chain[cur] = m_head; 217095d67482SBill Paul sc->bge_txcnt += cnt; 217195d67482SBill Paul 217295d67482SBill Paul *txidx = frag; 217395d67482SBill Paul 217495d67482SBill Paul return(0); 217595d67482SBill Paul } 217695d67482SBill Paul 217795d67482SBill Paul /* 217895d67482SBill Paul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 217995d67482SBill Paul * to the mbuf data regions directly in the transmit descriptors. 218095d67482SBill Paul */ 218195d67482SBill Paul static void 218295d67482SBill Paul bge_start(ifp) 218395d67482SBill Paul struct ifnet *ifp; 218495d67482SBill Paul { 218595d67482SBill Paul struct bge_softc *sc; 218695d67482SBill Paul struct mbuf *m_head = NULL; 218795d67482SBill Paul u_int32_t prodidx = 0; 218895d67482SBill Paul 218995d67482SBill Paul sc = ifp->if_softc; 219095d67482SBill Paul 219195d67482SBill Paul if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 219295d67482SBill Paul return; 219395d67482SBill Paul 219495d67482SBill Paul prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 219595d67482SBill Paul 219695d67482SBill Paul while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 219795d67482SBill Paul IF_DEQUEUE(&ifp->if_snd, m_head); 219895d67482SBill Paul if (m_head == NULL) 219995d67482SBill Paul break; 220095d67482SBill Paul 220195d67482SBill Paul /* 220295d67482SBill Paul * XXX 220395d67482SBill Paul * safety overkill. If this is a fragmented packet chain 220495d67482SBill Paul * with delayed TCP/UDP checksums, then only encapsulate 220595d67482SBill Paul * it if we have enough descriptors to handle the entire 220695d67482SBill Paul * chain at once. 220795d67482SBill Paul * (paranoia -- may not actually be needed) 220895d67482SBill Paul */ 220995d67482SBill Paul if (m_head->m_flags & M_FIRSTFRAG && 221095d67482SBill Paul m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 221195d67482SBill Paul if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 221295d67482SBill Paul m_head->m_pkthdr.csum_data + 16) { 221395d67482SBill Paul IF_PREPEND(&ifp->if_snd, m_head); 221495d67482SBill Paul ifp->if_flags |= IFF_OACTIVE; 221595d67482SBill Paul break; 221695d67482SBill Paul } 221795d67482SBill Paul } 221895d67482SBill Paul 221995d67482SBill Paul /* 222095d67482SBill Paul * Pack the data into the transmit ring. If we 222195d67482SBill Paul * don't have room, set the OACTIVE flag and wait 222295d67482SBill Paul * for the NIC to drain the ring. 222395d67482SBill Paul */ 222495d67482SBill Paul if (bge_encap(sc, m_head, &prodidx)) { 222595d67482SBill Paul IF_PREPEND(&ifp->if_snd, m_head); 222695d67482SBill Paul ifp->if_flags |= IFF_OACTIVE; 222795d67482SBill Paul break; 222895d67482SBill Paul } 222995d67482SBill Paul 223095d67482SBill Paul /* 223195d67482SBill Paul * If there's a BPF listener, bounce a copy of this frame 223295d67482SBill Paul * to him. 223395d67482SBill Paul */ 223495d67482SBill Paul if (ifp->if_bpf) 223595d67482SBill Paul bpf_mtap(ifp, m_head); 223695d67482SBill Paul } 223795d67482SBill Paul 223895d67482SBill Paul /* Transmit */ 223995d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 224095d67482SBill Paul 224195d67482SBill Paul /* 224295d67482SBill Paul * Set a timeout in case the chip goes out to lunch. 224395d67482SBill Paul */ 224495d67482SBill Paul ifp->if_timer = 5; 224595d67482SBill Paul 224695d67482SBill Paul return; 224795d67482SBill Paul } 224895d67482SBill Paul 224995d67482SBill Paul /* 225095d67482SBill Paul * If we have a BCM5400 or BCM5401 PHY, we need to properly 225195d67482SBill Paul * program its internal DSP. Failing to do this can result in 225295d67482SBill Paul * massive packet loss at 1Gb speeds. 225395d67482SBill Paul */ 225495d67482SBill Paul static void 225595d67482SBill Paul bge_phy_hack(sc) 225695d67482SBill Paul struct bge_softc *sc; 225795d67482SBill Paul { 225895d67482SBill Paul struct bge_bcom_hack bhack[] = { 225995d67482SBill Paul { BRGPHY_MII_AUXCTL, 0x4C20 }, 226095d67482SBill Paul { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 226195d67482SBill Paul { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 226295d67482SBill Paul { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 226395d67482SBill Paul { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 226495d67482SBill Paul { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 226595d67482SBill Paul { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 226695d67482SBill Paul { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 226795d67482SBill Paul { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 226895d67482SBill Paul { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 226995d67482SBill Paul { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 227095d67482SBill Paul { 0, 0 } }; 227195d67482SBill Paul u_int16_t vid, did; 227295d67482SBill Paul int i; 227395d67482SBill Paul 227495d67482SBill Paul vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 227595d67482SBill Paul did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 227695d67482SBill Paul 227795d67482SBill Paul if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 227895d67482SBill Paul (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 227995d67482SBill Paul MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 228095d67482SBill Paul i = 0; 228195d67482SBill Paul while(bhack[i].reg) { 228295d67482SBill Paul bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 228395d67482SBill Paul bhack[i].val); 228495d67482SBill Paul i++; 228595d67482SBill Paul } 228695d67482SBill Paul } 228795d67482SBill Paul 228895d67482SBill Paul return; 228995d67482SBill Paul } 229095d67482SBill Paul 229195d67482SBill Paul static void 229295d67482SBill Paul bge_init(xsc) 229395d67482SBill Paul void *xsc; 229495d67482SBill Paul { 229595d67482SBill Paul struct bge_softc *sc = xsc; 229695d67482SBill Paul struct ifnet *ifp; 229795d67482SBill Paul u_int16_t *m; 229895d67482SBill Paul int s; 229995d67482SBill Paul 230095d67482SBill Paul s = splimp(); 230195d67482SBill Paul 230295d67482SBill Paul ifp = &sc->arpcom.ac_if; 230395d67482SBill Paul 230495d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) 230595d67482SBill Paul return; 230695d67482SBill Paul 230795d67482SBill Paul /* Cancel pending I/O and flush buffers. */ 230895d67482SBill Paul bge_stop(sc); 230995d67482SBill Paul bge_reset(sc); 231095d67482SBill Paul bge_chipinit(sc); 231195d67482SBill Paul 231295d67482SBill Paul /* 231395d67482SBill Paul * Init the various state machines, ring 231495d67482SBill Paul * control blocks and firmware. 231595d67482SBill Paul */ 231695d67482SBill Paul if (bge_blockinit(sc)) { 231795d67482SBill Paul printf("bge%d: initialization failure\n", sc->bge_unit); 231895d67482SBill Paul splx(s); 231995d67482SBill Paul return; 232095d67482SBill Paul } 232195d67482SBill Paul 232295d67482SBill Paul ifp = &sc->arpcom.ac_if; 232395d67482SBill Paul 232495d67482SBill Paul /* Specify MTU. */ 232595d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 232695d67482SBill Paul ETHER_HDR_LEN + ETHER_CRC_LEN); 232795d67482SBill Paul 232895d67482SBill Paul /* Load our MAC address. */ 232995d67482SBill Paul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 233095d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 233195d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 233295d67482SBill Paul 233395d67482SBill Paul /* Enable or disable promiscuous mode as needed. */ 233495d67482SBill Paul if (ifp->if_flags & IFF_PROMISC) { 233595d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 233695d67482SBill Paul } else { 233795d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 233895d67482SBill Paul } 233995d67482SBill Paul 234095d67482SBill Paul /* Program multicast filter. */ 234195d67482SBill Paul bge_setmulti(sc); 234295d67482SBill Paul 234395d67482SBill Paul /* Init RX ring. */ 234495d67482SBill Paul bge_init_rx_ring_std(sc); 234595d67482SBill Paul 234695d67482SBill Paul /* Init jumbo RX ring. */ 234795d67482SBill Paul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 234895d67482SBill Paul bge_init_rx_ring_jumbo(sc); 234995d67482SBill Paul 235095d67482SBill Paul /* Init our RX return ring index */ 235195d67482SBill Paul sc->bge_rx_saved_considx = 0; 235295d67482SBill Paul 235395d67482SBill Paul /* Init TX ring. */ 235495d67482SBill Paul bge_init_tx_ring(sc); 235595d67482SBill Paul 235695d67482SBill Paul /* Turn on transmitter */ 235795d67482SBill Paul BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 235895d67482SBill Paul 235995d67482SBill Paul /* Turn on receiver */ 236095d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 236195d67482SBill Paul 236295d67482SBill Paul /* Tell firmware we're alive. */ 236395d67482SBill Paul BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 236495d67482SBill Paul 236595d67482SBill Paul /* Enable host interrupts. */ 236695d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 236795d67482SBill Paul BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 236895d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 236995d67482SBill Paul 237095d67482SBill Paul bge_ifmedia_upd(ifp); 237195d67482SBill Paul 237295d67482SBill Paul ifp->if_flags |= IFF_RUNNING; 237395d67482SBill Paul ifp->if_flags &= ~IFF_OACTIVE; 237495d67482SBill Paul 237595d67482SBill Paul splx(s); 237695d67482SBill Paul 237795d67482SBill Paul sc->bge_stat_ch = timeout(bge_tick, sc, hz); 237895d67482SBill Paul 237995d67482SBill Paul return; 238095d67482SBill Paul } 238195d67482SBill Paul 238295d67482SBill Paul /* 238395d67482SBill Paul * Set media options. 238495d67482SBill Paul */ 238595d67482SBill Paul static int 238695d67482SBill Paul bge_ifmedia_upd(ifp) 238795d67482SBill Paul struct ifnet *ifp; 238895d67482SBill Paul { 238995d67482SBill Paul struct bge_softc *sc; 239095d67482SBill Paul struct mii_data *mii; 239195d67482SBill Paul struct ifmedia *ifm; 239295d67482SBill Paul 239395d67482SBill Paul sc = ifp->if_softc; 239495d67482SBill Paul ifm = &sc->bge_ifmedia; 239595d67482SBill Paul 239695d67482SBill Paul /* If this is a 1000baseX NIC, enable the TBI port. */ 239795d67482SBill Paul if (sc->bge_tbi) { 239895d67482SBill Paul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 239995d67482SBill Paul return(EINVAL); 240095d67482SBill Paul switch(IFM_SUBTYPE(ifm->ifm_media)) { 240195d67482SBill Paul case IFM_AUTO: 240295d67482SBill Paul break; 240395d67482SBill Paul case IFM_1000_SX: 240495d67482SBill Paul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 240595d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, 240695d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 240795d67482SBill Paul } else { 240895d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, 240995d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 241095d67482SBill Paul } 241195d67482SBill Paul break; 241295d67482SBill Paul default: 241395d67482SBill Paul return(EINVAL); 241495d67482SBill Paul } 241595d67482SBill Paul return(0); 241695d67482SBill Paul } 241795d67482SBill Paul 241895d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 241995d67482SBill Paul sc->bge_link = 0; 242095d67482SBill Paul if (mii->mii_instance) { 242195d67482SBill Paul struct mii_softc *miisc; 242295d67482SBill Paul for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 242395d67482SBill Paul miisc = LIST_NEXT(miisc, mii_list)) 242495d67482SBill Paul mii_phy_reset(miisc); 242595d67482SBill Paul } 242695d67482SBill Paul bge_phy_hack(sc); 242795d67482SBill Paul mii_mediachg(mii); 242895d67482SBill Paul 242995d67482SBill Paul return(0); 243095d67482SBill Paul } 243195d67482SBill Paul 243295d67482SBill Paul /* 243395d67482SBill Paul * Report current media status. 243495d67482SBill Paul */ 243595d67482SBill Paul static void 243695d67482SBill Paul bge_ifmedia_sts(ifp, ifmr) 243795d67482SBill Paul struct ifnet *ifp; 243895d67482SBill Paul struct ifmediareq *ifmr; 243995d67482SBill Paul { 244095d67482SBill Paul struct bge_softc *sc; 244195d67482SBill Paul struct mii_data *mii; 244295d67482SBill Paul 244395d67482SBill Paul sc = ifp->if_softc; 244495d67482SBill Paul 244595d67482SBill Paul if (sc->bge_tbi) { 244695d67482SBill Paul ifmr->ifm_status = IFM_AVALID; 244795d67482SBill Paul ifmr->ifm_active = IFM_ETHER; 244895d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_STS) & 244995d67482SBill Paul BGE_MACSTAT_TBI_PCS_SYNCHED) 245095d67482SBill Paul ifmr->ifm_status |= IFM_ACTIVE; 245195d67482SBill Paul ifmr->ifm_active |= IFM_1000_SX; 245295d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 245395d67482SBill Paul ifmr->ifm_active |= IFM_HDX; 245495d67482SBill Paul else 245595d67482SBill Paul ifmr->ifm_active |= IFM_FDX; 245695d67482SBill Paul return; 245795d67482SBill Paul } 245895d67482SBill Paul 245995d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 246095d67482SBill Paul mii_pollstat(mii); 246195d67482SBill Paul ifmr->ifm_active = mii->mii_media_active; 246295d67482SBill Paul ifmr->ifm_status = mii->mii_media_status; 246395d67482SBill Paul 246495d67482SBill Paul return; 246595d67482SBill Paul } 246695d67482SBill Paul 246795d67482SBill Paul static int 246895d67482SBill Paul bge_ioctl(ifp, command, data) 246995d67482SBill Paul struct ifnet *ifp; 247095d67482SBill Paul u_long command; 247195d67482SBill Paul caddr_t data; 247295d67482SBill Paul { 247395d67482SBill Paul struct bge_softc *sc = ifp->if_softc; 247495d67482SBill Paul struct ifreq *ifr = (struct ifreq *) data; 247595d67482SBill Paul int s, mask, error = 0; 247695d67482SBill Paul struct mii_data *mii; 247795d67482SBill Paul 247895d67482SBill Paul s = splimp(); 247995d67482SBill Paul 248095d67482SBill Paul switch(command) { 248195d67482SBill Paul case SIOCSIFADDR: 248295d67482SBill Paul case SIOCGIFADDR: 248395d67482SBill Paul error = ether_ioctl(ifp, command, data); 248495d67482SBill Paul break; 248595d67482SBill Paul case SIOCSIFMTU: 248695d67482SBill Paul if (ifr->ifr_mtu > BGE_JUMBO_MTU) 248795d67482SBill Paul error = EINVAL; 248895d67482SBill Paul else { 248995d67482SBill Paul ifp->if_mtu = ifr->ifr_mtu; 249095d67482SBill Paul ifp->if_flags &= ~IFF_RUNNING; 249195d67482SBill Paul bge_init(sc); 249295d67482SBill Paul } 249395d67482SBill Paul break; 249495d67482SBill Paul case SIOCSIFFLAGS: 249595d67482SBill Paul if (ifp->if_flags & IFF_UP) { 249695d67482SBill Paul /* 249795d67482SBill Paul * If only the state of the PROMISC flag changed, 249895d67482SBill Paul * then just use the 'set promisc mode' command 249995d67482SBill Paul * instead of reinitializing the entire NIC. Doing 250095d67482SBill Paul * a full re-init means reloading the firmware and 250195d67482SBill Paul * waiting for it to start up, which may take a 250295d67482SBill Paul * second or two. 250395d67482SBill Paul */ 250495d67482SBill Paul if (ifp->if_flags & IFF_RUNNING && 250595d67482SBill Paul ifp->if_flags & IFF_PROMISC && 250695d67482SBill Paul !(sc->bge_if_flags & IFF_PROMISC)) { 250795d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, 250895d67482SBill Paul BGE_RXMODE_RX_PROMISC); 250995d67482SBill Paul } else if (ifp->if_flags & IFF_RUNNING && 251095d67482SBill Paul !(ifp->if_flags & IFF_PROMISC) && 251195d67482SBill Paul sc->bge_if_flags & IFF_PROMISC) { 251295d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, 251395d67482SBill Paul BGE_RXMODE_RX_PROMISC); 251495d67482SBill Paul } else 251595d67482SBill Paul bge_init(sc); 251695d67482SBill Paul } else { 251795d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) { 251895d67482SBill Paul bge_stop(sc); 251995d67482SBill Paul } 252095d67482SBill Paul } 252195d67482SBill Paul sc->bge_if_flags = ifp->if_flags; 252295d67482SBill Paul error = 0; 252395d67482SBill Paul break; 252495d67482SBill Paul case SIOCADDMULTI: 252595d67482SBill Paul case SIOCDELMULTI: 252695d67482SBill Paul if (ifp->if_flags & IFF_RUNNING) { 252795d67482SBill Paul bge_setmulti(sc); 252895d67482SBill Paul error = 0; 252995d67482SBill Paul } 253095d67482SBill Paul break; 253195d67482SBill Paul case SIOCSIFMEDIA: 253295d67482SBill Paul case SIOCGIFMEDIA: 253395d67482SBill Paul if (sc->bge_tbi) { 253495d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 253595d67482SBill Paul &sc->bge_ifmedia, command); 253695d67482SBill Paul } else { 253795d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 253895d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 253995d67482SBill Paul &mii->mii_media, command); 254095d67482SBill Paul } 254195d67482SBill Paul break; 254295d67482SBill Paul case SIOCSIFCAP: 254395d67482SBill Paul mask = ifr->ifr_reqcap ^ ifp->if_capenable; 254495d67482SBill Paul if (mask & IFCAP_HWCSUM) { 254595d67482SBill Paul if (IFCAP_HWCSUM & ifp->if_capenable) 254695d67482SBill Paul ifp->if_capenable &= ~IFCAP_HWCSUM; 254795d67482SBill Paul else 254895d67482SBill Paul ifp->if_capenable |= IFCAP_HWCSUM; 254995d67482SBill Paul } 255095d67482SBill Paul error = 0; 255195d67482SBill Paul break; 255295d67482SBill Paul default: 255395d67482SBill Paul error = EINVAL; 255495d67482SBill Paul break; 255595d67482SBill Paul } 255695d67482SBill Paul 255795d67482SBill Paul (void)splx(s); 255895d67482SBill Paul 255995d67482SBill Paul return(error); 256095d67482SBill Paul } 256195d67482SBill Paul 256295d67482SBill Paul static void 256395d67482SBill Paul bge_watchdog(ifp) 256495d67482SBill Paul struct ifnet *ifp; 256595d67482SBill Paul { 256695d67482SBill Paul struct bge_softc *sc; 256795d67482SBill Paul 256895d67482SBill Paul sc = ifp->if_softc; 256995d67482SBill Paul 257095d67482SBill Paul printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 257195d67482SBill Paul 257295d67482SBill Paul ifp->if_flags &= ~IFF_RUNNING; 257395d67482SBill Paul bge_init(sc); 257495d67482SBill Paul 257595d67482SBill Paul ifp->if_oerrors++; 257695d67482SBill Paul 257795d67482SBill Paul return; 257895d67482SBill Paul } 257995d67482SBill Paul 258095d67482SBill Paul /* 258195d67482SBill Paul * Stop the adapter and free any mbufs allocated to the 258295d67482SBill Paul * RX and TX lists. 258395d67482SBill Paul */ 258495d67482SBill Paul static void 258595d67482SBill Paul bge_stop(sc) 258695d67482SBill Paul struct bge_softc *sc; 258795d67482SBill Paul { 258895d67482SBill Paul struct ifnet *ifp; 258995d67482SBill Paul struct ifmedia_entry *ifm; 259095d67482SBill Paul struct mii_data *mii = NULL; 259195d67482SBill Paul int mtmp, itmp; 259295d67482SBill Paul 259395d67482SBill Paul ifp = &sc->arpcom.ac_if; 259495d67482SBill Paul 259595d67482SBill Paul if (!sc->bge_tbi) 259695d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 259795d67482SBill Paul 259895d67482SBill Paul untimeout(bge_tick, sc, sc->bge_stat_ch); 259995d67482SBill Paul 260095d67482SBill Paul /* 260195d67482SBill Paul * Disable all of the receiver blocks 260295d67482SBill Paul */ 260395d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 260495d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 260595d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 260695d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 260795d67482SBill Paul BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 260895d67482SBill Paul BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 260995d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 261095d67482SBill Paul 261195d67482SBill Paul /* 261295d67482SBill Paul * Disable all of the transmit blocks 261395d67482SBill Paul */ 261495d67482SBill Paul BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 261595d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 261695d67482SBill Paul BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 261795d67482SBill Paul BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 261895d67482SBill Paul BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 261995d67482SBill Paul BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 262095d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 262195d67482SBill Paul 262295d67482SBill Paul /* 262395d67482SBill Paul * Shut down all of the memory managers and related 262495d67482SBill Paul * state machines. 262595d67482SBill Paul */ 262695d67482SBill Paul BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 262795d67482SBill Paul BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 262895d67482SBill Paul BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 262995d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 263095d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 263195d67482SBill Paul BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 263295d67482SBill Paul BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 263395d67482SBill Paul 263495d67482SBill Paul /* Disable host interrupts. */ 263595d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 263695d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 263795d67482SBill Paul 263895d67482SBill Paul /* 263995d67482SBill Paul * Tell firmware we're shutting down. 264095d67482SBill Paul */ 264195d67482SBill Paul BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 264295d67482SBill Paul 264395d67482SBill Paul /* Free the RX lists. */ 264495d67482SBill Paul bge_free_rx_ring_std(sc); 264595d67482SBill Paul 264695d67482SBill Paul /* Free jumbo RX list. */ 264795d67482SBill Paul bge_free_rx_ring_jumbo(sc); 264895d67482SBill Paul 264995d67482SBill Paul /* Free TX buffers. */ 265095d67482SBill Paul bge_free_tx_ring(sc); 265195d67482SBill Paul 265295d67482SBill Paul /* 265395d67482SBill Paul * Isolate/power down the PHY, but leave the media selection 265495d67482SBill Paul * unchanged so that things will be put back to normal when 265595d67482SBill Paul * we bring the interface back up. 265695d67482SBill Paul */ 265795d67482SBill Paul if (!sc->bge_tbi) { 265895d67482SBill Paul itmp = ifp->if_flags; 265995d67482SBill Paul ifp->if_flags |= IFF_UP; 266095d67482SBill Paul ifm = mii->mii_media.ifm_cur; 266195d67482SBill Paul mtmp = ifm->ifm_media; 266295d67482SBill Paul ifm->ifm_media = IFM_ETHER|IFM_NONE; 266395d67482SBill Paul mii_mediachg(mii); 266495d67482SBill Paul ifm->ifm_media = mtmp; 266595d67482SBill Paul ifp->if_flags = itmp; 266695d67482SBill Paul } 266795d67482SBill Paul 266895d67482SBill Paul sc->bge_link = 0; 266995d67482SBill Paul 267095d67482SBill Paul sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 267195d67482SBill Paul 267295d67482SBill Paul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 267395d67482SBill Paul 267495d67482SBill Paul return; 267595d67482SBill Paul } 267695d67482SBill Paul 267795d67482SBill Paul /* 267895d67482SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 267995d67482SBill Paul * get confused by errant DMAs when rebooting. 268095d67482SBill Paul */ 268195d67482SBill Paul static void 268295d67482SBill Paul bge_shutdown(dev) 268395d67482SBill Paul device_t dev; 268495d67482SBill Paul { 268595d67482SBill Paul struct bge_softc *sc; 268695d67482SBill Paul 268795d67482SBill Paul sc = device_get_softc(dev); 268895d67482SBill Paul 268995d67482SBill Paul bge_stop(sc); 269095d67482SBill Paul bge_reset(sc); 269195d67482SBill Paul 269295d67482SBill Paul return; 269395d67482SBill Paul } 2694