xref: /freebsd/sys/dev/bge/if_bge.c (revision 8a2e22dec0bedd7ba9f517ec3e7804adf0046876)
195d67482SBill Paul /*
295d67482SBill Paul  * Copyright (c) 2001 Wind River Systems
395d67482SBill Paul  * Copyright (c) 1997, 1998, 1999, 2001
495d67482SBill Paul  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
595d67482SBill Paul  *
695d67482SBill Paul  * Redistribution and use in source and binary forms, with or without
795d67482SBill Paul  * modification, are permitted provided that the following conditions
895d67482SBill Paul  * are met:
995d67482SBill Paul  * 1. Redistributions of source code must retain the above copyright
1095d67482SBill Paul  *    notice, this list of conditions and the following disclaimer.
1195d67482SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
1295d67482SBill Paul  *    notice, this list of conditions and the following disclaimer in the
1395d67482SBill Paul  *    documentation and/or other materials provided with the distribution.
1495d67482SBill Paul  * 3. All advertising materials mentioning features or use of this software
1595d67482SBill Paul  *    must display the following acknowledgement:
1695d67482SBill Paul  *	This product includes software developed by Bill Paul.
1795d67482SBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
1895d67482SBill Paul  *    may be used to endorse or promote products derived from this software
1995d67482SBill Paul  *    without specific prior written permission.
2095d67482SBill Paul  *
2195d67482SBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2295d67482SBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2395d67482SBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2495d67482SBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2595d67482SBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2695d67482SBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2795d67482SBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2895d67482SBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2995d67482SBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3095d67482SBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3195d67482SBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
3295d67482SBill Paul  */
3395d67482SBill Paul 
34aad970f1SDavid E. O'Brien #include <sys/cdefs.h>
35aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$");
36aad970f1SDavid E. O'Brien 
3795d67482SBill Paul /*
3895d67482SBill Paul  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
3995d67482SBill Paul  *
4095d67482SBill Paul  * The Broadcom BCM5700 is based on technology originally developed by
4195d67482SBill Paul  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
4295d67482SBill Paul  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
4395d67482SBill Paul  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
4495d67482SBill Paul  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
4595d67482SBill Paul  * frames, highly configurable RX filtering, and 16 RX and TX queues
4695d67482SBill Paul  * (which, along with RX filter rules, can be used for QOS applications).
4795d67482SBill Paul  * Other features, such as TCP segmentation, may be available as part
4895d67482SBill Paul  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
4995d67482SBill Paul  * firmware images can be stored in hardware and need not be compiled
5095d67482SBill Paul  * into the driver.
5195d67482SBill Paul  *
5295d67482SBill Paul  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
5395d67482SBill Paul  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
5495d67482SBill Paul  *
5595d67482SBill Paul  * The BCM5701 is a single-chip solution incorporating both the BCM5700
5698b28ee5SBill Paul  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
5795d67482SBill Paul  * does not support external SSRAM.
5895d67482SBill Paul  *
5995d67482SBill Paul  * Broadcom also produces a variation of the BCM5700 under the "Altima"
6095d67482SBill Paul  * brand name, which is functionally similar but lacks PCI-X support.
6195d67482SBill Paul  *
6295d67482SBill Paul  * Without external SSRAM, you can only have at most 4 TX rings,
6395d67482SBill Paul  * and the use of the mini RX ring is disabled. This seems to imply
6495d67482SBill Paul  * that these features are simply not available on the BCM5701. As a
6595d67482SBill Paul  * result, this driver does not implement any support for the mini RX
6695d67482SBill Paul  * ring.
6795d67482SBill Paul  */
6895d67482SBill Paul 
6995d67482SBill Paul #include <sys/param.h>
70f41ac2beSBill Paul #include <sys/endian.h>
7195d67482SBill Paul #include <sys/systm.h>
7295d67482SBill Paul #include <sys/sockio.h>
7395d67482SBill Paul #include <sys/mbuf.h>
7495d67482SBill Paul #include <sys/malloc.h>
7595d67482SBill Paul #include <sys/kernel.h>
76fe12f24bSPoul-Henning Kamp #include <sys/module.h>
7795d67482SBill Paul #include <sys/socket.h>
7895d67482SBill Paul #include <sys/queue.h>
7995d67482SBill Paul 
8095d67482SBill Paul #include <net/if.h>
8195d67482SBill Paul #include <net/if_arp.h>
8295d67482SBill Paul #include <net/ethernet.h>
8395d67482SBill Paul #include <net/if_dl.h>
8495d67482SBill Paul #include <net/if_media.h>
8595d67482SBill Paul 
8695d67482SBill Paul #include <net/bpf.h>
8795d67482SBill Paul 
8895d67482SBill Paul #include <net/if_types.h>
8995d67482SBill Paul #include <net/if_vlan_var.h>
9095d67482SBill Paul 
9195d67482SBill Paul #include <netinet/in_systm.h>
9295d67482SBill Paul #include <netinet/in.h>
9395d67482SBill Paul #include <netinet/ip.h>
9495d67482SBill Paul 
9595d67482SBill Paul #include <machine/clock.h>      /* for DELAY */
9695d67482SBill Paul #include <machine/bus_memio.h>
9795d67482SBill Paul #include <machine/bus.h>
9895d67482SBill Paul #include <machine/resource.h>
9995d67482SBill Paul #include <sys/bus.h>
10095d67482SBill Paul #include <sys/rman.h>
10195d67482SBill Paul 
10295d67482SBill Paul #include <dev/mii/mii.h>
10395d67482SBill Paul #include <dev/mii/miivar.h>
1042d3ce713SDavid E. O'Brien #include "miidevs.h"
10595d67482SBill Paul #include <dev/mii/brgphyreg.h>
10695d67482SBill Paul 
1074fbd232cSWarner Losh #include <dev/pci/pcireg.h>
1084fbd232cSWarner Losh #include <dev/pci/pcivar.h>
10995d67482SBill Paul 
11095d67482SBill Paul #include <dev/bge/if_bgereg.h>
11195d67482SBill Paul 
1125ddc5794SJohn Polstra #define BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
11395d67482SBill Paul 
114f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, pci, 1, 1, 1);
115f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, ether, 1, 1, 1);
11695d67482SBill Paul MODULE_DEPEND(bge, miibus, 1, 1, 1);
11795d67482SBill Paul 
11895d67482SBill Paul /* "controller miibus0" required.  See GENERIC if you get errors here. */
11995d67482SBill Paul #include "miibus_if.h"
12095d67482SBill Paul 
12195d67482SBill Paul /*
12295d67482SBill Paul  * Various supported device vendors/types and their names. Note: the
12395d67482SBill Paul  * spec seems to indicate that the hardware still has Alteon's vendor
12495d67482SBill Paul  * ID burned into it, though it will always be overriden by the vendor
12595d67482SBill Paul  * ID in the EEPROM. Just to be safe, we cover all possibilities.
12695d67482SBill Paul  */
127029e2ee3SJohn Polstra #define BGE_DEVDESC_MAX		64	/* Maximum device description length */
12895d67482SBill Paul 
12995d67482SBill Paul static struct bge_type bge_devs[] = {
13095d67482SBill Paul 	{ ALT_VENDORID,	ALT_DEVICEID_BCM5700,
13195d67482SBill Paul 		"Broadcom BCM5700 Gigabit Ethernet" },
13295d67482SBill Paul 	{ ALT_VENDORID,	ALT_DEVICEID_BCM5701,
13395d67482SBill Paul 		"Broadcom BCM5701 Gigabit Ethernet" },
13495d67482SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5700,
13595d67482SBill Paul 		"Broadcom BCM5700 Gigabit Ethernet" },
13695d67482SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5701,
13795d67482SBill Paul 		"Broadcom BCM5701 Gigabit Ethernet" },
1380434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702,
1390434d1b8SBill Paul 		"Broadcom BCM5702 Gigabit Ethernet" },
14001598b8dSMitsuru IWASAKI 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702X,
14101598b8dSMitsuru IWASAKI 		"Broadcom BCM5702X Gigabit Ethernet" },
1420434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703,
1430434d1b8SBill Paul 		"Broadcom BCM5703 Gigabit Ethernet" },
144b1265c1aSJohn Polstra 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703X,
145b1265c1aSJohn Polstra 		"Broadcom BCM5703X Gigabit Ethernet" },
1466ac6d2c8SPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704C,
1476ac6d2c8SPaul Saab 		"Broadcom BCM5704C Dual Gigabit Ethernet" },
1486ac6d2c8SPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
1496ac6d2c8SPaul Saab 		"Broadcom BCM5704S Dual Gigabit Ethernet" },
1500434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
1510434d1b8SBill Paul 		"Broadcom BCM5705 Gigabit Ethernet" },
152c001ccf2SPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
153c001ccf2SPaul Saab 		"Broadcom BCM5705K Gigabit Ethernet" },
1540434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
1550434d1b8SBill Paul 		"Broadcom BCM5705M Gigabit Ethernet" },
1560434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
1570434d1b8SBill Paul 		"Broadcom BCM5705M Gigabit Ethernet" },
158e53d81eeSPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
159e53d81eeSPaul Saab 		"Broadcom BCM5750 Gigabit Ethernet" },
160e53d81eeSPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750M,
161e53d81eeSPaul Saab 		"Broadcom BCM5750M Gigabit Ethernet" },
162e53d81eeSPaul Saab 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
163e53d81eeSPaul Saab 		"Broadcom BCM5751 Gigabit Ethernet" },
1640434d1b8SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
1650434d1b8SBill Paul 		"Broadcom BCM5782 Gigabit Ethernet" },
1669f71a4c2SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
1679f71a4c2SBill Paul 		"Broadcom BCM5788 Gigabit Ethernet" },
1685d99c641SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5901,
1695d99c641SBill Paul 		"Broadcom BCM5901 Fast Ethernet" },
1705d99c641SBill Paul 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,
1715d99c641SBill Paul 		"Broadcom BCM5901A2 Fast Ethernet" },
17295d67482SBill Paul 	{ SK_VENDORID, SK_DEVICEID_ALTIMA,
17395d67482SBill Paul 		"SysKonnect Gigabit Ethernet" },
174586d7c2eSJohn Polstra 	{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000,
175586d7c2eSJohn Polstra 		"Altima AC1000 Gigabit Ethernet" },
1762aae6624SBill Paul 	{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002,
1772aae6624SBill Paul 		"Altima AC1002 Gigabit Ethernet" },
178470bd96aSJohn Polstra 	{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100,
179470bd96aSJohn Polstra 		"Altima AC9100 Gigabit Ethernet" },
18095d67482SBill Paul 	{ 0, 0, NULL }
18195d67482SBill Paul };
18295d67482SBill Paul 
183e51a25f8SAlfred Perlstein static int bge_probe		(device_t);
184e51a25f8SAlfred Perlstein static int bge_attach		(device_t);
185e51a25f8SAlfred Perlstein static int bge_detach		(device_t);
18695d67482SBill Paul static void bge_release_resources
187e51a25f8SAlfred Perlstein 				(struct bge_softc *);
188f41ac2beSBill Paul static void bge_dma_map_addr	(void *, bus_dma_segment_t *, int, int);
189f41ac2beSBill Paul static void bge_dma_map_tx_desc	(void *, bus_dma_segment_t *, int,
190f41ac2beSBill Paul 				    bus_size_t, int);
191f41ac2beSBill Paul static int bge_dma_alloc	(device_t);
192f41ac2beSBill Paul static void bge_dma_free	(struct bge_softc *);
193f41ac2beSBill Paul 
194e51a25f8SAlfred Perlstein static void bge_txeof		(struct bge_softc *);
195e51a25f8SAlfred Perlstein static void bge_rxeof		(struct bge_softc *);
19695d67482SBill Paul 
1970f9bd73bSSam Leffler static void bge_tick_locked	(struct bge_softc *);
198e51a25f8SAlfred Perlstein static void bge_tick		(void *);
199e51a25f8SAlfred Perlstein static void bge_stats_update	(struct bge_softc *);
2000434d1b8SBill Paul static void bge_stats_update_regs
2010434d1b8SBill Paul 				(struct bge_softc *);
202e51a25f8SAlfred Perlstein static int bge_encap		(struct bge_softc *, struct mbuf *,
203e51a25f8SAlfred Perlstein 					u_int32_t *);
20495d67482SBill Paul 
205e51a25f8SAlfred Perlstein static void bge_intr		(void *);
2060f9bd73bSSam Leffler static void bge_start_locked	(struct ifnet *);
207e51a25f8SAlfred Perlstein static void bge_start		(struct ifnet *);
208e51a25f8SAlfred Perlstein static int bge_ioctl		(struct ifnet *, u_long, caddr_t);
2090f9bd73bSSam Leffler static void bge_init_locked	(struct bge_softc *);
210e51a25f8SAlfred Perlstein static void bge_init		(void *);
211e51a25f8SAlfred Perlstein static void bge_stop		(struct bge_softc *);
212e51a25f8SAlfred Perlstein static void bge_watchdog		(struct ifnet *);
213e51a25f8SAlfred Perlstein static void bge_shutdown		(device_t);
214e51a25f8SAlfred Perlstein static int bge_ifmedia_upd	(struct ifnet *);
215e51a25f8SAlfred Perlstein static void bge_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
21695d67482SBill Paul 
217e51a25f8SAlfred Perlstein static u_int8_t	bge_eeprom_getbyte	(struct bge_softc *, int, u_int8_t *);
218e51a25f8SAlfred Perlstein static int bge_read_eeprom	(struct bge_softc *, caddr_t, int, int);
21995d67482SBill Paul 
220e51a25f8SAlfred Perlstein static void bge_setmulti	(struct bge_softc *);
22195d67482SBill Paul 
222e51a25f8SAlfred Perlstein static void bge_handle_events	(struct bge_softc *);
223e51a25f8SAlfred Perlstein static int bge_alloc_jumbo_mem	(struct bge_softc *);
224e51a25f8SAlfred Perlstein static void bge_free_jumbo_mem	(struct bge_softc *);
225e51a25f8SAlfred Perlstein static void *bge_jalloc		(struct bge_softc *);
226914596abSAlfred Perlstein static void bge_jfree		(void *, void *);
227e51a25f8SAlfred Perlstein static int bge_newbuf_std	(struct bge_softc *, int, struct mbuf *);
228e51a25f8SAlfred Perlstein static int bge_newbuf_jumbo	(struct bge_softc *, int, struct mbuf *);
229e51a25f8SAlfred Perlstein static int bge_init_rx_ring_std	(struct bge_softc *);
230e51a25f8SAlfred Perlstein static void bge_free_rx_ring_std	(struct bge_softc *);
231e51a25f8SAlfred Perlstein static int bge_init_rx_ring_jumbo	(struct bge_softc *);
232e51a25f8SAlfred Perlstein static void bge_free_rx_ring_jumbo	(struct bge_softc *);
233e51a25f8SAlfred Perlstein static void bge_free_tx_ring	(struct bge_softc *);
234e51a25f8SAlfred Perlstein static int bge_init_tx_ring	(struct bge_softc *);
23595d67482SBill Paul 
236e51a25f8SAlfred Perlstein static int bge_chipinit		(struct bge_softc *);
237e51a25f8SAlfred Perlstein static int bge_blockinit	(struct bge_softc *);
23895d67482SBill Paul 
2391b4a3b2fSPeter Wemm #ifdef notdef
240e51a25f8SAlfred Perlstein static u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
241e51a25f8SAlfred Perlstein static void bge_vpd_read_res	(struct bge_softc *, struct vpd_res *, int);
242e51a25f8SAlfred Perlstein static void bge_vpd_read	(struct bge_softc *);
2431b4a3b2fSPeter Wemm #endif
24495d67482SBill Paul 
24595d67482SBill Paul static u_int32_t bge_readmem_ind
246e51a25f8SAlfred Perlstein 				(struct bge_softc *, int);
247e51a25f8SAlfred Perlstein static void bge_writemem_ind	(struct bge_softc *, int, int);
24895d67482SBill Paul #ifdef notdef
24995d67482SBill Paul static u_int32_t bge_readreg_ind
250e51a25f8SAlfred Perlstein 				(struct bge_softc *, int);
25195d67482SBill Paul #endif
252e51a25f8SAlfred Perlstein static void bge_writereg_ind	(struct bge_softc *, int, int);
25395d67482SBill Paul 
254e51a25f8SAlfred Perlstein static int bge_miibus_readreg	(device_t, int, int);
255e51a25f8SAlfred Perlstein static int bge_miibus_writereg	(device_t, int, int, int);
256e51a25f8SAlfred Perlstein static void bge_miibus_statchg	(device_t);
25795d67482SBill Paul 
258e51a25f8SAlfred Perlstein static void bge_reset		(struct bge_softc *);
25995d67482SBill Paul 
26095d67482SBill Paul static device_method_t bge_methods[] = {
26195d67482SBill Paul 	/* Device interface */
26295d67482SBill Paul 	DEVMETHOD(device_probe,		bge_probe),
26395d67482SBill Paul 	DEVMETHOD(device_attach,	bge_attach),
26495d67482SBill Paul 	DEVMETHOD(device_detach,	bge_detach),
26595d67482SBill Paul 	DEVMETHOD(device_shutdown,	bge_shutdown),
26695d67482SBill Paul 
26795d67482SBill Paul 	/* bus interface */
26895d67482SBill Paul 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
26995d67482SBill Paul 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
27095d67482SBill Paul 
27195d67482SBill Paul 	/* MII interface */
27295d67482SBill Paul 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
27395d67482SBill Paul 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
27495d67482SBill Paul 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
27595d67482SBill Paul 
27695d67482SBill Paul 	{ 0, 0 }
27795d67482SBill Paul };
27895d67482SBill Paul 
27995d67482SBill Paul static driver_t bge_driver = {
28095d67482SBill Paul 	"bge",
28195d67482SBill Paul 	bge_methods,
28295d67482SBill Paul 	sizeof(struct bge_softc)
28395d67482SBill Paul };
28495d67482SBill Paul 
28595d67482SBill Paul static devclass_t bge_devclass;
28695d67482SBill Paul 
287f246e4a1SMatthew N. Dodd DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
28895d67482SBill Paul DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
28995d67482SBill Paul 
29095d67482SBill Paul static u_int32_t
29195d67482SBill Paul bge_readmem_ind(sc, off)
29295d67482SBill Paul 	struct bge_softc *sc;
29395d67482SBill Paul 	int off;
29495d67482SBill Paul {
29595d67482SBill Paul 	device_t dev;
29695d67482SBill Paul 
29795d67482SBill Paul 	dev = sc->bge_dev;
29895d67482SBill Paul 
29995d67482SBill Paul 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
30095d67482SBill Paul 	return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
30195d67482SBill Paul }
30295d67482SBill Paul 
30395d67482SBill Paul static void
30495d67482SBill Paul bge_writemem_ind(sc, off, val)
30595d67482SBill Paul 	struct bge_softc *sc;
30695d67482SBill Paul 	int off, val;
30795d67482SBill Paul {
30895d67482SBill Paul 	device_t dev;
30995d67482SBill Paul 
31095d67482SBill Paul 	dev = sc->bge_dev;
31195d67482SBill Paul 
31295d67482SBill Paul 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
31395d67482SBill Paul 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
31495d67482SBill Paul 
31595d67482SBill Paul 	return;
31695d67482SBill Paul }
31795d67482SBill Paul 
31895d67482SBill Paul #ifdef notdef
31995d67482SBill Paul static u_int32_t
32095d67482SBill Paul bge_readreg_ind(sc, off)
32195d67482SBill Paul 	struct bge_softc *sc;
32295d67482SBill Paul 	int off;
32395d67482SBill Paul {
32495d67482SBill Paul 	device_t dev;
32595d67482SBill Paul 
32695d67482SBill Paul 	dev = sc->bge_dev;
32795d67482SBill Paul 
32895d67482SBill Paul 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
32995d67482SBill Paul 	return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
33095d67482SBill Paul }
33195d67482SBill Paul #endif
33295d67482SBill Paul 
33395d67482SBill Paul static void
33495d67482SBill Paul bge_writereg_ind(sc, off, val)
33595d67482SBill Paul 	struct bge_softc *sc;
33695d67482SBill Paul 	int off, val;
33795d67482SBill Paul {
33895d67482SBill Paul 	device_t dev;
33995d67482SBill Paul 
34095d67482SBill Paul 	dev = sc->bge_dev;
34195d67482SBill Paul 
34295d67482SBill Paul 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
34395d67482SBill Paul 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
34495d67482SBill Paul 
34595d67482SBill Paul 	return;
34695d67482SBill Paul }
34795d67482SBill Paul 
348f41ac2beSBill Paul /*
349f41ac2beSBill Paul  * Map a single buffer address.
350f41ac2beSBill Paul  */
351f41ac2beSBill Paul 
352f41ac2beSBill Paul static void
353f41ac2beSBill Paul bge_dma_map_addr(arg, segs, nseg, error)
354f41ac2beSBill Paul 	void *arg;
355f41ac2beSBill Paul 	bus_dma_segment_t *segs;
356f41ac2beSBill Paul 	int nseg;
357f41ac2beSBill Paul 	int error;
358f41ac2beSBill Paul {
359f41ac2beSBill Paul 	struct bge_dmamap_arg *ctx;
360f41ac2beSBill Paul 
361f41ac2beSBill Paul 	if (error)
362f41ac2beSBill Paul 		return;
363f41ac2beSBill Paul 
364f41ac2beSBill Paul 	ctx = arg;
365f41ac2beSBill Paul 
366f41ac2beSBill Paul 	if (nseg > ctx->bge_maxsegs) {
367f41ac2beSBill Paul 		ctx->bge_maxsegs = 0;
368f41ac2beSBill Paul 		return;
369f41ac2beSBill Paul 	}
370f41ac2beSBill Paul 
371f41ac2beSBill Paul 	ctx->bge_busaddr = segs->ds_addr;
372f41ac2beSBill Paul 
373f41ac2beSBill Paul 	return;
374f41ac2beSBill Paul }
375f41ac2beSBill Paul 
376f41ac2beSBill Paul /*
377f41ac2beSBill Paul  * Map an mbuf chain into an TX ring.
378f41ac2beSBill Paul  */
379f41ac2beSBill Paul 
380f41ac2beSBill Paul static void
381f41ac2beSBill Paul bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error)
382f41ac2beSBill Paul 	void *arg;
383f41ac2beSBill Paul 	bus_dma_segment_t *segs;
384f41ac2beSBill Paul 	int nseg;
385f41ac2beSBill Paul 	bus_size_t mapsize;
386f41ac2beSBill Paul 	int error;
387f41ac2beSBill Paul {
388f41ac2beSBill Paul 	struct bge_dmamap_arg *ctx;
389f41ac2beSBill Paul 	struct bge_tx_bd *d = NULL;
390f41ac2beSBill Paul 	int i = 0, idx;
391f41ac2beSBill Paul 
392f41ac2beSBill Paul 	if (error)
393f41ac2beSBill Paul 		return;
394f41ac2beSBill Paul 
395f41ac2beSBill Paul 	ctx = arg;
396f41ac2beSBill Paul 
397f41ac2beSBill Paul 	/* Signal error to caller if there's too many segments */
398f41ac2beSBill Paul 	if (nseg > ctx->bge_maxsegs) {
399f41ac2beSBill Paul 		ctx->bge_maxsegs = 0;
400f41ac2beSBill Paul 		return;
401f41ac2beSBill Paul 	}
402f41ac2beSBill Paul 
403f41ac2beSBill Paul 	idx = ctx->bge_idx;
404f41ac2beSBill Paul 	while(1) {
405f41ac2beSBill Paul 		d = &ctx->bge_ring[idx];
406f41ac2beSBill Paul 		d->bge_addr.bge_addr_lo =
407f41ac2beSBill Paul 		    htole32(BGE_ADDR_LO(segs[i].ds_addr));
408f41ac2beSBill Paul 		d->bge_addr.bge_addr_hi =
409f41ac2beSBill Paul 		    htole32(BGE_ADDR_HI(segs[i].ds_addr));
410f41ac2beSBill Paul 		d->bge_len = htole16(segs[i].ds_len);
411f41ac2beSBill Paul 		d->bge_flags = htole16(ctx->bge_flags);
412f41ac2beSBill Paul                 i++;
413f41ac2beSBill Paul 		if (i == nseg)
414f41ac2beSBill Paul 			break;
415f41ac2beSBill Paul 		BGE_INC(idx, BGE_TX_RING_CNT);
416f41ac2beSBill Paul 	}
417f41ac2beSBill Paul 
418f41ac2beSBill Paul 	d->bge_flags |= htole16(BGE_TXBDFLAG_END);
419f41ac2beSBill Paul 	ctx->bge_maxsegs = nseg;
420f41ac2beSBill Paul 	ctx->bge_idx = idx;
421f41ac2beSBill Paul 
422f41ac2beSBill Paul 	return;
423f41ac2beSBill Paul }
424f41ac2beSBill Paul 
425f41ac2beSBill Paul 
4261b4a3b2fSPeter Wemm #ifdef notdef
42795d67482SBill Paul static u_int8_t
42895d67482SBill Paul bge_vpd_readbyte(sc, addr)
42995d67482SBill Paul 	struct bge_softc *sc;
43095d67482SBill Paul 	int addr;
43195d67482SBill Paul {
43295d67482SBill Paul 	int i;
43395d67482SBill Paul 	device_t dev;
43495d67482SBill Paul 	u_int32_t val;
43595d67482SBill Paul 
43695d67482SBill Paul 	dev = sc->bge_dev;
43795d67482SBill Paul 	pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
43895d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
43995d67482SBill Paul 		DELAY(10);
44095d67482SBill Paul 		if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
44195d67482SBill Paul 			break;
44295d67482SBill Paul 	}
44395d67482SBill Paul 
44495d67482SBill Paul 	if (i == BGE_TIMEOUT) {
44595d67482SBill Paul 		printf("bge%d: VPD read timed out\n", sc->bge_unit);
44695d67482SBill Paul 		return(0);
44795d67482SBill Paul 	}
44895d67482SBill Paul 
44995d67482SBill Paul 	val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
45095d67482SBill Paul 
45195d67482SBill Paul 	return((val >> ((addr % 4) * 8)) & 0xFF);
45295d67482SBill Paul }
45395d67482SBill Paul 
45495d67482SBill Paul static void
45595d67482SBill Paul bge_vpd_read_res(sc, res, addr)
45695d67482SBill Paul 	struct bge_softc *sc;
45795d67482SBill Paul 	struct vpd_res *res;
45895d67482SBill Paul 	int addr;
45995d67482SBill Paul {
46095d67482SBill Paul 	int i;
46195d67482SBill Paul 	u_int8_t *ptr;
46295d67482SBill Paul 
46395d67482SBill Paul 	ptr = (u_int8_t *)res;
46495d67482SBill Paul 	for (i = 0; i < sizeof(struct vpd_res); i++)
46595d67482SBill Paul 		ptr[i] = bge_vpd_readbyte(sc, i + addr);
46695d67482SBill Paul 
46795d67482SBill Paul 	return;
46895d67482SBill Paul }
46995d67482SBill Paul 
47095d67482SBill Paul static void
47195d67482SBill Paul bge_vpd_read(sc)
47295d67482SBill Paul 	struct bge_softc *sc;
47395d67482SBill Paul {
47495d67482SBill Paul 	int pos = 0, i;
47595d67482SBill Paul 	struct vpd_res res;
47695d67482SBill Paul 
47795d67482SBill Paul 	if (sc->bge_vpd_prodname != NULL)
47895d67482SBill Paul 		free(sc->bge_vpd_prodname, M_DEVBUF);
47995d67482SBill Paul 	if (sc->bge_vpd_readonly != NULL)
48095d67482SBill Paul 		free(sc->bge_vpd_readonly, M_DEVBUF);
48195d67482SBill Paul 	sc->bge_vpd_prodname = NULL;
48295d67482SBill Paul 	sc->bge_vpd_readonly = NULL;
48395d67482SBill Paul 
48495d67482SBill Paul 	bge_vpd_read_res(sc, &res, pos);
48595d67482SBill Paul 
48695d67482SBill Paul 	if (res.vr_id != VPD_RES_ID) {
48795d67482SBill Paul 		printf("bge%d: bad VPD resource id: expected %x got %x\n",
48895d67482SBill Paul 			sc->bge_unit, VPD_RES_ID, res.vr_id);
48995d67482SBill Paul                 return;
49095d67482SBill Paul         }
49195d67482SBill Paul 
49295d67482SBill Paul 	pos += sizeof(res);
49395d67482SBill Paul 	sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
49495d67482SBill Paul 	for (i = 0; i < res.vr_len; i++)
49595d67482SBill Paul 		sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
49695d67482SBill Paul 	sc->bge_vpd_prodname[i] = '\0';
49795d67482SBill Paul 	pos += i;
49895d67482SBill Paul 
49995d67482SBill Paul 	bge_vpd_read_res(sc, &res, pos);
50095d67482SBill Paul 
50195d67482SBill Paul 	if (res.vr_id != VPD_RES_READ) {
50295d67482SBill Paul 		printf("bge%d: bad VPD resource id: expected %x got %x\n",
50395d67482SBill Paul 		    sc->bge_unit, VPD_RES_READ, res.vr_id);
50495d67482SBill Paul 		return;
50595d67482SBill Paul 	}
50695d67482SBill Paul 
50795d67482SBill Paul 	pos += sizeof(res);
50895d67482SBill Paul 	sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
50995d67482SBill Paul 	for (i = 0; i < res.vr_len + 1; i++)
51095d67482SBill Paul 		sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
51195d67482SBill Paul 
51295d67482SBill Paul 	return;
51395d67482SBill Paul }
5141b4a3b2fSPeter Wemm #endif
51595d67482SBill Paul 
51695d67482SBill Paul /*
51795d67482SBill Paul  * Read a byte of data stored in the EEPROM at address 'addr.' The
51895d67482SBill Paul  * BCM570x supports both the traditional bitbang interface and an
51995d67482SBill Paul  * auto access interface for reading the EEPROM. We use the auto
52095d67482SBill Paul  * access method.
52195d67482SBill Paul  */
52295d67482SBill Paul static u_int8_t
52395d67482SBill Paul bge_eeprom_getbyte(sc, addr, dest)
52495d67482SBill Paul 	struct bge_softc *sc;
52595d67482SBill Paul 	int addr;
52695d67482SBill Paul 	u_int8_t *dest;
52795d67482SBill Paul {
52895d67482SBill Paul 	int i;
52995d67482SBill Paul 	u_int32_t byte = 0;
53095d67482SBill Paul 
53195d67482SBill Paul 	/*
53295d67482SBill Paul 	 * Enable use of auto EEPROM access so we can avoid
53395d67482SBill Paul 	 * having to use the bitbang method.
53495d67482SBill Paul 	 */
53595d67482SBill Paul 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
53695d67482SBill Paul 
53795d67482SBill Paul 	/* Reset the EEPROM, load the clock period. */
53895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_EE_ADDR,
53995d67482SBill Paul 	    BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
54095d67482SBill Paul 	DELAY(20);
54195d67482SBill Paul 
54295d67482SBill Paul 	/* Issue the read EEPROM command. */
54395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
54495d67482SBill Paul 
54595d67482SBill Paul 	/* Wait for completion */
54695d67482SBill Paul 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
54795d67482SBill Paul 		DELAY(10);
54895d67482SBill Paul 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
54995d67482SBill Paul 			break;
55095d67482SBill Paul 	}
55195d67482SBill Paul 
55295d67482SBill Paul 	if (i == BGE_TIMEOUT) {
55395d67482SBill Paul 		printf("bge%d: eeprom read timed out\n", sc->bge_unit);
55495d67482SBill Paul 		return(0);
55595d67482SBill Paul 	}
55695d67482SBill Paul 
55795d67482SBill Paul 	/* Get result. */
55895d67482SBill Paul 	byte = CSR_READ_4(sc, BGE_EE_DATA);
55995d67482SBill Paul 
56095d67482SBill Paul         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
56195d67482SBill Paul 
56295d67482SBill Paul 	return(0);
56395d67482SBill Paul }
56495d67482SBill Paul 
56595d67482SBill Paul /*
56695d67482SBill Paul  * Read a sequence of bytes from the EEPROM.
56795d67482SBill Paul  */
56895d67482SBill Paul static int
56995d67482SBill Paul bge_read_eeprom(sc, dest, off, cnt)
57095d67482SBill Paul 	struct bge_softc *sc;
57195d67482SBill Paul 	caddr_t dest;
57295d67482SBill Paul 	int off;
57395d67482SBill Paul 	int cnt;
57495d67482SBill Paul {
57595d67482SBill Paul 	int err = 0, i;
57695d67482SBill Paul 	u_int8_t byte = 0;
57795d67482SBill Paul 
57895d67482SBill Paul 	for (i = 0; i < cnt; i++) {
57995d67482SBill Paul 		err = bge_eeprom_getbyte(sc, off + i, &byte);
58095d67482SBill Paul 		if (err)
58195d67482SBill Paul 			break;
58295d67482SBill Paul 		*(dest + i) = byte;
58395d67482SBill Paul 	}
58495d67482SBill Paul 
58595d67482SBill Paul 	return(err ? 1 : 0);
58695d67482SBill Paul }
58795d67482SBill Paul 
58895d67482SBill Paul static int
58995d67482SBill Paul bge_miibus_readreg(dev, phy, reg)
59095d67482SBill Paul 	device_t dev;
59195d67482SBill Paul 	int phy, reg;
59295d67482SBill Paul {
59395d67482SBill Paul 	struct bge_softc *sc;
59437ceeb4dSPaul Saab 	u_int32_t val, autopoll;
59595d67482SBill Paul 	int i;
59695d67482SBill Paul 
59795d67482SBill Paul 	sc = device_get_softc(dev);
59895d67482SBill Paul 
5990434d1b8SBill Paul 	/*
6000434d1b8SBill Paul 	 * Broadcom's own driver always assumes the internal
6010434d1b8SBill Paul 	 * PHY is at GMII address 1. On some chips, the PHY responds
6020434d1b8SBill Paul 	 * to accesses at all addresses, which could cause us to
6030434d1b8SBill Paul 	 * bogusly attach the PHY 32 times at probe type. Always
6040434d1b8SBill Paul 	 * restricting the lookup to address 1 is simpler than
6050434d1b8SBill Paul 	 * trying to figure out which chips revisions should be
6060434d1b8SBill Paul 	 * special-cased.
6070434d1b8SBill Paul 	 */
608b1265c1aSJohn Polstra 	if (phy != 1)
60998b28ee5SBill Paul 		return(0);
61098b28ee5SBill Paul 
61137ceeb4dSPaul Saab 	/* Reading with autopolling on may trigger PCI errors */
61237ceeb4dSPaul Saab 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
61337ceeb4dSPaul Saab 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
61437ceeb4dSPaul Saab 		BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
61537ceeb4dSPaul Saab 		DELAY(40);
61637ceeb4dSPaul Saab 	}
61737ceeb4dSPaul Saab 
61895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
61995d67482SBill Paul 	    BGE_MIPHY(phy)|BGE_MIREG(reg));
62095d67482SBill Paul 
62195d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
62295d67482SBill Paul 		val = CSR_READ_4(sc, BGE_MI_COMM);
62395d67482SBill Paul 		if (!(val & BGE_MICOMM_BUSY))
62495d67482SBill Paul 			break;
62595d67482SBill Paul 	}
62695d67482SBill Paul 
62795d67482SBill Paul 	if (i == BGE_TIMEOUT) {
62895d67482SBill Paul 		printf("bge%d: PHY read timed out\n", sc->bge_unit);
62937ceeb4dSPaul Saab 		val = 0;
63037ceeb4dSPaul Saab 		goto done;
63195d67482SBill Paul 	}
63295d67482SBill Paul 
63395d67482SBill Paul 	val = CSR_READ_4(sc, BGE_MI_COMM);
63495d67482SBill Paul 
63537ceeb4dSPaul Saab done:
63637ceeb4dSPaul Saab 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
63737ceeb4dSPaul Saab 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
63837ceeb4dSPaul Saab 		DELAY(40);
63937ceeb4dSPaul Saab 	}
64037ceeb4dSPaul Saab 
64195d67482SBill Paul 	if (val & BGE_MICOMM_READFAIL)
64295d67482SBill Paul 		return(0);
64395d67482SBill Paul 
64495d67482SBill Paul 	return(val & 0xFFFF);
64595d67482SBill Paul }
64695d67482SBill Paul 
64795d67482SBill Paul static int
64895d67482SBill Paul bge_miibus_writereg(dev, phy, reg, val)
64995d67482SBill Paul 	device_t dev;
65095d67482SBill Paul 	int phy, reg, val;
65195d67482SBill Paul {
65295d67482SBill Paul 	struct bge_softc *sc;
65337ceeb4dSPaul Saab 	u_int32_t autopoll;
65495d67482SBill Paul 	int i;
65595d67482SBill Paul 
65695d67482SBill Paul 	sc = device_get_softc(dev);
65795d67482SBill Paul 
65837ceeb4dSPaul Saab 	/* Reading with autopolling on may trigger PCI errors */
65937ceeb4dSPaul Saab 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
66037ceeb4dSPaul Saab 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
66137ceeb4dSPaul Saab 		BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
66237ceeb4dSPaul Saab 		DELAY(40);
66337ceeb4dSPaul Saab 	}
66437ceeb4dSPaul Saab 
66595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
66695d67482SBill Paul 	    BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
66795d67482SBill Paul 
66895d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
66995d67482SBill Paul 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
67095d67482SBill Paul 			break;
67195d67482SBill Paul 	}
67295d67482SBill Paul 
67337ceeb4dSPaul Saab 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
67437ceeb4dSPaul Saab 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
67537ceeb4dSPaul Saab 		DELAY(40);
67637ceeb4dSPaul Saab 	}
67737ceeb4dSPaul Saab 
67895d67482SBill Paul 	if (i == BGE_TIMEOUT) {
67995d67482SBill Paul 		printf("bge%d: PHY read timed out\n", sc->bge_unit);
68095d67482SBill Paul 		return(0);
68195d67482SBill Paul 	}
68295d67482SBill Paul 
68395d67482SBill Paul 	return(0);
68495d67482SBill Paul }
68595d67482SBill Paul 
68695d67482SBill Paul static void
68795d67482SBill Paul bge_miibus_statchg(dev)
68895d67482SBill Paul 	device_t dev;
68995d67482SBill Paul {
69095d67482SBill Paul 	struct bge_softc *sc;
69195d67482SBill Paul 	struct mii_data *mii;
69295d67482SBill Paul 
69395d67482SBill Paul 	sc = device_get_softc(dev);
69495d67482SBill Paul 	mii = device_get_softc(sc->bge_miibus);
69595d67482SBill Paul 
69695d67482SBill Paul 	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
697b418ad5cSPoul-Henning Kamp 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
69895d67482SBill Paul 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
69995d67482SBill Paul 	} else {
70095d67482SBill Paul 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
70195d67482SBill Paul 	}
70295d67482SBill Paul 
70395d67482SBill Paul 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
70495d67482SBill Paul 		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
70595d67482SBill Paul 	} else {
70695d67482SBill Paul 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
70795d67482SBill Paul 	}
70895d67482SBill Paul 
70995d67482SBill Paul 	return;
71095d67482SBill Paul }
71195d67482SBill Paul 
71295d67482SBill Paul /*
71395d67482SBill Paul  * Handle events that have triggered interrupts.
71495d67482SBill Paul  */
71595d67482SBill Paul static void
71695d67482SBill Paul bge_handle_events(sc)
71795d67482SBill Paul 	struct bge_softc		*sc;
71895d67482SBill Paul {
71995d67482SBill Paul 
72095d67482SBill Paul 	return;
72195d67482SBill Paul }
72295d67482SBill Paul 
72395d67482SBill Paul /*
72495d67482SBill Paul  * Memory management for jumbo frames.
72595d67482SBill Paul  */
72695d67482SBill Paul 
72795d67482SBill Paul static int
72895d67482SBill Paul bge_alloc_jumbo_mem(sc)
72995d67482SBill Paul 	struct bge_softc		*sc;
73095d67482SBill Paul {
73195d67482SBill Paul 	caddr_t			ptr;
732f41ac2beSBill Paul 	register int		i, error;
73395d67482SBill Paul 	struct bge_jpool_entry   *entry;
73495d67482SBill Paul 
735f41ac2beSBill Paul 	/* Create tag for jumbo buffer block */
73695d67482SBill Paul 
737f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
738f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
739f41ac2beSBill Paul 	    NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL,
740f41ac2beSBill Paul 	    &sc->bge_cdata.bge_jumbo_tag);
741f41ac2beSBill Paul 
742f41ac2beSBill Paul 	if (error) {
743f41ac2beSBill Paul 		printf("bge%d: could not allocate jumbo dma tag\n",
744f41ac2beSBill Paul 		    sc->bge_unit);
745f41ac2beSBill Paul 		return (ENOMEM);
74695d67482SBill Paul 	}
74795d67482SBill Paul 
748f41ac2beSBill Paul 	/* Allocate DMA'able memory for jumbo buffer block */
749f41ac2beSBill Paul 
750f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag,
751f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT,
752f41ac2beSBill Paul 	    &sc->bge_cdata.bge_jumbo_map);
753f41ac2beSBill Paul 
754f41ac2beSBill Paul 	if (error)
755f41ac2beSBill Paul                 return (ENOMEM);
756f41ac2beSBill Paul 
75795d67482SBill Paul 	SLIST_INIT(&sc->bge_jfree_listhead);
75895d67482SBill Paul 	SLIST_INIT(&sc->bge_jinuse_listhead);
75995d67482SBill Paul 
76095d67482SBill Paul 	/*
76195d67482SBill Paul 	 * Now divide it up into 9K pieces and save the addresses
76295d67482SBill Paul 	 * in an array.
76395d67482SBill Paul 	 */
764f41ac2beSBill Paul 	ptr = sc->bge_ldata.bge_jumbo_buf;
76595d67482SBill Paul 	for (i = 0; i < BGE_JSLOTS; i++) {
76695d67482SBill Paul 		sc->bge_cdata.bge_jslots[i] = ptr;
76795d67482SBill Paul 		ptr += BGE_JLEN;
76895d67482SBill Paul 		entry = malloc(sizeof(struct bge_jpool_entry),
76995d67482SBill Paul 		    M_DEVBUF, M_NOWAIT);
77095d67482SBill Paul 		if (entry == NULL) {
771f41ac2beSBill Paul 			bge_free_jumbo_mem(sc);
772f41ac2beSBill Paul 			sc->bge_ldata.bge_jumbo_buf = NULL;
77395d67482SBill Paul 			printf("bge%d: no memory for jumbo "
77495d67482SBill Paul 			    "buffer queue!\n", sc->bge_unit);
77595d67482SBill Paul 			return(ENOBUFS);
77695d67482SBill Paul 		}
77795d67482SBill Paul 		entry->slot = i;
77895d67482SBill Paul 		SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
77995d67482SBill Paul 		    entry, jpool_entries);
78095d67482SBill Paul 	}
78195d67482SBill Paul 
78295d67482SBill Paul 	return(0);
78395d67482SBill Paul }
78495d67482SBill Paul 
78595d67482SBill Paul static void
78695d67482SBill Paul bge_free_jumbo_mem(sc)
78795d67482SBill Paul         struct bge_softc *sc;
78895d67482SBill Paul {
78995d67482SBill Paul         int i;
79095d67482SBill Paul         struct bge_jpool_entry *entry;
79195d67482SBill Paul 
79295d67482SBill Paul 	for (i = 0; i < BGE_JSLOTS; i++) {
79395d67482SBill Paul 		entry = SLIST_FIRST(&sc->bge_jfree_listhead);
79495d67482SBill Paul 		SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
79595d67482SBill Paul 		free(entry, M_DEVBUF);
79695d67482SBill Paul 	}
79795d67482SBill Paul 
798f41ac2beSBill Paul 	/* Destroy jumbo buffer block */
799f41ac2beSBill Paul 
800f41ac2beSBill Paul 	if (sc->bge_ldata.bge_rx_jumbo_ring)
801f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag,
802f41ac2beSBill Paul 		    sc->bge_ldata.bge_jumbo_buf,
803f41ac2beSBill Paul 		    sc->bge_cdata.bge_jumbo_map);
804f41ac2beSBill Paul 
805f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_jumbo_ring_map)
806f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag,
807f41ac2beSBill Paul 		    sc->bge_cdata.bge_jumbo_map);
808f41ac2beSBill Paul 
809f41ac2beSBill Paul 	if (sc->bge_cdata.bge_jumbo_tag)
810f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag);
81195d67482SBill Paul 
81295d67482SBill Paul         return;
81395d67482SBill Paul }
81495d67482SBill Paul 
81595d67482SBill Paul /*
81695d67482SBill Paul  * Allocate a jumbo buffer.
81795d67482SBill Paul  */
81895d67482SBill Paul static void *
81995d67482SBill Paul bge_jalloc(sc)
82095d67482SBill Paul 	struct bge_softc		*sc;
82195d67482SBill Paul {
82295d67482SBill Paul 	struct bge_jpool_entry   *entry;
82395d67482SBill Paul 
82495d67482SBill Paul 	entry = SLIST_FIRST(&sc->bge_jfree_listhead);
82595d67482SBill Paul 
82695d67482SBill Paul 	if (entry == NULL) {
82795d67482SBill Paul 		printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
82895d67482SBill Paul 		return(NULL);
82995d67482SBill Paul 	}
83095d67482SBill Paul 
83195d67482SBill Paul 	SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
83295d67482SBill Paul 	SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
83395d67482SBill Paul 	return(sc->bge_cdata.bge_jslots[entry->slot]);
83495d67482SBill Paul }
83595d67482SBill Paul 
83695d67482SBill Paul /*
83795d67482SBill Paul  * Release a jumbo buffer.
83895d67482SBill Paul  */
83995d67482SBill Paul static void
84095d67482SBill Paul bge_jfree(buf, args)
841914596abSAlfred Perlstein 	void *buf;
84295d67482SBill Paul 	void *args;
84395d67482SBill Paul {
84495d67482SBill Paul 	struct bge_jpool_entry *entry;
84595d67482SBill Paul 	struct bge_softc *sc;
84695d67482SBill Paul 	int i;
84795d67482SBill Paul 
84895d67482SBill Paul 	/* Extract the softc struct pointer. */
84995d67482SBill Paul 	sc = (struct bge_softc *)args;
85095d67482SBill Paul 
85195d67482SBill Paul 	if (sc == NULL)
85295d67482SBill Paul 		panic("bge_jfree: can't find softc pointer!");
85395d67482SBill Paul 
85495d67482SBill Paul 	/* calculate the slot this buffer belongs to */
85595d67482SBill Paul 
85695d67482SBill Paul 	i = ((vm_offset_t)buf
857f41ac2beSBill Paul 	     - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN;
85895d67482SBill Paul 
85995d67482SBill Paul 	if ((i < 0) || (i >= BGE_JSLOTS))
86095d67482SBill Paul 		panic("bge_jfree: asked to free buffer that we don't manage!");
86195d67482SBill Paul 
86295d67482SBill Paul 	entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
86395d67482SBill Paul 	if (entry == NULL)
86495d67482SBill Paul 		panic("bge_jfree: buffer not in use!");
86595d67482SBill Paul 	entry->slot = i;
86695d67482SBill Paul 	SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
86795d67482SBill Paul 	SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
86895d67482SBill Paul 
86995d67482SBill Paul 	return;
87095d67482SBill Paul }
87195d67482SBill Paul 
87295d67482SBill Paul 
87395d67482SBill Paul /*
87495d67482SBill Paul  * Intialize a standard receive ring descriptor.
87595d67482SBill Paul  */
87695d67482SBill Paul static int
87795d67482SBill Paul bge_newbuf_std(sc, i, m)
87895d67482SBill Paul 	struct bge_softc	*sc;
87995d67482SBill Paul 	int			i;
88095d67482SBill Paul 	struct mbuf		*m;
88195d67482SBill Paul {
88295d67482SBill Paul 	struct mbuf		*m_new = NULL;
88395d67482SBill Paul 	struct bge_rx_bd	*r;
884f41ac2beSBill Paul 	struct bge_dmamap_arg	ctx;
885f41ac2beSBill Paul 	int			error;
88695d67482SBill Paul 
88795d67482SBill Paul 	if (m == NULL) {
888a163d034SWarner Losh 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
88995d67482SBill Paul 		if (m_new == NULL) {
89095d67482SBill Paul 			return(ENOBUFS);
89195d67482SBill Paul 		}
89295d67482SBill Paul 
893a163d034SWarner Losh 		MCLGET(m_new, M_DONTWAIT);
89495d67482SBill Paul 		if (!(m_new->m_flags & M_EXT)) {
89595d67482SBill Paul 			m_freem(m_new);
89695d67482SBill Paul 			return(ENOBUFS);
89795d67482SBill Paul 		}
89895d67482SBill Paul 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
89995d67482SBill Paul 	} else {
90095d67482SBill Paul 		m_new = m;
90195d67482SBill Paul 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
90295d67482SBill Paul 		m_new->m_data = m_new->m_ext.ext_buf;
90395d67482SBill Paul 	}
90495d67482SBill Paul 
905e255b776SJohn Polstra 	if (!sc->bge_rx_alignment_bug)
90695d67482SBill Paul 		m_adj(m_new, ETHER_ALIGN);
90795d67482SBill Paul 	sc->bge_cdata.bge_rx_std_chain[i] = m_new;
908f41ac2beSBill Paul 	r = &sc->bge_ldata.bge_rx_std_ring[i];
909f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
910f41ac2beSBill Paul 	ctx.sc = sc;
911f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
912f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
913f41ac2beSBill Paul 	    m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
914f41ac2beSBill Paul 	if (error || ctx.bge_maxsegs == 0) {
915f41ac2beSBill Paul 		if (m == NULL)
916f41ac2beSBill Paul 			m_freem(m_new);
917f41ac2beSBill Paul 		return(ENOMEM);
918f41ac2beSBill Paul 	}
919f41ac2beSBill Paul 	r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr));
920f41ac2beSBill Paul 	r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr));
921f41ac2beSBill Paul 	r->bge_flags = htole16(BGE_RXBDFLAG_END);
922f41ac2beSBill Paul 	r->bge_len = htole16(m_new->m_len);
923f41ac2beSBill Paul 	r->bge_idx = htole16(i);
924f41ac2beSBill Paul 
925f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_mtag,
926f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_dmamap[i],
927f41ac2beSBill Paul 	    BUS_DMASYNC_PREREAD);
92895d67482SBill Paul 
92995d67482SBill Paul 	return(0);
93095d67482SBill Paul }
93195d67482SBill Paul 
93295d67482SBill Paul /*
93395d67482SBill Paul  * Initialize a jumbo receive ring descriptor. This allocates
93495d67482SBill Paul  * a jumbo buffer from the pool managed internally by the driver.
93595d67482SBill Paul  */
93695d67482SBill Paul static int
93795d67482SBill Paul bge_newbuf_jumbo(sc, i, m)
93895d67482SBill Paul 	struct bge_softc *sc;
93995d67482SBill Paul 	int i;
94095d67482SBill Paul 	struct mbuf *m;
94195d67482SBill Paul {
94295d67482SBill Paul 	struct mbuf *m_new = NULL;
94395d67482SBill Paul 	struct bge_rx_bd *r;
944f41ac2beSBill Paul 	struct bge_dmamap_arg ctx;
945f41ac2beSBill Paul 	int error;
94695d67482SBill Paul 
94795d67482SBill Paul 	if (m == NULL) {
94895d67482SBill Paul 		caddr_t			*buf = NULL;
94995d67482SBill Paul 
95095d67482SBill Paul 		/* Allocate the mbuf. */
951a163d034SWarner Losh 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
95295d67482SBill Paul 		if (m_new == NULL) {
95395d67482SBill Paul 			return(ENOBUFS);
95495d67482SBill Paul 		}
95595d67482SBill Paul 
95695d67482SBill Paul 		/* Allocate the jumbo buffer */
95795d67482SBill Paul 		buf = bge_jalloc(sc);
95895d67482SBill Paul 		if (buf == NULL) {
95995d67482SBill Paul 			m_freem(m_new);
96095d67482SBill Paul 			printf("bge%d: jumbo allocation failed "
96195d67482SBill Paul 			    "-- packet dropped!\n", sc->bge_unit);
96295d67482SBill Paul 			return(ENOBUFS);
96395d67482SBill Paul 		}
96495d67482SBill Paul 
96595d67482SBill Paul 		/* Attach the buffer to the mbuf. */
96695d67482SBill Paul 		m_new->m_data = (void *) buf;
96795d67482SBill Paul 		m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
96895d67482SBill Paul 		MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree,
96995d67482SBill Paul 		    (struct bge_softc *)sc, 0, EXT_NET_DRV);
97095d67482SBill Paul 	} else {
97195d67482SBill Paul 		m_new = m;
97295d67482SBill Paul 		m_new->m_data = m_new->m_ext.ext_buf;
97395d67482SBill Paul 		m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
97495d67482SBill Paul 	}
97595d67482SBill Paul 
976e255b776SJohn Polstra 	if (!sc->bge_rx_alignment_bug)
97795d67482SBill Paul 		m_adj(m_new, ETHER_ALIGN);
97895d67482SBill Paul 	/* Set up the descriptor. */
97995d67482SBill Paul 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
980f41ac2beSBill Paul 	r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
981f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
982f41ac2beSBill Paul 	ctx.sc = sc;
983f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo,
984f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *),
985f41ac2beSBill Paul 	    m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
986f41ac2beSBill Paul 	if (error || ctx.bge_maxsegs == 0) {
987f41ac2beSBill Paul 		if (m == NULL)
988f41ac2beSBill Paul 			m_freem(m_new);
989f41ac2beSBill Paul 		return(ENOMEM);
990f41ac2beSBill Paul 	}
991f41ac2beSBill Paul 	r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr));
992f41ac2beSBill Paul 	r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr));
993f41ac2beSBill Paul 	r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING);
994f41ac2beSBill Paul 	r->bge_len = htole16(m_new->m_len);
995f41ac2beSBill Paul 	r->bge_idx = htole16(i);
996f41ac2beSBill Paul 
997f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_mtag,
998f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
999f41ac2beSBill Paul 	    BUS_DMASYNC_PREREAD);
100095d67482SBill Paul 
100195d67482SBill Paul 	return(0);
100295d67482SBill Paul }
100395d67482SBill Paul 
100495d67482SBill Paul /*
100595d67482SBill Paul  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
100695d67482SBill Paul  * that's 1MB or memory, which is a lot. For now, we fill only the first
100795d67482SBill Paul  * 256 ring entries and hope that our CPU is fast enough to keep up with
100895d67482SBill Paul  * the NIC.
100995d67482SBill Paul  */
101095d67482SBill Paul static int
101195d67482SBill Paul bge_init_rx_ring_std(sc)
101295d67482SBill Paul 	struct bge_softc *sc;
101395d67482SBill Paul {
101495d67482SBill Paul 	int i;
101595d67482SBill Paul 
101695d67482SBill Paul 	for (i = 0; i < BGE_SSLOTS; i++) {
101795d67482SBill Paul 		if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
101895d67482SBill Paul 			return(ENOBUFS);
101995d67482SBill Paul 	};
102095d67482SBill Paul 
1021f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1022f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_ring_map,
1023f41ac2beSBill Paul 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1024f41ac2beSBill Paul 
102595d67482SBill Paul 	sc->bge_std = i - 1;
102695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
102795d67482SBill Paul 
102895d67482SBill Paul 	return(0);
102995d67482SBill Paul }
103095d67482SBill Paul 
103195d67482SBill Paul static void
103295d67482SBill Paul bge_free_rx_ring_std(sc)
103395d67482SBill Paul 	struct bge_softc *sc;
103495d67482SBill Paul {
103595d67482SBill Paul 	int i;
103695d67482SBill Paul 
103795d67482SBill Paul 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
103895d67482SBill Paul 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
103995d67482SBill Paul 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
104095d67482SBill Paul 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1041f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1042f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
104395d67482SBill Paul 		}
1044f41ac2beSBill Paul 		bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
104595d67482SBill Paul 		    sizeof(struct bge_rx_bd));
104695d67482SBill Paul 	}
104795d67482SBill Paul 
104895d67482SBill Paul 	return;
104995d67482SBill Paul }
105095d67482SBill Paul 
105195d67482SBill Paul static int
105295d67482SBill Paul bge_init_rx_ring_jumbo(sc)
105395d67482SBill Paul 	struct bge_softc *sc;
105495d67482SBill Paul {
105595d67482SBill Paul 	int i;
105695d67482SBill Paul 	struct bge_rcb *rcb;
105795d67482SBill Paul 
105895d67482SBill Paul 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
105995d67482SBill Paul 		if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
106095d67482SBill Paul 			return(ENOBUFS);
106195d67482SBill Paul 	};
106295d67482SBill Paul 
1063f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1064f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_jumbo_ring_map,
1065f41ac2beSBill Paul 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1066f41ac2beSBill Paul 
106795d67482SBill Paul 	sc->bge_jumbo = i - 1;
106895d67482SBill Paul 
1069f41ac2beSBill Paul 	rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
107067111612SJohn Polstra 	rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
107167111612SJohn Polstra 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
107295d67482SBill Paul 
107395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
107495d67482SBill Paul 
107595d67482SBill Paul 	return(0);
107695d67482SBill Paul }
107795d67482SBill Paul 
107895d67482SBill Paul static void
107995d67482SBill Paul bge_free_rx_ring_jumbo(sc)
108095d67482SBill Paul 	struct bge_softc *sc;
108195d67482SBill Paul {
108295d67482SBill Paul 	int i;
108395d67482SBill Paul 
108495d67482SBill Paul 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
108595d67482SBill Paul 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
108695d67482SBill Paul 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
108795d67482SBill Paul 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1088f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1089f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
109095d67482SBill Paul 		}
1091f41ac2beSBill Paul 		bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
109295d67482SBill Paul 		    sizeof(struct bge_rx_bd));
109395d67482SBill Paul 	}
109495d67482SBill Paul 
109595d67482SBill Paul 	return;
109695d67482SBill Paul }
109795d67482SBill Paul 
109895d67482SBill Paul static void
109995d67482SBill Paul bge_free_tx_ring(sc)
110095d67482SBill Paul 	struct bge_softc *sc;
110195d67482SBill Paul {
110295d67482SBill Paul 	int i;
110395d67482SBill Paul 
1104f41ac2beSBill Paul 	if (sc->bge_ldata.bge_tx_ring == NULL)
110595d67482SBill Paul 		return;
110695d67482SBill Paul 
110795d67482SBill Paul 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
110895d67482SBill Paul 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
110995d67482SBill Paul 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
111095d67482SBill Paul 			sc->bge_cdata.bge_tx_chain[i] = NULL;
1111f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1112f41ac2beSBill Paul 			    sc->bge_cdata.bge_tx_dmamap[i]);
111395d67482SBill Paul 		}
1114f41ac2beSBill Paul 		bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
111595d67482SBill Paul 		    sizeof(struct bge_tx_bd));
111695d67482SBill Paul 	}
111795d67482SBill Paul 
111895d67482SBill Paul 	return;
111995d67482SBill Paul }
112095d67482SBill Paul 
112195d67482SBill Paul static int
112295d67482SBill Paul bge_init_tx_ring(sc)
112395d67482SBill Paul 	struct bge_softc *sc;
112495d67482SBill Paul {
112595d67482SBill Paul 	sc->bge_txcnt = 0;
112695d67482SBill Paul 	sc->bge_tx_saved_considx = 0;
11273927098fSPaul Saab 
112895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
11293927098fSPaul Saab 	/* 5700 b2 errata */
1130e0ced696SPaul Saab 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
11313927098fSPaul Saab 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
11323927098fSPaul Saab 
11333927098fSPaul Saab 	CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
11343927098fSPaul Saab 	/* 5700 b2 errata */
1135e0ced696SPaul Saab 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
113695d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
113795d67482SBill Paul 
113895d67482SBill Paul 	return(0);
113995d67482SBill Paul }
114095d67482SBill Paul 
114195d67482SBill Paul static void
114295d67482SBill Paul bge_setmulti(sc)
114395d67482SBill Paul 	struct bge_softc *sc;
114495d67482SBill Paul {
114595d67482SBill Paul 	struct ifnet *ifp;
114695d67482SBill Paul 	struct ifmultiaddr *ifma;
114795d67482SBill Paul 	u_int32_t hashes[4] = { 0, 0, 0, 0 };
114895d67482SBill Paul 	int h, i;
114995d67482SBill Paul 
11500f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
11510f9bd73bSSam Leffler 
115295d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
115395d67482SBill Paul 
115495d67482SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
115595d67482SBill Paul 		for (i = 0; i < 4; i++)
115695d67482SBill Paul 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
115795d67482SBill Paul 		return;
115895d67482SBill Paul 	}
115995d67482SBill Paul 
116095d67482SBill Paul 	/* First, zot all the existing filters. */
116195d67482SBill Paul 	for (i = 0; i < 4; i++)
116295d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
116395d67482SBill Paul 
116495d67482SBill Paul 	/* Now program new ones. */
116595d67482SBill Paul 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
116695d67482SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
116795d67482SBill Paul 			continue;
11680e939c0cSChristian Weisgerber 		h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
11690e939c0cSChristian Weisgerber 		    ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
117095d67482SBill Paul 		hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
117195d67482SBill Paul 	}
117295d67482SBill Paul 
117395d67482SBill Paul 	for (i = 0; i < 4; i++)
117495d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
117595d67482SBill Paul 
117695d67482SBill Paul 	return;
117795d67482SBill Paul }
117895d67482SBill Paul 
117995d67482SBill Paul /*
118095d67482SBill Paul  * Do endian, PCI and DMA initialization. Also check the on-board ROM
118195d67482SBill Paul  * self-test results.
118295d67482SBill Paul  */
118395d67482SBill Paul static int
118495d67482SBill Paul bge_chipinit(sc)
118595d67482SBill Paul 	struct bge_softc *sc;
118695d67482SBill Paul {
118795d67482SBill Paul 	int			i;
11885cba12d3SPaul Saab 	u_int32_t		dma_rw_ctl;
118995d67482SBill Paul 
119095d67482SBill Paul 	/* Set endianness before we access any non-PCI registers. */
119195d67482SBill Paul #if BYTE_ORDER == BIG_ENDIAN
119295d67482SBill Paul 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
119395d67482SBill Paul 	    BGE_BIGENDIAN_INIT, 4);
119495d67482SBill Paul #else
119595d67482SBill Paul 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
119695d67482SBill Paul 	    BGE_LITTLEENDIAN_INIT, 4);
119795d67482SBill Paul #endif
119895d67482SBill Paul 
119995d67482SBill Paul 	/*
120095d67482SBill Paul 	 * Check the 'ROM failed' bit on the RX CPU to see if
120195d67482SBill Paul 	 * self-tests passed.
120295d67482SBill Paul 	 */
120395d67482SBill Paul 	if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
120495d67482SBill Paul 		printf("bge%d: RX CPU self-diagnostics failed!\n",
120595d67482SBill Paul 		    sc->bge_unit);
120695d67482SBill Paul 		return(ENODEV);
120795d67482SBill Paul 	}
120895d67482SBill Paul 
120995d67482SBill Paul 	/* Clear the MAC control register */
121095d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
121195d67482SBill Paul 
121295d67482SBill Paul 	/*
121395d67482SBill Paul 	 * Clear the MAC statistics block in the NIC's
121495d67482SBill Paul 	 * internal memory.
121595d67482SBill Paul 	 */
121695d67482SBill Paul 	for (i = BGE_STATS_BLOCK;
121795d67482SBill Paul 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
121895d67482SBill Paul 		BGE_MEMWIN_WRITE(sc, i, 0);
121995d67482SBill Paul 
122095d67482SBill Paul 	for (i = BGE_STATUS_BLOCK;
122195d67482SBill Paul 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
122295d67482SBill Paul 		BGE_MEMWIN_WRITE(sc, i, 0);
122395d67482SBill Paul 
122495d67482SBill Paul 	/* Set up the PCI DMA control register. */
1225e53d81eeSPaul Saab 	if (sc->bge_pcie) {
1226e53d81eeSPaul Saab 		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1227e53d81eeSPaul Saab 		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1228e53d81eeSPaul Saab 		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1229e53d81eeSPaul Saab 	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
12308287860eSJohn Polstra 	    BGE_PCISTATE_PCI_BUSMODE) {
12318287860eSJohn Polstra 		/* Conventional PCI bus */
12325cba12d3SPaul Saab 		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
12335cba12d3SPaul Saab 		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
12345cba12d3SPaul Saab 		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
12355cba12d3SPaul Saab 		    (0x0F);
12368287860eSJohn Polstra 	} else {
12378287860eSJohn Polstra 		/* PCI-X bus */
12385cba12d3SPaul Saab 		/*
12395cba12d3SPaul Saab 		 * The 5704 uses a different encoding of read/write
12405cba12d3SPaul Saab 		 * watermarks.
12415cba12d3SPaul Saab 		 */
1242e0ced696SPaul Saab 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
12435cba12d3SPaul Saab 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
12445cba12d3SPaul Saab 			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
12455cba12d3SPaul Saab 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
12465cba12d3SPaul Saab 		else
12475cba12d3SPaul Saab 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
12485cba12d3SPaul Saab 			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
12495cba12d3SPaul Saab 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
12505cba12d3SPaul Saab 			    (0x0F);
12515cba12d3SPaul Saab 
12525cba12d3SPaul Saab 		/*
12535cba12d3SPaul Saab 		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
12545cba12d3SPaul Saab 		 * for hardware bugs.
12555cba12d3SPaul Saab 		 */
1256e0ced696SPaul Saab 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1257e0ced696SPaul Saab 		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
12585cba12d3SPaul Saab 			u_int32_t tmp;
12595cba12d3SPaul Saab 
12605cba12d3SPaul Saab 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
12615cba12d3SPaul Saab 			if (tmp == 0x6 || tmp == 0x7)
12625cba12d3SPaul Saab 				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
12638287860eSJohn Polstra 		}
12645cba12d3SPaul Saab 	}
12655cba12d3SPaul Saab 
1266e0ced696SPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
12670434d1b8SBill Paul 	    sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1268e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1269e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
12705cba12d3SPaul Saab 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
12715cba12d3SPaul Saab 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
127295d67482SBill Paul 
127395d67482SBill Paul 	/*
127495d67482SBill Paul 	 * Set up general mode register.
127595d67482SBill Paul 	 */
127695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
127795d67482SBill Paul 	    BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
127895d67482SBill Paul 	    BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1279e446dc86SPaul Saab 	    BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
128095d67482SBill Paul 
128195d67482SBill Paul 	/*
1282ea13bdd5SJohn Polstra 	 * Disable memory write invalidate.  Apparently it is not supported
1283ea13bdd5SJohn Polstra 	 * properly by these devices.
128495d67482SBill Paul 	 */
1285ea13bdd5SJohn Polstra 	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
128695d67482SBill Paul 
128795d67482SBill Paul #ifdef __brokenalpha__
128895d67482SBill Paul 	/*
128995d67482SBill Paul 	 * Must insure that we do not cross an 8K (bytes) boundary
129095d67482SBill Paul 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a
129195d67482SBill Paul 	 * restriction on some ALPHA platforms with early revision
129295d67482SBill Paul 	 * 21174 PCI chipsets, such as the AlphaPC 164lx
129395d67482SBill Paul 	 */
129462f1ea9cSJohn Polstra 	PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
129562f1ea9cSJohn Polstra 	    BGE_PCI_READ_BNDRY_1024BYTES, 4);
129695d67482SBill Paul #endif
129795d67482SBill Paul 
129895d67482SBill Paul 	/* Set the timer prescaler (always 66Mhz) */
129995d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
130095d67482SBill Paul 
130195d67482SBill Paul 	return(0);
130295d67482SBill Paul }
130395d67482SBill Paul 
130495d67482SBill Paul static int
130595d67482SBill Paul bge_blockinit(sc)
130695d67482SBill Paul 	struct bge_softc *sc;
130795d67482SBill Paul {
130895d67482SBill Paul 	struct bge_rcb *rcb;
130967111612SJohn Polstra 	volatile struct bge_rcb *vrcb;
131095d67482SBill Paul 	int i;
131195d67482SBill Paul 
131295d67482SBill Paul 	/*
131395d67482SBill Paul 	 * Initialize the memory window pointer register so that
131495d67482SBill Paul 	 * we can access the first 32K of internal NIC RAM. This will
131595d67482SBill Paul 	 * allow us to set up the TX send ring RCBs and the RX return
131695d67482SBill Paul 	 * ring RCBs, plus other things which live in NIC memory.
131795d67482SBill Paul 	 */
131895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
131995d67482SBill Paul 
1320822f63fcSBill Paul 	/* Note: the BCM5704 has a smaller mbuf space than other chips. */
1321822f63fcSBill Paul 
13225dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1323e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
132495d67482SBill Paul 		/* Configure mbuf memory pool */
132595d67482SBill Paul 		if (sc->bge_extram) {
13260434d1b8SBill Paul 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
13270434d1b8SBill Paul 			    BGE_EXT_SSRAM);
1328822f63fcSBill Paul 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1329822f63fcSBill Paul 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1330822f63fcSBill Paul 			else
133195d67482SBill Paul 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
133295d67482SBill Paul 		} else {
13330434d1b8SBill Paul 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
13340434d1b8SBill Paul 			    BGE_BUFFPOOL_1);
1335822f63fcSBill Paul 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1336822f63fcSBill Paul 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1337822f63fcSBill Paul 			else
133895d67482SBill Paul 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
133995d67482SBill Paul 		}
134095d67482SBill Paul 
134195d67482SBill Paul 		/* Configure DMA resource pool */
13420434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
13430434d1b8SBill Paul 		    BGE_DMA_DESCRIPTORS);
134495d67482SBill Paul 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
13450434d1b8SBill Paul 	}
134695d67482SBill Paul 
134795d67482SBill Paul 	/* Configure mbuf pool watermarks */
1348e53d81eeSPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1349e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5750) {
13500434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
13510434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
13520434d1b8SBill Paul 	} else {
1353fa228020SPaul Saab 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1354fa228020SPaul Saab 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
13550434d1b8SBill Paul 	}
1356fa228020SPaul Saab 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
135795d67482SBill Paul 
135895d67482SBill Paul 	/* Configure DMA resource watermarks */
135995d67482SBill Paul 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
136095d67482SBill Paul 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
136195d67482SBill Paul 
136295d67482SBill Paul 	/* Enable buffer manager */
13635dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1364e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
136595d67482SBill Paul 		CSR_WRITE_4(sc, BGE_BMAN_MODE,
136695d67482SBill Paul 		    BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
136795d67482SBill Paul 
136895d67482SBill Paul 		/* Poll for buffer manager start indication */
136995d67482SBill Paul 		for (i = 0; i < BGE_TIMEOUT; i++) {
137095d67482SBill Paul 			if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
137195d67482SBill Paul 				break;
137295d67482SBill Paul 			DELAY(10);
137395d67482SBill Paul 		}
137495d67482SBill Paul 
137595d67482SBill Paul 		if (i == BGE_TIMEOUT) {
137695d67482SBill Paul 			printf("bge%d: buffer manager failed to start\n",
137795d67482SBill Paul 			    sc->bge_unit);
137895d67482SBill Paul 			return(ENXIO);
137995d67482SBill Paul 		}
13800434d1b8SBill Paul 	}
138195d67482SBill Paul 
138295d67482SBill Paul 	/* Enable flow-through queues */
138395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
138495d67482SBill Paul 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
138595d67482SBill Paul 
138695d67482SBill Paul 	/* Wait until queue initialization is complete */
138795d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
138895d67482SBill Paul 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
138995d67482SBill Paul 			break;
139095d67482SBill Paul 		DELAY(10);
139195d67482SBill Paul 	}
139295d67482SBill Paul 
139395d67482SBill Paul 	if (i == BGE_TIMEOUT) {
139495d67482SBill Paul 		printf("bge%d: flow-through queue init failed\n",
139595d67482SBill Paul 		    sc->bge_unit);
139695d67482SBill Paul 		return(ENXIO);
139795d67482SBill Paul 	}
139895d67482SBill Paul 
139995d67482SBill Paul 	/* Initialize the standard RX ring control block */
1400f41ac2beSBill Paul 	rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1401f41ac2beSBill Paul 	rcb->bge_hostaddr.bge_addr_lo =
1402f41ac2beSBill Paul 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1403f41ac2beSBill Paul 	rcb->bge_hostaddr.bge_addr_hi =
1404f41ac2beSBill Paul 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1405f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1406f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1407e53d81eeSPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1408e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
14090434d1b8SBill Paul 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
14100434d1b8SBill Paul 	else
14110434d1b8SBill Paul 		rcb->bge_maxlen_flags =
14120434d1b8SBill Paul 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
141395d67482SBill Paul 	if (sc->bge_extram)
141495d67482SBill Paul 		rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
141595d67482SBill Paul 	else
141695d67482SBill Paul 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
141767111612SJohn Polstra 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
141867111612SJohn Polstra 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1419f41ac2beSBill Paul 
142067111612SJohn Polstra 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
142167111612SJohn Polstra 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
142295d67482SBill Paul 
142395d67482SBill Paul 	/*
142495d67482SBill Paul 	 * Initialize the jumbo RX ring control block
142595d67482SBill Paul 	 * We set the 'ring disabled' bit in the flags
142695d67482SBill Paul 	 * field until we're actually ready to start
142795d67482SBill Paul 	 * using this ring (i.e. once we set the MTU
142895d67482SBill Paul 	 * high enough to require it).
142995d67482SBill Paul 	 */
14305dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1431e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1432f41ac2beSBill Paul 		rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1433f41ac2beSBill Paul 
1434f41ac2beSBill Paul 		rcb->bge_hostaddr.bge_addr_lo =
1435f41ac2beSBill Paul 		    BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1436f41ac2beSBill Paul 		rcb->bge_hostaddr.bge_addr_hi =
1437f41ac2beSBill Paul 		    BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1438f41ac2beSBill Paul 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1439f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
1440f41ac2beSBill Paul 		    BUS_DMASYNC_PREREAD);
144167111612SJohn Polstra 		rcb->bge_maxlen_flags =
14420434d1b8SBill Paul 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
14430434d1b8SBill Paul 		    BGE_RCB_FLAG_RING_DISABLED);
144495d67482SBill Paul 		if (sc->bge_extram)
144595d67482SBill Paul 			rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
144695d67482SBill Paul 		else
144795d67482SBill Paul 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
144867111612SJohn Polstra 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
144967111612SJohn Polstra 		    rcb->bge_hostaddr.bge_addr_hi);
145067111612SJohn Polstra 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
145167111612SJohn Polstra 		    rcb->bge_hostaddr.bge_addr_lo);
1452f41ac2beSBill Paul 
14530434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
14540434d1b8SBill Paul 		    rcb->bge_maxlen_flags);
145567111612SJohn Polstra 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
145695d67482SBill Paul 
145795d67482SBill Paul 		/* Set up dummy disabled mini ring RCB */
1458f41ac2beSBill Paul 		rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
145967111612SJohn Polstra 		rcb->bge_maxlen_flags =
146067111612SJohn Polstra 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
14610434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
14620434d1b8SBill Paul 		    rcb->bge_maxlen_flags);
14630434d1b8SBill Paul 	}
146495d67482SBill Paul 
146595d67482SBill Paul 	/*
146695d67482SBill Paul 	 * Set the BD ring replentish thresholds. The recommended
146795d67482SBill Paul 	 * values are 1/8th the number of descriptors allocated to
146895d67482SBill Paul 	 * each ring.
146995d67482SBill Paul 	 */
147095d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
147195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
147295d67482SBill Paul 
147395d67482SBill Paul 	/*
147495d67482SBill Paul 	 * Disable all unused send rings by setting the 'ring disabled'
147595d67482SBill Paul 	 * bit in the flags field of all the TX send ring control blocks.
147695d67482SBill Paul 	 * These are located in NIC memory.
147795d67482SBill Paul 	 */
147867111612SJohn Polstra 	vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
147995d67482SBill Paul 	    BGE_SEND_RING_RCB);
148095d67482SBill Paul 	for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
148167111612SJohn Polstra 		vrcb->bge_maxlen_flags =
148267111612SJohn Polstra 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
148367111612SJohn Polstra 		vrcb->bge_nicaddr = 0;
148467111612SJohn Polstra 		vrcb++;
148595d67482SBill Paul 	}
148695d67482SBill Paul 
148795d67482SBill Paul 	/* Configure TX RCB 0 (we use only the first ring) */
148867111612SJohn Polstra 	vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
148995d67482SBill Paul 	    BGE_SEND_RING_RCB);
1490f41ac2beSBill Paul 	vrcb->bge_hostaddr.bge_addr_lo =
1491f41ac2beSBill Paul 	    htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr));
1492f41ac2beSBill Paul 	vrcb->bge_hostaddr.bge_addr_hi =
1493f41ac2beSBill Paul 	    htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr));
149467111612SJohn Polstra 	vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
14955dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1496e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
14970434d1b8SBill Paul 		vrcb->bge_maxlen_flags =
14980434d1b8SBill Paul 		    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
149995d67482SBill Paul 
150095d67482SBill Paul 	/* Disable all unused RX return rings */
150167111612SJohn Polstra 	vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
150295d67482SBill Paul 	    BGE_RX_RETURN_RING_RCB);
150395d67482SBill Paul 	for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
150467111612SJohn Polstra 		vrcb->bge_hostaddr.bge_addr_hi = 0;
150567111612SJohn Polstra 		vrcb->bge_hostaddr.bge_addr_lo = 0;
150667111612SJohn Polstra 		vrcb->bge_maxlen_flags =
15070434d1b8SBill Paul 		    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
150867111612SJohn Polstra 		    BGE_RCB_FLAG_RING_DISABLED);
150967111612SJohn Polstra 		vrcb->bge_nicaddr = 0;
151095d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
151195d67482SBill Paul 		    (i * (sizeof(u_int64_t))), 0);
151267111612SJohn Polstra 		vrcb++;
151395d67482SBill Paul 	}
151495d67482SBill Paul 
151595d67482SBill Paul 	/* Initialize RX ring indexes */
151695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
151795d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
151895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
151995d67482SBill Paul 
152095d67482SBill Paul 	/*
152195d67482SBill Paul 	 * Set up RX return ring 0
152295d67482SBill Paul 	 * Note that the NIC address for RX return rings is 0x00000000.
152395d67482SBill Paul 	 * The return rings live entirely within the host, so the
152495d67482SBill Paul 	 * nicaddr field in the RCB isn't used.
152595d67482SBill Paul 	 */
152667111612SJohn Polstra 	vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
152795d67482SBill Paul 	    BGE_RX_RETURN_RING_RCB);
1528f41ac2beSBill Paul 	vrcb->bge_hostaddr.bge_addr_lo =
1529f41ac2beSBill Paul 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr);
1530f41ac2beSBill Paul 	vrcb->bge_hostaddr.bge_addr_hi =
1531f41ac2beSBill Paul 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr);
1532f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
1533f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
153467111612SJohn Polstra 	vrcb->bge_nicaddr = 0x00000000;
15350434d1b8SBill Paul 	vrcb->bge_maxlen_flags =
15360434d1b8SBill Paul 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
153795d67482SBill Paul 
153895d67482SBill Paul 	/* Set random backoff seed for TX */
153995d67482SBill Paul 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
154095d67482SBill Paul 	    sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
154195d67482SBill Paul 	    sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
154295d67482SBill Paul 	    sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
154395d67482SBill Paul 	    BGE_TX_BACKOFF_SEED_MASK);
154495d67482SBill Paul 
154595d67482SBill Paul 	/* Set inter-packet gap */
154695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
154795d67482SBill Paul 
154895d67482SBill Paul 	/*
154995d67482SBill Paul 	 * Specify which ring to use for packets that don't match
155095d67482SBill Paul 	 * any RX rules.
155195d67482SBill Paul 	 */
155295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
155395d67482SBill Paul 
155495d67482SBill Paul 	/*
155595d67482SBill Paul 	 * Configure number of RX lists. One interrupt distribution
155695d67482SBill Paul 	 * list, sixteen active lists, one bad frames class.
155795d67482SBill Paul 	 */
155895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
155995d67482SBill Paul 
156095d67482SBill Paul 	/* Inialize RX list placement stats mask. */
156195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
156295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
156395d67482SBill Paul 
156495d67482SBill Paul 	/* Disable host coalescing until we get it set up */
156595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
156695d67482SBill Paul 
156795d67482SBill Paul 	/* Poll to make sure it's shut down. */
156895d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
156995d67482SBill Paul 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
157095d67482SBill Paul 			break;
157195d67482SBill Paul 		DELAY(10);
157295d67482SBill Paul 	}
157395d67482SBill Paul 
157495d67482SBill Paul 	if (i == BGE_TIMEOUT) {
157595d67482SBill Paul 		printf("bge%d: host coalescing engine failed to idle\n",
157695d67482SBill Paul 		    sc->bge_unit);
157795d67482SBill Paul 		return(ENXIO);
157895d67482SBill Paul 	}
157995d67482SBill Paul 
158095d67482SBill Paul 	/* Set up host coalescing defaults */
158195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
158295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
158395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
158495d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
15855dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1586e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
158795d67482SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
158895d67482SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
15890434d1b8SBill Paul 	}
159095d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
159195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
159295d67482SBill Paul 
159395d67482SBill Paul 	/* Set up address of statistics block */
15945dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1595e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1596f41ac2beSBill Paul 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1597f41ac2beSBill Paul 		    BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
159895d67482SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1599f41ac2beSBill Paul 		    BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
16000434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
160195d67482SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
16020434d1b8SBill Paul 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
16030434d1b8SBill Paul 	}
16040434d1b8SBill Paul 
16050434d1b8SBill Paul 	/* Set up address of status block */
1606f41ac2beSBill Paul 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1607f41ac2beSBill Paul 	    BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
160895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1609f41ac2beSBill Paul 	    BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1610f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
1611f41ac2beSBill Paul 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE);
1612f41ac2beSBill Paul 	sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1613f41ac2beSBill Paul 	sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
161495d67482SBill Paul 
161595d67482SBill Paul 	/* Turn on host coalescing state machine */
161695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
161795d67482SBill Paul 
161895d67482SBill Paul 	/* Turn on RX BD completion state machine and enable attentions */
161995d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
162095d67482SBill Paul 	    BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
162195d67482SBill Paul 
162295d67482SBill Paul 	/* Turn on RX list placement state machine */
162395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
162495d67482SBill Paul 
162595d67482SBill Paul 	/* Turn on RX list selector state machine. */
16265dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1627e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
162895d67482SBill Paul 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
162995d67482SBill Paul 
163095d67482SBill Paul 	/* Turn on DMA, clear stats */
163195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
163295d67482SBill Paul 	    BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
163395d67482SBill Paul 	    BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
163495d67482SBill Paul 	    BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
163595d67482SBill Paul 	    (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
163695d67482SBill Paul 
163795d67482SBill Paul 	/* Set misc. local control, enable interrupts on attentions */
163895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
163995d67482SBill Paul 
164095d67482SBill Paul #ifdef notdef
164195d67482SBill Paul 	/* Assert GPIO pins for PHY reset */
164295d67482SBill Paul 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
164395d67482SBill Paul 	    BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
164495d67482SBill Paul 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
164595d67482SBill Paul 	    BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
164695d67482SBill Paul #endif
164795d67482SBill Paul 
164895d67482SBill Paul 	/* Turn on DMA completion state machine */
16495dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1650e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
165195d67482SBill Paul 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
165295d67482SBill Paul 
165395d67482SBill Paul 	/* Turn on write DMA state machine */
165495d67482SBill Paul 	CSR_WRITE_4(sc, BGE_WDMA_MODE,
165595d67482SBill Paul 	    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
165695d67482SBill Paul 
165795d67482SBill Paul 	/* Turn on read DMA state machine */
165895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RDMA_MODE,
165995d67482SBill Paul 	    BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
166095d67482SBill Paul 
166195d67482SBill Paul 	/* Turn on RX data completion state machine */
166295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
166395d67482SBill Paul 
166495d67482SBill Paul 	/* Turn on RX BD initiator state machine */
166595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
166695d67482SBill Paul 
166795d67482SBill Paul 	/* Turn on RX data and RX BD initiator state machine */
166895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
166995d67482SBill Paul 
167095d67482SBill Paul 	/* Turn on Mbuf cluster free state machine */
16715dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1672e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
167395d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
167495d67482SBill Paul 
167595d67482SBill Paul 	/* Turn on send BD completion state machine */
167695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
167795d67482SBill Paul 
167895d67482SBill Paul 	/* Turn on send data completion state machine */
167995d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
168095d67482SBill Paul 
168195d67482SBill Paul 	/* Turn on send data initiator state machine */
168295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
168395d67482SBill Paul 
168495d67482SBill Paul 	/* Turn on send BD initiator state machine */
168595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
168695d67482SBill Paul 
168795d67482SBill Paul 	/* Turn on send BD selector state machine */
168895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
168995d67482SBill Paul 
169095d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
169195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
169295d67482SBill Paul 	    BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
169395d67482SBill Paul 
169495d67482SBill Paul 	/* ack/clear link change events */
169595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
16960434d1b8SBill Paul 	    BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
16970434d1b8SBill Paul 	    BGE_MACSTAT_LINK_CHANGED);
1698f41ac2beSBill Paul 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
169995d67482SBill Paul 
170095d67482SBill Paul 	/* Enable PHY auto polling (for MII/GMII only) */
170195d67482SBill Paul 	if (sc->bge_tbi) {
170295d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1703a1d52896SBill Paul  	} else {
170495d67482SBill Paul 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1705e0ced696SPaul Saab 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1706a1d52896SBill Paul 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1707a1d52896SBill Paul 			    BGE_EVTENB_MI_INTERRUPT);
1708a1d52896SBill Paul 	}
170995d67482SBill Paul 
171095d67482SBill Paul 	/* Enable link state change attentions. */
171195d67482SBill Paul 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
171295d67482SBill Paul 
171395d67482SBill Paul 	return(0);
171495d67482SBill Paul }
171595d67482SBill Paul 
171695d67482SBill Paul /*
171795d67482SBill Paul  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
171895d67482SBill Paul  * against our list and return its name if we find a match. Note
171995d67482SBill Paul  * that since the Broadcom controller contains VPD support, we
172095d67482SBill Paul  * can get the device name string from the controller itself instead
172195d67482SBill Paul  * of the compiled-in string. This is a little slow, but it guarantees
172295d67482SBill Paul  * we'll always announce the right product name.
172395d67482SBill Paul  */
172495d67482SBill Paul static int
172595d67482SBill Paul bge_probe(dev)
172695d67482SBill Paul 	device_t dev;
172795d67482SBill Paul {
172895d67482SBill Paul 	struct bge_type *t;
172995d67482SBill Paul 	struct bge_softc *sc;
1730029e2ee3SJohn Polstra 	char *descbuf;
173195d67482SBill Paul 
173295d67482SBill Paul 	t = bge_devs;
173395d67482SBill Paul 
173495d67482SBill Paul 	sc = device_get_softc(dev);
173595d67482SBill Paul 	bzero(sc, sizeof(struct bge_softc));
173695d67482SBill Paul 	sc->bge_unit = device_get_unit(dev);
173795d67482SBill Paul 	sc->bge_dev = dev;
173895d67482SBill Paul 
173995d67482SBill Paul 	while(t->bge_name != NULL) {
174095d67482SBill Paul 		if ((pci_get_vendor(dev) == t->bge_vid) &&
174195d67482SBill Paul 		    (pci_get_device(dev) == t->bge_did)) {
174295d67482SBill Paul #ifdef notdef
174395d67482SBill Paul 			bge_vpd_read(sc);
174495d67482SBill Paul 			device_set_desc(dev, sc->bge_vpd_prodname);
174595d67482SBill Paul #endif
1746029e2ee3SJohn Polstra 			descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
1747029e2ee3SJohn Polstra 			if (descbuf == NULL)
1748029e2ee3SJohn Polstra 				return(ENOMEM);
1749029e2ee3SJohn Polstra 			snprintf(descbuf, BGE_DEVDESC_MAX,
1750029e2ee3SJohn Polstra 			    "%s, ASIC rev. %#04x", t->bge_name,
1751029e2ee3SJohn Polstra 			    pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1752029e2ee3SJohn Polstra 			device_set_desc_copy(dev, descbuf);
17536d2a9bd6SDoug Ambrisko 			if (pci_get_subvendor(dev) == DELL_VENDORID)
17546d2a9bd6SDoug Ambrisko 				sc->bge_no_3_led = 1;
1755029e2ee3SJohn Polstra 			free(descbuf, M_TEMP);
175695d67482SBill Paul 			return(0);
175795d67482SBill Paul 		}
175895d67482SBill Paul 		t++;
175995d67482SBill Paul 	}
176095d67482SBill Paul 
176195d67482SBill Paul 	return(ENXIO);
176295d67482SBill Paul }
176395d67482SBill Paul 
1764f41ac2beSBill Paul static void
1765f41ac2beSBill Paul bge_dma_free(sc)
1766f41ac2beSBill Paul 	struct bge_softc *sc;
1767f41ac2beSBill Paul {
1768f41ac2beSBill Paul 	int i;
1769f41ac2beSBill Paul 
1770f41ac2beSBill Paul 
1771f41ac2beSBill Paul 	/* Destroy DMA maps for RX buffers */
1772f41ac2beSBill Paul 
1773f41ac2beSBill Paul 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1774f41ac2beSBill Paul 		if (sc->bge_cdata.bge_rx_std_dmamap[i])
1775f41ac2beSBill Paul 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1776f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
1777f41ac2beSBill Paul 	}
1778f41ac2beSBill Paul 
1779f41ac2beSBill Paul 	/* Destroy DMA maps for jumbo RX buffers */
1780f41ac2beSBill Paul 
1781f41ac2beSBill Paul 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1782f41ac2beSBill Paul 		if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1783f41ac2beSBill Paul 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1784f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1785f41ac2beSBill Paul 	}
1786f41ac2beSBill Paul 
1787f41ac2beSBill Paul 	/* Destroy DMA maps for TX buffers */
1788f41ac2beSBill Paul 
1789f41ac2beSBill Paul 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1790f41ac2beSBill Paul 		if (sc->bge_cdata.bge_tx_dmamap[i])
1791f41ac2beSBill Paul 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1792f41ac2beSBill Paul 			    sc->bge_cdata.bge_tx_dmamap[i]);
1793f41ac2beSBill Paul 	}
1794f41ac2beSBill Paul 
1795f41ac2beSBill Paul 	if (sc->bge_cdata.bge_mtag)
1796f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1797f41ac2beSBill Paul 
1798f41ac2beSBill Paul 
1799f41ac2beSBill Paul 	/* Destroy standard RX ring */
1800f41ac2beSBill Paul 
1801f41ac2beSBill Paul 	if (sc->bge_ldata.bge_rx_std_ring)
1802f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1803f41ac2beSBill Paul 		    sc->bge_ldata.bge_rx_std_ring,
1804f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_std_ring_map);
1805f41ac2beSBill Paul 
1806f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_std_ring_map) {
1807f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1808f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_std_ring_map);
1809f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag,
1810f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_std_ring_map);
1811f41ac2beSBill Paul 	}
1812f41ac2beSBill Paul 
1813f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_std_ring_tag)
1814f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1815f41ac2beSBill Paul 
1816f41ac2beSBill Paul 	/* Destroy jumbo RX ring */
1817f41ac2beSBill Paul 
1818f41ac2beSBill Paul 	if (sc->bge_ldata.bge_rx_jumbo_ring)
1819f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1820f41ac2beSBill Paul 		    sc->bge_ldata.bge_rx_jumbo_ring,
1821f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
1822f41ac2beSBill Paul 
1823f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_jumbo_ring_map) {
1824f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1825f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
1826f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1827f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
1828f41ac2beSBill Paul 	}
1829f41ac2beSBill Paul 
1830f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1831f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1832f41ac2beSBill Paul 
1833f41ac2beSBill Paul 	/* Destroy RX return ring */
1834f41ac2beSBill Paul 
1835f41ac2beSBill Paul 	if (sc->bge_ldata.bge_rx_return_ring)
1836f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1837f41ac2beSBill Paul 		    sc->bge_ldata.bge_rx_return_ring,
1838f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_return_ring_map);
1839f41ac2beSBill Paul 
1840f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_return_ring_map) {
1841f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1842f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_return_ring_map);
1843f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag,
1844f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_return_ring_map);
1845f41ac2beSBill Paul 	}
1846f41ac2beSBill Paul 
1847f41ac2beSBill Paul 	if (sc->bge_cdata.bge_rx_return_ring_tag)
1848f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1849f41ac2beSBill Paul 
1850f41ac2beSBill Paul 	/* Destroy TX ring */
1851f41ac2beSBill Paul 
1852f41ac2beSBill Paul 	if (sc->bge_ldata.bge_tx_ring)
1853f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1854f41ac2beSBill Paul 		    sc->bge_ldata.bge_tx_ring,
1855f41ac2beSBill Paul 		    sc->bge_cdata.bge_tx_ring_map);
1856f41ac2beSBill Paul 
1857f41ac2beSBill Paul 	if (sc->bge_cdata.bge_tx_ring_map) {
1858f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1859f41ac2beSBill Paul 		    sc->bge_cdata.bge_tx_ring_map);
1860f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag,
1861f41ac2beSBill Paul 		    sc->bge_cdata.bge_tx_ring_map);
1862f41ac2beSBill Paul 	}
1863f41ac2beSBill Paul 
1864f41ac2beSBill Paul 	if (sc->bge_cdata.bge_tx_ring_tag)
1865f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1866f41ac2beSBill Paul 
1867f41ac2beSBill Paul 	/* Destroy status block */
1868f41ac2beSBill Paul 
1869f41ac2beSBill Paul 	if (sc->bge_ldata.bge_status_block)
1870f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_status_tag,
1871f41ac2beSBill Paul 		    sc->bge_ldata.bge_status_block,
1872f41ac2beSBill Paul 		    sc->bge_cdata.bge_status_map);
1873f41ac2beSBill Paul 
1874f41ac2beSBill Paul 	if (sc->bge_cdata.bge_status_map) {
1875f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1876f41ac2beSBill Paul 		    sc->bge_cdata.bge_status_map);
1877f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_status_tag,
1878f41ac2beSBill Paul 		    sc->bge_cdata.bge_status_map);
1879f41ac2beSBill Paul 	}
1880f41ac2beSBill Paul 
1881f41ac2beSBill Paul 	if (sc->bge_cdata.bge_status_tag)
1882f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
1883f41ac2beSBill Paul 
1884f41ac2beSBill Paul 	/* Destroy statistics block */
1885f41ac2beSBill Paul 
1886f41ac2beSBill Paul 	if (sc->bge_ldata.bge_stats)
1887f41ac2beSBill Paul 		bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
1888f41ac2beSBill Paul 		    sc->bge_ldata.bge_stats,
1889f41ac2beSBill Paul 		    sc->bge_cdata.bge_stats_map);
1890f41ac2beSBill Paul 
1891f41ac2beSBill Paul 	if (sc->bge_cdata.bge_stats_map) {
1892f41ac2beSBill Paul 		bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
1893f41ac2beSBill Paul 		    sc->bge_cdata.bge_stats_map);
1894f41ac2beSBill Paul 		bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag,
1895f41ac2beSBill Paul 		    sc->bge_cdata.bge_stats_map);
1896f41ac2beSBill Paul 	}
1897f41ac2beSBill Paul 
1898f41ac2beSBill Paul 	if (sc->bge_cdata.bge_stats_tag)
1899f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
1900f41ac2beSBill Paul 
1901f41ac2beSBill Paul 	/* Destroy the parent tag */
1902f41ac2beSBill Paul 
1903f41ac2beSBill Paul 	if (sc->bge_cdata.bge_parent_tag)
1904f41ac2beSBill Paul 		bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
1905f41ac2beSBill Paul 
1906f41ac2beSBill Paul 	return;
1907f41ac2beSBill Paul }
1908f41ac2beSBill Paul 
1909f41ac2beSBill Paul static int
1910f41ac2beSBill Paul bge_dma_alloc(dev)
1911f41ac2beSBill Paul 	device_t dev;
1912f41ac2beSBill Paul {
1913f41ac2beSBill Paul 	struct bge_softc *sc;
1914f41ac2beSBill Paul 	int nseg, i, error;
1915f41ac2beSBill Paul 	struct bge_dmamap_arg ctx;
1916f41ac2beSBill Paul 
1917f41ac2beSBill Paul 	sc = device_get_softc(dev);
1918f41ac2beSBill Paul 
1919f41ac2beSBill Paul 	/*
1920f41ac2beSBill Paul 	 * Allocate the parent bus DMA tag appropriate for PCI.
1921f41ac2beSBill Paul 	 */
1922f41ac2beSBill Paul #define BGE_NSEG_NEW 32
1923f41ac2beSBill Paul 	error = bus_dma_tag_create(NULL,	/* parent */
1924f41ac2beSBill Paul 			PAGE_SIZE, 0,		/* alignment, boundary */
1925f41ac2beSBill Paul 			BUS_SPACE_MAXADDR,	/* lowaddr */
1926f41ac2beSBill Paul 			BUS_SPACE_MAXADDR_32BIT,/* highaddr */
1927f41ac2beSBill Paul 			NULL, NULL,		/* filter, filterarg */
1928f41ac2beSBill Paul 			MAXBSIZE, BGE_NSEG_NEW,	/* maxsize, nsegments */
1929f41ac2beSBill Paul 			BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1930f41ac2beSBill Paul                         BUS_DMA_ALLOCNOW,	/* flags */
1931f41ac2beSBill Paul 			NULL, NULL,		/* lockfunc, lockarg */
1932f41ac2beSBill Paul 			&sc->bge_cdata.bge_parent_tag);
1933f41ac2beSBill Paul 
1934f41ac2beSBill Paul 	/*
1935f41ac2beSBill Paul 	 * Create tag for RX mbufs.
1936f41ac2beSBill Paul 	 */
1937f41ac2beSBill Paul 	nseg = 32;
19388a2e22deSScott Long 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
1939f41ac2beSBill Paul 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1940f41ac2beSBill Paul 	    NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL,
1941f41ac2beSBill Paul 	    &sc->bge_cdata.bge_mtag);
1942f41ac2beSBill Paul 
1943f41ac2beSBill Paul 	if (error) {
1944f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
1945f41ac2beSBill Paul 		return (ENOMEM);
1946f41ac2beSBill Paul 	}
1947f41ac2beSBill Paul 
1948f41ac2beSBill Paul 	/* Create DMA maps for RX buffers */
1949f41ac2beSBill Paul 
1950f41ac2beSBill Paul 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1951f41ac2beSBill Paul 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1952f41ac2beSBill Paul 			    &sc->bge_cdata.bge_rx_std_dmamap[i]);
1953f41ac2beSBill Paul 		if (error) {
1954f41ac2beSBill Paul 			device_printf(dev, "can't create DMA map for RX\n");
1955f41ac2beSBill Paul 			return(ENOMEM);
1956f41ac2beSBill Paul 		}
1957f41ac2beSBill Paul 	}
1958f41ac2beSBill Paul 
1959f41ac2beSBill Paul 	/* Create DMA maps for TX buffers */
1960f41ac2beSBill Paul 
1961f41ac2beSBill Paul 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1962f41ac2beSBill Paul 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1963f41ac2beSBill Paul 			    &sc->bge_cdata.bge_tx_dmamap[i]);
1964f41ac2beSBill Paul 		if (error) {
1965f41ac2beSBill Paul 			device_printf(dev, "can't create DMA map for RX\n");
1966f41ac2beSBill Paul 			return(ENOMEM);
1967f41ac2beSBill Paul 		}
1968f41ac2beSBill Paul 	}
1969f41ac2beSBill Paul 
1970f41ac2beSBill Paul 	/* Create tag for standard RX ring */
1971f41ac2beSBill Paul 
1972f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1973f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1974f41ac2beSBill Paul 	    NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
1975f41ac2beSBill Paul 	    NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
1976f41ac2beSBill Paul 
1977f41ac2beSBill Paul 	if (error) {
1978f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
1979f41ac2beSBill Paul 		return (ENOMEM);
1980f41ac2beSBill Paul 	}
1981f41ac2beSBill Paul 
1982f41ac2beSBill Paul 	/* Allocate DMA'able memory for standard RX ring */
1983f41ac2beSBill Paul 
1984f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
1985f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
1986f41ac2beSBill Paul 	    &sc->bge_cdata.bge_rx_std_ring_map);
1987f41ac2beSBill Paul         if (error)
1988f41ac2beSBill Paul                 return (ENOMEM);
1989f41ac2beSBill Paul 
1990f41ac2beSBill Paul         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1991f41ac2beSBill Paul 
1992f41ac2beSBill Paul 	/* Load the address of the standard RX ring */
1993f41ac2beSBill Paul 
1994f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
1995f41ac2beSBill Paul 	ctx.sc = sc;
1996f41ac2beSBill Paul 
1997f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
1998f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
1999f41ac2beSBill Paul 	    BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2000f41ac2beSBill Paul 
2001f41ac2beSBill Paul 	if (error)
2002f41ac2beSBill Paul 		return (ENOMEM);
2003f41ac2beSBill Paul 
2004f41ac2beSBill Paul 	sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2005f41ac2beSBill Paul 
20065dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2007e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2008f41ac2beSBill Paul 
2009f41ac2beSBill Paul 		/*
2010f41ac2beSBill Paul 		 * Create tag for jumbo mbufs.
2011f41ac2beSBill Paul 		 * This is really a bit of a kludge. We allocate a special
2012f41ac2beSBill Paul 		 * jumbo buffer pool which (thanks to the way our DMA
2013f41ac2beSBill Paul 		 * memory allocation works) will consist of contiguous
2014f41ac2beSBill Paul 		 * pages. This means that even though a jumbo buffer might
2015f41ac2beSBill Paul 		 * be larger than a page size, we don't really need to
2016f41ac2beSBill Paul 		 * map it into more than one DMA segment. However, the
2017f41ac2beSBill Paul 		 * default mbuf tag will result in multi-segment mappings,
2018f41ac2beSBill Paul 		 * so we have to create a special jumbo mbuf tag that
2019f41ac2beSBill Paul 		 * lets us get away with mapping the jumbo buffers as
2020f41ac2beSBill Paul 		 * a single segment. I think eventually the driver should
2021f41ac2beSBill Paul 		 * be changed so that it uses ordinary mbufs and cluster
2022f41ac2beSBill Paul 		 * buffers, i.e. jumbo frames can span multiple DMA
2023f41ac2beSBill Paul 		 * descriptors. But that's a project for another day.
2024f41ac2beSBill Paul 		 */
2025f41ac2beSBill Paul 
2026f41ac2beSBill Paul 		error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
20278a2e22deSScott Long 		    1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2028f41ac2beSBill Paul 		    NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL,
2029f41ac2beSBill Paul 		    &sc->bge_cdata.bge_mtag_jumbo);
2030f41ac2beSBill Paul 
2031f41ac2beSBill Paul 		if (error) {
2032f41ac2beSBill Paul 			device_printf(dev, "could not allocate dma tag\n");
2033f41ac2beSBill Paul 			return (ENOMEM);
2034f41ac2beSBill Paul 		}
2035f41ac2beSBill Paul 
2036f41ac2beSBill Paul 		/* Create tag for jumbo RX ring */
2037f41ac2beSBill Paul 
2038f41ac2beSBill Paul 		error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2039f41ac2beSBill Paul 		    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2040f41ac2beSBill Paul 		    NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2041f41ac2beSBill Paul 		    NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2042f41ac2beSBill Paul 
2043f41ac2beSBill Paul 		if (error) {
2044f41ac2beSBill Paul 			device_printf(dev, "could not allocate dma tag\n");
2045f41ac2beSBill Paul 			return (ENOMEM);
2046f41ac2beSBill Paul 		}
2047f41ac2beSBill Paul 
2048f41ac2beSBill Paul 		/* Allocate DMA'able memory for jumbo RX ring */
2049f41ac2beSBill Paul 
2050f41ac2beSBill Paul 		error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2051f41ac2beSBill Paul 		    (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT,
2052f41ac2beSBill Paul 		    &sc->bge_cdata.bge_rx_jumbo_ring_map);
2053f41ac2beSBill Paul 		if (error)
2054f41ac2beSBill Paul 			return (ENOMEM);
2055f41ac2beSBill Paul 
2056f41ac2beSBill Paul 		bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring,
2057f41ac2beSBill Paul 		    BGE_JUMBO_RX_RING_SZ);
2058f41ac2beSBill Paul 
2059f41ac2beSBill Paul 		/* Load the address of the jumbo RX ring */
2060f41ac2beSBill Paul 
2061f41ac2beSBill Paul 		ctx.bge_maxsegs = 1;
2062f41ac2beSBill Paul 		ctx.sc = sc;
2063f41ac2beSBill Paul 
2064f41ac2beSBill Paul 		error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2065f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2066f41ac2beSBill Paul 		    sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2067f41ac2beSBill Paul 		    bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2068f41ac2beSBill Paul 
2069f41ac2beSBill Paul 		if (error)
2070f41ac2beSBill Paul 			return (ENOMEM);
2071f41ac2beSBill Paul 
2072f41ac2beSBill Paul 		sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2073f41ac2beSBill Paul 
2074f41ac2beSBill Paul 		/* Create DMA maps for jumbo RX buffers */
2075f41ac2beSBill Paul 
2076f41ac2beSBill Paul 		for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2077f41ac2beSBill Paul 			error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2078f41ac2beSBill Paul 				    0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2079f41ac2beSBill Paul 			if (error) {
2080f41ac2beSBill Paul 				device_printf(dev,
2081f41ac2beSBill Paul 				    "can't create DMA map for RX\n");
2082f41ac2beSBill Paul 				return(ENOMEM);
2083f41ac2beSBill Paul 			}
2084f41ac2beSBill Paul 		}
2085f41ac2beSBill Paul 
2086f41ac2beSBill Paul 	}
2087f41ac2beSBill Paul 
2088f41ac2beSBill Paul 	/* Create tag for RX return ring */
2089f41ac2beSBill Paul 
2090f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2091f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2092f41ac2beSBill Paul 	    NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2093f41ac2beSBill Paul 	    NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2094f41ac2beSBill Paul 
2095f41ac2beSBill Paul 	if (error) {
2096f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
2097f41ac2beSBill Paul 		return (ENOMEM);
2098f41ac2beSBill Paul 	}
2099f41ac2beSBill Paul 
2100f41ac2beSBill Paul 	/* Allocate DMA'able memory for RX return ring */
2101f41ac2beSBill Paul 
2102f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2103f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2104f41ac2beSBill Paul 	    &sc->bge_cdata.bge_rx_return_ring_map);
2105f41ac2beSBill Paul         if (error)
2106f41ac2beSBill Paul                 return (ENOMEM);
2107f41ac2beSBill Paul 
2108f41ac2beSBill Paul         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2109f41ac2beSBill Paul 	    BGE_RX_RTN_RING_SZ(sc));
2110f41ac2beSBill Paul 
2111f41ac2beSBill Paul 	/* Load the address of the RX return ring */
2112f41ac2beSBill Paul 
2113f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
2114f41ac2beSBill Paul 	ctx.sc = sc;
2115f41ac2beSBill Paul 
2116f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2117f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_return_ring_map,
2118f41ac2beSBill Paul 	    sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2119f41ac2beSBill Paul 	    bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2120f41ac2beSBill Paul 
2121f41ac2beSBill Paul 	if (error)
2122f41ac2beSBill Paul 		return (ENOMEM);
2123f41ac2beSBill Paul 
2124f41ac2beSBill Paul 	sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2125f41ac2beSBill Paul 
2126f41ac2beSBill Paul 	/* Create tag for TX ring */
2127f41ac2beSBill Paul 
2128f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2129f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2130f41ac2beSBill Paul 	    NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2131f41ac2beSBill Paul 	    &sc->bge_cdata.bge_tx_ring_tag);
2132f41ac2beSBill Paul 
2133f41ac2beSBill Paul 	if (error) {
2134f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
2135f41ac2beSBill Paul 		return (ENOMEM);
2136f41ac2beSBill Paul 	}
2137f41ac2beSBill Paul 
2138f41ac2beSBill Paul 	/* Allocate DMA'able memory for TX ring */
2139f41ac2beSBill Paul 
2140f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2141f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2142f41ac2beSBill Paul 	    &sc->bge_cdata.bge_tx_ring_map);
2143f41ac2beSBill Paul         if (error)
2144f41ac2beSBill Paul                 return (ENOMEM);
2145f41ac2beSBill Paul 
2146f41ac2beSBill Paul         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2147f41ac2beSBill Paul 
2148f41ac2beSBill Paul 	/* Load the address of the TX ring */
2149f41ac2beSBill Paul 
2150f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
2151f41ac2beSBill Paul 	ctx.sc = sc;
2152f41ac2beSBill Paul 
2153f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2154f41ac2beSBill Paul 	    sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2155f41ac2beSBill Paul 	    BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2156f41ac2beSBill Paul 
2157f41ac2beSBill Paul 	if (error)
2158f41ac2beSBill Paul 		return (ENOMEM);
2159f41ac2beSBill Paul 
2160f41ac2beSBill Paul 	sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2161f41ac2beSBill Paul 
2162f41ac2beSBill Paul 	/* Create tag for status block */
2163f41ac2beSBill Paul 
2164f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2165f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2166f41ac2beSBill Paul 	    NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2167f41ac2beSBill Paul 	    NULL, NULL, &sc->bge_cdata.bge_status_tag);
2168f41ac2beSBill Paul 
2169f41ac2beSBill Paul 	if (error) {
2170f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
2171f41ac2beSBill Paul 		return (ENOMEM);
2172f41ac2beSBill Paul 	}
2173f41ac2beSBill Paul 
2174f41ac2beSBill Paul 	/* Allocate DMA'able memory for status block */
2175f41ac2beSBill Paul 
2176f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2177f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2178f41ac2beSBill Paul 	    &sc->bge_cdata.bge_status_map);
2179f41ac2beSBill Paul         if (error)
2180f41ac2beSBill Paul                 return (ENOMEM);
2181f41ac2beSBill Paul 
2182f41ac2beSBill Paul         bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2183f41ac2beSBill Paul 
2184f41ac2beSBill Paul 	/* Load the address of the status block */
2185f41ac2beSBill Paul 
2186f41ac2beSBill Paul 	ctx.sc = sc;
2187f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
2188f41ac2beSBill Paul 
2189f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2190f41ac2beSBill Paul 	    sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2191f41ac2beSBill Paul 	    BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2192f41ac2beSBill Paul 
2193f41ac2beSBill Paul 	if (error)
2194f41ac2beSBill Paul 		return (ENOMEM);
2195f41ac2beSBill Paul 
2196f41ac2beSBill Paul 	sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2197f41ac2beSBill Paul 
2198f41ac2beSBill Paul 	/* Create tag for statistics block */
2199f41ac2beSBill Paul 
2200f41ac2beSBill Paul 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2201f41ac2beSBill Paul 	    PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2202f41ac2beSBill Paul 	    NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2203f41ac2beSBill Paul 	    &sc->bge_cdata.bge_stats_tag);
2204f41ac2beSBill Paul 
2205f41ac2beSBill Paul 	if (error) {
2206f41ac2beSBill Paul 		device_printf(dev, "could not allocate dma tag\n");
2207f41ac2beSBill Paul 		return (ENOMEM);
2208f41ac2beSBill Paul 	}
2209f41ac2beSBill Paul 
2210f41ac2beSBill Paul 	/* Allocate DMA'able memory for statistics block */
2211f41ac2beSBill Paul 
2212f41ac2beSBill Paul 	error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2213f41ac2beSBill Paul 	    (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2214f41ac2beSBill Paul 	    &sc->bge_cdata.bge_stats_map);
2215f41ac2beSBill Paul         if (error)
2216f41ac2beSBill Paul                 return (ENOMEM);
2217f41ac2beSBill Paul 
2218f41ac2beSBill Paul         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2219f41ac2beSBill Paul 
2220f41ac2beSBill Paul 	/* Load the address of the statstics block */
2221f41ac2beSBill Paul 
2222f41ac2beSBill Paul 	ctx.sc = sc;
2223f41ac2beSBill Paul 	ctx.bge_maxsegs = 1;
2224f41ac2beSBill Paul 
2225f41ac2beSBill Paul 	error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2226f41ac2beSBill Paul 	    sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2227f41ac2beSBill Paul 	    BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2228f41ac2beSBill Paul 
2229f41ac2beSBill Paul 	if (error)
2230f41ac2beSBill Paul 		return (ENOMEM);
2231f41ac2beSBill Paul 
2232f41ac2beSBill Paul 	sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2233f41ac2beSBill Paul 
2234f41ac2beSBill Paul 	return(0);
2235f41ac2beSBill Paul }
2236f41ac2beSBill Paul 
223795d67482SBill Paul static int
223895d67482SBill Paul bge_attach(dev)
223995d67482SBill Paul 	device_t dev;
224095d67482SBill Paul {
224195d67482SBill Paul 	struct ifnet *ifp;
224295d67482SBill Paul 	struct bge_softc *sc;
2243a1d52896SBill Paul 	u_int32_t hwcfg = 0;
2244b1265c1aSJohn Polstra 	u_int32_t mac_addr = 0;
224595d67482SBill Paul 	int unit, error = 0, rid;
224695d67482SBill Paul 
224795d67482SBill Paul 	sc = device_get_softc(dev);
224895d67482SBill Paul 	unit = device_get_unit(dev);
224995d67482SBill Paul 	sc->bge_dev = dev;
225095d67482SBill Paul 	sc->bge_unit = unit;
225195d67482SBill Paul 
225295d67482SBill Paul 	/*
225395d67482SBill Paul 	 * Map control/status registers.
225495d67482SBill Paul 	 */
225595d67482SBill Paul 	pci_enable_busmaster(dev);
225695d67482SBill Paul 
225795d67482SBill Paul 	rid = BGE_PCI_BAR0;
22585f96beb9SNate Lawson 	sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
22595f96beb9SNate Lawson 	    RF_ACTIVE|PCI_RF_DENSE);
226095d67482SBill Paul 
226195d67482SBill Paul 	if (sc->bge_res == NULL) {
226295d67482SBill Paul 		printf ("bge%d: couldn't map memory\n", unit);
226395d67482SBill Paul 		error = ENXIO;
226495d67482SBill Paul 		goto fail;
226595d67482SBill Paul 	}
226695d67482SBill Paul 
226795d67482SBill Paul 	sc->bge_btag = rman_get_bustag(sc->bge_res);
226895d67482SBill Paul 	sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
226995d67482SBill Paul 	sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
227095d67482SBill Paul 
227195d67482SBill Paul 	/* Allocate interrupt */
227295d67482SBill Paul 	rid = 0;
227395d67482SBill Paul 
22745f96beb9SNate Lawson 	sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
227595d67482SBill Paul 	    RF_SHAREABLE | RF_ACTIVE);
227695d67482SBill Paul 
227795d67482SBill Paul 	if (sc->bge_irq == NULL) {
227895d67482SBill Paul 		printf("bge%d: couldn't map interrupt\n", unit);
227995d67482SBill Paul 		error = ENXIO;
228095d67482SBill Paul 		goto fail;
228195d67482SBill Paul 	}
228295d67482SBill Paul 
228395d67482SBill Paul 	sc->bge_unit = unit;
228495d67482SBill Paul 
22850f9bd73bSSam Leffler 	BGE_LOCK_INIT(sc, device_get_nameunit(dev));
22860f9bd73bSSam Leffler 
2287e53d81eeSPaul Saab 	/* Save ASIC rev. */
2288e53d81eeSPaul Saab 
2289e53d81eeSPaul Saab 	sc->bge_chipid =
2290e53d81eeSPaul Saab 	    pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2291e53d81eeSPaul Saab 	    BGE_PCIMISCCTL_ASICREV;
2292e53d81eeSPaul Saab 	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2293e53d81eeSPaul Saab 	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2294e53d81eeSPaul Saab 
2295e53d81eeSPaul Saab 	/*
2296e53d81eeSPaul Saab 	 * XXX: Broadcom Linux driver.  Not in specs or eratta.
2297e53d81eeSPaul Saab 	 * PCI-Express?
2298e53d81eeSPaul Saab 	 */
2299e53d81eeSPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2300e53d81eeSPaul Saab 		u_int32_t v;
2301e53d81eeSPaul Saab 
2302e53d81eeSPaul Saab 		v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
2303e53d81eeSPaul Saab 		if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
2304e53d81eeSPaul Saab 			v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2305e53d81eeSPaul Saab 			if ((v & 0xff) == BGE_PCIE_CAPID)
2306e53d81eeSPaul Saab 				sc->bge_pcie = 1;
2307e53d81eeSPaul Saab 		}
2308e53d81eeSPaul Saab 	}
2309e53d81eeSPaul Saab 
231095d67482SBill Paul 	/* Try to reset the chip. */
231195d67482SBill Paul 	bge_reset(sc);
231295d67482SBill Paul 
231395d67482SBill Paul 	if (bge_chipinit(sc)) {
231495d67482SBill Paul 		printf("bge%d: chip initialization failed\n", sc->bge_unit);
231595d67482SBill Paul 		bge_release_resources(sc);
231695d67482SBill Paul 		error = ENXIO;
231795d67482SBill Paul 		goto fail;
231895d67482SBill Paul 	}
231995d67482SBill Paul 
232095d67482SBill Paul 	/*
232195d67482SBill Paul 	 * Get station address from the EEPROM.
232295d67482SBill Paul 	 */
2323b1265c1aSJohn Polstra 	mac_addr = bge_readmem_ind(sc, 0x0c14);
2324b1265c1aSJohn Polstra 	if ((mac_addr >> 16) == 0x484b) {
2325b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8);
2326b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[1] = (u_char)mac_addr;
2327b1265c1aSJohn Polstra 		mac_addr = bge_readmem_ind(sc, 0x0c18);
2328b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24);
2329b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16);
2330b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8);
2331b1265c1aSJohn Polstra 		sc->arpcom.ac_enaddr[5] = (u_char)mac_addr;
2332b1265c1aSJohn Polstra 	} else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
233395d67482SBill Paul 	    BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
233495d67482SBill Paul 		printf("bge%d: failed to read station address\n", unit);
233595d67482SBill Paul 		bge_release_resources(sc);
233695d67482SBill Paul 		error = ENXIO;
233795d67482SBill Paul 		goto fail;
233895d67482SBill Paul 	}
233995d67482SBill Paul 
2340f41ac2beSBill Paul 	/* 5705 limits RX return ring to 512 entries. */
2341e53d81eeSPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2342e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
2343f41ac2beSBill Paul 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2344f41ac2beSBill Paul 	else
2345f41ac2beSBill Paul 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2346f41ac2beSBill Paul 
2347f41ac2beSBill Paul 	if (bge_dma_alloc(dev)) {
2348f41ac2beSBill Paul 		printf ("bge%d: failed to allocate DMA resources\n",
2349f41ac2beSBill Paul 		    sc->bge_unit);
2350f41ac2beSBill Paul 		bge_release_resources(sc);
2351f41ac2beSBill Paul 		error = ENXIO;
2352f41ac2beSBill Paul 		goto fail;
2353f41ac2beSBill Paul 	}
2354f41ac2beSBill Paul 
23550434d1b8SBill Paul 	/*
23560434d1b8SBill Paul 	 * Try to allocate memory for jumbo buffers.
23570434d1b8SBill Paul 	 * The 5705 does not appear to support jumbo frames.
23580434d1b8SBill Paul 	 */
23595dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2360e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
236195d67482SBill Paul 		if (bge_alloc_jumbo_mem(sc)) {
236295d67482SBill Paul 			printf("bge%d: jumbo buffer allocation "
236395d67482SBill Paul 			    "failed\n", sc->bge_unit);
236495d67482SBill Paul 			bge_release_resources(sc);
236595d67482SBill Paul 			error = ENXIO;
236695d67482SBill Paul 			goto fail;
236795d67482SBill Paul 		}
23680434d1b8SBill Paul 	}
236995d67482SBill Paul 
237095d67482SBill Paul 	/* Set default tuneable values. */
237195d67482SBill Paul 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
237295d67482SBill Paul 	sc->bge_rx_coal_ticks = 150;
237395d67482SBill Paul 	sc->bge_tx_coal_ticks = 150;
237495d67482SBill Paul 	sc->bge_rx_max_coal_bds = 64;
237595d67482SBill Paul 	sc->bge_tx_max_coal_bds = 128;
237695d67482SBill Paul 
237795d67482SBill Paul 	/* Set up ifnet structure */
237895d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
237995d67482SBill Paul 	ifp->if_softc = sc;
23809bf40edeSBrooks Davis 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
238195d67482SBill Paul 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
238295d67482SBill Paul 	ifp->if_ioctl = bge_ioctl;
238395d67482SBill Paul 	ifp->if_start = bge_start;
238495d67482SBill Paul 	ifp->if_watchdog = bge_watchdog;
238595d67482SBill Paul 	ifp->if_init = bge_init;
238695d67482SBill Paul 	ifp->if_mtu = ETHERMTU;
238795d67482SBill Paul 	ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
238895d67482SBill Paul 	ifp->if_hwassist = BGE_CSUM_FEATURES;
2389b874fdd4SYaroslav Tykhiy 	/* NB: the code for RX csum offload is disabled for now */
2390b874fdd4SYaroslav Tykhiy 	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING |
23910434d1b8SBill Paul 	    IFCAP_VLAN_MTU;
239295d67482SBill Paul 	ifp->if_capenable = ifp->if_capabilities;
239395d67482SBill Paul 
2394a1d52896SBill Paul 	/*
2395a1d52896SBill Paul 	 * Figure out what sort of media we have by checking the
239641abcc1bSPaul Saab 	 * hardware config word in the first 32k of NIC internal memory,
239741abcc1bSPaul Saab 	 * or fall back to examining the EEPROM if necessary.
239841abcc1bSPaul Saab 	 * Note: on some BCM5700 cards, this value appears to be unset.
239941abcc1bSPaul Saab 	 * If that's the case, we have to rely on identifying the NIC
240041abcc1bSPaul Saab 	 * by its PCI subsystem ID, as we do below for the SysKonnect
240141abcc1bSPaul Saab 	 * SK-9D41.
2402a1d52896SBill Paul 	 */
240341abcc1bSPaul Saab 	if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
240441abcc1bSPaul Saab 		hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
240541abcc1bSPaul Saab 	else {
2406a1d52896SBill Paul 		bge_read_eeprom(sc, (caddr_t)&hwcfg,
2407a1d52896SBill Paul 				BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
240841abcc1bSPaul Saab 		hwcfg = ntohl(hwcfg);
240941abcc1bSPaul Saab 	}
241041abcc1bSPaul Saab 
241141abcc1bSPaul Saab 	if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2412a1d52896SBill Paul 		sc->bge_tbi = 1;
2413a1d52896SBill Paul 
241495d67482SBill Paul 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
241595d67482SBill Paul 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
241695d67482SBill Paul 		sc->bge_tbi = 1;
241795d67482SBill Paul 
241895d67482SBill Paul 	if (sc->bge_tbi) {
241995d67482SBill Paul 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
242095d67482SBill Paul 		    bge_ifmedia_upd, bge_ifmedia_sts);
242195d67482SBill Paul 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
242295d67482SBill Paul 		ifmedia_add(&sc->bge_ifmedia,
242395d67482SBill Paul 		    IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
242495d67482SBill Paul 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
242595d67482SBill Paul 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2426da3003f0SBill Paul 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
242795d67482SBill Paul 	} else {
242895d67482SBill Paul 		/*
242995d67482SBill Paul 		 * Do transceiver setup.
243095d67482SBill Paul 		 */
243195d67482SBill Paul 		if (mii_phy_probe(dev, &sc->bge_miibus,
243295d67482SBill Paul 		    bge_ifmedia_upd, bge_ifmedia_sts)) {
243395d67482SBill Paul 			printf("bge%d: MII without any PHY!\n", sc->bge_unit);
243495d67482SBill Paul 			bge_release_resources(sc);
243595d67482SBill Paul 			bge_free_jumbo_mem(sc);
243695d67482SBill Paul 			error = ENXIO;
243795d67482SBill Paul 			goto fail;
243895d67482SBill Paul 		}
243995d67482SBill Paul 	}
244095d67482SBill Paul 
244195d67482SBill Paul 	/*
2442e255b776SJohn Polstra 	 * When using the BCM5701 in PCI-X mode, data corruption has
2443e255b776SJohn Polstra 	 * been observed in the first few bytes of some received packets.
2444e255b776SJohn Polstra 	 * Aligning the packet buffer in memory eliminates the corruption.
2445e255b776SJohn Polstra 	 * Unfortunately, this misaligns the packet payloads.  On platforms
2446e255b776SJohn Polstra 	 * which do not support unaligned accesses, we will realign the
2447e255b776SJohn Polstra 	 * payloads by copying the received packets.
2448e255b776SJohn Polstra 	 */
2449e0ced696SPaul Saab 	switch (sc->bge_chipid) {
2450e0ced696SPaul Saab 	case BGE_CHIPID_BCM5701_A0:
2451e0ced696SPaul Saab 	case BGE_CHIPID_BCM5701_B0:
2452e0ced696SPaul Saab 	case BGE_CHIPID_BCM5701_B2:
2453e0ced696SPaul Saab 	case BGE_CHIPID_BCM5701_B5:
2454e255b776SJohn Polstra 		/* If in PCI-X mode, work around the alignment bug. */
2455e255b776SJohn Polstra 		if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2456e255b776SJohn Polstra 		    (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
2457e255b776SJohn Polstra 		    BGE_PCISTATE_PCI_BUSSPEED)
2458e255b776SJohn Polstra 			sc->bge_rx_alignment_bug = 1;
2459e255b776SJohn Polstra 		break;
2460e255b776SJohn Polstra 	}
2461e255b776SJohn Polstra 
2462e255b776SJohn Polstra 	/*
246395d67482SBill Paul 	 * Call MI attach routine.
246495d67482SBill Paul 	 */
2465673d9191SSam Leffler 	ether_ifattach(ifp, sc->arpcom.ac_enaddr);
24660f9bd73bSSam Leffler 	callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE);
24670f9bd73bSSam Leffler 
24680f9bd73bSSam Leffler 	/*
24690f9bd73bSSam Leffler 	 * Hookup IRQ last.
24700f9bd73bSSam Leffler 	 */
24710f9bd73bSSam Leffler 	error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
24720f9bd73bSSam Leffler 	   bge_intr, sc, &sc->bge_intrhand);
24730f9bd73bSSam Leffler 
24740f9bd73bSSam Leffler 	if (error) {
24750f9bd73bSSam Leffler 		bge_release_resources(sc);
24760f9bd73bSSam Leffler 		printf("bge%d: couldn't set up irq\n", unit);
24770f9bd73bSSam Leffler 	}
247895d67482SBill Paul 
247995d67482SBill Paul fail:
248095d67482SBill Paul 	return(error);
248195d67482SBill Paul }
248295d67482SBill Paul 
248395d67482SBill Paul static int
248495d67482SBill Paul bge_detach(dev)
248595d67482SBill Paul 	device_t dev;
248695d67482SBill Paul {
248795d67482SBill Paul 	struct bge_softc *sc;
248895d67482SBill Paul 	struct ifnet *ifp;
248995d67482SBill Paul 
249095d67482SBill Paul 	sc = device_get_softc(dev);
249195d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
249295d67482SBill Paul 
24930f9bd73bSSam Leffler 	BGE_LOCK(sc);
249495d67482SBill Paul 	bge_stop(sc);
249595d67482SBill Paul 	bge_reset(sc);
24960f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
24970f9bd73bSSam Leffler 
24980f9bd73bSSam Leffler 	ether_ifdetach(ifp);
249995d67482SBill Paul 
250095d67482SBill Paul 	if (sc->bge_tbi) {
250195d67482SBill Paul 		ifmedia_removeall(&sc->bge_ifmedia);
250295d67482SBill Paul 	} else {
250395d67482SBill Paul 		bus_generic_detach(dev);
250495d67482SBill Paul 		device_delete_child(dev, sc->bge_miibus);
250595d67482SBill Paul 	}
250695d67482SBill Paul 
250795d67482SBill Paul 	bge_release_resources(sc);
25085dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2509e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
251095d67482SBill Paul 		bge_free_jumbo_mem(sc);
251195d67482SBill Paul 
251295d67482SBill Paul 	return(0);
251395d67482SBill Paul }
251495d67482SBill Paul 
251595d67482SBill Paul static void
251695d67482SBill Paul bge_release_resources(sc)
251795d67482SBill Paul 	struct bge_softc *sc;
251895d67482SBill Paul {
251995d67482SBill Paul         device_t dev;
252095d67482SBill Paul 
252195d67482SBill Paul         dev = sc->bge_dev;
252295d67482SBill Paul 
252395d67482SBill Paul 	if (sc->bge_vpd_prodname != NULL)
252495d67482SBill Paul 		free(sc->bge_vpd_prodname, M_DEVBUF);
252595d67482SBill Paul 
252695d67482SBill Paul 	if (sc->bge_vpd_readonly != NULL)
252795d67482SBill Paul 		free(sc->bge_vpd_readonly, M_DEVBUF);
252895d67482SBill Paul 
252995d67482SBill Paul         if (sc->bge_intrhand != NULL)
253095d67482SBill Paul                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
253195d67482SBill Paul 
253295d67482SBill Paul         if (sc->bge_irq != NULL)
253395d67482SBill Paul 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
253495d67482SBill Paul 
253595d67482SBill Paul         if (sc->bge_res != NULL)
253695d67482SBill Paul 		bus_release_resource(dev, SYS_RES_MEMORY,
253795d67482SBill Paul 		    BGE_PCI_BAR0, sc->bge_res);
253895d67482SBill Paul 
2539f41ac2beSBill Paul 	bge_dma_free(sc);
254095d67482SBill Paul 
25410f9bd73bSSam Leffler 	if (mtx_initialized(&sc->bge_mtx))	/* XXX */
25420f9bd73bSSam Leffler 		BGE_LOCK_DESTROY(sc);
25430f9bd73bSSam Leffler 
254495d67482SBill Paul         return;
254595d67482SBill Paul }
254695d67482SBill Paul 
254795d67482SBill Paul static void
254895d67482SBill Paul bge_reset(sc)
254995d67482SBill Paul 	struct bge_softc *sc;
255095d67482SBill Paul {
255195d67482SBill Paul 	device_t dev;
2552e53d81eeSPaul Saab 	u_int32_t cachesize, command, pcistate, reset;
255395d67482SBill Paul 	int i, val = 0;
255495d67482SBill Paul 
255595d67482SBill Paul 	dev = sc->bge_dev;
255695d67482SBill Paul 
255795d67482SBill Paul 	/* Save some important PCI state. */
255895d67482SBill Paul 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
255995d67482SBill Paul 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
256095d67482SBill Paul 	pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
256195d67482SBill Paul 
256295d67482SBill Paul 	pci_write_config(dev, BGE_PCI_MISC_CTL,
256395d67482SBill Paul 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
256495d67482SBill Paul 	    BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
256595d67482SBill Paul 
2566e53d81eeSPaul Saab 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2567e53d81eeSPaul Saab 
2568e53d81eeSPaul Saab 	/* XXX: Broadcom Linux driver. */
2569e53d81eeSPaul Saab 	if (sc->bge_pcie) {
2570e53d81eeSPaul Saab 		if (CSR_READ_4(sc, 0x7e2c) == 0x60)	/* PCIE 1.0 */
2571e53d81eeSPaul Saab 			CSR_WRITE_4(sc, 0x7e2c, 0x20);
2572e53d81eeSPaul Saab 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2573e53d81eeSPaul Saab 			/* Prevent PCIE link training during global reset */
2574e53d81eeSPaul Saab 			CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2575e53d81eeSPaul Saab 			reset |= (1<<29);
2576e53d81eeSPaul Saab 		}
2577e53d81eeSPaul Saab 	}
2578e53d81eeSPaul Saab 
257995d67482SBill Paul 	/* Issue global reset */
2580e53d81eeSPaul Saab 	bge_writereg_ind(sc, BGE_MISC_CFG, reset);
258195d67482SBill Paul 
258295d67482SBill Paul 	DELAY(1000);
258395d67482SBill Paul 
2584e53d81eeSPaul Saab 	/* XXX: Broadcom Linux driver. */
2585e53d81eeSPaul Saab 	if (sc->bge_pcie) {
2586e53d81eeSPaul Saab 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2587e53d81eeSPaul Saab 			uint32_t v;
2588e53d81eeSPaul Saab 
2589e53d81eeSPaul Saab 			DELAY(500000); /* wait for link training to complete */
2590e53d81eeSPaul Saab 			v = pci_read_config(dev, 0xc4, 4);
2591e53d81eeSPaul Saab 			pci_write_config(dev, 0xc4, v | (1<<15), 4);
2592e53d81eeSPaul Saab 		}
2593e53d81eeSPaul Saab 		/* Set PCIE max payload size and clear error status. */
2594e53d81eeSPaul Saab 		pci_write_config(dev, 0xd8, 0xf5000, 4);
2595e53d81eeSPaul Saab 	}
2596e53d81eeSPaul Saab 
259795d67482SBill Paul 	/* Reset some of the PCI state that got zapped by reset */
259895d67482SBill Paul 	pci_write_config(dev, BGE_PCI_MISC_CTL,
259995d67482SBill Paul 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
260095d67482SBill Paul 	    BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
260195d67482SBill Paul 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
260295d67482SBill Paul 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
260395d67482SBill Paul 	bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
260495d67482SBill Paul 
2605a7b0c314SPaul Saab 	/* Enable memory arbiter. */
26065dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2607e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
2608a7b0c314SPaul Saab 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2609a7b0c314SPaul Saab 
261095d67482SBill Paul 	/*
261195d67482SBill Paul 	 * Prevent PXE restart: write a magic number to the
261295d67482SBill Paul 	 * general communications memory at 0xB50.
261395d67482SBill Paul 	 */
261495d67482SBill Paul 	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
261595d67482SBill Paul 	/*
261695d67482SBill Paul 	 * Poll the value location we just wrote until
261795d67482SBill Paul 	 * we see the 1's complement of the magic number.
261895d67482SBill Paul 	 * This indicates that the firmware initialization
261995d67482SBill Paul 	 * is complete.
262095d67482SBill Paul 	 */
262195d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
262295d67482SBill Paul 		val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
262395d67482SBill Paul 		if (val == ~BGE_MAGIC_NUMBER)
262495d67482SBill Paul 			break;
262595d67482SBill Paul 		DELAY(10);
262695d67482SBill Paul 	}
262795d67482SBill Paul 
262895d67482SBill Paul 	if (i == BGE_TIMEOUT) {
262995d67482SBill Paul 		printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
263095d67482SBill Paul 		return;
263195d67482SBill Paul 	}
263295d67482SBill Paul 
263395d67482SBill Paul 	/*
263495d67482SBill Paul 	 * XXX Wait for the value of the PCISTATE register to
263595d67482SBill Paul 	 * return to its original pre-reset state. This is a
263695d67482SBill Paul 	 * fairly good indicator of reset completion. If we don't
263795d67482SBill Paul 	 * wait for the reset to fully complete, trying to read
263895d67482SBill Paul 	 * from the device's non-PCI registers may yield garbage
263995d67482SBill Paul 	 * results.
264095d67482SBill Paul 	 */
264195d67482SBill Paul 	for (i = 0; i < BGE_TIMEOUT; i++) {
264295d67482SBill Paul 		if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
264395d67482SBill Paul 			break;
264495d67482SBill Paul 		DELAY(10);
264595d67482SBill Paul 	}
264695d67482SBill Paul 
264795d67482SBill Paul 	/* Fix up byte swapping */
264895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
264995d67482SBill Paul 	    BGE_MODECTL_BYTESWAP_DATA);
265095d67482SBill Paul 
265195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
265295d67482SBill Paul 
2653da3003f0SBill Paul 	/*
2654da3003f0SBill Paul 	 * The 5704 in TBI mode apparently needs some special
2655da3003f0SBill Paul 	 * adjustment to insure the SERDES drive level is set
2656da3003f0SBill Paul 	 * to 1.2V.
2657da3003f0SBill Paul 	 */
2658da3003f0SBill Paul 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
2659da3003f0SBill Paul 		uint32_t serdescfg;
2660da3003f0SBill Paul 		serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2661da3003f0SBill Paul 		serdescfg = (serdescfg & ~0xFFF) | 0x880;
2662da3003f0SBill Paul 		CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2663da3003f0SBill Paul 	}
2664da3003f0SBill Paul 
2665e53d81eeSPaul Saab 	/* XXX: Broadcom Linux driver. */
2666e53d81eeSPaul Saab 	if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2667e53d81eeSPaul Saab 		uint32_t v;
2668e53d81eeSPaul Saab 
2669e53d81eeSPaul Saab 		v = CSR_READ_4(sc, 0x7c00);
2670e53d81eeSPaul Saab 		CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2671e53d81eeSPaul Saab 	}
267295d67482SBill Paul 	DELAY(10000);
267395d67482SBill Paul 
267495d67482SBill Paul 	return;
267595d67482SBill Paul }
267695d67482SBill Paul 
267795d67482SBill Paul /*
267895d67482SBill Paul  * Frame reception handling. This is called if there's a frame
267995d67482SBill Paul  * on the receive return list.
268095d67482SBill Paul  *
268195d67482SBill Paul  * Note: we have to be able to handle two possibilities here:
268295d67482SBill Paul  * 1) the frame is from the jumbo recieve ring
268395d67482SBill Paul  * 2) the frame is from the standard receive ring
268495d67482SBill Paul  */
268595d67482SBill Paul 
268695d67482SBill Paul static void
268795d67482SBill Paul bge_rxeof(sc)
268895d67482SBill Paul 	struct bge_softc *sc;
268995d67482SBill Paul {
269095d67482SBill Paul 	struct ifnet *ifp;
269195d67482SBill Paul 	int stdcnt = 0, jumbocnt = 0;
269295d67482SBill Paul 
26930f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
26940f9bd73bSSam Leffler 
269595d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
269695d67482SBill Paul 
2697f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2698f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE);
2699f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2700f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
27015dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2702e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2703f41ac2beSBill Paul 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2704f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2705f41ac2beSBill Paul 		    BUS_DMASYNC_POSTREAD);
2706f41ac2beSBill Paul 	}
2707f41ac2beSBill Paul 
270895d67482SBill Paul 	while(sc->bge_rx_saved_considx !=
2709f41ac2beSBill Paul 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
271095d67482SBill Paul 		struct bge_rx_bd	*cur_rx;
271195d67482SBill Paul 		u_int32_t		rxidx;
271295d67482SBill Paul 		struct ether_header	*eh;
271395d67482SBill Paul 		struct mbuf		*m = NULL;
271495d67482SBill Paul 		u_int16_t		vlan_tag = 0;
271595d67482SBill Paul 		int			have_tag = 0;
271695d67482SBill Paul 
271795d67482SBill Paul 		cur_rx =
2718f41ac2beSBill Paul 	    &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
271995d67482SBill Paul 
272095d67482SBill Paul 		rxidx = cur_rx->bge_idx;
27210434d1b8SBill Paul 		BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
272295d67482SBill Paul 
272395d67482SBill Paul 		if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
272495d67482SBill Paul 			have_tag = 1;
272595d67482SBill Paul 			vlan_tag = cur_rx->bge_vlan_tag;
272695d67482SBill Paul 		}
272795d67482SBill Paul 
272895d67482SBill Paul 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
272995d67482SBill Paul 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2730f41ac2beSBill Paul 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
2731f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
2732f41ac2beSBill Paul 			    BUS_DMASYNC_POSTREAD);
2733f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
2734f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
273595d67482SBill Paul 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
273695d67482SBill Paul 			sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
273795d67482SBill Paul 			jumbocnt++;
273895d67482SBill Paul 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
273995d67482SBill Paul 				ifp->if_ierrors++;
274095d67482SBill Paul 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
274195d67482SBill Paul 				continue;
274295d67482SBill Paul 			}
274395d67482SBill Paul 			if (bge_newbuf_jumbo(sc,
274495d67482SBill Paul 			    sc->bge_jumbo, NULL) == ENOBUFS) {
274595d67482SBill Paul 				ifp->if_ierrors++;
274695d67482SBill Paul 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
274795d67482SBill Paul 				continue;
274895d67482SBill Paul 			}
274995d67482SBill Paul 		} else {
275095d67482SBill Paul 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2751f41ac2beSBill Paul 			bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2752f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2753f41ac2beSBill Paul 			    BUS_DMASYNC_POSTREAD);
2754f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2755f41ac2beSBill Paul 			    sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
275695d67482SBill Paul 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
275795d67482SBill Paul 			sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
275895d67482SBill Paul 			stdcnt++;
275995d67482SBill Paul 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
276095d67482SBill Paul 				ifp->if_ierrors++;
276195d67482SBill Paul 				bge_newbuf_std(sc, sc->bge_std, m);
276295d67482SBill Paul 				continue;
276395d67482SBill Paul 			}
276495d67482SBill Paul 			if (bge_newbuf_std(sc, sc->bge_std,
276595d67482SBill Paul 			    NULL) == ENOBUFS) {
276695d67482SBill Paul 				ifp->if_ierrors++;
276795d67482SBill Paul 				bge_newbuf_std(sc, sc->bge_std, m);
276895d67482SBill Paul 				continue;
276995d67482SBill Paul 			}
277095d67482SBill Paul 		}
277195d67482SBill Paul 
277295d67482SBill Paul 		ifp->if_ipackets++;
2773e255b776SJohn Polstra #ifndef __i386__
2774e255b776SJohn Polstra 		/*
2775e255b776SJohn Polstra 		 * The i386 allows unaligned accesses, but for other
2776e255b776SJohn Polstra 		 * platforms we must make sure the payload is aligned.
2777e255b776SJohn Polstra 		 */
2778e255b776SJohn Polstra 		if (sc->bge_rx_alignment_bug) {
2779e255b776SJohn Polstra 			bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2780e255b776SJohn Polstra 			    cur_rx->bge_len);
2781e255b776SJohn Polstra 			m->m_data += ETHER_ALIGN;
2782e255b776SJohn Polstra 		}
2783e255b776SJohn Polstra #endif
278495d67482SBill Paul 		eh = mtod(m, struct ether_header *);
2785473851baSPaul Saab 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
278695d67482SBill Paul 		m->m_pkthdr.rcvif = ifp;
278795d67482SBill Paul 
2788eb48892eSDavid Greenman #if 0 /* currently broken for some packets, possibly related to TCP options */
2789b874fdd4SYaroslav Tykhiy 		if (ifp->if_capenable & IFCAP_RXCSUM) {
279095d67482SBill Paul 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
279195d67482SBill Paul 			if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
279295d67482SBill Paul 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
279395d67482SBill Paul 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
279495d67482SBill Paul 				m->m_pkthdr.csum_data =
279595d67482SBill Paul 				    cur_rx->bge_tcp_udp_csum;
27960189c944SBill Paul 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
279795d67482SBill Paul 			}
279895d67482SBill Paul 		}
2799eb48892eSDavid Greenman #endif
280095d67482SBill Paul 
280195d67482SBill Paul 		/*
2802673d9191SSam Leffler 		 * If we received a packet with a vlan tag,
2803673d9191SSam Leffler 		 * attach that information to the packet.
280495d67482SBill Paul 		 */
2805673d9191SSam Leffler 		if (have_tag)
2806673d9191SSam Leffler 			VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
280795d67482SBill Paul 
28080f9bd73bSSam Leffler 		BGE_UNLOCK(sc);
2809673d9191SSam Leffler 		(*ifp->if_input)(ifp, m);
28100f9bd73bSSam Leffler 		BGE_LOCK(sc);
281195d67482SBill Paul 	}
281295d67482SBill Paul 
2813f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2814f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
2815f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2816f41ac2beSBill Paul 	    sc->bge_cdata.bge_rx_std_ring_map,
2817f41ac2beSBill Paul 	    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE);
28185dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2819e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2820f41ac2beSBill Paul 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2821f41ac2beSBill Paul 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2822f41ac2beSBill Paul 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2823f41ac2beSBill Paul 	}
2824f41ac2beSBill Paul 
282595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
282695d67482SBill Paul 	if (stdcnt)
282795d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
282895d67482SBill Paul 	if (jumbocnt)
282995d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
283095d67482SBill Paul 
283195d67482SBill Paul 	return;
283295d67482SBill Paul }
283395d67482SBill Paul 
283495d67482SBill Paul static void
283595d67482SBill Paul bge_txeof(sc)
283695d67482SBill Paul 	struct bge_softc *sc;
283795d67482SBill Paul {
283895d67482SBill Paul 	struct bge_tx_bd *cur_tx = NULL;
283995d67482SBill Paul 	struct ifnet *ifp;
284095d67482SBill Paul 
28410f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
28420f9bd73bSSam Leffler 
284395d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
284495d67482SBill Paul 
284595d67482SBill Paul 	/*
284695d67482SBill Paul 	 * Go through our tx ring and free mbufs for those
284795d67482SBill Paul 	 * frames that have been sent.
284895d67482SBill Paul 	 */
284995d67482SBill Paul 	while (sc->bge_tx_saved_considx !=
2850f41ac2beSBill Paul 	    sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
285195d67482SBill Paul 		u_int32_t		idx = 0;
285295d67482SBill Paul 
285395d67482SBill Paul 		idx = sc->bge_tx_saved_considx;
2854f41ac2beSBill Paul 		cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
285595d67482SBill Paul 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
285695d67482SBill Paul 			ifp->if_opackets++;
285795d67482SBill Paul 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
285895d67482SBill Paul 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
285995d67482SBill Paul 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
2860f41ac2beSBill Paul 			bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2861f41ac2beSBill Paul 			    sc->bge_cdata.bge_tx_dmamap[idx]);
286295d67482SBill Paul 		}
286395d67482SBill Paul 		sc->bge_txcnt--;
286495d67482SBill Paul 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
286595d67482SBill Paul 		ifp->if_timer = 0;
286695d67482SBill Paul 	}
286795d67482SBill Paul 
286895d67482SBill Paul 	if (cur_tx != NULL)
286995d67482SBill Paul 		ifp->if_flags &= ~IFF_OACTIVE;
287095d67482SBill Paul 
287195d67482SBill Paul 	return;
287295d67482SBill Paul }
287395d67482SBill Paul 
287495d67482SBill Paul static void
287595d67482SBill Paul bge_intr(xsc)
287695d67482SBill Paul 	void *xsc;
287795d67482SBill Paul {
287895d67482SBill Paul 	struct bge_softc *sc;
287995d67482SBill Paul 	struct ifnet *ifp;
2880487a8c7eSPaul Saab 	u_int32_t statusword;
2881dc961de0SBill Paul 	u_int32_t status, mimode;
288295d67482SBill Paul 
288395d67482SBill Paul 	sc = xsc;
288495d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
2885f41ac2beSBill Paul 
28860f9bd73bSSam Leffler 	BGE_LOCK(sc);
28870f9bd73bSSam Leffler 
2888f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2889f41ac2beSBill Paul 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE);
2890f41ac2beSBill Paul 
2891487a8c7eSPaul Saab 	statusword =
2892f41ac2beSBill Paul 	    atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status);
289395d67482SBill Paul 
289495d67482SBill Paul #ifdef notdef
289595d67482SBill Paul 	/* Avoid this for now -- checking this register is expensive. */
289695d67482SBill Paul 	/* Make sure this is really our interrupt. */
289795d67482SBill Paul 	if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
289895d67482SBill Paul 		return;
289995d67482SBill Paul #endif
290095d67482SBill Paul 	/* Ack interrupt and stop others from occuring. */
290195d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
290295d67482SBill Paul 
2903a1d52896SBill Paul 	/*
2904a1d52896SBill Paul 	 * Process link state changes.
2905a1d52896SBill Paul 	 * Grrr. The link status word in the status block does
2906a1d52896SBill Paul 	 * not work correctly on the BCM5700 rev AX and BX chips,
29076034c701SChristian Brueffer 	 * according to all available information. Hence, we have
2908a1d52896SBill Paul 	 * to enable MII interrupts in order to properly obtain
2909a1d52896SBill Paul 	 * async link changes. Unfortunately, this also means that
2910a1d52896SBill Paul 	 * we have to read the MAC status register to detect link
2911a1d52896SBill Paul 	 * changes, thereby adding an additional register access to
2912a1d52896SBill Paul 	 * the interrupt handler.
2913a1d52896SBill Paul 	 */
2914a1d52896SBill Paul 
2915e0ced696SPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2916a1d52896SBill Paul 
2917a1d52896SBill Paul 		status = CSR_READ_4(sc, BGE_MAC_STS);
2918a1d52896SBill Paul 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
291995d67482SBill Paul 			sc->bge_link = 0;
29200f9bd73bSSam Leffler 			callout_stop(&sc->bge_stat_ch);
29210f9bd73bSSam Leffler 			bge_tick_locked(sc);
2922a1d52896SBill Paul 			/* Clear the interrupt */
2923a1d52896SBill Paul 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2924a1d52896SBill Paul 			    BGE_EVTENB_MI_INTERRUPT);
2925a1d52896SBill Paul 			bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2926a1d52896SBill Paul 			bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2927a1d52896SBill Paul 			    BRGPHY_INTRS);
292898b28ee5SBill Paul 		}
2929a1d52896SBill Paul 	} else {
2930487a8c7eSPaul Saab 		if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
293122606b20SBill Paul 			/*
293222606b20SBill Paul 			 * Sometimes PCS encoding errors are detected in
293322606b20SBill Paul 			 * TBI mode (on fiber NICs), and for some reason
293422606b20SBill Paul 			 * the chip will signal them as link changes.
293522606b20SBill Paul 			 * If we get a link change event, but the 'PCS
293622606b20SBill Paul 			 * encoding error' bit in the MAC status register
293722606b20SBill Paul 			 * is set, don't bother doing a link check.
293822606b20SBill Paul 			 * This avoids spurious "gigabit link up" messages
293922606b20SBill Paul 			 * that sometimes appear on fiber NICs during
294022606b20SBill Paul 			 * periods of heavy traffic. (There should be no
294122606b20SBill Paul 			 * effect on copper NICs.)
2942dc961de0SBill Paul 			 *
2943dc961de0SBill Paul 			 * If we do have a copper NIC (bge_tbi == 0) then
2944dc961de0SBill Paul 			 * check that the AUTOPOLL bit is set before
2945dc961de0SBill Paul 			 * processing the event as a real link change.
2946dc961de0SBill Paul 			 * Turning AUTOPOLL on and off in the MII read/write
2947dc961de0SBill Paul 			 * functions will often trigger a link status
2948dc961de0SBill Paul 			 * interrupt for no reason.
294922606b20SBill Paul 			 */
295022606b20SBill Paul 			status = CSR_READ_4(sc, BGE_MAC_STS);
2951dc961de0SBill Paul 			mimode = CSR_READ_4(sc, BGE_MI_MODE);
2952ca3f4fd0SBill Paul 			if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2953dc961de0SBill Paul 			    BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi &&
2954dc961de0SBill Paul 			    (mimode & BGE_MIMODE_AUTOPOLL))) {
2955a1d52896SBill Paul 				sc->bge_link = 0;
29560f9bd73bSSam Leffler 				callout_stop(&sc->bge_stat_ch);
29570f9bd73bSSam Leffler 				bge_tick_locked(sc);
295822606b20SBill Paul 			}
2959a1d52896SBill Paul 			/* Clear the interrupt */
296095d67482SBill Paul 			CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
29610434d1b8SBill Paul 			    BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
29620434d1b8SBill Paul 			    BGE_MACSTAT_LINK_CHANGED);
296337ceeb4dSPaul Saab 
296437ceeb4dSPaul Saab 			/* Force flush the status block cached by PCI bridge */
296537ceeb4dSPaul Saab 			CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2966a1d52896SBill Paul 		}
296795d67482SBill Paul 	}
296895d67482SBill Paul 
296995d67482SBill Paul 	if (ifp->if_flags & IFF_RUNNING) {
297095d67482SBill Paul 		/* Check RX return ring producer/consumer */
297195d67482SBill Paul 		bge_rxeof(sc);
297295d67482SBill Paul 
297395d67482SBill Paul 		/* Check TX ring producer/consumer */
297495d67482SBill Paul 		bge_txeof(sc);
297595d67482SBill Paul 	}
297695d67482SBill Paul 
2977f41ac2beSBill Paul 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2978f41ac2beSBill Paul 	    sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE);
2979f41ac2beSBill Paul 
298095d67482SBill Paul 	bge_handle_events(sc);
298195d67482SBill Paul 
298295d67482SBill Paul 	/* Re-enable interrupts. */
298395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
298495d67482SBill Paul 
298595d67482SBill Paul 	if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
29860f9bd73bSSam Leffler 		bge_start_locked(ifp);
29870f9bd73bSSam Leffler 
29880f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
298995d67482SBill Paul 
299095d67482SBill Paul 	return;
299195d67482SBill Paul }
299295d67482SBill Paul 
299395d67482SBill Paul static void
29940f9bd73bSSam Leffler bge_tick_locked(sc)
299595d67482SBill Paul 	struct bge_softc *sc;
29960f9bd73bSSam Leffler {
299795d67482SBill Paul 	struct mii_data *mii = NULL;
299895d67482SBill Paul 	struct ifmedia *ifm = NULL;
299995d67482SBill Paul 	struct ifnet *ifp;
300095d67482SBill Paul 
300195d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
300295d67482SBill Paul 
30030f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
300495d67482SBill Paul 
3005e53d81eeSPaul Saab 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
3006e53d81eeSPaul Saab 	    sc->bge_asicrev == BGE_ASICREV_BCM5750)
30070434d1b8SBill Paul 		bge_stats_update_regs(sc);
30080434d1b8SBill Paul 	else
300995d67482SBill Paul 		bge_stats_update(sc);
30100f9bd73bSSam Leffler 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
30110f9bd73bSSam Leffler 	if (sc->bge_link)
301295d67482SBill Paul 		return;
301395d67482SBill Paul 
301495d67482SBill Paul 	if (sc->bge_tbi) {
301595d67482SBill Paul 		ifm = &sc->bge_ifmedia;
301695d67482SBill Paul 		if (CSR_READ_4(sc, BGE_MAC_STS) &
301795d67482SBill Paul 		    BGE_MACSTAT_TBI_PCS_SYNCHED) {
301895d67482SBill Paul 			sc->bge_link++;
3019da3003f0SBill Paul 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
3020da3003f0SBill Paul 				BGE_CLRBIT(sc, BGE_MAC_MODE,
3021da3003f0SBill Paul 				    BGE_MACMODE_TBI_SEND_CFGS);
302295d67482SBill Paul 			CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
302395d67482SBill Paul 			printf("bge%d: gigabit link up\n", sc->bge_unit);
302495d67482SBill Paul 			if (ifp->if_snd.ifq_head != NULL)
30250f9bd73bSSam Leffler 				bge_start_locked(ifp);
302695d67482SBill Paul 		}
302795d67482SBill Paul 		return;
302895d67482SBill Paul 	}
302995d67482SBill Paul 
303095d67482SBill Paul 	mii = device_get_softc(sc->bge_miibus);
303195d67482SBill Paul 	mii_tick(mii);
303295d67482SBill Paul 
3033b2561871SJonathan Lemon 	if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
303495d67482SBill Paul 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
303595d67482SBill Paul 		sc->bge_link++;
3036b418ad5cSPoul-Henning Kamp 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
303795d67482SBill Paul 		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
303895d67482SBill Paul 			printf("bge%d: gigabit link up\n",
303995d67482SBill Paul 			   sc->bge_unit);
304095d67482SBill Paul 		if (ifp->if_snd.ifq_head != NULL)
30410f9bd73bSSam Leffler 			bge_start_locked(ifp);
304295d67482SBill Paul 	}
304395d67482SBill Paul 
304495d67482SBill Paul 	return;
304595d67482SBill Paul }
304695d67482SBill Paul 
304795d67482SBill Paul static void
30480f9bd73bSSam Leffler bge_tick(xsc)
30490f9bd73bSSam Leffler 	void *xsc;
30500f9bd73bSSam Leffler {
30510f9bd73bSSam Leffler 	struct bge_softc *sc;
30520f9bd73bSSam Leffler 
30530f9bd73bSSam Leffler 	sc = xsc;
30540f9bd73bSSam Leffler 
30550f9bd73bSSam Leffler 	BGE_LOCK(sc);
30560f9bd73bSSam Leffler 	bge_tick_locked(sc);
30570f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
30580f9bd73bSSam Leffler }
30590f9bd73bSSam Leffler 
30600f9bd73bSSam Leffler static void
30610434d1b8SBill Paul bge_stats_update_regs(sc)
30620434d1b8SBill Paul 	struct bge_softc *sc;
30630434d1b8SBill Paul {
30640434d1b8SBill Paul 	struct ifnet *ifp;
30650434d1b8SBill Paul 	struct bge_mac_stats_regs stats;
30660434d1b8SBill Paul 	u_int32_t *s;
30670434d1b8SBill Paul 	int i;
30680434d1b8SBill Paul 
30690434d1b8SBill Paul 	ifp = &sc->arpcom.ac_if;
30700434d1b8SBill Paul 
30710434d1b8SBill Paul 	s = (u_int32_t *)&stats;
30720434d1b8SBill Paul 	for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
30730434d1b8SBill Paul 		*s = CSR_READ_4(sc, BGE_RX_STATS + i);
30740434d1b8SBill Paul 		s++;
30750434d1b8SBill Paul 	}
30760434d1b8SBill Paul 
30770434d1b8SBill Paul 	ifp->if_collisions +=
30780434d1b8SBill Paul 	   (stats.dot3StatsSingleCollisionFrames +
30790434d1b8SBill Paul 	   stats.dot3StatsMultipleCollisionFrames +
30800434d1b8SBill Paul 	   stats.dot3StatsExcessiveCollisions +
30810434d1b8SBill Paul 	   stats.dot3StatsLateCollisions) -
30820434d1b8SBill Paul 	   ifp->if_collisions;
30830434d1b8SBill Paul 
30840434d1b8SBill Paul 	return;
30850434d1b8SBill Paul }
30860434d1b8SBill Paul 
30870434d1b8SBill Paul static void
308895d67482SBill Paul bge_stats_update(sc)
308995d67482SBill Paul 	struct bge_softc *sc;
309095d67482SBill Paul {
309195d67482SBill Paul 	struct ifnet *ifp;
309295d67482SBill Paul 	struct bge_stats *stats;
309395d67482SBill Paul 
309495d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
309595d67482SBill Paul 
309695d67482SBill Paul 	stats = (struct bge_stats *)(sc->bge_vhandle +
309795d67482SBill Paul 	    BGE_MEMWIN_START + BGE_STATS_BLOCK);
309895d67482SBill Paul 
309995d67482SBill Paul 	ifp->if_collisions +=
31000434d1b8SBill Paul 	   (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
31010434d1b8SBill Paul 	   stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
31020434d1b8SBill Paul 	   stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
31030434d1b8SBill Paul 	   stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
310495d67482SBill Paul 	   ifp->if_collisions;
310595d67482SBill Paul 
310695d67482SBill Paul #ifdef notdef
310795d67482SBill Paul 	ifp->if_collisions +=
310895d67482SBill Paul 	   (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
310995d67482SBill Paul 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
311095d67482SBill Paul 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
311195d67482SBill Paul 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
311295d67482SBill Paul 	   ifp->if_collisions;
311395d67482SBill Paul #endif
311495d67482SBill Paul 
311595d67482SBill Paul 	return;
311695d67482SBill Paul }
311795d67482SBill Paul 
311895d67482SBill Paul /*
311995d67482SBill Paul  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
312095d67482SBill Paul  * pointers to descriptors.
312195d67482SBill Paul  */
312295d67482SBill Paul static int
312395d67482SBill Paul bge_encap(sc, m_head, txidx)
312495d67482SBill Paul 	struct bge_softc *sc;
312595d67482SBill Paul 	struct mbuf *m_head;
312695d67482SBill Paul 	u_int32_t *txidx;
312795d67482SBill Paul {
312895d67482SBill Paul 	struct bge_tx_bd	*f = NULL;
312995d67482SBill Paul 	u_int16_t		csum_flags = 0;
3130673d9191SSam Leffler 	struct m_tag		*mtag;
3131f41ac2beSBill Paul 	struct bge_dmamap_arg	ctx;
3132f41ac2beSBill Paul 	bus_dmamap_t		map;
3133f41ac2beSBill Paul 	int			error;
313495d67482SBill Paul 
313595d67482SBill Paul 
313695d67482SBill Paul 	if (m_head->m_pkthdr.csum_flags) {
313795d67482SBill Paul 		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
313895d67482SBill Paul 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
313995d67482SBill Paul 		if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
314095d67482SBill Paul 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
314195d67482SBill Paul 		if (m_head->m_flags & M_LASTFRAG)
314295d67482SBill Paul 			csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
314395d67482SBill Paul 		else if (m_head->m_flags & M_FRAG)
314495d67482SBill Paul 			csum_flags |= BGE_TXBDFLAG_IP_FRAG;
314595d67482SBill Paul 	}
314695d67482SBill Paul 
3147f41ac2beSBill Paul 	mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head);
3148673d9191SSam Leffler 
3149f41ac2beSBill Paul 	ctx.sc = sc;
3150f41ac2beSBill Paul 	ctx.bge_idx = *txidx;
3151f41ac2beSBill Paul 	ctx.bge_ring = sc->bge_ldata.bge_tx_ring;
3152f41ac2beSBill Paul 	ctx.bge_flags = csum_flags;
315395d67482SBill Paul 	/*
315495d67482SBill Paul 	 * Sanity check: avoid coming within 16 descriptors
315595d67482SBill Paul 	 * of the end of the ring.
315695d67482SBill Paul 	 */
3157f41ac2beSBill Paul 	ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16;
3158f41ac2beSBill Paul 
3159f41ac2beSBill Paul 	map = sc->bge_cdata.bge_tx_dmamap[*txidx];
3160f41ac2beSBill Paul 	error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
3161f41ac2beSBill Paul 	    m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT);
3162f41ac2beSBill Paul 
3163f41ac2beSBill Paul 	if (error || ctx.bge_maxsegs == 0 /*||
3164f41ac2beSBill Paul 	    ctx.bge_idx == sc->bge_tx_saved_considx*/)
316595d67482SBill Paul 		return (ENOBUFS);
3166f41ac2beSBill Paul 
3167f41ac2beSBill Paul 	/*
3168f41ac2beSBill Paul 	 * Insure that the map for this transmission
3169f41ac2beSBill Paul 	 * is placed at the array index of the last descriptor
3170f41ac2beSBill Paul 	 * in this chain.
3171f41ac2beSBill Paul 	 */
3172f41ac2beSBill Paul 	sc->bge_cdata.bge_tx_dmamap[*txidx] =
3173f41ac2beSBill Paul 	    sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx];
3174f41ac2beSBill Paul 	sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map;
3175f41ac2beSBill Paul 	sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head;
3176f41ac2beSBill Paul 	sc->bge_txcnt += ctx.bge_maxsegs;
3177f41ac2beSBill Paul 	f = &sc->bge_ldata.bge_tx_ring[*txidx];
3178f41ac2beSBill Paul 	if (mtag != NULL) {
3179f41ac2beSBill Paul 		f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG);
3180f41ac2beSBill Paul 		f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag));
3181f41ac2beSBill Paul 	} else {
3182f41ac2beSBill Paul 		f->bge_vlan_tag = 0;
318395d67482SBill Paul 	}
318495d67482SBill Paul 
3185f41ac2beSBill Paul 	BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT);
3186f41ac2beSBill Paul 	*txidx = ctx.bge_idx;
318795d67482SBill Paul 
318895d67482SBill Paul 	return(0);
318995d67482SBill Paul }
319095d67482SBill Paul 
319195d67482SBill Paul /*
319295d67482SBill Paul  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
319395d67482SBill Paul  * to the mbuf data regions directly in the transmit descriptors.
319495d67482SBill Paul  */
319595d67482SBill Paul static void
31960f9bd73bSSam Leffler bge_start_locked(ifp)
319795d67482SBill Paul 	struct ifnet *ifp;
319895d67482SBill Paul {
319995d67482SBill Paul 	struct bge_softc *sc;
320095d67482SBill Paul 	struct mbuf *m_head = NULL;
320195d67482SBill Paul 	u_int32_t prodidx = 0;
320295d67482SBill Paul 
320395d67482SBill Paul 	sc = ifp->if_softc;
320495d67482SBill Paul 
320595d67482SBill Paul 	if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
320695d67482SBill Paul 		return;
320795d67482SBill Paul 
320895d67482SBill Paul 	prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
320995d67482SBill Paul 
321095d67482SBill Paul 	while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
321195d67482SBill Paul 		IF_DEQUEUE(&ifp->if_snd, m_head);
321295d67482SBill Paul 		if (m_head == NULL)
321395d67482SBill Paul 			break;
321495d67482SBill Paul 
321595d67482SBill Paul 		/*
321695d67482SBill Paul 		 * XXX
3217b874fdd4SYaroslav Tykhiy 		 * The code inside the if() block is never reached since we
3218b874fdd4SYaroslav Tykhiy 		 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3219b874fdd4SYaroslav Tykhiy 		 * requests to checksum TCP/UDP in a fragmented packet.
3220b874fdd4SYaroslav Tykhiy 		 *
3221b874fdd4SYaroslav Tykhiy 		 * XXX
322295d67482SBill Paul 		 * safety overkill.  If this is a fragmented packet chain
322395d67482SBill Paul 		 * with delayed TCP/UDP checksums, then only encapsulate
322495d67482SBill Paul 		 * it if we have enough descriptors to handle the entire
322595d67482SBill Paul 		 * chain at once.
322695d67482SBill Paul 		 * (paranoia -- may not actually be needed)
322795d67482SBill Paul 		 */
322895d67482SBill Paul 		if (m_head->m_flags & M_FIRSTFRAG &&
322995d67482SBill Paul 		    m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
323095d67482SBill Paul 			if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
323195d67482SBill Paul 			    m_head->m_pkthdr.csum_data + 16) {
323295d67482SBill Paul 				IF_PREPEND(&ifp->if_snd, m_head);
323395d67482SBill Paul 				ifp->if_flags |= IFF_OACTIVE;
323495d67482SBill Paul 				break;
323595d67482SBill Paul 			}
323695d67482SBill Paul 		}
323795d67482SBill Paul 
323895d67482SBill Paul 		/*
323995d67482SBill Paul 		 * Pack the data into the transmit ring. If we
324095d67482SBill Paul 		 * don't have room, set the OACTIVE flag and wait
324195d67482SBill Paul 		 * for the NIC to drain the ring.
324295d67482SBill Paul 		 */
324395d67482SBill Paul 		if (bge_encap(sc, m_head, &prodidx)) {
324495d67482SBill Paul 			IF_PREPEND(&ifp->if_snd, m_head);
324595d67482SBill Paul 			ifp->if_flags |= IFF_OACTIVE;
324695d67482SBill Paul 			break;
324795d67482SBill Paul 		}
324895d67482SBill Paul 
324995d67482SBill Paul 		/*
325095d67482SBill Paul 		 * If there's a BPF listener, bounce a copy of this frame
325195d67482SBill Paul 		 * to him.
325295d67482SBill Paul 		 */
3253673d9191SSam Leffler 		BPF_MTAP(ifp, m_head);
325495d67482SBill Paul 	}
325595d67482SBill Paul 
325695d67482SBill Paul 	/* Transmit */
325795d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
32583927098fSPaul Saab 	/* 5700 b2 errata */
3259e0ced696SPaul Saab 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
32603927098fSPaul Saab 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
326195d67482SBill Paul 
326295d67482SBill Paul 	/*
326395d67482SBill Paul 	 * Set a timeout in case the chip goes out to lunch.
326495d67482SBill Paul 	 */
326595d67482SBill Paul 	ifp->if_timer = 5;
326695d67482SBill Paul 
326795d67482SBill Paul 	return;
326895d67482SBill Paul }
326995d67482SBill Paul 
32700f9bd73bSSam Leffler /*
32710f9bd73bSSam Leffler  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
32720f9bd73bSSam Leffler  * to the mbuf data regions directly in the transmit descriptors.
32730f9bd73bSSam Leffler  */
327495d67482SBill Paul static void
32750f9bd73bSSam Leffler bge_start(ifp)
32760f9bd73bSSam Leffler 	struct ifnet *ifp;
327795d67482SBill Paul {
32780f9bd73bSSam Leffler 	struct bge_softc *sc;
32790f9bd73bSSam Leffler 
32800f9bd73bSSam Leffler 	sc = ifp->if_softc;
32810f9bd73bSSam Leffler 	BGE_LOCK(sc);
32820f9bd73bSSam Leffler 	bge_start_locked(ifp);
32830f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
32840f9bd73bSSam Leffler }
32850f9bd73bSSam Leffler 
32860f9bd73bSSam Leffler static void
32870f9bd73bSSam Leffler bge_init_locked(sc)
32880f9bd73bSSam Leffler 	struct bge_softc *sc;
32890f9bd73bSSam Leffler {
329095d67482SBill Paul 	struct ifnet *ifp;
329195d67482SBill Paul 	u_int16_t *m;
329295d67482SBill Paul 
32930f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
329495d67482SBill Paul 
329595d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
329695d67482SBill Paul 
32970f9bd73bSSam Leffler 	if (ifp->if_flags & IFF_RUNNING)
329895d67482SBill Paul 		return;
329995d67482SBill Paul 
330095d67482SBill Paul 	/* Cancel pending I/O and flush buffers. */
330195d67482SBill Paul 	bge_stop(sc);
330295d67482SBill Paul 	bge_reset(sc);
330395d67482SBill Paul 	bge_chipinit(sc);
330495d67482SBill Paul 
330595d67482SBill Paul 	/*
330695d67482SBill Paul 	 * Init the various state machines, ring
330795d67482SBill Paul 	 * control blocks and firmware.
330895d67482SBill Paul 	 */
330995d67482SBill Paul 	if (bge_blockinit(sc)) {
331095d67482SBill Paul 		printf("bge%d: initialization failure\n", sc->bge_unit);
331195d67482SBill Paul 		return;
331295d67482SBill Paul 	}
331395d67482SBill Paul 
331495d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
331595d67482SBill Paul 
331695d67482SBill Paul 	/* Specify MTU. */
331795d67482SBill Paul 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3318859c6c7dSBill Paul 	    ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
331995d67482SBill Paul 
332095d67482SBill Paul 	/* Load our MAC address. */
332195d67482SBill Paul 	m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
332295d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
332395d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
332495d67482SBill Paul 
332595d67482SBill Paul 	/* Enable or disable promiscuous mode as needed. */
332695d67482SBill Paul 	if (ifp->if_flags & IFF_PROMISC) {
332795d67482SBill Paul 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
332895d67482SBill Paul 	} else {
332995d67482SBill Paul 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
333095d67482SBill Paul 	}
333195d67482SBill Paul 
333295d67482SBill Paul 	/* Program multicast filter. */
333395d67482SBill Paul 	bge_setmulti(sc);
333495d67482SBill Paul 
333595d67482SBill Paul 	/* Init RX ring. */
333695d67482SBill Paul 	bge_init_rx_ring_std(sc);
333795d67482SBill Paul 
33380434d1b8SBill Paul 	/*
33390434d1b8SBill Paul 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
33400434d1b8SBill Paul 	 * memory to insure that the chip has in fact read the first
33410434d1b8SBill Paul 	 * entry of the ring.
33420434d1b8SBill Paul 	 */
33430434d1b8SBill Paul 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
33440434d1b8SBill Paul 		u_int32_t		v, i;
33450434d1b8SBill Paul 		for (i = 0; i < 10; i++) {
33460434d1b8SBill Paul 			DELAY(20);
33470434d1b8SBill Paul 			v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
33480434d1b8SBill Paul 			if (v == (MCLBYTES - ETHER_ALIGN))
33490434d1b8SBill Paul 				break;
33500434d1b8SBill Paul 		}
33510434d1b8SBill Paul 		if (i == 10)
33520434d1b8SBill Paul 			printf ("bge%d: 5705 A0 chip failed to load RX ring\n",
33530434d1b8SBill Paul 			    sc->bge_unit);
33540434d1b8SBill Paul 	}
33550434d1b8SBill Paul 
335695d67482SBill Paul 	/* Init jumbo RX ring. */
335795d67482SBill Paul 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
335895d67482SBill Paul 		bge_init_rx_ring_jumbo(sc);
335995d67482SBill Paul 
336095d67482SBill Paul 	/* Init our RX return ring index */
336195d67482SBill Paul 	sc->bge_rx_saved_considx = 0;
336295d67482SBill Paul 
336395d67482SBill Paul 	/* Init TX ring. */
336495d67482SBill Paul 	bge_init_tx_ring(sc);
336595d67482SBill Paul 
336695d67482SBill Paul 	/* Turn on transmitter */
336795d67482SBill Paul 	BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
336895d67482SBill Paul 
336995d67482SBill Paul 	/* Turn on receiver */
337095d67482SBill Paul 	BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
337195d67482SBill Paul 
337295d67482SBill Paul 	/* Tell firmware we're alive. */
337395d67482SBill Paul 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
337495d67482SBill Paul 
337595d67482SBill Paul 	/* Enable host interrupts. */
337695d67482SBill Paul 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
337795d67482SBill Paul 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
337895d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
337995d67482SBill Paul 
338095d67482SBill Paul 	bge_ifmedia_upd(ifp);
338195d67482SBill Paul 
338295d67482SBill Paul 	ifp->if_flags |= IFF_RUNNING;
338395d67482SBill Paul 	ifp->if_flags &= ~IFF_OACTIVE;
338495d67482SBill Paul 
33850f9bd73bSSam Leffler 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
338695d67482SBill Paul 
33870f9bd73bSSam Leffler 	return;
33880f9bd73bSSam Leffler }
33890f9bd73bSSam Leffler 
33900f9bd73bSSam Leffler static void
33910f9bd73bSSam Leffler bge_init(xsc)
33920f9bd73bSSam Leffler 	void *xsc;
33930f9bd73bSSam Leffler {
33940f9bd73bSSam Leffler 	struct bge_softc *sc = xsc;
33950f9bd73bSSam Leffler 
33960f9bd73bSSam Leffler 	BGE_LOCK(sc);
33970f9bd73bSSam Leffler 	bge_init_locked(sc);
33980f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
339995d67482SBill Paul 
340095d67482SBill Paul 	return;
340195d67482SBill Paul }
340295d67482SBill Paul 
340395d67482SBill Paul /*
340495d67482SBill Paul  * Set media options.
340595d67482SBill Paul  */
340695d67482SBill Paul static int
340795d67482SBill Paul bge_ifmedia_upd(ifp)
340895d67482SBill Paul 	struct ifnet *ifp;
340995d67482SBill Paul {
341095d67482SBill Paul 	struct bge_softc *sc;
341195d67482SBill Paul 	struct mii_data *mii;
341295d67482SBill Paul 	struct ifmedia *ifm;
341395d67482SBill Paul 
341495d67482SBill Paul 	sc = ifp->if_softc;
341595d67482SBill Paul 	ifm = &sc->bge_ifmedia;
341695d67482SBill Paul 
341795d67482SBill Paul 	/* If this is a 1000baseX NIC, enable the TBI port. */
341895d67482SBill Paul 	if (sc->bge_tbi) {
341995d67482SBill Paul 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
342095d67482SBill Paul 			return(EINVAL);
342195d67482SBill Paul 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
342295d67482SBill Paul 		case IFM_AUTO:
3423da3003f0SBill Paul 			/*
3424da3003f0SBill Paul 			 * The BCM5704 ASIC appears to have a special
3425da3003f0SBill Paul 			 * mechanism for programming the autoneg
3426da3003f0SBill Paul 			 * advertisement registers in TBI mode.
3427da3003f0SBill Paul 			 */
3428da3003f0SBill Paul 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3429da3003f0SBill Paul 				uint32_t sgdig;
3430da3003f0SBill Paul 				CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3431da3003f0SBill Paul 				sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3432da3003f0SBill Paul 				sgdig |= BGE_SGDIGCFG_AUTO|
3433da3003f0SBill Paul 				    BGE_SGDIGCFG_PAUSE_CAP|
3434da3003f0SBill Paul 				    BGE_SGDIGCFG_ASYM_PAUSE;
3435da3003f0SBill Paul 				CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3436da3003f0SBill Paul 				    sgdig|BGE_SGDIGCFG_SEND);
3437da3003f0SBill Paul 				DELAY(5);
3438da3003f0SBill Paul 				CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3439da3003f0SBill Paul 			}
344095d67482SBill Paul 			break;
344195d67482SBill Paul 		case IFM_1000_SX:
344295d67482SBill Paul 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
344395d67482SBill Paul 				BGE_CLRBIT(sc, BGE_MAC_MODE,
344495d67482SBill Paul 				    BGE_MACMODE_HALF_DUPLEX);
344595d67482SBill Paul 			} else {
344695d67482SBill Paul 				BGE_SETBIT(sc, BGE_MAC_MODE,
344795d67482SBill Paul 				    BGE_MACMODE_HALF_DUPLEX);
344895d67482SBill Paul 			}
344995d67482SBill Paul 			break;
345095d67482SBill Paul 		default:
345195d67482SBill Paul 			return(EINVAL);
345295d67482SBill Paul 		}
345395d67482SBill Paul 		return(0);
345495d67482SBill Paul 	}
345595d67482SBill Paul 
345695d67482SBill Paul 	mii = device_get_softc(sc->bge_miibus);
345795d67482SBill Paul 	sc->bge_link = 0;
345895d67482SBill Paul 	if (mii->mii_instance) {
345995d67482SBill Paul 		struct mii_softc *miisc;
346095d67482SBill Paul 		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
346195d67482SBill Paul 		    miisc = LIST_NEXT(miisc, mii_list))
346295d67482SBill Paul 			mii_phy_reset(miisc);
346395d67482SBill Paul 	}
346495d67482SBill Paul 	mii_mediachg(mii);
346595d67482SBill Paul 
346695d67482SBill Paul 	return(0);
346795d67482SBill Paul }
346895d67482SBill Paul 
346995d67482SBill Paul /*
347095d67482SBill Paul  * Report current media status.
347195d67482SBill Paul  */
347295d67482SBill Paul static void
347395d67482SBill Paul bge_ifmedia_sts(ifp, ifmr)
347495d67482SBill Paul 	struct ifnet *ifp;
347595d67482SBill Paul 	struct ifmediareq *ifmr;
347695d67482SBill Paul {
347795d67482SBill Paul 	struct bge_softc *sc;
347895d67482SBill Paul 	struct mii_data *mii;
347995d67482SBill Paul 
348095d67482SBill Paul 	sc = ifp->if_softc;
348195d67482SBill Paul 
348295d67482SBill Paul 	if (sc->bge_tbi) {
348395d67482SBill Paul 		ifmr->ifm_status = IFM_AVALID;
348495d67482SBill Paul 		ifmr->ifm_active = IFM_ETHER;
348595d67482SBill Paul 		if (CSR_READ_4(sc, BGE_MAC_STS) &
348695d67482SBill Paul 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
348795d67482SBill Paul 			ifmr->ifm_status |= IFM_ACTIVE;
348895d67482SBill Paul 		ifmr->ifm_active |= IFM_1000_SX;
348995d67482SBill Paul 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
349095d67482SBill Paul 			ifmr->ifm_active |= IFM_HDX;
349195d67482SBill Paul 		else
349295d67482SBill Paul 			ifmr->ifm_active |= IFM_FDX;
349395d67482SBill Paul 		return;
349495d67482SBill Paul 	}
349595d67482SBill Paul 
349695d67482SBill Paul 	mii = device_get_softc(sc->bge_miibus);
349795d67482SBill Paul 	mii_pollstat(mii);
349895d67482SBill Paul 	ifmr->ifm_active = mii->mii_media_active;
349995d67482SBill Paul 	ifmr->ifm_status = mii->mii_media_status;
350095d67482SBill Paul 
350195d67482SBill Paul 	return;
350295d67482SBill Paul }
350395d67482SBill Paul 
350495d67482SBill Paul static int
350595d67482SBill Paul bge_ioctl(ifp, command, data)
350695d67482SBill Paul 	struct ifnet *ifp;
350795d67482SBill Paul 	u_long command;
350895d67482SBill Paul 	caddr_t data;
350995d67482SBill Paul {
351095d67482SBill Paul 	struct bge_softc *sc = ifp->if_softc;
351195d67482SBill Paul 	struct ifreq *ifr = (struct ifreq *) data;
35120f9bd73bSSam Leffler 	int mask, error = 0;
351395d67482SBill Paul 	struct mii_data *mii;
351495d67482SBill Paul 
351595d67482SBill Paul 	switch(command) {
351695d67482SBill Paul 	case SIOCSIFMTU:
35170434d1b8SBill Paul 		/* Disallow jumbo frames on 5705. */
3518e53d81eeSPaul Saab 		if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
3519e53d81eeSPaul Saab 		      sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
35200434d1b8SBill Paul 		    ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
352195d67482SBill Paul 			error = EINVAL;
352295d67482SBill Paul 		else {
352395d67482SBill Paul 			ifp->if_mtu = ifr->ifr_mtu;
352495d67482SBill Paul 			ifp->if_flags &= ~IFF_RUNNING;
352595d67482SBill Paul 			bge_init(sc);
352695d67482SBill Paul 		}
352795d67482SBill Paul 		break;
352895d67482SBill Paul 	case SIOCSIFFLAGS:
35290f9bd73bSSam Leffler 		BGE_LOCK(sc);
353095d67482SBill Paul 		if (ifp->if_flags & IFF_UP) {
353195d67482SBill Paul 			/*
353295d67482SBill Paul 			 * If only the state of the PROMISC flag changed,
353395d67482SBill Paul 			 * then just use the 'set promisc mode' command
353495d67482SBill Paul 			 * instead of reinitializing the entire NIC. Doing
353595d67482SBill Paul 			 * a full re-init means reloading the firmware and
353695d67482SBill Paul 			 * waiting for it to start up, which may take a
353795d67482SBill Paul 			 * second or two.
353895d67482SBill Paul 			 */
353995d67482SBill Paul 			if (ifp->if_flags & IFF_RUNNING &&
354095d67482SBill Paul 			    ifp->if_flags & IFF_PROMISC &&
354195d67482SBill Paul 			    !(sc->bge_if_flags & IFF_PROMISC)) {
354295d67482SBill Paul 				BGE_SETBIT(sc, BGE_RX_MODE,
354395d67482SBill Paul 				    BGE_RXMODE_RX_PROMISC);
354495d67482SBill Paul 			} else if (ifp->if_flags & IFF_RUNNING &&
354595d67482SBill Paul 			    !(ifp->if_flags & IFF_PROMISC) &&
354695d67482SBill Paul 			    sc->bge_if_flags & IFF_PROMISC) {
354795d67482SBill Paul 				BGE_CLRBIT(sc, BGE_RX_MODE,
354895d67482SBill Paul 				    BGE_RXMODE_RX_PROMISC);
354995d67482SBill Paul 			} else
35500f9bd73bSSam Leffler 				bge_init_locked(sc);
355195d67482SBill Paul 		} else {
355295d67482SBill Paul 			if (ifp->if_flags & IFF_RUNNING) {
355395d67482SBill Paul 				bge_stop(sc);
355495d67482SBill Paul 			}
355595d67482SBill Paul 		}
355695d67482SBill Paul 		sc->bge_if_flags = ifp->if_flags;
35570f9bd73bSSam Leffler 		BGE_UNLOCK(sc);
355895d67482SBill Paul 		error = 0;
355995d67482SBill Paul 		break;
356095d67482SBill Paul 	case SIOCADDMULTI:
356195d67482SBill Paul 	case SIOCDELMULTI:
356295d67482SBill Paul 		if (ifp->if_flags & IFF_RUNNING) {
35630f9bd73bSSam Leffler 			BGE_LOCK(sc);
356495d67482SBill Paul 			bge_setmulti(sc);
35650f9bd73bSSam Leffler 			BGE_UNLOCK(sc);
356695d67482SBill Paul 			error = 0;
356795d67482SBill Paul 		}
356895d67482SBill Paul 		break;
356995d67482SBill Paul 	case SIOCSIFMEDIA:
357095d67482SBill Paul 	case SIOCGIFMEDIA:
357195d67482SBill Paul 		if (sc->bge_tbi) {
357295d67482SBill Paul 			error = ifmedia_ioctl(ifp, ifr,
357395d67482SBill Paul 			    &sc->bge_ifmedia, command);
357495d67482SBill Paul 		} else {
357595d67482SBill Paul 			mii = device_get_softc(sc->bge_miibus);
357695d67482SBill Paul 			error = ifmedia_ioctl(ifp, ifr,
357795d67482SBill Paul 			    &mii->mii_media, command);
357895d67482SBill Paul 		}
357995d67482SBill Paul 		break;
358095d67482SBill Paul         case SIOCSIFCAP:
358195d67482SBill Paul 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3582b874fdd4SYaroslav Tykhiy 		/* NB: the code for RX csum offload is disabled for now */
3583b874fdd4SYaroslav Tykhiy 		if (mask & IFCAP_TXCSUM) {
3584b874fdd4SYaroslav Tykhiy 			ifp->if_capenable ^= IFCAP_TXCSUM;
3585b874fdd4SYaroslav Tykhiy 			if (IFCAP_TXCSUM & ifp->if_capenable)
3586b874fdd4SYaroslav Tykhiy 				ifp->if_hwassist = BGE_CSUM_FEATURES;
358795d67482SBill Paul 			else
3588b874fdd4SYaroslav Tykhiy 				ifp->if_hwassist = 0;
358995d67482SBill Paul 		}
359095d67482SBill Paul 		error = 0;
359195d67482SBill Paul 		break;
359295d67482SBill Paul 	default:
3593673d9191SSam Leffler 		error = ether_ioctl(ifp, command, data);
359495d67482SBill Paul 		break;
359595d67482SBill Paul 	}
359695d67482SBill Paul 
359795d67482SBill Paul 	return(error);
359895d67482SBill Paul }
359995d67482SBill Paul 
360095d67482SBill Paul static void
360195d67482SBill Paul bge_watchdog(ifp)
360295d67482SBill Paul 	struct ifnet *ifp;
360395d67482SBill Paul {
360495d67482SBill Paul 	struct bge_softc *sc;
360595d67482SBill Paul 
360695d67482SBill Paul 	sc = ifp->if_softc;
360795d67482SBill Paul 
360895d67482SBill Paul 	printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
360995d67482SBill Paul 
361095d67482SBill Paul 	ifp->if_flags &= ~IFF_RUNNING;
361195d67482SBill Paul 	bge_init(sc);
361295d67482SBill Paul 
361395d67482SBill Paul 	ifp->if_oerrors++;
361495d67482SBill Paul 
361595d67482SBill Paul 	return;
361695d67482SBill Paul }
361795d67482SBill Paul 
361895d67482SBill Paul /*
361995d67482SBill Paul  * Stop the adapter and free any mbufs allocated to the
362095d67482SBill Paul  * RX and TX lists.
362195d67482SBill Paul  */
362295d67482SBill Paul static void
362395d67482SBill Paul bge_stop(sc)
362495d67482SBill Paul 	struct bge_softc *sc;
362595d67482SBill Paul {
362695d67482SBill Paul 	struct ifnet *ifp;
362795d67482SBill Paul 	struct ifmedia_entry *ifm;
362895d67482SBill Paul 	struct mii_data *mii = NULL;
362995d67482SBill Paul 	int mtmp, itmp;
363095d67482SBill Paul 
36310f9bd73bSSam Leffler 	BGE_LOCK_ASSERT(sc);
36320f9bd73bSSam Leffler 
363395d67482SBill Paul 	ifp = &sc->arpcom.ac_if;
363495d67482SBill Paul 
363595d67482SBill Paul 	if (!sc->bge_tbi)
363695d67482SBill Paul 		mii = device_get_softc(sc->bge_miibus);
363795d67482SBill Paul 
36380f9bd73bSSam Leffler 	callout_stop(&sc->bge_stat_ch);
363995d67482SBill Paul 
364095d67482SBill Paul 	/*
364195d67482SBill Paul 	 * Disable all of the receiver blocks
364295d67482SBill Paul 	 */
364395d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
364495d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
364595d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
36465dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3647e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
364895d67482SBill Paul 		BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
364995d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
365095d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
365195d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
365295d67482SBill Paul 
365395d67482SBill Paul 	/*
365495d67482SBill Paul 	 * Disable all of the transmit blocks
365595d67482SBill Paul 	 */
365695d67482SBill Paul 	BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
365795d67482SBill Paul 	BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
365895d67482SBill Paul 	BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
365995d67482SBill Paul 	BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
366095d67482SBill Paul 	BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
36615dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3662e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
366395d67482SBill Paul 		BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
366495d67482SBill Paul 	BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
366595d67482SBill Paul 
366695d67482SBill Paul 	/*
366795d67482SBill Paul 	 * Shut down all of the memory managers and related
366895d67482SBill Paul 	 * state machines.
366995d67482SBill Paul 	 */
367095d67482SBill Paul 	BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
367195d67482SBill Paul 	BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
36725dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3673e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
367495d67482SBill Paul 		BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
367595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
367695d67482SBill Paul 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
36775dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3678e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750) {
367995d67482SBill Paul 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
368095d67482SBill Paul 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
36810434d1b8SBill Paul 	}
368295d67482SBill Paul 
368395d67482SBill Paul 	/* Disable host interrupts. */
368495d67482SBill Paul 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
368595d67482SBill Paul 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
368695d67482SBill Paul 
368795d67482SBill Paul 	/*
368895d67482SBill Paul 	 * Tell firmware we're shutting down.
368995d67482SBill Paul 	 */
369095d67482SBill Paul 	BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
369195d67482SBill Paul 
369295d67482SBill Paul 	/* Free the RX lists. */
369395d67482SBill Paul 	bge_free_rx_ring_std(sc);
369495d67482SBill Paul 
369595d67482SBill Paul 	/* Free jumbo RX list. */
36965dc9afc5SPaul Saab 	if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3697e53d81eeSPaul Saab 	    sc->bge_asicrev != BGE_ASICREV_BCM5750)
369895d67482SBill Paul 		bge_free_rx_ring_jumbo(sc);
369995d67482SBill Paul 
370095d67482SBill Paul 	/* Free TX buffers. */
370195d67482SBill Paul 	bge_free_tx_ring(sc);
370295d67482SBill Paul 
370395d67482SBill Paul 	/*
370495d67482SBill Paul 	 * Isolate/power down the PHY, but leave the media selection
370595d67482SBill Paul 	 * unchanged so that things will be put back to normal when
370695d67482SBill Paul 	 * we bring the interface back up.
370795d67482SBill Paul 	 */
370895d67482SBill Paul 	if (!sc->bge_tbi) {
370995d67482SBill Paul 		itmp = ifp->if_flags;
371095d67482SBill Paul 		ifp->if_flags |= IFF_UP;
371195d67482SBill Paul 		ifm = mii->mii_media.ifm_cur;
371295d67482SBill Paul 		mtmp = ifm->ifm_media;
371395d67482SBill Paul 		ifm->ifm_media = IFM_ETHER|IFM_NONE;
371495d67482SBill Paul 		mii_mediachg(mii);
371595d67482SBill Paul 		ifm->ifm_media = mtmp;
371695d67482SBill Paul 		ifp->if_flags = itmp;
371795d67482SBill Paul 	}
371895d67482SBill Paul 
371995d67482SBill Paul 	sc->bge_link = 0;
372095d67482SBill Paul 
372195d67482SBill Paul 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
372295d67482SBill Paul 
372395d67482SBill Paul 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
372495d67482SBill Paul 
372595d67482SBill Paul 	return;
372695d67482SBill Paul }
372795d67482SBill Paul 
372895d67482SBill Paul /*
372995d67482SBill Paul  * Stop all chip I/O so that the kernel's probe routines don't
373095d67482SBill Paul  * get confused by errant DMAs when rebooting.
373195d67482SBill Paul  */
373295d67482SBill Paul static void
373395d67482SBill Paul bge_shutdown(dev)
373495d67482SBill Paul 	device_t dev;
373595d67482SBill Paul {
373695d67482SBill Paul 	struct bge_softc *sc;
373795d67482SBill Paul 
373895d67482SBill Paul 	sc = device_get_softc(dev);
373995d67482SBill Paul 
37400f9bd73bSSam Leffler 	BGE_LOCK(sc);
374195d67482SBill Paul 	bge_stop(sc);
374295d67482SBill Paul 	bge_reset(sc);
37430f9bd73bSSam Leffler 	BGE_UNLOCK(sc);
374495d67482SBill Paul 
374595d67482SBill Paul 	return;
374695d67482SBill Paul }
3747