1098ca2bdSWarner Losh /*- 295d67482SBill Paul * Copyright (c) 2001 Wind River Systems 395d67482SBill Paul * Copyright (c) 1997, 1998, 1999, 2001 495d67482SBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 595d67482SBill Paul * 695d67482SBill Paul * Redistribution and use in source and binary forms, with or without 795d67482SBill Paul * modification, are permitted provided that the following conditions 895d67482SBill Paul * are met: 995d67482SBill Paul * 1. Redistributions of source code must retain the above copyright 1095d67482SBill Paul * notice, this list of conditions and the following disclaimer. 1195d67482SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1295d67482SBill Paul * notice, this list of conditions and the following disclaimer in the 1395d67482SBill Paul * documentation and/or other materials provided with the distribution. 1495d67482SBill Paul * 3. All advertising materials mentioning features or use of this software 1595d67482SBill Paul * must display the following acknowledgement: 1695d67482SBill Paul * This product includes software developed by Bill Paul. 1795d67482SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1895d67482SBill Paul * may be used to endorse or promote products derived from this software 1995d67482SBill Paul * without specific prior written permission. 2095d67482SBill Paul * 2195d67482SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2295d67482SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2395d67482SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2495d67482SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2595d67482SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2695d67482SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2795d67482SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2895d67482SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2995d67482SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3095d67482SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3195d67482SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3295d67482SBill Paul */ 3395d67482SBill Paul 34aad970f1SDavid E. O'Brien #include <sys/cdefs.h> 35aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$"); 36aad970f1SDavid E. O'Brien 3795d67482SBill Paul /* 3895d67482SBill Paul * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 3995d67482SBill Paul * 4095d67482SBill Paul * The Broadcom BCM5700 is based on technology originally developed by 4195d67482SBill Paul * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 4295d67482SBill Paul * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 4395d67482SBill Paul * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 4495d67482SBill Paul * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 4595d67482SBill Paul * frames, highly configurable RX filtering, and 16 RX and TX queues 4695d67482SBill Paul * (which, along with RX filter rules, can be used for QOS applications). 4795d67482SBill Paul * Other features, such as TCP segmentation, may be available as part 4895d67482SBill Paul * of value-added firmware updates. Unlike the Tigon I and Tigon II, 4995d67482SBill Paul * firmware images can be stored in hardware and need not be compiled 5095d67482SBill Paul * into the driver. 5195d67482SBill Paul * 5295d67482SBill Paul * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 5395d67482SBill Paul * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 5495d67482SBill Paul * 5595d67482SBill Paul * The BCM5701 is a single-chip solution incorporating both the BCM5700 5698b28ee5SBill Paul * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 5795d67482SBill Paul * does not support external SSRAM. 5895d67482SBill Paul * 5995d67482SBill Paul * Broadcom also produces a variation of the BCM5700 under the "Altima" 6095d67482SBill Paul * brand name, which is functionally similar but lacks PCI-X support. 6195d67482SBill Paul * 6295d67482SBill Paul * Without external SSRAM, you can only have at most 4 TX rings, 6395d67482SBill Paul * and the use of the mini RX ring is disabled. This seems to imply 6495d67482SBill Paul * that these features are simply not available on the BCM5701. As a 6595d67482SBill Paul * result, this driver does not implement any support for the mini RX 6695d67482SBill Paul * ring. 6795d67482SBill Paul */ 6895d67482SBill Paul 6975719184SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 7075719184SGleb Smirnoff #include "opt_device_polling.h" 7175719184SGleb Smirnoff #endif 7275719184SGleb Smirnoff 7395d67482SBill Paul #include <sys/param.h> 74f41ac2beSBill Paul #include <sys/endian.h> 7595d67482SBill Paul #include <sys/systm.h> 7695d67482SBill Paul #include <sys/sockio.h> 7795d67482SBill Paul #include <sys/mbuf.h> 7895d67482SBill Paul #include <sys/malloc.h> 7995d67482SBill Paul #include <sys/kernel.h> 80fe12f24bSPoul-Henning Kamp #include <sys/module.h> 8195d67482SBill Paul #include <sys/socket.h> 82f1a7e6d5SScott Long #include <sys/sysctl.h> 83dfe0df9aSPyun YongHyeon #include <sys/taskqueue.h> 8495d67482SBill Paul 8595d67482SBill Paul #include <net/if.h> 8695d67482SBill Paul #include <net/if_arp.h> 8795d67482SBill Paul #include <net/ethernet.h> 8895d67482SBill Paul #include <net/if_dl.h> 8995d67482SBill Paul #include <net/if_media.h> 9095d67482SBill Paul 9195d67482SBill Paul #include <net/bpf.h> 9295d67482SBill Paul 9395d67482SBill Paul #include <net/if_types.h> 9495d67482SBill Paul #include <net/if_vlan_var.h> 9595d67482SBill Paul 9695d67482SBill Paul #include <netinet/in_systm.h> 9795d67482SBill Paul #include <netinet/in.h> 9895d67482SBill Paul #include <netinet/ip.h> 99ca3f1187SPyun YongHyeon #include <netinet/tcp.h> 10095d67482SBill Paul 10195d67482SBill Paul #include <machine/bus.h> 10295d67482SBill Paul #include <machine/resource.h> 10395d67482SBill Paul #include <sys/bus.h> 10495d67482SBill Paul #include <sys/rman.h> 10595d67482SBill Paul 10695d67482SBill Paul #include <dev/mii/mii.h> 10795d67482SBill Paul #include <dev/mii/miivar.h> 1082d3ce713SDavid E. O'Brien #include "miidevs.h" 10995d67482SBill Paul #include <dev/mii/brgphyreg.h> 11095d67482SBill Paul 11108013fd3SMarius Strobl #ifdef __sparc64__ 11208013fd3SMarius Strobl #include <dev/ofw/ofw_bus.h> 11308013fd3SMarius Strobl #include <dev/ofw/openfirm.h> 11408013fd3SMarius Strobl #include <machine/ofw_machdep.h> 11508013fd3SMarius Strobl #include <machine/ver.h> 11608013fd3SMarius Strobl #endif 11708013fd3SMarius Strobl 1184fbd232cSWarner Losh #include <dev/pci/pcireg.h> 1194fbd232cSWarner Losh #include <dev/pci/pcivar.h> 12095d67482SBill Paul 12195d67482SBill Paul #include <dev/bge/if_bgereg.h> 12295d67482SBill Paul 1235ddc5794SJohn Polstra #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 124d375e524SGleb Smirnoff #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 12595d67482SBill Paul 126f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, pci, 1, 1, 1); 127f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, ether, 1, 1, 1); 12895d67482SBill Paul MODULE_DEPEND(bge, miibus, 1, 1, 1); 12995d67482SBill Paul 1307b279558SWarner Losh /* "device miibus" required. See GENERIC if you get errors here. */ 13195d67482SBill Paul #include "miibus_if.h" 13295d67482SBill Paul 13395d67482SBill Paul /* 13495d67482SBill Paul * Various supported device vendors/types and their names. Note: the 13595d67482SBill Paul * spec seems to indicate that the hardware still has Alteon's vendor 13695d67482SBill Paul * ID burned into it, though it will always be overriden by the vendor 13795d67482SBill Paul * ID in the EEPROM. Just to be safe, we cover all possibilities. 13895d67482SBill Paul */ 139852c67f9SMarius Strobl static const struct bge_type { 1404c0da0ffSGleb Smirnoff uint16_t bge_vid; 1414c0da0ffSGleb Smirnoff uint16_t bge_did; 1424c0da0ffSGleb Smirnoff } bge_devs[] = { 1434c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 1444c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 14595d67482SBill Paul 1464c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 1474c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 1484c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 1494c0da0ffSGleb Smirnoff 1504c0da0ffSGleb Smirnoff { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 1514c0da0ffSGleb Smirnoff 1524c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 1534c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 1544c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 1554c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 1564c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 1574c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 1584c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 1594c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 1604c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 1614c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 1624c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 1634c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 1644c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 1654c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 1664c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 1674c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 1684c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 1694c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 1704c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 1714c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 1724c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 1734c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174effef978SRemko Lodder { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 1764c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 1774c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 1784c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 1794c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 1804c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 1814c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 1824c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 1834c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 1844c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 1854c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 1869e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 1879e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 1889e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 1899e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190f7d1b2ebSXin LI { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 191a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 192a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 193a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 194a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 195a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 1964c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 1974c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 1984c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 1994c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 200a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 201a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 202a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 2039e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 2049e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 205a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 2069e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 2074c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 2084c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 2094c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 2104c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 2114c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 21238cc658fSJohn Baldwin { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 21338cc658fSJohn Baldwin { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 214a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 215a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 216a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 217a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 2184c0da0ffSGleb Smirnoff 2194c0da0ffSGleb Smirnoff { SK_VENDORID, SK_DEVICEID_ALTIMA }, 2204c0da0ffSGleb Smirnoff 2214c0da0ffSGleb Smirnoff { TC_VENDORID, TC_DEVICEID_3C996 }, 2224c0da0ffSGleb Smirnoff 223a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 224a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 225a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 226a5779553SStanislav Sedov 2274c0da0ffSGleb Smirnoff { 0, 0 } 22895d67482SBill Paul }; 22995d67482SBill Paul 2304c0da0ffSGleb Smirnoff static const struct bge_vendor { 2314c0da0ffSGleb Smirnoff uint16_t v_id; 2324c0da0ffSGleb Smirnoff const char *v_name; 2334c0da0ffSGleb Smirnoff } bge_vendors[] = { 2344c0da0ffSGleb Smirnoff { ALTEON_VENDORID, "Alteon" }, 2354c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, "Altima" }, 2364c0da0ffSGleb Smirnoff { APPLE_VENDORID, "Apple" }, 2374c0da0ffSGleb Smirnoff { BCOM_VENDORID, "Broadcom" }, 2384c0da0ffSGleb Smirnoff { SK_VENDORID, "SysKonnect" }, 2394c0da0ffSGleb Smirnoff { TC_VENDORID, "3Com" }, 240a5779553SStanislav Sedov { FJTSU_VENDORID, "Fujitsu" }, 2414c0da0ffSGleb Smirnoff 2424c0da0ffSGleb Smirnoff { 0, NULL } 2434c0da0ffSGleb Smirnoff }; 2444c0da0ffSGleb Smirnoff 2454c0da0ffSGleb Smirnoff static const struct bge_revision { 2464c0da0ffSGleb Smirnoff uint32_t br_chipid; 2474c0da0ffSGleb Smirnoff const char *br_name; 2484c0da0ffSGleb Smirnoff } bge_revisions[] = { 2494c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 2504c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 2514c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 2524c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 2534c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 2544c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 2554c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 2564c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 2574c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 2584c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 2594c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 2604c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 2614c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 2624c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 2634c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 2644c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 2659e86676bSGleb Smirnoff { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 2664c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 2674c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 2684c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 2694c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 2704c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 2714c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 2724c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 2734c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 2744c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 2754c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 2764c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 2774c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 2784c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 2794c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 2804c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 2814c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 28242787b76SGleb Smirnoff { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 2834c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 2844c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 2854c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 2864c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 2874c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 2884c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 2894c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 2904c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 2910c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 2920c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 2930c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 2940c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 295bcc20328SJohn Baldwin { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 296a5779553SStanislav Sedov { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 297a5779553SStanislav Sedov { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 298a5779553SStanislav Sedov { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 299a5779553SStanislav Sedov { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 30081179070SJung-uk Kim /* 5754 and 5787 share the same ASIC ID */ 3016f8718a3SScott Long { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 3026f8718a3SScott Long { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 3036f8718a3SScott Long { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 30438cc658fSJohn Baldwin { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 30538cc658fSJohn Baldwin { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 306a5779553SStanislav Sedov { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 307a5779553SStanislav Sedov { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 3084c0da0ffSGleb Smirnoff 3094c0da0ffSGleb Smirnoff { 0, NULL } 3104c0da0ffSGleb Smirnoff }; 3114c0da0ffSGleb Smirnoff 3124c0da0ffSGleb Smirnoff /* 3134c0da0ffSGleb Smirnoff * Some defaults for major revisions, so that newer steppings 3144c0da0ffSGleb Smirnoff * that we don't know about have a shot at working. 3154c0da0ffSGleb Smirnoff */ 3164c0da0ffSGleb Smirnoff static const struct bge_revision bge_majorrevs[] = { 3179e86676bSGleb Smirnoff { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 3189e86676bSGleb Smirnoff { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 3199e86676bSGleb Smirnoff { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 3209e86676bSGleb Smirnoff { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 3219e86676bSGleb Smirnoff { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 3229e86676bSGleb Smirnoff { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 3239e86676bSGleb Smirnoff { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 3249e86676bSGleb Smirnoff { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 3259e86676bSGleb Smirnoff { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 3269e86676bSGleb Smirnoff { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 3279e86676bSGleb Smirnoff { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 328a5779553SStanislav Sedov { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 329a5779553SStanislav Sedov { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 330a5779553SStanislav Sedov { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 33181179070SJung-uk Kim /* 5754 and 5787 share the same ASIC ID */ 3326f8718a3SScott Long { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 33338cc658fSJohn Baldwin { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 334a5779553SStanislav Sedov { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 3354c0da0ffSGleb Smirnoff 3364c0da0ffSGleb Smirnoff { 0, NULL } 3374c0da0ffSGleb Smirnoff }; 3384c0da0ffSGleb Smirnoff 3390c8aa4eaSJung-uk Kim #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 3400c8aa4eaSJung-uk Kim #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 3410c8aa4eaSJung-uk Kim #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 3420c8aa4eaSJung-uk Kim #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 3430c8aa4eaSJung-uk Kim #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 344a5779553SStanislav Sedov #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 3454c0da0ffSGleb Smirnoff 3464c0da0ffSGleb Smirnoff const struct bge_revision * bge_lookup_rev(uint32_t); 3474c0da0ffSGleb Smirnoff const struct bge_vendor * bge_lookup_vendor(uint16_t); 34838cc658fSJohn Baldwin 34938cc658fSJohn Baldwin typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 35038cc658fSJohn Baldwin 351e51a25f8SAlfred Perlstein static int bge_probe(device_t); 352e51a25f8SAlfred Perlstein static int bge_attach(device_t); 353e51a25f8SAlfred Perlstein static int bge_detach(device_t); 35414afefa3SPawel Jakub Dawidek static int bge_suspend(device_t); 35514afefa3SPawel Jakub Dawidek static int bge_resume(device_t); 3563f74909aSGleb Smirnoff static void bge_release_resources(struct bge_softc *); 357f41ac2beSBill Paul static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 358f41ac2beSBill Paul static int bge_dma_alloc(device_t); 359f41ac2beSBill Paul static void bge_dma_free(struct bge_softc *); 360f41ac2beSBill Paul 3615fea260fSMarius Strobl static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 36238cc658fSJohn Baldwin static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 36338cc658fSJohn Baldwin static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 36438cc658fSJohn Baldwin static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 36538cc658fSJohn Baldwin static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 36638cc658fSJohn Baldwin 367b9c05fa5SPyun YongHyeon static void bge_txeof(struct bge_softc *, uint16_t); 368dfe0df9aSPyun YongHyeon static int bge_rxeof(struct bge_softc *, uint16_t, int); 36995d67482SBill Paul 3708cb1383cSDoug Ambrisko static void bge_asf_driver_up (struct bge_softc *); 371e51a25f8SAlfred Perlstein static void bge_tick(void *); 372e51a25f8SAlfred Perlstein static void bge_stats_update(struct bge_softc *); 3733f74909aSGleb Smirnoff static void bge_stats_update_regs(struct bge_softc *); 3742e1d4df4SPyun YongHyeon static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 3752e1d4df4SPyun YongHyeon uint16_t *); 376676ad2c9SGleb Smirnoff static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 37795d67482SBill Paul 378e51a25f8SAlfred Perlstein static void bge_intr(void *); 379dfe0df9aSPyun YongHyeon static int bge_msi_intr(void *); 380dfe0df9aSPyun YongHyeon static void bge_intr_task(void *, int); 3810f9bd73bSSam Leffler static void bge_start_locked(struct ifnet *); 382e51a25f8SAlfred Perlstein static void bge_start(struct ifnet *); 383e51a25f8SAlfred Perlstein static int bge_ioctl(struct ifnet *, u_long, caddr_t); 3840f9bd73bSSam Leffler static void bge_init_locked(struct bge_softc *); 385e51a25f8SAlfred Perlstein static void bge_init(void *); 386e51a25f8SAlfred Perlstein static void bge_stop(struct bge_softc *); 387b74e67fbSGleb Smirnoff static void bge_watchdog(struct bge_softc *); 388b6c974e8SWarner Losh static int bge_shutdown(device_t); 38967d5e043SOleg Bulyzhin static int bge_ifmedia_upd_locked(struct ifnet *); 390e51a25f8SAlfred Perlstein static int bge_ifmedia_upd(struct ifnet *); 391e51a25f8SAlfred Perlstein static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 39295d67482SBill Paul 39338cc658fSJohn Baldwin static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 39438cc658fSJohn Baldwin static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 39538cc658fSJohn Baldwin 3963f74909aSGleb Smirnoff static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 397e51a25f8SAlfred Perlstein static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 39895d67482SBill Paul 3993e9b1bcaSJung-uk Kim static void bge_setpromisc(struct bge_softc *); 400e51a25f8SAlfred Perlstein static void bge_setmulti(struct bge_softc *); 401cb2eacc7SYaroslav Tykhiy static void bge_setvlan(struct bge_softc *); 40295d67482SBill Paul 403e0b7b101SPyun YongHyeon static __inline void bge_rxreuse_std(struct bge_softc *, int); 404e0b7b101SPyun YongHyeon static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 405943787f3SPyun YongHyeon static int bge_newbuf_std(struct bge_softc *, int); 406943787f3SPyun YongHyeon static int bge_newbuf_jumbo(struct bge_softc *, int); 407e51a25f8SAlfred Perlstein static int bge_init_rx_ring_std(struct bge_softc *); 408e51a25f8SAlfred Perlstein static void bge_free_rx_ring_std(struct bge_softc *); 409e51a25f8SAlfred Perlstein static int bge_init_rx_ring_jumbo(struct bge_softc *); 410e51a25f8SAlfred Perlstein static void bge_free_rx_ring_jumbo(struct bge_softc *); 411e51a25f8SAlfred Perlstein static void bge_free_tx_ring(struct bge_softc *); 412e51a25f8SAlfred Perlstein static int bge_init_tx_ring(struct bge_softc *); 41395d67482SBill Paul 414e51a25f8SAlfred Perlstein static int bge_chipinit(struct bge_softc *); 415e51a25f8SAlfred Perlstein static int bge_blockinit(struct bge_softc *); 41695d67482SBill Paul 4175fea260fSMarius Strobl static int bge_has_eaddr(struct bge_softc *); 4183f74909aSGleb Smirnoff static uint32_t bge_readmem_ind(struct bge_softc *, int); 419e51a25f8SAlfred Perlstein static void bge_writemem_ind(struct bge_softc *, int, int); 42038cc658fSJohn Baldwin static void bge_writembx(struct bge_softc *, int, int); 42195d67482SBill Paul #ifdef notdef 4223f74909aSGleb Smirnoff static uint32_t bge_readreg_ind(struct bge_softc *, int); 42395d67482SBill Paul #endif 4249ba784dbSScott Long static void bge_writemem_direct(struct bge_softc *, int, int); 425e51a25f8SAlfred Perlstein static void bge_writereg_ind(struct bge_softc *, int, int); 42695d67482SBill Paul 427e51a25f8SAlfred Perlstein static int bge_miibus_readreg(device_t, int, int); 428e51a25f8SAlfred Perlstein static int bge_miibus_writereg(device_t, int, int, int); 429e51a25f8SAlfred Perlstein static void bge_miibus_statchg(device_t); 43075719184SGleb Smirnoff #ifdef DEVICE_POLLING 4311abcdbd1SAttilio Rao static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 43275719184SGleb Smirnoff #endif 43395d67482SBill Paul 4348cb1383cSDoug Ambrisko #define BGE_RESET_START 1 4358cb1383cSDoug Ambrisko #define BGE_RESET_STOP 2 4368cb1383cSDoug Ambrisko static void bge_sig_post_reset(struct bge_softc *, int); 4378cb1383cSDoug Ambrisko static void bge_sig_legacy(struct bge_softc *, int); 4388cb1383cSDoug Ambrisko static void bge_sig_pre_reset(struct bge_softc *, int); 439797ab05eSPyun YongHyeon static void bge_stop_fw(struct bge_softc *); 4408cb1383cSDoug Ambrisko static int bge_reset(struct bge_softc *); 441dab5cd05SOleg Bulyzhin static void bge_link_upd(struct bge_softc *); 44295d67482SBill Paul 4436f8718a3SScott Long /* 4446f8718a3SScott Long * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 4456f8718a3SScott Long * leak information to untrusted users. It is also known to cause alignment 4466f8718a3SScott Long * traps on certain architectures. 4476f8718a3SScott Long */ 4486f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 4496f8718a3SScott Long static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 4506f8718a3SScott Long static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 4516f8718a3SScott Long static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 4526f8718a3SScott Long #endif 4536f8718a3SScott Long static void bge_add_sysctls(struct bge_softc *); 454763757b2SScott Long static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 4556f8718a3SScott Long 45695d67482SBill Paul static device_method_t bge_methods[] = { 45795d67482SBill Paul /* Device interface */ 45895d67482SBill Paul DEVMETHOD(device_probe, bge_probe), 45995d67482SBill Paul DEVMETHOD(device_attach, bge_attach), 46095d67482SBill Paul DEVMETHOD(device_detach, bge_detach), 46195d67482SBill Paul DEVMETHOD(device_shutdown, bge_shutdown), 46214afefa3SPawel Jakub Dawidek DEVMETHOD(device_suspend, bge_suspend), 46314afefa3SPawel Jakub Dawidek DEVMETHOD(device_resume, bge_resume), 46495d67482SBill Paul 46595d67482SBill Paul /* bus interface */ 46695d67482SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 46795d67482SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 46895d67482SBill Paul 46995d67482SBill Paul /* MII interface */ 47095d67482SBill Paul DEVMETHOD(miibus_readreg, bge_miibus_readreg), 47195d67482SBill Paul DEVMETHOD(miibus_writereg, bge_miibus_writereg), 47295d67482SBill Paul DEVMETHOD(miibus_statchg, bge_miibus_statchg), 47395d67482SBill Paul 47495d67482SBill Paul { 0, 0 } 47595d67482SBill Paul }; 47695d67482SBill Paul 47795d67482SBill Paul static driver_t bge_driver = { 47895d67482SBill Paul "bge", 47995d67482SBill Paul bge_methods, 48095d67482SBill Paul sizeof(struct bge_softc) 48195d67482SBill Paul }; 48295d67482SBill Paul 48395d67482SBill Paul static devclass_t bge_devclass; 48495d67482SBill Paul 485f246e4a1SMatthew N. Dodd DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 48695d67482SBill Paul DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 48795d67482SBill Paul 488f1a7e6d5SScott Long static int bge_allow_asf = 1; 489f1a7e6d5SScott Long 490f1a7e6d5SScott Long TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 491f1a7e6d5SScott Long 492f1a7e6d5SScott Long SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 493f1a7e6d5SScott Long SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 494f1a7e6d5SScott Long "Allow ASF mode if available"); 495c4529f41SMichael Reifenberger 49608013fd3SMarius Strobl #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 49708013fd3SMarius Strobl #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 49808013fd3SMarius Strobl #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 49908013fd3SMarius Strobl #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 50008013fd3SMarius Strobl #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 50108013fd3SMarius Strobl 50208013fd3SMarius Strobl static int 5035fea260fSMarius Strobl bge_has_eaddr(struct bge_softc *sc) 50408013fd3SMarius Strobl { 50508013fd3SMarius Strobl #ifdef __sparc64__ 50608013fd3SMarius Strobl char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 50708013fd3SMarius Strobl device_t dev; 50808013fd3SMarius Strobl uint32_t subvendor; 50908013fd3SMarius Strobl 51008013fd3SMarius Strobl dev = sc->bge_dev; 51108013fd3SMarius Strobl 51208013fd3SMarius Strobl /* 51308013fd3SMarius Strobl * The on-board BGEs found in sun4u machines aren't fitted with 51408013fd3SMarius Strobl * an EEPROM which means that we have to obtain the MAC address 51508013fd3SMarius Strobl * via OFW and that some tests will always fail. We distinguish 51608013fd3SMarius Strobl * such BGEs by the subvendor ID, which also has to be obtained 51708013fd3SMarius Strobl * from OFW instead of the PCI configuration space as the latter 51808013fd3SMarius Strobl * indicates Broadcom as the subvendor of the netboot interface. 51908013fd3SMarius Strobl * For early Blade 1500 and 2500 we even have to check the OFW 52008013fd3SMarius Strobl * device path as the subvendor ID always defaults to Broadcom 52108013fd3SMarius Strobl * there. 52208013fd3SMarius Strobl */ 52308013fd3SMarius Strobl if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 52408013fd3SMarius Strobl &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 5252d857b9bSMarius Strobl (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 52608013fd3SMarius Strobl return (0); 52708013fd3SMarius Strobl memset(buf, 0, sizeof(buf)); 52808013fd3SMarius Strobl if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 52908013fd3SMarius Strobl if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 53008013fd3SMarius Strobl strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 53108013fd3SMarius Strobl return (0); 53208013fd3SMarius Strobl if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 53308013fd3SMarius Strobl strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 53408013fd3SMarius Strobl return (0); 53508013fd3SMarius Strobl } 53608013fd3SMarius Strobl #endif 53708013fd3SMarius Strobl return (1); 53808013fd3SMarius Strobl } 53908013fd3SMarius Strobl 5403f74909aSGleb Smirnoff static uint32_t 5413f74909aSGleb Smirnoff bge_readmem_ind(struct bge_softc *sc, int off) 54295d67482SBill Paul { 54395d67482SBill Paul device_t dev; 5446f8718a3SScott Long uint32_t val; 54595d67482SBill Paul 54695d67482SBill Paul dev = sc->bge_dev; 54795d67482SBill Paul 54895d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 5496f8718a3SScott Long val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 5506f8718a3SScott Long pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 5516f8718a3SScott Long return (val); 55295d67482SBill Paul } 55395d67482SBill Paul 55495d67482SBill Paul static void 5553f74909aSGleb Smirnoff bge_writemem_ind(struct bge_softc *sc, int off, int val) 55695d67482SBill Paul { 55795d67482SBill Paul device_t dev; 55895d67482SBill Paul 55995d67482SBill Paul dev = sc->bge_dev; 56095d67482SBill Paul 56195d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 56295d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 5636f8718a3SScott Long pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 56495d67482SBill Paul } 56595d67482SBill Paul 56695d67482SBill Paul #ifdef notdef 5673f74909aSGleb Smirnoff static uint32_t 5683f74909aSGleb Smirnoff bge_readreg_ind(struct bge_softc *sc, int off) 56995d67482SBill Paul { 57095d67482SBill Paul device_t dev; 57195d67482SBill Paul 57295d67482SBill Paul dev = sc->bge_dev; 57395d67482SBill Paul 57495d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 57595d67482SBill Paul return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 57695d67482SBill Paul } 57795d67482SBill Paul #endif 57895d67482SBill Paul 57995d67482SBill Paul static void 5803f74909aSGleb Smirnoff bge_writereg_ind(struct bge_softc *sc, int off, int val) 58195d67482SBill Paul { 58295d67482SBill Paul device_t dev; 58395d67482SBill Paul 58495d67482SBill Paul dev = sc->bge_dev; 58595d67482SBill Paul 58695d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 58795d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 58895d67482SBill Paul } 58995d67482SBill Paul 5906f8718a3SScott Long static void 5916f8718a3SScott Long bge_writemem_direct(struct bge_softc *sc, int off, int val) 5926f8718a3SScott Long { 5936f8718a3SScott Long CSR_WRITE_4(sc, off, val); 5946f8718a3SScott Long } 5956f8718a3SScott Long 59638cc658fSJohn Baldwin static void 59738cc658fSJohn Baldwin bge_writembx(struct bge_softc *sc, int off, int val) 59838cc658fSJohn Baldwin { 59938cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 60038cc658fSJohn Baldwin off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 60138cc658fSJohn Baldwin 60238cc658fSJohn Baldwin CSR_WRITE_4(sc, off, val); 60338cc658fSJohn Baldwin } 60438cc658fSJohn Baldwin 605f41ac2beSBill Paul /* 606f41ac2beSBill Paul * Map a single buffer address. 607f41ac2beSBill Paul */ 608f41ac2beSBill Paul 609f41ac2beSBill Paul static void 6103f74909aSGleb Smirnoff bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 611f41ac2beSBill Paul { 612f41ac2beSBill Paul struct bge_dmamap_arg *ctx; 613f41ac2beSBill Paul 614f41ac2beSBill Paul if (error) 615f41ac2beSBill Paul return; 616f41ac2beSBill Paul 617f41ac2beSBill Paul ctx = arg; 618f41ac2beSBill Paul 619f41ac2beSBill Paul if (nseg > ctx->bge_maxsegs) { 620f41ac2beSBill Paul ctx->bge_maxsegs = 0; 621f41ac2beSBill Paul return; 622f41ac2beSBill Paul } 623f41ac2beSBill Paul 624f41ac2beSBill Paul ctx->bge_busaddr = segs->ds_addr; 625f41ac2beSBill Paul } 626f41ac2beSBill Paul 62738cc658fSJohn Baldwin static uint8_t 62838cc658fSJohn Baldwin bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 62938cc658fSJohn Baldwin { 63038cc658fSJohn Baldwin uint32_t access, byte = 0; 63138cc658fSJohn Baldwin int i; 63238cc658fSJohn Baldwin 63338cc658fSJohn Baldwin /* Lock. */ 63438cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 63538cc658fSJohn Baldwin for (i = 0; i < 8000; i++) { 63638cc658fSJohn Baldwin if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 63738cc658fSJohn Baldwin break; 63838cc658fSJohn Baldwin DELAY(20); 63938cc658fSJohn Baldwin } 64038cc658fSJohn Baldwin if (i == 8000) 64138cc658fSJohn Baldwin return (1); 64238cc658fSJohn Baldwin 64338cc658fSJohn Baldwin /* Enable access. */ 64438cc658fSJohn Baldwin access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 64538cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 64638cc658fSJohn Baldwin 64738cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 64838cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 64938cc658fSJohn Baldwin for (i = 0; i < BGE_TIMEOUT * 10; i++) { 65038cc658fSJohn Baldwin DELAY(10); 65138cc658fSJohn Baldwin if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 65238cc658fSJohn Baldwin DELAY(10); 65338cc658fSJohn Baldwin break; 65438cc658fSJohn Baldwin } 65538cc658fSJohn Baldwin } 65638cc658fSJohn Baldwin 65738cc658fSJohn Baldwin if (i == BGE_TIMEOUT * 10) { 65838cc658fSJohn Baldwin if_printf(sc->bge_ifp, "nvram read timed out\n"); 65938cc658fSJohn Baldwin return (1); 66038cc658fSJohn Baldwin } 66138cc658fSJohn Baldwin 66238cc658fSJohn Baldwin /* Get result. */ 66338cc658fSJohn Baldwin byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 66438cc658fSJohn Baldwin 66538cc658fSJohn Baldwin *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 66638cc658fSJohn Baldwin 66738cc658fSJohn Baldwin /* Disable access. */ 66838cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 66938cc658fSJohn Baldwin 67038cc658fSJohn Baldwin /* Unlock. */ 67138cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 67238cc658fSJohn Baldwin CSR_READ_4(sc, BGE_NVRAM_SWARB); 67338cc658fSJohn Baldwin 67438cc658fSJohn Baldwin return (0); 67538cc658fSJohn Baldwin } 67638cc658fSJohn Baldwin 67738cc658fSJohn Baldwin /* 67838cc658fSJohn Baldwin * Read a sequence of bytes from NVRAM. 67938cc658fSJohn Baldwin */ 68038cc658fSJohn Baldwin static int 68138cc658fSJohn Baldwin bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 68238cc658fSJohn Baldwin { 68338cc658fSJohn Baldwin int err = 0, i; 68438cc658fSJohn Baldwin uint8_t byte = 0; 68538cc658fSJohn Baldwin 68638cc658fSJohn Baldwin if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 68738cc658fSJohn Baldwin return (1); 68838cc658fSJohn Baldwin 68938cc658fSJohn Baldwin for (i = 0; i < cnt; i++) { 69038cc658fSJohn Baldwin err = bge_nvram_getbyte(sc, off + i, &byte); 69138cc658fSJohn Baldwin if (err) 69238cc658fSJohn Baldwin break; 69338cc658fSJohn Baldwin *(dest + i) = byte; 69438cc658fSJohn Baldwin } 69538cc658fSJohn Baldwin 69638cc658fSJohn Baldwin return (err ? 1 : 0); 69738cc658fSJohn Baldwin } 69838cc658fSJohn Baldwin 69995d67482SBill Paul /* 70095d67482SBill Paul * Read a byte of data stored in the EEPROM at address 'addr.' The 70195d67482SBill Paul * BCM570x supports both the traditional bitbang interface and an 70295d67482SBill Paul * auto access interface for reading the EEPROM. We use the auto 70395d67482SBill Paul * access method. 70495d67482SBill Paul */ 7053f74909aSGleb Smirnoff static uint8_t 7063f74909aSGleb Smirnoff bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 70795d67482SBill Paul { 70895d67482SBill Paul int i; 7093f74909aSGleb Smirnoff uint32_t byte = 0; 71095d67482SBill Paul 71195d67482SBill Paul /* 71295d67482SBill Paul * Enable use of auto EEPROM access so we can avoid 71395d67482SBill Paul * having to use the bitbang method. 71495d67482SBill Paul */ 71595d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 71695d67482SBill Paul 71795d67482SBill Paul /* Reset the EEPROM, load the clock period. */ 71895d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, 71995d67482SBill Paul BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 72095d67482SBill Paul DELAY(20); 72195d67482SBill Paul 72295d67482SBill Paul /* Issue the read EEPROM command. */ 72395d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 72495d67482SBill Paul 72595d67482SBill Paul /* Wait for completion */ 72695d67482SBill Paul for(i = 0; i < BGE_TIMEOUT * 10; i++) { 72795d67482SBill Paul DELAY(10); 72895d67482SBill Paul if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 72995d67482SBill Paul break; 73095d67482SBill Paul } 73195d67482SBill Paul 732d5d23857SJung-uk Kim if (i == BGE_TIMEOUT * 10) { 733fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "EEPROM read timed out\n"); 734f6789fbaSPyun YongHyeon return (1); 73595d67482SBill Paul } 73695d67482SBill Paul 73795d67482SBill Paul /* Get result. */ 73895d67482SBill Paul byte = CSR_READ_4(sc, BGE_EE_DATA); 73995d67482SBill Paul 7400c8aa4eaSJung-uk Kim *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 74195d67482SBill Paul 74295d67482SBill Paul return (0); 74395d67482SBill Paul } 74495d67482SBill Paul 74595d67482SBill Paul /* 74695d67482SBill Paul * Read a sequence of bytes from the EEPROM. 74795d67482SBill Paul */ 74895d67482SBill Paul static int 7493f74909aSGleb Smirnoff bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 75095d67482SBill Paul { 7513f74909aSGleb Smirnoff int i, error = 0; 7523f74909aSGleb Smirnoff uint8_t byte = 0; 75395d67482SBill Paul 75495d67482SBill Paul for (i = 0; i < cnt; i++) { 7553f74909aSGleb Smirnoff error = bge_eeprom_getbyte(sc, off + i, &byte); 7563f74909aSGleb Smirnoff if (error) 75795d67482SBill Paul break; 75895d67482SBill Paul *(dest + i) = byte; 75995d67482SBill Paul } 76095d67482SBill Paul 7613f74909aSGleb Smirnoff return (error ? 1 : 0); 76295d67482SBill Paul } 76395d67482SBill Paul 76495d67482SBill Paul static int 7653f74909aSGleb Smirnoff bge_miibus_readreg(device_t dev, int phy, int reg) 76695d67482SBill Paul { 76795d67482SBill Paul struct bge_softc *sc; 7683f74909aSGleb Smirnoff uint32_t val, autopoll; 76995d67482SBill Paul int i; 77095d67482SBill Paul 77195d67482SBill Paul sc = device_get_softc(dev); 77295d67482SBill Paul 7730434d1b8SBill Paul /* 7740434d1b8SBill Paul * Broadcom's own driver always assumes the internal 7750434d1b8SBill Paul * PHY is at GMII address 1. On some chips, the PHY responds 7760434d1b8SBill Paul * to accesses at all addresses, which could cause us to 7770434d1b8SBill Paul * bogusly attach the PHY 32 times at probe type. Always 7780434d1b8SBill Paul * restricting the lookup to address 1 is simpler than 7790434d1b8SBill Paul * trying to figure out which chips revisions should be 7800434d1b8SBill Paul * special-cased. 7810434d1b8SBill Paul */ 782b1265c1aSJohn Polstra if (phy != 1) 78398b28ee5SBill Paul return (0); 78498b28ee5SBill Paul 78537ceeb4dSPaul Saab /* Reading with autopolling on may trigger PCI errors */ 78637ceeb4dSPaul Saab autopoll = CSR_READ_4(sc, BGE_MI_MODE); 78737ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 78837ceeb4dSPaul Saab BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 78937ceeb4dSPaul Saab DELAY(40); 79037ceeb4dSPaul Saab } 79137ceeb4dSPaul Saab 79295d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 79395d67482SBill Paul BGE_MIPHY(phy) | BGE_MIREG(reg)); 79495d67482SBill Paul 79595d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 796d5d23857SJung-uk Kim DELAY(10); 79795d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 79895d67482SBill Paul if (!(val & BGE_MICOMM_BUSY)) 79995d67482SBill Paul break; 80095d67482SBill Paul } 80195d67482SBill Paul 80295d67482SBill Paul if (i == BGE_TIMEOUT) { 8035fea260fSMarius Strobl device_printf(sc->bge_dev, 8045fea260fSMarius Strobl "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 8055fea260fSMarius Strobl phy, reg, val); 80637ceeb4dSPaul Saab val = 0; 80737ceeb4dSPaul Saab goto done; 80895d67482SBill Paul } 80995d67482SBill Paul 81038cc658fSJohn Baldwin DELAY(5); 81195d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 81295d67482SBill Paul 81337ceeb4dSPaul Saab done: 81437ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 81537ceeb4dSPaul Saab BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 81637ceeb4dSPaul Saab DELAY(40); 81737ceeb4dSPaul Saab } 81837ceeb4dSPaul Saab 81995d67482SBill Paul if (val & BGE_MICOMM_READFAIL) 82095d67482SBill Paul return (0); 82195d67482SBill Paul 8220c8aa4eaSJung-uk Kim return (val & 0xFFFF); 82395d67482SBill Paul } 82495d67482SBill Paul 82595d67482SBill Paul static int 8263f74909aSGleb Smirnoff bge_miibus_writereg(device_t dev, int phy, int reg, int val) 82795d67482SBill Paul { 82895d67482SBill Paul struct bge_softc *sc; 8293f74909aSGleb Smirnoff uint32_t autopoll; 83095d67482SBill Paul int i; 83195d67482SBill Paul 83295d67482SBill Paul sc = device_get_softc(dev); 83395d67482SBill Paul 83438cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 83538cc658fSJohn Baldwin (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 83638cc658fSJohn Baldwin return (0); 83738cc658fSJohn Baldwin 83837ceeb4dSPaul Saab /* Reading with autopolling on may trigger PCI errors */ 83937ceeb4dSPaul Saab autopoll = CSR_READ_4(sc, BGE_MI_MODE); 84037ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 84137ceeb4dSPaul Saab BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 84237ceeb4dSPaul Saab DELAY(40); 84337ceeb4dSPaul Saab } 84437ceeb4dSPaul Saab 84595d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 84695d67482SBill Paul BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 84795d67482SBill Paul 84895d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 849d5d23857SJung-uk Kim DELAY(10); 85038cc658fSJohn Baldwin if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 85138cc658fSJohn Baldwin DELAY(5); 85238cc658fSJohn Baldwin CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 85395d67482SBill Paul break; 854d5d23857SJung-uk Kim } 85538cc658fSJohn Baldwin } 856d5d23857SJung-uk Kim 857d5d23857SJung-uk Kim if (i == BGE_TIMEOUT) { 85838cc658fSJohn Baldwin device_printf(sc->bge_dev, 85938cc658fSJohn Baldwin "PHY write timed out (phy %d, reg %d, val %d)\n", 86038cc658fSJohn Baldwin phy, reg, val); 861d5d23857SJung-uk Kim return (0); 86295d67482SBill Paul } 86395d67482SBill Paul 86437ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 86537ceeb4dSPaul Saab BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 86637ceeb4dSPaul Saab DELAY(40); 86737ceeb4dSPaul Saab } 86837ceeb4dSPaul Saab 86995d67482SBill Paul return (0); 87095d67482SBill Paul } 87195d67482SBill Paul 87295d67482SBill Paul static void 8733f74909aSGleb Smirnoff bge_miibus_statchg(device_t dev) 87495d67482SBill Paul { 87595d67482SBill Paul struct bge_softc *sc; 87695d67482SBill Paul struct mii_data *mii; 87795d67482SBill Paul sc = device_get_softc(dev); 87895d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 87995d67482SBill Paul 88095d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 881ea3b4127SPyun YongHyeon if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 882ea3b4127SPyun YongHyeon IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 88395d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 8843f74909aSGleb Smirnoff else 88595d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 88695d67482SBill Paul 8873f74909aSGleb Smirnoff if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 88895d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 8893f74909aSGleb Smirnoff else 89095d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 89195d67482SBill Paul } 89295d67482SBill Paul 89395d67482SBill Paul /* 89495d67482SBill Paul * Intialize a standard receive ring descriptor. 89595d67482SBill Paul */ 89695d67482SBill Paul static int 897943787f3SPyun YongHyeon bge_newbuf_std(struct bge_softc *sc, int i) 89895d67482SBill Paul { 899943787f3SPyun YongHyeon struct mbuf *m; 90095d67482SBill Paul struct bge_rx_bd *r; 901a23634a1SPyun YongHyeon bus_dma_segment_t segs[1]; 902943787f3SPyun YongHyeon bus_dmamap_t map; 903a23634a1SPyun YongHyeon int error, nsegs; 90495d67482SBill Paul 905943787f3SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 906943787f3SPyun YongHyeon if (m == NULL) 90795d67482SBill Paul return (ENOBUFS); 908943787f3SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 909652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 910943787f3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 911943787f3SPyun YongHyeon 9120ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 913943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 914a23634a1SPyun YongHyeon if (error != 0) { 915943787f3SPyun YongHyeon m_freem(m); 916a23634a1SPyun YongHyeon return (error); 917f41ac2beSBill Paul } 918943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 919943787f3SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 920943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 921943787f3SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 922943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i]); 923943787f3SPyun YongHyeon } 924943787f3SPyun YongHyeon map = sc->bge_cdata.bge_rx_std_dmamap[i]; 925943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 926943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap = map; 927943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_chain[i] = m; 928e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 929943787f3SPyun YongHyeon r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 930a23634a1SPyun YongHyeon r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 931a23634a1SPyun YongHyeon r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 932e907febfSPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_END; 933a23634a1SPyun YongHyeon r->bge_len = segs[0].ds_len; 934e907febfSPyun YongHyeon r->bge_idx = i; 935f41ac2beSBill Paul 9360ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 937943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 93895d67482SBill Paul 93995d67482SBill Paul return (0); 94095d67482SBill Paul } 94195d67482SBill Paul 94295d67482SBill Paul /* 94395d67482SBill Paul * Initialize a jumbo receive ring descriptor. This allocates 94495d67482SBill Paul * a jumbo buffer from the pool managed internally by the driver. 94595d67482SBill Paul */ 94695d67482SBill Paul static int 947943787f3SPyun YongHyeon bge_newbuf_jumbo(struct bge_softc *sc, int i) 94895d67482SBill Paul { 9491be6acb7SGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 950943787f3SPyun YongHyeon bus_dmamap_t map; 9511be6acb7SGleb Smirnoff struct bge_extrx_bd *r; 952943787f3SPyun YongHyeon struct mbuf *m; 953943787f3SPyun YongHyeon int error, nsegs; 95495d67482SBill Paul 955943787f3SPyun YongHyeon MGETHDR(m, M_DONTWAIT, MT_DATA); 956943787f3SPyun YongHyeon if (m == NULL) 95795d67482SBill Paul return (ENOBUFS); 95895d67482SBill Paul 959943787f3SPyun YongHyeon m_cljget(m, M_DONTWAIT, MJUM9BYTES); 960943787f3SPyun YongHyeon if (!(m->m_flags & M_EXT)) { 961943787f3SPyun YongHyeon m_freem(m); 96295d67482SBill Paul return (ENOBUFS); 96395d67482SBill Paul } 964943787f3SPyun YongHyeon m->m_len = m->m_pkthdr.len = MJUM9BYTES; 965652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 966943787f3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 9671be6acb7SGleb Smirnoff 9681be6acb7SGleb Smirnoff error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 969943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 970943787f3SPyun YongHyeon if (error != 0) { 971943787f3SPyun YongHyeon m_freem(m); 9721be6acb7SGleb Smirnoff return (error); 973f7cea149SGleb Smirnoff } 9741be6acb7SGleb Smirnoff 975943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 976943787f3SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 977943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 978943787f3SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 979943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 980943787f3SPyun YongHyeon } 981943787f3SPyun YongHyeon map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 982943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 983943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap; 984943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap = map; 985943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 986e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 987e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 988e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 989e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 990e0b7b101SPyun YongHyeon 9911be6acb7SGleb Smirnoff /* 9921be6acb7SGleb Smirnoff * Fill in the extended RX buffer descriptor. 9931be6acb7SGleb Smirnoff */ 994943787f3SPyun YongHyeon r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 9954e7ba1abSGleb Smirnoff r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 9964e7ba1abSGleb Smirnoff r->bge_idx = i; 9974e7ba1abSGleb Smirnoff r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 9984e7ba1abSGleb Smirnoff switch (nsegs) { 9994e7ba1abSGleb Smirnoff case 4: 10004e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 10014e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 10024e7ba1abSGleb Smirnoff r->bge_len3 = segs[3].ds_len; 1003e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 10044e7ba1abSGleb Smirnoff case 3: 1005e907febfSPyun YongHyeon r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1006e907febfSPyun YongHyeon r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1007e907febfSPyun YongHyeon r->bge_len2 = segs[2].ds_len; 1008e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 10094e7ba1abSGleb Smirnoff case 2: 10104e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 10114e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 10124e7ba1abSGleb Smirnoff r->bge_len1 = segs[1].ds_len; 1013e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 10144e7ba1abSGleb Smirnoff case 1: 10154e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 10164e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 10174e7ba1abSGleb Smirnoff r->bge_len0 = segs[0].ds_len; 1018e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 10194e7ba1abSGleb Smirnoff break; 10204e7ba1abSGleb Smirnoff default: 10214e7ba1abSGleb Smirnoff panic("%s: %d segments\n", __func__, nsegs); 10224e7ba1abSGleb Smirnoff } 1023f41ac2beSBill Paul 1024a41504a9SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1025943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 102695d67482SBill Paul 102795d67482SBill Paul return (0); 102895d67482SBill Paul } 102995d67482SBill Paul 103095d67482SBill Paul static int 10313f74909aSGleb Smirnoff bge_init_rx_ring_std(struct bge_softc *sc) 103295d67482SBill Paul { 10333ee5d7daSPyun YongHyeon int error, i; 103495d67482SBill Paul 1035e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 103603e78bd0SPyun YongHyeon sc->bge_std = 0; 1037e0b7b101SPyun YongHyeon for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1038943787f3SPyun YongHyeon if ((error = bge_newbuf_std(sc, i)) != 0) 10393ee5d7daSPyun YongHyeon return (error); 104003e78bd0SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 104195d67482SBill Paul }; 104295d67482SBill Paul 1043f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1044d77e9fa7SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1045f41ac2beSBill Paul 1046e0b7b101SPyun YongHyeon sc->bge_std = 0; 1047e0b7b101SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 104895d67482SBill Paul 104995d67482SBill Paul return (0); 105095d67482SBill Paul } 105195d67482SBill Paul 105295d67482SBill Paul static void 10533f74909aSGleb Smirnoff bge_free_rx_ring_std(struct bge_softc *sc) 105495d67482SBill Paul { 105595d67482SBill Paul int i; 105695d67482SBill Paul 105795d67482SBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 105895d67482SBill Paul if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 10590ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1060e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], 1061e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 10620ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1063f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 1064e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1065e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_chain[i] = NULL; 106695d67482SBill Paul } 1067f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 106895d67482SBill Paul sizeof(struct bge_rx_bd)); 106995d67482SBill Paul } 107095d67482SBill Paul } 107195d67482SBill Paul 107295d67482SBill Paul static int 10733f74909aSGleb Smirnoff bge_init_rx_ring_jumbo(struct bge_softc *sc) 107495d67482SBill Paul { 107595d67482SBill Paul struct bge_rcb *rcb; 10763ee5d7daSPyun YongHyeon int error, i; 107795d67482SBill Paul 1078e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 107903e78bd0SPyun YongHyeon sc->bge_jumbo = 0; 108095d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1081943787f3SPyun YongHyeon if ((error = bge_newbuf_jumbo(sc, i)) != 0) 10823ee5d7daSPyun YongHyeon return (error); 108303e78bd0SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 108495d67482SBill Paul }; 108595d67482SBill Paul 1086f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1087d77e9fa7SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1088f41ac2beSBill Paul 1089e0b7b101SPyun YongHyeon sc->bge_jumbo = 0; 109095d67482SBill Paul 1091f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 10921be6acb7SGleb Smirnoff rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 10931be6acb7SGleb Smirnoff BGE_RCB_FLAG_USE_EXT_RX_BD); 109467111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 109595d67482SBill Paul 1096e0b7b101SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 109795d67482SBill Paul 109895d67482SBill Paul return (0); 109995d67482SBill Paul } 110095d67482SBill Paul 110195d67482SBill Paul static void 11023f74909aSGleb Smirnoff bge_free_rx_ring_jumbo(struct bge_softc *sc) 110395d67482SBill Paul { 110495d67482SBill Paul int i; 110595d67482SBill Paul 110695d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 110795d67482SBill Paul if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1108e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1109e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1110e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1111f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1112f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1113e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1114e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 111595d67482SBill Paul } 1116f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 11171be6acb7SGleb Smirnoff sizeof(struct bge_extrx_bd)); 111895d67482SBill Paul } 111995d67482SBill Paul } 112095d67482SBill Paul 112195d67482SBill Paul static void 11223f74909aSGleb Smirnoff bge_free_tx_ring(struct bge_softc *sc) 112395d67482SBill Paul { 112495d67482SBill Paul int i; 112595d67482SBill Paul 1126f41ac2beSBill Paul if (sc->bge_ldata.bge_tx_ring == NULL) 112795d67482SBill Paul return; 112895d67482SBill Paul 112995d67482SBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 113095d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 11310ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1132e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[i], 1133e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 11340ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1135f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 1136e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[i]); 1137e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[i] = NULL; 113895d67482SBill Paul } 1139f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 114095d67482SBill Paul sizeof(struct bge_tx_bd)); 114195d67482SBill Paul } 114295d67482SBill Paul } 114395d67482SBill Paul 114495d67482SBill Paul static int 11453f74909aSGleb Smirnoff bge_init_tx_ring(struct bge_softc *sc) 114695d67482SBill Paul { 114795d67482SBill Paul sc->bge_txcnt = 0; 114895d67482SBill Paul sc->bge_tx_saved_considx = 0; 11493927098fSPaul Saab 1150e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1151e6bf277eSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 11525c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1153e6bf277eSPyun YongHyeon 115414bbd30fSGleb Smirnoff /* Initialize transmit producer index for host-memory send ring. */ 115514bbd30fSGleb Smirnoff sc->bge_tx_prodidx = 0; 115638cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 115714bbd30fSGleb Smirnoff 11583927098fSPaul Saab /* 5700 b2 errata */ 1159e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 116038cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 11613927098fSPaul Saab 116214bbd30fSGleb Smirnoff /* NIC-memory send ring not used; initialize to zero. */ 116338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 11643927098fSPaul Saab /* 5700 b2 errata */ 1165e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 116638cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 116795d67482SBill Paul 116895d67482SBill Paul return (0); 116995d67482SBill Paul } 117095d67482SBill Paul 117195d67482SBill Paul static void 11723e9b1bcaSJung-uk Kim bge_setpromisc(struct bge_softc *sc) 11733e9b1bcaSJung-uk Kim { 11743e9b1bcaSJung-uk Kim struct ifnet *ifp; 11753e9b1bcaSJung-uk Kim 11763e9b1bcaSJung-uk Kim BGE_LOCK_ASSERT(sc); 11773e9b1bcaSJung-uk Kim 11783e9b1bcaSJung-uk Kim ifp = sc->bge_ifp; 11793e9b1bcaSJung-uk Kim 118045ee6ab3SJung-uk Kim /* Enable or disable promiscuous mode as needed. */ 11813e9b1bcaSJung-uk Kim if (ifp->if_flags & IFF_PROMISC) 118245ee6ab3SJung-uk Kim BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 11833e9b1bcaSJung-uk Kim else 118445ee6ab3SJung-uk Kim BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 11853e9b1bcaSJung-uk Kim } 11863e9b1bcaSJung-uk Kim 11873e9b1bcaSJung-uk Kim static void 11883f74909aSGleb Smirnoff bge_setmulti(struct bge_softc *sc) 118995d67482SBill Paul { 119095d67482SBill Paul struct ifnet *ifp; 119195d67482SBill Paul struct ifmultiaddr *ifma; 11923f74909aSGleb Smirnoff uint32_t hashes[4] = { 0, 0, 0, 0 }; 119395d67482SBill Paul int h, i; 119495d67482SBill Paul 11950f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 11960f9bd73bSSam Leffler 1197fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 119895d67482SBill Paul 119995d67482SBill Paul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 120095d67482SBill Paul for (i = 0; i < 4; i++) 12010c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 120295d67482SBill Paul return; 120395d67482SBill Paul } 120495d67482SBill Paul 120595d67482SBill Paul /* First, zot all the existing filters. */ 120695d67482SBill Paul for (i = 0; i < 4; i++) 120795d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 120895d67482SBill Paul 120995d67482SBill Paul /* Now program new ones. */ 1210eb956cd0SRobert Watson if_maddr_rlock(ifp); 121195d67482SBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 121295d67482SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 121395d67482SBill Paul continue; 12140e939c0cSChristian Weisgerber h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 12150c8aa4eaSJung-uk Kim ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 12160c8aa4eaSJung-uk Kim hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 121795d67482SBill Paul } 1218eb956cd0SRobert Watson if_maddr_runlock(ifp); 121995d67482SBill Paul 122095d67482SBill Paul for (i = 0; i < 4; i++) 122195d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 122295d67482SBill Paul } 122395d67482SBill Paul 12248cb1383cSDoug Ambrisko static void 1225cb2eacc7SYaroslav Tykhiy bge_setvlan(struct bge_softc *sc) 1226cb2eacc7SYaroslav Tykhiy { 1227cb2eacc7SYaroslav Tykhiy struct ifnet *ifp; 1228cb2eacc7SYaroslav Tykhiy 1229cb2eacc7SYaroslav Tykhiy BGE_LOCK_ASSERT(sc); 1230cb2eacc7SYaroslav Tykhiy 1231cb2eacc7SYaroslav Tykhiy ifp = sc->bge_ifp; 1232cb2eacc7SYaroslav Tykhiy 1233cb2eacc7SYaroslav Tykhiy /* Enable or disable VLAN tag stripping as needed. */ 1234cb2eacc7SYaroslav Tykhiy if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1235cb2eacc7SYaroslav Tykhiy BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1236cb2eacc7SYaroslav Tykhiy else 1237cb2eacc7SYaroslav Tykhiy BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1238cb2eacc7SYaroslav Tykhiy } 1239cb2eacc7SYaroslav Tykhiy 1240cb2eacc7SYaroslav Tykhiy static void 1241797ab05eSPyun YongHyeon bge_sig_pre_reset(struct bge_softc *sc, int type) 12428cb1383cSDoug Ambrisko { 1243797ab05eSPyun YongHyeon 12448cb1383cSDoug Ambrisko /* 12458cb1383cSDoug Ambrisko * Some chips don't like this so only do this if ASF is enabled 12468cb1383cSDoug Ambrisko */ 12478cb1383cSDoug Ambrisko if (sc->bge_asf_mode) 12488cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 12498cb1383cSDoug Ambrisko 12508cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 12518cb1383cSDoug Ambrisko switch (type) { 12528cb1383cSDoug Ambrisko case BGE_RESET_START: 12538cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 12548cb1383cSDoug Ambrisko break; 12558cb1383cSDoug Ambrisko case BGE_RESET_STOP: 12568cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 12578cb1383cSDoug Ambrisko break; 12588cb1383cSDoug Ambrisko } 12598cb1383cSDoug Ambrisko } 12608cb1383cSDoug Ambrisko } 12618cb1383cSDoug Ambrisko 12628cb1383cSDoug Ambrisko static void 1263797ab05eSPyun YongHyeon bge_sig_post_reset(struct bge_softc *sc, int type) 12648cb1383cSDoug Ambrisko { 1265797ab05eSPyun YongHyeon 12668cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 12678cb1383cSDoug Ambrisko switch (type) { 12688cb1383cSDoug Ambrisko case BGE_RESET_START: 12698cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 12708cb1383cSDoug Ambrisko /* START DONE */ 12718cb1383cSDoug Ambrisko break; 12728cb1383cSDoug Ambrisko case BGE_RESET_STOP: 12738cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 12748cb1383cSDoug Ambrisko break; 12758cb1383cSDoug Ambrisko } 12768cb1383cSDoug Ambrisko } 12778cb1383cSDoug Ambrisko } 12788cb1383cSDoug Ambrisko 12798cb1383cSDoug Ambrisko static void 1280797ab05eSPyun YongHyeon bge_sig_legacy(struct bge_softc *sc, int type) 12818cb1383cSDoug Ambrisko { 1282797ab05eSPyun YongHyeon 12838cb1383cSDoug Ambrisko if (sc->bge_asf_mode) { 12848cb1383cSDoug Ambrisko switch (type) { 12858cb1383cSDoug Ambrisko case BGE_RESET_START: 12868cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 12878cb1383cSDoug Ambrisko break; 12888cb1383cSDoug Ambrisko case BGE_RESET_STOP: 12898cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 12908cb1383cSDoug Ambrisko break; 12918cb1383cSDoug Ambrisko } 12928cb1383cSDoug Ambrisko } 12938cb1383cSDoug Ambrisko } 12948cb1383cSDoug Ambrisko 1295797ab05eSPyun YongHyeon static void 1296797ab05eSPyun YongHyeon bge_stop_fw(struct bge_softc *sc) 12978cb1383cSDoug Ambrisko { 12988cb1383cSDoug Ambrisko int i; 12998cb1383cSDoug Ambrisko 13008cb1383cSDoug Ambrisko if (sc->bge_asf_mode) { 13018cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 13028cb1383cSDoug Ambrisko CSR_WRITE_4(sc, BGE_CPU_EVENT, 130339153c5aSJung-uk Kim CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 13048cb1383cSDoug Ambrisko 13058cb1383cSDoug Ambrisko for (i = 0; i < 100; i++ ) { 13068cb1383cSDoug Ambrisko if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 13078cb1383cSDoug Ambrisko break; 13088cb1383cSDoug Ambrisko DELAY(10); 13098cb1383cSDoug Ambrisko } 13108cb1383cSDoug Ambrisko } 13118cb1383cSDoug Ambrisko } 13128cb1383cSDoug Ambrisko 131395d67482SBill Paul /* 1314c9ffd9f0SMarius Strobl * Do endian, PCI and DMA initialization. 131595d67482SBill Paul */ 131695d67482SBill Paul static int 13173f74909aSGleb Smirnoff bge_chipinit(struct bge_softc *sc) 131895d67482SBill Paul { 13193f74909aSGleb Smirnoff uint32_t dma_rw_ctl; 1320fbc374afSPyun YongHyeon uint16_t val; 132195d67482SBill Paul int i; 132295d67482SBill Paul 13238cb1383cSDoug Ambrisko /* Set endianness before we access any non-PCI registers. */ 1324e907febfSPyun YongHyeon pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 132595d67482SBill Paul 132695d67482SBill Paul /* Clear the MAC control register */ 132795d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 132895d67482SBill Paul 132995d67482SBill Paul /* 133095d67482SBill Paul * Clear the MAC statistics block in the NIC's 133195d67482SBill Paul * internal memory. 133295d67482SBill Paul */ 133395d67482SBill Paul for (i = BGE_STATS_BLOCK; 13343f74909aSGleb Smirnoff i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 133595d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 133695d67482SBill Paul 133795d67482SBill Paul for (i = BGE_STATUS_BLOCK; 13383f74909aSGleb Smirnoff i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 133995d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 134095d67482SBill Paul 1341fbc374afSPyun YongHyeon if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1342fbc374afSPyun YongHyeon /* 1343d896b3feSPyun YongHyeon * Fix data corruption caused by non-qword write with WB. 1344fbc374afSPyun YongHyeon * Fix master abort in PCI mode. 1345fbc374afSPyun YongHyeon * Fix PCI latency timer. 1346fbc374afSPyun YongHyeon */ 1347fbc374afSPyun YongHyeon val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1348fbc374afSPyun YongHyeon val |= (1 << 10) | (1 << 12) | (1 << 13); 1349fbc374afSPyun YongHyeon pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1350fbc374afSPyun YongHyeon } 1351fbc374afSPyun YongHyeon 1352186f842bSJung-uk Kim /* 1353186f842bSJung-uk Kim * Set up the PCI DMA control register. 1354186f842bSJung-uk Kim */ 1355186f842bSJung-uk Kim dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1356186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1357652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 1358186f842bSJung-uk Kim /* Read watermark not used, 128 bytes for write. */ 1359186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1360652ae483SGleb Smirnoff } else if (sc->bge_flags & BGE_FLAG_PCIX) { 13614c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 1362186f842bSJung-uk Kim /* 256 bytes for read and write. */ 1363186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1364186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1365186f842bSJung-uk Kim dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1366186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1367186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1368cbb2b2feSPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1369cbb2b2feSPyun YongHyeon /* 1370cbb2b2feSPyun YongHyeon * In the BCM5703, the DMA read watermark should 1371cbb2b2feSPyun YongHyeon * be set to less than or equal to the maximum 1372cbb2b2feSPyun YongHyeon * memory read byte count of the PCI-X command 1373cbb2b2feSPyun YongHyeon * register. 1374cbb2b2feSPyun YongHyeon */ 1375cbb2b2feSPyun YongHyeon dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1376cbb2b2feSPyun YongHyeon BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1377186f842bSJung-uk Kim } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1378186f842bSJung-uk Kim /* 1536 bytes for read, 384 bytes for write. */ 1379186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1380186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1381186f842bSJung-uk Kim } else { 1382186f842bSJung-uk Kim /* 384 bytes for read and write. */ 1383186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1384186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 13850c8aa4eaSJung-uk Kim 0x0F; 1386186f842bSJung-uk Kim } 1387e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1388e0ced696SPaul Saab sc->bge_asicrev == BGE_ASICREV_BCM5704) { 13893f74909aSGleb Smirnoff uint32_t tmp; 13905cba12d3SPaul Saab 1391186f842bSJung-uk Kim /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 13920c8aa4eaSJung-uk Kim tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1393186f842bSJung-uk Kim if (tmp == 6 || tmp == 7) 1394186f842bSJung-uk Kim dma_rw_ctl |= 1395186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 13965cba12d3SPaul Saab 1397186f842bSJung-uk Kim /* Set PCI-X DMA write workaround. */ 1398186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1399186f842bSJung-uk Kim } 1400186f842bSJung-uk Kim } else { 1401186f842bSJung-uk Kim /* Conventional PCI bus: 256 bytes for read and write. */ 1402186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1403186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1404186f842bSJung-uk Kim 1405186f842bSJung-uk Kim if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1406186f842bSJung-uk Kim sc->bge_asicrev != BGE_ASICREV_BCM5750) 1407186f842bSJung-uk Kim dma_rw_ctl |= 0x0F; 1408186f842bSJung-uk Kim } 1409186f842bSJung-uk Kim if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1410186f842bSJung-uk Kim sc->bge_asicrev == BGE_ASICREV_BCM5701) 1411186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1412186f842bSJung-uk Kim BGE_PCIDMARWCTL_ASRT_ALL_BE; 1413e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1414186f842bSJung-uk Kim sc->bge_asicrev == BGE_ASICREV_BCM5704) 14155cba12d3SPaul Saab dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 14165cba12d3SPaul Saab pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 141795d67482SBill Paul 141895d67482SBill Paul /* 141995d67482SBill Paul * Set up general mode register. 142095d67482SBill Paul */ 1421e907febfSPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 142295d67482SBill Paul BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1423ee7ef91cSOleg Bulyzhin BGE_MODECTL_TX_NO_PHDR_CSUM); 142495d67482SBill Paul 142595d67482SBill Paul /* 142690447aadSMarius Strobl * BCM5701 B5 have a bug causing data corruption when using 142790447aadSMarius Strobl * 64-bit DMA reads, which can be terminated early and then 142890447aadSMarius Strobl * completed later as 32-bit accesses, in combination with 142990447aadSMarius Strobl * certain bridges. 143090447aadSMarius Strobl */ 143190447aadSMarius Strobl if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 143290447aadSMarius Strobl sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 143390447aadSMarius Strobl BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 143490447aadSMarius Strobl 143590447aadSMarius Strobl /* 14368cb1383cSDoug Ambrisko * Tell the firmware the driver is running 14378cb1383cSDoug Ambrisko */ 14388cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 14398cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 14408cb1383cSDoug Ambrisko 14418cb1383cSDoug Ambrisko /* 1442ea13bdd5SJohn Polstra * Disable memory write invalidate. Apparently it is not supported 1443c9ffd9f0SMarius Strobl * properly by these devices. Also ensure that INTx isn't disabled, 1444c9ffd9f0SMarius Strobl * as these chips need it even when using MSI. 144595d67482SBill Paul */ 1446c9ffd9f0SMarius Strobl PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1447c9ffd9f0SMarius Strobl PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 144895d67482SBill Paul 144995d67482SBill Paul /* Set the timer prescaler (always 66Mhz) */ 14500c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 145195d67482SBill Paul 145238cc658fSJohn Baldwin /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 145338cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 145438cc658fSJohn Baldwin DELAY(40); /* XXX */ 145538cc658fSJohn Baldwin 145638cc658fSJohn Baldwin /* Put PHY into ready state */ 145738cc658fSJohn Baldwin BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 145838cc658fSJohn Baldwin CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 145938cc658fSJohn Baldwin DELAY(40); 146038cc658fSJohn Baldwin } 146138cc658fSJohn Baldwin 146295d67482SBill Paul return (0); 146395d67482SBill Paul } 146495d67482SBill Paul 146595d67482SBill Paul static int 14663f74909aSGleb Smirnoff bge_blockinit(struct bge_softc *sc) 146795d67482SBill Paul { 146895d67482SBill Paul struct bge_rcb *rcb; 1469e907febfSPyun YongHyeon bus_size_t vrcb; 1470e907febfSPyun YongHyeon bge_hostaddr taddr; 14716f8718a3SScott Long uint32_t val; 147295d67482SBill Paul int i; 147395d67482SBill Paul 147495d67482SBill Paul /* 147595d67482SBill Paul * Initialize the memory window pointer register so that 147695d67482SBill Paul * we can access the first 32K of internal NIC RAM. This will 147795d67482SBill Paul * allow us to set up the TX send ring RCBs and the RX return 147895d67482SBill Paul * ring RCBs, plus other things which live in NIC memory. 147995d67482SBill Paul */ 148095d67482SBill Paul CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 148195d67482SBill Paul 1482822f63fcSBill Paul /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1483822f63fcSBill Paul 14847ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 148595d67482SBill Paul /* Configure mbuf memory pool */ 14860dae9719SJung-uk Kim CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1487822f63fcSBill Paul if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1488822f63fcSBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1489822f63fcSBill Paul else 149095d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 149195d67482SBill Paul 149295d67482SBill Paul /* Configure DMA resource pool */ 14930434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 14940434d1b8SBill Paul BGE_DMA_DESCRIPTORS); 149595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 14960434d1b8SBill Paul } 149795d67482SBill Paul 149895d67482SBill Paul /* Configure mbuf pool watermarks */ 149938cc658fSJohn Baldwin if (!BGE_IS_5705_PLUS(sc)) { 1500fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1501fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1502fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 150338cc658fSJohn Baldwin } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 150438cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 150538cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 150638cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 150738cc658fSJohn Baldwin } else { 150838cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 150938cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 151038cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 151138cc658fSJohn Baldwin } 151295d67482SBill Paul 151395d67482SBill Paul /* Configure DMA resource watermarks */ 151495d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 151595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 151695d67482SBill Paul 151795d67482SBill Paul /* Enable buffer manager */ 15187ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 151995d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MODE, 152095d67482SBill Paul BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 152195d67482SBill Paul 152295d67482SBill Paul /* Poll for buffer manager start indication */ 152395d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 1524d5d23857SJung-uk Kim DELAY(10); 15250c8aa4eaSJung-uk Kim if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 152695d67482SBill Paul break; 152795d67482SBill Paul } 152895d67482SBill Paul 152995d67482SBill Paul if (i == BGE_TIMEOUT) { 1530fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1531fe806fdaSPyun YongHyeon "buffer manager failed to start\n"); 153295d67482SBill Paul return (ENXIO); 153395d67482SBill Paul } 15340434d1b8SBill Paul } 153595d67482SBill Paul 153695d67482SBill Paul /* Enable flow-through queues */ 15370c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 153895d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 153995d67482SBill Paul 154095d67482SBill Paul /* Wait until queue initialization is complete */ 154195d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 1542d5d23857SJung-uk Kim DELAY(10); 154395d67482SBill Paul if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 154495d67482SBill Paul break; 154595d67482SBill Paul } 154695d67482SBill Paul 154795d67482SBill Paul if (i == BGE_TIMEOUT) { 1548fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "flow-through queue init failed\n"); 154995d67482SBill Paul return (ENXIO); 155095d67482SBill Paul } 155195d67482SBill Paul 155295d67482SBill Paul /* Initialize the standard RX ring control block */ 1553f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1554f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 1555f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1556f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 1557f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1558f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1559f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 15607ee00338SJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 15610434d1b8SBill Paul rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 15620434d1b8SBill Paul else 15630434d1b8SBill Paul rcb->bge_maxlen_flags = 15640434d1b8SBill Paul BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 156595d67482SBill Paul rcb->bge_nicaddr = BGE_STD_RX_RINGS; 15660c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 15670c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1568f41ac2beSBill Paul 156967111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 157067111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 157195d67482SBill Paul 157295d67482SBill Paul /* 157395d67482SBill Paul * Initialize the jumbo RX ring control block 157495d67482SBill Paul * We set the 'ring disabled' bit in the flags 157595d67482SBill Paul * field until we're actually ready to start 157695d67482SBill Paul * using this ring (i.e. once we set the MTU 157795d67482SBill Paul * high enough to require it). 157895d67482SBill Paul */ 15794c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 1580f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1581f41ac2beSBill Paul 1582f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 1583f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1584f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 1585f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1586f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1587f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 1588f41ac2beSBill Paul BUS_DMASYNC_PREREAD); 15891be6acb7SGleb Smirnoff rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 15901be6acb7SGleb Smirnoff BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 159195d67482SBill Paul rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 159267111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 159367111612SJohn Polstra rcb->bge_hostaddr.bge_addr_hi); 159467111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 159567111612SJohn Polstra rcb->bge_hostaddr.bge_addr_lo); 1596f41ac2beSBill Paul 15970434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 15980434d1b8SBill Paul rcb->bge_maxlen_flags); 159967111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 160095d67482SBill Paul 160195d67482SBill Paul /* Set up dummy disabled mini ring RCB */ 1602f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 160367111612SJohn Polstra rcb->bge_maxlen_flags = 160467111612SJohn Polstra BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 16050434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 16060434d1b8SBill Paul rcb->bge_maxlen_flags); 16070434d1b8SBill Paul } 160895d67482SBill Paul 160995d67482SBill Paul /* 161095d67482SBill Paul * Set the BD ring replentish thresholds. The recommended 161195d67482SBill Paul * values are 1/8th the number of descriptors allocated to 161295d67482SBill Paul * each ring. 16139ba784dbSScott Long * XXX The 5754 requires a lower threshold, so it might be a 16149ba784dbSScott Long * requirement of all 575x family chips. The Linux driver sets 16159ba784dbSScott Long * the lower threshold for all 5705 family chips as well, but there 16169ba784dbSScott Long * are reports that it might not need to be so strict. 161738cc658fSJohn Baldwin * 161838cc658fSJohn Baldwin * XXX Linux does some extra fiddling here for the 5906 parts as 161938cc658fSJohn Baldwin * well. 162095d67482SBill Paul */ 16215345bad0SScott Long if (BGE_IS_5705_PLUS(sc)) 16226f8718a3SScott Long val = 8; 16236f8718a3SScott Long else 16246f8718a3SScott Long val = BGE_STD_RX_RING_CNT / 8; 16256f8718a3SScott Long CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 16262a141b94SPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc)) 16272a141b94SPyun YongHyeon CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 16282a141b94SPyun YongHyeon BGE_JUMBO_RX_RING_CNT/8); 162995d67482SBill Paul 163095d67482SBill Paul /* 163195d67482SBill Paul * Disable all unused send rings by setting the 'ring disabled' 163295d67482SBill Paul * bit in the flags field of all the TX send ring control blocks. 163395d67482SBill Paul * These are located in NIC memory. 163495d67482SBill Paul */ 1635e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 163695d67482SBill Paul for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1637e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1638e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1639e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1640e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 164195d67482SBill Paul } 164295d67482SBill Paul 164395d67482SBill Paul /* Configure TX RCB 0 (we use only the first ring) */ 1644e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1645e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1646e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1647e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1648e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1649e907febfSPyun YongHyeon BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 16507ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 1651e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1652e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 165395d67482SBill Paul 165495d67482SBill Paul /* Disable all unused RX return rings */ 1655e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 165695d67482SBill Paul for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1657e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1658e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1659e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 16600434d1b8SBill Paul BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1661e907febfSPyun YongHyeon BGE_RCB_FLAG_RING_DISABLED)); 1662e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 166338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 16643f74909aSGleb Smirnoff (i * (sizeof(uint64_t))), 0); 1665e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 166695d67482SBill Paul } 166795d67482SBill Paul 166895d67482SBill Paul /* Initialize RX ring indexes */ 166938cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 16702a141b94SPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc)) 167138cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 16722a141b94SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 167338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 167495d67482SBill Paul 167595d67482SBill Paul /* 167695d67482SBill Paul * Set up RX return ring 0 167795d67482SBill Paul * Note that the NIC address for RX return rings is 0x00000000. 167895d67482SBill Paul * The return rings live entirely within the host, so the 167995d67482SBill Paul * nicaddr field in the RCB isn't used. 168095d67482SBill Paul */ 1681e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1682e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1683e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1684e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1685e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1686e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1687e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 168895d67482SBill Paul 168995d67482SBill Paul /* Set random backoff seed for TX */ 169095d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 16914a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 16924a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 16934a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 169495d67482SBill Paul BGE_TX_BACKOFF_SEED_MASK); 169595d67482SBill Paul 169695d67482SBill Paul /* Set inter-packet gap */ 169795d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 169895d67482SBill Paul 169995d67482SBill Paul /* 170095d67482SBill Paul * Specify which ring to use for packets that don't match 170195d67482SBill Paul * any RX rules. 170295d67482SBill Paul */ 170395d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 170495d67482SBill Paul 170595d67482SBill Paul /* 170695d67482SBill Paul * Configure number of RX lists. One interrupt distribution 170795d67482SBill Paul * list, sixteen active lists, one bad frames class. 170895d67482SBill Paul */ 170995d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 171095d67482SBill Paul 171195d67482SBill Paul /* Inialize RX list placement stats mask. */ 17120c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 171395d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 171495d67482SBill Paul 171595d67482SBill Paul /* Disable host coalescing until we get it set up */ 171695d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 171795d67482SBill Paul 171895d67482SBill Paul /* Poll to make sure it's shut down. */ 171995d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 1720d5d23857SJung-uk Kim DELAY(10); 172195d67482SBill Paul if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 172295d67482SBill Paul break; 172395d67482SBill Paul } 172495d67482SBill Paul 172595d67482SBill Paul if (i == BGE_TIMEOUT) { 1726fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1727fe806fdaSPyun YongHyeon "host coalescing engine failed to idle\n"); 172895d67482SBill Paul return (ENXIO); 172995d67482SBill Paul } 173095d67482SBill Paul 173195d67482SBill Paul /* Set up host coalescing defaults */ 173295d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 173395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 173495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 173595d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 17367ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 173795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 173895d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 17390434d1b8SBill Paul } 1740b64728e5SBruce Evans CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1741b64728e5SBruce Evans CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 174295d67482SBill Paul 174395d67482SBill Paul /* Set up address of statistics block */ 17447ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 1745f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1746f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 174795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1748f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 17490434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 175095d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 17510434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 17520434d1b8SBill Paul } 17530434d1b8SBill Paul 17540434d1b8SBill Paul /* Set up address of status block */ 1755f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1756f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 175795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1758f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 175995d67482SBill Paul 176030f57f61SPyun YongHyeon /* Set up status block size. */ 176130f57f61SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1762864104feSPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 176330f57f61SPyun YongHyeon val = BGE_STATBLKSZ_FULL; 1764864104feSPyun YongHyeon bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1765864104feSPyun YongHyeon } else { 176630f57f61SPyun YongHyeon val = BGE_STATBLKSZ_32BYTE; 1767864104feSPyun YongHyeon bzero(sc->bge_ldata.bge_status_block, 32); 1768864104feSPyun YongHyeon } 1769864104feSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1770864104feSPyun YongHyeon sc->bge_cdata.bge_status_map, 1771864104feSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 177230f57f61SPyun YongHyeon 177395d67482SBill Paul /* Turn on host coalescing state machine */ 177430f57f61SPyun YongHyeon CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 177595d67482SBill Paul 177695d67482SBill Paul /* Turn on RX BD completion state machine and enable attentions */ 177795d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDC_MODE, 177895d67482SBill Paul BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 177995d67482SBill Paul 178095d67482SBill Paul /* Turn on RX list placement state machine */ 178195d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 178295d67482SBill Paul 178395d67482SBill Paul /* Turn on RX list selector state machine. */ 17847ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 178595d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 178695d67482SBill Paul 1787ea3b4127SPyun YongHyeon val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1788ea3b4127SPyun YongHyeon BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1789ea3b4127SPyun YongHyeon BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1790ea3b4127SPyun YongHyeon BGE_MACMODE_FRMHDR_DMA_ENB; 1791ea3b4127SPyun YongHyeon 1792ea3b4127SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TBI) 1793ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_TBI; 1794ea3b4127SPyun YongHyeon else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1795ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_GMII; 1796ea3b4127SPyun YongHyeon else 1797ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_MII; 1798ea3b4127SPyun YongHyeon 179995d67482SBill Paul /* Turn on DMA, clear stats */ 1800ea3b4127SPyun YongHyeon CSR_WRITE_4(sc, BGE_MAC_MODE, val); 180195d67482SBill Paul 180295d67482SBill Paul /* Set misc. local control, enable interrupts on attentions */ 180395d67482SBill Paul CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 180495d67482SBill Paul 180595d67482SBill Paul #ifdef notdef 180695d67482SBill Paul /* Assert GPIO pins for PHY reset */ 180795d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 180895d67482SBill Paul BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 180995d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 181095d67482SBill Paul BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 181195d67482SBill Paul #endif 181295d67482SBill Paul 181395d67482SBill Paul /* Turn on DMA completion state machine */ 18147ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 181595d67482SBill Paul CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 181695d67482SBill Paul 18176f8718a3SScott Long val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 18186f8718a3SScott Long 18196f8718a3SScott Long /* Enable host coalescing bug fix. */ 1820a5779553SStanislav Sedov if (BGE_IS_5755_PLUS(sc)) 18213889907fSStanislav Sedov val |= BGE_WDMAMODE_STATUS_TAG_FIX; 18226f8718a3SScott Long 182395d67482SBill Paul /* Turn on write DMA state machine */ 18246f8718a3SScott Long CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 18254f09c4c7SMarius Strobl DELAY(40); 182695d67482SBill Paul 182795d67482SBill Paul /* Turn on read DMA state machine */ 18284f09c4c7SMarius Strobl val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1829a5779553SStanislav Sedov if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1830a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1831a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM57780) 1832a5779553SStanislav Sedov val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1833a5779553SStanislav Sedov BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1834a5779553SStanislav Sedov BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 18354f09c4c7SMarius Strobl if (sc->bge_flags & BGE_FLAG_PCIE) 18364f09c4c7SMarius Strobl val |= BGE_RDMAMODE_FIFO_LONG_BURST; 183755a24a05SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TSO) { 1838ca3f1187SPyun YongHyeon val |= BGE_RDMAMODE_TSO4_ENABLE; 183955a24a05SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5785 || 184055a24a05SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM57780) 184155a24a05SPyun YongHyeon val |= BGE_RDMAMODE_TSO6_ENABLE; 184255a24a05SPyun YongHyeon } 18434f09c4c7SMarius Strobl CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 18444f09c4c7SMarius Strobl DELAY(40); 184595d67482SBill Paul 184695d67482SBill Paul /* Turn on RX data completion state machine */ 184795d67482SBill Paul CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 184895d67482SBill Paul 184995d67482SBill Paul /* Turn on RX BD initiator state machine */ 185095d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 185195d67482SBill Paul 185295d67482SBill Paul /* Turn on RX data and RX BD initiator state machine */ 185395d67482SBill Paul CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 185495d67482SBill Paul 185595d67482SBill Paul /* Turn on Mbuf cluster free state machine */ 18567ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 185795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 185895d67482SBill Paul 185995d67482SBill Paul /* Turn on send BD completion state machine */ 186095d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 186195d67482SBill Paul 186295d67482SBill Paul /* Turn on send data completion state machine */ 1863a5779553SStanislav Sedov val = BGE_SDCMODE_ENABLE; 1864a5779553SStanislav Sedov if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1865a5779553SStanislav Sedov val |= BGE_SDCMODE_CDELAY; 1866a5779553SStanislav Sedov CSR_WRITE_4(sc, BGE_SDC_MODE, val); 186795d67482SBill Paul 186895d67482SBill Paul /* Turn on send data initiator state machine */ 1869ca3f1187SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TSO) 1870ca3f1187SPyun YongHyeon CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1871ca3f1187SPyun YongHyeon else 187295d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 187395d67482SBill Paul 187495d67482SBill Paul /* Turn on send BD initiator state machine */ 187595d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 187695d67482SBill Paul 187795d67482SBill Paul /* Turn on send BD selector state machine */ 187895d67482SBill Paul CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 187995d67482SBill Paul 18800c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 188195d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 188295d67482SBill Paul BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 188395d67482SBill Paul 188495d67482SBill Paul /* ack/clear link change events */ 188595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 18860434d1b8SBill Paul BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 18870434d1b8SBill Paul BGE_MACSTAT_LINK_CHANGED); 1888f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_MI_STS, 0); 188995d67482SBill Paul 189095d67482SBill Paul /* Enable PHY auto polling (for MII/GMII only) */ 1891652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 189295d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1893a1d52896SBill Paul } else { 18946098821cSJung-uk Kim BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 18951f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 18964c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1897a1d52896SBill Paul CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1898a1d52896SBill Paul BGE_EVTENB_MI_INTERRUPT); 1899a1d52896SBill Paul } 190095d67482SBill Paul 19011f313773SOleg Bulyzhin /* 19021f313773SOleg Bulyzhin * Clear any pending link state attention. 19031f313773SOleg Bulyzhin * Otherwise some link state change events may be lost until attention 19041f313773SOleg Bulyzhin * is cleared by bge_intr() -> bge_link_upd() sequence. 19051f313773SOleg Bulyzhin * It's not necessary on newer BCM chips - perhaps enabling link 19061f313773SOleg Bulyzhin * state change attentions implies clearing pending attention. 19071f313773SOleg Bulyzhin */ 19081f313773SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 19091f313773SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 19101f313773SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 19111f313773SOleg Bulyzhin 191295d67482SBill Paul /* Enable link state change attentions. */ 191395d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 191495d67482SBill Paul 191595d67482SBill Paul return (0); 191695d67482SBill Paul } 191795d67482SBill Paul 19184c0da0ffSGleb Smirnoff const struct bge_revision * 19194c0da0ffSGleb Smirnoff bge_lookup_rev(uint32_t chipid) 19204c0da0ffSGleb Smirnoff { 19214c0da0ffSGleb Smirnoff const struct bge_revision *br; 19224c0da0ffSGleb Smirnoff 19234c0da0ffSGleb Smirnoff for (br = bge_revisions; br->br_name != NULL; br++) { 19244c0da0ffSGleb Smirnoff if (br->br_chipid == chipid) 19254c0da0ffSGleb Smirnoff return (br); 19264c0da0ffSGleb Smirnoff } 19274c0da0ffSGleb Smirnoff 19284c0da0ffSGleb Smirnoff for (br = bge_majorrevs; br->br_name != NULL; br++) { 19294c0da0ffSGleb Smirnoff if (br->br_chipid == BGE_ASICREV(chipid)) 19304c0da0ffSGleb Smirnoff return (br); 19314c0da0ffSGleb Smirnoff } 19324c0da0ffSGleb Smirnoff 19334c0da0ffSGleb Smirnoff return (NULL); 19344c0da0ffSGleb Smirnoff } 19354c0da0ffSGleb Smirnoff 19364c0da0ffSGleb Smirnoff const struct bge_vendor * 19374c0da0ffSGleb Smirnoff bge_lookup_vendor(uint16_t vid) 19384c0da0ffSGleb Smirnoff { 19394c0da0ffSGleb Smirnoff const struct bge_vendor *v; 19404c0da0ffSGleb Smirnoff 19414c0da0ffSGleb Smirnoff for (v = bge_vendors; v->v_name != NULL; v++) 19424c0da0ffSGleb Smirnoff if (v->v_id == vid) 19434c0da0ffSGleb Smirnoff return (v); 19444c0da0ffSGleb Smirnoff 19454c0da0ffSGleb Smirnoff panic("%s: unknown vendor %d", __func__, vid); 19464c0da0ffSGleb Smirnoff return (NULL); 19474c0da0ffSGleb Smirnoff } 19484c0da0ffSGleb Smirnoff 194995d67482SBill Paul /* 195095d67482SBill Paul * Probe for a Broadcom chip. Check the PCI vendor and device IDs 19514c0da0ffSGleb Smirnoff * against our list and return its name if we find a match. 19524c0da0ffSGleb Smirnoff * 19534c0da0ffSGleb Smirnoff * Note that since the Broadcom controller contains VPD support, we 19547c929cf9SJung-uk Kim * try to get the device name string from the controller itself instead 19557c929cf9SJung-uk Kim * of the compiled-in string. It guarantees we'll always announce the 19567c929cf9SJung-uk Kim * right product name. We fall back to the compiled-in string when 19577c929cf9SJung-uk Kim * VPD is unavailable or corrupt. 195895d67482SBill Paul */ 195995d67482SBill Paul static int 19603f74909aSGleb Smirnoff bge_probe(device_t dev) 196195d67482SBill Paul { 1962852c67f9SMarius Strobl const struct bge_type *t = bge_devs; 19634c0da0ffSGleb Smirnoff struct bge_softc *sc = device_get_softc(dev); 19647c929cf9SJung-uk Kim uint16_t vid, did; 196595d67482SBill Paul 196695d67482SBill Paul sc->bge_dev = dev; 19677c929cf9SJung-uk Kim vid = pci_get_vendor(dev); 19687c929cf9SJung-uk Kim did = pci_get_device(dev); 19694c0da0ffSGleb Smirnoff while(t->bge_vid != 0) { 19707c929cf9SJung-uk Kim if ((vid == t->bge_vid) && (did == t->bge_did)) { 19717c929cf9SJung-uk Kim char model[64], buf[96]; 19724c0da0ffSGleb Smirnoff const struct bge_revision *br; 19734c0da0ffSGleb Smirnoff const struct bge_vendor *v; 19744c0da0ffSGleb Smirnoff uint32_t id; 19754c0da0ffSGleb Smirnoff 1976a5779553SStanislav Sedov id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1977a5779553SStanislav Sedov BGE_PCIMISCCTL_ASICREV_SHIFT; 1978a5779553SStanislav Sedov if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 1979a5779553SStanislav Sedov id = pci_read_config(dev, 1980a5779553SStanislav Sedov BGE_PCI_PRODID_ASICREV, 4); 19814c0da0ffSGleb Smirnoff br = bge_lookup_rev(id); 19827c929cf9SJung-uk Kim v = bge_lookup_vendor(vid); 19834e35d186SJung-uk Kim { 19844e35d186SJung-uk Kim #if __FreeBSD_version > 700024 19854e35d186SJung-uk Kim const char *pname; 19864e35d186SJung-uk Kim 1987852c67f9SMarius Strobl if (bge_has_eaddr(sc) && 1988852c67f9SMarius Strobl pci_get_vpd_ident(dev, &pname) == 0) 19894e35d186SJung-uk Kim snprintf(model, 64, "%s", pname); 19904e35d186SJung-uk Kim else 19914e35d186SJung-uk Kim #endif 19927c929cf9SJung-uk Kim snprintf(model, 64, "%s %s", 19937c929cf9SJung-uk Kim v->v_name, 19947c929cf9SJung-uk Kim br != NULL ? br->br_name : 19957c929cf9SJung-uk Kim "NetXtreme Ethernet Controller"); 19964e35d186SJung-uk Kim } 1997a5779553SStanislav Sedov snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 1998a5779553SStanislav Sedov br != NULL ? "" : "unknown ", id); 19994c0da0ffSGleb Smirnoff device_set_desc_copy(dev, buf); 200095d67482SBill Paul return (0); 200195d67482SBill Paul } 200295d67482SBill Paul t++; 200395d67482SBill Paul } 200495d67482SBill Paul 200595d67482SBill Paul return (ENXIO); 200695d67482SBill Paul } 200795d67482SBill Paul 2008f41ac2beSBill Paul static void 20093f74909aSGleb Smirnoff bge_dma_free(struct bge_softc *sc) 2010f41ac2beSBill Paul { 2011f41ac2beSBill Paul int i; 2012f41ac2beSBill Paul 20133f74909aSGleb Smirnoff /* Destroy DMA maps for RX buffers. */ 2014f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2015f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_dmamap[i]) 20160ac56796SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2017f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 2018f41ac2beSBill Paul } 2019943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_sparemap) 2020943787f3SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2021943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap); 2022f41ac2beSBill Paul 20233f74909aSGleb Smirnoff /* Destroy DMA maps for jumbo RX buffers. */ 2024f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2025f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2026f41ac2beSBill Paul bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2027f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2028f41ac2beSBill Paul } 2029943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2030943787f3SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2031943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap); 2032f41ac2beSBill Paul 20333f74909aSGleb Smirnoff /* Destroy DMA maps for TX buffers. */ 2034f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 2035f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_dmamap[i]) 20360ac56796SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2037f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 2038f41ac2beSBill Paul } 2039f41ac2beSBill Paul 20400ac56796SPyun YongHyeon if (sc->bge_cdata.bge_rx_mtag) 20410ac56796SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 20420ac56796SPyun YongHyeon if (sc->bge_cdata.bge_tx_mtag) 20430ac56796SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2044f41ac2beSBill Paul 2045f41ac2beSBill Paul 20463f74909aSGleb Smirnoff /* Destroy standard RX ring. */ 2047e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_ring_map) 2048e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2049e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map); 2050e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2051f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2052f41ac2beSBill Paul sc->bge_ldata.bge_rx_std_ring, 2053f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map); 2054f41ac2beSBill Paul 2055f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_ring_tag) 2056f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2057f41ac2beSBill Paul 20583f74909aSGleb Smirnoff /* Destroy jumbo RX ring. */ 2059e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2060e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2061e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_ring_map); 2062e65bed95SPyun YongHyeon 2063e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2064e65bed95SPyun YongHyeon sc->bge_ldata.bge_rx_jumbo_ring) 2065f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2066f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring, 2067f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map); 2068f41ac2beSBill Paul 2069f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2070f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2071f41ac2beSBill Paul 20723f74909aSGleb Smirnoff /* Destroy RX return ring. */ 2073e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_return_ring_map) 2074e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2075e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map); 2076e65bed95SPyun YongHyeon 2077e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_return_ring_map && 2078e65bed95SPyun YongHyeon sc->bge_ldata.bge_rx_return_ring) 2079f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2080f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring, 2081f41ac2beSBill Paul sc->bge_cdata.bge_rx_return_ring_map); 2082f41ac2beSBill Paul 2083f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_return_ring_tag) 2084f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2085f41ac2beSBill Paul 20863f74909aSGleb Smirnoff /* Destroy TX ring. */ 2087e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_tx_ring_map) 2088e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2089e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_ring_map); 2090e65bed95SPyun YongHyeon 2091e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2092f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2093f41ac2beSBill Paul sc->bge_ldata.bge_tx_ring, 2094f41ac2beSBill Paul sc->bge_cdata.bge_tx_ring_map); 2095f41ac2beSBill Paul 2096f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_ring_tag) 2097f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2098f41ac2beSBill Paul 20993f74909aSGleb Smirnoff /* Destroy status block. */ 2100e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_status_map) 2101e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2102e65bed95SPyun YongHyeon sc->bge_cdata.bge_status_map); 2103e65bed95SPyun YongHyeon 2104e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2105f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2106f41ac2beSBill Paul sc->bge_ldata.bge_status_block, 2107f41ac2beSBill Paul sc->bge_cdata.bge_status_map); 2108f41ac2beSBill Paul 2109f41ac2beSBill Paul if (sc->bge_cdata.bge_status_tag) 2110f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2111f41ac2beSBill Paul 21123f74909aSGleb Smirnoff /* Destroy statistics block. */ 2113e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_stats_map) 2114e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2115e65bed95SPyun YongHyeon sc->bge_cdata.bge_stats_map); 2116e65bed95SPyun YongHyeon 2117e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2118f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2119f41ac2beSBill Paul sc->bge_ldata.bge_stats, 2120f41ac2beSBill Paul sc->bge_cdata.bge_stats_map); 2121f41ac2beSBill Paul 2122f41ac2beSBill Paul if (sc->bge_cdata.bge_stats_tag) 2123f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2124f41ac2beSBill Paul 21253f74909aSGleb Smirnoff /* Destroy the parent tag. */ 2126f41ac2beSBill Paul if (sc->bge_cdata.bge_parent_tag) 2127f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2128f41ac2beSBill Paul } 2129f41ac2beSBill Paul 2130f41ac2beSBill Paul static int 21313f74909aSGleb Smirnoff bge_dma_alloc(device_t dev) 2132f41ac2beSBill Paul { 21333f74909aSGleb Smirnoff struct bge_dmamap_arg ctx; 2134f41ac2beSBill Paul struct bge_softc *sc; 2135f681b29aSPyun YongHyeon bus_addr_t lowaddr; 213630f57f61SPyun YongHyeon bus_size_t sbsz, txsegsz, txmaxsegsz; 21371be6acb7SGleb Smirnoff int i, error; 2138f41ac2beSBill Paul 2139f41ac2beSBill Paul sc = device_get_softc(dev); 2140f41ac2beSBill Paul 2141f681b29aSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 2142f681b29aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2143f681b29aSPyun YongHyeon lowaddr = BGE_DMA_MAXADDR; 2144f681b29aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2145f681b29aSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 2146f41ac2beSBill Paul /* 2147f41ac2beSBill Paul * Allocate the parent bus DMA tag appropriate for PCI. 2148f41ac2beSBill Paul */ 21494eee14cbSMarius Strobl error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2150f681b29aSPyun YongHyeon 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 21514eee14cbSMarius Strobl NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 21524eee14cbSMarius Strobl 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2153f41ac2beSBill Paul 2154e65bed95SPyun YongHyeon if (error != 0) { 2155fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2156fe806fdaSPyun YongHyeon "could not allocate parent dma tag\n"); 2157e65bed95SPyun YongHyeon return (ENOMEM); 2158e65bed95SPyun YongHyeon } 2159e65bed95SPyun YongHyeon 2160f41ac2beSBill Paul /* 21610ac56796SPyun YongHyeon * Create tag for Tx mbufs. 2162f41ac2beSBill Paul */ 2163ca3f1187SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TSO) { 2164ca3f1187SPyun YongHyeon txsegsz = BGE_TSOSEG_SZ; 2165ca3f1187SPyun YongHyeon txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2166ca3f1187SPyun YongHyeon } else { 2167ca3f1187SPyun YongHyeon txsegsz = MCLBYTES; 2168ca3f1187SPyun YongHyeon txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2169ca3f1187SPyun YongHyeon } 21708a2e22deSScott Long error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2171ca3f1187SPyun YongHyeon 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2172ca3f1187SPyun YongHyeon txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2173ca3f1187SPyun YongHyeon &sc->bge_cdata.bge_tx_mtag); 2174f41ac2beSBill Paul 2175f41ac2beSBill Paul if (error) { 21760ac56796SPyun YongHyeon device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 21770ac56796SPyun YongHyeon return (ENOMEM); 21780ac56796SPyun YongHyeon } 21790ac56796SPyun YongHyeon 21800ac56796SPyun YongHyeon /* 21810ac56796SPyun YongHyeon * Create tag for Rx mbufs. 21820ac56796SPyun YongHyeon */ 21830ac56796SPyun YongHyeon error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 21840ac56796SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2185ca3f1187SPyun YongHyeon MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 21860ac56796SPyun YongHyeon 21870ac56796SPyun YongHyeon if (error) { 21880ac56796SPyun YongHyeon device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2189f41ac2beSBill Paul return (ENOMEM); 2190f41ac2beSBill Paul } 2191f41ac2beSBill Paul 21923f74909aSGleb Smirnoff /* Create DMA maps for RX buffers. */ 2193943787f3SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2194943787f3SPyun YongHyeon &sc->bge_cdata.bge_rx_std_sparemap); 2195943787f3SPyun YongHyeon if (error) { 2196943787f3SPyun YongHyeon device_printf(sc->bge_dev, 2197943787f3SPyun YongHyeon "can't create spare DMA map for RX\n"); 2198943787f3SPyun YongHyeon return (ENOMEM); 2199943787f3SPyun YongHyeon } 2200f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 22010ac56796SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2202f41ac2beSBill Paul &sc->bge_cdata.bge_rx_std_dmamap[i]); 2203f41ac2beSBill Paul if (error) { 2204fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2205fe806fdaSPyun YongHyeon "can't create DMA map for RX\n"); 2206f41ac2beSBill Paul return (ENOMEM); 2207f41ac2beSBill Paul } 2208f41ac2beSBill Paul } 2209f41ac2beSBill Paul 22103f74909aSGleb Smirnoff /* Create DMA maps for TX buffers. */ 2211f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 22120ac56796SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2213f41ac2beSBill Paul &sc->bge_cdata.bge_tx_dmamap[i]); 2214f41ac2beSBill Paul if (error) { 2215fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 22160ac56796SPyun YongHyeon "can't create DMA map for TX\n"); 2217f41ac2beSBill Paul return (ENOMEM); 2218f41ac2beSBill Paul } 2219f41ac2beSBill Paul } 2220f41ac2beSBill Paul 22213f74909aSGleb Smirnoff /* Create tag for standard RX ring. */ 2222f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2223f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2224f41ac2beSBill Paul NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2225f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2226f41ac2beSBill Paul 2227f41ac2beSBill Paul if (error) { 2228fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2229f41ac2beSBill Paul return (ENOMEM); 2230f41ac2beSBill Paul } 2231f41ac2beSBill Paul 22323f74909aSGleb Smirnoff /* Allocate DMA'able memory for standard RX ring. */ 2233f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2234f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2235f41ac2beSBill Paul &sc->bge_cdata.bge_rx_std_ring_map); 2236f41ac2beSBill Paul if (error) 2237f41ac2beSBill Paul return (ENOMEM); 2238f41ac2beSBill Paul 2239f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2240f41ac2beSBill Paul 22413f74909aSGleb Smirnoff /* Load the address of the standard RX ring. */ 2242f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2243f41ac2beSBill Paul ctx.sc = sc; 2244f41ac2beSBill Paul 2245f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2246f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2247f41ac2beSBill Paul BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2248f41ac2beSBill Paul 2249f41ac2beSBill Paul if (error) 2250f41ac2beSBill Paul return (ENOMEM); 2251f41ac2beSBill Paul 2252f41ac2beSBill Paul sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2253f41ac2beSBill Paul 22543f74909aSGleb Smirnoff /* Create tags for jumbo mbufs. */ 22554c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 2256f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 22578a2e22deSScott Long 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 22581be6acb7SGleb Smirnoff NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 22591be6acb7SGleb Smirnoff 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2260f41ac2beSBill Paul if (error) { 2261fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 22623f74909aSGleb Smirnoff "could not allocate jumbo dma tag\n"); 2263f41ac2beSBill Paul return (ENOMEM); 2264f41ac2beSBill Paul } 2265f41ac2beSBill Paul 22663f74909aSGleb Smirnoff /* Create tag for jumbo RX ring. */ 2267f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2268f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2269f41ac2beSBill Paul NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2270f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2271f41ac2beSBill Paul 2272f41ac2beSBill Paul if (error) { 2273fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 22743f74909aSGleb Smirnoff "could not allocate jumbo ring dma tag\n"); 2275f41ac2beSBill Paul return (ENOMEM); 2276f41ac2beSBill Paul } 2277f41ac2beSBill Paul 22783f74909aSGleb Smirnoff /* Allocate DMA'able memory for jumbo RX ring. */ 2279f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 22801be6acb7SGleb Smirnoff (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 22811be6acb7SGleb Smirnoff BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2282f41ac2beSBill Paul &sc->bge_cdata.bge_rx_jumbo_ring_map); 2283f41ac2beSBill Paul if (error) 2284f41ac2beSBill Paul return (ENOMEM); 2285f41ac2beSBill Paul 22863f74909aSGleb Smirnoff /* Load the address of the jumbo RX ring. */ 2287f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2288f41ac2beSBill Paul ctx.sc = sc; 2289f41ac2beSBill Paul 2290f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2291f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 2292f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2293f41ac2beSBill Paul bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2294f41ac2beSBill Paul 2295f41ac2beSBill Paul if (error) 2296f41ac2beSBill Paul return (ENOMEM); 2297f41ac2beSBill Paul 2298f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2299f41ac2beSBill Paul 23003f74909aSGleb Smirnoff /* Create DMA maps for jumbo RX buffers. */ 2301943787f3SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2302943787f3SPyun YongHyeon 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2303943787f3SPyun YongHyeon if (error) { 2304943787f3SPyun YongHyeon device_printf(sc->bge_dev, 23051b90d0bdSPyun YongHyeon "can't create spare DMA map for jumbo RX\n"); 2306943787f3SPyun YongHyeon return (ENOMEM); 2307943787f3SPyun YongHyeon } 2308f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2309f41ac2beSBill Paul error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2310f41ac2beSBill Paul 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2311f41ac2beSBill Paul if (error) { 2312fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 23133f74909aSGleb Smirnoff "can't create DMA map for jumbo RX\n"); 2314f41ac2beSBill Paul return (ENOMEM); 2315f41ac2beSBill Paul } 2316f41ac2beSBill Paul } 2317f41ac2beSBill Paul 2318f41ac2beSBill Paul } 2319f41ac2beSBill Paul 23203f74909aSGleb Smirnoff /* Create tag for RX return ring. */ 2321f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2322f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2323f41ac2beSBill Paul NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2324f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2325f41ac2beSBill Paul 2326f41ac2beSBill Paul if (error) { 2327fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2328f41ac2beSBill Paul return (ENOMEM); 2329f41ac2beSBill Paul } 2330f41ac2beSBill Paul 23313f74909aSGleb Smirnoff /* Allocate DMA'able memory for RX return ring. */ 2332f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2333f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2334f41ac2beSBill Paul &sc->bge_cdata.bge_rx_return_ring_map); 2335f41ac2beSBill Paul if (error) 2336f41ac2beSBill Paul return (ENOMEM); 2337f41ac2beSBill Paul 2338f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2339f41ac2beSBill Paul BGE_RX_RTN_RING_SZ(sc)); 2340f41ac2beSBill Paul 23413f74909aSGleb Smirnoff /* Load the address of the RX return ring. */ 2342f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2343f41ac2beSBill Paul ctx.sc = sc; 2344f41ac2beSBill Paul 2345f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2346f41ac2beSBill Paul sc->bge_cdata.bge_rx_return_ring_map, 2347f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2348f41ac2beSBill Paul bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2349f41ac2beSBill Paul 2350f41ac2beSBill Paul if (error) 2351f41ac2beSBill Paul return (ENOMEM); 2352f41ac2beSBill Paul 2353f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2354f41ac2beSBill Paul 23553f74909aSGleb Smirnoff /* Create tag for TX ring. */ 2356f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2357f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2358f41ac2beSBill Paul NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2359f41ac2beSBill Paul &sc->bge_cdata.bge_tx_ring_tag); 2360f41ac2beSBill Paul 2361f41ac2beSBill Paul if (error) { 2362fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2363f41ac2beSBill Paul return (ENOMEM); 2364f41ac2beSBill Paul } 2365f41ac2beSBill Paul 23663f74909aSGleb Smirnoff /* Allocate DMA'able memory for TX ring. */ 2367f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2368f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2369f41ac2beSBill Paul &sc->bge_cdata.bge_tx_ring_map); 2370f41ac2beSBill Paul if (error) 2371f41ac2beSBill Paul return (ENOMEM); 2372f41ac2beSBill Paul 2373f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2374f41ac2beSBill Paul 23753f74909aSGleb Smirnoff /* Load the address of the TX ring. */ 2376f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2377f41ac2beSBill Paul ctx.sc = sc; 2378f41ac2beSBill Paul 2379f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2380f41ac2beSBill Paul sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2381f41ac2beSBill Paul BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2382f41ac2beSBill Paul 2383f41ac2beSBill Paul if (error) 2384f41ac2beSBill Paul return (ENOMEM); 2385f41ac2beSBill Paul 2386f41ac2beSBill Paul sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2387f41ac2beSBill Paul 238830f57f61SPyun YongHyeon /* 238930f57f61SPyun YongHyeon * Create tag for status block. 239030f57f61SPyun YongHyeon * Because we only use single Tx/Rx/Rx return ring, use 239130f57f61SPyun YongHyeon * minimum status block size except BCM5700 AX/BX which 239230f57f61SPyun YongHyeon * seems to want to see full status block size regardless 239330f57f61SPyun YongHyeon * of configured number of ring. 239430f57f61SPyun YongHyeon */ 239530f57f61SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 239630f57f61SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 239730f57f61SPyun YongHyeon sbsz = BGE_STATUS_BLK_SZ; 239830f57f61SPyun YongHyeon else 239930f57f61SPyun YongHyeon sbsz = 32; 2400f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2401f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 240230f57f61SPyun YongHyeon NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag); 2403f41ac2beSBill Paul 2404f41ac2beSBill Paul if (error) { 240530f57f61SPyun YongHyeon device_printf(sc->bge_dev, 240630f57f61SPyun YongHyeon "could not allocate status dma tag\n"); 2407f41ac2beSBill Paul return (ENOMEM); 2408f41ac2beSBill Paul } 2409f41ac2beSBill Paul 24103f74909aSGleb Smirnoff /* Allocate DMA'able memory for status block. */ 2411f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2412f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2413f41ac2beSBill Paul &sc->bge_cdata.bge_status_map); 2414f41ac2beSBill Paul if (error) 2415f41ac2beSBill Paul return (ENOMEM); 2416f41ac2beSBill Paul 241730f57f61SPyun YongHyeon bzero((char *)sc->bge_ldata.bge_status_block, sbsz); 2418f41ac2beSBill Paul 24193f74909aSGleb Smirnoff /* Load the address of the status block. */ 2420f41ac2beSBill Paul ctx.sc = sc; 2421f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2422f41ac2beSBill Paul 2423f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2424f41ac2beSBill Paul sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 242530f57f61SPyun YongHyeon sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2426f41ac2beSBill Paul 2427f41ac2beSBill Paul if (error) 2428f41ac2beSBill Paul return (ENOMEM); 2429f41ac2beSBill Paul 2430f41ac2beSBill Paul sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2431f41ac2beSBill Paul 24323f74909aSGleb Smirnoff /* Create tag for statistics block. */ 2433f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2434f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2435f41ac2beSBill Paul NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2436f41ac2beSBill Paul &sc->bge_cdata.bge_stats_tag); 2437f41ac2beSBill Paul 2438f41ac2beSBill Paul if (error) { 2439fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2440f41ac2beSBill Paul return (ENOMEM); 2441f41ac2beSBill Paul } 2442f41ac2beSBill Paul 24433f74909aSGleb Smirnoff /* Allocate DMA'able memory for statistics block. */ 2444f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2445f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2446f41ac2beSBill Paul &sc->bge_cdata.bge_stats_map); 2447f41ac2beSBill Paul if (error) 2448f41ac2beSBill Paul return (ENOMEM); 2449f41ac2beSBill Paul 2450f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2451f41ac2beSBill Paul 24523f74909aSGleb Smirnoff /* Load the address of the statstics block. */ 2453f41ac2beSBill Paul ctx.sc = sc; 2454f41ac2beSBill Paul ctx.bge_maxsegs = 1; 2455f41ac2beSBill Paul 2456f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2457f41ac2beSBill Paul sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2458f41ac2beSBill Paul BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2459f41ac2beSBill Paul 2460f41ac2beSBill Paul if (error) 2461f41ac2beSBill Paul return (ENOMEM); 2462f41ac2beSBill Paul 2463f41ac2beSBill Paul sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2464f41ac2beSBill Paul 2465f41ac2beSBill Paul return (0); 2466f41ac2beSBill Paul } 2467f41ac2beSBill Paul 2468bf6ef57aSJohn Polstra /* 2469bf6ef57aSJohn Polstra * Return true if this device has more than one port. 2470bf6ef57aSJohn Polstra */ 2471bf6ef57aSJohn Polstra static int 2472bf6ef57aSJohn Polstra bge_has_multiple_ports(struct bge_softc *sc) 2473bf6ef57aSJohn Polstra { 2474bf6ef57aSJohn Polstra device_t dev = sc->bge_dev; 247555aaf894SMarius Strobl u_int b, d, f, fscan, s; 2476bf6ef57aSJohn Polstra 247755aaf894SMarius Strobl d = pci_get_domain(dev); 2478bf6ef57aSJohn Polstra b = pci_get_bus(dev); 2479bf6ef57aSJohn Polstra s = pci_get_slot(dev); 2480bf6ef57aSJohn Polstra f = pci_get_function(dev); 2481bf6ef57aSJohn Polstra for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 248255aaf894SMarius Strobl if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2483bf6ef57aSJohn Polstra return (1); 2484bf6ef57aSJohn Polstra return (0); 2485bf6ef57aSJohn Polstra } 2486bf6ef57aSJohn Polstra 2487bf6ef57aSJohn Polstra /* 2488bf6ef57aSJohn Polstra * Return true if MSI can be used with this device. 2489bf6ef57aSJohn Polstra */ 2490bf6ef57aSJohn Polstra static int 2491bf6ef57aSJohn Polstra bge_can_use_msi(struct bge_softc *sc) 2492bf6ef57aSJohn Polstra { 2493bf6ef57aSJohn Polstra int can_use_msi = 0; 2494bf6ef57aSJohn Polstra 2495bf6ef57aSJohn Polstra switch (sc->bge_asicrev) { 2496a8376f70SMarius Strobl case BGE_ASICREV_BCM5714_A0: 2497bf6ef57aSJohn Polstra case BGE_ASICREV_BCM5714: 2498bf6ef57aSJohn Polstra /* 2499a8376f70SMarius Strobl * Apparently, MSI doesn't work when these chips are 2500a8376f70SMarius Strobl * configured in single-port mode. 2501bf6ef57aSJohn Polstra */ 2502bf6ef57aSJohn Polstra if (bge_has_multiple_ports(sc)) 2503bf6ef57aSJohn Polstra can_use_msi = 1; 2504bf6ef57aSJohn Polstra break; 2505bf6ef57aSJohn Polstra case BGE_ASICREV_BCM5750: 2506bf6ef57aSJohn Polstra if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2507bf6ef57aSJohn Polstra sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2508bf6ef57aSJohn Polstra can_use_msi = 1; 2509bf6ef57aSJohn Polstra break; 2510a8376f70SMarius Strobl default: 2511a8376f70SMarius Strobl if (BGE_IS_575X_PLUS(sc)) 2512bf6ef57aSJohn Polstra can_use_msi = 1; 2513bf6ef57aSJohn Polstra } 2514bf6ef57aSJohn Polstra return (can_use_msi); 2515bf6ef57aSJohn Polstra } 2516bf6ef57aSJohn Polstra 251795d67482SBill Paul static int 25183f74909aSGleb Smirnoff bge_attach(device_t dev) 251995d67482SBill Paul { 252095d67482SBill Paul struct ifnet *ifp; 252195d67482SBill Paul struct bge_softc *sc; 25224f0794ffSBjoern A. Zeeb uint32_t hwcfg = 0, misccfg; 252308013fd3SMarius Strobl u_char eaddr[ETHER_ADDR_LEN]; 2524d648358bSPyun YongHyeon int error, msicount, reg, rid, trys; 252595d67482SBill Paul 252695d67482SBill Paul sc = device_get_softc(dev); 252795d67482SBill Paul sc->bge_dev = dev; 252895d67482SBill Paul 2529dfe0df9aSPyun YongHyeon TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2530dfe0df9aSPyun YongHyeon 253195d67482SBill Paul /* 253295d67482SBill Paul * Map control/status registers. 253395d67482SBill Paul */ 253495d67482SBill Paul pci_enable_busmaster(dev); 253595d67482SBill Paul 2536*736b9319SPyun YongHyeon rid = PCIR_BAR(0); 25375f96beb9SNate Lawson sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 253844f8f2fcSMarius Strobl RF_ACTIVE); 253995d67482SBill Paul 254095d67482SBill Paul if (sc->bge_res == NULL) { 2541fe806fdaSPyun YongHyeon device_printf (sc->bge_dev, "couldn't map memory\n"); 254295d67482SBill Paul error = ENXIO; 254395d67482SBill Paul goto fail; 254495d67482SBill Paul } 254595d67482SBill Paul 25464f09c4c7SMarius Strobl /* Save various chip information. */ 2547e53d81eeSPaul Saab sc->bge_chipid = 2548a5779553SStanislav Sedov pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2549a5779553SStanislav Sedov BGE_PCIMISCCTL_ASICREV_SHIFT; 2550a5779553SStanislav Sedov if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2551a5779553SStanislav Sedov sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2552a5779553SStanislav Sedov 4); 2553e53d81eeSPaul Saab sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2554e53d81eeSPaul Saab sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2555e53d81eeSPaul Saab 255686543395SJung-uk Kim /* 255738cc658fSJohn Baldwin * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 255886543395SJung-uk Kim * 5705 A0 and A1 chips. 255986543395SJung-uk Kim */ 256086543395SJung-uk Kim if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 256138cc658fSJohn Baldwin sc->bge_asicrev != BGE_ASICREV_BCM5906 && 256286543395SJung-uk Kim sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 256386543395SJung-uk Kim sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 256486543395SJung-uk Kim sc->bge_flags |= BGE_FLAG_WIRESPEED; 256586543395SJung-uk Kim 25665fea260fSMarius Strobl if (bge_has_eaddr(sc)) 25675fea260fSMarius Strobl sc->bge_flags |= BGE_FLAG_EADDR; 256808013fd3SMarius Strobl 25690dae9719SJung-uk Kim /* Save chipset family. */ 25700dae9719SJung-uk Kim switch (sc->bge_asicrev) { 2571a5779553SStanislav Sedov case BGE_ASICREV_BCM5755: 2572a5779553SStanislav Sedov case BGE_ASICREV_BCM5761: 2573a5779553SStanislav Sedov case BGE_ASICREV_BCM5784: 2574a5779553SStanislav Sedov case BGE_ASICREV_BCM5785: 2575a5779553SStanislav Sedov case BGE_ASICREV_BCM5787: 2576a5779553SStanislav Sedov case BGE_ASICREV_BCM57780: 2577a5779553SStanislav Sedov sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2578a5779553SStanislav Sedov BGE_FLAG_5705_PLUS; 2579a5779553SStanislav Sedov break; 25800dae9719SJung-uk Kim case BGE_ASICREV_BCM5700: 25810dae9719SJung-uk Kim case BGE_ASICREV_BCM5701: 25820dae9719SJung-uk Kim case BGE_ASICREV_BCM5703: 25830dae9719SJung-uk Kim case BGE_ASICREV_BCM5704: 25847ee00338SJung-uk Kim sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 25850dae9719SJung-uk Kim break; 25860dae9719SJung-uk Kim case BGE_ASICREV_BCM5714_A0: 25870dae9719SJung-uk Kim case BGE_ASICREV_BCM5780: 25880dae9719SJung-uk Kim case BGE_ASICREV_BCM5714: 25897ee00338SJung-uk Kim sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 25909fe569d8SXin LI /* FALLTHROUGH */ 25910dae9719SJung-uk Kim case BGE_ASICREV_BCM5750: 25920dae9719SJung-uk Kim case BGE_ASICREV_BCM5752: 259338cc658fSJohn Baldwin case BGE_ASICREV_BCM5906: 25940dae9719SJung-uk Kim sc->bge_flags |= BGE_FLAG_575X_PLUS; 25959fe569d8SXin LI /* FALLTHROUGH */ 25960dae9719SJung-uk Kim case BGE_ASICREV_BCM5705: 25970dae9719SJung-uk Kim sc->bge_flags |= BGE_FLAG_5705_PLUS; 25980dae9719SJung-uk Kim break; 25990dae9719SJung-uk Kim } 26000dae9719SJung-uk Kim 26015ee49a3aSJung-uk Kim /* Set various bug flags. */ 26021ec4c3a8SJung-uk Kim if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 26031ec4c3a8SJung-uk Kim sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 26041ec4c3a8SJung-uk Kim sc->bge_flags |= BGE_FLAG_CRC_BUG; 26055ee49a3aSJung-uk Kim if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 26065ee49a3aSJung-uk Kim sc->bge_chiprev == BGE_CHIPREV_5704_AX) 26075ee49a3aSJung-uk Kim sc->bge_flags |= BGE_FLAG_ADC_BUG; 26085ee49a3aSJung-uk Kim if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 26095ee49a3aSJung-uk Kim sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 26104150ce6fSPyun YongHyeon if (pci_get_subvendor(dev) == DELL_VENDORID) 26114150ce6fSPyun YongHyeon sc->bge_flags |= BGE_FLAG_NO_3LED; 26124150ce6fSPyun YongHyeon if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 26134150ce6fSPyun YongHyeon sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 261408bf8bb7SJung-uk Kim if (BGE_IS_5705_PLUS(sc) && 261508bf8bb7SJung-uk Kim !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 26165ee49a3aSJung-uk Kim if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2617a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2618a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM5784 || 26194fcf220bSJohn Baldwin sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2620f7d1b2ebSXin LI if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2621f7d1b2ebSXin LI pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 26225ee49a3aSJung-uk Kim sc->bge_flags |= BGE_FLAG_JITTER_BUG; 262338cc658fSJohn Baldwin } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 26245ee49a3aSJung-uk Kim sc->bge_flags |= BGE_FLAG_BER_BUG; 26255ee49a3aSJung-uk Kim } 26265ee49a3aSJung-uk Kim 2627f681b29aSPyun YongHyeon /* 2628f681b29aSPyun YongHyeon * All controllers that are not 5755 or higher have 4GB 2629f681b29aSPyun YongHyeon * boundary DMA bug. 2630f681b29aSPyun YongHyeon * Whenever an address crosses a multiple of the 4GB boundary 2631f681b29aSPyun YongHyeon * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2632f681b29aSPyun YongHyeon * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2633f681b29aSPyun YongHyeon * state machine will lockup and cause the device to hang. 2634f681b29aSPyun YongHyeon */ 2635f681b29aSPyun YongHyeon if (BGE_IS_5755_PLUS(sc) == 0) 2636f681b29aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 26374f0794ffSBjoern A. Zeeb 26384f0794ffSBjoern A. Zeeb /* 26394f0794ffSBjoern A. Zeeb * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 26404f0794ffSBjoern A. Zeeb * but I do not know the DEVICEID for the 5788M. 26414f0794ffSBjoern A. Zeeb */ 26424f0794ffSBjoern A. Zeeb misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 26434f0794ffSBjoern A. Zeeb if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 26444f0794ffSBjoern A. Zeeb misccfg == BGE_MISCCFG_BOARD_ID_5788M) 26454f0794ffSBjoern A. Zeeb sc->bge_flags |= BGE_FLAG_5788; 26464f0794ffSBjoern A. Zeeb 2647e53d81eeSPaul Saab /* 2648ca3f1187SPyun YongHyeon * Some controllers seem to require a special firmware to use 2649ca3f1187SPyun YongHyeon * TSO. But the firmware is not available to FreeBSD and Linux 2650ca3f1187SPyun YongHyeon * claims that the TSO performed by the firmware is slower than 2651ca3f1187SPyun YongHyeon * hardware based TSO. Moreover the firmware based TSO has one 2652ca3f1187SPyun YongHyeon * known bug which can't handle TSO if ethernet header + IP/TCP 2653ca3f1187SPyun YongHyeon * header is greater than 80 bytes. The workaround for the TSO 2654ca3f1187SPyun YongHyeon * bug exist but it seems it's too expensive than not using 2655ca3f1187SPyun YongHyeon * TSO at all. Some hardwares also have the TSO bug so limit 2656ca3f1187SPyun YongHyeon * the TSO to the controllers that are not affected TSO issues 2657ca3f1187SPyun YongHyeon * (e.g. 5755 or higher). 2658ca3f1187SPyun YongHyeon */ 26594f4a16e1SPyun YongHyeon if (BGE_IS_5755_PLUS(sc)) { 26604f4a16e1SPyun YongHyeon /* 26614f4a16e1SPyun YongHyeon * BCM5754 and BCM5787 shares the same ASIC id so 26624f4a16e1SPyun YongHyeon * explicit device id check is required. 2663be95548dSPyun YongHyeon * Due to unknown reason TSO does not work on BCM5755M. 26644f4a16e1SPyun YongHyeon */ 26654f4a16e1SPyun YongHyeon if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2666be95548dSPyun YongHyeon pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 2667be95548dSPyun YongHyeon pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 2668ca3f1187SPyun YongHyeon sc->bge_flags |= BGE_FLAG_TSO; 26694f4a16e1SPyun YongHyeon } 2670ca3f1187SPyun YongHyeon 2671ca3f1187SPyun YongHyeon /* 26726f8718a3SScott Long * Check if this is a PCI-X or PCI Express device. 2673e53d81eeSPaul Saab */ 26746f8718a3SScott Long if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 26754c0da0ffSGleb Smirnoff /* 26766f8718a3SScott Long * Found a PCI Express capabilities register, this 26776f8718a3SScott Long * must be a PCI Express device. 26786f8718a3SScott Long */ 26796f8718a3SScott Long sc->bge_flags |= BGE_FLAG_PCIE; 26800aaf1057SPyun YongHyeon sc->bge_expcap = reg; 2681d2b6e9a0SPyun YongHyeon if (pci_get_max_read_req(dev) != 4096) 2682d2b6e9a0SPyun YongHyeon pci_set_max_read_req(dev, 4096); 26836f8718a3SScott Long } else { 26846f8718a3SScott Long /* 26856f8718a3SScott Long * Check if the device is in PCI-X Mode. 26866f8718a3SScott Long * (This bit is not valid on PCI Express controllers.) 26874c0da0ffSGleb Smirnoff */ 26880aaf1057SPyun YongHyeon if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 26890aaf1057SPyun YongHyeon sc->bge_pcixcap = reg; 269090447aadSMarius Strobl if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 26914c0da0ffSGleb Smirnoff BGE_PCISTATE_PCI_BUSMODE) == 0) 2692652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_PCIX; 26936f8718a3SScott Long } 26944c0da0ffSGleb Smirnoff 2695bf6ef57aSJohn Polstra /* 2696fd4d32feSPyun YongHyeon * The 40bit DMA bug applies to the 5714/5715 controllers and is 2697fd4d32feSPyun YongHyeon * not actually a MAC controller bug but an issue with the embedded 2698fd4d32feSPyun YongHyeon * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2699fd4d32feSPyun YongHyeon */ 2700fd4d32feSPyun YongHyeon if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2701fd4d32feSPyun YongHyeon sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2702fd4d32feSPyun YongHyeon /* 2703bf6ef57aSJohn Polstra * Allocate the interrupt, using MSI if possible. These devices 2704bf6ef57aSJohn Polstra * support 8 MSI messages, but only the first one is used in 2705bf6ef57aSJohn Polstra * normal operation. 2706bf6ef57aSJohn Polstra */ 27070aaf1057SPyun YongHyeon rid = 0; 27086a15578dSPyun YongHyeon if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { 27090aaf1057SPyun YongHyeon sc->bge_msicap = reg; 2710bf6ef57aSJohn Polstra if (bge_can_use_msi(sc)) { 2711bf6ef57aSJohn Polstra msicount = pci_msi_count(dev); 2712bf6ef57aSJohn Polstra if (msicount > 1) 2713bf6ef57aSJohn Polstra msicount = 1; 2714bf6ef57aSJohn Polstra } else 2715bf6ef57aSJohn Polstra msicount = 0; 2716bf6ef57aSJohn Polstra if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2717bf6ef57aSJohn Polstra rid = 1; 2718bf6ef57aSJohn Polstra sc->bge_flags |= BGE_FLAG_MSI; 27190aaf1057SPyun YongHyeon } 27200aaf1057SPyun YongHyeon } 2721bf6ef57aSJohn Polstra 2722bf6ef57aSJohn Polstra sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2723bf6ef57aSJohn Polstra RF_SHAREABLE | RF_ACTIVE); 2724bf6ef57aSJohn Polstra 2725bf6ef57aSJohn Polstra if (sc->bge_irq == NULL) { 2726bf6ef57aSJohn Polstra device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2727bf6ef57aSJohn Polstra error = ENXIO; 2728bf6ef57aSJohn Polstra goto fail; 2729bf6ef57aSJohn Polstra } 2730bf6ef57aSJohn Polstra 27314f09c4c7SMarius Strobl if (bootverbose) 27324f09c4c7SMarius Strobl device_printf(dev, 27334f09c4c7SMarius Strobl "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 27344f09c4c7SMarius Strobl sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 27354f09c4c7SMarius Strobl (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 27364f09c4c7SMarius Strobl ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 27374f09c4c7SMarius Strobl 2738bf6ef57aSJohn Polstra BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2739bf6ef57aSJohn Polstra 274095d67482SBill Paul /* Try to reset the chip. */ 27418cb1383cSDoug Ambrisko if (bge_reset(sc)) { 27428cb1383cSDoug Ambrisko device_printf(sc->bge_dev, "chip reset failed\n"); 27438cb1383cSDoug Ambrisko error = ENXIO; 27448cb1383cSDoug Ambrisko goto fail; 27458cb1383cSDoug Ambrisko } 27468cb1383cSDoug Ambrisko 27478cb1383cSDoug Ambrisko sc->bge_asf_mode = 0; 2748f1a7e6d5SScott Long if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2749f1a7e6d5SScott Long == BGE_MAGIC_NUMBER)) { 27508cb1383cSDoug Ambrisko if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 27518cb1383cSDoug Ambrisko & BGE_HWCFG_ASF) { 27528cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_ENABLE; 27538cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_STACKUP; 2754d67eba2fSPyun YongHyeon if (BGE_IS_575X_PLUS(sc)) 27558cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 27568cb1383cSDoug Ambrisko } 27578cb1383cSDoug Ambrisko } 27588cb1383cSDoug Ambrisko 27598cb1383cSDoug Ambrisko /* Try to reset the chip again the nice way. */ 27608cb1383cSDoug Ambrisko bge_stop_fw(sc); 27618cb1383cSDoug Ambrisko bge_sig_pre_reset(sc, BGE_RESET_STOP); 27628cb1383cSDoug Ambrisko if (bge_reset(sc)) { 27638cb1383cSDoug Ambrisko device_printf(sc->bge_dev, "chip reset failed\n"); 27648cb1383cSDoug Ambrisko error = ENXIO; 27658cb1383cSDoug Ambrisko goto fail; 27668cb1383cSDoug Ambrisko } 27678cb1383cSDoug Ambrisko 27688cb1383cSDoug Ambrisko bge_sig_legacy(sc, BGE_RESET_STOP); 27698cb1383cSDoug Ambrisko bge_sig_post_reset(sc, BGE_RESET_STOP); 277095d67482SBill Paul 277195d67482SBill Paul if (bge_chipinit(sc)) { 2772fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "chip initialization failed\n"); 277395d67482SBill Paul error = ENXIO; 277495d67482SBill Paul goto fail; 277595d67482SBill Paul } 277695d67482SBill Paul 277738cc658fSJohn Baldwin error = bge_get_eaddr(sc, eaddr); 277838cc658fSJohn Baldwin if (error) { 277908013fd3SMarius Strobl device_printf(sc->bge_dev, 278008013fd3SMarius Strobl "failed to read station address\n"); 278195d67482SBill Paul error = ENXIO; 278295d67482SBill Paul goto fail; 278395d67482SBill Paul } 278495d67482SBill Paul 2785f41ac2beSBill Paul /* 5705 limits RX return ring to 512 entries. */ 27867ee00338SJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 2787f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2788f41ac2beSBill Paul else 2789f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2790f41ac2beSBill Paul 2791f41ac2beSBill Paul if (bge_dma_alloc(dev)) { 2792fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2793fe806fdaSPyun YongHyeon "failed to allocate DMA resources\n"); 2794f41ac2beSBill Paul error = ENXIO; 2795f41ac2beSBill Paul goto fail; 2796f41ac2beSBill Paul } 2797f41ac2beSBill Paul 279895d67482SBill Paul /* Set default tuneable values. */ 279995d67482SBill Paul sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 280095d67482SBill Paul sc->bge_rx_coal_ticks = 150; 280195d67482SBill Paul sc->bge_tx_coal_ticks = 150; 28026f8718a3SScott Long sc->bge_rx_max_coal_bds = 10; 28036f8718a3SScott Long sc->bge_tx_max_coal_bds = 10; 280495d67482SBill Paul 280595d67482SBill Paul /* Set up ifnet structure */ 2806fc74a9f9SBrooks Davis ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2807fc74a9f9SBrooks Davis if (ifp == NULL) { 2808fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2809fc74a9f9SBrooks Davis error = ENXIO; 2810fc74a9f9SBrooks Davis goto fail; 2811fc74a9f9SBrooks Davis } 281295d67482SBill Paul ifp->if_softc = sc; 28139bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 281495d67482SBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 281595d67482SBill Paul ifp->if_ioctl = bge_ioctl; 281695d67482SBill Paul ifp->if_start = bge_start; 281795d67482SBill Paul ifp->if_init = bge_init; 28184d665c4dSDag-Erling Smørgrav ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 28194d665c4dSDag-Erling Smørgrav IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 28204d665c4dSDag-Erling Smørgrav IFQ_SET_READY(&ifp->if_snd); 282195d67482SBill Paul ifp->if_hwassist = BGE_CSUM_FEATURES; 2822d375e524SGleb Smirnoff ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 28234e35d186SJung-uk Kim IFCAP_VLAN_MTU; 2824ca3f1187SPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2825ca3f1187SPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 282604bde852SPyun YongHyeon ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 2827ca3f1187SPyun YongHyeon } 28284e35d186SJung-uk Kim #ifdef IFCAP_VLAN_HWCSUM 28294e35d186SJung-uk Kim ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 28304e35d186SJung-uk Kim #endif 283195d67482SBill Paul ifp->if_capenable = ifp->if_capabilities; 283275719184SGleb Smirnoff #ifdef DEVICE_POLLING 283375719184SGleb Smirnoff ifp->if_capabilities |= IFCAP_POLLING; 283475719184SGleb Smirnoff #endif 283595d67482SBill Paul 2836a1d52896SBill Paul /* 2837d375e524SGleb Smirnoff * 5700 B0 chips do not support checksumming correctly due 2838d375e524SGleb Smirnoff * to hardware bugs. 2839d375e524SGleb Smirnoff */ 2840d375e524SGleb Smirnoff if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2841d375e524SGleb Smirnoff ifp->if_capabilities &= ~IFCAP_HWCSUM; 28424d3a629cSPyun YongHyeon ifp->if_capenable &= ~IFCAP_HWCSUM; 2843d375e524SGleb Smirnoff ifp->if_hwassist = 0; 2844d375e524SGleb Smirnoff } 2845d375e524SGleb Smirnoff 2846d375e524SGleb Smirnoff /* 2847a1d52896SBill Paul * Figure out what sort of media we have by checking the 284841abcc1bSPaul Saab * hardware config word in the first 32k of NIC internal memory, 284941abcc1bSPaul Saab * or fall back to examining the EEPROM if necessary. 285041abcc1bSPaul Saab * Note: on some BCM5700 cards, this value appears to be unset. 285141abcc1bSPaul Saab * If that's the case, we have to rely on identifying the NIC 285241abcc1bSPaul Saab * by its PCI subsystem ID, as we do below for the SysKonnect 285341abcc1bSPaul Saab * SK-9D41. 2854a1d52896SBill Paul */ 285541abcc1bSPaul Saab if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 285641abcc1bSPaul Saab hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 28575fea260fSMarius Strobl else if ((sc->bge_flags & BGE_FLAG_EADDR) && 28585fea260fSMarius Strobl (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2859f6789fbaSPyun YongHyeon if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2860f6789fbaSPyun YongHyeon sizeof(hwcfg))) { 2861fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2862f6789fbaSPyun YongHyeon error = ENXIO; 2863f6789fbaSPyun YongHyeon goto fail; 2864f6789fbaSPyun YongHyeon } 286541abcc1bSPaul Saab hwcfg = ntohl(hwcfg); 286641abcc1bSPaul Saab } 286741abcc1bSPaul Saab 286895d67482SBill Paul /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2869ea3b4127SPyun YongHyeon if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 2870ea3b4127SPyun YongHyeon SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2871ea3b4127SPyun YongHyeon if (BGE_IS_5714_FAMILY(sc)) 2872ea3b4127SPyun YongHyeon sc->bge_flags |= BGE_FLAG_MII_SERDES; 2873ea3b4127SPyun YongHyeon else 2874652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_TBI; 2875ea3b4127SPyun YongHyeon } 287695d67482SBill Paul 2877652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 28780c8aa4eaSJung-uk Kim ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 28790c8aa4eaSJung-uk Kim bge_ifmedia_sts); 28800c8aa4eaSJung-uk Kim ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 28816098821cSJung-uk Kim ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 28826098821cSJung-uk Kim 0, NULL); 288395d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 288495d67482SBill Paul ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2885da3003f0SBill Paul sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 288695d67482SBill Paul } else { 288795d67482SBill Paul /* 28888cb1383cSDoug Ambrisko * Do transceiver setup and tell the firmware the 28898cb1383cSDoug Ambrisko * driver is down so we can try to get access the 28908cb1383cSDoug Ambrisko * probe if ASF is running. Retry a couple of times 28918cb1383cSDoug Ambrisko * if we get a conflict with the ASF firmware accessing 28928cb1383cSDoug Ambrisko * the PHY. 289395d67482SBill Paul */ 28944012d104SMarius Strobl trys = 0; 28958cb1383cSDoug Ambrisko BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 28968cb1383cSDoug Ambrisko again: 28978cb1383cSDoug Ambrisko bge_asf_driver_up(sc); 28988cb1383cSDoug Ambrisko 289995d67482SBill Paul if (mii_phy_probe(dev, &sc->bge_miibus, 290095d67482SBill Paul bge_ifmedia_upd, bge_ifmedia_sts)) { 29018cb1383cSDoug Ambrisko if (trys++ < 4) { 29028cb1383cSDoug Ambrisko device_printf(sc->bge_dev, "Try again\n"); 29034e35d186SJung-uk Kim bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 29044e35d186SJung-uk Kim BMCR_RESET); 29058cb1383cSDoug Ambrisko goto again; 29068cb1383cSDoug Ambrisko } 29078cb1383cSDoug Ambrisko 2908fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "MII without any PHY!\n"); 290995d67482SBill Paul error = ENXIO; 291095d67482SBill Paul goto fail; 291195d67482SBill Paul } 29128cb1383cSDoug Ambrisko 29138cb1383cSDoug Ambrisko /* 29148cb1383cSDoug Ambrisko * Now tell the firmware we are going up after probing the PHY 29158cb1383cSDoug Ambrisko */ 29168cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 29178cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 291895d67482SBill Paul } 291995d67482SBill Paul 292095d67482SBill Paul /* 2921e255b776SJohn Polstra * When using the BCM5701 in PCI-X mode, data corruption has 2922e255b776SJohn Polstra * been observed in the first few bytes of some received packets. 2923e255b776SJohn Polstra * Aligning the packet buffer in memory eliminates the corruption. 2924e255b776SJohn Polstra * Unfortunately, this misaligns the packet payloads. On platforms 2925e255b776SJohn Polstra * which do not support unaligned accesses, we will realign the 2926e255b776SJohn Polstra * payloads by copying the received packets. 2927e255b776SJohn Polstra */ 2928652ae483SGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2929652ae483SGleb Smirnoff sc->bge_flags & BGE_FLAG_PCIX) 2930652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2931e255b776SJohn Polstra 2932e255b776SJohn Polstra /* 293395d67482SBill Paul * Call MI attach routine. 293495d67482SBill Paul */ 2935fc74a9f9SBrooks Davis ether_ifattach(ifp, eaddr); 2936b74e67fbSGleb Smirnoff callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 29370f9bd73bSSam Leffler 293861ccb9daSPyun YongHyeon /* Tell upper layer we support long frames. */ 293961ccb9daSPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 294061ccb9daSPyun YongHyeon 29410f9bd73bSSam Leffler /* 29420f9bd73bSSam Leffler * Hookup IRQ last. 29430f9bd73bSSam Leffler */ 29444e35d186SJung-uk Kim #if __FreeBSD_version > 700030 2945dfe0df9aSPyun YongHyeon if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 2946dfe0df9aSPyun YongHyeon /* Take advantage of single-shot MSI. */ 29477e6acdf1SPyun YongHyeon CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 29487e6acdf1SPyun YongHyeon ~BGE_MSIMODE_ONE_SHOT_DISABLE); 2949dfe0df9aSPyun YongHyeon sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 2950dfe0df9aSPyun YongHyeon taskqueue_thread_enqueue, &sc->bge_tq); 2951dfe0df9aSPyun YongHyeon if (sc->bge_tq == NULL) { 2952dfe0df9aSPyun YongHyeon device_printf(dev, "could not create taskqueue.\n"); 2953dfe0df9aSPyun YongHyeon ether_ifdetach(ifp); 2954dfe0df9aSPyun YongHyeon error = ENXIO; 2955dfe0df9aSPyun YongHyeon goto fail; 2956dfe0df9aSPyun YongHyeon } 2957dfe0df9aSPyun YongHyeon taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 2958dfe0df9aSPyun YongHyeon device_get_nameunit(sc->bge_dev)); 2959dfe0df9aSPyun YongHyeon error = bus_setup_intr(dev, sc->bge_irq, 2960dfe0df9aSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 2961dfe0df9aSPyun YongHyeon &sc->bge_intrhand); 2962dfe0df9aSPyun YongHyeon if (error) 2963dfe0df9aSPyun YongHyeon ether_ifdetach(ifp); 2964dfe0df9aSPyun YongHyeon } else 2965dfe0df9aSPyun YongHyeon error = bus_setup_intr(dev, sc->bge_irq, 2966dfe0df9aSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 2967dfe0df9aSPyun YongHyeon &sc->bge_intrhand); 29684e35d186SJung-uk Kim #else 29694e35d186SJung-uk Kim error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 29704e35d186SJung-uk Kim bge_intr, sc, &sc->bge_intrhand); 29714e35d186SJung-uk Kim #endif 29720f9bd73bSSam Leffler 29730f9bd73bSSam Leffler if (error) { 2974fc74a9f9SBrooks Davis bge_detach(dev); 2975fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "couldn't set up irq\n"); 29760f9bd73bSSam Leffler } 297795d67482SBill Paul 29786f8718a3SScott Long bge_add_sysctls(sc); 29796f8718a3SScott Long 298008013fd3SMarius Strobl return (0); 298108013fd3SMarius Strobl 298295d67482SBill Paul fail: 298308013fd3SMarius Strobl bge_release_resources(sc); 298408013fd3SMarius Strobl 298595d67482SBill Paul return (error); 298695d67482SBill Paul } 298795d67482SBill Paul 298895d67482SBill Paul static int 29893f74909aSGleb Smirnoff bge_detach(device_t dev) 299095d67482SBill Paul { 299195d67482SBill Paul struct bge_softc *sc; 299295d67482SBill Paul struct ifnet *ifp; 299395d67482SBill Paul 299495d67482SBill Paul sc = device_get_softc(dev); 2995fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 299695d67482SBill Paul 299775719184SGleb Smirnoff #ifdef DEVICE_POLLING 299875719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 299975719184SGleb Smirnoff ether_poll_deregister(ifp); 300075719184SGleb Smirnoff #endif 300175719184SGleb Smirnoff 30020f9bd73bSSam Leffler BGE_LOCK(sc); 300395d67482SBill Paul bge_stop(sc); 300495d67482SBill Paul bge_reset(sc); 30050f9bd73bSSam Leffler BGE_UNLOCK(sc); 30060f9bd73bSSam Leffler 30075dda8085SOleg Bulyzhin callout_drain(&sc->bge_stat_ch); 30085dda8085SOleg Bulyzhin 3009dfe0df9aSPyun YongHyeon if (sc->bge_tq) 3010dfe0df9aSPyun YongHyeon taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 30110f9bd73bSSam Leffler ether_ifdetach(ifp); 301295d67482SBill Paul 3013652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 301495d67482SBill Paul ifmedia_removeall(&sc->bge_ifmedia); 301595d67482SBill Paul } else { 301695d67482SBill Paul bus_generic_detach(dev); 301795d67482SBill Paul device_delete_child(dev, sc->bge_miibus); 301895d67482SBill Paul } 301995d67482SBill Paul 302095d67482SBill Paul bge_release_resources(sc); 302195d67482SBill Paul 302295d67482SBill Paul return (0); 302395d67482SBill Paul } 302495d67482SBill Paul 302595d67482SBill Paul static void 30263f74909aSGleb Smirnoff bge_release_resources(struct bge_softc *sc) 302795d67482SBill Paul { 302895d67482SBill Paul device_t dev; 302995d67482SBill Paul 303095d67482SBill Paul dev = sc->bge_dev; 303195d67482SBill Paul 3032dfe0df9aSPyun YongHyeon if (sc->bge_tq != NULL) 3033dfe0df9aSPyun YongHyeon taskqueue_free(sc->bge_tq); 3034dfe0df9aSPyun YongHyeon 303595d67482SBill Paul if (sc->bge_intrhand != NULL) 303695d67482SBill Paul bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 303795d67482SBill Paul 303895d67482SBill Paul if (sc->bge_irq != NULL) 3039724bd939SJohn Polstra bus_release_resource(dev, SYS_RES_IRQ, 3040724bd939SJohn Polstra sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3041724bd939SJohn Polstra 3042724bd939SJohn Polstra if (sc->bge_flags & BGE_FLAG_MSI) 3043724bd939SJohn Polstra pci_release_msi(dev); 304495d67482SBill Paul 304595d67482SBill Paul if (sc->bge_res != NULL) 304695d67482SBill Paul bus_release_resource(dev, SYS_RES_MEMORY, 3047*736b9319SPyun YongHyeon PCIR_BAR(0), sc->bge_res); 304895d67482SBill Paul 3049ad61f896SRuslan Ermilov if (sc->bge_ifp != NULL) 3050ad61f896SRuslan Ermilov if_free(sc->bge_ifp); 3051ad61f896SRuslan Ermilov 3052f41ac2beSBill Paul bge_dma_free(sc); 305395d67482SBill Paul 30540f9bd73bSSam Leffler if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 30550f9bd73bSSam Leffler BGE_LOCK_DESTROY(sc); 305695d67482SBill Paul } 305795d67482SBill Paul 30588cb1383cSDoug Ambrisko static int 30593f74909aSGleb Smirnoff bge_reset(struct bge_softc *sc) 306095d67482SBill Paul { 306195d67482SBill Paul device_t dev; 30625fea260fSMarius Strobl uint32_t cachesize, command, pcistate, reset, val; 30636f8718a3SScott Long void (*write_op)(struct bge_softc *, int, int); 30640aaf1057SPyun YongHyeon uint16_t devctl; 30655fea260fSMarius Strobl int i; 306695d67482SBill Paul 306795d67482SBill Paul dev = sc->bge_dev; 306895d67482SBill Paul 306938cc658fSJohn Baldwin if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 307038cc658fSJohn Baldwin (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 30716f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIE) 30726f8718a3SScott Long write_op = bge_writemem_direct; 30736f8718a3SScott Long else 30746f8718a3SScott Long write_op = bge_writemem_ind; 30759ba784dbSScott Long } else 30766f8718a3SScott Long write_op = bge_writereg_ind; 30776f8718a3SScott Long 307895d67482SBill Paul /* Save some important PCI state. */ 307995d67482SBill Paul cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 308095d67482SBill Paul command = pci_read_config(dev, BGE_PCI_CMD, 4); 308195d67482SBill Paul pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 308295d67482SBill Paul 308395d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 308495d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3085e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 308695d67482SBill Paul 30876f8718a3SScott Long /* Disable fastboot on controllers that support it. */ 30886f8718a3SScott Long if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3089a5779553SStanislav Sedov BGE_IS_5755_PLUS(sc)) { 30906f8718a3SScott Long if (bootverbose) 3091333704a3SPyun YongHyeon device_printf(dev, "Disabling fastboot\n"); 30926f8718a3SScott Long CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 30936f8718a3SScott Long } 30946f8718a3SScott Long 30956f8718a3SScott Long /* 30966f8718a3SScott Long * Write the magic number to SRAM at offset 0xB50. 30976f8718a3SScott Long * When firmware finishes its initialization it will 30986f8718a3SScott Long * write ~BGE_MAGIC_NUMBER to the same location. 30996f8718a3SScott Long */ 31006f8718a3SScott Long bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 31016f8718a3SScott Long 31020c8aa4eaSJung-uk Kim reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3103e53d81eeSPaul Saab 3104e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 3105652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 31060c8aa4eaSJung-uk Kim if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 31070c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, 0x7E2C, 0x20); 3108e53d81eeSPaul Saab if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3109e53d81eeSPaul Saab /* Prevent PCIE link training during global reset */ 31100c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 31110c8aa4eaSJung-uk Kim reset |= 1 << 29; 3112e53d81eeSPaul Saab } 3113e53d81eeSPaul Saab } 3114e53d81eeSPaul Saab 311521c9e407SDavid Christensen /* 31166f8718a3SScott Long * Set GPHY Power Down Override to leave GPHY 31176f8718a3SScott Long * powered up in D0 uninitialized. 31186f8718a3SScott Long */ 31195345bad0SScott Long if (BGE_IS_5705_PLUS(sc)) 31206f8718a3SScott Long reset |= 0x04000000; 31216f8718a3SScott Long 312295d67482SBill Paul /* Issue global reset */ 31236f8718a3SScott Long write_op(sc, BGE_MISC_CFG, reset); 312495d67482SBill Paul 312538cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 31265fea260fSMarius Strobl val = CSR_READ_4(sc, BGE_VCPU_STATUS); 312738cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_VCPU_STATUS, 31285fea260fSMarius Strobl val | BGE_VCPU_STATUS_DRV_RESET); 31295fea260fSMarius Strobl val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 313038cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 31315fea260fSMarius Strobl val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 313238cc658fSJohn Baldwin } 313338cc658fSJohn Baldwin 313495d67482SBill Paul DELAY(1000); 313595d67482SBill Paul 3136e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 3137652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 3138e53d81eeSPaul Saab if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3139e53d81eeSPaul Saab DELAY(500000); /* wait for link training to complete */ 31405fea260fSMarius Strobl val = pci_read_config(dev, 0xC4, 4); 31415fea260fSMarius Strobl pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3142e53d81eeSPaul Saab } 31430aaf1057SPyun YongHyeon devctl = pci_read_config(dev, 31440aaf1057SPyun YongHyeon sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 31450aaf1057SPyun YongHyeon /* Clear enable no snoop and disable relaxed ordering. */ 31469a6e301dSPyun YongHyeon devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 31479a6e301dSPyun YongHyeon PCIM_EXP_CTL_NOSNOOP_ENABLE); 31480aaf1057SPyun YongHyeon /* Set PCIE max payload size to 128. */ 31490aaf1057SPyun YongHyeon devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 31500aaf1057SPyun YongHyeon pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 31510aaf1057SPyun YongHyeon devctl, 2); 31520aaf1057SPyun YongHyeon /* Clear error status. */ 31530aaf1057SPyun YongHyeon pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 31549a6e301dSPyun YongHyeon PCIM_EXP_STA_CORRECTABLE_ERROR | 31559a6e301dSPyun YongHyeon PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 31569a6e301dSPyun YongHyeon PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3157e53d81eeSPaul Saab } 3158e53d81eeSPaul Saab 31593f74909aSGleb Smirnoff /* Reset some of the PCI state that got zapped by reset. */ 316095d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 316195d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3162e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 316395d67482SBill Paul pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 316495d67482SBill Paul pci_write_config(dev, BGE_PCI_CMD, command, 4); 31650c8aa4eaSJung-uk Kim write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3166cbb2b2feSPyun YongHyeon /* 3167cbb2b2feSPyun YongHyeon * Disable PCI-X relaxed ordering to ensure status block update 3168fa8b4d63SPyun YongHyeon * comes first then packet buffer DMA. Otherwise driver may 3169cbb2b2feSPyun YongHyeon * read stale status block. 3170cbb2b2feSPyun YongHyeon */ 3171cbb2b2feSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_PCIX) { 3172cbb2b2feSPyun YongHyeon devctl = pci_read_config(dev, 3173cbb2b2feSPyun YongHyeon sc->bge_pcixcap + PCIXR_COMMAND, 2); 3174cbb2b2feSPyun YongHyeon devctl &= ~PCIXM_COMMAND_ERO; 3175cbb2b2feSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3176cbb2b2feSPyun YongHyeon devctl &= ~PCIXM_COMMAND_MAX_READ; 3177cbb2b2feSPyun YongHyeon devctl |= PCIXM_COMMAND_MAX_READ_2048; 3178cbb2b2feSPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3179cbb2b2feSPyun YongHyeon devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3180cbb2b2feSPyun YongHyeon PCIXM_COMMAND_MAX_READ); 3181cbb2b2feSPyun YongHyeon devctl |= PCIXM_COMMAND_MAX_READ_2048; 3182cbb2b2feSPyun YongHyeon } 3183cbb2b2feSPyun YongHyeon pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3184cbb2b2feSPyun YongHyeon devctl, 2); 3185cbb2b2feSPyun YongHyeon } 3186bf6ef57aSJohn Polstra /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 31874c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 3188bf6ef57aSJohn Polstra /* This chip disables MSI on reset. */ 3189bf6ef57aSJohn Polstra if (sc->bge_flags & BGE_FLAG_MSI) { 31900aaf1057SPyun YongHyeon val = pci_read_config(dev, 31910aaf1057SPyun YongHyeon sc->bge_msicap + PCIR_MSI_CTRL, 2); 31920aaf1057SPyun YongHyeon pci_write_config(dev, 31930aaf1057SPyun YongHyeon sc->bge_msicap + PCIR_MSI_CTRL, 3194bf6ef57aSJohn Polstra val | PCIM_MSICTRL_MSI_ENABLE, 2); 3195bf6ef57aSJohn Polstra val = CSR_READ_4(sc, BGE_MSI_MODE); 3196bf6ef57aSJohn Polstra CSR_WRITE_4(sc, BGE_MSI_MODE, 3197bf6ef57aSJohn Polstra val | BGE_MSIMODE_ENABLE); 3198bf6ef57aSJohn Polstra } 31994c0da0ffSGleb Smirnoff val = CSR_READ_4(sc, BGE_MARB_MODE); 32004c0da0ffSGleb Smirnoff CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 32014c0da0ffSGleb Smirnoff } else 3202a7b0c314SPaul Saab CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3203a7b0c314SPaul Saab 320438cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 320538cc658fSJohn Baldwin for (i = 0; i < BGE_TIMEOUT; i++) { 320638cc658fSJohn Baldwin val = CSR_READ_4(sc, BGE_VCPU_STATUS); 320738cc658fSJohn Baldwin if (val & BGE_VCPU_STATUS_INIT_DONE) 320838cc658fSJohn Baldwin break; 320938cc658fSJohn Baldwin DELAY(100); 321038cc658fSJohn Baldwin } 321138cc658fSJohn Baldwin if (i == BGE_TIMEOUT) { 3212333704a3SPyun YongHyeon device_printf(dev, "reset timed out\n"); 321338cc658fSJohn Baldwin return (1); 321438cc658fSJohn Baldwin } 321538cc658fSJohn Baldwin } else { 321695d67482SBill Paul /* 32176f8718a3SScott Long * Poll until we see the 1's complement of the magic number. 321808013fd3SMarius Strobl * This indicates that the firmware initialization is complete. 32195fea260fSMarius Strobl * We expect this to fail if no chip containing the Ethernet 32205fea260fSMarius Strobl * address is fitted though. 322195d67482SBill Paul */ 322295d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 3223d5d23857SJung-uk Kim DELAY(10); 322495d67482SBill Paul val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 322595d67482SBill Paul if (val == ~BGE_MAGIC_NUMBER) 322695d67482SBill Paul break; 322795d67482SBill Paul } 322895d67482SBill Paul 32295fea260fSMarius Strobl if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3230333704a3SPyun YongHyeon device_printf(dev, 3231333704a3SPyun YongHyeon "firmware handshake timed out, found 0x%08x\n", 3232333704a3SPyun YongHyeon val); 323338cc658fSJohn Baldwin } 323495d67482SBill Paul 323595d67482SBill Paul /* 323695d67482SBill Paul * XXX Wait for the value of the PCISTATE register to 323795d67482SBill Paul * return to its original pre-reset state. This is a 323895d67482SBill Paul * fairly good indicator of reset completion. If we don't 323995d67482SBill Paul * wait for the reset to fully complete, trying to read 324095d67482SBill Paul * from the device's non-PCI registers may yield garbage 324195d67482SBill Paul * results. 324295d67482SBill Paul */ 324395d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 324495d67482SBill Paul if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 324595d67482SBill Paul break; 324695d67482SBill Paul DELAY(10); 324795d67482SBill Paul } 324895d67482SBill Paul 32496f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIE) { 32500c8aa4eaSJung-uk Kim reset = bge_readmem_ind(sc, 0x7C00); 32510c8aa4eaSJung-uk Kim bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 32526f8718a3SScott Long } 32536f8718a3SScott Long 32543f74909aSGleb Smirnoff /* Fix up byte swapping. */ 3255e907febfSPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 325695d67482SBill Paul BGE_MODECTL_BYTESWAP_DATA); 325795d67482SBill Paul 32588cb1383cSDoug Ambrisko /* Tell the ASF firmware we are up */ 32598cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 32608cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 32618cb1383cSDoug Ambrisko 326295d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 326395d67482SBill Paul 3264da3003f0SBill Paul /* 3265da3003f0SBill Paul * The 5704 in TBI mode apparently needs some special 3266da3003f0SBill Paul * adjustment to insure the SERDES drive level is set 3267da3003f0SBill Paul * to 1.2V. 3268da3003f0SBill Paul */ 3269652ae483SGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3270652ae483SGleb Smirnoff sc->bge_flags & BGE_FLAG_TBI) { 32715fea260fSMarius Strobl val = CSR_READ_4(sc, BGE_SERDES_CFG); 32725fea260fSMarius Strobl val = (val & ~0xFFF) | 0x880; 32735fea260fSMarius Strobl CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3274da3003f0SBill Paul } 3275da3003f0SBill Paul 3276e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 3277652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE && 3278652ae483SGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 32795fea260fSMarius Strobl val = CSR_READ_4(sc, 0x7C00); 32805fea260fSMarius Strobl CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3281e53d81eeSPaul Saab } 328295d67482SBill Paul DELAY(10000); 32838cb1383cSDoug Ambrisko 32848cb1383cSDoug Ambrisko return (0); 328595d67482SBill Paul } 328695d67482SBill Paul 3287e0b7b101SPyun YongHyeon static __inline void 3288e0b7b101SPyun YongHyeon bge_rxreuse_std(struct bge_softc *sc, int i) 3289e0b7b101SPyun YongHyeon { 3290e0b7b101SPyun YongHyeon struct bge_rx_bd *r; 3291e0b7b101SPyun YongHyeon 3292e0b7b101SPyun YongHyeon r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3293e0b7b101SPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_END; 3294e0b7b101SPyun YongHyeon r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3295e0b7b101SPyun YongHyeon r->bge_idx = i; 3296e0b7b101SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3297e0b7b101SPyun YongHyeon } 3298e0b7b101SPyun YongHyeon 3299e0b7b101SPyun YongHyeon static __inline void 3300e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3301e0b7b101SPyun YongHyeon { 3302e0b7b101SPyun YongHyeon struct bge_extrx_bd *r; 3303e0b7b101SPyun YongHyeon 3304e0b7b101SPyun YongHyeon r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3305e0b7b101SPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3306e0b7b101SPyun YongHyeon r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3307e0b7b101SPyun YongHyeon r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3308e0b7b101SPyun YongHyeon r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3309e0b7b101SPyun YongHyeon r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3310e0b7b101SPyun YongHyeon r->bge_idx = i; 3311e0b7b101SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3312e0b7b101SPyun YongHyeon } 3313e0b7b101SPyun YongHyeon 331495d67482SBill Paul /* 331595d67482SBill Paul * Frame reception handling. This is called if there's a frame 331695d67482SBill Paul * on the receive return list. 331795d67482SBill Paul * 331895d67482SBill Paul * Note: we have to be able to handle two possibilities here: 33191be6acb7SGleb Smirnoff * 1) the frame is from the jumbo receive ring 332095d67482SBill Paul * 2) the frame is from the standard receive ring 332195d67482SBill Paul */ 332295d67482SBill Paul 33231abcdbd1SAttilio Rao static int 3324dfe0df9aSPyun YongHyeon bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 332595d67482SBill Paul { 332695d67482SBill Paul struct ifnet *ifp; 33271abcdbd1SAttilio Rao int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3328b9c05fa5SPyun YongHyeon uint16_t rx_cons; 332995d67482SBill Paul 33307f21e273SStanislav Sedov rx_cons = sc->bge_rx_saved_considx; 33310f9bd73bSSam Leffler 33323f74909aSGleb Smirnoff /* Nothing to do. */ 33337f21e273SStanislav Sedov if (rx_cons == rx_prod) 33341abcdbd1SAttilio Rao return (rx_npkts); 3335cfcb5025SOleg Bulyzhin 3336fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 333795d67482SBill Paul 3338f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3339e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3340f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 334115eda801SStanislav Sedov sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3342c215fd77SPyun YongHyeon if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3343c215fd77SPyun YongHyeon (MCLBYTES - ETHER_ALIGN)) 3344f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 334515eda801SStanislav Sedov sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3346f41ac2beSBill Paul 33477f21e273SStanislav Sedov while (rx_cons != rx_prod) { 334895d67482SBill Paul struct bge_rx_bd *cur_rx; 33493f74909aSGleb Smirnoff uint32_t rxidx; 335095d67482SBill Paul struct mbuf *m = NULL; 33513f74909aSGleb Smirnoff uint16_t vlan_tag = 0; 335295d67482SBill Paul int have_tag = 0; 335395d67482SBill Paul 335475719184SGleb Smirnoff #ifdef DEVICE_POLLING 335575719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 335675719184SGleb Smirnoff if (sc->rxcycles <= 0) 335775719184SGleb Smirnoff break; 335875719184SGleb Smirnoff sc->rxcycles--; 335975719184SGleb Smirnoff } 336075719184SGleb Smirnoff #endif 336175719184SGleb Smirnoff 33627f21e273SStanislav Sedov cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 336395d67482SBill Paul 336495d67482SBill Paul rxidx = cur_rx->bge_idx; 33657f21e273SStanislav Sedov BGE_INC(rx_cons, sc->bge_return_ring_cnt); 336695d67482SBill Paul 3367cb2eacc7SYaroslav Tykhiy if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3368cb2eacc7SYaroslav Tykhiy cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 336995d67482SBill Paul have_tag = 1; 337095d67482SBill Paul vlan_tag = cur_rx->bge_vlan_tag; 337195d67482SBill Paul } 337295d67482SBill Paul 337395d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 337495d67482SBill Paul jumbocnt++; 3375943787f3SPyun YongHyeon m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 337695d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3377e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(sc, rxidx); 337895d67482SBill Paul continue; 337995d67482SBill Paul } 3380943787f3SPyun YongHyeon if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3381e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(sc, rxidx); 3382943787f3SPyun YongHyeon ifp->if_iqdrops++; 338395d67482SBill Paul continue; 338495d67482SBill Paul } 338503e78bd0SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 338695d67482SBill Paul } else { 338795d67482SBill Paul stdcnt++; 3388e0b7b101SPyun YongHyeon m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 338995d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3390e0b7b101SPyun YongHyeon bge_rxreuse_std(sc, rxidx); 339195d67482SBill Paul continue; 339295d67482SBill Paul } 3393943787f3SPyun YongHyeon if (bge_newbuf_std(sc, rxidx) != 0) { 3394e0b7b101SPyun YongHyeon bge_rxreuse_std(sc, rxidx); 3395943787f3SPyun YongHyeon ifp->if_iqdrops++; 339695d67482SBill Paul continue; 339795d67482SBill Paul } 339803e78bd0SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 339995d67482SBill Paul } 340095d67482SBill Paul 340195d67482SBill Paul ifp->if_ipackets++; 3402e65bed95SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 3403e255b776SJohn Polstra /* 3404e65bed95SPyun YongHyeon * For architectures with strict alignment we must make sure 3405e65bed95SPyun YongHyeon * the payload is aligned. 3406e255b776SJohn Polstra */ 3407652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3408e255b776SJohn Polstra bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3409e255b776SJohn Polstra cur_rx->bge_len); 3410e255b776SJohn Polstra m->m_data += ETHER_ALIGN; 3411e255b776SJohn Polstra } 3412e255b776SJohn Polstra #endif 3413473851baSPaul Saab m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 341495d67482SBill Paul m->m_pkthdr.rcvif = ifp; 341595d67482SBill Paul 3416b874fdd4SYaroslav Tykhiy if (ifp->if_capenable & IFCAP_RXCSUM) { 341778178cd1SGleb Smirnoff if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 341895d67482SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 34190c8aa4eaSJung-uk Kim if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 34200c8aa4eaSJung-uk Kim m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 342178178cd1SGleb Smirnoff } 3422d375e524SGleb Smirnoff if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3423d375e524SGleb Smirnoff m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 342495d67482SBill Paul m->m_pkthdr.csum_data = 342595d67482SBill Paul cur_rx->bge_tcp_udp_csum; 3426ee7ef91cSOleg Bulyzhin m->m_pkthdr.csum_flags |= 3427ee7ef91cSOleg Bulyzhin CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 342895d67482SBill Paul } 342995d67482SBill Paul } 343095d67482SBill Paul 343195d67482SBill Paul /* 3432673d9191SSam Leffler * If we received a packet with a vlan tag, 3433673d9191SSam Leffler * attach that information to the packet. 343495d67482SBill Paul */ 3435d147662cSGleb Smirnoff if (have_tag) { 34364e35d186SJung-uk Kim #if __FreeBSD_version > 700022 343778ba57b9SAndre Oppermann m->m_pkthdr.ether_vtag = vlan_tag; 343878ba57b9SAndre Oppermann m->m_flags |= M_VLANTAG; 34394e35d186SJung-uk Kim #else 34404e35d186SJung-uk Kim VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 34414e35d186SJung-uk Kim if (m == NULL) 34424e35d186SJung-uk Kim continue; 34434e35d186SJung-uk Kim #endif 3444d147662cSGleb Smirnoff } 344595d67482SBill Paul 3446dfe0df9aSPyun YongHyeon if (holdlck != 0) { 34470f9bd73bSSam Leffler BGE_UNLOCK(sc); 3448673d9191SSam Leffler (*ifp->if_input)(ifp, m); 34490f9bd73bSSam Leffler BGE_LOCK(sc); 3450dfe0df9aSPyun YongHyeon } else 3451dfe0df9aSPyun YongHyeon (*ifp->if_input)(ifp, m); 3452d4da719cSAttilio Rao rx_npkts++; 345325e13e68SXin LI 345425e13e68SXin LI if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 34558cf7d13dSAttilio Rao return (rx_npkts); 345695d67482SBill Paul } 345795d67482SBill Paul 345815eda801SStanislav Sedov bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 345915eda801SStanislav Sedov sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3460e65bed95SPyun YongHyeon if (stdcnt > 0) 3461f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3462e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 34634c0da0ffSGleb Smirnoff 3464c215fd77SPyun YongHyeon if (jumbocnt > 0) 3465f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 34664c0da0ffSGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3467f41ac2beSBill Paul 34687f21e273SStanislav Sedov sc->bge_rx_saved_considx = rx_cons; 346938cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 347095d67482SBill Paul if (stdcnt) 347138cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 347295d67482SBill Paul if (jumbocnt) 347338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3474f5a034f9SPyun YongHyeon #ifdef notyet 3475f5a034f9SPyun YongHyeon /* 3476f5a034f9SPyun YongHyeon * This register wraps very quickly under heavy packet drops. 3477f5a034f9SPyun YongHyeon * If you need correct statistics, you can enable this check. 3478f5a034f9SPyun YongHyeon */ 3479f5a034f9SPyun YongHyeon if (BGE_IS_5705_PLUS(sc)) 3480f5a034f9SPyun YongHyeon ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3481f5a034f9SPyun YongHyeon #endif 34821abcdbd1SAttilio Rao return (rx_npkts); 348395d67482SBill Paul } 348495d67482SBill Paul 348595d67482SBill Paul static void 3486b9c05fa5SPyun YongHyeon bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 348795d67482SBill Paul { 348895d67482SBill Paul struct bge_tx_bd *cur_tx = NULL; 348995d67482SBill Paul struct ifnet *ifp; 349095d67482SBill Paul 34910f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 34920f9bd73bSSam Leffler 34933f74909aSGleb Smirnoff /* Nothing to do. */ 3494b9c05fa5SPyun YongHyeon if (sc->bge_tx_saved_considx == tx_cons) 3495cfcb5025SOleg Bulyzhin return; 3496cfcb5025SOleg Bulyzhin 3497fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 349895d67482SBill Paul 3499e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 35005c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 350195d67482SBill Paul /* 350295d67482SBill Paul * Go through our tx ring and free mbufs for those 350395d67482SBill Paul * frames that have been sent. 350495d67482SBill Paul */ 3505b9c05fa5SPyun YongHyeon while (sc->bge_tx_saved_considx != tx_cons) { 35063f74909aSGleb Smirnoff uint32_t idx = 0; 350795d67482SBill Paul 350895d67482SBill Paul idx = sc->bge_tx_saved_considx; 3509f41ac2beSBill Paul cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 351095d67482SBill Paul if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 351195d67482SBill Paul ifp->if_opackets++; 351295d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 35130ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3514e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[idx], 3515e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 35160ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3517f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[idx]); 3518e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3519e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[idx] = NULL; 352095d67482SBill Paul } 352195d67482SBill Paul sc->bge_txcnt--; 352295d67482SBill Paul BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 352395d67482SBill Paul } 352495d67482SBill Paul 352595d67482SBill Paul if (cur_tx != NULL) 352613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 35275b01e77cSBruce Evans if (sc->bge_txcnt == 0) 35285b01e77cSBruce Evans sc->bge_timer = 0; 352995d67482SBill Paul } 353095d67482SBill Paul 353175719184SGleb Smirnoff #ifdef DEVICE_POLLING 35321abcdbd1SAttilio Rao static int 353375719184SGleb Smirnoff bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 353475719184SGleb Smirnoff { 353575719184SGleb Smirnoff struct bge_softc *sc = ifp->if_softc; 3536b9c05fa5SPyun YongHyeon uint16_t rx_prod, tx_cons; 3537366454f2SOleg Bulyzhin uint32_t statusword; 35381abcdbd1SAttilio Rao int rx_npkts = 0; 353975719184SGleb Smirnoff 35403f74909aSGleb Smirnoff BGE_LOCK(sc); 35413f74909aSGleb Smirnoff if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 35423f74909aSGleb Smirnoff BGE_UNLOCK(sc); 35431abcdbd1SAttilio Rao return (rx_npkts); 35443f74909aSGleb Smirnoff } 354575719184SGleb Smirnoff 3546dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3547b9c05fa5SPyun YongHyeon sc->bge_cdata.bge_status_map, 3548b9c05fa5SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3549b9c05fa5SPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3550b9c05fa5SPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3551dab5cd05SOleg Bulyzhin 35523f74909aSGleb Smirnoff statusword = atomic_readandclear_32( 35533f74909aSGleb Smirnoff &sc->bge_ldata.bge_status_block->bge_status); 3554dab5cd05SOleg Bulyzhin 3555dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3556b9c05fa5SPyun YongHyeon sc->bge_cdata.bge_status_map, 3557b9c05fa5SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3558366454f2SOleg Bulyzhin 35590c8aa4eaSJung-uk Kim /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3560366454f2SOleg Bulyzhin if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3561366454f2SOleg Bulyzhin sc->bge_link_evt++; 3562366454f2SOleg Bulyzhin 3563366454f2SOleg Bulyzhin if (cmd == POLL_AND_CHECK_STATUS) 3564366454f2SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 35654c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3566652ae483SGleb Smirnoff sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3567366454f2SOleg Bulyzhin bge_link_upd(sc); 3568366454f2SOleg Bulyzhin 3569366454f2SOleg Bulyzhin sc->rxcycles = count; 3570dfe0df9aSPyun YongHyeon rx_npkts = bge_rxeof(sc, rx_prod, 1); 357125e13e68SXin LI if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 357225e13e68SXin LI BGE_UNLOCK(sc); 35738cf7d13dSAttilio Rao return (rx_npkts); 357425e13e68SXin LI } 3575b9c05fa5SPyun YongHyeon bge_txeof(sc, tx_cons); 3576366454f2SOleg Bulyzhin if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3577366454f2SOleg Bulyzhin bge_start_locked(ifp); 35783f74909aSGleb Smirnoff 35793f74909aSGleb Smirnoff BGE_UNLOCK(sc); 35801abcdbd1SAttilio Rao return (rx_npkts); 358175719184SGleb Smirnoff } 358275719184SGleb Smirnoff #endif /* DEVICE_POLLING */ 358375719184SGleb Smirnoff 3584dfe0df9aSPyun YongHyeon static int 3585dfe0df9aSPyun YongHyeon bge_msi_intr(void *arg) 3586dfe0df9aSPyun YongHyeon { 3587dfe0df9aSPyun YongHyeon struct bge_softc *sc; 3588dfe0df9aSPyun YongHyeon 3589dfe0df9aSPyun YongHyeon sc = (struct bge_softc *)arg; 3590dfe0df9aSPyun YongHyeon /* 3591dfe0df9aSPyun YongHyeon * This interrupt is not shared and controller already 3592dfe0df9aSPyun YongHyeon * disabled further interrupt. 3593dfe0df9aSPyun YongHyeon */ 3594dfe0df9aSPyun YongHyeon taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3595dfe0df9aSPyun YongHyeon return (FILTER_HANDLED); 3596dfe0df9aSPyun YongHyeon } 3597dfe0df9aSPyun YongHyeon 3598dfe0df9aSPyun YongHyeon static void 3599dfe0df9aSPyun YongHyeon bge_intr_task(void *arg, int pending) 3600dfe0df9aSPyun YongHyeon { 3601dfe0df9aSPyun YongHyeon struct bge_softc *sc; 3602dfe0df9aSPyun YongHyeon struct ifnet *ifp; 3603dfe0df9aSPyun YongHyeon uint32_t status; 3604dfe0df9aSPyun YongHyeon uint16_t rx_prod, tx_cons; 3605dfe0df9aSPyun YongHyeon 3606dfe0df9aSPyun YongHyeon sc = (struct bge_softc *)arg; 3607dfe0df9aSPyun YongHyeon ifp = sc->bge_ifp; 3608dfe0df9aSPyun YongHyeon 3609dfe0df9aSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3610dfe0df9aSPyun YongHyeon return; 3611dfe0df9aSPyun YongHyeon 3612dfe0df9aSPyun YongHyeon /* Get updated status block. */ 3613dfe0df9aSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3614dfe0df9aSPyun YongHyeon sc->bge_cdata.bge_status_map, 3615dfe0df9aSPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3616dfe0df9aSPyun YongHyeon 3617dfe0df9aSPyun YongHyeon /* Save producer/consumer indexess. */ 3618dfe0df9aSPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3619dfe0df9aSPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3620dfe0df9aSPyun YongHyeon status = sc->bge_ldata.bge_status_block->bge_status; 3621dfe0df9aSPyun YongHyeon sc->bge_ldata.bge_status_block->bge_status = 0; 3622dfe0df9aSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3623dfe0df9aSPyun YongHyeon sc->bge_cdata.bge_status_map, 3624dfe0df9aSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3625dfe0df9aSPyun YongHyeon /* Let controller work. */ 3626dfe0df9aSPyun YongHyeon bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3627dfe0df9aSPyun YongHyeon 3628dfe0df9aSPyun YongHyeon if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) { 3629dfe0df9aSPyun YongHyeon BGE_LOCK(sc); 3630dfe0df9aSPyun YongHyeon bge_link_upd(sc); 3631dfe0df9aSPyun YongHyeon BGE_UNLOCK(sc); 3632dfe0df9aSPyun YongHyeon } 3633dfe0df9aSPyun YongHyeon if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3634dfe0df9aSPyun YongHyeon /* Check RX return ring producer/consumer. */ 3635dfe0df9aSPyun YongHyeon bge_rxeof(sc, rx_prod, 0); 3636dfe0df9aSPyun YongHyeon } 3637dfe0df9aSPyun YongHyeon if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3638dfe0df9aSPyun YongHyeon BGE_LOCK(sc); 3639dfe0df9aSPyun YongHyeon /* Check TX ring producer/consumer. */ 3640dfe0df9aSPyun YongHyeon bge_txeof(sc, tx_cons); 3641dfe0df9aSPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3642dfe0df9aSPyun YongHyeon bge_start_locked(ifp); 3643dfe0df9aSPyun YongHyeon BGE_UNLOCK(sc); 3644dfe0df9aSPyun YongHyeon } 3645dfe0df9aSPyun YongHyeon } 3646dfe0df9aSPyun YongHyeon 364795d67482SBill Paul static void 36483f74909aSGleb Smirnoff bge_intr(void *xsc) 364995d67482SBill Paul { 365095d67482SBill Paul struct bge_softc *sc; 365195d67482SBill Paul struct ifnet *ifp; 3652dab5cd05SOleg Bulyzhin uint32_t statusword; 3653b9c05fa5SPyun YongHyeon uint16_t rx_prod, tx_cons; 365495d67482SBill Paul 365595d67482SBill Paul sc = xsc; 3656f41ac2beSBill Paul 36570f9bd73bSSam Leffler BGE_LOCK(sc); 36580f9bd73bSSam Leffler 3659dab5cd05SOleg Bulyzhin ifp = sc->bge_ifp; 3660dab5cd05SOleg Bulyzhin 366175719184SGleb Smirnoff #ifdef DEVICE_POLLING 366275719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 366375719184SGleb Smirnoff BGE_UNLOCK(sc); 366475719184SGleb Smirnoff return; 366575719184SGleb Smirnoff } 366675719184SGleb Smirnoff #endif 366775719184SGleb Smirnoff 3668f30cbfc6SScott Long /* 3669b848e032SBruce Evans * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3670b848e032SBruce Evans * disable interrupts by writing nonzero like we used to, since with 3671b848e032SBruce Evans * our current organization this just gives complications and 3672b848e032SBruce Evans * pessimizations for re-enabling interrupts. We used to have races 3673b848e032SBruce Evans * instead of the necessary complications. Disabling interrupts 3674b848e032SBruce Evans * would just reduce the chance of a status update while we are 3675b848e032SBruce Evans * running (by switching to the interrupt-mode coalescence 3676b848e032SBruce Evans * parameters), but this chance is already very low so it is more 3677b848e032SBruce Evans * efficient to get another interrupt than prevent it. 3678b848e032SBruce Evans * 3679b848e032SBruce Evans * We do the ack first to ensure another interrupt if there is a 3680b848e032SBruce Evans * status update after the ack. We don't check for the status 3681b848e032SBruce Evans * changing later because it is more efficient to get another 3682b848e032SBruce Evans * interrupt than prevent it, not quite as above (not checking is 3683b848e032SBruce Evans * a smaller optimization than not toggling the interrupt enable, 3684b848e032SBruce Evans * since checking doesn't involve PCI accesses and toggling require 3685b848e032SBruce Evans * the status check). So toggling would probably be a pessimization 3686b848e032SBruce Evans * even with MSI. It would only be needed for using a task queue. 3687b848e032SBruce Evans */ 368838cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3689b848e032SBruce Evans 3690f584dfd1SPyun YongHyeon /* 3691f584dfd1SPyun YongHyeon * Do the mandatory PCI flush as well as get the link status. 3692f584dfd1SPyun YongHyeon */ 3693f584dfd1SPyun YongHyeon statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3694f584dfd1SPyun YongHyeon 3695f584dfd1SPyun YongHyeon /* Make sure the descriptor ring indexes are coherent. */ 3696f584dfd1SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3697f584dfd1SPyun YongHyeon sc->bge_cdata.bge_status_map, 3698f584dfd1SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3699f584dfd1SPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3700f584dfd1SPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3701f584dfd1SPyun YongHyeon sc->bge_ldata.bge_status_block->bge_status = 0; 3702f584dfd1SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3703f584dfd1SPyun YongHyeon sc->bge_cdata.bge_status_map, 3704f584dfd1SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3705f584dfd1SPyun YongHyeon 37061f313773SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 37074c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3708f30cbfc6SScott Long statusword || sc->bge_link_evt) 3709dab5cd05SOleg Bulyzhin bge_link_upd(sc); 371095d67482SBill Paul 371113f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 37123f74909aSGleb Smirnoff /* Check RX return ring producer/consumer. */ 3713dfe0df9aSPyun YongHyeon bge_rxeof(sc, rx_prod, 1); 371425e13e68SXin LI } 371595d67482SBill Paul 371625e13e68SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 37173f74909aSGleb Smirnoff /* Check TX ring producer/consumer. */ 3718b9c05fa5SPyun YongHyeon bge_txeof(sc, tx_cons); 371995d67482SBill Paul } 372095d67482SBill Paul 372113f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 372213f4c340SRobert Watson !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 37230f9bd73bSSam Leffler bge_start_locked(ifp); 37240f9bd73bSSam Leffler 37250f9bd73bSSam Leffler BGE_UNLOCK(sc); 372695d67482SBill Paul } 372795d67482SBill Paul 372895d67482SBill Paul static void 37298cb1383cSDoug Ambrisko bge_asf_driver_up(struct bge_softc *sc) 37308cb1383cSDoug Ambrisko { 37318cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) { 37328cb1383cSDoug Ambrisko /* Send ASF heartbeat aprox. every 2s */ 37338cb1383cSDoug Ambrisko if (sc->bge_asf_count) 37348cb1383cSDoug Ambrisko sc->bge_asf_count --; 37358cb1383cSDoug Ambrisko else { 3736899d6846SPyun YongHyeon sc->bge_asf_count = 2; 37378cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 37388cb1383cSDoug Ambrisko BGE_FW_DRV_ALIVE); 37398cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 37408cb1383cSDoug Ambrisko bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 37418cb1383cSDoug Ambrisko CSR_WRITE_4(sc, BGE_CPU_EVENT, 374239153c5aSJung-uk Kim CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 37438cb1383cSDoug Ambrisko } 37448cb1383cSDoug Ambrisko } 37458cb1383cSDoug Ambrisko } 37468cb1383cSDoug Ambrisko 37478cb1383cSDoug Ambrisko static void 3748b74e67fbSGleb Smirnoff bge_tick(void *xsc) 37490f9bd73bSSam Leffler { 3750b74e67fbSGleb Smirnoff struct bge_softc *sc = xsc; 375195d67482SBill Paul struct mii_data *mii = NULL; 375295d67482SBill Paul 37530f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 375495d67482SBill Paul 37555dda8085SOleg Bulyzhin /* Synchronize with possible callout reset/stop. */ 37565dda8085SOleg Bulyzhin if (callout_pending(&sc->bge_stat_ch) || 37575dda8085SOleg Bulyzhin !callout_active(&sc->bge_stat_ch)) 37585dda8085SOleg Bulyzhin return; 37595dda8085SOleg Bulyzhin 37607ee00338SJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 37610434d1b8SBill Paul bge_stats_update_regs(sc); 37620434d1b8SBill Paul else 376395d67482SBill Paul bge_stats_update(sc); 376495d67482SBill Paul 3765652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 376695d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 376782b67c01SOleg Bulyzhin /* 376882b67c01SOleg Bulyzhin * Do not touch PHY if we have link up. This could break 376982b67c01SOleg Bulyzhin * IPMI/ASF mode or produce extra input errors 377082b67c01SOleg Bulyzhin * (extra errors was reported for bcm5701 & bcm5704). 377182b67c01SOleg Bulyzhin */ 377282b67c01SOleg Bulyzhin if (!sc->bge_link) 377395d67482SBill Paul mii_tick(mii); 37747b97099dSOleg Bulyzhin } else { 37757b97099dSOleg Bulyzhin /* 37767b97099dSOleg Bulyzhin * Since in TBI mode auto-polling can't be used we should poll 37777b97099dSOleg Bulyzhin * link status manually. Here we register pending link event 37787b97099dSOleg Bulyzhin * and trigger interrupt. 37797b97099dSOleg Bulyzhin */ 37807b97099dSOleg Bulyzhin #ifdef DEVICE_POLLING 37813f74909aSGleb Smirnoff /* In polling mode we poll link state in bge_poll(). */ 37827b97099dSOleg Bulyzhin if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 37837b97099dSOleg Bulyzhin #endif 37847b97099dSOleg Bulyzhin { 37857b97099dSOleg Bulyzhin sc->bge_link_evt++; 37864f0794ffSBjoern A. Zeeb if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 37874f0794ffSBjoern A. Zeeb sc->bge_flags & BGE_FLAG_5788) 37887b97099dSOleg Bulyzhin BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 37894f0794ffSBjoern A. Zeeb else 37904f0794ffSBjoern A. Zeeb BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 37917b97099dSOleg Bulyzhin } 3792dab5cd05SOleg Bulyzhin } 379395d67482SBill Paul 37948cb1383cSDoug Ambrisko bge_asf_driver_up(sc); 3795b74e67fbSGleb Smirnoff bge_watchdog(sc); 37968cb1383cSDoug Ambrisko 3797dab5cd05SOleg Bulyzhin callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 379895d67482SBill Paul } 379995d67482SBill Paul 380095d67482SBill Paul static void 38013f74909aSGleb Smirnoff bge_stats_update_regs(struct bge_softc *sc) 38020434d1b8SBill Paul { 38033f74909aSGleb Smirnoff struct ifnet *ifp; 38040434d1b8SBill Paul 3805fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 38060434d1b8SBill Paul 38076b037352SJung-uk Kim ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 38087e6e2507SJung-uk Kim offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 38097e6e2507SJung-uk Kim 3810e238d4eaSPyun YongHyeon ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 38116b037352SJung-uk Kim ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3812e238d4eaSPyun YongHyeon ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 38130434d1b8SBill Paul } 38140434d1b8SBill Paul 38150434d1b8SBill Paul static void 38163f74909aSGleb Smirnoff bge_stats_update(struct bge_softc *sc) 381795d67482SBill Paul { 381895d67482SBill Paul struct ifnet *ifp; 3819e907febfSPyun YongHyeon bus_size_t stats; 38207e6e2507SJung-uk Kim uint32_t cnt; /* current register value */ 382195d67482SBill Paul 3822fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 382395d67482SBill Paul 3824e907febfSPyun YongHyeon stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3825e907febfSPyun YongHyeon 3826e907febfSPyun YongHyeon #define READ_STAT(sc, stats, stat) \ 3827e907febfSPyun YongHyeon CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 382895d67482SBill Paul 38298634dfffSJung-uk Kim cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 38306b037352SJung-uk Kim ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 38316fb34dd2SOleg Bulyzhin sc->bge_tx_collisions = cnt; 38326fb34dd2SOleg Bulyzhin 38336fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 38346b037352SJung-uk Kim ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 38356fb34dd2SOleg Bulyzhin sc->bge_rx_discards = cnt; 38366fb34dd2SOleg Bulyzhin 38376fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 38386b037352SJung-uk Kim ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 38396fb34dd2SOleg Bulyzhin sc->bge_tx_discards = cnt; 384095d67482SBill Paul 3841e907febfSPyun YongHyeon #undef READ_STAT 384295d67482SBill Paul } 384395d67482SBill Paul 384495d67482SBill Paul /* 3845d375e524SGleb Smirnoff * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3846d375e524SGleb Smirnoff * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3847d375e524SGleb Smirnoff * but when such padded frames employ the bge IP/TCP checksum offload, 3848d375e524SGleb Smirnoff * the hardware checksum assist gives incorrect results (possibly 3849d375e524SGleb Smirnoff * from incorporating its own padding into the UDP/TCP checksum; who knows). 3850d375e524SGleb Smirnoff * If we pad such runts with zeros, the onboard checksum comes out correct. 3851d375e524SGleb Smirnoff */ 3852d375e524SGleb Smirnoff static __inline int 3853d375e524SGleb Smirnoff bge_cksum_pad(struct mbuf *m) 3854d375e524SGleb Smirnoff { 3855d375e524SGleb Smirnoff int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3856d375e524SGleb Smirnoff struct mbuf *last; 3857d375e524SGleb Smirnoff 3858d375e524SGleb Smirnoff /* If there's only the packet-header and we can pad there, use it. */ 3859d375e524SGleb Smirnoff if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3860d375e524SGleb Smirnoff M_TRAILINGSPACE(m) >= padlen) { 3861d375e524SGleb Smirnoff last = m; 3862d375e524SGleb Smirnoff } else { 3863d375e524SGleb Smirnoff /* 3864d375e524SGleb Smirnoff * Walk packet chain to find last mbuf. We will either 3865d375e524SGleb Smirnoff * pad there, or append a new mbuf and pad it. 3866d375e524SGleb Smirnoff */ 3867d375e524SGleb Smirnoff for (last = m; last->m_next != NULL; last = last->m_next); 3868d375e524SGleb Smirnoff if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3869d375e524SGleb Smirnoff /* Allocate new empty mbuf, pad it. Compact later. */ 3870d375e524SGleb Smirnoff struct mbuf *n; 3871d375e524SGleb Smirnoff 3872d375e524SGleb Smirnoff MGET(n, M_DONTWAIT, MT_DATA); 3873d375e524SGleb Smirnoff if (n == NULL) 3874d375e524SGleb Smirnoff return (ENOBUFS); 3875d375e524SGleb Smirnoff n->m_len = 0; 3876d375e524SGleb Smirnoff last->m_next = n; 3877d375e524SGleb Smirnoff last = n; 3878d375e524SGleb Smirnoff } 3879d375e524SGleb Smirnoff } 3880d375e524SGleb Smirnoff 3881d375e524SGleb Smirnoff /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3882d375e524SGleb Smirnoff memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3883d375e524SGleb Smirnoff last->m_len += padlen; 3884d375e524SGleb Smirnoff m->m_pkthdr.len += padlen; 3885d375e524SGleb Smirnoff 3886d375e524SGleb Smirnoff return (0); 3887d375e524SGleb Smirnoff } 3888d375e524SGleb Smirnoff 3889ca3f1187SPyun YongHyeon static struct mbuf * 3890ca3f1187SPyun YongHyeon bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 3891ca3f1187SPyun YongHyeon { 3892ca3f1187SPyun YongHyeon struct ip *ip; 3893ca3f1187SPyun YongHyeon struct tcphdr *tcp; 3894ca3f1187SPyun YongHyeon struct mbuf *n; 3895ca3f1187SPyun YongHyeon uint16_t hlen; 38965b355c4fSPyun YongHyeon uint32_t poff; 3897ca3f1187SPyun YongHyeon 3898ca3f1187SPyun YongHyeon if (M_WRITABLE(m) == 0) { 3899ca3f1187SPyun YongHyeon /* Get a writable copy. */ 3900ca3f1187SPyun YongHyeon n = m_dup(m, M_DONTWAIT); 3901ca3f1187SPyun YongHyeon m_freem(m); 3902ca3f1187SPyun YongHyeon if (n == NULL) 3903ca3f1187SPyun YongHyeon return (NULL); 3904ca3f1187SPyun YongHyeon m = n; 3905ca3f1187SPyun YongHyeon } 39065b355c4fSPyun YongHyeon m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 3907ca3f1187SPyun YongHyeon if (m == NULL) 3908ca3f1187SPyun YongHyeon return (NULL); 39095b355c4fSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 39105b355c4fSPyun YongHyeon poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 3911ca3f1187SPyun YongHyeon m = m_pullup(m, poff + sizeof(struct tcphdr)); 3912ca3f1187SPyun YongHyeon if (m == NULL) 3913ca3f1187SPyun YongHyeon return (NULL); 3914ca3f1187SPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 39155b355c4fSPyun YongHyeon m = m_pullup(m, poff + (tcp->th_off << 2)); 3916ca3f1187SPyun YongHyeon if (m == NULL) 3917ca3f1187SPyun YongHyeon return (NULL); 3918ca3f1187SPyun YongHyeon /* 3919ca3f1187SPyun YongHyeon * It seems controller doesn't modify IP length and TCP pseudo 3920ca3f1187SPyun YongHyeon * checksum. These checksum computed by upper stack should be 0. 3921ca3f1187SPyun YongHyeon */ 3922ca3f1187SPyun YongHyeon *mss = m->m_pkthdr.tso_segsz; 3923ca3f1187SPyun YongHyeon ip->ip_sum = 0; 3924ca3f1187SPyun YongHyeon ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 3925ca3f1187SPyun YongHyeon /* Clear pseudo checksum computed by TCP stack. */ 3926ca3f1187SPyun YongHyeon tcp->th_sum = 0; 3927ca3f1187SPyun YongHyeon /* 3928ca3f1187SPyun YongHyeon * Broadcom controllers uses different descriptor format for 3929ca3f1187SPyun YongHyeon * TSO depending on ASIC revision. Due to TSO-capable firmware 3930ca3f1187SPyun YongHyeon * license issue and lower performance of firmware based TSO 3931ca3f1187SPyun YongHyeon * we only support hardware based TSO which is applicable for 3932ca3f1187SPyun YongHyeon * BCM5755 or newer controllers. Hardware based TSO uses 11 3933ca3f1187SPyun YongHyeon * bits to store MSS and upper 5 bits are used to store IP/TCP 3934ca3f1187SPyun YongHyeon * header length(including IP/TCP options). The header length 3935ca3f1187SPyun YongHyeon * is expressed as 32 bits unit. 3936ca3f1187SPyun YongHyeon */ 3937ca3f1187SPyun YongHyeon hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 3938ca3f1187SPyun YongHyeon *mss |= (hlen << 11); 3939ca3f1187SPyun YongHyeon return (m); 3940ca3f1187SPyun YongHyeon } 3941ca3f1187SPyun YongHyeon 3942d375e524SGleb Smirnoff /* 394395d67482SBill Paul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 394495d67482SBill Paul * pointers to descriptors. 394595d67482SBill Paul */ 394695d67482SBill Paul static int 3947676ad2c9SGleb Smirnoff bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 394895d67482SBill Paul { 39497e27542aSGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_NEW]; 3950f41ac2beSBill Paul bus_dmamap_t map; 3951676ad2c9SGleb Smirnoff struct bge_tx_bd *d; 3952676ad2c9SGleb Smirnoff struct mbuf *m = *m_head; 39537e27542aSGleb Smirnoff uint32_t idx = *txidx; 3954ca3f1187SPyun YongHyeon uint16_t csum_flags, mss, vlan_tag; 39557e27542aSGleb Smirnoff int nsegs, i, error; 395695d67482SBill Paul 39576909dc43SGleb Smirnoff csum_flags = 0; 3958ca3f1187SPyun YongHyeon mss = 0; 3959ca3f1187SPyun YongHyeon vlan_tag = 0; 3960ca3f1187SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 3961ca3f1187SPyun YongHyeon *m_head = m = bge_setup_tso(sc, m, &mss); 3962ca3f1187SPyun YongHyeon if (*m_head == NULL) 3963ca3f1187SPyun YongHyeon return (ENOBUFS); 3964ca3f1187SPyun YongHyeon csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 3965ca3f1187SPyun YongHyeon BGE_TXBDFLAG_CPU_POST_DMA; 3966ca3f1187SPyun YongHyeon } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) { 39676909dc43SGleb Smirnoff if (m->m_pkthdr.csum_flags & CSUM_IP) 39686909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_IP_CSUM; 39696909dc43SGleb Smirnoff if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 39706909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 39716909dc43SGleb Smirnoff if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 39726909dc43SGleb Smirnoff (error = bge_cksum_pad(m)) != 0) { 39736909dc43SGleb Smirnoff m_freem(m); 39746909dc43SGleb Smirnoff *m_head = NULL; 39756909dc43SGleb Smirnoff return (error); 39766909dc43SGleb Smirnoff } 39776909dc43SGleb Smirnoff } 39786909dc43SGleb Smirnoff if (m->m_flags & M_LASTFRAG) 39796909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 39806909dc43SGleb Smirnoff else if (m->m_flags & M_FRAG) 39816909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_IP_FRAG; 39826909dc43SGleb Smirnoff } 39836909dc43SGleb Smirnoff 3984d94f2b85SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3985beaa2ae1SPyun YongHyeon sc->bge_forced_collapse > 0 && 3986beaa2ae1SPyun YongHyeon (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 3987d94f2b85SPyun YongHyeon /* 3988d94f2b85SPyun YongHyeon * Forcedly collapse mbuf chains to overcome hardware 3989d94f2b85SPyun YongHyeon * limitation which only support a single outstanding 3990d94f2b85SPyun YongHyeon * DMA read operation. 3991d94f2b85SPyun YongHyeon */ 3992beaa2ae1SPyun YongHyeon if (sc->bge_forced_collapse == 1) 3993d94f2b85SPyun YongHyeon m = m_defrag(m, M_DONTWAIT); 3994d94f2b85SPyun YongHyeon else 3995beaa2ae1SPyun YongHyeon m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse); 3996261f04d6SPyun YongHyeon if (m == NULL) 3997261f04d6SPyun YongHyeon m = *m_head; 3998d94f2b85SPyun YongHyeon *m_head = m; 3999d94f2b85SPyun YongHyeon } 4000d94f2b85SPyun YongHyeon 40017e27542aSGleb Smirnoff map = sc->bge_cdata.bge_tx_dmamap[idx]; 40020ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4003676ad2c9SGleb Smirnoff &nsegs, BUS_DMA_NOWAIT); 40047e27542aSGleb Smirnoff if (error == EFBIG) { 40054eee14cbSMarius Strobl m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4006676ad2c9SGleb Smirnoff if (m == NULL) { 4007676ad2c9SGleb Smirnoff m_freem(*m_head); 4008676ad2c9SGleb Smirnoff *m_head = NULL; 40097e27542aSGleb Smirnoff return (ENOBUFS); 40107e27542aSGleb Smirnoff } 4011676ad2c9SGleb Smirnoff *m_head = m; 40120ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 40130ac56796SPyun YongHyeon m, segs, &nsegs, BUS_DMA_NOWAIT); 4014676ad2c9SGleb Smirnoff if (error) { 4015676ad2c9SGleb Smirnoff m_freem(m); 4016676ad2c9SGleb Smirnoff *m_head = NULL; 40177e27542aSGleb Smirnoff return (error); 40187e27542aSGleb Smirnoff } 4019676ad2c9SGleb Smirnoff } else if (error != 0) 4020676ad2c9SGleb Smirnoff return (error); 40217e27542aSGleb Smirnoff 4022167fdb62SPyun YongHyeon /* Check if we have enough free send BDs. */ 4023167fdb62SPyun YongHyeon if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 40240ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 402595d67482SBill Paul return (ENOBUFS); 40267e27542aSGleb Smirnoff } 40277e27542aSGleb Smirnoff 40280ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4029e65bed95SPyun YongHyeon 4030ca3f1187SPyun YongHyeon #if __FreeBSD_version > 700022 4031ca3f1187SPyun YongHyeon if (m->m_flags & M_VLANTAG) { 4032ca3f1187SPyun YongHyeon csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4033ca3f1187SPyun YongHyeon vlan_tag = m->m_pkthdr.ether_vtag; 4034ca3f1187SPyun YongHyeon } 4035ca3f1187SPyun YongHyeon #else 4036ca3f1187SPyun YongHyeon { 4037ca3f1187SPyun YongHyeon struct m_tag *mtag; 4038ca3f1187SPyun YongHyeon 4039ca3f1187SPyun YongHyeon if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 4040ca3f1187SPyun YongHyeon csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4041ca3f1187SPyun YongHyeon vlan_tag = VLAN_TAG_VALUE(mtag); 4042ca3f1187SPyun YongHyeon } 4043ca3f1187SPyun YongHyeon } 4044ca3f1187SPyun YongHyeon #endif 40457e27542aSGleb Smirnoff for (i = 0; ; i++) { 40467e27542aSGleb Smirnoff d = &sc->bge_ldata.bge_tx_ring[idx]; 40477e27542aSGleb Smirnoff d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 40487e27542aSGleb Smirnoff d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 40497e27542aSGleb Smirnoff d->bge_len = segs[i].ds_len; 40507e27542aSGleb Smirnoff d->bge_flags = csum_flags; 4051ca3f1187SPyun YongHyeon d->bge_vlan_tag = vlan_tag; 4052ca3f1187SPyun YongHyeon d->bge_mss = mss; 40537e27542aSGleb Smirnoff if (i == nsegs - 1) 40547e27542aSGleb Smirnoff break; 40557e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 40567e27542aSGleb Smirnoff } 40577e27542aSGleb Smirnoff 40587e27542aSGleb Smirnoff /* Mark the last segment as end of packet... */ 40597e27542aSGleb Smirnoff d->bge_flags |= BGE_TXBDFLAG_END; 4060676ad2c9SGleb Smirnoff 4061f41ac2beSBill Paul /* 4062f41ac2beSBill Paul * Insure that the map for this transmission 4063f41ac2beSBill Paul * is placed at the array index of the last descriptor 4064f41ac2beSBill Paul * in this chain. 4065f41ac2beSBill Paul */ 40667e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 40677e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[idx] = map; 4068676ad2c9SGleb Smirnoff sc->bge_cdata.bge_tx_chain[idx] = m; 40697e27542aSGleb Smirnoff sc->bge_txcnt += nsegs; 407095d67482SBill Paul 40717e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 40727e27542aSGleb Smirnoff *txidx = idx; 407395d67482SBill Paul 407495d67482SBill Paul return (0); 407595d67482SBill Paul } 407695d67482SBill Paul 407795d67482SBill Paul /* 407895d67482SBill Paul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 407995d67482SBill Paul * to the mbuf data regions directly in the transmit descriptors. 408095d67482SBill Paul */ 408195d67482SBill Paul static void 40823f74909aSGleb Smirnoff bge_start_locked(struct ifnet *ifp) 408395d67482SBill Paul { 408495d67482SBill Paul struct bge_softc *sc; 4085167fdb62SPyun YongHyeon struct mbuf *m_head; 408614bbd30fSGleb Smirnoff uint32_t prodidx; 4087167fdb62SPyun YongHyeon int count; 408895d67482SBill Paul 408995d67482SBill Paul sc = ifp->if_softc; 4090167fdb62SPyun YongHyeon BGE_LOCK_ASSERT(sc); 409195d67482SBill Paul 4092167fdb62SPyun YongHyeon if (!sc->bge_link || 4093167fdb62SPyun YongHyeon (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4094167fdb62SPyun YongHyeon IFF_DRV_RUNNING) 409595d67482SBill Paul return; 409695d67482SBill Paul 409714bbd30fSGleb Smirnoff prodidx = sc->bge_tx_prodidx; 409895d67482SBill Paul 4099167fdb62SPyun YongHyeon for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4100167fdb62SPyun YongHyeon if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4101167fdb62SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4102167fdb62SPyun YongHyeon break; 4103167fdb62SPyun YongHyeon } 41044d665c4dSDag-Erling Smørgrav IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 410595d67482SBill Paul if (m_head == NULL) 410695d67482SBill Paul break; 410795d67482SBill Paul 410895d67482SBill Paul /* 410995d67482SBill Paul * XXX 4110b874fdd4SYaroslav Tykhiy * The code inside the if() block is never reached since we 4111b874fdd4SYaroslav Tykhiy * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4112b874fdd4SYaroslav Tykhiy * requests to checksum TCP/UDP in a fragmented packet. 4113b874fdd4SYaroslav Tykhiy * 4114b874fdd4SYaroslav Tykhiy * XXX 411595d67482SBill Paul * safety overkill. If this is a fragmented packet chain 411695d67482SBill Paul * with delayed TCP/UDP checksums, then only encapsulate 411795d67482SBill Paul * it if we have enough descriptors to handle the entire 411895d67482SBill Paul * chain at once. 411995d67482SBill Paul * (paranoia -- may not actually be needed) 412095d67482SBill Paul */ 412195d67482SBill Paul if (m_head->m_flags & M_FIRSTFRAG && 412295d67482SBill Paul m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 412395d67482SBill Paul if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 412495d67482SBill Paul m_head->m_pkthdr.csum_data + 16) { 41254d665c4dSDag-Erling Smørgrav IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 412613f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 412795d67482SBill Paul break; 412895d67482SBill Paul } 412995d67482SBill Paul } 413095d67482SBill Paul 413195d67482SBill Paul /* 413295d67482SBill Paul * Pack the data into the transmit ring. If we 413395d67482SBill Paul * don't have room, set the OACTIVE flag and wait 413495d67482SBill Paul * for the NIC to drain the ring. 413595d67482SBill Paul */ 4136676ad2c9SGleb Smirnoff if (bge_encap(sc, &m_head, &prodidx)) { 4137676ad2c9SGleb Smirnoff if (m_head == NULL) 4138676ad2c9SGleb Smirnoff break; 41394d665c4dSDag-Erling Smørgrav IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 414013f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 414195d67482SBill Paul break; 414295d67482SBill Paul } 4143303a718cSDag-Erling Smørgrav ++count; 414495d67482SBill Paul 414595d67482SBill Paul /* 414695d67482SBill Paul * If there's a BPF listener, bounce a copy of this frame 414795d67482SBill Paul * to him. 414895d67482SBill Paul */ 41494e35d186SJung-uk Kim #ifdef ETHER_BPF_MTAP 415045ee6ab3SJung-uk Kim ETHER_BPF_MTAP(ifp, m_head); 41514e35d186SJung-uk Kim #else 41524e35d186SJung-uk Kim BPF_MTAP(ifp, m_head); 41534e35d186SJung-uk Kim #endif 415495d67482SBill Paul } 415595d67482SBill Paul 4156167fdb62SPyun YongHyeon if (count > 0) { 4157aa94f333SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 41585c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 41593f74909aSGleb Smirnoff /* Transmit. */ 416038cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 41613927098fSPaul Saab /* 5700 b2 errata */ 4162e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 416338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 416495d67482SBill Paul 416514bbd30fSGleb Smirnoff sc->bge_tx_prodidx = prodidx; 416614bbd30fSGleb Smirnoff 416795d67482SBill Paul /* 416895d67482SBill Paul * Set a timeout in case the chip goes out to lunch. 416995d67482SBill Paul */ 4170b74e67fbSGleb Smirnoff sc->bge_timer = 5; 417195d67482SBill Paul } 4172167fdb62SPyun YongHyeon } 417395d67482SBill Paul 41740f9bd73bSSam Leffler /* 41750f9bd73bSSam Leffler * Main transmit routine. To avoid having to do mbuf copies, we put pointers 41760f9bd73bSSam Leffler * to the mbuf data regions directly in the transmit descriptors. 41770f9bd73bSSam Leffler */ 417895d67482SBill Paul static void 41793f74909aSGleb Smirnoff bge_start(struct ifnet *ifp) 418095d67482SBill Paul { 41810f9bd73bSSam Leffler struct bge_softc *sc; 41820f9bd73bSSam Leffler 41830f9bd73bSSam Leffler sc = ifp->if_softc; 41840f9bd73bSSam Leffler BGE_LOCK(sc); 41850f9bd73bSSam Leffler bge_start_locked(ifp); 41860f9bd73bSSam Leffler BGE_UNLOCK(sc); 41870f9bd73bSSam Leffler } 41880f9bd73bSSam Leffler 41890f9bd73bSSam Leffler static void 41903f74909aSGleb Smirnoff bge_init_locked(struct bge_softc *sc) 41910f9bd73bSSam Leffler { 419295d67482SBill Paul struct ifnet *ifp; 41933f74909aSGleb Smirnoff uint16_t *m; 419495d67482SBill Paul 41950f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 419695d67482SBill Paul 4197fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 419895d67482SBill Paul 419913f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 420095d67482SBill Paul return; 420195d67482SBill Paul 420295d67482SBill Paul /* Cancel pending I/O and flush buffers. */ 420395d67482SBill Paul bge_stop(sc); 42048cb1383cSDoug Ambrisko 42058cb1383cSDoug Ambrisko bge_stop_fw(sc); 42068cb1383cSDoug Ambrisko bge_sig_pre_reset(sc, BGE_RESET_START); 420795d67482SBill Paul bge_reset(sc); 42088cb1383cSDoug Ambrisko bge_sig_legacy(sc, BGE_RESET_START); 42098cb1383cSDoug Ambrisko bge_sig_post_reset(sc, BGE_RESET_START); 42108cb1383cSDoug Ambrisko 421195d67482SBill Paul bge_chipinit(sc); 421295d67482SBill Paul 421395d67482SBill Paul /* 421495d67482SBill Paul * Init the various state machines, ring 421595d67482SBill Paul * control blocks and firmware. 421695d67482SBill Paul */ 421795d67482SBill Paul if (bge_blockinit(sc)) { 4218fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "initialization failure\n"); 421995d67482SBill Paul return; 422095d67482SBill Paul } 422195d67482SBill Paul 4222fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 422395d67482SBill Paul 422495d67482SBill Paul /* Specify MTU. */ 422595d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4226cb2eacc7SYaroslav Tykhiy ETHER_HDR_LEN + ETHER_CRC_LEN + 4227cb2eacc7SYaroslav Tykhiy (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 422895d67482SBill Paul 422995d67482SBill Paul /* Load our MAC address. */ 42303f74909aSGleb Smirnoff m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 423195d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 423295d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 423395d67482SBill Paul 42343e9b1bcaSJung-uk Kim /* Program promiscuous mode. */ 42353e9b1bcaSJung-uk Kim bge_setpromisc(sc); 423695d67482SBill Paul 423795d67482SBill Paul /* Program multicast filter. */ 423895d67482SBill Paul bge_setmulti(sc); 423995d67482SBill Paul 4240cb2eacc7SYaroslav Tykhiy /* Program VLAN tag stripping. */ 4241cb2eacc7SYaroslav Tykhiy bge_setvlan(sc); 4242cb2eacc7SYaroslav Tykhiy 424395d67482SBill Paul /* Init RX ring. */ 42443ee5d7daSPyun YongHyeon if (bge_init_rx_ring_std(sc) != 0) { 42453ee5d7daSPyun YongHyeon device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 42463ee5d7daSPyun YongHyeon bge_stop(sc); 42473ee5d7daSPyun YongHyeon return; 42483ee5d7daSPyun YongHyeon } 424995d67482SBill Paul 42500434d1b8SBill Paul /* 42510434d1b8SBill Paul * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 42520434d1b8SBill Paul * memory to insure that the chip has in fact read the first 42530434d1b8SBill Paul * entry of the ring. 42540434d1b8SBill Paul */ 42550434d1b8SBill Paul if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 42563f74909aSGleb Smirnoff uint32_t v, i; 42570434d1b8SBill Paul for (i = 0; i < 10; i++) { 42580434d1b8SBill Paul DELAY(20); 42590434d1b8SBill Paul v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 42600434d1b8SBill Paul if (v == (MCLBYTES - ETHER_ALIGN)) 42610434d1b8SBill Paul break; 42620434d1b8SBill Paul } 42630434d1b8SBill Paul if (i == 10) 4264fe806fdaSPyun YongHyeon device_printf (sc->bge_dev, 4265fe806fdaSPyun YongHyeon "5705 A0 chip failed to load RX ring\n"); 42660434d1b8SBill Paul } 42670434d1b8SBill Paul 426895d67482SBill Paul /* Init jumbo RX ring. */ 4269c215fd77SPyun YongHyeon if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4270c215fd77SPyun YongHyeon (MCLBYTES - ETHER_ALIGN)) { 42713ee5d7daSPyun YongHyeon if (bge_init_rx_ring_jumbo(sc) != 0) { 4272333704a3SPyun YongHyeon device_printf(sc->bge_dev, 4273b65256d7SPyun YongHyeon "no memory for jumbo Rx buffers.\n"); 42743ee5d7daSPyun YongHyeon bge_stop(sc); 42753ee5d7daSPyun YongHyeon return; 42763ee5d7daSPyun YongHyeon } 42773ee5d7daSPyun YongHyeon } 427895d67482SBill Paul 42793f74909aSGleb Smirnoff /* Init our RX return ring index. */ 428095d67482SBill Paul sc->bge_rx_saved_considx = 0; 428195d67482SBill Paul 42827e6e2507SJung-uk Kim /* Init our RX/TX stat counters. */ 42837e6e2507SJung-uk Kim sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 42847e6e2507SJung-uk Kim 428595d67482SBill Paul /* Init TX ring. */ 428695d67482SBill Paul bge_init_tx_ring(sc); 428795d67482SBill Paul 42883f74909aSGleb Smirnoff /* Turn on transmitter. */ 428995d67482SBill Paul BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 429095d67482SBill Paul 42913f74909aSGleb Smirnoff /* Turn on receiver. */ 429295d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 429395d67482SBill Paul 429495d67482SBill Paul /* Tell firmware we're alive. */ 429595d67482SBill Paul BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 429695d67482SBill Paul 429775719184SGleb Smirnoff #ifdef DEVICE_POLLING 429875719184SGleb Smirnoff /* Disable interrupts if we are polling. */ 429975719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 430075719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 430175719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 430238cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 430375719184SGleb Smirnoff } else 430475719184SGleb Smirnoff #endif 430575719184SGleb Smirnoff 430695d67482SBill Paul /* Enable host interrupts. */ 430775719184SGleb Smirnoff { 430895d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 430995d67482SBill Paul BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 431038cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 431175719184SGleb Smirnoff } 431295d67482SBill Paul 431367d5e043SOleg Bulyzhin bge_ifmedia_upd_locked(ifp); 431495d67482SBill Paul 431513f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 431613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 431795d67482SBill Paul 43180f9bd73bSSam Leffler callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 43190f9bd73bSSam Leffler } 43200f9bd73bSSam Leffler 43210f9bd73bSSam Leffler static void 43223f74909aSGleb Smirnoff bge_init(void *xsc) 43230f9bd73bSSam Leffler { 43240f9bd73bSSam Leffler struct bge_softc *sc = xsc; 43250f9bd73bSSam Leffler 43260f9bd73bSSam Leffler BGE_LOCK(sc); 43270f9bd73bSSam Leffler bge_init_locked(sc); 43280f9bd73bSSam Leffler BGE_UNLOCK(sc); 432995d67482SBill Paul } 433095d67482SBill Paul 433195d67482SBill Paul /* 433295d67482SBill Paul * Set media options. 433395d67482SBill Paul */ 433495d67482SBill Paul static int 43353f74909aSGleb Smirnoff bge_ifmedia_upd(struct ifnet *ifp) 433695d67482SBill Paul { 433767d5e043SOleg Bulyzhin struct bge_softc *sc = ifp->if_softc; 433867d5e043SOleg Bulyzhin int res; 433967d5e043SOleg Bulyzhin 434067d5e043SOleg Bulyzhin BGE_LOCK(sc); 434167d5e043SOleg Bulyzhin res = bge_ifmedia_upd_locked(ifp); 434267d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 434367d5e043SOleg Bulyzhin 434467d5e043SOleg Bulyzhin return (res); 434567d5e043SOleg Bulyzhin } 434667d5e043SOleg Bulyzhin 434767d5e043SOleg Bulyzhin static int 434867d5e043SOleg Bulyzhin bge_ifmedia_upd_locked(struct ifnet *ifp) 434967d5e043SOleg Bulyzhin { 435067d5e043SOleg Bulyzhin struct bge_softc *sc = ifp->if_softc; 435195d67482SBill Paul struct mii_data *mii; 43524f09c4c7SMarius Strobl struct mii_softc *miisc; 435395d67482SBill Paul struct ifmedia *ifm; 435495d67482SBill Paul 435567d5e043SOleg Bulyzhin BGE_LOCK_ASSERT(sc); 435667d5e043SOleg Bulyzhin 435795d67482SBill Paul ifm = &sc->bge_ifmedia; 435895d67482SBill Paul 435995d67482SBill Paul /* If this is a 1000baseX NIC, enable the TBI port. */ 4360652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 436195d67482SBill Paul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 436295d67482SBill Paul return (EINVAL); 436395d67482SBill Paul switch(IFM_SUBTYPE(ifm->ifm_media)) { 436495d67482SBill Paul case IFM_AUTO: 4365ff50922bSDoug White /* 4366ff50922bSDoug White * The BCM5704 ASIC appears to have a special 4367ff50922bSDoug White * mechanism for programming the autoneg 4368ff50922bSDoug White * advertisement registers in TBI mode. 4369ff50922bSDoug White */ 43700f89fde2SJung-uk Kim if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4371ff50922bSDoug White uint32_t sgdig; 43720f89fde2SJung-uk Kim sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 43730f89fde2SJung-uk Kim if (sgdig & BGE_SGDIGSTS_DONE) { 4374ff50922bSDoug White CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4375ff50922bSDoug White sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4376ff50922bSDoug White sgdig |= BGE_SGDIGCFG_AUTO | 4377ff50922bSDoug White BGE_SGDIGCFG_PAUSE_CAP | 4378ff50922bSDoug White BGE_SGDIGCFG_ASYM_PAUSE; 4379ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4380ff50922bSDoug White sgdig | BGE_SGDIGCFG_SEND); 4381ff50922bSDoug White DELAY(5); 4382ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4383ff50922bSDoug White } 43840f89fde2SJung-uk Kim } 438595d67482SBill Paul break; 438695d67482SBill Paul case IFM_1000_SX: 438795d67482SBill Paul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 438895d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, 438995d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 439095d67482SBill Paul } else { 439195d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, 439295d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 439395d67482SBill Paul } 439495d67482SBill Paul break; 439595d67482SBill Paul default: 439695d67482SBill Paul return (EINVAL); 439795d67482SBill Paul } 439895d67482SBill Paul return (0); 439995d67482SBill Paul } 440095d67482SBill Paul 44011493e883SOleg Bulyzhin sc->bge_link_evt++; 440295d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 44034f09c4c7SMarius Strobl if (mii->mii_instance) 44044f09c4c7SMarius Strobl LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 440595d67482SBill Paul mii_phy_reset(miisc); 440695d67482SBill Paul mii_mediachg(mii); 440795d67482SBill Paul 4408902827f6SBjoern A. Zeeb /* 4409902827f6SBjoern A. Zeeb * Force an interrupt so that we will call bge_link_upd 4410902827f6SBjoern A. Zeeb * if needed and clear any pending link state attention. 4411902827f6SBjoern A. Zeeb * Without this we are not getting any further interrupts 4412902827f6SBjoern A. Zeeb * for link state changes and thus will not UP the link and 4413902827f6SBjoern A. Zeeb * not be able to send in bge_start_locked. The only 4414902827f6SBjoern A. Zeeb * way to get things working was to receive a packet and 4415902827f6SBjoern A. Zeeb * get an RX intr. 4416902827f6SBjoern A. Zeeb * bge_tick should help for fiber cards and we might not 4417902827f6SBjoern A. Zeeb * need to do this here if BGE_FLAG_TBI is set but as 4418902827f6SBjoern A. Zeeb * we poll for fiber anyway it should not harm. 4419902827f6SBjoern A. Zeeb */ 44204f0794ffSBjoern A. Zeeb if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 44214f0794ffSBjoern A. Zeeb sc->bge_flags & BGE_FLAG_5788) 4422902827f6SBjoern A. Zeeb BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 44234f0794ffSBjoern A. Zeeb else 442463ccfe30SBjoern A. Zeeb BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4425902827f6SBjoern A. Zeeb 442695d67482SBill Paul return (0); 442795d67482SBill Paul } 442895d67482SBill Paul 442995d67482SBill Paul /* 443095d67482SBill Paul * Report current media status. 443195d67482SBill Paul */ 443295d67482SBill Paul static void 44333f74909aSGleb Smirnoff bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 443495d67482SBill Paul { 443567d5e043SOleg Bulyzhin struct bge_softc *sc = ifp->if_softc; 443695d67482SBill Paul struct mii_data *mii; 443795d67482SBill Paul 443867d5e043SOleg Bulyzhin BGE_LOCK(sc); 443995d67482SBill Paul 4440652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 444195d67482SBill Paul ifmr->ifm_status = IFM_AVALID; 444295d67482SBill Paul ifmr->ifm_active = IFM_ETHER; 444395d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_STS) & 444495d67482SBill Paul BGE_MACSTAT_TBI_PCS_SYNCHED) 444595d67482SBill Paul ifmr->ifm_status |= IFM_ACTIVE; 44464c0da0ffSGleb Smirnoff else { 44474c0da0ffSGleb Smirnoff ifmr->ifm_active |= IFM_NONE; 444867d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 44494c0da0ffSGleb Smirnoff return; 44504c0da0ffSGleb Smirnoff } 445195d67482SBill Paul ifmr->ifm_active |= IFM_1000_SX; 445295d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 445395d67482SBill Paul ifmr->ifm_active |= IFM_HDX; 445495d67482SBill Paul else 445595d67482SBill Paul ifmr->ifm_active |= IFM_FDX; 445667d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 445795d67482SBill Paul return; 445895d67482SBill Paul } 445995d67482SBill Paul 446095d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 446195d67482SBill Paul mii_pollstat(mii); 446295d67482SBill Paul ifmr->ifm_active = mii->mii_media_active; 446395d67482SBill Paul ifmr->ifm_status = mii->mii_media_status; 446467d5e043SOleg Bulyzhin 446567d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 446695d67482SBill Paul } 446795d67482SBill Paul 446895d67482SBill Paul static int 44693f74909aSGleb Smirnoff bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 447095d67482SBill Paul { 447195d67482SBill Paul struct bge_softc *sc = ifp->if_softc; 447295d67482SBill Paul struct ifreq *ifr = (struct ifreq *) data; 447395d67482SBill Paul struct mii_data *mii; 4474f9004b6dSJung-uk Kim int flags, mask, error = 0; 447595d67482SBill Paul 447695d67482SBill Paul switch (command) { 447795d67482SBill Paul case SIOCSIFMTU: 44784c0da0ffSGleb Smirnoff if (ifr->ifr_mtu < ETHERMIN || 44794c0da0ffSGleb Smirnoff ((BGE_IS_JUMBO_CAPABLE(sc)) && 44804c0da0ffSGleb Smirnoff ifr->ifr_mtu > BGE_JUMBO_MTU) || 44814c0da0ffSGleb Smirnoff ((!BGE_IS_JUMBO_CAPABLE(sc)) && 44824c0da0ffSGleb Smirnoff ifr->ifr_mtu > ETHERMTU)) 448395d67482SBill Paul error = EINVAL; 44844c0da0ffSGleb Smirnoff else if (ifp->if_mtu != ifr->ifr_mtu) { 448595d67482SBill Paul ifp->if_mtu = ifr->ifr_mtu; 448613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 448795d67482SBill Paul bge_init(sc); 448895d67482SBill Paul } 448995d67482SBill Paul break; 449095d67482SBill Paul case SIOCSIFFLAGS: 44910f9bd73bSSam Leffler BGE_LOCK(sc); 449295d67482SBill Paul if (ifp->if_flags & IFF_UP) { 449395d67482SBill Paul /* 449495d67482SBill Paul * If only the state of the PROMISC flag changed, 449595d67482SBill Paul * then just use the 'set promisc mode' command 449695d67482SBill Paul * instead of reinitializing the entire NIC. Doing 449795d67482SBill Paul * a full re-init means reloading the firmware and 449895d67482SBill Paul * waiting for it to start up, which may take a 4499d183af7fSRuslan Ermilov * second or two. Similarly for ALLMULTI. 450095d67482SBill Paul */ 4501f9004b6dSJung-uk Kim if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4502f9004b6dSJung-uk Kim flags = ifp->if_flags ^ sc->bge_if_flags; 45033e9b1bcaSJung-uk Kim if (flags & IFF_PROMISC) 45043e9b1bcaSJung-uk Kim bge_setpromisc(sc); 4505f9004b6dSJung-uk Kim if (flags & IFF_ALLMULTI) 4506d183af7fSRuslan Ermilov bge_setmulti(sc); 450795d67482SBill Paul } else 45080f9bd73bSSam Leffler bge_init_locked(sc); 450995d67482SBill Paul } else { 451013f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 451195d67482SBill Paul bge_stop(sc); 451295d67482SBill Paul } 451395d67482SBill Paul } 451495d67482SBill Paul sc->bge_if_flags = ifp->if_flags; 45150f9bd73bSSam Leffler BGE_UNLOCK(sc); 451695d67482SBill Paul error = 0; 451795d67482SBill Paul break; 451895d67482SBill Paul case SIOCADDMULTI: 451995d67482SBill Paul case SIOCDELMULTI: 452013f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 45210f9bd73bSSam Leffler BGE_LOCK(sc); 452295d67482SBill Paul bge_setmulti(sc); 45230f9bd73bSSam Leffler BGE_UNLOCK(sc); 452495d67482SBill Paul error = 0; 452595d67482SBill Paul } 452695d67482SBill Paul break; 452795d67482SBill Paul case SIOCSIFMEDIA: 452895d67482SBill Paul case SIOCGIFMEDIA: 4529652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 453095d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 453195d67482SBill Paul &sc->bge_ifmedia, command); 453295d67482SBill Paul } else { 453395d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 453495d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 453595d67482SBill Paul &mii->mii_media, command); 453695d67482SBill Paul } 453795d67482SBill Paul break; 453895d67482SBill Paul case SIOCSIFCAP: 453995d67482SBill Paul mask = ifr->ifr_reqcap ^ ifp->if_capenable; 454075719184SGleb Smirnoff #ifdef DEVICE_POLLING 454175719184SGleb Smirnoff if (mask & IFCAP_POLLING) { 454275719184SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING) { 454375719184SGleb Smirnoff error = ether_poll_register(bge_poll, ifp); 454475719184SGleb Smirnoff if (error) 454575719184SGleb Smirnoff return (error); 454675719184SGleb Smirnoff BGE_LOCK(sc); 454775719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 454875719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 454938cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 455075719184SGleb Smirnoff ifp->if_capenable |= IFCAP_POLLING; 455175719184SGleb Smirnoff BGE_UNLOCK(sc); 455275719184SGleb Smirnoff } else { 455375719184SGleb Smirnoff error = ether_poll_deregister(ifp); 455475719184SGleb Smirnoff /* Enable interrupt even in error case */ 455575719184SGleb Smirnoff BGE_LOCK(sc); 455675719184SGleb Smirnoff BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 455775719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 455838cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 455975719184SGleb Smirnoff ifp->if_capenable &= ~IFCAP_POLLING; 456075719184SGleb Smirnoff BGE_UNLOCK(sc); 456175719184SGleb Smirnoff } 456275719184SGleb Smirnoff } 456375719184SGleb Smirnoff #endif 4564d375e524SGleb Smirnoff if (mask & IFCAP_HWCSUM) { 4565d375e524SGleb Smirnoff ifp->if_capenable ^= IFCAP_HWCSUM; 4566d375e524SGleb Smirnoff if (IFCAP_HWCSUM & ifp->if_capenable && 4567d375e524SGleb Smirnoff IFCAP_HWCSUM & ifp->if_capabilities) 4568ca3f1187SPyun YongHyeon ifp->if_hwassist |= BGE_CSUM_FEATURES; 456995d67482SBill Paul else 4570ca3f1187SPyun YongHyeon ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 457195d67482SBill Paul } 4572cb2eacc7SYaroslav Tykhiy 4573ca3f1187SPyun YongHyeon if ((mask & IFCAP_TSO4) != 0 && 4574ca3f1187SPyun YongHyeon (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4575ca3f1187SPyun YongHyeon ifp->if_capenable ^= IFCAP_TSO4; 4576ca3f1187SPyun YongHyeon if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4577ca3f1187SPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 4578ca3f1187SPyun YongHyeon else 4579ca3f1187SPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 4580ca3f1187SPyun YongHyeon } 4581ca3f1187SPyun YongHyeon 4582cb2eacc7SYaroslav Tykhiy if (mask & IFCAP_VLAN_MTU) { 4583cb2eacc7SYaroslav Tykhiy ifp->if_capenable ^= IFCAP_VLAN_MTU; 4584cb2eacc7SYaroslav Tykhiy ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4585cb2eacc7SYaroslav Tykhiy bge_init(sc); 4586cb2eacc7SYaroslav Tykhiy } 4587cb2eacc7SYaroslav Tykhiy 458804bde852SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTSO) != 0 && 458904bde852SPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 459004bde852SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 459104bde852SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 459204bde852SPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 4593cb2eacc7SYaroslav Tykhiy ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 459404bde852SPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 459504bde852SPyun YongHyeon ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 4596cb2eacc7SYaroslav Tykhiy BGE_LOCK(sc); 4597cb2eacc7SYaroslav Tykhiy bge_setvlan(sc); 4598cb2eacc7SYaroslav Tykhiy BGE_UNLOCK(sc); 459904bde852SPyun YongHyeon } 4600cb2eacc7SYaroslav Tykhiy #ifdef VLAN_CAPABILITIES 4601cb2eacc7SYaroslav Tykhiy VLAN_CAPABILITIES(ifp); 4602cb2eacc7SYaroslav Tykhiy #endif 460395d67482SBill Paul break; 460495d67482SBill Paul default: 4605673d9191SSam Leffler error = ether_ioctl(ifp, command, data); 460695d67482SBill Paul break; 460795d67482SBill Paul } 460895d67482SBill Paul 460995d67482SBill Paul return (error); 461095d67482SBill Paul } 461195d67482SBill Paul 461295d67482SBill Paul static void 4613b74e67fbSGleb Smirnoff bge_watchdog(struct bge_softc *sc) 461495d67482SBill Paul { 4615b74e67fbSGleb Smirnoff struct ifnet *ifp; 461695d67482SBill Paul 4617b74e67fbSGleb Smirnoff BGE_LOCK_ASSERT(sc); 4618b74e67fbSGleb Smirnoff 4619b74e67fbSGleb Smirnoff if (sc->bge_timer == 0 || --sc->bge_timer) 4620b74e67fbSGleb Smirnoff return; 4621b74e67fbSGleb Smirnoff 4622b74e67fbSGleb Smirnoff ifp = sc->bge_ifp; 462395d67482SBill Paul 4624fe806fdaSPyun YongHyeon if_printf(ifp, "watchdog timeout -- resetting\n"); 462595d67482SBill Paul 462613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4627426742bfSGleb Smirnoff bge_init_locked(sc); 462895d67482SBill Paul 462995d67482SBill Paul ifp->if_oerrors++; 463095d67482SBill Paul } 463195d67482SBill Paul 463295d67482SBill Paul /* 463395d67482SBill Paul * Stop the adapter and free any mbufs allocated to the 463495d67482SBill Paul * RX and TX lists. 463595d67482SBill Paul */ 463695d67482SBill Paul static void 46373f74909aSGleb Smirnoff bge_stop(struct bge_softc *sc) 463895d67482SBill Paul { 463995d67482SBill Paul struct ifnet *ifp; 464095d67482SBill Paul 46410f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 46420f9bd73bSSam Leffler 4643fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 464495d67482SBill Paul 46450f9bd73bSSam Leffler callout_stop(&sc->bge_stat_ch); 464695d67482SBill Paul 464744b63691SBjoern A. Zeeb /* Disable host interrupts. */ 464844b63691SBjoern A. Zeeb BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 464944b63691SBjoern A. Zeeb bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 465044b63691SBjoern A. Zeeb 465144b63691SBjoern A. Zeeb /* 465244b63691SBjoern A. Zeeb * Tell firmware we're shutting down. 465344b63691SBjoern A. Zeeb */ 465444b63691SBjoern A. Zeeb bge_stop_fw(sc); 465544b63691SBjoern A. Zeeb bge_sig_pre_reset(sc, BGE_RESET_STOP); 465644b63691SBjoern A. Zeeb 465795d67482SBill Paul /* 46583f74909aSGleb Smirnoff * Disable all of the receiver blocks. 465995d67482SBill Paul */ 466095d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 466195d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 466295d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 46637ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 466495d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 466595d67482SBill Paul BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 466695d67482SBill Paul BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 466795d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 466895d67482SBill Paul 466995d67482SBill Paul /* 46703f74909aSGleb Smirnoff * Disable all of the transmit blocks. 467195d67482SBill Paul */ 467295d67482SBill Paul BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 467395d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 467495d67482SBill Paul BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 467595d67482SBill Paul BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 467695d67482SBill Paul BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 46777ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 467895d67482SBill Paul BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 467995d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 468095d67482SBill Paul 468195d67482SBill Paul /* 468295d67482SBill Paul * Shut down all of the memory managers and related 468395d67482SBill Paul * state machines. 468495d67482SBill Paul */ 468595d67482SBill Paul BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 468695d67482SBill Paul BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 46877ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 468895d67482SBill Paul BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 46890c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 469095d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 46917ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 469295d67482SBill Paul BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 469395d67482SBill Paul BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 46940434d1b8SBill Paul } 469595d67482SBill Paul 46968cb1383cSDoug Ambrisko bge_reset(sc); 46978cb1383cSDoug Ambrisko bge_sig_legacy(sc, BGE_RESET_STOP); 46988cb1383cSDoug Ambrisko bge_sig_post_reset(sc, BGE_RESET_STOP); 46998cb1383cSDoug Ambrisko 47008cb1383cSDoug Ambrisko /* 47018cb1383cSDoug Ambrisko * Keep the ASF firmware running if up. 47028cb1383cSDoug Ambrisko */ 47038cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 47048cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 47058cb1383cSDoug Ambrisko else 470695d67482SBill Paul BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 470795d67482SBill Paul 470895d67482SBill Paul /* Free the RX lists. */ 470995d67482SBill Paul bge_free_rx_ring_std(sc); 471095d67482SBill Paul 471195d67482SBill Paul /* Free jumbo RX list. */ 47124c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) 471395d67482SBill Paul bge_free_rx_ring_jumbo(sc); 471495d67482SBill Paul 471595d67482SBill Paul /* Free TX buffers. */ 471695d67482SBill Paul bge_free_tx_ring(sc); 471795d67482SBill Paul 471895d67482SBill Paul sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 471995d67482SBill Paul 47205dda8085SOleg Bulyzhin /* Clear MAC's link state (PHY may still have link UP). */ 47211493e883SOleg Bulyzhin if (bootverbose && sc->bge_link) 47221493e883SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 47231493e883SOleg Bulyzhin sc->bge_link = 0; 472495d67482SBill Paul 47251493e883SOleg Bulyzhin ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 472695d67482SBill Paul } 472795d67482SBill Paul 472895d67482SBill Paul /* 472995d67482SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 473095d67482SBill Paul * get confused by errant DMAs when rebooting. 473195d67482SBill Paul */ 4732b6c974e8SWarner Losh static int 47333f74909aSGleb Smirnoff bge_shutdown(device_t dev) 473495d67482SBill Paul { 473595d67482SBill Paul struct bge_softc *sc; 473695d67482SBill Paul 473795d67482SBill Paul sc = device_get_softc(dev); 47380f9bd73bSSam Leffler BGE_LOCK(sc); 473995d67482SBill Paul bge_stop(sc); 474095d67482SBill Paul bge_reset(sc); 47410f9bd73bSSam Leffler BGE_UNLOCK(sc); 4742b6c974e8SWarner Losh 4743b6c974e8SWarner Losh return (0); 474495d67482SBill Paul } 474514afefa3SPawel Jakub Dawidek 474614afefa3SPawel Jakub Dawidek static int 474714afefa3SPawel Jakub Dawidek bge_suspend(device_t dev) 474814afefa3SPawel Jakub Dawidek { 474914afefa3SPawel Jakub Dawidek struct bge_softc *sc; 475014afefa3SPawel Jakub Dawidek 475114afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 475214afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 475314afefa3SPawel Jakub Dawidek bge_stop(sc); 475414afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 475514afefa3SPawel Jakub Dawidek 475614afefa3SPawel Jakub Dawidek return (0); 475714afefa3SPawel Jakub Dawidek } 475814afefa3SPawel Jakub Dawidek 475914afefa3SPawel Jakub Dawidek static int 476014afefa3SPawel Jakub Dawidek bge_resume(device_t dev) 476114afefa3SPawel Jakub Dawidek { 476214afefa3SPawel Jakub Dawidek struct bge_softc *sc; 476314afefa3SPawel Jakub Dawidek struct ifnet *ifp; 476414afefa3SPawel Jakub Dawidek 476514afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 476614afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 476714afefa3SPawel Jakub Dawidek ifp = sc->bge_ifp; 476814afefa3SPawel Jakub Dawidek if (ifp->if_flags & IFF_UP) { 476914afefa3SPawel Jakub Dawidek bge_init_locked(sc); 477014afefa3SPawel Jakub Dawidek if (ifp->if_drv_flags & IFF_DRV_RUNNING) 477114afefa3SPawel Jakub Dawidek bge_start_locked(ifp); 477214afefa3SPawel Jakub Dawidek } 477314afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 477414afefa3SPawel Jakub Dawidek 477514afefa3SPawel Jakub Dawidek return (0); 477614afefa3SPawel Jakub Dawidek } 4777dab5cd05SOleg Bulyzhin 4778dab5cd05SOleg Bulyzhin static void 47793f74909aSGleb Smirnoff bge_link_upd(struct bge_softc *sc) 4780dab5cd05SOleg Bulyzhin { 47811f313773SOleg Bulyzhin struct mii_data *mii; 47821f313773SOleg Bulyzhin uint32_t link, status; 4783dab5cd05SOleg Bulyzhin 4784dab5cd05SOleg Bulyzhin BGE_LOCK_ASSERT(sc); 47851f313773SOleg Bulyzhin 47863f74909aSGleb Smirnoff /* Clear 'pending link event' flag. */ 47877b97099dSOleg Bulyzhin sc->bge_link_evt = 0; 47887b97099dSOleg Bulyzhin 4789dab5cd05SOleg Bulyzhin /* 4790dab5cd05SOleg Bulyzhin * Process link state changes. 4791dab5cd05SOleg Bulyzhin * Grrr. The link status word in the status block does 4792dab5cd05SOleg Bulyzhin * not work correctly on the BCM5700 rev AX and BX chips, 4793dab5cd05SOleg Bulyzhin * according to all available information. Hence, we have 4794dab5cd05SOleg Bulyzhin * to enable MII interrupts in order to properly obtain 4795dab5cd05SOleg Bulyzhin * async link changes. Unfortunately, this also means that 4796dab5cd05SOleg Bulyzhin * we have to read the MAC status register to detect link 4797dab5cd05SOleg Bulyzhin * changes, thereby adding an additional register access to 4798dab5cd05SOleg Bulyzhin * the interrupt handler. 47991f313773SOleg Bulyzhin * 48001f313773SOleg Bulyzhin * XXX: perhaps link state detection procedure used for 48014c0da0ffSGleb Smirnoff * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4802dab5cd05SOleg Bulyzhin */ 4803dab5cd05SOleg Bulyzhin 48041f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 48054c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4806dab5cd05SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 4807dab5cd05SOleg Bulyzhin if (status & BGE_MACSTAT_MI_INTERRUPT) { 48081f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 48095dda8085SOleg Bulyzhin mii_pollstat(mii); 48101f313773SOleg Bulyzhin if (!sc->bge_link && 48111f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 48121f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 48131f313773SOleg Bulyzhin sc->bge_link++; 48141f313773SOleg Bulyzhin if (bootverbose) 48151f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 48161f313773SOleg Bulyzhin } else if (sc->bge_link && 48171f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 48181f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 48191f313773SOleg Bulyzhin sc->bge_link = 0; 48201f313773SOleg Bulyzhin if (bootverbose) 48211f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 48221f313773SOleg Bulyzhin } 48231f313773SOleg Bulyzhin 48243f74909aSGleb Smirnoff /* Clear the interrupt. */ 4825dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4826dab5cd05SOleg Bulyzhin BGE_EVTENB_MI_INTERRUPT); 4827dab5cd05SOleg Bulyzhin bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4828dab5cd05SOleg Bulyzhin bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4829dab5cd05SOleg Bulyzhin BRGPHY_INTRS); 4830dab5cd05SOleg Bulyzhin } 4831dab5cd05SOleg Bulyzhin return; 4832dab5cd05SOleg Bulyzhin } 4833dab5cd05SOleg Bulyzhin 4834652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 48351f313773SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 48367b97099dSOleg Bulyzhin if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 48377b97099dSOleg Bulyzhin if (!sc->bge_link) { 48381f313773SOleg Bulyzhin sc->bge_link++; 48391f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 48401f313773SOleg Bulyzhin BGE_CLRBIT(sc, BGE_MAC_MODE, 48411f313773SOleg Bulyzhin BGE_MACMODE_TBI_SEND_CFGS); 48420c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 48431f313773SOleg Bulyzhin if (bootverbose) 48441f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 48453f74909aSGleb Smirnoff if_link_state_change(sc->bge_ifp, 48463f74909aSGleb Smirnoff LINK_STATE_UP); 48477b97099dSOleg Bulyzhin } 48481f313773SOleg Bulyzhin } else if (sc->bge_link) { 4849dab5cd05SOleg Bulyzhin sc->bge_link = 0; 48501f313773SOleg Bulyzhin if (bootverbose) 48511f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 48527b97099dSOleg Bulyzhin if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 48531f313773SOleg Bulyzhin } 48541493e883SOleg Bulyzhin } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 48551f313773SOleg Bulyzhin /* 48560c8aa4eaSJung-uk Kim * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 48570c8aa4eaSJung-uk Kim * in status word always set. Workaround this bug by reading 48580c8aa4eaSJung-uk Kim * PHY link status directly. 48591f313773SOleg Bulyzhin */ 48601f313773SOleg Bulyzhin link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 48611f313773SOleg Bulyzhin 48621f313773SOleg Bulyzhin if (link != sc->bge_link || 48631f313773SOleg Bulyzhin sc->bge_asicrev == BGE_ASICREV_BCM5700) { 48641f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 48655dda8085SOleg Bulyzhin mii_pollstat(mii); 48661f313773SOleg Bulyzhin if (!sc->bge_link && 48671f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 48681f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 48691f313773SOleg Bulyzhin sc->bge_link++; 48701f313773SOleg Bulyzhin if (bootverbose) 48711f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 48721f313773SOleg Bulyzhin } else if (sc->bge_link && 48731f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 48741f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 48751f313773SOleg Bulyzhin sc->bge_link = 0; 48761f313773SOleg Bulyzhin if (bootverbose) 48771f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 48781f313773SOleg Bulyzhin } 48791f313773SOleg Bulyzhin } 48800c8aa4eaSJung-uk Kim } else { 48810c8aa4eaSJung-uk Kim /* 48820c8aa4eaSJung-uk Kim * Discard link events for MII/GMII controllers 48830c8aa4eaSJung-uk Kim * if MI auto-polling is disabled. 48840c8aa4eaSJung-uk Kim */ 4885dab5cd05SOleg Bulyzhin } 4886dab5cd05SOleg Bulyzhin 48873f74909aSGleb Smirnoff /* Clear the attention. */ 4888dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4889dab5cd05SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4890dab5cd05SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 4891dab5cd05SOleg Bulyzhin } 48926f8718a3SScott Long 4893763757b2SScott Long #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 489406e83c7eSScott Long SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4895763757b2SScott Long sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4896763757b2SScott Long desc) 4897763757b2SScott Long 48986f8718a3SScott Long static void 48996f8718a3SScott Long bge_add_sysctls(struct bge_softc *sc) 49006f8718a3SScott Long { 49016f8718a3SScott Long struct sysctl_ctx_list *ctx; 4902763757b2SScott Long struct sysctl_oid_list *children, *schildren; 4903763757b2SScott Long struct sysctl_oid *tree; 49046f8718a3SScott Long 49056f8718a3SScott Long ctx = device_get_sysctl_ctx(sc->bge_dev); 49066f8718a3SScott Long children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 49076f8718a3SScott Long 49086f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 49096f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 49106f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 49116f8718a3SScott Long "Debug Information"); 49126f8718a3SScott Long 49136f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 49146f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 49156f8718a3SScott Long "Register Read"); 49166f8718a3SScott Long 49176f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 49186f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 49196f8718a3SScott Long "Memory Read"); 49206f8718a3SScott Long 49216f8718a3SScott Long #endif 4922763757b2SScott Long 4923beaa2ae1SPyun YongHyeon /* 4924beaa2ae1SPyun YongHyeon * A common design characteristic for many Broadcom client controllers 4925beaa2ae1SPyun YongHyeon * is that they only support a single outstanding DMA read operation 4926beaa2ae1SPyun YongHyeon * on the PCIe bus. This means that it will take twice as long to fetch 4927beaa2ae1SPyun YongHyeon * a TX frame that is split into header and payload buffers as it does 4928beaa2ae1SPyun YongHyeon * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 4929beaa2ae1SPyun YongHyeon * these controllers, coalescing buffers to reduce the number of memory 4930beaa2ae1SPyun YongHyeon * reads is effective way to get maximum performance(about 940Mbps). 4931beaa2ae1SPyun YongHyeon * Without collapsing TX buffers the maximum TCP bulk transfer 4932beaa2ae1SPyun YongHyeon * performance is about 850Mbps. However forcing coalescing mbufs 4933beaa2ae1SPyun YongHyeon * consumes a lot of CPU cycles, so leave it off by default. 4934beaa2ae1SPyun YongHyeon */ 4935beaa2ae1SPyun YongHyeon SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 4936beaa2ae1SPyun YongHyeon CTLFLAG_RW, &sc->bge_forced_collapse, 0, 4937beaa2ae1SPyun YongHyeon "Number of fragmented TX buffers of a frame allowed before " 4938beaa2ae1SPyun YongHyeon "forced collapsing"); 4939beaa2ae1SPyun YongHyeon resource_int_value(device_get_name(sc->bge_dev), 4940beaa2ae1SPyun YongHyeon device_get_unit(sc->bge_dev), "forced_collapse", 4941beaa2ae1SPyun YongHyeon &sc->bge_forced_collapse); 4942beaa2ae1SPyun YongHyeon 4943d949071dSJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 4944d949071dSJung-uk Kim return; 4945d949071dSJung-uk Kim 4946763757b2SScott Long tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4947763757b2SScott Long NULL, "BGE Statistics"); 4948763757b2SScott Long schildren = children = SYSCTL_CHILDREN(tree); 4949763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4950763757b2SScott Long children, COSFramesDroppedDueToFilters, 4951763757b2SScott Long "FramesDroppedDueToFilters"); 4952763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4953763757b2SScott Long children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4954763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4955763757b2SScott Long children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4956763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4957763757b2SScott Long children, nicNoMoreRxBDs, "NoMoreRxBDs"); 495806e83c7eSScott Long BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 495906e83c7eSScott Long children, ifInDiscards, "InputDiscards"); 496006e83c7eSScott Long BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 496106e83c7eSScott Long children, ifInErrors, "InputErrors"); 4962763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4963763757b2SScott Long children, nicRecvThresholdHit, "RecvThresholdHit"); 4964763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4965763757b2SScott Long children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4966763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4967763757b2SScott Long children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4968763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4969763757b2SScott Long children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4970763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4971763757b2SScott Long children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4972763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4973763757b2SScott Long children, nicRingStatusUpdate, "RingStatusUpdate"); 4974763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4975763757b2SScott Long children, nicInterrupts, "Interrupts"); 4976763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4977763757b2SScott Long children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4978763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4979763757b2SScott Long children, nicSendThresholdHit, "SendThresholdHit"); 4980763757b2SScott Long 4981763757b2SScott Long tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4982763757b2SScott Long NULL, "BGE RX Statistics"); 4983763757b2SScott Long children = SYSCTL_CHILDREN(tree); 4984763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4985763757b2SScott Long children, rxstats.ifHCInOctets, "Octets"); 4986763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4987763757b2SScott Long children, rxstats.etherStatsFragments, "Fragments"); 4988763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4989763757b2SScott Long children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4990763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4991763757b2SScott Long children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4992763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4993763757b2SScott Long children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4994763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4995763757b2SScott Long children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4996763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4997763757b2SScott Long children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4998763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4999763757b2SScott Long children, rxstats.xoffPauseFramesReceived, 5000763757b2SScott Long "xoffPauseFramesReceived"); 5001763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5002763757b2SScott Long children, rxstats.macControlFramesReceived, 5003763757b2SScott Long "ControlFramesReceived"); 5004763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5005763757b2SScott Long children, rxstats.xoffStateEntered, "xoffStateEntered"); 5006763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5007763757b2SScott Long children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5008763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5009763757b2SScott Long children, rxstats.etherStatsJabbers, "Jabbers"); 5010763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5011763757b2SScott Long children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5012763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 501306e83c7eSScott Long children, rxstats.inRangeLengthError, "inRangeLengthError"); 5014763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 501506e83c7eSScott Long children, rxstats.outRangeLengthError, "outRangeLengthError"); 5016763757b2SScott Long 5017763757b2SScott Long tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5018763757b2SScott Long NULL, "BGE TX Statistics"); 5019763757b2SScott Long children = SYSCTL_CHILDREN(tree); 5020763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5021763757b2SScott Long children, txstats.ifHCOutOctets, "Octets"); 5022763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5023763757b2SScott Long children, txstats.etherStatsCollisions, "Collisions"); 5024763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5025763757b2SScott Long children, txstats.outXonSent, "XonSent"); 5026763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5027763757b2SScott Long children, txstats.outXoffSent, "XoffSent"); 5028763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5029763757b2SScott Long children, txstats.flowControlDone, "flowControlDone"); 5030763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5031763757b2SScott Long children, txstats.dot3StatsInternalMacTransmitErrors, 5032763757b2SScott Long "InternalMacTransmitErrors"); 5033763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5034763757b2SScott Long children, txstats.dot3StatsSingleCollisionFrames, 5035763757b2SScott Long "SingleCollisionFrames"); 5036763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5037763757b2SScott Long children, txstats.dot3StatsMultipleCollisionFrames, 5038763757b2SScott Long "MultipleCollisionFrames"); 5039763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5040763757b2SScott Long children, txstats.dot3StatsDeferredTransmissions, 5041763757b2SScott Long "DeferredTransmissions"); 5042763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5043763757b2SScott Long children, txstats.dot3StatsExcessiveCollisions, 5044763757b2SScott Long "ExcessiveCollisions"); 5045763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 504606e83c7eSScott Long children, txstats.dot3StatsLateCollisions, 504706e83c7eSScott Long "LateCollisions"); 5048763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5049763757b2SScott Long children, txstats.ifHCOutUcastPkts, "UcastPkts"); 5050763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5051763757b2SScott Long children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5052763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5053763757b2SScott Long children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5054763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5055763757b2SScott Long children, txstats.dot3StatsCarrierSenseErrors, 5056763757b2SScott Long "CarrierSenseErrors"); 5057763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5058763757b2SScott Long children, txstats.ifOutDiscards, "Discards"); 5059763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5060763757b2SScott Long children, txstats.ifOutErrors, "Errors"); 5061763757b2SScott Long } 5062763757b2SScott Long 5063763757b2SScott Long static int 5064763757b2SScott Long bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5065763757b2SScott Long { 5066763757b2SScott Long struct bge_softc *sc; 506706e83c7eSScott Long uint32_t result; 5068d949071dSJung-uk Kim int offset; 5069763757b2SScott Long 5070763757b2SScott Long sc = (struct bge_softc *)arg1; 5071763757b2SScott Long offset = arg2; 5072d949071dSJung-uk Kim result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5073d949071dSJung-uk Kim offsetof(bge_hostaddr, bge_addr_lo)); 5074041b706bSDavid Malone return (sysctl_handle_int(oidp, &result, 0, req)); 50756f8718a3SScott Long } 50766f8718a3SScott Long 50776f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 50786f8718a3SScott Long static int 50796f8718a3SScott Long bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 50806f8718a3SScott Long { 50816f8718a3SScott Long struct bge_softc *sc; 50826f8718a3SScott Long uint16_t *sbdata; 50836f8718a3SScott Long int error; 50846f8718a3SScott Long int result; 50856f8718a3SScott Long int i, j; 50866f8718a3SScott Long 50876f8718a3SScott Long result = -1; 50886f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 50896f8718a3SScott Long if (error || (req->newptr == NULL)) 50906f8718a3SScott Long return (error); 50916f8718a3SScott Long 50926f8718a3SScott Long if (result == 1) { 50936f8718a3SScott Long sc = (struct bge_softc *)arg1; 50946f8718a3SScott Long 50956f8718a3SScott Long sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 50966f8718a3SScott Long printf("Status Block:\n"); 50976f8718a3SScott Long for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 50986f8718a3SScott Long printf("%06x:", i); 50996f8718a3SScott Long for (j = 0; j < 8; j++) { 51006f8718a3SScott Long printf(" %04x", sbdata[i]); 51016f8718a3SScott Long i += 4; 51026f8718a3SScott Long } 51036f8718a3SScott Long printf("\n"); 51046f8718a3SScott Long } 51056f8718a3SScott Long 51066f8718a3SScott Long printf("Registers:\n"); 51070c8aa4eaSJung-uk Kim for (i = 0x800; i < 0xA00; ) { 51086f8718a3SScott Long printf("%06x:", i); 51096f8718a3SScott Long for (j = 0; j < 8; j++) { 51106f8718a3SScott Long printf(" %08x", CSR_READ_4(sc, i)); 51116f8718a3SScott Long i += 4; 51126f8718a3SScott Long } 51136f8718a3SScott Long printf("\n"); 51146f8718a3SScott Long } 51156f8718a3SScott Long 51166f8718a3SScott Long printf("Hardware Flags:\n"); 5117a5779553SStanislav Sedov if (BGE_IS_5755_PLUS(sc)) 5118a5779553SStanislav Sedov printf(" - 5755 Plus\n"); 51195345bad0SScott Long if (BGE_IS_575X_PLUS(sc)) 51206f8718a3SScott Long printf(" - 575X Plus\n"); 51215345bad0SScott Long if (BGE_IS_5705_PLUS(sc)) 51226f8718a3SScott Long printf(" - 5705 Plus\n"); 51235345bad0SScott Long if (BGE_IS_5714_FAMILY(sc)) 51245345bad0SScott Long printf(" - 5714 Family\n"); 51255345bad0SScott Long if (BGE_IS_5700_FAMILY(sc)) 51265345bad0SScott Long printf(" - 5700 Family\n"); 51276f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_JUMBO) 51286f8718a3SScott Long printf(" - Supports Jumbo Frames\n"); 51296f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIX) 51306f8718a3SScott Long printf(" - PCI-X Bus\n"); 51316f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIE) 51326f8718a3SScott Long printf(" - PCI Express Bus\n"); 51335ee49a3aSJung-uk Kim if (sc->bge_flags & BGE_FLAG_NO_3LED) 51346f8718a3SScott Long printf(" - No 3 LEDs\n"); 51356f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 51366f8718a3SScott Long printf(" - RX Alignment Bug\n"); 51376f8718a3SScott Long } 51386f8718a3SScott Long 51396f8718a3SScott Long return (error); 51406f8718a3SScott Long } 51416f8718a3SScott Long 51426f8718a3SScott Long static int 51436f8718a3SScott Long bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 51446f8718a3SScott Long { 51456f8718a3SScott Long struct bge_softc *sc; 51466f8718a3SScott Long int error; 51476f8718a3SScott Long uint16_t result; 51486f8718a3SScott Long uint32_t val; 51496f8718a3SScott Long 51506f8718a3SScott Long result = -1; 51516f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 51526f8718a3SScott Long if (error || (req->newptr == NULL)) 51536f8718a3SScott Long return (error); 51546f8718a3SScott Long 51556f8718a3SScott Long if (result < 0x8000) { 51566f8718a3SScott Long sc = (struct bge_softc *)arg1; 51576f8718a3SScott Long val = CSR_READ_4(sc, result); 51586f8718a3SScott Long printf("reg 0x%06X = 0x%08X\n", result, val); 51596f8718a3SScott Long } 51606f8718a3SScott Long 51616f8718a3SScott Long return (error); 51626f8718a3SScott Long } 51636f8718a3SScott Long 51646f8718a3SScott Long static int 51656f8718a3SScott Long bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 51666f8718a3SScott Long { 51676f8718a3SScott Long struct bge_softc *sc; 51686f8718a3SScott Long int error; 51696f8718a3SScott Long uint16_t result; 51706f8718a3SScott Long uint32_t val; 51716f8718a3SScott Long 51726f8718a3SScott Long result = -1; 51736f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 51746f8718a3SScott Long if (error || (req->newptr == NULL)) 51756f8718a3SScott Long return (error); 51766f8718a3SScott Long 51776f8718a3SScott Long if (result < 0x8000) { 51786f8718a3SScott Long sc = (struct bge_softc *)arg1; 51796f8718a3SScott Long val = bge_readmem_ind(sc, result); 51806f8718a3SScott Long printf("mem 0x%06X = 0x%08X\n", result, val); 51816f8718a3SScott Long } 51826f8718a3SScott Long 51836f8718a3SScott Long return (error); 51846f8718a3SScott Long } 51856f8718a3SScott Long #endif 518638cc658fSJohn Baldwin 518738cc658fSJohn Baldwin static int 51885fea260fSMarius Strobl bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 51895fea260fSMarius Strobl { 51905fea260fSMarius Strobl 51915fea260fSMarius Strobl if (sc->bge_flags & BGE_FLAG_EADDR) 51925fea260fSMarius Strobl return (1); 51935fea260fSMarius Strobl 51945fea260fSMarius Strobl #ifdef __sparc64__ 51955fea260fSMarius Strobl OF_getetheraddr(sc->bge_dev, ether_addr); 51965fea260fSMarius Strobl return (0); 51975fea260fSMarius Strobl #endif 51985fea260fSMarius Strobl return (1); 51995fea260fSMarius Strobl } 52005fea260fSMarius Strobl 52015fea260fSMarius Strobl static int 520238cc658fSJohn Baldwin bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 520338cc658fSJohn Baldwin { 520438cc658fSJohn Baldwin uint32_t mac_addr; 520538cc658fSJohn Baldwin 520638cc658fSJohn Baldwin mac_addr = bge_readmem_ind(sc, 0x0c14); 520738cc658fSJohn Baldwin if ((mac_addr >> 16) == 0x484b) { 520838cc658fSJohn Baldwin ether_addr[0] = (uint8_t)(mac_addr >> 8); 520938cc658fSJohn Baldwin ether_addr[1] = (uint8_t)mac_addr; 521038cc658fSJohn Baldwin mac_addr = bge_readmem_ind(sc, 0x0c18); 521138cc658fSJohn Baldwin ether_addr[2] = (uint8_t)(mac_addr >> 24); 521238cc658fSJohn Baldwin ether_addr[3] = (uint8_t)(mac_addr >> 16); 521338cc658fSJohn Baldwin ether_addr[4] = (uint8_t)(mac_addr >> 8); 521438cc658fSJohn Baldwin ether_addr[5] = (uint8_t)mac_addr; 52155fea260fSMarius Strobl return (0); 521638cc658fSJohn Baldwin } 52175fea260fSMarius Strobl return (1); 521838cc658fSJohn Baldwin } 521938cc658fSJohn Baldwin 522038cc658fSJohn Baldwin static int 522138cc658fSJohn Baldwin bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 522238cc658fSJohn Baldwin { 522338cc658fSJohn Baldwin int mac_offset = BGE_EE_MAC_OFFSET; 522438cc658fSJohn Baldwin 522538cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 522638cc658fSJohn Baldwin mac_offset = BGE_EE_MAC_OFFSET_5906; 522738cc658fSJohn Baldwin 52285fea260fSMarius Strobl return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 52295fea260fSMarius Strobl ETHER_ADDR_LEN)); 523038cc658fSJohn Baldwin } 523138cc658fSJohn Baldwin 523238cc658fSJohn Baldwin static int 523338cc658fSJohn Baldwin bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 523438cc658fSJohn Baldwin { 523538cc658fSJohn Baldwin 52365fea260fSMarius Strobl if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 52375fea260fSMarius Strobl return (1); 52385fea260fSMarius Strobl 52395fea260fSMarius Strobl return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 52405fea260fSMarius Strobl ETHER_ADDR_LEN)); 524138cc658fSJohn Baldwin } 524238cc658fSJohn Baldwin 524338cc658fSJohn Baldwin static int 524438cc658fSJohn Baldwin bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 524538cc658fSJohn Baldwin { 524638cc658fSJohn Baldwin static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 524738cc658fSJohn Baldwin /* NOTE: Order is critical */ 52485fea260fSMarius Strobl bge_get_eaddr_fw, 524938cc658fSJohn Baldwin bge_get_eaddr_mem, 525038cc658fSJohn Baldwin bge_get_eaddr_nvram, 525138cc658fSJohn Baldwin bge_get_eaddr_eeprom, 525238cc658fSJohn Baldwin NULL 525338cc658fSJohn Baldwin }; 525438cc658fSJohn Baldwin const bge_eaddr_fcn_t *func; 525538cc658fSJohn Baldwin 525638cc658fSJohn Baldwin for (func = bge_eaddr_funcs; *func != NULL; ++func) { 525738cc658fSJohn Baldwin if ((*func)(sc, eaddr) == 0) 525838cc658fSJohn Baldwin break; 525938cc658fSJohn Baldwin } 526038cc658fSJohn Baldwin return (*func == NULL ? ENXIO : 0); 526138cc658fSJohn Baldwin } 5262