1098ca2bdSWarner Losh /*- 295d67482SBill Paul * Copyright (c) 2001 Wind River Systems 395d67482SBill Paul * Copyright (c) 1997, 1998, 1999, 2001 495d67482SBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 595d67482SBill Paul * 695d67482SBill Paul * Redistribution and use in source and binary forms, with or without 795d67482SBill Paul * modification, are permitted provided that the following conditions 895d67482SBill Paul * are met: 995d67482SBill Paul * 1. Redistributions of source code must retain the above copyright 1095d67482SBill Paul * notice, this list of conditions and the following disclaimer. 1195d67482SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1295d67482SBill Paul * notice, this list of conditions and the following disclaimer in the 1395d67482SBill Paul * documentation and/or other materials provided with the distribution. 1495d67482SBill Paul * 3. All advertising materials mentioning features or use of this software 1595d67482SBill Paul * must display the following acknowledgement: 1695d67482SBill Paul * This product includes software developed by Bill Paul. 1795d67482SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1895d67482SBill Paul * may be used to endorse or promote products derived from this software 1995d67482SBill Paul * without specific prior written permission. 2095d67482SBill Paul * 2195d67482SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2295d67482SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2395d67482SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2495d67482SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2595d67482SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2695d67482SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2795d67482SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2895d67482SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2995d67482SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3095d67482SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3195d67482SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3295d67482SBill Paul */ 3395d67482SBill Paul 34aad970f1SDavid E. O'Brien #include <sys/cdefs.h> 35aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$"); 36aad970f1SDavid E. O'Brien 3795d67482SBill Paul /* 3895d67482SBill Paul * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 3995d67482SBill Paul * 4095d67482SBill Paul * The Broadcom BCM5700 is based on technology originally developed by 4195d67482SBill Paul * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 4295d67482SBill Paul * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 4395d67482SBill Paul * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 4495d67482SBill Paul * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 4595d67482SBill Paul * frames, highly configurable RX filtering, and 16 RX and TX queues 4695d67482SBill Paul * (which, along with RX filter rules, can be used for QOS applications). 4795d67482SBill Paul * Other features, such as TCP segmentation, may be available as part 4895d67482SBill Paul * of value-added firmware updates. Unlike the Tigon I and Tigon II, 4995d67482SBill Paul * firmware images can be stored in hardware and need not be compiled 5095d67482SBill Paul * into the driver. 5195d67482SBill Paul * 5295d67482SBill Paul * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 5395d67482SBill Paul * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 5495d67482SBill Paul * 5595d67482SBill Paul * The BCM5701 is a single-chip solution incorporating both the BCM5700 5698b28ee5SBill Paul * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 5795d67482SBill Paul * does not support external SSRAM. 5895d67482SBill Paul * 5995d67482SBill Paul * Broadcom also produces a variation of the BCM5700 under the "Altima" 6095d67482SBill Paul * brand name, which is functionally similar but lacks PCI-X support. 6195d67482SBill Paul * 6295d67482SBill Paul * Without external SSRAM, you can only have at most 4 TX rings, 6395d67482SBill Paul * and the use of the mini RX ring is disabled. This seems to imply 6495d67482SBill Paul * that these features are simply not available on the BCM5701. As a 6595d67482SBill Paul * result, this driver does not implement any support for the mini RX 6695d67482SBill Paul * ring. 6795d67482SBill Paul */ 6895d67482SBill Paul 6975719184SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 7075719184SGleb Smirnoff #include "opt_device_polling.h" 7175719184SGleb Smirnoff #endif 7275719184SGleb Smirnoff 7395d67482SBill Paul #include <sys/param.h> 74f41ac2beSBill Paul #include <sys/endian.h> 7595d67482SBill Paul #include <sys/systm.h> 7695d67482SBill Paul #include <sys/sockio.h> 7795d67482SBill Paul #include <sys/mbuf.h> 7895d67482SBill Paul #include <sys/malloc.h> 7995d67482SBill Paul #include <sys/kernel.h> 80fe12f24bSPoul-Henning Kamp #include <sys/module.h> 8195d67482SBill Paul #include <sys/socket.h> 8295d67482SBill Paul 8395d67482SBill Paul #include <net/if.h> 8495d67482SBill Paul #include <net/if_arp.h> 8595d67482SBill Paul #include <net/ethernet.h> 8695d67482SBill Paul #include <net/if_dl.h> 8795d67482SBill Paul #include <net/if_media.h> 8895d67482SBill Paul 8995d67482SBill Paul #include <net/bpf.h> 9095d67482SBill Paul 9195d67482SBill Paul #include <net/if_types.h> 9295d67482SBill Paul #include <net/if_vlan_var.h> 9395d67482SBill Paul 9495d67482SBill Paul #include <netinet/in_systm.h> 9595d67482SBill Paul #include <netinet/in.h> 9695d67482SBill Paul #include <netinet/ip.h> 9795d67482SBill Paul 9895d67482SBill Paul #include <machine/bus.h> 9995d67482SBill Paul #include <machine/resource.h> 10095d67482SBill Paul #include <sys/bus.h> 10195d67482SBill Paul #include <sys/rman.h> 10295d67482SBill Paul 10395d67482SBill Paul #include <dev/mii/mii.h> 10495d67482SBill Paul #include <dev/mii/miivar.h> 1052d3ce713SDavid E. O'Brien #include "miidevs.h" 10695d67482SBill Paul #include <dev/mii/brgphyreg.h> 10795d67482SBill Paul 1084fbd232cSWarner Losh #include <dev/pci/pcireg.h> 1094fbd232cSWarner Losh #include <dev/pci/pcivar.h> 11095d67482SBill Paul 11195d67482SBill Paul #include <dev/bge/if_bgereg.h> 11295d67482SBill Paul 1135ddc5794SJohn Polstra #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 114d375e524SGleb Smirnoff #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 11595d67482SBill Paul 116f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, pci, 1, 1, 1); 117f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, ether, 1, 1, 1); 11895d67482SBill Paul MODULE_DEPEND(bge, miibus, 1, 1, 1); 11995d67482SBill Paul 1207b279558SWarner Losh /* "device miibus" required. See GENERIC if you get errors here. */ 12195d67482SBill Paul #include "miibus_if.h" 12295d67482SBill Paul 12395d67482SBill Paul /* 12495d67482SBill Paul * Various supported device vendors/types and their names. Note: the 12595d67482SBill Paul * spec seems to indicate that the hardware still has Alteon's vendor 12695d67482SBill Paul * ID burned into it, though it will always be overriden by the vendor 12795d67482SBill Paul * ID in the EEPROM. Just to be safe, we cover all possibilities. 12895d67482SBill Paul */ 1294c0da0ffSGleb Smirnoff static struct bge_type { 1304c0da0ffSGleb Smirnoff uint16_t bge_vid; 1314c0da0ffSGleb Smirnoff uint16_t bge_did; 1324c0da0ffSGleb Smirnoff } bge_devs[] = { 1334c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 1344c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 13595d67482SBill Paul 1364c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 1374c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 1384c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 1394c0da0ffSGleb Smirnoff 1404c0da0ffSGleb Smirnoff { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 1414c0da0ffSGleb Smirnoff 1424c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 1434c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 1444c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 1454c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 1464c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 1474c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 1484c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 1494c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 1504c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 1514c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 1524c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 1534c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 1544c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 1554c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 1564c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 1574c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 1584c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 1594c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 1604c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 1614c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 1624c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 1634c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 1644c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 1654c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 1664c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 1674c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 1684c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 1694c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 1704c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 1714c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 1724c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 1734c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 1744c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 1754c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 1764c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 1774c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 1784c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 1794c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 1804c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 1814c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 1824c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 1834c0da0ffSGleb Smirnoff 1844c0da0ffSGleb Smirnoff { SK_VENDORID, SK_DEVICEID_ALTIMA }, 1854c0da0ffSGleb Smirnoff 1864c0da0ffSGleb Smirnoff { TC_VENDORID, TC_DEVICEID_3C985 }, 1874c0da0ffSGleb Smirnoff { TC_VENDORID, TC_DEVICEID_3C996 }, 1884c0da0ffSGleb Smirnoff 1894c0da0ffSGleb Smirnoff { 0, 0 } 19095d67482SBill Paul }; 19195d67482SBill Paul 1924c0da0ffSGleb Smirnoff static const struct bge_vendor { 1934c0da0ffSGleb Smirnoff uint16_t v_id; 1944c0da0ffSGleb Smirnoff const char *v_name; 1954c0da0ffSGleb Smirnoff } bge_vendors[] = { 1964c0da0ffSGleb Smirnoff { ALTEON_VENDORID, "Alteon" }, 1974c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, "Altima" }, 1984c0da0ffSGleb Smirnoff { APPLE_VENDORID, "Apple" }, 1994c0da0ffSGleb Smirnoff { BCOM_VENDORID, "Broadcom" }, 2004c0da0ffSGleb Smirnoff { SK_VENDORID, "SysKonnect" }, 2014c0da0ffSGleb Smirnoff { TC_VENDORID, "3Com" }, 2024c0da0ffSGleb Smirnoff 2034c0da0ffSGleb Smirnoff { 0, NULL } 2044c0da0ffSGleb Smirnoff }; 2054c0da0ffSGleb Smirnoff 2064c0da0ffSGleb Smirnoff static const struct bge_revision { 2074c0da0ffSGleb Smirnoff uint32_t br_chipid; 2084c0da0ffSGleb Smirnoff const char *br_name; 2094c0da0ffSGleb Smirnoff } bge_revisions[] = { 2104c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 2114c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 2124c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 2134c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 2144c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 2154c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 2164c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 2174c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 2184c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 2194c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 2204c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 2214c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 2224c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 2234c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 2244c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 2254c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 2264c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 2274c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 2284c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 2294c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 2304c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 2314c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 2324c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 2334c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 2344c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 2354c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 2364c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 2374c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 2384c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 2394c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 2404c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 2414c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 2424c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 2434c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 2444c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 2454c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 2464c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 2474c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 2484c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 2494c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 2504c0da0ffSGleb Smirnoff 2514c0da0ffSGleb Smirnoff { 0, NULL } 2524c0da0ffSGleb Smirnoff }; 2534c0da0ffSGleb Smirnoff 2544c0da0ffSGleb Smirnoff /* 2554c0da0ffSGleb Smirnoff * Some defaults for major revisions, so that newer steppings 2564c0da0ffSGleb Smirnoff * that we don't know about have a shot at working. 2574c0da0ffSGleb Smirnoff */ 2584c0da0ffSGleb Smirnoff static const struct bge_revision bge_majorrevs[] = { 2594c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5700, 2604c0da0ffSGleb Smirnoff "unknown BCM5700" }, 2614c0da0ffSGleb Smirnoff 2624c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5701, 2634c0da0ffSGleb Smirnoff "unknown BCM5701" }, 2644c0da0ffSGleb Smirnoff 2654c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5703, 2664c0da0ffSGleb Smirnoff "unknown BCM5703" }, 2674c0da0ffSGleb Smirnoff 2684c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5704, 2694c0da0ffSGleb Smirnoff "unknown BCM5704" }, 2704c0da0ffSGleb Smirnoff 2714c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5705, 2724c0da0ffSGleb Smirnoff "unknown BCM5705" }, 2734c0da0ffSGleb Smirnoff 2744c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5750, 2754c0da0ffSGleb Smirnoff "unknown BCM5750" }, 2764c0da0ffSGleb Smirnoff 2774c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5714_A0, 2784c0da0ffSGleb Smirnoff "unknown BCM5714" }, 2794c0da0ffSGleb Smirnoff 2804c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5752, 2814c0da0ffSGleb Smirnoff "unknown BCM5752" }, 2824c0da0ffSGleb Smirnoff 2834c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5780, 2844c0da0ffSGleb Smirnoff "unknown BCM5780" }, 2854c0da0ffSGleb Smirnoff 2864c0da0ffSGleb Smirnoff { BGE_ASICREV_BCM5714, 2874c0da0ffSGleb Smirnoff "unknown BCM5714" }, 2884c0da0ffSGleb Smirnoff 2894c0da0ffSGleb Smirnoff { 0, NULL } 2904c0da0ffSGleb Smirnoff }; 2914c0da0ffSGleb Smirnoff 2924c0da0ffSGleb Smirnoff #define BGE_IS_5705_OR_BEYOND(sc) \ 2934c0da0ffSGleb Smirnoff ((sc)->bge_asicrev == BGE_ASICREV_BCM5705 || \ 2944c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5750 || \ 2954c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \ 2964c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \ 2974c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5714 || \ 2984c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5752) 2994c0da0ffSGleb Smirnoff 3004c0da0ffSGleb Smirnoff #define BGE_IS_575X_PLUS(sc) \ 3014c0da0ffSGleb Smirnoff ((sc)->bge_asicrev == BGE_ASICREV_BCM5750 || \ 3024c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \ 3034c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \ 3044c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5714 || \ 3054c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5752) 3064c0da0ffSGleb Smirnoff 3074c0da0ffSGleb Smirnoff #define BGE_IS_5714_FAMILY(sc) \ 3084c0da0ffSGleb Smirnoff ((sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \ 3094c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \ 3104c0da0ffSGleb Smirnoff (sc)->bge_asicrev == BGE_ASICREV_BCM5714) 3114c0da0ffSGleb Smirnoff 3124c0da0ffSGleb Smirnoff #define BGE_IS_JUMBO_CAPABLE(sc) \ 3134c0da0ffSGleb Smirnoff ((sc)->bge_asicrev != BGE_ASICREV_BCM5705 && \ 3144c0da0ffSGleb Smirnoff (sc)->bge_asicrev != BGE_ASICREV_BCM5750) 3154c0da0ffSGleb Smirnoff 3164c0da0ffSGleb Smirnoff const struct bge_revision * bge_lookup_rev(uint32_t); 3174c0da0ffSGleb Smirnoff const struct bge_vendor * bge_lookup_vendor(uint16_t); 318e51a25f8SAlfred Perlstein static int bge_probe(device_t); 319e51a25f8SAlfred Perlstein static int bge_attach(device_t); 320e51a25f8SAlfred Perlstein static int bge_detach(device_t); 32114afefa3SPawel Jakub Dawidek static int bge_suspend(device_t); 32214afefa3SPawel Jakub Dawidek static int bge_resume(device_t); 3233f74909aSGleb Smirnoff static void bge_release_resources(struct bge_softc *); 324f41ac2beSBill Paul static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 325f41ac2beSBill Paul static int bge_dma_alloc(device_t); 326f41ac2beSBill Paul static void bge_dma_free(struct bge_softc *); 327f41ac2beSBill Paul 328e51a25f8SAlfred Perlstein static void bge_txeof(struct bge_softc *); 329e51a25f8SAlfred Perlstein static void bge_rxeof(struct bge_softc *); 33095d67482SBill Paul 3310f9bd73bSSam Leffler static void bge_tick_locked(struct bge_softc *); 332e51a25f8SAlfred Perlstein static void bge_tick(void *); 333e51a25f8SAlfred Perlstein static void bge_stats_update(struct bge_softc *); 3343f74909aSGleb Smirnoff static void bge_stats_update_regs(struct bge_softc *); 3353f74909aSGleb Smirnoff static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 33695d67482SBill Paul 337e51a25f8SAlfred Perlstein static void bge_intr(void *); 3380f9bd73bSSam Leffler static void bge_start_locked(struct ifnet *); 339e51a25f8SAlfred Perlstein static void bge_start(struct ifnet *); 340e51a25f8SAlfred Perlstein static int bge_ioctl(struct ifnet *, u_long, caddr_t); 3410f9bd73bSSam Leffler static void bge_init_locked(struct bge_softc *); 342e51a25f8SAlfred Perlstein static void bge_init(void *); 343e51a25f8SAlfred Perlstein static void bge_stop(struct bge_softc *); 344e51a25f8SAlfred Perlstein static void bge_watchdog(struct ifnet *); 345e51a25f8SAlfred Perlstein static void bge_shutdown(device_t); 346e51a25f8SAlfred Perlstein static int bge_ifmedia_upd(struct ifnet *); 347e51a25f8SAlfred Perlstein static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 34895d67482SBill Paul 3493f74909aSGleb Smirnoff static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 350e51a25f8SAlfred Perlstein static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 35195d67482SBill Paul 352e51a25f8SAlfred Perlstein static void bge_setmulti(struct bge_softc *); 35395d67482SBill Paul 354e51a25f8SAlfred Perlstein static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 355e51a25f8SAlfred Perlstein static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 356e51a25f8SAlfred Perlstein static int bge_init_rx_ring_std(struct bge_softc *); 357e51a25f8SAlfred Perlstein static void bge_free_rx_ring_std(struct bge_softc *); 358e51a25f8SAlfred Perlstein static int bge_init_rx_ring_jumbo(struct bge_softc *); 359e51a25f8SAlfred Perlstein static void bge_free_rx_ring_jumbo(struct bge_softc *); 360e51a25f8SAlfred Perlstein static void bge_free_tx_ring(struct bge_softc *); 361e51a25f8SAlfred Perlstein static int bge_init_tx_ring(struct bge_softc *); 36295d67482SBill Paul 363e51a25f8SAlfred Perlstein static int bge_chipinit(struct bge_softc *); 364e51a25f8SAlfred Perlstein static int bge_blockinit(struct bge_softc *); 36595d67482SBill Paul 3663f74909aSGleb Smirnoff static uint32_t bge_readmem_ind(struct bge_softc *, int); 367e51a25f8SAlfred Perlstein static void bge_writemem_ind(struct bge_softc *, int, int); 36895d67482SBill Paul #ifdef notdef 3693f74909aSGleb Smirnoff static uint32_t bge_readreg_ind(struct bge_softc *, int); 37095d67482SBill Paul #endif 371e51a25f8SAlfred Perlstein static void bge_writereg_ind(struct bge_softc *, int, int); 37295d67482SBill Paul 373e51a25f8SAlfred Perlstein static int bge_miibus_readreg(device_t, int, int); 374e51a25f8SAlfred Perlstein static int bge_miibus_writereg(device_t, int, int, int); 375e51a25f8SAlfred Perlstein static void bge_miibus_statchg(device_t); 37675719184SGleb Smirnoff #ifdef DEVICE_POLLING 3773f74909aSGleb Smirnoff static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 37875719184SGleb Smirnoff #endif 37995d67482SBill Paul 380e51a25f8SAlfred Perlstein static void bge_reset(struct bge_softc *); 381dab5cd05SOleg Bulyzhin static void bge_link_upd(struct bge_softc *); 38295d67482SBill Paul 38395d67482SBill Paul static device_method_t bge_methods[] = { 38495d67482SBill Paul /* Device interface */ 38595d67482SBill Paul DEVMETHOD(device_probe, bge_probe), 38695d67482SBill Paul DEVMETHOD(device_attach, bge_attach), 38795d67482SBill Paul DEVMETHOD(device_detach, bge_detach), 38895d67482SBill Paul DEVMETHOD(device_shutdown, bge_shutdown), 38914afefa3SPawel Jakub Dawidek DEVMETHOD(device_suspend, bge_suspend), 39014afefa3SPawel Jakub Dawidek DEVMETHOD(device_resume, bge_resume), 39195d67482SBill Paul 39295d67482SBill Paul /* bus interface */ 39395d67482SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 39495d67482SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 39595d67482SBill Paul 39695d67482SBill Paul /* MII interface */ 39795d67482SBill Paul DEVMETHOD(miibus_readreg, bge_miibus_readreg), 39895d67482SBill Paul DEVMETHOD(miibus_writereg, bge_miibus_writereg), 39995d67482SBill Paul DEVMETHOD(miibus_statchg, bge_miibus_statchg), 40095d67482SBill Paul 40195d67482SBill Paul { 0, 0 } 40295d67482SBill Paul }; 40395d67482SBill Paul 40495d67482SBill Paul static driver_t bge_driver = { 40595d67482SBill Paul "bge", 40695d67482SBill Paul bge_methods, 40795d67482SBill Paul sizeof(struct bge_softc) 40895d67482SBill Paul }; 40995d67482SBill Paul 41095d67482SBill Paul static devclass_t bge_devclass; 41195d67482SBill Paul 412f246e4a1SMatthew N. Dodd DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 41395d67482SBill Paul DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 41495d67482SBill Paul 415c4529f41SMichael Reifenberger static int bge_fake_autoneg = 0; 416c4529f41SMichael Reifenberger TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 417c4529f41SMichael Reifenberger 4183f74909aSGleb Smirnoff static uint32_t 4193f74909aSGleb Smirnoff bge_readmem_ind(struct bge_softc *sc, int off) 42095d67482SBill Paul { 42195d67482SBill Paul device_t dev; 42295d67482SBill Paul 42395d67482SBill Paul dev = sc->bge_dev; 42495d67482SBill Paul 42595d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 42695d67482SBill Paul return (pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 42795d67482SBill Paul } 42895d67482SBill Paul 42995d67482SBill Paul static void 4303f74909aSGleb Smirnoff bge_writemem_ind(struct bge_softc *sc, int off, int val) 43195d67482SBill Paul { 43295d67482SBill Paul device_t dev; 43395d67482SBill Paul 43495d67482SBill Paul dev = sc->bge_dev; 43595d67482SBill Paul 43695d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 43795d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 43895d67482SBill Paul } 43995d67482SBill Paul 44095d67482SBill Paul #ifdef notdef 4413f74909aSGleb Smirnoff static uint32_t 4423f74909aSGleb Smirnoff bge_readreg_ind(struct bge_softc *sc, int off) 44395d67482SBill Paul { 44495d67482SBill Paul device_t dev; 44595d67482SBill Paul 44695d67482SBill Paul dev = sc->bge_dev; 44795d67482SBill Paul 44895d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 44995d67482SBill Paul return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 45095d67482SBill Paul } 45195d67482SBill Paul #endif 45295d67482SBill Paul 45395d67482SBill Paul static void 4543f74909aSGleb Smirnoff bge_writereg_ind(struct bge_softc *sc, int off, int val) 45595d67482SBill Paul { 45695d67482SBill Paul device_t dev; 45795d67482SBill Paul 45895d67482SBill Paul dev = sc->bge_dev; 45995d67482SBill Paul 46095d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 46195d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 46295d67482SBill Paul } 46395d67482SBill Paul 464f41ac2beSBill Paul /* 465f41ac2beSBill Paul * Map a single buffer address. 466f41ac2beSBill Paul */ 467f41ac2beSBill Paul 468f41ac2beSBill Paul static void 4693f74909aSGleb Smirnoff bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 470f41ac2beSBill Paul { 471f41ac2beSBill Paul struct bge_dmamap_arg *ctx; 472f41ac2beSBill Paul 473f41ac2beSBill Paul if (error) 474f41ac2beSBill Paul return; 475f41ac2beSBill Paul 476f41ac2beSBill Paul ctx = arg; 477f41ac2beSBill Paul 478f41ac2beSBill Paul if (nseg > ctx->bge_maxsegs) { 479f41ac2beSBill Paul ctx->bge_maxsegs = 0; 480f41ac2beSBill Paul return; 481f41ac2beSBill Paul } 482f41ac2beSBill Paul 483f41ac2beSBill Paul ctx->bge_busaddr = segs->ds_addr; 484f41ac2beSBill Paul } 485f41ac2beSBill Paul 48695d67482SBill Paul /* 48795d67482SBill Paul * Read a byte of data stored in the EEPROM at address 'addr.' The 48895d67482SBill Paul * BCM570x supports both the traditional bitbang interface and an 48995d67482SBill Paul * auto access interface for reading the EEPROM. We use the auto 49095d67482SBill Paul * access method. 49195d67482SBill Paul */ 4923f74909aSGleb Smirnoff static uint8_t 4933f74909aSGleb Smirnoff bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 49495d67482SBill Paul { 49595d67482SBill Paul int i; 4963f74909aSGleb Smirnoff uint32_t byte = 0; 49795d67482SBill Paul 49895d67482SBill Paul /* 49995d67482SBill Paul * Enable use of auto EEPROM access so we can avoid 50095d67482SBill Paul * having to use the bitbang method. 50195d67482SBill Paul */ 50295d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 50395d67482SBill Paul 50495d67482SBill Paul /* Reset the EEPROM, load the clock period. */ 50595d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, 50695d67482SBill Paul BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 50795d67482SBill Paul DELAY(20); 50895d67482SBill Paul 50995d67482SBill Paul /* Issue the read EEPROM command. */ 51095d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 51195d67482SBill Paul 51295d67482SBill Paul /* Wait for completion */ 51395d67482SBill Paul for(i = 0; i < BGE_TIMEOUT * 10; i++) { 51495d67482SBill Paul DELAY(10); 51595d67482SBill Paul if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 51695d67482SBill Paul break; 51795d67482SBill Paul } 51895d67482SBill Paul 51995d67482SBill Paul if (i == BGE_TIMEOUT) { 520fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "EEPROM read timed out\n"); 521f6789fbaSPyun YongHyeon return (1); 52295d67482SBill Paul } 52395d67482SBill Paul 52495d67482SBill Paul /* Get result. */ 52595d67482SBill Paul byte = CSR_READ_4(sc, BGE_EE_DATA); 52695d67482SBill Paul 52795d67482SBill Paul *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 52895d67482SBill Paul 52995d67482SBill Paul return (0); 53095d67482SBill Paul } 53195d67482SBill Paul 53295d67482SBill Paul /* 53395d67482SBill Paul * Read a sequence of bytes from the EEPROM. 53495d67482SBill Paul */ 53595d67482SBill Paul static int 5363f74909aSGleb Smirnoff bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 53795d67482SBill Paul { 5383f74909aSGleb Smirnoff int i, error = 0; 5393f74909aSGleb Smirnoff uint8_t byte = 0; 54095d67482SBill Paul 54195d67482SBill Paul for (i = 0; i < cnt; i++) { 5423f74909aSGleb Smirnoff error = bge_eeprom_getbyte(sc, off + i, &byte); 5433f74909aSGleb Smirnoff if (error) 54495d67482SBill Paul break; 54595d67482SBill Paul *(dest + i) = byte; 54695d67482SBill Paul } 54795d67482SBill Paul 5483f74909aSGleb Smirnoff return (error ? 1 : 0); 54995d67482SBill Paul } 55095d67482SBill Paul 55195d67482SBill Paul static int 5523f74909aSGleb Smirnoff bge_miibus_readreg(device_t dev, int phy, int reg) 55395d67482SBill Paul { 55495d67482SBill Paul struct bge_softc *sc; 5553f74909aSGleb Smirnoff uint32_t val, autopoll; 55695d67482SBill Paul int i; 55795d67482SBill Paul 55895d67482SBill Paul sc = device_get_softc(dev); 55995d67482SBill Paul 5600434d1b8SBill Paul /* 5610434d1b8SBill Paul * Broadcom's own driver always assumes the internal 5620434d1b8SBill Paul * PHY is at GMII address 1. On some chips, the PHY responds 5630434d1b8SBill Paul * to accesses at all addresses, which could cause us to 5640434d1b8SBill Paul * bogusly attach the PHY 32 times at probe type. Always 5650434d1b8SBill Paul * restricting the lookup to address 1 is simpler than 5660434d1b8SBill Paul * trying to figure out which chips revisions should be 5670434d1b8SBill Paul * special-cased. 5680434d1b8SBill Paul */ 569b1265c1aSJohn Polstra if (phy != 1) 57098b28ee5SBill Paul return (0); 57198b28ee5SBill Paul 57237ceeb4dSPaul Saab /* Reading with autopolling on may trigger PCI errors */ 57337ceeb4dSPaul Saab autopoll = CSR_READ_4(sc, BGE_MI_MODE); 57437ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 57537ceeb4dSPaul Saab BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 57637ceeb4dSPaul Saab DELAY(40); 57737ceeb4dSPaul Saab } 57837ceeb4dSPaul Saab 57995d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 58095d67482SBill Paul BGE_MIPHY(phy)|BGE_MIREG(reg)); 58195d67482SBill Paul 58295d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 58395d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 58495d67482SBill Paul if (!(val & BGE_MICOMM_BUSY)) 58595d67482SBill Paul break; 58695d67482SBill Paul } 58795d67482SBill Paul 58895d67482SBill Paul if (i == BGE_TIMEOUT) { 589fe806fdaSPyun YongHyeon if_printf(sc->bge_ifp, "PHY read timed out\n"); 59037ceeb4dSPaul Saab val = 0; 59137ceeb4dSPaul Saab goto done; 59295d67482SBill Paul } 59395d67482SBill Paul 59495d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 59595d67482SBill Paul 59637ceeb4dSPaul Saab done: 59737ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 59837ceeb4dSPaul Saab BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 59937ceeb4dSPaul Saab DELAY(40); 60037ceeb4dSPaul Saab } 60137ceeb4dSPaul Saab 60295d67482SBill Paul if (val & BGE_MICOMM_READFAIL) 60395d67482SBill Paul return (0); 60495d67482SBill Paul 60595d67482SBill Paul return (val & 0xFFFF); 60695d67482SBill Paul } 60795d67482SBill Paul 60895d67482SBill Paul static int 6093f74909aSGleb Smirnoff bge_miibus_writereg(device_t dev, int phy, int reg, int val) 61095d67482SBill Paul { 61195d67482SBill Paul struct bge_softc *sc; 6123f74909aSGleb Smirnoff uint32_t autopoll; 61395d67482SBill Paul int i; 61495d67482SBill Paul 61595d67482SBill Paul sc = device_get_softc(dev); 61695d67482SBill Paul 61737ceeb4dSPaul Saab /* Reading with autopolling on may trigger PCI errors */ 61837ceeb4dSPaul Saab autopoll = CSR_READ_4(sc, BGE_MI_MODE); 61937ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 62037ceeb4dSPaul Saab BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 62137ceeb4dSPaul Saab DELAY(40); 62237ceeb4dSPaul Saab } 62337ceeb4dSPaul Saab 62495d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 62595d67482SBill Paul BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 62695d67482SBill Paul 62795d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 62895d67482SBill Paul if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 62995d67482SBill Paul break; 63095d67482SBill Paul } 63195d67482SBill Paul 63237ceeb4dSPaul Saab if (autopoll & BGE_MIMODE_AUTOPOLL) { 63337ceeb4dSPaul Saab BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 63437ceeb4dSPaul Saab DELAY(40); 63537ceeb4dSPaul Saab } 63637ceeb4dSPaul Saab 63795d67482SBill Paul if (i == BGE_TIMEOUT) { 638fe806fdaSPyun YongHyeon if_printf(sc->bge_ifp, "PHY read timed out\n"); 63995d67482SBill Paul return (0); 64095d67482SBill Paul } 64195d67482SBill Paul 64295d67482SBill Paul return (0); 64395d67482SBill Paul } 64495d67482SBill Paul 64595d67482SBill Paul static void 6463f74909aSGleb Smirnoff bge_miibus_statchg(device_t dev) 64795d67482SBill Paul { 64895d67482SBill Paul struct bge_softc *sc; 64995d67482SBill Paul struct mii_data *mii; 65095d67482SBill Paul 65195d67482SBill Paul sc = device_get_softc(dev); 65295d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 65395d67482SBill Paul 65495d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 6553f74909aSGleb Smirnoff if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 65695d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 6573f74909aSGleb Smirnoff else 65895d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 65995d67482SBill Paul 6603f74909aSGleb Smirnoff if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 66195d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 6623f74909aSGleb Smirnoff else 66395d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 66495d67482SBill Paul } 66595d67482SBill Paul 66695d67482SBill Paul /* 66795d67482SBill Paul * Intialize a standard receive ring descriptor. 66895d67482SBill Paul */ 66995d67482SBill Paul static int 6703f74909aSGleb Smirnoff bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 67195d67482SBill Paul { 67295d67482SBill Paul struct mbuf *m_new = NULL; 67395d67482SBill Paul struct bge_rx_bd *r; 674f41ac2beSBill Paul struct bge_dmamap_arg ctx; 675f41ac2beSBill Paul int error; 67695d67482SBill Paul 67795d67482SBill Paul if (m == NULL) { 678c3a56752SGleb Smirnoff m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 679c3a56752SGleb Smirnoff if (m_new == NULL) 68095d67482SBill Paul return (ENOBUFS); 68195d67482SBill Paul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 68295d67482SBill Paul } else { 68395d67482SBill Paul m_new = m; 68495d67482SBill Paul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 68595d67482SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 68695d67482SBill Paul } 68795d67482SBill Paul 688e255b776SJohn Polstra if (!sc->bge_rx_alignment_bug) 68995d67482SBill Paul m_adj(m_new, ETHER_ALIGN); 69095d67482SBill Paul sc->bge_cdata.bge_rx_std_chain[i] = m_new; 691f41ac2beSBill Paul r = &sc->bge_ldata.bge_rx_std_ring[i]; 692f41ac2beSBill Paul ctx.bge_maxsegs = 1; 693f41ac2beSBill Paul ctx.sc = sc; 694f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 695f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 696f41ac2beSBill Paul m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 697f41ac2beSBill Paul if (error || ctx.bge_maxsegs == 0) { 698f7cea149SGleb Smirnoff if (m == NULL) { 699f7cea149SGleb Smirnoff sc->bge_cdata.bge_rx_std_chain[i] = NULL; 700f41ac2beSBill Paul m_freem(m_new); 701f7cea149SGleb Smirnoff } 702f41ac2beSBill Paul return (ENOMEM); 703f41ac2beSBill Paul } 704e907febfSPyun YongHyeon r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 705e907febfSPyun YongHyeon r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 706e907febfSPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_END; 707e907febfSPyun YongHyeon r->bge_len = m_new->m_len; 708e907febfSPyun YongHyeon r->bge_idx = i; 709f41ac2beSBill Paul 710f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_mtag, 711f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i], 712f41ac2beSBill Paul BUS_DMASYNC_PREREAD); 71395d67482SBill Paul 71495d67482SBill Paul return (0); 71595d67482SBill Paul } 71695d67482SBill Paul 71795d67482SBill Paul /* 71895d67482SBill Paul * Initialize a jumbo receive ring descriptor. This allocates 71995d67482SBill Paul * a jumbo buffer from the pool managed internally by the driver. 72095d67482SBill Paul */ 72195d67482SBill Paul static int 7223f74909aSGleb Smirnoff bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 72395d67482SBill Paul { 7241be6acb7SGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 7251be6acb7SGleb Smirnoff struct bge_extrx_bd *r; 72695d67482SBill Paul struct mbuf *m_new = NULL; 7271be6acb7SGleb Smirnoff int nsegs; 728f41ac2beSBill Paul int error; 72995d67482SBill Paul 73095d67482SBill Paul if (m == NULL) { 731a163d034SWarner Losh MGETHDR(m_new, M_DONTWAIT, MT_DATA); 7321be6acb7SGleb Smirnoff if (m_new == NULL) 73395d67482SBill Paul return (ENOBUFS); 73495d67482SBill Paul 7351be6acb7SGleb Smirnoff m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 7361be6acb7SGleb Smirnoff if (!(m_new->m_flags & M_EXT)) { 73795d67482SBill Paul m_freem(m_new); 73895d67482SBill Paul return (ENOBUFS); 73995d67482SBill Paul } 7401be6acb7SGleb Smirnoff m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 74195d67482SBill Paul } else { 74295d67482SBill Paul m_new = m; 7431be6acb7SGleb Smirnoff m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 74495d67482SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 74595d67482SBill Paul } 74695d67482SBill Paul 747e255b776SJohn Polstra if (!sc->bge_rx_alignment_bug) 74895d67482SBill Paul m_adj(m_new, ETHER_ALIGN); 7491be6acb7SGleb Smirnoff 7501be6acb7SGleb Smirnoff error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 7511be6acb7SGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_dmamap[i], 7521be6acb7SGleb Smirnoff m_new, segs, &nsegs, BUS_DMA_NOWAIT); 7531be6acb7SGleb Smirnoff if (error) { 7541be6acb7SGleb Smirnoff if (m == NULL) 755f41ac2beSBill Paul m_freem(m_new); 7561be6acb7SGleb Smirnoff return (error); 757f7cea149SGleb Smirnoff } 7581be6acb7SGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 7591be6acb7SGleb Smirnoff 7601be6acb7SGleb Smirnoff /* 7611be6acb7SGleb Smirnoff * Fill in the extended RX buffer descriptor. 7621be6acb7SGleb Smirnoff */ 7631be6acb7SGleb Smirnoff r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 7644e7ba1abSGleb Smirnoff r->bge_flags = BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END; 7654e7ba1abSGleb Smirnoff r->bge_idx = i; 7664e7ba1abSGleb Smirnoff r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 7674e7ba1abSGleb Smirnoff switch (nsegs) { 7684e7ba1abSGleb Smirnoff case 4: 7694e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 7704e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 7714e7ba1abSGleb Smirnoff r->bge_len3 = segs[3].ds_len; 7724e7ba1abSGleb Smirnoff case 3: 773e907febfSPyun YongHyeon r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 774e907febfSPyun YongHyeon r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 775e907febfSPyun YongHyeon r->bge_len2 = segs[2].ds_len; 7764e7ba1abSGleb Smirnoff case 2: 7774e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 7784e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 7794e7ba1abSGleb Smirnoff r->bge_len1 = segs[1].ds_len; 7804e7ba1abSGleb Smirnoff case 1: 7814e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 7824e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 7834e7ba1abSGleb Smirnoff r->bge_len0 = segs[0].ds_len; 7844e7ba1abSGleb Smirnoff break; 7854e7ba1abSGleb Smirnoff default: 7864e7ba1abSGleb Smirnoff panic("%s: %d segments\n", __func__, nsegs); 7874e7ba1abSGleb Smirnoff } 788f41ac2beSBill Paul 789f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_mtag, 790f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i], 791f41ac2beSBill Paul BUS_DMASYNC_PREREAD); 79295d67482SBill Paul 79395d67482SBill Paul return (0); 79495d67482SBill Paul } 79595d67482SBill Paul 79695d67482SBill Paul /* 79795d67482SBill Paul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 79895d67482SBill Paul * that's 1MB or memory, which is a lot. For now, we fill only the first 79995d67482SBill Paul * 256 ring entries and hope that our CPU is fast enough to keep up with 80095d67482SBill Paul * the NIC. 80195d67482SBill Paul */ 80295d67482SBill Paul static int 8033f74909aSGleb Smirnoff bge_init_rx_ring_std(struct bge_softc *sc) 80495d67482SBill Paul { 80595d67482SBill Paul int i; 80695d67482SBill Paul 80795d67482SBill Paul for (i = 0; i < BGE_SSLOTS; i++) { 80895d67482SBill Paul if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 80995d67482SBill Paul return (ENOBUFS); 81095d67482SBill Paul }; 81195d67482SBill Paul 812f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 813f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, 814f41ac2beSBill Paul BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 815f41ac2beSBill Paul 81695d67482SBill Paul sc->bge_std = i - 1; 81795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 81895d67482SBill Paul 81995d67482SBill Paul return (0); 82095d67482SBill Paul } 82195d67482SBill Paul 82295d67482SBill Paul static void 8233f74909aSGleb Smirnoff bge_free_rx_ring_std(struct bge_softc *sc) 82495d67482SBill Paul { 82595d67482SBill Paul int i; 82695d67482SBill Paul 82795d67482SBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 82895d67482SBill Paul if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 829e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag, 830e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], 831e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 832f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag, 833f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 834e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 835e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_chain[i] = NULL; 83695d67482SBill Paul } 837f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 83895d67482SBill Paul sizeof(struct bge_rx_bd)); 83995d67482SBill Paul } 84095d67482SBill Paul } 84195d67482SBill Paul 84295d67482SBill Paul static int 8433f74909aSGleb Smirnoff bge_init_rx_ring_jumbo(struct bge_softc *sc) 84495d67482SBill Paul { 84595d67482SBill Paul struct bge_rcb *rcb; 8461be6acb7SGleb Smirnoff int i; 84795d67482SBill Paul 84895d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 84995d67482SBill Paul if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 85095d67482SBill Paul return (ENOBUFS); 85195d67482SBill Paul }; 85295d67482SBill Paul 853f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 854f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 855f41ac2beSBill Paul BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856f41ac2beSBill Paul 85795d67482SBill Paul sc->bge_jumbo = i - 1; 85895d67482SBill Paul 859f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 8601be6acb7SGleb Smirnoff rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 8611be6acb7SGleb Smirnoff BGE_RCB_FLAG_USE_EXT_RX_BD); 86267111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 86395d67482SBill Paul 86495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 86595d67482SBill Paul 86695d67482SBill Paul return (0); 86795d67482SBill Paul } 86895d67482SBill Paul 86995d67482SBill Paul static void 8703f74909aSGleb Smirnoff bge_free_rx_ring_jumbo(struct bge_softc *sc) 87195d67482SBill Paul { 87295d67482SBill Paul int i; 87395d67482SBill Paul 87495d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 87595d67482SBill Paul if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 876e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 877e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], 878e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 879f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 880f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 881e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 882e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 88395d67482SBill Paul } 884f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 8851be6acb7SGleb Smirnoff sizeof(struct bge_extrx_bd)); 88695d67482SBill Paul } 88795d67482SBill Paul } 88895d67482SBill Paul 88995d67482SBill Paul static void 8903f74909aSGleb Smirnoff bge_free_tx_ring(struct bge_softc *sc) 89195d67482SBill Paul { 89295d67482SBill Paul int i; 89395d67482SBill Paul 894f41ac2beSBill Paul if (sc->bge_ldata.bge_tx_ring == NULL) 89595d67482SBill Paul return; 89695d67482SBill Paul 89795d67482SBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 89895d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 899e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag, 900e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[i], 901e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 902f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag, 903f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 904e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[i]); 905e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[i] = NULL; 90695d67482SBill Paul } 907f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 90895d67482SBill Paul sizeof(struct bge_tx_bd)); 90995d67482SBill Paul } 91095d67482SBill Paul } 91195d67482SBill Paul 91295d67482SBill Paul static int 9133f74909aSGleb Smirnoff bge_init_tx_ring(struct bge_softc *sc) 91495d67482SBill Paul { 91595d67482SBill Paul sc->bge_txcnt = 0; 91695d67482SBill Paul sc->bge_tx_saved_considx = 0; 9173927098fSPaul Saab 91814bbd30fSGleb Smirnoff /* Initialize transmit producer index for host-memory send ring. */ 91914bbd30fSGleb Smirnoff sc->bge_tx_prodidx = 0; 92014bbd30fSGleb Smirnoff CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 92114bbd30fSGleb Smirnoff 9223927098fSPaul Saab /* 5700 b2 errata */ 923e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 92414bbd30fSGleb Smirnoff CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 9253927098fSPaul Saab 92614bbd30fSGleb Smirnoff /* NIC-memory send ring not used; initialize to zero. */ 9273927098fSPaul Saab CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 9283927098fSPaul Saab /* 5700 b2 errata */ 929e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 93095d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 93195d67482SBill Paul 93295d67482SBill Paul return (0); 93395d67482SBill Paul } 93495d67482SBill Paul 93595d67482SBill Paul static void 9363f74909aSGleb Smirnoff bge_setmulti(struct bge_softc *sc) 93795d67482SBill Paul { 93895d67482SBill Paul struct ifnet *ifp; 93995d67482SBill Paul struct ifmultiaddr *ifma; 9403f74909aSGleb Smirnoff uint32_t hashes[4] = { 0, 0, 0, 0 }; 94195d67482SBill Paul int h, i; 94295d67482SBill Paul 9430f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 9440f9bd73bSSam Leffler 945fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 94695d67482SBill Paul 94795d67482SBill Paul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 94895d67482SBill Paul for (i = 0; i < 4; i++) 94995d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 95095d67482SBill Paul return; 95195d67482SBill Paul } 95295d67482SBill Paul 95395d67482SBill Paul /* First, zot all the existing filters. */ 95495d67482SBill Paul for (i = 0; i < 4; i++) 95595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 95695d67482SBill Paul 95795d67482SBill Paul /* Now program new ones. */ 95813b203d0SRobert Watson IF_ADDR_LOCK(ifp); 95995d67482SBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 96095d67482SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 96195d67482SBill Paul continue; 9620e939c0cSChristian Weisgerber h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 9630e939c0cSChristian Weisgerber ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 96495d67482SBill Paul hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 96595d67482SBill Paul } 96613b203d0SRobert Watson IF_ADDR_UNLOCK(ifp); 96795d67482SBill Paul 96895d67482SBill Paul for (i = 0; i < 4; i++) 96995d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 97095d67482SBill Paul } 97195d67482SBill Paul 97295d67482SBill Paul /* 97395d67482SBill Paul * Do endian, PCI and DMA initialization. Also check the on-board ROM 97495d67482SBill Paul * self-test results. 97595d67482SBill Paul */ 97695d67482SBill Paul static int 9773f74909aSGleb Smirnoff bge_chipinit(struct bge_softc *sc) 97895d67482SBill Paul { 9793f74909aSGleb Smirnoff uint32_t dma_rw_ctl; 98095d67482SBill Paul int i; 98195d67482SBill Paul 982e907febfSPyun YongHyeon /* Set endian type before we access any non-PCI registers. */ 983e907febfSPyun YongHyeon pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 98495d67482SBill Paul 98595d67482SBill Paul /* 98695d67482SBill Paul * Check the 'ROM failed' bit on the RX CPU to see if 98795d67482SBill Paul * self-tests passed. 98895d67482SBill Paul */ 98995d67482SBill Paul if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 990fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 99195d67482SBill Paul return (ENODEV); 99295d67482SBill Paul } 99395d67482SBill Paul 99495d67482SBill Paul /* Clear the MAC control register */ 99595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 99695d67482SBill Paul 99795d67482SBill Paul /* 99895d67482SBill Paul * Clear the MAC statistics block in the NIC's 99995d67482SBill Paul * internal memory. 100095d67482SBill Paul */ 100195d67482SBill Paul for (i = BGE_STATS_BLOCK; 10023f74909aSGleb Smirnoff i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 100395d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 100495d67482SBill Paul 100595d67482SBill Paul for (i = BGE_STATUS_BLOCK; 10063f74909aSGleb Smirnoff i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 100795d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 100895d67482SBill Paul 100995d67482SBill Paul /* Set up the PCI DMA control register. */ 1010e53d81eeSPaul Saab if (sc->bge_pcie) { 10114c0da0ffSGleb Smirnoff /* PCI Express bus */ 1012e53d81eeSPaul Saab dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1013e53d81eeSPaul Saab (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1014e53d81eeSPaul Saab (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 10154c0da0ffSGleb Smirnoff } else if (sc->bge_pcix) { 10168287860eSJohn Polstra /* PCI-X bus */ 10174c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 10184c0da0ffSGleb Smirnoff dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 10194c0da0ffSGleb Smirnoff dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 10204c0da0ffSGleb Smirnoff /* XXX magic values, Broadcom-supplied Linux driver */ 10214c0da0ffSGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5780) 10224c0da0ffSGleb Smirnoff dma_rw_ctl |= (1 << 20) | (1 << 18) | 10234c0da0ffSGleb Smirnoff BGE_PCIDMARWCTL_ONEDMA_ATONCE; 10244c0da0ffSGleb Smirnoff else 10254c0da0ffSGleb Smirnoff dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15); 10264c0da0ffSGleb Smirnoff 10274c0da0ffSGleb Smirnoff } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 10285cba12d3SPaul Saab /* 10295cba12d3SPaul Saab * The 5704 uses a different encoding of read/write 10305cba12d3SPaul Saab * watermarks. 10315cba12d3SPaul Saab */ 10325cba12d3SPaul Saab dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 10335cba12d3SPaul Saab (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 10345cba12d3SPaul Saab (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 10355cba12d3SPaul Saab else 10365cba12d3SPaul Saab dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 10375cba12d3SPaul Saab (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 10385cba12d3SPaul Saab (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 10395cba12d3SPaul Saab (0x0F); 10405cba12d3SPaul Saab 10415cba12d3SPaul Saab /* 10425cba12d3SPaul Saab * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 10435cba12d3SPaul Saab * for hardware bugs. 10445cba12d3SPaul Saab */ 1045e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1046e0ced696SPaul Saab sc->bge_asicrev == BGE_ASICREV_BCM5704) { 10473f74909aSGleb Smirnoff uint32_t tmp; 10485cba12d3SPaul Saab 10495cba12d3SPaul Saab tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 10505cba12d3SPaul Saab if (tmp == 0x6 || tmp == 0x7) 10515cba12d3SPaul Saab dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 10528287860eSJohn Polstra } 10534c0da0ffSGleb Smirnoff } else 10544c0da0ffSGleb Smirnoff /* Conventional PCI bus */ 10554c0da0ffSGleb Smirnoff dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 10564c0da0ffSGleb Smirnoff (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 10574c0da0ffSGleb Smirnoff (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 10584c0da0ffSGleb Smirnoff (0x0F); 10595cba12d3SPaul Saab 1060e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 10610434d1b8SBill Paul sc->bge_asicrev == BGE_ASICREV_BCM5704 || 10624c0da0ffSGleb Smirnoff sc->bge_asicrev == BGE_ASICREV_BCM5705) 10635cba12d3SPaul Saab dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 10645cba12d3SPaul Saab pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 106595d67482SBill Paul 106695d67482SBill Paul /* 106795d67482SBill Paul * Set up general mode register. 106895d67482SBill Paul */ 1069e907febfSPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 107095d67482SBill Paul BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1071ee7ef91cSOleg Bulyzhin BGE_MODECTL_TX_NO_PHDR_CSUM); 107295d67482SBill Paul 107395d67482SBill Paul /* 1074ea13bdd5SJohn Polstra * Disable memory write invalidate. Apparently it is not supported 1075ea13bdd5SJohn Polstra * properly by these devices. 107695d67482SBill Paul */ 1077ea13bdd5SJohn Polstra PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 107895d67482SBill Paul 107995d67482SBill Paul #ifdef __brokenalpha__ 108095d67482SBill Paul /* 108195d67482SBill Paul * Must insure that we do not cross an 8K (bytes) boundary 108295d67482SBill Paul * for DMA reads. Our highest limit is 1K bytes. This is a 108395d67482SBill Paul * restriction on some ALPHA platforms with early revision 108495d67482SBill Paul * 21174 PCI chipsets, such as the AlphaPC 164lx 108595d67482SBill Paul */ 108662f1ea9cSJohn Polstra PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 108762f1ea9cSJohn Polstra BGE_PCI_READ_BNDRY_1024BYTES, 4); 108895d67482SBill Paul #endif 108995d67482SBill Paul 109095d67482SBill Paul /* Set the timer prescaler (always 66Mhz) */ 109195d67482SBill Paul CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 109295d67482SBill Paul 109395d67482SBill Paul return (0); 109495d67482SBill Paul } 109595d67482SBill Paul 109695d67482SBill Paul static int 10973f74909aSGleb Smirnoff bge_blockinit(struct bge_softc *sc) 109895d67482SBill Paul { 109995d67482SBill Paul struct bge_rcb *rcb; 1100e907febfSPyun YongHyeon bus_size_t vrcb; 1101e907febfSPyun YongHyeon bge_hostaddr taddr; 110295d67482SBill Paul int i; 110395d67482SBill Paul 110495d67482SBill Paul /* 110595d67482SBill Paul * Initialize the memory window pointer register so that 110695d67482SBill Paul * we can access the first 32K of internal NIC RAM. This will 110795d67482SBill Paul * allow us to set up the TX send ring RCBs and the RX return 110895d67482SBill Paul * ring RCBs, plus other things which live in NIC memory. 110995d67482SBill Paul */ 111095d67482SBill Paul CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 111195d67482SBill Paul 1112822f63fcSBill Paul /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1113822f63fcSBill Paul 11144c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 111595d67482SBill Paul /* Configure mbuf memory pool */ 111695d67482SBill Paul if (sc->bge_extram) { 11170434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 11180434d1b8SBill Paul BGE_EXT_SSRAM); 1119822f63fcSBill Paul if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1120822f63fcSBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1121822f63fcSBill Paul else 112295d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 112395d67482SBill Paul } else { 11240434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 11250434d1b8SBill Paul BGE_BUFFPOOL_1); 1126822f63fcSBill Paul if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1127822f63fcSBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1128822f63fcSBill Paul else 112995d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 113095d67482SBill Paul } 113195d67482SBill Paul 113295d67482SBill Paul /* Configure DMA resource pool */ 11330434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 11340434d1b8SBill Paul BGE_DMA_DESCRIPTORS); 113595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 11360434d1b8SBill Paul } 113795d67482SBill Paul 113895d67482SBill Paul /* Configure mbuf pool watermarks */ 11394c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 11400434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 11410434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 11420434d1b8SBill Paul } else { 1143fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1144fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 11450434d1b8SBill Paul } 1146fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 114795d67482SBill Paul 114895d67482SBill Paul /* Configure DMA resource watermarks */ 114995d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 115095d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 115195d67482SBill Paul 115295d67482SBill Paul /* Enable buffer manager */ 11534c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 115495d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MODE, 115595d67482SBill Paul BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 115695d67482SBill Paul 115795d67482SBill Paul /* Poll for buffer manager start indication */ 115895d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 115995d67482SBill Paul if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 116095d67482SBill Paul break; 116195d67482SBill Paul DELAY(10); 116295d67482SBill Paul } 116395d67482SBill Paul 116495d67482SBill Paul if (i == BGE_TIMEOUT) { 1165fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1166fe806fdaSPyun YongHyeon "buffer manager failed to start\n"); 116795d67482SBill Paul return (ENXIO); 116895d67482SBill Paul } 11690434d1b8SBill Paul } 117095d67482SBill Paul 117195d67482SBill Paul /* Enable flow-through queues */ 117295d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 117395d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 117495d67482SBill Paul 117595d67482SBill Paul /* Wait until queue initialization is complete */ 117695d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 117795d67482SBill Paul if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 117895d67482SBill Paul break; 117995d67482SBill Paul DELAY(10); 118095d67482SBill Paul } 118195d67482SBill Paul 118295d67482SBill Paul if (i == BGE_TIMEOUT) { 1183fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "flow-through queue init failed\n"); 118495d67482SBill Paul return (ENXIO); 118595d67482SBill Paul } 118695d67482SBill Paul 118795d67482SBill Paul /* Initialize the standard RX ring control block */ 1188f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1189f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 1190f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1191f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 1192f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1193f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1194f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 11954c0da0ffSGleb Smirnoff if (BGE_IS_5705_OR_BEYOND(sc)) 11960434d1b8SBill Paul rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 11970434d1b8SBill Paul else 11980434d1b8SBill Paul rcb->bge_maxlen_flags = 11990434d1b8SBill Paul BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 120095d67482SBill Paul if (sc->bge_extram) 120195d67482SBill Paul rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 120295d67482SBill Paul else 120395d67482SBill Paul rcb->bge_nicaddr = BGE_STD_RX_RINGS; 120467111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 120567111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1206f41ac2beSBill Paul 120767111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 120867111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 120995d67482SBill Paul 121095d67482SBill Paul /* 121195d67482SBill Paul * Initialize the jumbo RX ring control block 121295d67482SBill Paul * We set the 'ring disabled' bit in the flags 121395d67482SBill Paul * field until we're actually ready to start 121495d67482SBill Paul * using this ring (i.e. once we set the MTU 121595d67482SBill Paul * high enough to require it). 121695d67482SBill Paul */ 12174c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 1218f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1219f41ac2beSBill Paul 1220f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 1221f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1222f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 1223f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1224f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1225f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 1226f41ac2beSBill Paul BUS_DMASYNC_PREREAD); 12271be6acb7SGleb Smirnoff rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 12281be6acb7SGleb Smirnoff BGE_RCB_FLAG_USE_EXT_RX_BD|BGE_RCB_FLAG_RING_DISABLED); 122995d67482SBill Paul if (sc->bge_extram) 123095d67482SBill Paul rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 123195d67482SBill Paul else 123295d67482SBill Paul rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 123367111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 123467111612SJohn Polstra rcb->bge_hostaddr.bge_addr_hi); 123567111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 123667111612SJohn Polstra rcb->bge_hostaddr.bge_addr_lo); 1237f41ac2beSBill Paul 12380434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 12390434d1b8SBill Paul rcb->bge_maxlen_flags); 124067111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 124195d67482SBill Paul 124295d67482SBill Paul /* Set up dummy disabled mini ring RCB */ 1243f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 124467111612SJohn Polstra rcb->bge_maxlen_flags = 124567111612SJohn Polstra BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 12460434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 12470434d1b8SBill Paul rcb->bge_maxlen_flags); 12480434d1b8SBill Paul } 124995d67482SBill Paul 125095d67482SBill Paul /* 125195d67482SBill Paul * Set the BD ring replentish thresholds. The recommended 125295d67482SBill Paul * values are 1/8th the number of descriptors allocated to 125395d67482SBill Paul * each ring. 125495d67482SBill Paul */ 125595d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 125695d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 125795d67482SBill Paul 125895d67482SBill Paul /* 125995d67482SBill Paul * Disable all unused send rings by setting the 'ring disabled' 126095d67482SBill Paul * bit in the flags field of all the TX send ring control blocks. 126195d67482SBill Paul * These are located in NIC memory. 126295d67482SBill Paul */ 1263e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 126495d67482SBill Paul for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1265e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1266e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1267e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1268e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 126995d67482SBill Paul } 127095d67482SBill Paul 127195d67482SBill Paul /* Configure TX RCB 0 (we use only the first ring) */ 1272e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1273e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1274e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1275e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1276e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1277e907febfSPyun YongHyeon BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 12784c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 1279e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1280e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 128195d67482SBill Paul 128295d67482SBill Paul /* Disable all unused RX return rings */ 1283e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 128495d67482SBill Paul for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1285e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1286e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1287e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 12880434d1b8SBill Paul BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1289e907febfSPyun YongHyeon BGE_RCB_FLAG_RING_DISABLED)); 1290e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 129195d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 12923f74909aSGleb Smirnoff (i * (sizeof(uint64_t))), 0); 1293e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 129495d67482SBill Paul } 129595d67482SBill Paul 129695d67482SBill Paul /* Initialize RX ring indexes */ 129795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 129895d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 129995d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 130095d67482SBill Paul 130195d67482SBill Paul /* 130295d67482SBill Paul * Set up RX return ring 0 130395d67482SBill Paul * Note that the NIC address for RX return rings is 0x00000000. 130495d67482SBill Paul * The return rings live entirely within the host, so the 130595d67482SBill Paul * nicaddr field in the RCB isn't used. 130695d67482SBill Paul */ 1307e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1308e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1309e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1310e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1311e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1312e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1313e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 131495d67482SBill Paul 131595d67482SBill Paul /* Set random backoff seed for TX */ 131695d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 13174a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 13184a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 13194a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 132095d67482SBill Paul BGE_TX_BACKOFF_SEED_MASK); 132195d67482SBill Paul 132295d67482SBill Paul /* Set inter-packet gap */ 132395d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 132495d67482SBill Paul 132595d67482SBill Paul /* 132695d67482SBill Paul * Specify which ring to use for packets that don't match 132795d67482SBill Paul * any RX rules. 132895d67482SBill Paul */ 132995d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 133095d67482SBill Paul 133195d67482SBill Paul /* 133295d67482SBill Paul * Configure number of RX lists. One interrupt distribution 133395d67482SBill Paul * list, sixteen active lists, one bad frames class. 133495d67482SBill Paul */ 133595d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 133695d67482SBill Paul 133795d67482SBill Paul /* Inialize RX list placement stats mask. */ 133895d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 133995d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 134095d67482SBill Paul 134195d67482SBill Paul /* Disable host coalescing until we get it set up */ 134295d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 134395d67482SBill Paul 134495d67482SBill Paul /* Poll to make sure it's shut down. */ 134595d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 134695d67482SBill Paul if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 134795d67482SBill Paul break; 134895d67482SBill Paul DELAY(10); 134995d67482SBill Paul } 135095d67482SBill Paul 135195d67482SBill Paul if (i == BGE_TIMEOUT) { 1352fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1353fe806fdaSPyun YongHyeon "host coalescing engine failed to idle\n"); 135495d67482SBill Paul return (ENXIO); 135595d67482SBill Paul } 135695d67482SBill Paul 135795d67482SBill Paul /* Set up host coalescing defaults */ 135895d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 135995d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 136095d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 136195d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 13624c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 136395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 136495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 13650434d1b8SBill Paul } 136695d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 136795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 136895d67482SBill Paul 136995d67482SBill Paul /* Set up address of statistics block */ 13704c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1371f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1372f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 137395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1374f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 13750434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 137695d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 13770434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 13780434d1b8SBill Paul } 13790434d1b8SBill Paul 13800434d1b8SBill Paul /* Set up address of status block */ 1381f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1382f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 138395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1384f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1385f41ac2beSBill Paul sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1386f41ac2beSBill Paul sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 138795d67482SBill Paul 138895d67482SBill Paul /* Turn on host coalescing state machine */ 138995d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 139095d67482SBill Paul 139195d67482SBill Paul /* Turn on RX BD completion state machine and enable attentions */ 139295d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDC_MODE, 139395d67482SBill Paul BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 139495d67482SBill Paul 139595d67482SBill Paul /* Turn on RX list placement state machine */ 139695d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 139795d67482SBill Paul 139895d67482SBill Paul /* Turn on RX list selector state machine. */ 13994c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 140095d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 140195d67482SBill Paul 140295d67482SBill Paul /* Turn on DMA, clear stats */ 140395d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 140495d67482SBill Paul BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 140595d67482SBill Paul BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 140695d67482SBill Paul BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 140795d67482SBill Paul (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 140895d67482SBill Paul 140995d67482SBill Paul /* Set misc. local control, enable interrupts on attentions */ 141095d67482SBill Paul CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 141195d67482SBill Paul 141295d67482SBill Paul #ifdef notdef 141395d67482SBill Paul /* Assert GPIO pins for PHY reset */ 141495d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 141595d67482SBill Paul BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 141695d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 141795d67482SBill Paul BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 141895d67482SBill Paul #endif 141995d67482SBill Paul 142095d67482SBill Paul /* Turn on DMA completion state machine */ 14214c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 142295d67482SBill Paul CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 142395d67482SBill Paul 142495d67482SBill Paul /* Turn on write DMA state machine */ 142595d67482SBill Paul CSR_WRITE_4(sc, BGE_WDMA_MODE, 142695d67482SBill Paul BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 142795d67482SBill Paul 142895d67482SBill Paul /* Turn on read DMA state machine */ 142995d67482SBill Paul CSR_WRITE_4(sc, BGE_RDMA_MODE, 143095d67482SBill Paul BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 143195d67482SBill Paul 143295d67482SBill Paul /* Turn on RX data completion state machine */ 143395d67482SBill Paul CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 143495d67482SBill Paul 143595d67482SBill Paul /* Turn on RX BD initiator state machine */ 143695d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 143795d67482SBill Paul 143895d67482SBill Paul /* Turn on RX data and RX BD initiator state machine */ 143995d67482SBill Paul CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 144095d67482SBill Paul 144195d67482SBill Paul /* Turn on Mbuf cluster free state machine */ 14424c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 144395d67482SBill Paul CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 144495d67482SBill Paul 144595d67482SBill Paul /* Turn on send BD completion state machine */ 144695d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 144795d67482SBill Paul 144895d67482SBill Paul /* Turn on send data completion state machine */ 144995d67482SBill Paul CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 145095d67482SBill Paul 145195d67482SBill Paul /* Turn on send data initiator state machine */ 145295d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 145395d67482SBill Paul 145495d67482SBill Paul /* Turn on send BD initiator state machine */ 145595d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 145695d67482SBill Paul 145795d67482SBill Paul /* Turn on send BD selector state machine */ 145895d67482SBill Paul CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 145995d67482SBill Paul 146095d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 146195d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 146295d67482SBill Paul BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 146395d67482SBill Paul 146495d67482SBill Paul /* ack/clear link change events */ 146595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 14660434d1b8SBill Paul BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 14670434d1b8SBill Paul BGE_MACSTAT_LINK_CHANGED); 1468f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_MI_STS, 0); 146995d67482SBill Paul 147095d67482SBill Paul /* Enable PHY auto polling (for MII/GMII only) */ 147195d67482SBill Paul if (sc->bge_tbi) { 147295d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1473a1d52896SBill Paul } else { 147495d67482SBill Paul BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 14751f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 14764c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1477a1d52896SBill Paul CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1478a1d52896SBill Paul BGE_EVTENB_MI_INTERRUPT); 1479a1d52896SBill Paul } 148095d67482SBill Paul 14811f313773SOleg Bulyzhin /* 14821f313773SOleg Bulyzhin * Clear any pending link state attention. 14831f313773SOleg Bulyzhin * Otherwise some link state change events may be lost until attention 14841f313773SOleg Bulyzhin * is cleared by bge_intr() -> bge_link_upd() sequence. 14851f313773SOleg Bulyzhin * It's not necessary on newer BCM chips - perhaps enabling link 14861f313773SOleg Bulyzhin * state change attentions implies clearing pending attention. 14871f313773SOleg Bulyzhin */ 14881f313773SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 14891f313773SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 14901f313773SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 14911f313773SOleg Bulyzhin 149295d67482SBill Paul /* Enable link state change attentions. */ 149395d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 149495d67482SBill Paul 149595d67482SBill Paul return (0); 149695d67482SBill Paul } 149795d67482SBill Paul 14984c0da0ffSGleb Smirnoff const struct bge_revision * 14994c0da0ffSGleb Smirnoff bge_lookup_rev(uint32_t chipid) 15004c0da0ffSGleb Smirnoff { 15014c0da0ffSGleb Smirnoff const struct bge_revision *br; 15024c0da0ffSGleb Smirnoff 15034c0da0ffSGleb Smirnoff for (br = bge_revisions; br->br_name != NULL; br++) { 15044c0da0ffSGleb Smirnoff if (br->br_chipid == chipid) 15054c0da0ffSGleb Smirnoff return (br); 15064c0da0ffSGleb Smirnoff } 15074c0da0ffSGleb Smirnoff 15084c0da0ffSGleb Smirnoff for (br = bge_majorrevs; br->br_name != NULL; br++) { 15094c0da0ffSGleb Smirnoff if (br->br_chipid == BGE_ASICREV(chipid)) 15104c0da0ffSGleb Smirnoff return (br); 15114c0da0ffSGleb Smirnoff } 15124c0da0ffSGleb Smirnoff 15134c0da0ffSGleb Smirnoff return (NULL); 15144c0da0ffSGleb Smirnoff } 15154c0da0ffSGleb Smirnoff 15164c0da0ffSGleb Smirnoff const struct bge_vendor * 15174c0da0ffSGleb Smirnoff bge_lookup_vendor(uint16_t vid) 15184c0da0ffSGleb Smirnoff { 15194c0da0ffSGleb Smirnoff const struct bge_vendor *v; 15204c0da0ffSGleb Smirnoff 15214c0da0ffSGleb Smirnoff for (v = bge_vendors; v->v_name != NULL; v++) 15224c0da0ffSGleb Smirnoff if (v->v_id == vid) 15234c0da0ffSGleb Smirnoff return (v); 15244c0da0ffSGleb Smirnoff 15254c0da0ffSGleb Smirnoff panic("%s: unknown vendor %d", __func__, vid); 15264c0da0ffSGleb Smirnoff return (NULL); 15274c0da0ffSGleb Smirnoff } 15284c0da0ffSGleb Smirnoff 152995d67482SBill Paul /* 153095d67482SBill Paul * Probe for a Broadcom chip. Check the PCI vendor and device IDs 15314c0da0ffSGleb Smirnoff * against our list and return its name if we find a match. 15324c0da0ffSGleb Smirnoff * 15334c0da0ffSGleb Smirnoff * Note that since the Broadcom controller contains VPD support, we 153495d67482SBill Paul * can get the device name string from the controller itself instead 153595d67482SBill Paul * of the compiled-in string. This is a little slow, but it guarantees 15364c0da0ffSGleb Smirnoff * we'll always announce the right product name. Unfortunately, this 15374c0da0ffSGleb Smirnoff * is possible only later in bge_attach(), when we have established 15384c0da0ffSGleb Smirnoff * access to EEPROM. 153995d67482SBill Paul */ 154095d67482SBill Paul static int 15413f74909aSGleb Smirnoff bge_probe(device_t dev) 154295d67482SBill Paul { 15434c0da0ffSGleb Smirnoff struct bge_type *t = bge_devs; 15444c0da0ffSGleb Smirnoff struct bge_softc *sc = device_get_softc(dev); 154595d67482SBill Paul 154695d67482SBill Paul bzero(sc, sizeof(struct bge_softc)); 154795d67482SBill Paul sc->bge_dev = dev; 154895d67482SBill Paul 15494c0da0ffSGleb Smirnoff while(t->bge_vid != 0) { 155095d67482SBill Paul if ((pci_get_vendor(dev) == t->bge_vid) && 155195d67482SBill Paul (pci_get_device(dev) == t->bge_did)) { 15524c0da0ffSGleb Smirnoff char buf[64]; 15534c0da0ffSGleb Smirnoff const struct bge_revision *br; 15544c0da0ffSGleb Smirnoff const struct bge_vendor *v; 15554c0da0ffSGleb Smirnoff uint32_t id; 15564c0da0ffSGleb Smirnoff 15574c0da0ffSGleb Smirnoff id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 15584c0da0ffSGleb Smirnoff BGE_PCIMISCCTL_ASICREV; 15594c0da0ffSGleb Smirnoff br = bge_lookup_rev(id); 15604c0da0ffSGleb Smirnoff id >>= 16; 15614c0da0ffSGleb Smirnoff v = bge_lookup_vendor(t->bge_vid); 15624c0da0ffSGleb Smirnoff if (br == NULL) 15634c0da0ffSGleb Smirnoff snprintf(buf, 64, "%s unknown ASIC (%#04x)", 15644c0da0ffSGleb Smirnoff v->v_name, id); 15654c0da0ffSGleb Smirnoff else 15664c0da0ffSGleb Smirnoff snprintf(buf, 64, "%s %s, ASIC rev. %#04x", 15674c0da0ffSGleb Smirnoff v->v_name, br->br_name, id); 15684c0da0ffSGleb Smirnoff device_set_desc_copy(dev, buf); 15696d2a9bd6SDoug Ambrisko if (pci_get_subvendor(dev) == DELL_VENDORID) 15706d2a9bd6SDoug Ambrisko sc->bge_no_3_led = 1; 157195d67482SBill Paul return (0); 157295d67482SBill Paul } 157395d67482SBill Paul t++; 157495d67482SBill Paul } 157595d67482SBill Paul 157695d67482SBill Paul return (ENXIO); 157795d67482SBill Paul } 157895d67482SBill Paul 1579f41ac2beSBill Paul static void 15803f74909aSGleb Smirnoff bge_dma_free(struct bge_softc *sc) 1581f41ac2beSBill Paul { 1582f41ac2beSBill Paul int i; 1583f41ac2beSBill Paul 15843f74909aSGleb Smirnoff /* Destroy DMA maps for RX buffers. */ 1585f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1586f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1587f41ac2beSBill Paul bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1588f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 1589f41ac2beSBill Paul } 1590f41ac2beSBill Paul 15913f74909aSGleb Smirnoff /* Destroy DMA maps for jumbo RX buffers. */ 1592f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1593f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1594f41ac2beSBill Paul bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1595f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1596f41ac2beSBill Paul } 1597f41ac2beSBill Paul 15983f74909aSGleb Smirnoff /* Destroy DMA maps for TX buffers. */ 1599f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 1600f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_dmamap[i]) 1601f41ac2beSBill Paul bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1602f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 1603f41ac2beSBill Paul } 1604f41ac2beSBill Paul 1605f41ac2beSBill Paul if (sc->bge_cdata.bge_mtag) 1606f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1607f41ac2beSBill Paul 1608f41ac2beSBill Paul 16093f74909aSGleb Smirnoff /* Destroy standard RX ring. */ 1610e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_ring_map) 1611e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1612e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map); 1613e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1614f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1615f41ac2beSBill Paul sc->bge_ldata.bge_rx_std_ring, 1616f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map); 1617f41ac2beSBill Paul 1618f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_ring_tag) 1619f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1620f41ac2beSBill Paul 16213f74909aSGleb Smirnoff /* Destroy jumbo RX ring. */ 1622e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1623e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1624e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_ring_map); 1625e65bed95SPyun YongHyeon 1626e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1627e65bed95SPyun YongHyeon sc->bge_ldata.bge_rx_jumbo_ring) 1628f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1629f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring, 1630f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map); 1631f41ac2beSBill Paul 1632f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1633f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1634f41ac2beSBill Paul 16353f74909aSGleb Smirnoff /* Destroy RX return ring. */ 1636e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_return_ring_map) 1637e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1638e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map); 1639e65bed95SPyun YongHyeon 1640e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_rx_return_ring_map && 1641e65bed95SPyun YongHyeon sc->bge_ldata.bge_rx_return_ring) 1642f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1643f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring, 1644f41ac2beSBill Paul sc->bge_cdata.bge_rx_return_ring_map); 1645f41ac2beSBill Paul 1646f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_return_ring_tag) 1647f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1648f41ac2beSBill Paul 16493f74909aSGleb Smirnoff /* Destroy TX ring. */ 1650e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_tx_ring_map) 1651e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1652e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_ring_map); 1653e65bed95SPyun YongHyeon 1654e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1655f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1656f41ac2beSBill Paul sc->bge_ldata.bge_tx_ring, 1657f41ac2beSBill Paul sc->bge_cdata.bge_tx_ring_map); 1658f41ac2beSBill Paul 1659f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_ring_tag) 1660f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1661f41ac2beSBill Paul 16623f74909aSGleb Smirnoff /* Destroy status block. */ 1663e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_status_map) 1664e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1665e65bed95SPyun YongHyeon sc->bge_cdata.bge_status_map); 1666e65bed95SPyun YongHyeon 1667e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1668f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1669f41ac2beSBill Paul sc->bge_ldata.bge_status_block, 1670f41ac2beSBill Paul sc->bge_cdata.bge_status_map); 1671f41ac2beSBill Paul 1672f41ac2beSBill Paul if (sc->bge_cdata.bge_status_tag) 1673f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1674f41ac2beSBill Paul 16753f74909aSGleb Smirnoff /* Destroy statistics block. */ 1676e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_stats_map) 1677e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1678e65bed95SPyun YongHyeon sc->bge_cdata.bge_stats_map); 1679e65bed95SPyun YongHyeon 1680e65bed95SPyun YongHyeon if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 1681f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1682f41ac2beSBill Paul sc->bge_ldata.bge_stats, 1683f41ac2beSBill Paul sc->bge_cdata.bge_stats_map); 1684f41ac2beSBill Paul 1685f41ac2beSBill Paul if (sc->bge_cdata.bge_stats_tag) 1686f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1687f41ac2beSBill Paul 16883f74909aSGleb Smirnoff /* Destroy the parent tag. */ 1689f41ac2beSBill Paul if (sc->bge_cdata.bge_parent_tag) 1690f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1691f41ac2beSBill Paul } 1692f41ac2beSBill Paul 1693f41ac2beSBill Paul static int 16943f74909aSGleb Smirnoff bge_dma_alloc(device_t dev) 1695f41ac2beSBill Paul { 16963f74909aSGleb Smirnoff struct bge_dmamap_arg ctx; 1697f41ac2beSBill Paul struct bge_softc *sc; 16981be6acb7SGleb Smirnoff int i, error; 1699f41ac2beSBill Paul 1700f41ac2beSBill Paul sc = device_get_softc(dev); 1701f41ac2beSBill Paul 1702f41ac2beSBill Paul /* 1703f41ac2beSBill Paul * Allocate the parent bus DMA tag appropriate for PCI. 1704f41ac2beSBill Paul */ 1705f41ac2beSBill Paul error = bus_dma_tag_create(NULL, /* parent */ 1706f41ac2beSBill Paul PAGE_SIZE, 0, /* alignment, boundary */ 1707f41ac2beSBill Paul BUS_SPACE_MAXADDR, /* lowaddr */ 17082f28b973SScott Long BUS_SPACE_MAXADDR, /* highaddr */ 1709f41ac2beSBill Paul NULL, NULL, /* filter, filterarg */ 1710f41ac2beSBill Paul MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1711f41ac2beSBill Paul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 17128a40c10eSScott Long 0, /* flags */ 1713f41ac2beSBill Paul NULL, NULL, /* lockfunc, lockarg */ 1714f41ac2beSBill Paul &sc->bge_cdata.bge_parent_tag); 1715f41ac2beSBill Paul 1716e65bed95SPyun YongHyeon if (error != 0) { 1717fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1718fe806fdaSPyun YongHyeon "could not allocate parent dma tag\n"); 1719e65bed95SPyun YongHyeon return (ENOMEM); 1720e65bed95SPyun YongHyeon } 1721e65bed95SPyun YongHyeon 1722f41ac2beSBill Paul /* 1723f41ac2beSBill Paul * Create tag for RX mbufs. 1724f41ac2beSBill Paul */ 17258a2e22deSScott Long error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1726f41ac2beSBill Paul 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 17271be6acb7SGleb Smirnoff NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 17281be6acb7SGleb Smirnoff BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 1729f41ac2beSBill Paul 1730f41ac2beSBill Paul if (error) { 1731fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1732f41ac2beSBill Paul return (ENOMEM); 1733f41ac2beSBill Paul } 1734f41ac2beSBill Paul 17353f74909aSGleb Smirnoff /* Create DMA maps for RX buffers. */ 1736f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1737f41ac2beSBill Paul error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1738f41ac2beSBill Paul &sc->bge_cdata.bge_rx_std_dmamap[i]); 1739f41ac2beSBill Paul if (error) { 1740fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1741fe806fdaSPyun YongHyeon "can't create DMA map for RX\n"); 1742f41ac2beSBill Paul return (ENOMEM); 1743f41ac2beSBill Paul } 1744f41ac2beSBill Paul } 1745f41ac2beSBill Paul 17463f74909aSGleb Smirnoff /* Create DMA maps for TX buffers. */ 1747f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 1748f41ac2beSBill Paul error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1749f41ac2beSBill Paul &sc->bge_cdata.bge_tx_dmamap[i]); 1750f41ac2beSBill Paul if (error) { 1751fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 1752fe806fdaSPyun YongHyeon "can't create DMA map for RX\n"); 1753f41ac2beSBill Paul return (ENOMEM); 1754f41ac2beSBill Paul } 1755f41ac2beSBill Paul } 1756f41ac2beSBill Paul 17573f74909aSGleb Smirnoff /* Create tag for standard RX ring. */ 1758f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1759f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1760f41ac2beSBill Paul NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1761f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1762f41ac2beSBill Paul 1763f41ac2beSBill Paul if (error) { 1764fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1765f41ac2beSBill Paul return (ENOMEM); 1766f41ac2beSBill Paul } 1767f41ac2beSBill Paul 17683f74909aSGleb Smirnoff /* Allocate DMA'able memory for standard RX ring. */ 1769f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1770f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1771f41ac2beSBill Paul &sc->bge_cdata.bge_rx_std_ring_map); 1772f41ac2beSBill Paul if (error) 1773f41ac2beSBill Paul return (ENOMEM); 1774f41ac2beSBill Paul 1775f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1776f41ac2beSBill Paul 17773f74909aSGleb Smirnoff /* Load the address of the standard RX ring. */ 1778f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1779f41ac2beSBill Paul ctx.sc = sc; 1780f41ac2beSBill Paul 1781f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1782f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1783f41ac2beSBill Paul BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1784f41ac2beSBill Paul 1785f41ac2beSBill Paul if (error) 1786f41ac2beSBill Paul return (ENOMEM); 1787f41ac2beSBill Paul 1788f41ac2beSBill Paul sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1789f41ac2beSBill Paul 17903f74909aSGleb Smirnoff /* Create tags for jumbo mbufs. */ 17914c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 1792f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 17938a2e22deSScott Long 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 17941be6acb7SGleb Smirnoff NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 17951be6acb7SGleb Smirnoff 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 1796f41ac2beSBill Paul if (error) { 1797fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 17983f74909aSGleb Smirnoff "could not allocate jumbo dma tag\n"); 1799f41ac2beSBill Paul return (ENOMEM); 1800f41ac2beSBill Paul } 1801f41ac2beSBill Paul 18023f74909aSGleb Smirnoff /* Create tag for jumbo RX ring. */ 1803f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1804f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1805f41ac2beSBill Paul NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 1806f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 1807f41ac2beSBill Paul 1808f41ac2beSBill Paul if (error) { 1809fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 18103f74909aSGleb Smirnoff "could not allocate jumbo ring dma tag\n"); 1811f41ac2beSBill Paul return (ENOMEM); 1812f41ac2beSBill Paul } 1813f41ac2beSBill Paul 18143f74909aSGleb Smirnoff /* Allocate DMA'able memory for jumbo RX ring. */ 1815f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 18161be6acb7SGleb Smirnoff (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 18171be6acb7SGleb Smirnoff BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1818f41ac2beSBill Paul &sc->bge_cdata.bge_rx_jumbo_ring_map); 1819f41ac2beSBill Paul if (error) 1820f41ac2beSBill Paul return (ENOMEM); 1821f41ac2beSBill Paul 18223f74909aSGleb Smirnoff /* Load the address of the jumbo RX ring. */ 1823f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1824f41ac2beSBill Paul ctx.sc = sc; 1825f41ac2beSBill Paul 1826f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1827f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 1828f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 1829f41ac2beSBill Paul bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1830f41ac2beSBill Paul 1831f41ac2beSBill Paul if (error) 1832f41ac2beSBill Paul return (ENOMEM); 1833f41ac2beSBill Paul 1834f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 1835f41ac2beSBill Paul 18363f74909aSGleb Smirnoff /* Create DMA maps for jumbo RX buffers. */ 1837f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1838f41ac2beSBill Paul error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 1839f41ac2beSBill Paul 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1840f41ac2beSBill Paul if (error) { 1841fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 18423f74909aSGleb Smirnoff "can't create DMA map for jumbo RX\n"); 1843f41ac2beSBill Paul return (ENOMEM); 1844f41ac2beSBill Paul } 1845f41ac2beSBill Paul } 1846f41ac2beSBill Paul 1847f41ac2beSBill Paul } 1848f41ac2beSBill Paul 18493f74909aSGleb Smirnoff /* Create tag for RX return ring. */ 1850f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1851f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1852f41ac2beSBill Paul NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 1853f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 1854f41ac2beSBill Paul 1855f41ac2beSBill Paul if (error) { 1856fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1857f41ac2beSBill Paul return (ENOMEM); 1858f41ac2beSBill Paul } 1859f41ac2beSBill Paul 18603f74909aSGleb Smirnoff /* Allocate DMA'able memory for RX return ring. */ 1861f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 1862f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 1863f41ac2beSBill Paul &sc->bge_cdata.bge_rx_return_ring_map); 1864f41ac2beSBill Paul if (error) 1865f41ac2beSBill Paul return (ENOMEM); 1866f41ac2beSBill Paul 1867f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_rx_return_ring, 1868f41ac2beSBill Paul BGE_RX_RTN_RING_SZ(sc)); 1869f41ac2beSBill Paul 18703f74909aSGleb Smirnoff /* Load the address of the RX return ring. */ 1871f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1872f41ac2beSBill Paul ctx.sc = sc; 1873f41ac2beSBill Paul 1874f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 1875f41ac2beSBill Paul sc->bge_cdata.bge_rx_return_ring_map, 1876f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 1877f41ac2beSBill Paul bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1878f41ac2beSBill Paul 1879f41ac2beSBill Paul if (error) 1880f41ac2beSBill Paul return (ENOMEM); 1881f41ac2beSBill Paul 1882f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 1883f41ac2beSBill Paul 18843f74909aSGleb Smirnoff /* Create tag for TX ring. */ 1885f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1886f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1887f41ac2beSBill Paul NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 1888f41ac2beSBill Paul &sc->bge_cdata.bge_tx_ring_tag); 1889f41ac2beSBill Paul 1890f41ac2beSBill Paul if (error) { 1891fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1892f41ac2beSBill Paul return (ENOMEM); 1893f41ac2beSBill Paul } 1894f41ac2beSBill Paul 18953f74909aSGleb Smirnoff /* Allocate DMA'able memory for TX ring. */ 1896f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 1897f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 1898f41ac2beSBill Paul &sc->bge_cdata.bge_tx_ring_map); 1899f41ac2beSBill Paul if (error) 1900f41ac2beSBill Paul return (ENOMEM); 1901f41ac2beSBill Paul 1902f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1903f41ac2beSBill Paul 19043f74909aSGleb Smirnoff /* Load the address of the TX ring. */ 1905f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1906f41ac2beSBill Paul ctx.sc = sc; 1907f41ac2beSBill Paul 1908f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 1909f41ac2beSBill Paul sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 1910f41ac2beSBill Paul BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1911f41ac2beSBill Paul 1912f41ac2beSBill Paul if (error) 1913f41ac2beSBill Paul return (ENOMEM); 1914f41ac2beSBill Paul 1915f41ac2beSBill Paul sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 1916f41ac2beSBill Paul 19173f74909aSGleb Smirnoff /* Create tag for status block. */ 1918f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1919f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1920f41ac2beSBill Paul NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 1921f41ac2beSBill Paul NULL, NULL, &sc->bge_cdata.bge_status_tag); 1922f41ac2beSBill Paul 1923f41ac2beSBill Paul if (error) { 1924fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1925f41ac2beSBill Paul return (ENOMEM); 1926f41ac2beSBill Paul } 1927f41ac2beSBill Paul 19283f74909aSGleb Smirnoff /* Allocate DMA'able memory for status block. */ 1929f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 1930f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 1931f41ac2beSBill Paul &sc->bge_cdata.bge_status_map); 1932f41ac2beSBill Paul if (error) 1933f41ac2beSBill Paul return (ENOMEM); 1934f41ac2beSBill Paul 1935f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1936f41ac2beSBill Paul 19373f74909aSGleb Smirnoff /* Load the address of the status block. */ 1938f41ac2beSBill Paul ctx.sc = sc; 1939f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1940f41ac2beSBill Paul 1941f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 1942f41ac2beSBill Paul sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 1943f41ac2beSBill Paul BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1944f41ac2beSBill Paul 1945f41ac2beSBill Paul if (error) 1946f41ac2beSBill Paul return (ENOMEM); 1947f41ac2beSBill Paul 1948f41ac2beSBill Paul sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 1949f41ac2beSBill Paul 19503f74909aSGleb Smirnoff /* Create tag for statistics block. */ 1951f41ac2beSBill Paul error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1952f41ac2beSBill Paul PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1953f41ac2beSBill Paul NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 1954f41ac2beSBill Paul &sc->bge_cdata.bge_stats_tag); 1955f41ac2beSBill Paul 1956f41ac2beSBill Paul if (error) { 1957fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1958f41ac2beSBill Paul return (ENOMEM); 1959f41ac2beSBill Paul } 1960f41ac2beSBill Paul 19613f74909aSGleb Smirnoff /* Allocate DMA'able memory for statistics block. */ 1962f41ac2beSBill Paul error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 1963f41ac2beSBill Paul (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 1964f41ac2beSBill Paul &sc->bge_cdata.bge_stats_map); 1965f41ac2beSBill Paul if (error) 1966f41ac2beSBill Paul return (ENOMEM); 1967f41ac2beSBill Paul 1968f41ac2beSBill Paul bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 1969f41ac2beSBill Paul 19703f74909aSGleb Smirnoff /* Load the address of the statstics block. */ 1971f41ac2beSBill Paul ctx.sc = sc; 1972f41ac2beSBill Paul ctx.bge_maxsegs = 1; 1973f41ac2beSBill Paul 1974f41ac2beSBill Paul error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 1975f41ac2beSBill Paul sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 1976f41ac2beSBill Paul BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1977f41ac2beSBill Paul 1978f41ac2beSBill Paul if (error) 1979f41ac2beSBill Paul return (ENOMEM); 1980f41ac2beSBill Paul 1981f41ac2beSBill Paul sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 1982f41ac2beSBill Paul 1983f41ac2beSBill Paul return (0); 1984f41ac2beSBill Paul } 1985f41ac2beSBill Paul 198695d67482SBill Paul static int 19873f74909aSGleb Smirnoff bge_attach(device_t dev) 198895d67482SBill Paul { 198995d67482SBill Paul struct ifnet *ifp; 199095d67482SBill Paul struct bge_softc *sc; 19913f74909aSGleb Smirnoff uint32_t hwcfg = 0; 19923f74909aSGleb Smirnoff uint32_t mac_tmp = 0; 1993fc74a9f9SBrooks Davis u_char eaddr[6]; 1994fe806fdaSPyun YongHyeon int error = 0, rid; 199595d67482SBill Paul 199695d67482SBill Paul sc = device_get_softc(dev); 199795d67482SBill Paul sc->bge_dev = dev; 199895d67482SBill Paul 199995d67482SBill Paul /* 200095d67482SBill Paul * Map control/status registers. 200195d67482SBill Paul */ 200295d67482SBill Paul pci_enable_busmaster(dev); 200395d67482SBill Paul 200495d67482SBill Paul rid = BGE_PCI_BAR0; 20055f96beb9SNate Lawson sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 20065f96beb9SNate Lawson RF_ACTIVE|PCI_RF_DENSE); 200795d67482SBill Paul 200895d67482SBill Paul if (sc->bge_res == NULL) { 2009fe806fdaSPyun YongHyeon device_printf (sc->bge_dev, "couldn't map memory\n"); 201095d67482SBill Paul error = ENXIO; 201195d67482SBill Paul goto fail; 201295d67482SBill Paul } 201395d67482SBill Paul 201495d67482SBill Paul sc->bge_btag = rman_get_bustag(sc->bge_res); 201595d67482SBill Paul sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 201695d67482SBill Paul 20173f74909aSGleb Smirnoff /* Allocate interrupt. */ 201895d67482SBill Paul rid = 0; 201995d67482SBill Paul 20205f96beb9SNate Lawson sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 202195d67482SBill Paul RF_SHAREABLE | RF_ACTIVE); 202295d67482SBill Paul 202395d67482SBill Paul if (sc->bge_irq == NULL) { 2024fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "couldn't map interrupt\n"); 202595d67482SBill Paul error = ENXIO; 202695d67482SBill Paul goto fail; 202795d67482SBill Paul } 202895d67482SBill Paul 20290f9bd73bSSam Leffler BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 20300f9bd73bSSam Leffler 2031e53d81eeSPaul Saab /* Save ASIC rev. */ 2032e53d81eeSPaul Saab 2033e53d81eeSPaul Saab sc->bge_chipid = 2034e53d81eeSPaul Saab pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2035e53d81eeSPaul Saab BGE_PCIMISCCTL_ASICREV; 2036e53d81eeSPaul Saab sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2037e53d81eeSPaul Saab sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2038e53d81eeSPaul Saab 2039e53d81eeSPaul Saab /* 2040e53d81eeSPaul Saab * XXX: Broadcom Linux driver. Not in specs or eratta. 2041e53d81eeSPaul Saab * PCI-Express? 2042e53d81eeSPaul Saab */ 20434c0da0ffSGleb Smirnoff if (BGE_IS_5705_OR_BEYOND(sc)) { 20443f74909aSGleb Smirnoff uint32_t v; 2045e53d81eeSPaul Saab 2046e53d81eeSPaul Saab v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4); 2047e53d81eeSPaul Saab if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) { 2048e53d81eeSPaul Saab v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2049e53d81eeSPaul Saab if ((v & 0xff) == BGE_PCIE_CAPID) 2050e53d81eeSPaul Saab sc->bge_pcie = 1; 2051e53d81eeSPaul Saab } 2052e53d81eeSPaul Saab } 2053e53d81eeSPaul Saab 20544c0da0ffSGleb Smirnoff /* 20554c0da0ffSGleb Smirnoff * PCI-X ? 20564c0da0ffSGleb Smirnoff */ 20574c0da0ffSGleb Smirnoff if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 20584c0da0ffSGleb Smirnoff BGE_PCISTATE_PCI_BUSMODE) == 0) 20594c0da0ffSGleb Smirnoff sc->bge_pcix = 1; 20604c0da0ffSGleb Smirnoff 206195d67482SBill Paul /* Try to reset the chip. */ 206295d67482SBill Paul bge_reset(sc); 206395d67482SBill Paul 206495d67482SBill Paul if (bge_chipinit(sc)) { 2065fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "chip initialization failed\n"); 206695d67482SBill Paul bge_release_resources(sc); 206795d67482SBill Paul error = ENXIO; 206895d67482SBill Paul goto fail; 206995d67482SBill Paul } 207095d67482SBill Paul 207195d67482SBill Paul /* 207295d67482SBill Paul * Get station address from the EEPROM. 207395d67482SBill Paul */ 2074fc74a9f9SBrooks Davis mac_tmp = bge_readmem_ind(sc, 0x0c14); 2075fc74a9f9SBrooks Davis if ((mac_tmp >> 16) == 0x484b) { 2076fc74a9f9SBrooks Davis eaddr[0] = (u_char)(mac_tmp >> 8); 2077fc74a9f9SBrooks Davis eaddr[1] = (u_char)mac_tmp; 2078fc74a9f9SBrooks Davis mac_tmp = bge_readmem_ind(sc, 0x0c18); 2079fc74a9f9SBrooks Davis eaddr[2] = (u_char)(mac_tmp >> 24); 2080fc74a9f9SBrooks Davis eaddr[3] = (u_char)(mac_tmp >> 16); 2081fc74a9f9SBrooks Davis eaddr[4] = (u_char)(mac_tmp >> 8); 2082fc74a9f9SBrooks Davis eaddr[5] = (u_char)mac_tmp; 2083fc74a9f9SBrooks Davis } else if (bge_read_eeprom(sc, eaddr, 208495d67482SBill Paul BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2085fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to read station address\n"); 208695d67482SBill Paul bge_release_resources(sc); 208795d67482SBill Paul error = ENXIO; 208895d67482SBill Paul goto fail; 208995d67482SBill Paul } 209095d67482SBill Paul 2091f41ac2beSBill Paul /* 5705 limits RX return ring to 512 entries. */ 20924c0da0ffSGleb Smirnoff if (BGE_IS_5705_OR_BEYOND(sc)) 2093f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2094f41ac2beSBill Paul else 2095f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2096f41ac2beSBill Paul 2097f41ac2beSBill Paul if (bge_dma_alloc(dev)) { 2098fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2099fe806fdaSPyun YongHyeon "failed to allocate DMA resources\n"); 2100f41ac2beSBill Paul bge_release_resources(sc); 2101f41ac2beSBill Paul error = ENXIO; 2102f41ac2beSBill Paul goto fail; 2103f41ac2beSBill Paul } 2104f41ac2beSBill Paul 210595d67482SBill Paul /* Set default tuneable values. */ 210695d67482SBill Paul sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 210795d67482SBill Paul sc->bge_rx_coal_ticks = 150; 210895d67482SBill Paul sc->bge_tx_coal_ticks = 150; 210995d67482SBill Paul sc->bge_rx_max_coal_bds = 64; 211095d67482SBill Paul sc->bge_tx_max_coal_bds = 128; 211195d67482SBill Paul 211295d67482SBill Paul /* Set up ifnet structure */ 2113fc74a9f9SBrooks Davis ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2114fc74a9f9SBrooks Davis if (ifp == NULL) { 2115fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2116fc74a9f9SBrooks Davis bge_release_resources(sc); 2117fc74a9f9SBrooks Davis error = ENXIO; 2118fc74a9f9SBrooks Davis goto fail; 2119fc74a9f9SBrooks Davis } 212095d67482SBill Paul ifp->if_softc = sc; 21219bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 212295d67482SBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 212395d67482SBill Paul ifp->if_ioctl = bge_ioctl; 212495d67482SBill Paul ifp->if_start = bge_start; 212595d67482SBill Paul ifp->if_watchdog = bge_watchdog; 212695d67482SBill Paul ifp->if_init = bge_init; 212795d67482SBill Paul ifp->if_mtu = ETHERMTU; 21284d665c4dSDag-Erling Smørgrav ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 21294d665c4dSDag-Erling Smørgrav IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 21304d665c4dSDag-Erling Smørgrav IFQ_SET_READY(&ifp->if_snd); 213195d67482SBill Paul ifp->if_hwassist = BGE_CSUM_FEATURES; 2132d375e524SGleb Smirnoff ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2133479b23b7SGleb Smirnoff IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM; 213495d67482SBill Paul ifp->if_capenable = ifp->if_capabilities; 213575719184SGleb Smirnoff #ifdef DEVICE_POLLING 213675719184SGleb Smirnoff ifp->if_capabilities |= IFCAP_POLLING; 213775719184SGleb Smirnoff #endif 213895d67482SBill Paul 2139a1d52896SBill Paul /* 2140d375e524SGleb Smirnoff * 5700 B0 chips do not support checksumming correctly due 2141d375e524SGleb Smirnoff * to hardware bugs. 2142d375e524SGleb Smirnoff */ 2143d375e524SGleb Smirnoff if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2144d375e524SGleb Smirnoff ifp->if_capabilities &= ~IFCAP_HWCSUM; 2145d375e524SGleb Smirnoff ifp->if_capenable &= IFCAP_HWCSUM; 2146d375e524SGleb Smirnoff ifp->if_hwassist = 0; 2147d375e524SGleb Smirnoff } 2148d375e524SGleb Smirnoff 2149d375e524SGleb Smirnoff /* 2150a1d52896SBill Paul * Figure out what sort of media we have by checking the 215141abcc1bSPaul Saab * hardware config word in the first 32k of NIC internal memory, 215241abcc1bSPaul Saab * or fall back to examining the EEPROM if necessary. 215341abcc1bSPaul Saab * Note: on some BCM5700 cards, this value appears to be unset. 215441abcc1bSPaul Saab * If that's the case, we have to rely on identifying the NIC 215541abcc1bSPaul Saab * by its PCI subsystem ID, as we do below for the SysKonnect 215641abcc1bSPaul Saab * SK-9D41. 2157a1d52896SBill Paul */ 215841abcc1bSPaul Saab if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 215941abcc1bSPaul Saab hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 216041abcc1bSPaul Saab else { 2161f6789fbaSPyun YongHyeon if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2162f6789fbaSPyun YongHyeon sizeof(hwcfg))) { 2163fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2164f6789fbaSPyun YongHyeon bge_release_resources(sc); 2165f6789fbaSPyun YongHyeon error = ENXIO; 2166f6789fbaSPyun YongHyeon goto fail; 2167f6789fbaSPyun YongHyeon } 216841abcc1bSPaul Saab hwcfg = ntohl(hwcfg); 216941abcc1bSPaul Saab } 217041abcc1bSPaul Saab 217141abcc1bSPaul Saab if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2172a1d52896SBill Paul sc->bge_tbi = 1; 2173a1d52896SBill Paul 217495d67482SBill Paul /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 217595d67482SBill Paul if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 217695d67482SBill Paul sc->bge_tbi = 1; 217795d67482SBill Paul 217895d67482SBill Paul if (sc->bge_tbi) { 217995d67482SBill Paul ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 218095d67482SBill Paul bge_ifmedia_upd, bge_ifmedia_sts); 218195d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 218295d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, 218395d67482SBill Paul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 218495d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 218595d67482SBill Paul ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2186da3003f0SBill Paul sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 218795d67482SBill Paul } else { 218895d67482SBill Paul /* 218995d67482SBill Paul * Do transceiver setup. 219095d67482SBill Paul */ 219195d67482SBill Paul if (mii_phy_probe(dev, &sc->bge_miibus, 219295d67482SBill Paul bge_ifmedia_upd, bge_ifmedia_sts)) { 2193fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "MII without any PHY!\n"); 219495d67482SBill Paul bge_release_resources(sc); 219595d67482SBill Paul error = ENXIO; 219695d67482SBill Paul goto fail; 219795d67482SBill Paul } 219895d67482SBill Paul } 219995d67482SBill Paul 220095d67482SBill Paul /* 2201e255b776SJohn Polstra * When using the BCM5701 in PCI-X mode, data corruption has 2202e255b776SJohn Polstra * been observed in the first few bytes of some received packets. 2203e255b776SJohn Polstra * Aligning the packet buffer in memory eliminates the corruption. 2204e255b776SJohn Polstra * Unfortunately, this misaligns the packet payloads. On platforms 2205e255b776SJohn Polstra * which do not support unaligned accesses, we will realign the 2206e255b776SJohn Polstra * payloads by copying the received packets. 2207e255b776SJohn Polstra */ 22084c0da0ffSGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && sc->bge_pcix) 2209e255b776SJohn Polstra sc->bge_rx_alignment_bug = 1; 2210e255b776SJohn Polstra 2211e255b776SJohn Polstra /* 221295d67482SBill Paul * Call MI attach routine. 221395d67482SBill Paul */ 2214fc74a9f9SBrooks Davis ether_ifattach(ifp, eaddr); 22150f9bd73bSSam Leffler callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE); 22160f9bd73bSSam Leffler 22170f9bd73bSSam Leffler /* 22180f9bd73bSSam Leffler * Hookup IRQ last. 22190f9bd73bSSam Leffler */ 22200f9bd73bSSam Leffler error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 22210f9bd73bSSam Leffler bge_intr, sc, &sc->bge_intrhand); 22220f9bd73bSSam Leffler 22230f9bd73bSSam Leffler if (error) { 2224fc74a9f9SBrooks Davis bge_detach(dev); 2225fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "couldn't set up irq\n"); 22260f9bd73bSSam Leffler } 222795d67482SBill Paul 222895d67482SBill Paul fail: 222995d67482SBill Paul return (error); 223095d67482SBill Paul } 223195d67482SBill Paul 223295d67482SBill Paul static int 22333f74909aSGleb Smirnoff bge_detach(device_t dev) 223495d67482SBill Paul { 223595d67482SBill Paul struct bge_softc *sc; 223695d67482SBill Paul struct ifnet *ifp; 223795d67482SBill Paul 223895d67482SBill Paul sc = device_get_softc(dev); 2239fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 224095d67482SBill Paul 224175719184SGleb Smirnoff #ifdef DEVICE_POLLING 224275719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 224375719184SGleb Smirnoff ether_poll_deregister(ifp); 224475719184SGleb Smirnoff #endif 224575719184SGleb Smirnoff 22460f9bd73bSSam Leffler BGE_LOCK(sc); 224795d67482SBill Paul bge_stop(sc); 224895d67482SBill Paul bge_reset(sc); 22490f9bd73bSSam Leffler BGE_UNLOCK(sc); 22500f9bd73bSSam Leffler 22510f9bd73bSSam Leffler ether_ifdetach(ifp); 225295d67482SBill Paul 225395d67482SBill Paul if (sc->bge_tbi) { 225495d67482SBill Paul ifmedia_removeall(&sc->bge_ifmedia); 225595d67482SBill Paul } else { 225695d67482SBill Paul bus_generic_detach(dev); 225795d67482SBill Paul device_delete_child(dev, sc->bge_miibus); 225895d67482SBill Paul } 225995d67482SBill Paul 226095d67482SBill Paul bge_release_resources(sc); 226195d67482SBill Paul 226295d67482SBill Paul return (0); 226395d67482SBill Paul } 226495d67482SBill Paul 226595d67482SBill Paul static void 22663f74909aSGleb Smirnoff bge_release_resources(struct bge_softc *sc) 226795d67482SBill Paul { 226895d67482SBill Paul device_t dev; 226995d67482SBill Paul 227095d67482SBill Paul dev = sc->bge_dev; 227195d67482SBill Paul 227295d67482SBill Paul if (sc->bge_vpd_prodname != NULL) 227395d67482SBill Paul free(sc->bge_vpd_prodname, M_DEVBUF); 227495d67482SBill Paul 227595d67482SBill Paul if (sc->bge_vpd_readonly != NULL) 227695d67482SBill Paul free(sc->bge_vpd_readonly, M_DEVBUF); 227795d67482SBill Paul 227895d67482SBill Paul if (sc->bge_intrhand != NULL) 227995d67482SBill Paul bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 228095d67482SBill Paul 228195d67482SBill Paul if (sc->bge_irq != NULL) 228295d67482SBill Paul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 228395d67482SBill Paul 228495d67482SBill Paul if (sc->bge_res != NULL) 228595d67482SBill Paul bus_release_resource(dev, SYS_RES_MEMORY, 228695d67482SBill Paul BGE_PCI_BAR0, sc->bge_res); 228795d67482SBill Paul 2288ad61f896SRuslan Ermilov if (sc->bge_ifp != NULL) 2289ad61f896SRuslan Ermilov if_free(sc->bge_ifp); 2290ad61f896SRuslan Ermilov 2291f41ac2beSBill Paul bge_dma_free(sc); 229295d67482SBill Paul 22930f9bd73bSSam Leffler if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 22940f9bd73bSSam Leffler BGE_LOCK_DESTROY(sc); 229595d67482SBill Paul } 229695d67482SBill Paul 229795d67482SBill Paul static void 22983f74909aSGleb Smirnoff bge_reset(struct bge_softc *sc) 229995d67482SBill Paul { 230095d67482SBill Paul device_t dev; 23013f74909aSGleb Smirnoff uint32_t cachesize, command, pcistate, reset; 230295d67482SBill Paul int i, val = 0; 230395d67482SBill Paul 230495d67482SBill Paul dev = sc->bge_dev; 230595d67482SBill Paul 230695d67482SBill Paul /* Save some important PCI state. */ 230795d67482SBill Paul cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 230895d67482SBill Paul command = pci_read_config(dev, BGE_PCI_CMD, 4); 230995d67482SBill Paul pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 231095d67482SBill Paul 231195d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 231295d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2313e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4); 231495d67482SBill Paul 2315e53d81eeSPaul Saab reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2316e53d81eeSPaul Saab 2317e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 2318e53d81eeSPaul Saab if (sc->bge_pcie) { 2319e53d81eeSPaul Saab if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */ 2320e53d81eeSPaul Saab CSR_WRITE_4(sc, 0x7e2c, 0x20); 2321e53d81eeSPaul Saab if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2322e53d81eeSPaul Saab /* Prevent PCIE link training during global reset */ 2323e53d81eeSPaul Saab CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2324e53d81eeSPaul Saab reset |= (1<<29); 2325e53d81eeSPaul Saab } 2326e53d81eeSPaul Saab } 2327e53d81eeSPaul Saab 232895d67482SBill Paul /* Issue global reset */ 2329e53d81eeSPaul Saab bge_writereg_ind(sc, BGE_MISC_CFG, reset); 233095d67482SBill Paul 233195d67482SBill Paul DELAY(1000); 233295d67482SBill Paul 2333e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 2334e53d81eeSPaul Saab if (sc->bge_pcie) { 2335e53d81eeSPaul Saab if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2336e53d81eeSPaul Saab uint32_t v; 2337e53d81eeSPaul Saab 2338e53d81eeSPaul Saab DELAY(500000); /* wait for link training to complete */ 2339e53d81eeSPaul Saab v = pci_read_config(dev, 0xc4, 4); 2340e53d81eeSPaul Saab pci_write_config(dev, 0xc4, v | (1<<15), 4); 2341e53d81eeSPaul Saab } 2342e53d81eeSPaul Saab /* Set PCIE max payload size and clear error status. */ 2343e53d81eeSPaul Saab pci_write_config(dev, 0xd8, 0xf5000, 4); 2344e53d81eeSPaul Saab } 2345e53d81eeSPaul Saab 23463f74909aSGleb Smirnoff /* Reset some of the PCI state that got zapped by reset. */ 234795d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 234895d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2349e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4); 235095d67482SBill Paul pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 235195d67482SBill Paul pci_write_config(dev, BGE_PCI_CMD, command, 4); 235295d67482SBill Paul bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 235395d67482SBill Paul 2354a7b0c314SPaul Saab /* Enable memory arbiter. */ 23554c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 23564c0da0ffSGleb Smirnoff uint32_t val; 23574c0da0ffSGleb Smirnoff 23584c0da0ffSGleb Smirnoff val = CSR_READ_4(sc, BGE_MARB_MODE); 23594c0da0ffSGleb Smirnoff CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 23604c0da0ffSGleb Smirnoff } else 2361a7b0c314SPaul Saab CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2362a7b0c314SPaul Saab 236395d67482SBill Paul /* 236495d67482SBill Paul * Prevent PXE restart: write a magic number to the 236595d67482SBill Paul * general communications memory at 0xB50. 236695d67482SBill Paul */ 236795d67482SBill Paul bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 236895d67482SBill Paul /* 236995d67482SBill Paul * Poll the value location we just wrote until 237095d67482SBill Paul * we see the 1's complement of the magic number. 237195d67482SBill Paul * This indicates that the firmware initialization 237295d67482SBill Paul * is complete. 237395d67482SBill Paul */ 237495d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 237595d67482SBill Paul val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 237695d67482SBill Paul if (val == ~BGE_MAGIC_NUMBER) 237795d67482SBill Paul break; 237895d67482SBill Paul DELAY(10); 237995d67482SBill Paul } 238095d67482SBill Paul 238195d67482SBill Paul if (i == BGE_TIMEOUT) { 2382fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "firmware handshake timed out\n"); 238395d67482SBill Paul return; 238495d67482SBill Paul } 238595d67482SBill Paul 238695d67482SBill Paul /* 238795d67482SBill Paul * XXX Wait for the value of the PCISTATE register to 238895d67482SBill Paul * return to its original pre-reset state. This is a 238995d67482SBill Paul * fairly good indicator of reset completion. If we don't 239095d67482SBill Paul * wait for the reset to fully complete, trying to read 239195d67482SBill Paul * from the device's non-PCI registers may yield garbage 239295d67482SBill Paul * results. 239395d67482SBill Paul */ 239495d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 239595d67482SBill Paul if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 239695d67482SBill Paul break; 239795d67482SBill Paul DELAY(10); 239895d67482SBill Paul } 239995d67482SBill Paul 24003f74909aSGleb Smirnoff /* Fix up byte swapping. */ 2401e907febfSPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 240295d67482SBill Paul BGE_MODECTL_BYTESWAP_DATA); 240395d67482SBill Paul 240495d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 240595d67482SBill Paul 2406da3003f0SBill Paul /* 2407da3003f0SBill Paul * The 5704 in TBI mode apparently needs some special 2408da3003f0SBill Paul * adjustment to insure the SERDES drive level is set 2409da3003f0SBill Paul * to 1.2V. 2410da3003f0SBill Paul */ 2411da3003f0SBill Paul if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) { 2412da3003f0SBill Paul uint32_t serdescfg; 2413da3003f0SBill Paul serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2414da3003f0SBill Paul serdescfg = (serdescfg & ~0xFFF) | 0x880; 2415da3003f0SBill Paul CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2416da3003f0SBill Paul } 2417da3003f0SBill Paul 2418e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 2419e53d81eeSPaul Saab if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2420e53d81eeSPaul Saab uint32_t v; 2421e53d81eeSPaul Saab 2422e53d81eeSPaul Saab v = CSR_READ_4(sc, 0x7c00); 2423e53d81eeSPaul Saab CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 2424e53d81eeSPaul Saab } 242595d67482SBill Paul DELAY(10000); 242695d67482SBill Paul } 242795d67482SBill Paul 242895d67482SBill Paul /* 242995d67482SBill Paul * Frame reception handling. This is called if there's a frame 243095d67482SBill Paul * on the receive return list. 243195d67482SBill Paul * 243295d67482SBill Paul * Note: we have to be able to handle two possibilities here: 24331be6acb7SGleb Smirnoff * 1) the frame is from the jumbo receive ring 243495d67482SBill Paul * 2) the frame is from the standard receive ring 243595d67482SBill Paul */ 243695d67482SBill Paul 243795d67482SBill Paul static void 24383f74909aSGleb Smirnoff bge_rxeof(struct bge_softc *sc) 243995d67482SBill Paul { 244095d67482SBill Paul struct ifnet *ifp; 244195d67482SBill Paul int stdcnt = 0, jumbocnt = 0; 244295d67482SBill Paul 24430f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 24440f9bd73bSSam Leffler 24453f74909aSGleb Smirnoff /* Nothing to do. */ 2446cfcb5025SOleg Bulyzhin if (sc->bge_rx_saved_considx == 2447cfcb5025SOleg Bulyzhin sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 2448cfcb5025SOleg Bulyzhin return; 2449cfcb5025SOleg Bulyzhin 2450fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 245195d67482SBill Paul 2452f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2453e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2454f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2455f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 24564c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) 2457f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 24584c0da0ffSGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 2459f41ac2beSBill Paul 246095d67482SBill Paul while(sc->bge_rx_saved_considx != 2461f41ac2beSBill Paul sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 246295d67482SBill Paul struct bge_rx_bd *cur_rx; 24633f74909aSGleb Smirnoff uint32_t rxidx; 246495d67482SBill Paul struct mbuf *m = NULL; 24653f74909aSGleb Smirnoff uint16_t vlan_tag = 0; 246695d67482SBill Paul int have_tag = 0; 246795d67482SBill Paul 246875719184SGleb Smirnoff #ifdef DEVICE_POLLING 246975719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 247075719184SGleb Smirnoff if (sc->rxcycles <= 0) 247175719184SGleb Smirnoff break; 247275719184SGleb Smirnoff sc->rxcycles--; 247375719184SGleb Smirnoff } 247475719184SGleb Smirnoff #endif 247575719184SGleb Smirnoff 247695d67482SBill Paul cur_rx = 2477f41ac2beSBill Paul &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 247895d67482SBill Paul 247995d67482SBill Paul rxidx = cur_rx->bge_idx; 24800434d1b8SBill Paul BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 248195d67482SBill Paul 248295d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 248395d67482SBill Paul have_tag = 1; 248495d67482SBill Paul vlan_tag = cur_rx->bge_vlan_tag; 248595d67482SBill Paul } 248695d67482SBill Paul 248795d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 248895d67482SBill Paul BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2489f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2490f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2491f41ac2beSBill Paul BUS_DMASYNC_POSTREAD); 2492f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2493f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 249495d67482SBill Paul m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 249595d67482SBill Paul sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 249695d67482SBill Paul jumbocnt++; 249795d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 249895d67482SBill Paul ifp->if_ierrors++; 249995d67482SBill Paul bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 250095d67482SBill Paul continue; 250195d67482SBill Paul } 250295d67482SBill Paul if (bge_newbuf_jumbo(sc, 250395d67482SBill Paul sc->bge_jumbo, NULL) == ENOBUFS) { 250495d67482SBill Paul ifp->if_ierrors++; 250595d67482SBill Paul bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 250695d67482SBill Paul continue; 250795d67482SBill Paul } 250895d67482SBill Paul } else { 250995d67482SBill Paul BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2510f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2511f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2512f41ac2beSBill Paul BUS_DMASYNC_POSTREAD); 2513f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2514f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 251595d67482SBill Paul m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 251695d67482SBill Paul sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 251795d67482SBill Paul stdcnt++; 251895d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 251995d67482SBill Paul ifp->if_ierrors++; 252095d67482SBill Paul bge_newbuf_std(sc, sc->bge_std, m); 252195d67482SBill Paul continue; 252295d67482SBill Paul } 252395d67482SBill Paul if (bge_newbuf_std(sc, sc->bge_std, 252495d67482SBill Paul NULL) == ENOBUFS) { 252595d67482SBill Paul ifp->if_ierrors++; 252695d67482SBill Paul bge_newbuf_std(sc, sc->bge_std, m); 252795d67482SBill Paul continue; 252895d67482SBill Paul } 252995d67482SBill Paul } 253095d67482SBill Paul 253195d67482SBill Paul ifp->if_ipackets++; 2532e65bed95SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 2533e255b776SJohn Polstra /* 2534e65bed95SPyun YongHyeon * For architectures with strict alignment we must make sure 2535e65bed95SPyun YongHyeon * the payload is aligned. 2536e255b776SJohn Polstra */ 2537e255b776SJohn Polstra if (sc->bge_rx_alignment_bug) { 2538e255b776SJohn Polstra bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2539e255b776SJohn Polstra cur_rx->bge_len); 2540e255b776SJohn Polstra m->m_data += ETHER_ALIGN; 2541e255b776SJohn Polstra } 2542e255b776SJohn Polstra #endif 2543473851baSPaul Saab m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 254495d67482SBill Paul m->m_pkthdr.rcvif = ifp; 254595d67482SBill Paul 2546b874fdd4SYaroslav Tykhiy if (ifp->if_capenable & IFCAP_RXCSUM) { 254778178cd1SGleb Smirnoff if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 254895d67482SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 254995d67482SBill Paul if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 255095d67482SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 255178178cd1SGleb Smirnoff } 2552d375e524SGleb Smirnoff if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2553d375e524SGleb Smirnoff m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 255495d67482SBill Paul m->m_pkthdr.csum_data = 255595d67482SBill Paul cur_rx->bge_tcp_udp_csum; 2556ee7ef91cSOleg Bulyzhin m->m_pkthdr.csum_flags |= 2557ee7ef91cSOleg Bulyzhin CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 255895d67482SBill Paul } 255995d67482SBill Paul } 256095d67482SBill Paul 256195d67482SBill Paul /* 2562673d9191SSam Leffler * If we received a packet with a vlan tag, 2563673d9191SSam Leffler * attach that information to the packet. 256495d67482SBill Paul */ 2565d147662cSGleb Smirnoff if (have_tag) { 2566d147662cSGleb Smirnoff VLAN_INPUT_TAG(ifp, m, vlan_tag); 2567d147662cSGleb Smirnoff if (m == NULL) 2568d147662cSGleb Smirnoff continue; 2569d147662cSGleb Smirnoff } 257095d67482SBill Paul 25710f9bd73bSSam Leffler BGE_UNLOCK(sc); 2572673d9191SSam Leffler (*ifp->if_input)(ifp, m); 25730f9bd73bSSam Leffler BGE_LOCK(sc); 257495d67482SBill Paul } 257595d67482SBill Paul 2576e65bed95SPyun YongHyeon if (stdcnt > 0) 2577f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2578e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 25794c0da0ffSGleb Smirnoff 25804c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 2581f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 25824c0da0ffSGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2583f41ac2beSBill Paul 258495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 258595d67482SBill Paul if (stdcnt) 258695d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 258795d67482SBill Paul if (jumbocnt) 258895d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 258995d67482SBill Paul } 259095d67482SBill Paul 259195d67482SBill Paul static void 25923f74909aSGleb Smirnoff bge_txeof(struct bge_softc *sc) 259395d67482SBill Paul { 259495d67482SBill Paul struct bge_tx_bd *cur_tx = NULL; 259595d67482SBill Paul struct ifnet *ifp; 259695d67482SBill Paul 25970f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 25980f9bd73bSSam Leffler 25993f74909aSGleb Smirnoff /* Nothing to do. */ 2600cfcb5025SOleg Bulyzhin if (sc->bge_tx_saved_considx == 2601cfcb5025SOleg Bulyzhin sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 2602cfcb5025SOleg Bulyzhin return; 2603cfcb5025SOleg Bulyzhin 2604fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 260595d67482SBill Paul 2606e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 2607e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, 2608e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 260995d67482SBill Paul /* 261095d67482SBill Paul * Go through our tx ring and free mbufs for those 261195d67482SBill Paul * frames that have been sent. 261295d67482SBill Paul */ 261395d67482SBill Paul while (sc->bge_tx_saved_considx != 2614f41ac2beSBill Paul sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 26153f74909aSGleb Smirnoff uint32_t idx = 0; 261695d67482SBill Paul 261795d67482SBill Paul idx = sc->bge_tx_saved_considx; 2618f41ac2beSBill Paul cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 261995d67482SBill Paul if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 262095d67482SBill Paul ifp->if_opackets++; 262195d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2622e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2623e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[idx], 2624e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 2625f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2626f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[idx]); 2627e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2628e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[idx] = NULL; 262995d67482SBill Paul } 263095d67482SBill Paul sc->bge_txcnt--; 263195d67482SBill Paul BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 263295d67482SBill Paul ifp->if_timer = 0; 263395d67482SBill Paul } 263495d67482SBill Paul 263595d67482SBill Paul if (cur_tx != NULL) 263613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 263795d67482SBill Paul } 263895d67482SBill Paul 263975719184SGleb Smirnoff #ifdef DEVICE_POLLING 264075719184SGleb Smirnoff static void 264175719184SGleb Smirnoff bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 264275719184SGleb Smirnoff { 264375719184SGleb Smirnoff struct bge_softc *sc = ifp->if_softc; 2644366454f2SOleg Bulyzhin uint32_t statusword; 264575719184SGleb Smirnoff 26463f74909aSGleb Smirnoff BGE_LOCK(sc); 26473f74909aSGleb Smirnoff if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 26483f74909aSGleb Smirnoff BGE_UNLOCK(sc); 26493f74909aSGleb Smirnoff return; 26503f74909aSGleb Smirnoff } 265175719184SGleb Smirnoff 2652dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2653e65bed95SPyun YongHyeon sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 2654dab5cd05SOleg Bulyzhin 26553f74909aSGleb Smirnoff statusword = atomic_readandclear_32( 26563f74909aSGleb Smirnoff &sc->bge_ldata.bge_status_block->bge_status); 2657dab5cd05SOleg Bulyzhin 2658dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2659e65bed95SPyun YongHyeon sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 2660366454f2SOleg Bulyzhin 2661366454f2SOleg Bulyzhin /* Note link event. It will be processed by POLL_AND_CHECK_STATUS cmd */ 2662366454f2SOleg Bulyzhin if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 2663366454f2SOleg Bulyzhin sc->bge_link_evt++; 2664366454f2SOleg Bulyzhin 2665366454f2SOleg Bulyzhin if (cmd == POLL_AND_CHECK_STATUS) 2666366454f2SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 26674c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 2668366454f2SOleg Bulyzhin sc->bge_link_evt || sc->bge_tbi) 2669366454f2SOleg Bulyzhin bge_link_upd(sc); 2670366454f2SOleg Bulyzhin 2671366454f2SOleg Bulyzhin sc->rxcycles = count; 2672366454f2SOleg Bulyzhin bge_rxeof(sc); 2673366454f2SOleg Bulyzhin bge_txeof(sc); 2674366454f2SOleg Bulyzhin if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2675366454f2SOleg Bulyzhin bge_start_locked(ifp); 26763f74909aSGleb Smirnoff 26773f74909aSGleb Smirnoff BGE_UNLOCK(sc); 267875719184SGleb Smirnoff } 267975719184SGleb Smirnoff #endif /* DEVICE_POLLING */ 268075719184SGleb Smirnoff 268195d67482SBill Paul static void 26823f74909aSGleb Smirnoff bge_intr(void *xsc) 268395d67482SBill Paul { 268495d67482SBill Paul struct bge_softc *sc; 268595d67482SBill Paul struct ifnet *ifp; 2686dab5cd05SOleg Bulyzhin uint32_t statusword; 268795d67482SBill Paul 268895d67482SBill Paul sc = xsc; 2689f41ac2beSBill Paul 26900f9bd73bSSam Leffler BGE_LOCK(sc); 26910f9bd73bSSam Leffler 2692dab5cd05SOleg Bulyzhin ifp = sc->bge_ifp; 2693dab5cd05SOleg Bulyzhin 269475719184SGleb Smirnoff #ifdef DEVICE_POLLING 269575719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 269675719184SGleb Smirnoff BGE_UNLOCK(sc); 269775719184SGleb Smirnoff return; 269875719184SGleb Smirnoff } 269975719184SGleb Smirnoff #endif 270075719184SGleb Smirnoff 2701f30cbfc6SScott Long /* 2702f30cbfc6SScott Long * Do the mandatory PCI flush as well as get the link status. 2703f30cbfc6SScott Long */ 2704f30cbfc6SScott Long statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 2705f41ac2beSBill Paul 270695d67482SBill Paul /* Ack interrupt and stop others from occuring. */ 270795d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 270895d67482SBill Paul 2709f30cbfc6SScott Long /* Make sure the descriptor ring indexes are coherent. */ 2710f30cbfc6SScott Long bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2711f30cbfc6SScott Long sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 2712f30cbfc6SScott Long bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2713f30cbfc6SScott Long sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 2714f30cbfc6SScott Long 27151f313773SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 27164c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 2717f30cbfc6SScott Long statusword || sc->bge_link_evt) 2718dab5cd05SOleg Bulyzhin bge_link_upd(sc); 271995d67482SBill Paul 272013f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 27213f74909aSGleb Smirnoff /* Check RX return ring producer/consumer. */ 272295d67482SBill Paul bge_rxeof(sc); 272395d67482SBill Paul 27243f74909aSGleb Smirnoff /* Check TX ring producer/consumer. */ 272595d67482SBill Paul bge_txeof(sc); 272695d67482SBill Paul } 272795d67482SBill Paul 272895d67482SBill Paul /* Re-enable interrupts. */ 272995d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 273095d67482SBill Paul 273113f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 273213f4c340SRobert Watson !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 27330f9bd73bSSam Leffler bge_start_locked(ifp); 27340f9bd73bSSam Leffler 27350f9bd73bSSam Leffler BGE_UNLOCK(sc); 273695d67482SBill Paul } 273795d67482SBill Paul 273895d67482SBill Paul static void 27393f74909aSGleb Smirnoff bge_tick_locked(struct bge_softc *sc) 27400f9bd73bSSam Leffler { 274195d67482SBill Paul struct mii_data *mii = NULL; 274295d67482SBill Paul 27430f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 274495d67482SBill Paul 27454c0da0ffSGleb Smirnoff if (BGE_IS_5705_OR_BEYOND(sc)) 27460434d1b8SBill Paul bge_stats_update_regs(sc); 27470434d1b8SBill Paul else 274895d67482SBill Paul bge_stats_update(sc); 274995d67482SBill Paul 27501f313773SOleg Bulyzhin if (!sc->bge_tbi) { 275195d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 275295d67482SBill Paul mii_tick(mii); 27537b97099dSOleg Bulyzhin } else { 27547b97099dSOleg Bulyzhin /* 27557b97099dSOleg Bulyzhin * Since in TBI mode auto-polling can't be used we should poll 27567b97099dSOleg Bulyzhin * link status manually. Here we register pending link event 27577b97099dSOleg Bulyzhin * and trigger interrupt. 27587b97099dSOleg Bulyzhin */ 27597b97099dSOleg Bulyzhin #ifdef DEVICE_POLLING 27603f74909aSGleb Smirnoff /* In polling mode we poll link state in bge_poll(). */ 27617b97099dSOleg Bulyzhin if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 27627b97099dSOleg Bulyzhin #endif 27637b97099dSOleg Bulyzhin { 27647b97099dSOleg Bulyzhin sc->bge_link_evt++; 27657b97099dSOleg Bulyzhin BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 27667b97099dSOleg Bulyzhin } 2767dab5cd05SOleg Bulyzhin } 276895d67482SBill Paul 2769dab5cd05SOleg Bulyzhin callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 277095d67482SBill Paul } 277195d67482SBill Paul 277295d67482SBill Paul static void 27733f74909aSGleb Smirnoff bge_tick(void *xsc) 27740f9bd73bSSam Leffler { 27750f9bd73bSSam Leffler struct bge_softc *sc; 27760f9bd73bSSam Leffler 27770f9bd73bSSam Leffler sc = xsc; 27780f9bd73bSSam Leffler 27790f9bd73bSSam Leffler BGE_LOCK(sc); 27800f9bd73bSSam Leffler bge_tick_locked(sc); 27810f9bd73bSSam Leffler BGE_UNLOCK(sc); 27820f9bd73bSSam Leffler } 27830f9bd73bSSam Leffler 27840f9bd73bSSam Leffler static void 27853f74909aSGleb Smirnoff bge_stats_update_regs(struct bge_softc *sc) 27860434d1b8SBill Paul { 27870434d1b8SBill Paul struct bge_mac_stats_regs stats; 27883f74909aSGleb Smirnoff struct ifnet *ifp; 27893f74909aSGleb Smirnoff uint32_t *s; 27906fb34dd2SOleg Bulyzhin u_long cnt; /* current register value */ 27910434d1b8SBill Paul int i; 27920434d1b8SBill Paul 2793fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 27940434d1b8SBill Paul 27953f74909aSGleb Smirnoff s = (uint32_t *)&stats; 27960434d1b8SBill Paul for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 27970434d1b8SBill Paul *s = CSR_READ_4(sc, BGE_RX_STATS + i); 27980434d1b8SBill Paul s++; 27990434d1b8SBill Paul } 28000434d1b8SBill Paul 28016fb34dd2SOleg Bulyzhin cnt = stats.dot3StatsSingleCollisionFrames + 28020434d1b8SBill Paul stats.dot3StatsMultipleCollisionFrames + 28030434d1b8SBill Paul stats.dot3StatsExcessiveCollisions + 28046fb34dd2SOleg Bulyzhin stats.dot3StatsLateCollisions; 28056fb34dd2SOleg Bulyzhin ifp->if_collisions += cnt >= sc->bge_tx_collisions ? 28066fb34dd2SOleg Bulyzhin cnt - sc->bge_tx_collisions : cnt; 28076fb34dd2SOleg Bulyzhin sc->bge_tx_collisions = cnt; 28080434d1b8SBill Paul } 28090434d1b8SBill Paul 28100434d1b8SBill Paul static void 28113f74909aSGleb Smirnoff bge_stats_update(struct bge_softc *sc) 281295d67482SBill Paul { 281395d67482SBill Paul struct ifnet *ifp; 2814e907febfSPyun YongHyeon bus_size_t stats; 28156fb34dd2SOleg Bulyzhin u_long cnt; /* current register value */ 281695d67482SBill Paul 2817fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 281895d67482SBill Paul 2819e907febfSPyun YongHyeon stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2820e907febfSPyun YongHyeon 2821e907febfSPyun YongHyeon #define READ_STAT(sc, stats, stat) \ 2822e907febfSPyun YongHyeon CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 282395d67482SBill Paul 28246fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, 28256fb34dd2SOleg Bulyzhin txstats.dot3StatsSingleCollisionFrames.bge_addr_lo); 28266fb34dd2SOleg Bulyzhin cnt += READ_STAT(sc, stats, 28276fb34dd2SOleg Bulyzhin txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo); 28286fb34dd2SOleg Bulyzhin cnt += READ_STAT(sc, stats, 28296fb34dd2SOleg Bulyzhin txstats.dot3StatsExcessiveCollisions.bge_addr_lo); 28306fb34dd2SOleg Bulyzhin cnt += READ_STAT(sc, stats, 28316fb34dd2SOleg Bulyzhin txstats.dot3StatsLateCollisions.bge_addr_lo); 28326fb34dd2SOleg Bulyzhin ifp->if_collisions += cnt >= sc->bge_tx_collisions ? 28336fb34dd2SOleg Bulyzhin cnt - sc->bge_tx_collisions : cnt; 28346fb34dd2SOleg Bulyzhin sc->bge_tx_collisions = cnt; 28356fb34dd2SOleg Bulyzhin 28366fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 28376fb34dd2SOleg Bulyzhin ifp->if_ierrors += cnt >= sc->bge_rx_discards ? 28386fb34dd2SOleg Bulyzhin cnt - sc->bge_rx_discards : cnt; 28396fb34dd2SOleg Bulyzhin sc->bge_rx_discards = cnt; 28406fb34dd2SOleg Bulyzhin 28416fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 28426fb34dd2SOleg Bulyzhin ifp->if_oerrors += cnt >= sc->bge_tx_discards ? 28436fb34dd2SOleg Bulyzhin cnt - sc->bge_tx_discards : cnt; 28446fb34dd2SOleg Bulyzhin sc->bge_tx_discards = cnt; 284595d67482SBill Paul 2846e907febfSPyun YongHyeon #undef READ_STAT 284795d67482SBill Paul } 284895d67482SBill Paul 284995d67482SBill Paul /* 2850d375e524SGleb Smirnoff * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2851d375e524SGleb Smirnoff * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2852d375e524SGleb Smirnoff * but when such padded frames employ the bge IP/TCP checksum offload, 2853d375e524SGleb Smirnoff * the hardware checksum assist gives incorrect results (possibly 2854d375e524SGleb Smirnoff * from incorporating its own padding into the UDP/TCP checksum; who knows). 2855d375e524SGleb Smirnoff * If we pad such runts with zeros, the onboard checksum comes out correct. 2856d375e524SGleb Smirnoff */ 2857d375e524SGleb Smirnoff static __inline int 2858d375e524SGleb Smirnoff bge_cksum_pad(struct mbuf *m) 2859d375e524SGleb Smirnoff { 2860d375e524SGleb Smirnoff int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 2861d375e524SGleb Smirnoff struct mbuf *last; 2862d375e524SGleb Smirnoff 2863d375e524SGleb Smirnoff /* If there's only the packet-header and we can pad there, use it. */ 2864d375e524SGleb Smirnoff if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 2865d375e524SGleb Smirnoff M_TRAILINGSPACE(m) >= padlen) { 2866d375e524SGleb Smirnoff last = m; 2867d375e524SGleb Smirnoff } else { 2868d375e524SGleb Smirnoff /* 2869d375e524SGleb Smirnoff * Walk packet chain to find last mbuf. We will either 2870d375e524SGleb Smirnoff * pad there, or append a new mbuf and pad it. 2871d375e524SGleb Smirnoff */ 2872d375e524SGleb Smirnoff for (last = m; last->m_next != NULL; last = last->m_next); 2873d375e524SGleb Smirnoff if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 2874d375e524SGleb Smirnoff /* Allocate new empty mbuf, pad it. Compact later. */ 2875d375e524SGleb Smirnoff struct mbuf *n; 2876d375e524SGleb Smirnoff 2877d375e524SGleb Smirnoff MGET(n, M_DONTWAIT, MT_DATA); 2878d375e524SGleb Smirnoff if (n == NULL) 2879d375e524SGleb Smirnoff return (ENOBUFS); 2880d375e524SGleb Smirnoff n->m_len = 0; 2881d375e524SGleb Smirnoff last->m_next = n; 2882d375e524SGleb Smirnoff last = n; 2883d375e524SGleb Smirnoff } 2884d375e524SGleb Smirnoff } 2885d375e524SGleb Smirnoff 2886d375e524SGleb Smirnoff /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 2887d375e524SGleb Smirnoff memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2888d375e524SGleb Smirnoff last->m_len += padlen; 2889d375e524SGleb Smirnoff m->m_pkthdr.len += padlen; 2890d375e524SGleb Smirnoff 2891d375e524SGleb Smirnoff return (0); 2892d375e524SGleb Smirnoff } 2893d375e524SGleb Smirnoff 2894d375e524SGleb Smirnoff /* 289595d67482SBill Paul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 289695d67482SBill Paul * pointers to descriptors. 289795d67482SBill Paul */ 289895d67482SBill Paul static int 28993f74909aSGleb Smirnoff bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 290095d67482SBill Paul { 29017e27542aSGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_NEW]; 2902f41ac2beSBill Paul bus_dmamap_t map; 29037e27542aSGleb Smirnoff struct bge_tx_bd *d = NULL; 29047e27542aSGleb Smirnoff struct m_tag *mtag; 29057e27542aSGleb Smirnoff uint32_t idx = *txidx; 29067e27542aSGleb Smirnoff uint16_t csum_flags = 0; 29077e27542aSGleb Smirnoff int nsegs, i, error; 290895d67482SBill Paul 290995d67482SBill Paul if (m_head->m_pkthdr.csum_flags) { 291095d67482SBill Paul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 291195d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2912d375e524SGleb Smirnoff if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 291395d67482SBill Paul csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2914d375e524SGleb Smirnoff if (m_head->m_pkthdr.len < ETHER_MIN_NOPAD && 2915d375e524SGleb Smirnoff bge_cksum_pad(m_head) != 0) 2916d375e524SGleb Smirnoff return (ENOBUFS); 2917d375e524SGleb Smirnoff } 291895d67482SBill Paul if (m_head->m_flags & M_LASTFRAG) 291995d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 292095d67482SBill Paul else if (m_head->m_flags & M_FRAG) 292195d67482SBill Paul csum_flags |= BGE_TXBDFLAG_IP_FRAG; 292295d67482SBill Paul } 292395d67482SBill Paul 2924fc74a9f9SBrooks Davis mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m_head); 2925673d9191SSam Leffler 29267e27542aSGleb Smirnoff map = sc->bge_cdata.bge_tx_dmamap[idx]; 29277e27542aSGleb Smirnoff error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, 29287e27542aSGleb Smirnoff m_head, segs, &nsegs, BUS_DMA_NOWAIT); 29297e27542aSGleb Smirnoff if (error) { 29307e27542aSGleb Smirnoff if (error == EFBIG) { 29317e27542aSGleb Smirnoff struct mbuf *m0; 29327e27542aSGleb Smirnoff 29337e27542aSGleb Smirnoff m0 = m_defrag(m_head, M_DONTWAIT); 29347e27542aSGleb Smirnoff if (m0 == NULL) 29357e27542aSGleb Smirnoff return (ENOBUFS); 29367e27542aSGleb Smirnoff m_head = m0; 29377e27542aSGleb Smirnoff error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, 29387e27542aSGleb Smirnoff map, m_head, segs, &nsegs, BUS_DMA_NOWAIT); 29397e27542aSGleb Smirnoff } 29407e27542aSGleb Smirnoff if (error) 29417e27542aSGleb Smirnoff return (error); 29427e27542aSGleb Smirnoff } 29437e27542aSGleb Smirnoff 294495d67482SBill Paul /* 294595d67482SBill Paul * Sanity check: avoid coming within 16 descriptors 294695d67482SBill Paul * of the end of the ring. 294795d67482SBill Paul */ 29487e27542aSGleb Smirnoff if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 29497e27542aSGleb Smirnoff bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 295095d67482SBill Paul return (ENOBUFS); 29517e27542aSGleb Smirnoff } 29527e27542aSGleb Smirnoff 2953e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 2954e65bed95SPyun YongHyeon 29557e27542aSGleb Smirnoff for (i = 0; ; i++) { 29567e27542aSGleb Smirnoff d = &sc->bge_ldata.bge_tx_ring[idx]; 29577e27542aSGleb Smirnoff d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 29587e27542aSGleb Smirnoff d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 29597e27542aSGleb Smirnoff d->bge_len = segs[i].ds_len; 29607e27542aSGleb Smirnoff d->bge_flags = csum_flags; 29617e27542aSGleb Smirnoff if (i == nsegs - 1) 29627e27542aSGleb Smirnoff break; 29637e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 29647e27542aSGleb Smirnoff } 29657e27542aSGleb Smirnoff 29667e27542aSGleb Smirnoff /* Mark the last segment as end of packet... */ 29677e27542aSGleb Smirnoff d->bge_flags |= BGE_TXBDFLAG_END; 29687e27542aSGleb Smirnoff /* ... and put VLAN tag into first segment. */ 29697e27542aSGleb Smirnoff d = &sc->bge_ldata.bge_tx_ring[*txidx]; 29707e27542aSGleb Smirnoff if (mtag != NULL) { 29717e27542aSGleb Smirnoff d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 29727e27542aSGleb Smirnoff d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 29737e27542aSGleb Smirnoff } else 29747e27542aSGleb Smirnoff d->bge_vlan_tag = 0; 2975f41ac2beSBill Paul 2976f41ac2beSBill Paul /* 2977f41ac2beSBill Paul * Insure that the map for this transmission 2978f41ac2beSBill Paul * is placed at the array index of the last descriptor 2979f41ac2beSBill Paul * in this chain. 2980f41ac2beSBill Paul */ 29817e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 29827e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[idx] = map; 29837e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_chain[idx] = m_head; 29847e27542aSGleb Smirnoff sc->bge_txcnt += nsegs; 298595d67482SBill Paul 29867e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 29877e27542aSGleb Smirnoff *txidx = idx; 298895d67482SBill Paul 298995d67482SBill Paul return (0); 299095d67482SBill Paul } 299195d67482SBill Paul 299295d67482SBill Paul /* 299395d67482SBill Paul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 299495d67482SBill Paul * to the mbuf data regions directly in the transmit descriptors. 299595d67482SBill Paul */ 299695d67482SBill Paul static void 29973f74909aSGleb Smirnoff bge_start_locked(struct ifnet *ifp) 299895d67482SBill Paul { 299995d67482SBill Paul struct bge_softc *sc; 300095d67482SBill Paul struct mbuf *m_head = NULL; 300114bbd30fSGleb Smirnoff uint32_t prodidx; 3002303a718cSDag-Erling Smørgrav int count = 0; 300395d67482SBill Paul 300495d67482SBill Paul sc = ifp->if_softc; 300595d67482SBill Paul 3006dab5cd05SOleg Bulyzhin if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 300795d67482SBill Paul return; 300895d67482SBill Paul 300914bbd30fSGleb Smirnoff prodidx = sc->bge_tx_prodidx; 301095d67482SBill Paul 301195d67482SBill Paul while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 30124d665c4dSDag-Erling Smørgrav IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 301395d67482SBill Paul if (m_head == NULL) 301495d67482SBill Paul break; 301595d67482SBill Paul 301695d67482SBill Paul /* 301795d67482SBill Paul * XXX 3018b874fdd4SYaroslav Tykhiy * The code inside the if() block is never reached since we 3019b874fdd4SYaroslav Tykhiy * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3020b874fdd4SYaroslav Tykhiy * requests to checksum TCP/UDP in a fragmented packet. 3021b874fdd4SYaroslav Tykhiy * 3022b874fdd4SYaroslav Tykhiy * XXX 302395d67482SBill Paul * safety overkill. If this is a fragmented packet chain 302495d67482SBill Paul * with delayed TCP/UDP checksums, then only encapsulate 302595d67482SBill Paul * it if we have enough descriptors to handle the entire 302695d67482SBill Paul * chain at once. 302795d67482SBill Paul * (paranoia -- may not actually be needed) 302895d67482SBill Paul */ 302995d67482SBill Paul if (m_head->m_flags & M_FIRSTFRAG && 303095d67482SBill Paul m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 303195d67482SBill Paul if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 303295d67482SBill Paul m_head->m_pkthdr.csum_data + 16) { 30334d665c4dSDag-Erling Smørgrav IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 303413f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 303595d67482SBill Paul break; 303695d67482SBill Paul } 303795d67482SBill Paul } 303895d67482SBill Paul 303995d67482SBill Paul /* 304095d67482SBill Paul * Pack the data into the transmit ring. If we 304195d67482SBill Paul * don't have room, set the OACTIVE flag and wait 304295d67482SBill Paul * for the NIC to drain the ring. 304395d67482SBill Paul */ 304495d67482SBill Paul if (bge_encap(sc, m_head, &prodidx)) { 30454d665c4dSDag-Erling Smørgrav IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 304613f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 304795d67482SBill Paul break; 304895d67482SBill Paul } 3049303a718cSDag-Erling Smørgrav ++count; 305095d67482SBill Paul 305195d67482SBill Paul /* 305295d67482SBill Paul * If there's a BPF listener, bounce a copy of this frame 305395d67482SBill Paul * to him. 305495d67482SBill Paul */ 3055673d9191SSam Leffler BPF_MTAP(ifp, m_head); 305695d67482SBill Paul } 305795d67482SBill Paul 30583f74909aSGleb Smirnoff if (count == 0) 30593f74909aSGleb Smirnoff /* No packets were dequeued. */ 3060303a718cSDag-Erling Smørgrav return; 3061303a718cSDag-Erling Smørgrav 30623f74909aSGleb Smirnoff /* Transmit. */ 306395d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 30643927098fSPaul Saab /* 5700 b2 errata */ 3065e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 30663927098fSPaul Saab CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 306795d67482SBill Paul 306814bbd30fSGleb Smirnoff sc->bge_tx_prodidx = prodidx; 306914bbd30fSGleb Smirnoff 307095d67482SBill Paul /* 307195d67482SBill Paul * Set a timeout in case the chip goes out to lunch. 307295d67482SBill Paul */ 307395d67482SBill Paul ifp->if_timer = 5; 307495d67482SBill Paul } 307595d67482SBill Paul 30760f9bd73bSSam Leffler /* 30770f9bd73bSSam Leffler * Main transmit routine. To avoid having to do mbuf copies, we put pointers 30780f9bd73bSSam Leffler * to the mbuf data regions directly in the transmit descriptors. 30790f9bd73bSSam Leffler */ 308095d67482SBill Paul static void 30813f74909aSGleb Smirnoff bge_start(struct ifnet *ifp) 308295d67482SBill Paul { 30830f9bd73bSSam Leffler struct bge_softc *sc; 30840f9bd73bSSam Leffler 30850f9bd73bSSam Leffler sc = ifp->if_softc; 30860f9bd73bSSam Leffler BGE_LOCK(sc); 30870f9bd73bSSam Leffler bge_start_locked(ifp); 30880f9bd73bSSam Leffler BGE_UNLOCK(sc); 30890f9bd73bSSam Leffler } 30900f9bd73bSSam Leffler 30910f9bd73bSSam Leffler static void 30923f74909aSGleb Smirnoff bge_init_locked(struct bge_softc *sc) 30930f9bd73bSSam Leffler { 309495d67482SBill Paul struct ifnet *ifp; 30953f74909aSGleb Smirnoff uint16_t *m; 309695d67482SBill Paul 30970f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 309895d67482SBill Paul 3099fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 310095d67482SBill Paul 310113f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 310295d67482SBill Paul return; 310395d67482SBill Paul 310495d67482SBill Paul /* Cancel pending I/O and flush buffers. */ 310595d67482SBill Paul bge_stop(sc); 310695d67482SBill Paul bge_reset(sc); 310795d67482SBill Paul bge_chipinit(sc); 310895d67482SBill Paul 310995d67482SBill Paul /* 311095d67482SBill Paul * Init the various state machines, ring 311195d67482SBill Paul * control blocks and firmware. 311295d67482SBill Paul */ 311395d67482SBill Paul if (bge_blockinit(sc)) { 3114fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "initialization failure\n"); 311595d67482SBill Paul return; 311695d67482SBill Paul } 311795d67482SBill Paul 3118fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 311995d67482SBill Paul 312095d67482SBill Paul /* Specify MTU. */ 312195d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3122859c6c7dSBill Paul ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 312395d67482SBill Paul 312495d67482SBill Paul /* Load our MAC address. */ 31253f74909aSGleb Smirnoff m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 312695d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 312795d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 312895d67482SBill Paul 312995d67482SBill Paul /* Enable or disable promiscuous mode as needed. */ 313095d67482SBill Paul if (ifp->if_flags & IFF_PROMISC) { 313195d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 313295d67482SBill Paul } else { 313395d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 313495d67482SBill Paul } 313595d67482SBill Paul 313695d67482SBill Paul /* Program multicast filter. */ 313795d67482SBill Paul bge_setmulti(sc); 313895d67482SBill Paul 313995d67482SBill Paul /* Init RX ring. */ 314095d67482SBill Paul bge_init_rx_ring_std(sc); 314195d67482SBill Paul 31420434d1b8SBill Paul /* 31430434d1b8SBill Paul * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 31440434d1b8SBill Paul * memory to insure that the chip has in fact read the first 31450434d1b8SBill Paul * entry of the ring. 31460434d1b8SBill Paul */ 31470434d1b8SBill Paul if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 31483f74909aSGleb Smirnoff uint32_t v, i; 31490434d1b8SBill Paul for (i = 0; i < 10; i++) { 31500434d1b8SBill Paul DELAY(20); 31510434d1b8SBill Paul v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 31520434d1b8SBill Paul if (v == (MCLBYTES - ETHER_ALIGN)) 31530434d1b8SBill Paul break; 31540434d1b8SBill Paul } 31550434d1b8SBill Paul if (i == 10) 3156fe806fdaSPyun YongHyeon device_printf (sc->bge_dev, 3157fe806fdaSPyun YongHyeon "5705 A0 chip failed to load RX ring\n"); 31580434d1b8SBill Paul } 31590434d1b8SBill Paul 316095d67482SBill Paul /* Init jumbo RX ring. */ 316195d67482SBill Paul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 316295d67482SBill Paul bge_init_rx_ring_jumbo(sc); 316395d67482SBill Paul 31643f74909aSGleb Smirnoff /* Init our RX return ring index. */ 316595d67482SBill Paul sc->bge_rx_saved_considx = 0; 316695d67482SBill Paul 316795d67482SBill Paul /* Init TX ring. */ 316895d67482SBill Paul bge_init_tx_ring(sc); 316995d67482SBill Paul 31703f74909aSGleb Smirnoff /* Turn on transmitter. */ 317195d67482SBill Paul BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 317295d67482SBill Paul 31733f74909aSGleb Smirnoff /* Turn on receiver. */ 317495d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 317595d67482SBill Paul 317695d67482SBill Paul /* Tell firmware we're alive. */ 317795d67482SBill Paul BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 317895d67482SBill Paul 317975719184SGleb Smirnoff #ifdef DEVICE_POLLING 318075719184SGleb Smirnoff /* Disable interrupts if we are polling. */ 318175719184SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 318275719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 318375719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 318475719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 318575719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 318675719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 318775719184SGleb Smirnoff } else 318875719184SGleb Smirnoff #endif 318975719184SGleb Smirnoff 319095d67482SBill Paul /* Enable host interrupts. */ 319175719184SGleb Smirnoff { 319295d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 319395d67482SBill Paul BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 319495d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 319575719184SGleb Smirnoff } 319695d67482SBill Paul 319795d67482SBill Paul bge_ifmedia_upd(ifp); 319895d67482SBill Paul 319913f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 320013f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 320195d67482SBill Paul 32020f9bd73bSSam Leffler callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 32030f9bd73bSSam Leffler } 32040f9bd73bSSam Leffler 32050f9bd73bSSam Leffler static void 32063f74909aSGleb Smirnoff bge_init(void *xsc) 32070f9bd73bSSam Leffler { 32080f9bd73bSSam Leffler struct bge_softc *sc = xsc; 32090f9bd73bSSam Leffler 32100f9bd73bSSam Leffler BGE_LOCK(sc); 32110f9bd73bSSam Leffler bge_init_locked(sc); 32120f9bd73bSSam Leffler BGE_UNLOCK(sc); 321395d67482SBill Paul } 321495d67482SBill Paul 321595d67482SBill Paul /* 321695d67482SBill Paul * Set media options. 321795d67482SBill Paul */ 321895d67482SBill Paul static int 32193f74909aSGleb Smirnoff bge_ifmedia_upd(struct ifnet *ifp) 322095d67482SBill Paul { 322195d67482SBill Paul struct bge_softc *sc; 322295d67482SBill Paul struct mii_data *mii; 322395d67482SBill Paul struct ifmedia *ifm; 322495d67482SBill Paul 322595d67482SBill Paul sc = ifp->if_softc; 322695d67482SBill Paul ifm = &sc->bge_ifmedia; 322795d67482SBill Paul 322895d67482SBill Paul /* If this is a 1000baseX NIC, enable the TBI port. */ 322995d67482SBill Paul if (sc->bge_tbi) { 323095d67482SBill Paul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 323195d67482SBill Paul return (EINVAL); 323295d67482SBill Paul switch(IFM_SUBTYPE(ifm->ifm_media)) { 323395d67482SBill Paul case IFM_AUTO: 3234ff50922bSDoug White /* 3235ff50922bSDoug White * The BCM5704 ASIC appears to have a special 3236ff50922bSDoug White * mechanism for programming the autoneg 3237ff50922bSDoug White * advertisement registers in TBI mode. 3238ff50922bSDoug White */ 3239c4529f41SMichael Reifenberger if (bge_fake_autoneg == 0 && 3240c4529f41SMichael Reifenberger sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3241ff50922bSDoug White uint32_t sgdig; 3242ff50922bSDoug White CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3243ff50922bSDoug White sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3244ff50922bSDoug White sgdig |= BGE_SGDIGCFG_AUTO| 3245ff50922bSDoug White BGE_SGDIGCFG_PAUSE_CAP| 3246ff50922bSDoug White BGE_SGDIGCFG_ASYM_PAUSE; 3247ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3248ff50922bSDoug White sgdig|BGE_SGDIGCFG_SEND); 3249ff50922bSDoug White DELAY(5); 3250ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3251ff50922bSDoug White } 325295d67482SBill Paul break; 325395d67482SBill Paul case IFM_1000_SX: 325495d67482SBill Paul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 325595d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, 325695d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 325795d67482SBill Paul } else { 325895d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, 325995d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 326095d67482SBill Paul } 326195d67482SBill Paul break; 326295d67482SBill Paul default: 326395d67482SBill Paul return (EINVAL); 326495d67482SBill Paul } 326595d67482SBill Paul return (0); 326695d67482SBill Paul } 326795d67482SBill Paul 32681493e883SOleg Bulyzhin sc->bge_link_evt++; 326995d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 327095d67482SBill Paul if (mii->mii_instance) { 327195d67482SBill Paul struct mii_softc *miisc; 327295d67482SBill Paul for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 327395d67482SBill Paul miisc = LIST_NEXT(miisc, mii_list)) 327495d67482SBill Paul mii_phy_reset(miisc); 327595d67482SBill Paul } 327695d67482SBill Paul mii_mediachg(mii); 327795d67482SBill Paul 327895d67482SBill Paul return (0); 327995d67482SBill Paul } 328095d67482SBill Paul 328195d67482SBill Paul /* 328295d67482SBill Paul * Report current media status. 328395d67482SBill Paul */ 328495d67482SBill Paul static void 32853f74909aSGleb Smirnoff bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 328695d67482SBill Paul { 328795d67482SBill Paul struct bge_softc *sc; 328895d67482SBill Paul struct mii_data *mii; 328995d67482SBill Paul 329095d67482SBill Paul sc = ifp->if_softc; 329195d67482SBill Paul 329295d67482SBill Paul if (sc->bge_tbi) { 329395d67482SBill Paul ifmr->ifm_status = IFM_AVALID; 329495d67482SBill Paul ifmr->ifm_active = IFM_ETHER; 329595d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_STS) & 329695d67482SBill Paul BGE_MACSTAT_TBI_PCS_SYNCHED) 329795d67482SBill Paul ifmr->ifm_status |= IFM_ACTIVE; 32984c0da0ffSGleb Smirnoff else { 32994c0da0ffSGleb Smirnoff ifmr->ifm_active |= IFM_NONE; 33004c0da0ffSGleb Smirnoff return; 33014c0da0ffSGleb Smirnoff } 330295d67482SBill Paul ifmr->ifm_active |= IFM_1000_SX; 330395d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 330495d67482SBill Paul ifmr->ifm_active |= IFM_HDX; 330595d67482SBill Paul else 330695d67482SBill Paul ifmr->ifm_active |= IFM_FDX; 330795d67482SBill Paul return; 330895d67482SBill Paul } 330995d67482SBill Paul 331095d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 331195d67482SBill Paul mii_pollstat(mii); 331295d67482SBill Paul ifmr->ifm_active = mii->mii_media_active; 331395d67482SBill Paul ifmr->ifm_status = mii->mii_media_status; 331495d67482SBill Paul } 331595d67482SBill Paul 331695d67482SBill Paul static int 33173f74909aSGleb Smirnoff bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 331895d67482SBill Paul { 331995d67482SBill Paul struct bge_softc *sc = ifp->if_softc; 332095d67482SBill Paul struct ifreq *ifr = (struct ifreq *) data; 332195d67482SBill Paul struct mii_data *mii; 33223f74909aSGleb Smirnoff int mask, error = 0; 332395d67482SBill Paul 332495d67482SBill Paul switch (command) { 332595d67482SBill Paul case SIOCSIFMTU: 33264c0da0ffSGleb Smirnoff if (ifr->ifr_mtu < ETHERMIN || 33274c0da0ffSGleb Smirnoff ((BGE_IS_JUMBO_CAPABLE(sc)) && 33284c0da0ffSGleb Smirnoff ifr->ifr_mtu > BGE_JUMBO_MTU) || 33294c0da0ffSGleb Smirnoff ((!BGE_IS_JUMBO_CAPABLE(sc)) && 33304c0da0ffSGleb Smirnoff ifr->ifr_mtu > ETHERMTU)) 333195d67482SBill Paul error = EINVAL; 33324c0da0ffSGleb Smirnoff else if (ifp->if_mtu != ifr->ifr_mtu) { 333395d67482SBill Paul ifp->if_mtu = ifr->ifr_mtu; 333413f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 333595d67482SBill Paul bge_init(sc); 333695d67482SBill Paul } 333795d67482SBill Paul break; 333895d67482SBill Paul case SIOCSIFFLAGS: 33390f9bd73bSSam Leffler BGE_LOCK(sc); 334095d67482SBill Paul if (ifp->if_flags & IFF_UP) { 334195d67482SBill Paul /* 334295d67482SBill Paul * If only the state of the PROMISC flag changed, 334395d67482SBill Paul * then just use the 'set promisc mode' command 334495d67482SBill Paul * instead of reinitializing the entire NIC. Doing 334595d67482SBill Paul * a full re-init means reloading the firmware and 334695d67482SBill Paul * waiting for it to start up, which may take a 3347d183af7fSRuslan Ermilov * second or two. Similarly for ALLMULTI. 334895d67482SBill Paul */ 334913f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 335095d67482SBill Paul ifp->if_flags & IFF_PROMISC && 335195d67482SBill Paul !(sc->bge_if_flags & IFF_PROMISC)) { 335295d67482SBill Paul BGE_SETBIT(sc, BGE_RX_MODE, 335395d67482SBill Paul BGE_RXMODE_RX_PROMISC); 335413f4c340SRobert Watson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 335595d67482SBill Paul !(ifp->if_flags & IFF_PROMISC) && 335695d67482SBill Paul sc->bge_if_flags & IFF_PROMISC) { 335795d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, 335895d67482SBill Paul BGE_RXMODE_RX_PROMISC); 3359d183af7fSRuslan Ermilov } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3360d183af7fSRuslan Ermilov (ifp->if_flags ^ sc->bge_if_flags) & IFF_ALLMULTI) { 3361d183af7fSRuslan Ermilov bge_setmulti(sc); 336295d67482SBill Paul } else 33630f9bd73bSSam Leffler bge_init_locked(sc); 336495d67482SBill Paul } else { 336513f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 336695d67482SBill Paul bge_stop(sc); 336795d67482SBill Paul } 336895d67482SBill Paul } 336995d67482SBill Paul sc->bge_if_flags = ifp->if_flags; 33700f9bd73bSSam Leffler BGE_UNLOCK(sc); 337195d67482SBill Paul error = 0; 337295d67482SBill Paul break; 337395d67482SBill Paul case SIOCADDMULTI: 337495d67482SBill Paul case SIOCDELMULTI: 337513f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 33760f9bd73bSSam Leffler BGE_LOCK(sc); 337795d67482SBill Paul bge_setmulti(sc); 33780f9bd73bSSam Leffler BGE_UNLOCK(sc); 337995d67482SBill Paul error = 0; 338095d67482SBill Paul } 338195d67482SBill Paul break; 338295d67482SBill Paul case SIOCSIFMEDIA: 338395d67482SBill Paul case SIOCGIFMEDIA: 338495d67482SBill Paul if (sc->bge_tbi) { 338595d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 338695d67482SBill Paul &sc->bge_ifmedia, command); 338795d67482SBill Paul } else { 338895d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 338995d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 339095d67482SBill Paul &mii->mii_media, command); 339195d67482SBill Paul } 339295d67482SBill Paul break; 339395d67482SBill Paul case SIOCSIFCAP: 339495d67482SBill Paul mask = ifr->ifr_reqcap ^ ifp->if_capenable; 339575719184SGleb Smirnoff #ifdef DEVICE_POLLING 339675719184SGleb Smirnoff if (mask & IFCAP_POLLING) { 339775719184SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING) { 339875719184SGleb Smirnoff error = ether_poll_register(bge_poll, ifp); 339975719184SGleb Smirnoff if (error) 340075719184SGleb Smirnoff return (error); 340175719184SGleb Smirnoff BGE_LOCK(sc); 340275719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 340375719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 340475719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 340575719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 340675719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 340775719184SGleb Smirnoff ifp->if_capenable |= IFCAP_POLLING; 340875719184SGleb Smirnoff BGE_UNLOCK(sc); 340975719184SGleb Smirnoff } else { 341075719184SGleb Smirnoff error = ether_poll_deregister(ifp); 341175719184SGleb Smirnoff /* Enable interrupt even in error case */ 341275719184SGleb Smirnoff BGE_LOCK(sc); 341375719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 341475719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 341575719184SGleb Smirnoff BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 341675719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 341775719184SGleb Smirnoff CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 341875719184SGleb Smirnoff ifp->if_capenable &= ~IFCAP_POLLING; 341975719184SGleb Smirnoff BGE_UNLOCK(sc); 342075719184SGleb Smirnoff } 342175719184SGleb Smirnoff } 342275719184SGleb Smirnoff #endif 3423d375e524SGleb Smirnoff if (mask & IFCAP_HWCSUM) { 3424d375e524SGleb Smirnoff ifp->if_capenable ^= IFCAP_HWCSUM; 3425d375e524SGleb Smirnoff if (IFCAP_HWCSUM & ifp->if_capenable && 3426d375e524SGleb Smirnoff IFCAP_HWCSUM & ifp->if_capabilities) 3427b874fdd4SYaroslav Tykhiy ifp->if_hwassist = BGE_CSUM_FEATURES; 342895d67482SBill Paul else 3429b874fdd4SYaroslav Tykhiy ifp->if_hwassist = 0; 3430479b23b7SGleb Smirnoff VLAN_CAPABILITIES(ifp); 343195d67482SBill Paul } 343295d67482SBill Paul break; 343395d67482SBill Paul default: 3434673d9191SSam Leffler error = ether_ioctl(ifp, command, data); 343595d67482SBill Paul break; 343695d67482SBill Paul } 343795d67482SBill Paul 343895d67482SBill Paul return (error); 343995d67482SBill Paul } 344095d67482SBill Paul 344195d67482SBill Paul static void 34423f74909aSGleb Smirnoff bge_watchdog(struct ifnet *ifp) 344395d67482SBill Paul { 344495d67482SBill Paul struct bge_softc *sc; 344595d67482SBill Paul 344695d67482SBill Paul sc = ifp->if_softc; 344795d67482SBill Paul 3448fe806fdaSPyun YongHyeon if_printf(ifp, "watchdog timeout -- resetting\n"); 344995d67482SBill Paul 345013f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 345195d67482SBill Paul bge_init(sc); 345295d67482SBill Paul 345395d67482SBill Paul ifp->if_oerrors++; 345495d67482SBill Paul } 345595d67482SBill Paul 345695d67482SBill Paul /* 345795d67482SBill Paul * Stop the adapter and free any mbufs allocated to the 345895d67482SBill Paul * RX and TX lists. 345995d67482SBill Paul */ 346095d67482SBill Paul static void 34613f74909aSGleb Smirnoff bge_stop(struct bge_softc *sc) 346295d67482SBill Paul { 346395d67482SBill Paul struct ifnet *ifp; 346495d67482SBill Paul struct ifmedia_entry *ifm; 346595d67482SBill Paul struct mii_data *mii = NULL; 346695d67482SBill Paul int mtmp, itmp; 346795d67482SBill Paul 34680f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 34690f9bd73bSSam Leffler 3470fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 347195d67482SBill Paul 347295d67482SBill Paul if (!sc->bge_tbi) 347395d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 347495d67482SBill Paul 34750f9bd73bSSam Leffler callout_stop(&sc->bge_stat_ch); 347695d67482SBill Paul 347795d67482SBill Paul /* 34783f74909aSGleb Smirnoff * Disable all of the receiver blocks. 347995d67482SBill Paul */ 348095d67482SBill Paul BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 348195d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 348295d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 34834c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 348495d67482SBill Paul BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 348595d67482SBill Paul BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 348695d67482SBill Paul BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 348795d67482SBill Paul BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 348895d67482SBill Paul 348995d67482SBill Paul /* 34903f74909aSGleb Smirnoff * Disable all of the transmit blocks. 349195d67482SBill Paul */ 349295d67482SBill Paul BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 349395d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 349495d67482SBill Paul BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 349595d67482SBill Paul BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 349695d67482SBill Paul BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 34974c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 349895d67482SBill Paul BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 349995d67482SBill Paul BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 350095d67482SBill Paul 350195d67482SBill Paul /* 350295d67482SBill Paul * Shut down all of the memory managers and related 350395d67482SBill Paul * state machines. 350495d67482SBill Paul */ 350595d67482SBill Paul BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 350695d67482SBill Paul BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 35074c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) 350895d67482SBill Paul BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 350995d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 351095d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 35114c0da0ffSGleb Smirnoff if (!(BGE_IS_5705_OR_BEYOND(sc))) { 351295d67482SBill Paul BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 351395d67482SBill Paul BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 35140434d1b8SBill Paul } 351595d67482SBill Paul 351695d67482SBill Paul /* Disable host interrupts. */ 351795d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 351895d67482SBill Paul CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 351995d67482SBill Paul 352095d67482SBill Paul /* 352195d67482SBill Paul * Tell firmware we're shutting down. 352295d67482SBill Paul */ 352395d67482SBill Paul BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 352495d67482SBill Paul 352595d67482SBill Paul /* Free the RX lists. */ 352695d67482SBill Paul bge_free_rx_ring_std(sc); 352795d67482SBill Paul 352895d67482SBill Paul /* Free jumbo RX list. */ 35294c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) 353095d67482SBill Paul bge_free_rx_ring_jumbo(sc); 353195d67482SBill Paul 353295d67482SBill Paul /* Free TX buffers. */ 353395d67482SBill Paul bge_free_tx_ring(sc); 353495d67482SBill Paul 353595d67482SBill Paul /* 353695d67482SBill Paul * Isolate/power down the PHY, but leave the media selection 353795d67482SBill Paul * unchanged so that things will be put back to normal when 353895d67482SBill Paul * we bring the interface back up. 353995d67482SBill Paul */ 354095d67482SBill Paul if (!sc->bge_tbi) { 354195d67482SBill Paul itmp = ifp->if_flags; 354295d67482SBill Paul ifp->if_flags |= IFF_UP; 3543dcc34049SPawel Jakub Dawidek /* 3544dcc34049SPawel Jakub Dawidek * If we are called from bge_detach(), mii is already NULL. 3545dcc34049SPawel Jakub Dawidek */ 3546dcc34049SPawel Jakub Dawidek if (mii != NULL) { 354795d67482SBill Paul ifm = mii->mii_media.ifm_cur; 354895d67482SBill Paul mtmp = ifm->ifm_media; 354995d67482SBill Paul ifm->ifm_media = IFM_ETHER|IFM_NONE; 355095d67482SBill Paul mii_mediachg(mii); 355195d67482SBill Paul ifm->ifm_media = mtmp; 3552dcc34049SPawel Jakub Dawidek } 355395d67482SBill Paul ifp->if_flags = itmp; 355495d67482SBill Paul } 355595d67482SBill Paul 355695d67482SBill Paul sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 355795d67482SBill Paul 35581493e883SOleg Bulyzhin /* 35591493e883SOleg Bulyzhin * We can't just call bge_link_upd() cause chip is almost stopped so 35601493e883SOleg Bulyzhin * bge_link_upd -> bge_tick_locked -> bge_stats_update sequence may 35611493e883SOleg Bulyzhin * lead to hardware deadlock. So we just clearing MAC's link state 35621493e883SOleg Bulyzhin * (PHY may still have link UP). 35631493e883SOleg Bulyzhin */ 35641493e883SOleg Bulyzhin if (bootverbose && sc->bge_link) 35651493e883SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 35661493e883SOleg Bulyzhin sc->bge_link = 0; 356795d67482SBill Paul 35681493e883SOleg Bulyzhin ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 356995d67482SBill Paul } 357095d67482SBill Paul 357195d67482SBill Paul /* 357295d67482SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 357395d67482SBill Paul * get confused by errant DMAs when rebooting. 357495d67482SBill Paul */ 357595d67482SBill Paul static void 35763f74909aSGleb Smirnoff bge_shutdown(device_t dev) 357795d67482SBill Paul { 357895d67482SBill Paul struct bge_softc *sc; 357995d67482SBill Paul 358095d67482SBill Paul sc = device_get_softc(dev); 358195d67482SBill Paul 35820f9bd73bSSam Leffler BGE_LOCK(sc); 358395d67482SBill Paul bge_stop(sc); 358495d67482SBill Paul bge_reset(sc); 35850f9bd73bSSam Leffler BGE_UNLOCK(sc); 358695d67482SBill Paul } 358714afefa3SPawel Jakub Dawidek 358814afefa3SPawel Jakub Dawidek static int 358914afefa3SPawel Jakub Dawidek bge_suspend(device_t dev) 359014afefa3SPawel Jakub Dawidek { 359114afefa3SPawel Jakub Dawidek struct bge_softc *sc; 359214afefa3SPawel Jakub Dawidek 359314afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 359414afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 359514afefa3SPawel Jakub Dawidek bge_stop(sc); 359614afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 359714afefa3SPawel Jakub Dawidek 359814afefa3SPawel Jakub Dawidek return (0); 359914afefa3SPawel Jakub Dawidek } 360014afefa3SPawel Jakub Dawidek 360114afefa3SPawel Jakub Dawidek static int 360214afefa3SPawel Jakub Dawidek bge_resume(device_t dev) 360314afefa3SPawel Jakub Dawidek { 360414afefa3SPawel Jakub Dawidek struct bge_softc *sc; 360514afefa3SPawel Jakub Dawidek struct ifnet *ifp; 360614afefa3SPawel Jakub Dawidek 360714afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 360814afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 360914afefa3SPawel Jakub Dawidek ifp = sc->bge_ifp; 361014afefa3SPawel Jakub Dawidek if (ifp->if_flags & IFF_UP) { 361114afefa3SPawel Jakub Dawidek bge_init_locked(sc); 361214afefa3SPawel Jakub Dawidek if (ifp->if_drv_flags & IFF_DRV_RUNNING) 361314afefa3SPawel Jakub Dawidek bge_start_locked(ifp); 361414afefa3SPawel Jakub Dawidek } 361514afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 361614afefa3SPawel Jakub Dawidek 361714afefa3SPawel Jakub Dawidek return (0); 361814afefa3SPawel Jakub Dawidek } 3619dab5cd05SOleg Bulyzhin 3620dab5cd05SOleg Bulyzhin static void 36213f74909aSGleb Smirnoff bge_link_upd(struct bge_softc *sc) 3622dab5cd05SOleg Bulyzhin { 36231f313773SOleg Bulyzhin struct mii_data *mii; 36241f313773SOleg Bulyzhin uint32_t link, status; 3625dab5cd05SOleg Bulyzhin 3626dab5cd05SOleg Bulyzhin BGE_LOCK_ASSERT(sc); 36271f313773SOleg Bulyzhin 36283f74909aSGleb Smirnoff /* Clear 'pending link event' flag. */ 36297b97099dSOleg Bulyzhin sc->bge_link_evt = 0; 36307b97099dSOleg Bulyzhin 3631dab5cd05SOleg Bulyzhin /* 3632dab5cd05SOleg Bulyzhin * Process link state changes. 3633dab5cd05SOleg Bulyzhin * Grrr. The link status word in the status block does 3634dab5cd05SOleg Bulyzhin * not work correctly on the BCM5700 rev AX and BX chips, 3635dab5cd05SOleg Bulyzhin * according to all available information. Hence, we have 3636dab5cd05SOleg Bulyzhin * to enable MII interrupts in order to properly obtain 3637dab5cd05SOleg Bulyzhin * async link changes. Unfortunately, this also means that 3638dab5cd05SOleg Bulyzhin * we have to read the MAC status register to detect link 3639dab5cd05SOleg Bulyzhin * changes, thereby adding an additional register access to 3640dab5cd05SOleg Bulyzhin * the interrupt handler. 36411f313773SOleg Bulyzhin * 36421f313773SOleg Bulyzhin * XXX: perhaps link state detection procedure used for 36434c0da0ffSGleb Smirnoff * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 3644dab5cd05SOleg Bulyzhin */ 3645dab5cd05SOleg Bulyzhin 36461f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 36474c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 3648dab5cd05SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 3649dab5cd05SOleg Bulyzhin if (status & BGE_MACSTAT_MI_INTERRUPT) { 3650dab5cd05SOleg Bulyzhin callout_stop(&sc->bge_stat_ch); 3651dab5cd05SOleg Bulyzhin bge_tick_locked(sc); 36521f313773SOleg Bulyzhin 36531f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 36541f313773SOleg Bulyzhin if (!sc->bge_link && 36551f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 36561f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 36571f313773SOleg Bulyzhin sc->bge_link++; 36581f313773SOleg Bulyzhin if (bootverbose) 36591f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 36601f313773SOleg Bulyzhin } else if (sc->bge_link && 36611f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 36621f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 36631f313773SOleg Bulyzhin sc->bge_link = 0; 36641f313773SOleg Bulyzhin if (bootverbose) 36651f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 36661f313773SOleg Bulyzhin } 36671f313773SOleg Bulyzhin 36683f74909aSGleb Smirnoff /* Clear the interrupt. */ 3669dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3670dab5cd05SOleg Bulyzhin BGE_EVTENB_MI_INTERRUPT); 3671dab5cd05SOleg Bulyzhin bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 3672dab5cd05SOleg Bulyzhin bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 3673dab5cd05SOleg Bulyzhin BRGPHY_INTRS); 3674dab5cd05SOleg Bulyzhin } 3675dab5cd05SOleg Bulyzhin return; 3676dab5cd05SOleg Bulyzhin } 3677dab5cd05SOleg Bulyzhin 36781f313773SOleg Bulyzhin if (sc->bge_tbi) { 36791f313773SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 36807b97099dSOleg Bulyzhin if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 36817b97099dSOleg Bulyzhin if (!sc->bge_link) { 36821f313773SOleg Bulyzhin sc->bge_link++; 36831f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 36841f313773SOleg Bulyzhin BGE_CLRBIT(sc, BGE_MAC_MODE, 36851f313773SOleg Bulyzhin BGE_MACMODE_TBI_SEND_CFGS); 36861f313773SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 36871f313773SOleg Bulyzhin if (bootverbose) 36881f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 36893f74909aSGleb Smirnoff if_link_state_change(sc->bge_ifp, 36903f74909aSGleb Smirnoff LINK_STATE_UP); 36917b97099dSOleg Bulyzhin } 36921f313773SOleg Bulyzhin } else if (sc->bge_link) { 3693dab5cd05SOleg Bulyzhin sc->bge_link = 0; 36941f313773SOleg Bulyzhin if (bootverbose) 36951f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 36967b97099dSOleg Bulyzhin if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 36971f313773SOleg Bulyzhin } 36981493e883SOleg Bulyzhin /* Discard link events for MII/GMII cards if MI auto-polling disabled */ 36991493e883SOleg Bulyzhin } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 37001f313773SOleg Bulyzhin /* 37011f313773SOleg Bulyzhin * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 37021f313773SOleg Bulyzhin * in status word always set. Workaround this bug by reading 37031f313773SOleg Bulyzhin * PHY link status directly. 37041f313773SOleg Bulyzhin */ 37051f313773SOleg Bulyzhin link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 37061f313773SOleg Bulyzhin 37071f313773SOleg Bulyzhin if (link != sc->bge_link || 37081f313773SOleg Bulyzhin sc->bge_asicrev == BGE_ASICREV_BCM5700) { 3709dab5cd05SOleg Bulyzhin callout_stop(&sc->bge_stat_ch); 3710dab5cd05SOleg Bulyzhin bge_tick_locked(sc); 37111f313773SOleg Bulyzhin 37121f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 37131f313773SOleg Bulyzhin if (!sc->bge_link && 37141f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 37151f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 37161f313773SOleg Bulyzhin sc->bge_link++; 37171f313773SOleg Bulyzhin if (bootverbose) 37181f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 37191f313773SOleg Bulyzhin } else if (sc->bge_link && 37201f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 37211f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 37221f313773SOleg Bulyzhin sc->bge_link = 0; 37231f313773SOleg Bulyzhin if (bootverbose) 37241f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 37251f313773SOleg Bulyzhin } 37261f313773SOleg Bulyzhin } 3727dab5cd05SOleg Bulyzhin } 3728dab5cd05SOleg Bulyzhin 37293f74909aSGleb Smirnoff /* Clear the attention. */ 3730dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3731dab5cd05SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3732dab5cd05SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 3733dab5cd05SOleg Bulyzhin } 3734