1098ca2bdSWarner Losh /*- 295d67482SBill Paul * Copyright (c) 2001 Wind River Systems 395d67482SBill Paul * Copyright (c) 1997, 1998, 1999, 2001 495d67482SBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 595d67482SBill Paul * 695d67482SBill Paul * Redistribution and use in source and binary forms, with or without 795d67482SBill Paul * modification, are permitted provided that the following conditions 895d67482SBill Paul * are met: 995d67482SBill Paul * 1. Redistributions of source code must retain the above copyright 1095d67482SBill Paul * notice, this list of conditions and the following disclaimer. 1195d67482SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1295d67482SBill Paul * notice, this list of conditions and the following disclaimer in the 1395d67482SBill Paul * documentation and/or other materials provided with the distribution. 1495d67482SBill Paul * 3. All advertising materials mentioning features or use of this software 1595d67482SBill Paul * must display the following acknowledgement: 1695d67482SBill Paul * This product includes software developed by Bill Paul. 1795d67482SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1895d67482SBill Paul * may be used to endorse or promote products derived from this software 1995d67482SBill Paul * without specific prior written permission. 2095d67482SBill Paul * 2195d67482SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2295d67482SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2395d67482SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2495d67482SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2595d67482SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2695d67482SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2795d67482SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2895d67482SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2995d67482SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3095d67482SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3195d67482SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3295d67482SBill Paul */ 3395d67482SBill Paul 34aad970f1SDavid E. O'Brien #include <sys/cdefs.h> 35aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$"); 36aad970f1SDavid E. O'Brien 3795d67482SBill Paul /* 38d7acafa1SMarius Strobl * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 3995d67482SBill Paul * 4095d67482SBill Paul * The Broadcom BCM5700 is based on technology originally developed by 41d7acafa1SMarius Strobl * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 4222a4ecedSMarius Strobl * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 4395d67482SBill Paul * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 4495d67482SBill Paul * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 4595d67482SBill Paul * frames, highly configurable RX filtering, and 16 RX and TX queues 4695d67482SBill Paul * (which, along with RX filter rules, can be used for QOS applications). 4795d67482SBill Paul * Other features, such as TCP segmentation, may be available as part 4895d67482SBill Paul * of value-added firmware updates. Unlike the Tigon I and Tigon II, 4995d67482SBill Paul * firmware images can be stored in hardware and need not be compiled 5095d67482SBill Paul * into the driver. 5195d67482SBill Paul * 5295d67482SBill Paul * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 5395d67482SBill Paul * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 5495d67482SBill Paul * 5595d67482SBill Paul * The BCM5701 is a single-chip solution incorporating both the BCM5700 5698b28ee5SBill Paul * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 5795d67482SBill Paul * does not support external SSRAM. 5895d67482SBill Paul * 5995d67482SBill Paul * Broadcom also produces a variation of the BCM5700 under the "Altima" 6095d67482SBill Paul * brand name, which is functionally similar but lacks PCI-X support. 6195d67482SBill Paul * 6295d67482SBill Paul * Without external SSRAM, you can only have at most 4 TX rings, 6395d67482SBill Paul * and the use of the mini RX ring is disabled. This seems to imply 6495d67482SBill Paul * that these features are simply not available on the BCM5701. As a 6595d67482SBill Paul * result, this driver does not implement any support for the mini RX 6695d67482SBill Paul * ring. 6795d67482SBill Paul */ 6895d67482SBill Paul 6975719184SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 7075719184SGleb Smirnoff #include "opt_device_polling.h" 7175719184SGleb Smirnoff #endif 7275719184SGleb Smirnoff 7395d67482SBill Paul #include <sys/param.h> 74f41ac2beSBill Paul #include <sys/endian.h> 7595d67482SBill Paul #include <sys/systm.h> 7695d67482SBill Paul #include <sys/sockio.h> 7795d67482SBill Paul #include <sys/mbuf.h> 7895d67482SBill Paul #include <sys/malloc.h> 7995d67482SBill Paul #include <sys/kernel.h> 80fe12f24bSPoul-Henning Kamp #include <sys/module.h> 8195d67482SBill Paul #include <sys/socket.h> 82f1a7e6d5SScott Long #include <sys/sysctl.h> 83dfe0df9aSPyun YongHyeon #include <sys/taskqueue.h> 8495d67482SBill Paul 8595d67482SBill Paul #include <net/if.h> 8676039bc8SGleb Smirnoff #include <net/if_var.h> 8795d67482SBill Paul #include <net/if_arp.h> 8895d67482SBill Paul #include <net/ethernet.h> 8995d67482SBill Paul #include <net/if_dl.h> 9095d67482SBill Paul #include <net/if_media.h> 9195d67482SBill Paul 9295d67482SBill Paul #include <net/bpf.h> 9395d67482SBill Paul 9495d67482SBill Paul #include <net/if_types.h> 9595d67482SBill Paul #include <net/if_vlan_var.h> 9695d67482SBill Paul 9795d67482SBill Paul #include <netinet/in_systm.h> 9895d67482SBill Paul #include <netinet/in.h> 9995d67482SBill Paul #include <netinet/ip.h> 100ca3f1187SPyun YongHyeon #include <netinet/tcp.h> 10195d67482SBill Paul 10295d67482SBill Paul #include <machine/bus.h> 10395d67482SBill Paul #include <machine/resource.h> 10495d67482SBill Paul #include <sys/bus.h> 10595d67482SBill Paul #include <sys/rman.h> 10695d67482SBill Paul 10795d67482SBill Paul #include <dev/mii/mii.h> 10895d67482SBill Paul #include <dev/mii/miivar.h> 1092d3ce713SDavid E. O'Brien #include "miidevs.h" 11095d67482SBill Paul #include <dev/mii/brgphyreg.h> 11195d67482SBill Paul 11208013fd3SMarius Strobl #ifdef __sparc64__ 11308013fd3SMarius Strobl #include <dev/ofw/ofw_bus.h> 11408013fd3SMarius Strobl #include <dev/ofw/openfirm.h> 11508013fd3SMarius Strobl #include <machine/ofw_machdep.h> 11608013fd3SMarius Strobl #include <machine/ver.h> 11708013fd3SMarius Strobl #endif 11808013fd3SMarius Strobl 1194fbd232cSWarner Losh #include <dev/pci/pcireg.h> 1204fbd232cSWarner Losh #include <dev/pci/pcivar.h> 12195d67482SBill Paul 12295d67482SBill Paul #include <dev/bge/if_bgereg.h> 12395d67482SBill Paul 12435f945cdSPyun YongHyeon #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 125d375e524SGleb Smirnoff #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 12695d67482SBill Paul 127f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, pci, 1, 1, 1); 128f246e4a1SMatthew N. Dodd MODULE_DEPEND(bge, ether, 1, 1, 1); 12995d67482SBill Paul MODULE_DEPEND(bge, miibus, 1, 1, 1); 13095d67482SBill Paul 1317b279558SWarner Losh /* "device miibus" required. See GENERIC if you get errors here. */ 13295d67482SBill Paul #include "miibus_if.h" 13395d67482SBill Paul 13495d67482SBill Paul /* 13595d67482SBill Paul * Various supported device vendors/types and their names. Note: the 13695d67482SBill Paul * spec seems to indicate that the hardware still has Alteon's vendor 13795d67482SBill Paul * ID burned into it, though it will always be overriden by the vendor 13895d67482SBill Paul * ID in the EEPROM. Just to be safe, we cover all possibilities. 13995d67482SBill Paul */ 140852c67f9SMarius Strobl static const struct bge_type { 1414c0da0ffSGleb Smirnoff uint16_t bge_vid; 1424c0da0ffSGleb Smirnoff uint16_t bge_did; 14329658c96SDimitry Andric } bge_devs[] = { 1444c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 1454c0da0ffSGleb Smirnoff { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 14695d67482SBill Paul 1474c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 1484c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 1494c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 1504c0da0ffSGleb Smirnoff 1514c0da0ffSGleb Smirnoff { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 1524c0da0ffSGleb Smirnoff 1534c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 1544c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 1554c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 1564c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 1574c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 1584c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 1594c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 1604c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 1614c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 1624c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 1634c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 1644c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 1654c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 1664c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 1674c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 1684c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 1694c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 1704c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 1714c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 1724c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 1731108273aSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 1741108273aSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 175bbe2ca75SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 1764c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 1774c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 178effef978SRemko Lodder { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 179a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 1802927f01fSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 1812927f01fSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 1824c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 1834c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 1844c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 1854c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 1864c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 1874c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 1884c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 1894c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 1904c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 1914c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 1929e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 1939e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 1949e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 1959e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 196f7d1b2ebSXin LI { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 197a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 198a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 199a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 200a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 2012927f01fSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 202a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 2034c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 2044c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 2054c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 2064c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 207a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 208a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 209a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 2109e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 2119e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 212a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 2139e86676bSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 2144c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 2154c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 2164c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 2174c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 2184c0da0ffSGleb Smirnoff { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 21938cc658fSJohn Baldwin { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 22038cc658fSJohn Baldwin { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 221a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 222b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 223fe26ad88SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 22467129934SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 225b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 226fe26ad88SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 22767129934SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 228a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 229b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 23067129934SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 231b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 23267129934SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 23367129934SPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 234a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 235a5779553SStanislav Sedov { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 236b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 237b4a256acSPyun YongHyeon { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 2384c0da0ffSGleb Smirnoff 2394c0da0ffSGleb Smirnoff { SK_VENDORID, SK_DEVICEID_ALTIMA }, 2404c0da0ffSGleb Smirnoff 2414c0da0ffSGleb Smirnoff { TC_VENDORID, TC_DEVICEID_3C996 }, 2424c0da0ffSGleb Smirnoff 243a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 244a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 245a5779553SStanislav Sedov { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 246a5779553SStanislav Sedov 2474c0da0ffSGleb Smirnoff { 0, 0 } 24895d67482SBill Paul }; 24995d67482SBill Paul 2504c0da0ffSGleb Smirnoff static const struct bge_vendor { 2514c0da0ffSGleb Smirnoff uint16_t v_id; 2524c0da0ffSGleb Smirnoff const char *v_name; 25329658c96SDimitry Andric } bge_vendors[] = { 2544c0da0ffSGleb Smirnoff { ALTEON_VENDORID, "Alteon" }, 2554c0da0ffSGleb Smirnoff { ALTIMA_VENDORID, "Altima" }, 2564c0da0ffSGleb Smirnoff { APPLE_VENDORID, "Apple" }, 2574c0da0ffSGleb Smirnoff { BCOM_VENDORID, "Broadcom" }, 2584c0da0ffSGleb Smirnoff { SK_VENDORID, "SysKonnect" }, 2594c0da0ffSGleb Smirnoff { TC_VENDORID, "3Com" }, 260a5779553SStanislav Sedov { FJTSU_VENDORID, "Fujitsu" }, 2614c0da0ffSGleb Smirnoff 2624c0da0ffSGleb Smirnoff { 0, NULL } 2634c0da0ffSGleb Smirnoff }; 2644c0da0ffSGleb Smirnoff 2654c0da0ffSGleb Smirnoff static const struct bge_revision { 2664c0da0ffSGleb Smirnoff uint32_t br_chipid; 2674c0da0ffSGleb Smirnoff const char *br_name; 26829658c96SDimitry Andric } bge_revisions[] = { 2694c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 2704c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 2714c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 2724c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 2734c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 2744c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 2754c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 2764c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 2774c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 2784c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 2794c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 2804c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 2814c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 2824c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 2834c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 2844c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 2859e86676bSGleb Smirnoff { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 2864c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 2874c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 2884c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 2894c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 2904c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 2914c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 2924c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 2934c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 2944c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 2954c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 2964c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 2974c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 2984c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 2994c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 3004c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 3014c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 30242787b76SGleb Smirnoff { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 3034c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 3044c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 3054c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 3064c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 3074c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 3084c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 3094c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 3104c0da0ffSGleb Smirnoff { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 3110c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 3121108273aSPyun YongHyeon { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 3131108273aSPyun YongHyeon { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 314bbe2ca75SPyun YongHyeon { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 31550515680SPyun YongHyeon { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 3160c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 3170c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 3180c4a1ef8SJung-uk Kim { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 319bcc20328SJohn Baldwin { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 320a5779553SStanislav Sedov { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 321a5779553SStanislav Sedov { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 3222927f01fSPyun YongHyeon { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 323a5779553SStanislav Sedov { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 324a5779553SStanislav Sedov { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 32581179070SJung-uk Kim /* 5754 and 5787 share the same ASIC ID */ 3266f8718a3SScott Long { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 3276f8718a3SScott Long { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 3286f8718a3SScott Long { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 32938cc658fSJohn Baldwin { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 33038cc658fSJohn Baldwin { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 331b4a256acSPyun YongHyeon { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 332b4a256acSPyun YongHyeon { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 333a5779553SStanislav Sedov { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 334a5779553SStanislav Sedov { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 3354c0da0ffSGleb Smirnoff 3364c0da0ffSGleb Smirnoff { 0, NULL } 3374c0da0ffSGleb Smirnoff }; 3384c0da0ffSGleb Smirnoff 3394c0da0ffSGleb Smirnoff /* 3404c0da0ffSGleb Smirnoff * Some defaults for major revisions, so that newer steppings 3414c0da0ffSGleb Smirnoff * that we don't know about have a shot at working. 3424c0da0ffSGleb Smirnoff */ 34329658c96SDimitry Andric static const struct bge_revision bge_majorrevs[] = { 3449e86676bSGleb Smirnoff { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 3459e86676bSGleb Smirnoff { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 3469e86676bSGleb Smirnoff { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 3479e86676bSGleb Smirnoff { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 3489e86676bSGleb Smirnoff { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 3499e86676bSGleb Smirnoff { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 3509e86676bSGleb Smirnoff { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 3519e86676bSGleb Smirnoff { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 3529e86676bSGleb Smirnoff { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 3539e86676bSGleb Smirnoff { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 3549e86676bSGleb Smirnoff { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 355a5779553SStanislav Sedov { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 356a5779553SStanislav Sedov { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 357a5779553SStanislav Sedov { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 35881179070SJung-uk Kim /* 5754 and 5787 share the same ASIC ID */ 3596f8718a3SScott Long { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 36038cc658fSJohn Baldwin { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 361b4a256acSPyun YongHyeon { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 362fe26ad88SPyun YongHyeon { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 363a5779553SStanislav Sedov { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 3641108273aSPyun YongHyeon { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 365bbe2ca75SPyun YongHyeon { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 36650515680SPyun YongHyeon { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 3672927f01fSPyun YongHyeon { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 3684c0da0ffSGleb Smirnoff 3694c0da0ffSGleb Smirnoff { 0, NULL } 3704c0da0ffSGleb Smirnoff }; 3714c0da0ffSGleb Smirnoff 3720c8aa4eaSJung-uk Kim #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 3730c8aa4eaSJung-uk Kim #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 3740c8aa4eaSJung-uk Kim #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 3750c8aa4eaSJung-uk Kim #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 3760c8aa4eaSJung-uk Kim #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 377a5779553SStanislav Sedov #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 3781108273aSPyun YongHyeon #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 379fe26ad88SPyun YongHyeon #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 3804c0da0ffSGleb Smirnoff 381d7acafa1SMarius Strobl static uint32_t bge_chipid(device_t); 382d7acafa1SMarius Strobl static const struct bge_vendor * bge_lookup_vendor(uint16_t); 383d7acafa1SMarius Strobl static const struct bge_revision * bge_lookup_rev(uint32_t); 38438cc658fSJohn Baldwin 38538cc658fSJohn Baldwin typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 38638cc658fSJohn Baldwin 387e51a25f8SAlfred Perlstein static int bge_probe(device_t); 388e51a25f8SAlfred Perlstein static int bge_attach(device_t); 389e51a25f8SAlfred Perlstein static int bge_detach(device_t); 39014afefa3SPawel Jakub Dawidek static int bge_suspend(device_t); 39114afefa3SPawel Jakub Dawidek static int bge_resume(device_t); 3923f74909aSGleb Smirnoff static void bge_release_resources(struct bge_softc *); 393f41ac2beSBill Paul static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 3945b610048SPyun YongHyeon static int bge_dma_alloc(struct bge_softc *); 395f41ac2beSBill Paul static void bge_dma_free(struct bge_softc *); 3965b610048SPyun YongHyeon static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 3975b610048SPyun YongHyeon bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 398f41ac2beSBill Paul 399ea9c3a30SPyun YongHyeon static void bge_devinfo(struct bge_softc *); 400062af0b0SPyun YongHyeon static int bge_mbox_reorder(struct bge_softc *); 401062af0b0SPyun YongHyeon 4025fea260fSMarius Strobl static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 40338cc658fSJohn Baldwin static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 40438cc658fSJohn Baldwin static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 40538cc658fSJohn Baldwin static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 40638cc658fSJohn Baldwin static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 40738cc658fSJohn Baldwin 408b9c05fa5SPyun YongHyeon static void bge_txeof(struct bge_softc *, uint16_t); 4091108273aSPyun YongHyeon static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 410dfe0df9aSPyun YongHyeon static int bge_rxeof(struct bge_softc *, uint16_t, int); 41195d67482SBill Paul 4128cb1383cSDoug Ambrisko static void bge_asf_driver_up (struct bge_softc *); 413e51a25f8SAlfred Perlstein static void bge_tick(void *); 4142280c16bSPyun YongHyeon static void bge_stats_clear_regs(struct bge_softc *); 415e51a25f8SAlfred Perlstein static void bge_stats_update(struct bge_softc *); 4163f74909aSGleb Smirnoff static void bge_stats_update_regs(struct bge_softc *); 417d598b626SPyun YongHyeon static struct mbuf *bge_check_short_dma(struct mbuf *); 4182e1d4df4SPyun YongHyeon static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 4191108273aSPyun YongHyeon uint16_t *, uint16_t *); 420676ad2c9SGleb Smirnoff static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 42195d67482SBill Paul 422e51a25f8SAlfred Perlstein static void bge_intr(void *); 423dfe0df9aSPyun YongHyeon static int bge_msi_intr(void *); 424dfe0df9aSPyun YongHyeon static void bge_intr_task(void *, int); 425fba8b109SMarcel Moolenaar static void bge_start_locked(if_t); 426fba8b109SMarcel Moolenaar static void bge_start(if_t); 427fba8b109SMarcel Moolenaar static int bge_ioctl(if_t, u_long, caddr_t); 4280f9bd73bSSam Leffler static void bge_init_locked(struct bge_softc *); 429e51a25f8SAlfred Perlstein static void bge_init(void *); 4305a147ba6SPyun YongHyeon static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 431e51a25f8SAlfred Perlstein static void bge_stop(struct bge_softc *); 432b74e67fbSGleb Smirnoff static void bge_watchdog(struct bge_softc *); 433b6c974e8SWarner Losh static int bge_shutdown(device_t); 434fba8b109SMarcel Moolenaar static int bge_ifmedia_upd_locked(if_t); 435fba8b109SMarcel Moolenaar static int bge_ifmedia_upd(if_t); 436fba8b109SMarcel Moolenaar static void bge_ifmedia_sts(if_t, struct ifmediareq *); 43795d67482SBill Paul 43838cc658fSJohn Baldwin static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 43938cc658fSJohn Baldwin static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 44038cc658fSJohn Baldwin 4413f74909aSGleb Smirnoff static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 442e51a25f8SAlfred Perlstein static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 44395d67482SBill Paul 4443e9b1bcaSJung-uk Kim static void bge_setpromisc(struct bge_softc *); 445e51a25f8SAlfred Perlstein static void bge_setmulti(struct bge_softc *); 446cb2eacc7SYaroslav Tykhiy static void bge_setvlan(struct bge_softc *); 44795d67482SBill Paul 448e0b7b101SPyun YongHyeon static __inline void bge_rxreuse_std(struct bge_softc *, int); 449e0b7b101SPyun YongHyeon static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 450943787f3SPyun YongHyeon static int bge_newbuf_std(struct bge_softc *, int); 451943787f3SPyun YongHyeon static int bge_newbuf_jumbo(struct bge_softc *, int); 452e51a25f8SAlfred Perlstein static int bge_init_rx_ring_std(struct bge_softc *); 453e51a25f8SAlfred Perlstein static void bge_free_rx_ring_std(struct bge_softc *); 454e51a25f8SAlfred Perlstein static int bge_init_rx_ring_jumbo(struct bge_softc *); 455e51a25f8SAlfred Perlstein static void bge_free_rx_ring_jumbo(struct bge_softc *); 456e51a25f8SAlfred Perlstein static void bge_free_tx_ring(struct bge_softc *); 457e51a25f8SAlfred Perlstein static int bge_init_tx_ring(struct bge_softc *); 45895d67482SBill Paul 459e51a25f8SAlfred Perlstein static int bge_chipinit(struct bge_softc *); 460e51a25f8SAlfred Perlstein static int bge_blockinit(struct bge_softc *); 46150515680SPyun YongHyeon static uint32_t bge_dma_swap_options(struct bge_softc *); 46295d67482SBill Paul 4635fea260fSMarius Strobl static int bge_has_eaddr(struct bge_softc *); 4643f74909aSGleb Smirnoff static uint32_t bge_readmem_ind(struct bge_softc *, int); 465e51a25f8SAlfred Perlstein static void bge_writemem_ind(struct bge_softc *, int, int); 46638cc658fSJohn Baldwin static void bge_writembx(struct bge_softc *, int, int); 46795d67482SBill Paul #ifdef notdef 4683f74909aSGleb Smirnoff static uint32_t bge_readreg_ind(struct bge_softc *, int); 46995d67482SBill Paul #endif 4709ba784dbSScott Long static void bge_writemem_direct(struct bge_softc *, int, int); 471e51a25f8SAlfred Perlstein static void bge_writereg_ind(struct bge_softc *, int, int); 47295d67482SBill Paul 473e51a25f8SAlfred Perlstein static int bge_miibus_readreg(device_t, int, int); 474e51a25f8SAlfred Perlstein static int bge_miibus_writereg(device_t, int, int, int); 475e51a25f8SAlfred Perlstein static void bge_miibus_statchg(device_t); 47675719184SGleb Smirnoff #ifdef DEVICE_POLLING 477fba8b109SMarcel Moolenaar static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 47875719184SGleb Smirnoff #endif 47995d67482SBill Paul 480548c8f1aSPyun YongHyeon #define BGE_RESET_SHUTDOWN 0 4818cb1383cSDoug Ambrisko #define BGE_RESET_START 1 482548c8f1aSPyun YongHyeon #define BGE_RESET_SUSPEND 2 4838cb1383cSDoug Ambrisko static void bge_sig_post_reset(struct bge_softc *, int); 4848cb1383cSDoug Ambrisko static void bge_sig_legacy(struct bge_softc *, int); 4858cb1383cSDoug Ambrisko static void bge_sig_pre_reset(struct bge_softc *, int); 486797ab05eSPyun YongHyeon static void bge_stop_fw(struct bge_softc *); 4878cb1383cSDoug Ambrisko static int bge_reset(struct bge_softc *); 488dab5cd05SOleg Bulyzhin static void bge_link_upd(struct bge_softc *); 48995d67482SBill Paul 490548c8f1aSPyun YongHyeon static void bge_ape_lock_init(struct bge_softc *); 491548c8f1aSPyun YongHyeon static void bge_ape_read_fw_ver(struct bge_softc *); 492548c8f1aSPyun YongHyeon static int bge_ape_lock(struct bge_softc *, int); 493548c8f1aSPyun YongHyeon static void bge_ape_unlock(struct bge_softc *, int); 494548c8f1aSPyun YongHyeon static void bge_ape_send_event(struct bge_softc *, uint32_t); 495548c8f1aSPyun YongHyeon static void bge_ape_driver_state_change(struct bge_softc *, int); 496548c8f1aSPyun YongHyeon 4976f8718a3SScott Long /* 4986f8718a3SScott Long * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 4996f8718a3SScott Long * leak information to untrusted users. It is also known to cause alignment 5006f8718a3SScott Long * traps on certain architectures. 5016f8718a3SScott Long */ 5026f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 5036f8718a3SScott Long static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 5046f8718a3SScott Long static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 505548c8f1aSPyun YongHyeon static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 5066f8718a3SScott Long static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 5076f8718a3SScott Long #endif 5086f8718a3SScott Long static void bge_add_sysctls(struct bge_softc *); 5092280c16bSPyun YongHyeon static void bge_add_sysctl_stats_regs(struct bge_softc *, 5102280c16bSPyun YongHyeon struct sysctl_ctx_list *, struct sysctl_oid_list *); 5112280c16bSPyun YongHyeon static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 5122280c16bSPyun YongHyeon struct sysctl_oid_list *); 513763757b2SScott Long static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 5146f8718a3SScott Long 51595d67482SBill Paul static device_method_t bge_methods[] = { 51695d67482SBill Paul /* Device interface */ 51795d67482SBill Paul DEVMETHOD(device_probe, bge_probe), 51895d67482SBill Paul DEVMETHOD(device_attach, bge_attach), 51995d67482SBill Paul DEVMETHOD(device_detach, bge_detach), 52095d67482SBill Paul DEVMETHOD(device_shutdown, bge_shutdown), 52114afefa3SPawel Jakub Dawidek DEVMETHOD(device_suspend, bge_suspend), 52214afefa3SPawel Jakub Dawidek DEVMETHOD(device_resume, bge_resume), 52395d67482SBill Paul 52495d67482SBill Paul /* MII interface */ 52595d67482SBill Paul DEVMETHOD(miibus_readreg, bge_miibus_readreg), 52695d67482SBill Paul DEVMETHOD(miibus_writereg, bge_miibus_writereg), 52795d67482SBill Paul DEVMETHOD(miibus_statchg, bge_miibus_statchg), 52895d67482SBill Paul 5294b7ec270SMarius Strobl DEVMETHOD_END 53095d67482SBill Paul }; 53195d67482SBill Paul 53295d67482SBill Paul static driver_t bge_driver = { 53395d67482SBill Paul "bge", 53495d67482SBill Paul bge_methods, 53595d67482SBill Paul sizeof(struct bge_softc) 53695d67482SBill Paul }; 53795d67482SBill Paul 53895d67482SBill Paul static devclass_t bge_devclass; 53995d67482SBill Paul 540f246e4a1SMatthew N. Dodd DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 54195d67482SBill Paul DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 54295d67482SBill Paul 543f1a7e6d5SScott Long static int bge_allow_asf = 1; 544f1a7e6d5SScott Long 5456472ac3dSEd Schouten static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 546af3b2549SHans Petter Selasky SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 547f1a7e6d5SScott Long "Allow ASF mode if available"); 548c4529f41SMichael Reifenberger 54908013fd3SMarius Strobl #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 55008013fd3SMarius Strobl #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 55108013fd3SMarius Strobl #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 55208013fd3SMarius Strobl #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 55308013fd3SMarius Strobl #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 55408013fd3SMarius Strobl 55508013fd3SMarius Strobl static int 5565fea260fSMarius Strobl bge_has_eaddr(struct bge_softc *sc) 55708013fd3SMarius Strobl { 55808013fd3SMarius Strobl #ifdef __sparc64__ 55908013fd3SMarius Strobl char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 56008013fd3SMarius Strobl device_t dev; 56108013fd3SMarius Strobl uint32_t subvendor; 56208013fd3SMarius Strobl 56308013fd3SMarius Strobl dev = sc->bge_dev; 56408013fd3SMarius Strobl 56508013fd3SMarius Strobl /* 56608013fd3SMarius Strobl * The on-board BGEs found in sun4u machines aren't fitted with 56708013fd3SMarius Strobl * an EEPROM which means that we have to obtain the MAC address 56808013fd3SMarius Strobl * via OFW and that some tests will always fail. We distinguish 56908013fd3SMarius Strobl * such BGEs by the subvendor ID, which also has to be obtained 57008013fd3SMarius Strobl * from OFW instead of the PCI configuration space as the latter 57108013fd3SMarius Strobl * indicates Broadcom as the subvendor of the netboot interface. 57208013fd3SMarius Strobl * For early Blade 1500 and 2500 we even have to check the OFW 57308013fd3SMarius Strobl * device path as the subvendor ID always defaults to Broadcom 57408013fd3SMarius Strobl * there. 57508013fd3SMarius Strobl */ 57608013fd3SMarius Strobl if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 57708013fd3SMarius Strobl &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 5782d857b9bSMarius Strobl (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 57908013fd3SMarius Strobl return (0); 58008013fd3SMarius Strobl memset(buf, 0, sizeof(buf)); 58108013fd3SMarius Strobl if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 58208013fd3SMarius Strobl if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 58308013fd3SMarius Strobl strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 58408013fd3SMarius Strobl return (0); 58508013fd3SMarius Strobl if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 58608013fd3SMarius Strobl strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 58708013fd3SMarius Strobl return (0); 58808013fd3SMarius Strobl } 58908013fd3SMarius Strobl #endif 59008013fd3SMarius Strobl return (1); 59108013fd3SMarius Strobl } 59208013fd3SMarius Strobl 5933f74909aSGleb Smirnoff static uint32_t 5943f74909aSGleb Smirnoff bge_readmem_ind(struct bge_softc *sc, int off) 59595d67482SBill Paul { 59695d67482SBill Paul device_t dev; 5976f8718a3SScott Long uint32_t val; 59895d67482SBill Paul 599a4431ebaSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 600a4431ebaSPyun YongHyeon off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 601a4431ebaSPyun YongHyeon return (0); 602a4431ebaSPyun YongHyeon 60395d67482SBill Paul dev = sc->bge_dev; 60495d67482SBill Paul 60595d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 6066f8718a3SScott Long val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 6076f8718a3SScott Long pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 6086f8718a3SScott Long return (val); 60995d67482SBill Paul } 61095d67482SBill Paul 61195d67482SBill Paul static void 6123f74909aSGleb Smirnoff bge_writemem_ind(struct bge_softc *sc, int off, int val) 61395d67482SBill Paul { 61495d67482SBill Paul device_t dev; 61595d67482SBill Paul 616a4431ebaSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 617a4431ebaSPyun YongHyeon off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 618a4431ebaSPyun YongHyeon return; 619a4431ebaSPyun YongHyeon 62095d67482SBill Paul dev = sc->bge_dev; 62195d67482SBill Paul 62295d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 62395d67482SBill Paul pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 6246f8718a3SScott Long pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 62595d67482SBill Paul } 62695d67482SBill Paul 62795d67482SBill Paul #ifdef notdef 6283f74909aSGleb Smirnoff static uint32_t 6293f74909aSGleb Smirnoff bge_readreg_ind(struct bge_softc *sc, int off) 63095d67482SBill Paul { 63195d67482SBill Paul device_t dev; 63295d67482SBill Paul 63395d67482SBill Paul dev = sc->bge_dev; 63495d67482SBill Paul 63595d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 63695d67482SBill Paul return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 63795d67482SBill Paul } 63895d67482SBill Paul #endif 63995d67482SBill Paul 64095d67482SBill Paul static void 6413f74909aSGleb Smirnoff bge_writereg_ind(struct bge_softc *sc, int off, int val) 64295d67482SBill Paul { 64395d67482SBill Paul device_t dev; 64495d67482SBill Paul 64595d67482SBill Paul dev = sc->bge_dev; 64695d67482SBill Paul 64795d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 64895d67482SBill Paul pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 64995d67482SBill Paul } 65095d67482SBill Paul 6516f8718a3SScott Long static void 6526f8718a3SScott Long bge_writemem_direct(struct bge_softc *sc, int off, int val) 6536f8718a3SScott Long { 6546f8718a3SScott Long CSR_WRITE_4(sc, off, val); 6556f8718a3SScott Long } 6566f8718a3SScott Long 65738cc658fSJohn Baldwin static void 65838cc658fSJohn Baldwin bge_writembx(struct bge_softc *sc, int off, int val) 65938cc658fSJohn Baldwin { 66038cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 66138cc658fSJohn Baldwin off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 66238cc658fSJohn Baldwin 66338cc658fSJohn Baldwin CSR_WRITE_4(sc, off, val); 664062af0b0SPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 665062af0b0SPyun YongHyeon CSR_READ_4(sc, off); 66638cc658fSJohn Baldwin } 66738cc658fSJohn Baldwin 668f41ac2beSBill Paul /* 669548c8f1aSPyun YongHyeon * Clear all stale locks and select the lock for this driver instance. 670548c8f1aSPyun YongHyeon */ 671548c8f1aSPyun YongHyeon static void 672548c8f1aSPyun YongHyeon bge_ape_lock_init(struct bge_softc *sc) 673548c8f1aSPyun YongHyeon { 674548c8f1aSPyun YongHyeon uint32_t bit, regbase; 675548c8f1aSPyun YongHyeon int i; 676548c8f1aSPyun YongHyeon 677548c8f1aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 678548c8f1aSPyun YongHyeon regbase = BGE_APE_LOCK_GRANT; 679548c8f1aSPyun YongHyeon else 680548c8f1aSPyun YongHyeon regbase = BGE_APE_PER_LOCK_GRANT; 681548c8f1aSPyun YongHyeon 682548c8f1aSPyun YongHyeon /* Clear any stale locks. */ 683548c8f1aSPyun YongHyeon for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 684548c8f1aSPyun YongHyeon switch (i) { 685548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY0: 686548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY1: 687548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY2: 688548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY3: 689548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 690548c8f1aSPyun YongHyeon break; 691548c8f1aSPyun YongHyeon default: 692bd9c196aSPyun YongHyeon if (sc->bge_func_addr == 0) 693548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 694548c8f1aSPyun YongHyeon else 695548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 696548c8f1aSPyun YongHyeon } 697548c8f1aSPyun YongHyeon APE_WRITE_4(sc, regbase + 4 * i, bit); 698548c8f1aSPyun YongHyeon } 699548c8f1aSPyun YongHyeon 700548c8f1aSPyun YongHyeon /* Select the PHY lock based on the device's function number. */ 701548c8f1aSPyun YongHyeon switch (sc->bge_func_addr) { 702548c8f1aSPyun YongHyeon case 0: 703548c8f1aSPyun YongHyeon sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 704548c8f1aSPyun YongHyeon break; 705548c8f1aSPyun YongHyeon case 1: 706548c8f1aSPyun YongHyeon sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 707548c8f1aSPyun YongHyeon break; 708548c8f1aSPyun YongHyeon case 2: 709548c8f1aSPyun YongHyeon sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 710548c8f1aSPyun YongHyeon break; 711548c8f1aSPyun YongHyeon case 3: 712548c8f1aSPyun YongHyeon sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 713548c8f1aSPyun YongHyeon break; 714548c8f1aSPyun YongHyeon default: 715548c8f1aSPyun YongHyeon device_printf(sc->bge_dev, 716548c8f1aSPyun YongHyeon "PHY lock not supported on this function\n"); 717548c8f1aSPyun YongHyeon } 718548c8f1aSPyun YongHyeon } 719548c8f1aSPyun YongHyeon 720548c8f1aSPyun YongHyeon /* 721548c8f1aSPyun YongHyeon * Check for APE firmware, set flags, and print version info. 722548c8f1aSPyun YongHyeon */ 723548c8f1aSPyun YongHyeon static void 724548c8f1aSPyun YongHyeon bge_ape_read_fw_ver(struct bge_softc *sc) 725548c8f1aSPyun YongHyeon { 726548c8f1aSPyun YongHyeon const char *fwtype; 727548c8f1aSPyun YongHyeon uint32_t apedata, features; 728548c8f1aSPyun YongHyeon 729548c8f1aSPyun YongHyeon /* Check for a valid APE signature in shared memory. */ 730548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 731548c8f1aSPyun YongHyeon if (apedata != BGE_APE_SEG_SIG_MAGIC) { 732548c8f1aSPyun YongHyeon sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 733548c8f1aSPyun YongHyeon return; 734548c8f1aSPyun YongHyeon } 735548c8f1aSPyun YongHyeon 736548c8f1aSPyun YongHyeon /* Check if APE firmware is running. */ 737548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 738548c8f1aSPyun YongHyeon if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 739548c8f1aSPyun YongHyeon device_printf(sc->bge_dev, "APE signature found " 740548c8f1aSPyun YongHyeon "but FW status not ready! 0x%08x\n", apedata); 741548c8f1aSPyun YongHyeon return; 742548c8f1aSPyun YongHyeon } 743548c8f1aSPyun YongHyeon 744548c8f1aSPyun YongHyeon sc->bge_mfw_flags |= BGE_MFW_ON_APE; 745548c8f1aSPyun YongHyeon 746548c8f1aSPyun YongHyeon /* Fetch the APE firwmare type and version. */ 747548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 748548c8f1aSPyun YongHyeon features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 749548c8f1aSPyun YongHyeon if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 750548c8f1aSPyun YongHyeon sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 751548c8f1aSPyun YongHyeon fwtype = "NCSI"; 752548c8f1aSPyun YongHyeon } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 753548c8f1aSPyun YongHyeon sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 754548c8f1aSPyun YongHyeon fwtype = "DASH"; 755548c8f1aSPyun YongHyeon } else 756548c8f1aSPyun YongHyeon fwtype = "UNKN"; 757548c8f1aSPyun YongHyeon 758548c8f1aSPyun YongHyeon /* Print the APE firmware version. */ 759548c8f1aSPyun YongHyeon device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 760548c8f1aSPyun YongHyeon fwtype, 761548c8f1aSPyun YongHyeon (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 762548c8f1aSPyun YongHyeon (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 763548c8f1aSPyun YongHyeon (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 764548c8f1aSPyun YongHyeon (apedata & BGE_APE_FW_VERSION_BLDMSK)); 765548c8f1aSPyun YongHyeon } 766548c8f1aSPyun YongHyeon 767548c8f1aSPyun YongHyeon static int 768548c8f1aSPyun YongHyeon bge_ape_lock(struct bge_softc *sc, int locknum) 769548c8f1aSPyun YongHyeon { 770548c8f1aSPyun YongHyeon uint32_t bit, gnt, req, status; 771548c8f1aSPyun YongHyeon int i, off; 772548c8f1aSPyun YongHyeon 773548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 774548c8f1aSPyun YongHyeon return (0); 775548c8f1aSPyun YongHyeon 776548c8f1aSPyun YongHyeon /* Lock request/grant registers have different bases. */ 777548c8f1aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 778548c8f1aSPyun YongHyeon req = BGE_APE_LOCK_REQ; 779548c8f1aSPyun YongHyeon gnt = BGE_APE_LOCK_GRANT; 780548c8f1aSPyun YongHyeon } else { 781548c8f1aSPyun YongHyeon req = BGE_APE_PER_LOCK_REQ; 782548c8f1aSPyun YongHyeon gnt = BGE_APE_PER_LOCK_GRANT; 783548c8f1aSPyun YongHyeon } 784548c8f1aSPyun YongHyeon 785548c8f1aSPyun YongHyeon off = 4 * locknum; 786548c8f1aSPyun YongHyeon 787548c8f1aSPyun YongHyeon switch (locknum) { 788548c8f1aSPyun YongHyeon case BGE_APE_LOCK_GPIO: 789548c8f1aSPyun YongHyeon /* Lock required when using GPIO. */ 790548c8f1aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 791548c8f1aSPyun YongHyeon return (0); 792548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 793548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_REQ_DRIVER0; 794548c8f1aSPyun YongHyeon else 795548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 796548c8f1aSPyun YongHyeon break; 797548c8f1aSPyun YongHyeon case BGE_APE_LOCK_GRC: 798548c8f1aSPyun YongHyeon /* Lock required to reset the device. */ 799548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 800548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_REQ_DRIVER0; 801548c8f1aSPyun YongHyeon else 802548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 803548c8f1aSPyun YongHyeon break; 804548c8f1aSPyun YongHyeon case BGE_APE_LOCK_MEM: 805548c8f1aSPyun YongHyeon /* Lock required when accessing certain APE memory. */ 806548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 807548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_REQ_DRIVER0; 808548c8f1aSPyun YongHyeon else 809548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 810548c8f1aSPyun YongHyeon break; 811548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY0: 812548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY1: 813548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY2: 814548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY3: 815548c8f1aSPyun YongHyeon /* Lock required when accessing PHYs. */ 816548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_REQ_DRIVER0; 817548c8f1aSPyun YongHyeon break; 818548c8f1aSPyun YongHyeon default: 819548c8f1aSPyun YongHyeon return (EINVAL); 820548c8f1aSPyun YongHyeon } 821548c8f1aSPyun YongHyeon 822548c8f1aSPyun YongHyeon /* Request a lock. */ 823548c8f1aSPyun YongHyeon APE_WRITE_4(sc, req + off, bit); 824548c8f1aSPyun YongHyeon 825548c8f1aSPyun YongHyeon /* Wait up to 1 second to acquire lock. */ 826548c8f1aSPyun YongHyeon for (i = 0; i < 20000; i++) { 827548c8f1aSPyun YongHyeon status = APE_READ_4(sc, gnt + off); 828548c8f1aSPyun YongHyeon if (status == bit) 829548c8f1aSPyun YongHyeon break; 830548c8f1aSPyun YongHyeon DELAY(50); 831548c8f1aSPyun YongHyeon } 832548c8f1aSPyun YongHyeon 833548c8f1aSPyun YongHyeon /* Handle any errors. */ 834548c8f1aSPyun YongHyeon if (status != bit) { 835548c8f1aSPyun YongHyeon device_printf(sc->bge_dev, "APE lock %d request failed! " 836548c8f1aSPyun YongHyeon "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 837548c8f1aSPyun YongHyeon locknum, req + off, bit & 0xFFFF, gnt + off, 838548c8f1aSPyun YongHyeon status & 0xFFFF); 839548c8f1aSPyun YongHyeon /* Revoke the lock request. */ 840548c8f1aSPyun YongHyeon APE_WRITE_4(sc, gnt + off, bit); 841548c8f1aSPyun YongHyeon return (EBUSY); 842548c8f1aSPyun YongHyeon } 843548c8f1aSPyun YongHyeon 844548c8f1aSPyun YongHyeon return (0); 845548c8f1aSPyun YongHyeon } 846548c8f1aSPyun YongHyeon 847548c8f1aSPyun YongHyeon static void 848548c8f1aSPyun YongHyeon bge_ape_unlock(struct bge_softc *sc, int locknum) 849548c8f1aSPyun YongHyeon { 850548c8f1aSPyun YongHyeon uint32_t bit, gnt; 851548c8f1aSPyun YongHyeon int off; 852548c8f1aSPyun YongHyeon 853548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 854548c8f1aSPyun YongHyeon return; 855548c8f1aSPyun YongHyeon 856548c8f1aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 857548c8f1aSPyun YongHyeon gnt = BGE_APE_LOCK_GRANT; 858548c8f1aSPyun YongHyeon else 859548c8f1aSPyun YongHyeon gnt = BGE_APE_PER_LOCK_GRANT; 860548c8f1aSPyun YongHyeon 861548c8f1aSPyun YongHyeon off = 4 * locknum; 862548c8f1aSPyun YongHyeon 863548c8f1aSPyun YongHyeon switch (locknum) { 864548c8f1aSPyun YongHyeon case BGE_APE_LOCK_GPIO: 865548c8f1aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 866548c8f1aSPyun YongHyeon return; 867548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 868548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 869548c8f1aSPyun YongHyeon else 870548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 871548c8f1aSPyun YongHyeon break; 872548c8f1aSPyun YongHyeon case BGE_APE_LOCK_GRC: 873548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 874548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 875548c8f1aSPyun YongHyeon else 876548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 877548c8f1aSPyun YongHyeon break; 878548c8f1aSPyun YongHyeon case BGE_APE_LOCK_MEM: 879548c8f1aSPyun YongHyeon if (sc->bge_func_addr == 0) 880548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 881548c8f1aSPyun YongHyeon else 882548c8f1aSPyun YongHyeon bit = (1 << sc->bge_func_addr); 883548c8f1aSPyun YongHyeon break; 884548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY0: 885548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY1: 886548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY2: 887548c8f1aSPyun YongHyeon case BGE_APE_LOCK_PHY3: 888548c8f1aSPyun YongHyeon bit = BGE_APE_LOCK_GRANT_DRIVER0; 889548c8f1aSPyun YongHyeon break; 890548c8f1aSPyun YongHyeon default: 891548c8f1aSPyun YongHyeon return; 892548c8f1aSPyun YongHyeon } 893548c8f1aSPyun YongHyeon 894548c8f1aSPyun YongHyeon APE_WRITE_4(sc, gnt + off, bit); 895548c8f1aSPyun YongHyeon } 896548c8f1aSPyun YongHyeon 897548c8f1aSPyun YongHyeon /* 898548c8f1aSPyun YongHyeon * Send an event to the APE firmware. 899548c8f1aSPyun YongHyeon */ 900548c8f1aSPyun YongHyeon static void 901548c8f1aSPyun YongHyeon bge_ape_send_event(struct bge_softc *sc, uint32_t event) 902548c8f1aSPyun YongHyeon { 903548c8f1aSPyun YongHyeon uint32_t apedata; 904548c8f1aSPyun YongHyeon int i; 905548c8f1aSPyun YongHyeon 906548c8f1aSPyun YongHyeon /* NCSI does not support APE events. */ 907548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 908548c8f1aSPyun YongHyeon return; 909548c8f1aSPyun YongHyeon 910548c8f1aSPyun YongHyeon /* Wait up to 1ms for APE to service previous event. */ 911548c8f1aSPyun YongHyeon for (i = 10; i > 0; i--) { 912548c8f1aSPyun YongHyeon if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 913548c8f1aSPyun YongHyeon break; 914548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 915548c8f1aSPyun YongHyeon if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 916548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 917548c8f1aSPyun YongHyeon BGE_APE_EVENT_STATUS_EVENT_PENDING); 918548c8f1aSPyun YongHyeon bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 919548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 920548c8f1aSPyun YongHyeon break; 921548c8f1aSPyun YongHyeon } 922548c8f1aSPyun YongHyeon bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 923548c8f1aSPyun YongHyeon DELAY(100); 924548c8f1aSPyun YongHyeon } 925548c8f1aSPyun YongHyeon if (i == 0) 926548c8f1aSPyun YongHyeon device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 927548c8f1aSPyun YongHyeon event); 928548c8f1aSPyun YongHyeon } 929548c8f1aSPyun YongHyeon 930548c8f1aSPyun YongHyeon static void 931548c8f1aSPyun YongHyeon bge_ape_driver_state_change(struct bge_softc *sc, int kind) 932548c8f1aSPyun YongHyeon { 933548c8f1aSPyun YongHyeon uint32_t apedata, event; 934548c8f1aSPyun YongHyeon 935548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 936548c8f1aSPyun YongHyeon return; 937548c8f1aSPyun YongHyeon 938548c8f1aSPyun YongHyeon switch (kind) { 939548c8f1aSPyun YongHyeon case BGE_RESET_START: 940548c8f1aSPyun YongHyeon /* If this is the first load, clear the load counter. */ 941548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 942548c8f1aSPyun YongHyeon if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 943548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 944548c8f1aSPyun YongHyeon else { 945548c8f1aSPyun YongHyeon apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 946548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 947548c8f1aSPyun YongHyeon } 948548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 949548c8f1aSPyun YongHyeon BGE_APE_HOST_SEG_SIG_MAGIC); 950548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 951548c8f1aSPyun YongHyeon BGE_APE_HOST_SEG_LEN_MAGIC); 952548c8f1aSPyun YongHyeon 953548c8f1aSPyun YongHyeon /* Add some version info if bge(4) supports it. */ 954548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 955548c8f1aSPyun YongHyeon BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 956548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 957548c8f1aSPyun YongHyeon BGE_APE_HOST_BEHAV_NO_PHYLOCK); 958548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 959548c8f1aSPyun YongHyeon BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 960548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 961548c8f1aSPyun YongHyeon BGE_APE_HOST_DRVR_STATE_START); 962548c8f1aSPyun YongHyeon event = BGE_APE_EVENT_STATUS_STATE_START; 963548c8f1aSPyun YongHyeon break; 964548c8f1aSPyun YongHyeon case BGE_RESET_SHUTDOWN: 965548c8f1aSPyun YongHyeon APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 966548c8f1aSPyun YongHyeon BGE_APE_HOST_DRVR_STATE_UNLOAD); 967548c8f1aSPyun YongHyeon event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 968548c8f1aSPyun YongHyeon break; 969548c8f1aSPyun YongHyeon case BGE_RESET_SUSPEND: 970548c8f1aSPyun YongHyeon event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 971548c8f1aSPyun YongHyeon break; 972548c8f1aSPyun YongHyeon default: 973548c8f1aSPyun YongHyeon return; 974548c8f1aSPyun YongHyeon } 975548c8f1aSPyun YongHyeon 976548c8f1aSPyun YongHyeon bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 977548c8f1aSPyun YongHyeon BGE_APE_EVENT_STATUS_STATE_CHNGE); 978548c8f1aSPyun YongHyeon } 979548c8f1aSPyun YongHyeon 980548c8f1aSPyun YongHyeon /* 981f41ac2beSBill Paul * Map a single buffer address. 982f41ac2beSBill Paul */ 983f41ac2beSBill Paul 984f41ac2beSBill Paul static void 9853f74909aSGleb Smirnoff bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986f41ac2beSBill Paul { 987f41ac2beSBill Paul struct bge_dmamap_arg *ctx; 988f41ac2beSBill Paul 989f41ac2beSBill Paul if (error) 990f41ac2beSBill Paul return; 991f41ac2beSBill Paul 9925b610048SPyun YongHyeon KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 9935b610048SPyun YongHyeon 994f41ac2beSBill Paul ctx = arg; 995f41ac2beSBill Paul ctx->bge_busaddr = segs->ds_addr; 996f41ac2beSBill Paul } 997f41ac2beSBill Paul 99838cc658fSJohn Baldwin static uint8_t 99938cc658fSJohn Baldwin bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 100038cc658fSJohn Baldwin { 100138cc658fSJohn Baldwin uint32_t access, byte = 0; 100238cc658fSJohn Baldwin int i; 100338cc658fSJohn Baldwin 100438cc658fSJohn Baldwin /* Lock. */ 100538cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 100638cc658fSJohn Baldwin for (i = 0; i < 8000; i++) { 100738cc658fSJohn Baldwin if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 100838cc658fSJohn Baldwin break; 100938cc658fSJohn Baldwin DELAY(20); 101038cc658fSJohn Baldwin } 101138cc658fSJohn Baldwin if (i == 8000) 101238cc658fSJohn Baldwin return (1); 101338cc658fSJohn Baldwin 101438cc658fSJohn Baldwin /* Enable access. */ 101538cc658fSJohn Baldwin access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 101638cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 101738cc658fSJohn Baldwin 101838cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 101938cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 102038cc658fSJohn Baldwin for (i = 0; i < BGE_TIMEOUT * 10; i++) { 102138cc658fSJohn Baldwin DELAY(10); 102238cc658fSJohn Baldwin if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 102338cc658fSJohn Baldwin DELAY(10); 102438cc658fSJohn Baldwin break; 102538cc658fSJohn Baldwin } 102638cc658fSJohn Baldwin } 102738cc658fSJohn Baldwin 102838cc658fSJohn Baldwin if (i == BGE_TIMEOUT * 10) { 102938cc658fSJohn Baldwin if_printf(sc->bge_ifp, "nvram read timed out\n"); 103038cc658fSJohn Baldwin return (1); 103138cc658fSJohn Baldwin } 103238cc658fSJohn Baldwin 103338cc658fSJohn Baldwin /* Get result. */ 103438cc658fSJohn Baldwin byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 103538cc658fSJohn Baldwin 103638cc658fSJohn Baldwin *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 103738cc658fSJohn Baldwin 103838cc658fSJohn Baldwin /* Disable access. */ 103938cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 104038cc658fSJohn Baldwin 104138cc658fSJohn Baldwin /* Unlock. */ 104238cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 104338cc658fSJohn Baldwin CSR_READ_4(sc, BGE_NVRAM_SWARB); 104438cc658fSJohn Baldwin 104538cc658fSJohn Baldwin return (0); 104638cc658fSJohn Baldwin } 104738cc658fSJohn Baldwin 104838cc658fSJohn Baldwin /* 104938cc658fSJohn Baldwin * Read a sequence of bytes from NVRAM. 105038cc658fSJohn Baldwin */ 105138cc658fSJohn Baldwin static int 105238cc658fSJohn Baldwin bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 105338cc658fSJohn Baldwin { 105438cc658fSJohn Baldwin int err = 0, i; 105538cc658fSJohn Baldwin uint8_t byte = 0; 105638cc658fSJohn Baldwin 105738cc658fSJohn Baldwin if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 105838cc658fSJohn Baldwin return (1); 105938cc658fSJohn Baldwin 106038cc658fSJohn Baldwin for (i = 0; i < cnt; i++) { 106138cc658fSJohn Baldwin err = bge_nvram_getbyte(sc, off + i, &byte); 106238cc658fSJohn Baldwin if (err) 106338cc658fSJohn Baldwin break; 106438cc658fSJohn Baldwin *(dest + i) = byte; 106538cc658fSJohn Baldwin } 106638cc658fSJohn Baldwin 106738cc658fSJohn Baldwin return (err ? 1 : 0); 106838cc658fSJohn Baldwin } 106938cc658fSJohn Baldwin 107095d67482SBill Paul /* 107195d67482SBill Paul * Read a byte of data stored in the EEPROM at address 'addr.' The 107295d67482SBill Paul * BCM570x supports both the traditional bitbang interface and an 107395d67482SBill Paul * auto access interface for reading the EEPROM. We use the auto 107495d67482SBill Paul * access method. 107595d67482SBill Paul */ 10763f74909aSGleb Smirnoff static uint8_t 10773f74909aSGleb Smirnoff bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 107895d67482SBill Paul { 107995d67482SBill Paul int i; 10803f74909aSGleb Smirnoff uint32_t byte = 0; 108195d67482SBill Paul 108295d67482SBill Paul /* 108395d67482SBill Paul * Enable use of auto EEPROM access so we can avoid 108495d67482SBill Paul * having to use the bitbang method. 108595d67482SBill Paul */ 108695d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 108795d67482SBill Paul 108895d67482SBill Paul /* Reset the EEPROM, load the clock period. */ 108995d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, 109095d67482SBill Paul BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 109195d67482SBill Paul DELAY(20); 109295d67482SBill Paul 109395d67482SBill Paul /* Issue the read EEPROM command. */ 109495d67482SBill Paul CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 109595d67482SBill Paul 109695d67482SBill Paul /* Wait for completion */ 109795d67482SBill Paul for(i = 0; i < BGE_TIMEOUT * 10; i++) { 109895d67482SBill Paul DELAY(10); 109995d67482SBill Paul if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 110095d67482SBill Paul break; 110195d67482SBill Paul } 110295d67482SBill Paul 1103d5d23857SJung-uk Kim if (i == BGE_TIMEOUT * 10) { 1104fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1105f6789fbaSPyun YongHyeon return (1); 110695d67482SBill Paul } 110795d67482SBill Paul 110895d67482SBill Paul /* Get result. */ 110995d67482SBill Paul byte = CSR_READ_4(sc, BGE_EE_DATA); 111095d67482SBill Paul 11110c8aa4eaSJung-uk Kim *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 111295d67482SBill Paul 111395d67482SBill Paul return (0); 111495d67482SBill Paul } 111595d67482SBill Paul 111695d67482SBill Paul /* 111795d67482SBill Paul * Read a sequence of bytes from the EEPROM. 111895d67482SBill Paul */ 111995d67482SBill Paul static int 11203f74909aSGleb Smirnoff bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 112195d67482SBill Paul { 11223f74909aSGleb Smirnoff int i, error = 0; 11233f74909aSGleb Smirnoff uint8_t byte = 0; 112495d67482SBill Paul 112595d67482SBill Paul for (i = 0; i < cnt; i++) { 11263f74909aSGleb Smirnoff error = bge_eeprom_getbyte(sc, off + i, &byte); 11273f74909aSGleb Smirnoff if (error) 112895d67482SBill Paul break; 112995d67482SBill Paul *(dest + i) = byte; 113095d67482SBill Paul } 113195d67482SBill Paul 11323f74909aSGleb Smirnoff return (error ? 1 : 0); 113395d67482SBill Paul } 113495d67482SBill Paul 113595d67482SBill Paul static int 11363f74909aSGleb Smirnoff bge_miibus_readreg(device_t dev, int phy, int reg) 113795d67482SBill Paul { 113895d67482SBill Paul struct bge_softc *sc; 1139a813ed78SPyun YongHyeon uint32_t val; 114095d67482SBill Paul int i; 114195d67482SBill Paul 114295d67482SBill Paul sc = device_get_softc(dev); 114395d67482SBill Paul 1144548c8f1aSPyun YongHyeon if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1145548c8f1aSPyun YongHyeon return (0); 1146548c8f1aSPyun YongHyeon 1147a813ed78SPyun YongHyeon /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1148a813ed78SPyun YongHyeon if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1149a813ed78SPyun YongHyeon CSR_WRITE_4(sc, BGE_MI_MODE, 1150a813ed78SPyun YongHyeon sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1151a813ed78SPyun YongHyeon DELAY(80); 115237ceeb4dSPaul Saab } 115337ceeb4dSPaul Saab 115495d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 115595d67482SBill Paul BGE_MIPHY(phy) | BGE_MIREG(reg)); 115695d67482SBill Paul 1157a813ed78SPyun YongHyeon /* Poll for the PHY register access to complete. */ 115895d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 1159d5d23857SJung-uk Kim DELAY(10); 116095d67482SBill Paul val = CSR_READ_4(sc, BGE_MI_COMM); 1161a813ed78SPyun YongHyeon if ((val & BGE_MICOMM_BUSY) == 0) { 1162a813ed78SPyun YongHyeon DELAY(5); 1163a813ed78SPyun YongHyeon val = CSR_READ_4(sc, BGE_MI_COMM); 116495d67482SBill Paul break; 116595d67482SBill Paul } 1166a813ed78SPyun YongHyeon } 116795d67482SBill Paul 116895d67482SBill Paul if (i == BGE_TIMEOUT) { 11695fea260fSMarius Strobl device_printf(sc->bge_dev, 11705fea260fSMarius Strobl "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 11715fea260fSMarius Strobl phy, reg, val); 117237ceeb4dSPaul Saab val = 0; 117395d67482SBill Paul } 117495d67482SBill Paul 1175a813ed78SPyun YongHyeon /* Restore the autopoll bit if necessary. */ 1176a813ed78SPyun YongHyeon if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1177a813ed78SPyun YongHyeon CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1178a813ed78SPyun YongHyeon DELAY(80); 117937ceeb4dSPaul Saab } 118037ceeb4dSPaul Saab 1181548c8f1aSPyun YongHyeon bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1182548c8f1aSPyun YongHyeon 118395d67482SBill Paul if (val & BGE_MICOMM_READFAIL) 118495d67482SBill Paul return (0); 118595d67482SBill Paul 11860c8aa4eaSJung-uk Kim return (val & 0xFFFF); 118795d67482SBill Paul } 118895d67482SBill Paul 118995d67482SBill Paul static int 11903f74909aSGleb Smirnoff bge_miibus_writereg(device_t dev, int phy, int reg, int val) 119195d67482SBill Paul { 119295d67482SBill Paul struct bge_softc *sc; 119395d67482SBill Paul int i; 119495d67482SBill Paul 119595d67482SBill Paul sc = device_get_softc(dev); 119695d67482SBill Paul 119738cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 119838cc658fSJohn Baldwin (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 119938cc658fSJohn Baldwin return (0); 120038cc658fSJohn Baldwin 1201548c8f1aSPyun YongHyeon if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1202548c8f1aSPyun YongHyeon return (0); 1203548c8f1aSPyun YongHyeon 1204a813ed78SPyun YongHyeon /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1205a813ed78SPyun YongHyeon if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1206a813ed78SPyun YongHyeon CSR_WRITE_4(sc, BGE_MI_MODE, 1207a813ed78SPyun YongHyeon sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1208a813ed78SPyun YongHyeon DELAY(80); 120937ceeb4dSPaul Saab } 121037ceeb4dSPaul Saab 121195d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 121295d67482SBill Paul BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 121395d67482SBill Paul 121495d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 1215d5d23857SJung-uk Kim DELAY(10); 121638cc658fSJohn Baldwin if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 121738cc658fSJohn Baldwin DELAY(5); 121838cc658fSJohn Baldwin CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 121995d67482SBill Paul break; 1220d5d23857SJung-uk Kim } 122138cc658fSJohn Baldwin } 1222d5d23857SJung-uk Kim 1223a813ed78SPyun YongHyeon /* Restore the autopoll bit if necessary. */ 1224a813ed78SPyun YongHyeon if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1225a813ed78SPyun YongHyeon CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1226a813ed78SPyun YongHyeon DELAY(80); 1227a813ed78SPyun YongHyeon } 1228a813ed78SPyun YongHyeon 1229548c8f1aSPyun YongHyeon bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1230548c8f1aSPyun YongHyeon 1231a813ed78SPyun YongHyeon if (i == BGE_TIMEOUT) 123238cc658fSJohn Baldwin device_printf(sc->bge_dev, 12332246e8c6SPyun YongHyeon "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 123438cc658fSJohn Baldwin phy, reg, val); 123537ceeb4dSPaul Saab 123695d67482SBill Paul return (0); 123795d67482SBill Paul } 123895d67482SBill Paul 123995d67482SBill Paul static void 12403f74909aSGleb Smirnoff bge_miibus_statchg(device_t dev) 124195d67482SBill Paul { 124295d67482SBill Paul struct bge_softc *sc; 124395d67482SBill Paul struct mii_data *mii; 1244a0a03d1eSPyun YongHyeon uint32_t mac_mode, rx_mode, tx_mode; 1245e4146b95SPyun YongHyeon 124695d67482SBill Paul sc = device_get_softc(dev); 1247fba8b109SMarcel Moolenaar if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1248e4146b95SPyun YongHyeon return; 124995d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 125095d67482SBill Paul 1251d4f5240aSPyun YongHyeon if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1252d4f5240aSPyun YongHyeon (IFM_ACTIVE | IFM_AVALID)) { 1253d4f5240aSPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 1254d4f5240aSPyun YongHyeon case IFM_10_T: 1255d4f5240aSPyun YongHyeon case IFM_100_TX: 1256d4f5240aSPyun YongHyeon sc->bge_link = 1; 1257d4f5240aSPyun YongHyeon break; 1258d4f5240aSPyun YongHyeon case IFM_1000_T: 1259d4f5240aSPyun YongHyeon case IFM_1000_SX: 1260d4f5240aSPyun YongHyeon case IFM_2500_SX: 1261d4f5240aSPyun YongHyeon if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1262d4f5240aSPyun YongHyeon sc->bge_link = 1; 1263d4f5240aSPyun YongHyeon else 1264d4f5240aSPyun YongHyeon sc->bge_link = 0; 1265d4f5240aSPyun YongHyeon break; 1266d4f5240aSPyun YongHyeon default: 1267d4f5240aSPyun YongHyeon sc->bge_link = 0; 1268d4f5240aSPyun YongHyeon break; 1269d4f5240aSPyun YongHyeon } 1270d4f5240aSPyun YongHyeon } else 1271d4f5240aSPyun YongHyeon sc->bge_link = 0; 1272d4f5240aSPyun YongHyeon if (sc->bge_link == 0) 1273d4f5240aSPyun YongHyeon return; 1274a0a03d1eSPyun YongHyeon 1275a0a03d1eSPyun YongHyeon /* 1276a0a03d1eSPyun YongHyeon * APE firmware touches these registers to keep the MAC 1277a0a03d1eSPyun YongHyeon * connected to the outside world. Try to keep the 1278a0a03d1eSPyun YongHyeon * accesses atomic. 1279a0a03d1eSPyun YongHyeon */ 1280a0a03d1eSPyun YongHyeon 1281a0a03d1eSPyun YongHyeon /* Set the port mode (MII/GMII) to match the link speed. */ 1282a0a03d1eSPyun YongHyeon mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1283a0a03d1eSPyun YongHyeon ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1284a0a03d1eSPyun YongHyeon tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1285a0a03d1eSPyun YongHyeon rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1286a0a03d1eSPyun YongHyeon 1287ea3b4127SPyun YongHyeon if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1288ea3b4127SPyun YongHyeon IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1289a0a03d1eSPyun YongHyeon mac_mode |= BGE_PORTMODE_GMII; 12903f74909aSGleb Smirnoff else 1291a0a03d1eSPyun YongHyeon mac_mode |= BGE_PORTMODE_MII; 129295d67482SBill Paul 1293a0a03d1eSPyun YongHyeon /* Set MAC flow control behavior to match link flow control settings. */ 1294a0a03d1eSPyun YongHyeon tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1295a0a03d1eSPyun YongHyeon rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 12964951ca86SPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1297a0a03d1eSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1298a0a03d1eSPyun YongHyeon tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1299a0a03d1eSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1300a0a03d1eSPyun YongHyeon rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1301a0a03d1eSPyun YongHyeon } else 1302a0a03d1eSPyun YongHyeon mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1303a0a03d1eSPyun YongHyeon 1304a0a03d1eSPyun YongHyeon CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 13059b80ffe7SPyun YongHyeon DELAY(40); 1306a0a03d1eSPyun YongHyeon CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1307a0a03d1eSPyun YongHyeon CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 130895d67482SBill Paul } 130995d67482SBill Paul 131095d67482SBill Paul /* 131195d67482SBill Paul * Intialize a standard receive ring descriptor. 131295d67482SBill Paul */ 131395d67482SBill Paul static int 1314943787f3SPyun YongHyeon bge_newbuf_std(struct bge_softc *sc, int i) 131595d67482SBill Paul { 1316943787f3SPyun YongHyeon struct mbuf *m; 131795d67482SBill Paul struct bge_rx_bd *r; 1318a23634a1SPyun YongHyeon bus_dma_segment_t segs[1]; 1319943787f3SPyun YongHyeon bus_dmamap_t map; 1320a23634a1SPyun YongHyeon int error, nsegs; 132195d67482SBill Paul 1322f5459d4cSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1323fba8b109SMarcel Moolenaar (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1324f5459d4cSPyun YongHyeon ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1325c6499eccSGleb Smirnoff m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1326f5459d4cSPyun YongHyeon if (m == NULL) 1327f5459d4cSPyun YongHyeon return (ENOBUFS); 1328f5459d4cSPyun YongHyeon m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1329f5459d4cSPyun YongHyeon } else { 1330c6499eccSGleb Smirnoff m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1331943787f3SPyun YongHyeon if (m == NULL) 133295d67482SBill Paul return (ENOBUFS); 1333943787f3SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 1334f5459d4cSPyun YongHyeon } 1335652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1336943787f3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 1337943787f3SPyun YongHyeon 13380ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1339943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1340a23634a1SPyun YongHyeon if (error != 0) { 1341943787f3SPyun YongHyeon m_freem(m); 1342a23634a1SPyun YongHyeon return (error); 1343f41ac2beSBill Paul } 1344943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1345943787f3SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1346943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1347943787f3SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1348943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i]); 1349943787f3SPyun YongHyeon } 1350943787f3SPyun YongHyeon map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1351943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1352943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap = map; 1353943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_chain[i] = m; 1354e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1355943787f3SPyun YongHyeon r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1356a23634a1SPyun YongHyeon r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1357a23634a1SPyun YongHyeon r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1358e907febfSPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_END; 1359a23634a1SPyun YongHyeon r->bge_len = segs[0].ds_len; 1360e907febfSPyun YongHyeon r->bge_idx = i; 1361f41ac2beSBill Paul 13620ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1363943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 136495d67482SBill Paul 136595d67482SBill Paul return (0); 136695d67482SBill Paul } 136795d67482SBill Paul 136895d67482SBill Paul /* 136995d67482SBill Paul * Initialize a jumbo receive ring descriptor. This allocates 137095d67482SBill Paul * a jumbo buffer from the pool managed internally by the driver. 137195d67482SBill Paul */ 137295d67482SBill Paul static int 1373943787f3SPyun YongHyeon bge_newbuf_jumbo(struct bge_softc *sc, int i) 137495d67482SBill Paul { 13751be6acb7SGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1376943787f3SPyun YongHyeon bus_dmamap_t map; 13771be6acb7SGleb Smirnoff struct bge_extrx_bd *r; 1378943787f3SPyun YongHyeon struct mbuf *m; 1379943787f3SPyun YongHyeon int error, nsegs; 138095d67482SBill Paul 1381c6499eccSGleb Smirnoff MGETHDR(m, M_NOWAIT, MT_DATA); 1382943787f3SPyun YongHyeon if (m == NULL) 138395d67482SBill Paul return (ENOBUFS); 138495d67482SBill Paul 1385c6499eccSGleb Smirnoff m_cljget(m, M_NOWAIT, MJUM9BYTES); 1386943787f3SPyun YongHyeon if (!(m->m_flags & M_EXT)) { 1387943787f3SPyun YongHyeon m_freem(m); 138895d67482SBill Paul return (ENOBUFS); 138995d67482SBill Paul } 1390943787f3SPyun YongHyeon m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1391652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1392943787f3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 13931be6acb7SGleb Smirnoff 13941be6acb7SGleb Smirnoff error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1395943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1396943787f3SPyun YongHyeon if (error != 0) { 1397943787f3SPyun YongHyeon m_freem(m); 13981be6acb7SGleb Smirnoff return (error); 1399f7cea149SGleb Smirnoff } 14001be6acb7SGleb Smirnoff 1401aa8cbdbfSMarius Strobl if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1402943787f3SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1403943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1404943787f3SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1405943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1406943787f3SPyun YongHyeon } 1407943787f3SPyun YongHyeon map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1408943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1409943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap; 1410943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1411943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1412e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1413e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1414e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1415e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1416e0b7b101SPyun YongHyeon 14171be6acb7SGleb Smirnoff /* 14181be6acb7SGleb Smirnoff * Fill in the extended RX buffer descriptor. 14191be6acb7SGleb Smirnoff */ 1420943787f3SPyun YongHyeon r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 14214e7ba1abSGleb Smirnoff r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 14224e7ba1abSGleb Smirnoff r->bge_idx = i; 14234e7ba1abSGleb Smirnoff r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 14244e7ba1abSGleb Smirnoff switch (nsegs) { 14254e7ba1abSGleb Smirnoff case 4: 14264e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 14274e7ba1abSGleb Smirnoff r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 14284e7ba1abSGleb Smirnoff r->bge_len3 = segs[3].ds_len; 1429e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 14304e7ba1abSGleb Smirnoff case 3: 1431e907febfSPyun YongHyeon r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1432e907febfSPyun YongHyeon r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1433e907febfSPyun YongHyeon r->bge_len2 = segs[2].ds_len; 1434e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 14354e7ba1abSGleb Smirnoff case 2: 14364e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 14374e7ba1abSGleb Smirnoff r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 14384e7ba1abSGleb Smirnoff r->bge_len1 = segs[1].ds_len; 1439e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 14404e7ba1abSGleb Smirnoff case 1: 14414e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 14424e7ba1abSGleb Smirnoff r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 14434e7ba1abSGleb Smirnoff r->bge_len0 = segs[0].ds_len; 1444e0b7b101SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 14454e7ba1abSGleb Smirnoff break; 14464e7ba1abSGleb Smirnoff default: 14474e7ba1abSGleb Smirnoff panic("%s: %d segments\n", __func__, nsegs); 14484e7ba1abSGleb Smirnoff } 1449f41ac2beSBill Paul 1450a41504a9SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1451943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 145295d67482SBill Paul 145395d67482SBill Paul return (0); 145495d67482SBill Paul } 145595d67482SBill Paul 145695d67482SBill Paul static int 14573f74909aSGleb Smirnoff bge_init_rx_ring_std(struct bge_softc *sc) 145895d67482SBill Paul { 14593ee5d7daSPyun YongHyeon int error, i; 146095d67482SBill Paul 1461e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 146203e78bd0SPyun YongHyeon sc->bge_std = 0; 1463e0b7b101SPyun YongHyeon for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1464943787f3SPyun YongHyeon if ((error = bge_newbuf_std(sc, i)) != 0) 14653ee5d7daSPyun YongHyeon return (error); 146603e78bd0SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 14671888f324SPyun YongHyeon } 146895d67482SBill Paul 1469f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1470d77e9fa7SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1471f41ac2beSBill Paul 1472e0b7b101SPyun YongHyeon sc->bge_std = 0; 1473e0b7b101SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 147495d67482SBill Paul 147595d67482SBill Paul return (0); 147695d67482SBill Paul } 147795d67482SBill Paul 147895d67482SBill Paul static void 14793f74909aSGleb Smirnoff bge_free_rx_ring_std(struct bge_softc *sc) 148095d67482SBill Paul { 148195d67482SBill Paul int i; 148295d67482SBill Paul 148395d67482SBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 148495d67482SBill Paul if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 14850ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1486e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_dmamap[i], 1487e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 14880ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1489f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 1490e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1491e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_chain[i] = NULL; 149295d67482SBill Paul } 1493f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 149495d67482SBill Paul sizeof(struct bge_rx_bd)); 149595d67482SBill Paul } 149695d67482SBill Paul } 149795d67482SBill Paul 149895d67482SBill Paul static int 14993f74909aSGleb Smirnoff bge_init_rx_ring_jumbo(struct bge_softc *sc) 150095d67482SBill Paul { 150195d67482SBill Paul struct bge_rcb *rcb; 15023ee5d7daSPyun YongHyeon int error, i; 150395d67482SBill Paul 1504e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 150503e78bd0SPyun YongHyeon sc->bge_jumbo = 0; 150695d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1507943787f3SPyun YongHyeon if ((error = bge_newbuf_jumbo(sc, i)) != 0) 15083ee5d7daSPyun YongHyeon return (error); 150903e78bd0SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 15101888f324SPyun YongHyeon } 151195d67482SBill Paul 1512f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1513d77e9fa7SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1514f41ac2beSBill Paul 1515e0b7b101SPyun YongHyeon sc->bge_jumbo = 0; 151695d67482SBill Paul 15178a315a6dSPyun YongHyeon /* Enable the jumbo receive producer ring. */ 1518f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 15198a315a6dSPyun YongHyeon rcb->bge_maxlen_flags = 15208a315a6dSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 152167111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 152295d67482SBill Paul 1523e0b7b101SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 152495d67482SBill Paul 152595d67482SBill Paul return (0); 152695d67482SBill Paul } 152795d67482SBill Paul 152895d67482SBill Paul static void 15293f74909aSGleb Smirnoff bge_free_rx_ring_jumbo(struct bge_softc *sc) 153095d67482SBill Paul { 153195d67482SBill Paul int i; 153295d67482SBill Paul 153395d67482SBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 153495d67482SBill Paul if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1535e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1536e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1537e65bed95SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1538f41ac2beSBill Paul bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1539f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1540e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1541e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 154295d67482SBill Paul } 1543f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 15441be6acb7SGleb Smirnoff sizeof(struct bge_extrx_bd)); 154595d67482SBill Paul } 154695d67482SBill Paul } 154795d67482SBill Paul 154895d67482SBill Paul static void 15493f74909aSGleb Smirnoff bge_free_tx_ring(struct bge_softc *sc) 155095d67482SBill Paul { 155195d67482SBill Paul int i; 155295d67482SBill Paul 1553f41ac2beSBill Paul if (sc->bge_ldata.bge_tx_ring == NULL) 155495d67482SBill Paul return; 155595d67482SBill Paul 155695d67482SBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 155795d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 15580ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1559e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[i], 1560e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 15610ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1562f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 1563e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[i]); 1564e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[i] = NULL; 156595d67482SBill Paul } 1566f41ac2beSBill Paul bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 156795d67482SBill Paul sizeof(struct bge_tx_bd)); 156895d67482SBill Paul } 156995d67482SBill Paul } 157095d67482SBill Paul 157195d67482SBill Paul static int 15723f74909aSGleb Smirnoff bge_init_tx_ring(struct bge_softc *sc) 157395d67482SBill Paul { 157495d67482SBill Paul sc->bge_txcnt = 0; 157595d67482SBill Paul sc->bge_tx_saved_considx = 0; 15763927098fSPaul Saab 1577e6bf277eSPyun YongHyeon bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1578e6bf277eSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 15795c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1580e6bf277eSPyun YongHyeon 158114bbd30fSGleb Smirnoff /* Initialize transmit producer index for host-memory send ring. */ 158214bbd30fSGleb Smirnoff sc->bge_tx_prodidx = 0; 158338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 158414bbd30fSGleb Smirnoff 15853927098fSPaul Saab /* 5700 b2 errata */ 1586e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 158738cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 15883927098fSPaul Saab 158914bbd30fSGleb Smirnoff /* NIC-memory send ring not used; initialize to zero. */ 159038cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 15913927098fSPaul Saab /* 5700 b2 errata */ 1592e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 159338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 159495d67482SBill Paul 159595d67482SBill Paul return (0); 159695d67482SBill Paul } 159795d67482SBill Paul 159895d67482SBill Paul static void 15993e9b1bcaSJung-uk Kim bge_setpromisc(struct bge_softc *sc) 16003e9b1bcaSJung-uk Kim { 1601fba8b109SMarcel Moolenaar if_t ifp; 16023e9b1bcaSJung-uk Kim 16033e9b1bcaSJung-uk Kim BGE_LOCK_ASSERT(sc); 16043e9b1bcaSJung-uk Kim 16053e9b1bcaSJung-uk Kim ifp = sc->bge_ifp; 16063e9b1bcaSJung-uk Kim 160745ee6ab3SJung-uk Kim /* Enable or disable promiscuous mode as needed. */ 1608fba8b109SMarcel Moolenaar if (if_getflags(ifp) & IFF_PROMISC) 160945ee6ab3SJung-uk Kim BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 16103e9b1bcaSJung-uk Kim else 161145ee6ab3SJung-uk Kim BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 16123e9b1bcaSJung-uk Kim } 16133e9b1bcaSJung-uk Kim 16143e9b1bcaSJung-uk Kim static void 16153f74909aSGleb Smirnoff bge_setmulti(struct bge_softc *sc) 161695d67482SBill Paul { 1617fba8b109SMarcel Moolenaar if_t ifp; 1618fba8b109SMarcel Moolenaar int mc_count = 0; 16193f74909aSGleb Smirnoff uint32_t hashes[4] = { 0, 0, 0, 0 }; 1620fba8b109SMarcel Moolenaar int h, i, mcnt; 1621fba8b109SMarcel Moolenaar unsigned char *mta; 162295d67482SBill Paul 16230f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 16240f9bd73bSSam Leffler 1625fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 162695d67482SBill Paul 1627fba8b109SMarcel Moolenaar mc_count = if_multiaddr_count(ifp, -1); 1628fba8b109SMarcel Moolenaar mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * 1629fba8b109SMarcel Moolenaar mc_count, M_DEVBUF, M_NOWAIT); 1630fba8b109SMarcel Moolenaar 1631fba8b109SMarcel Moolenaar if(mta == NULL) { 1632fba8b109SMarcel Moolenaar device_printf(sc->bge_dev, 1633fba8b109SMarcel Moolenaar "Failed to allocated temp mcast list\n"); 1634fba8b109SMarcel Moolenaar return; 1635fba8b109SMarcel Moolenaar } 1636fba8b109SMarcel Moolenaar 1637fba8b109SMarcel Moolenaar if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 163895d67482SBill Paul for (i = 0; i < 4; i++) 16390c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 164095d67482SBill Paul return; 164195d67482SBill Paul } 164295d67482SBill Paul 164395d67482SBill Paul /* First, zot all the existing filters. */ 164495d67482SBill Paul for (i = 0; i < 4; i++) 164595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 164695d67482SBill Paul 1647fba8b109SMarcel Moolenaar if_multiaddr_array(ifp, mta, &mcnt, mc_count); 1648fba8b109SMarcel Moolenaar for(i = 0; i < mcnt; i++) { 1649a127e581SPeter Wemm h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 1650a127e581SPeter Wemm ETHER_ADDR_LEN) & 0x7F; 16510c8aa4eaSJung-uk Kim hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 165295d67482SBill Paul } 165395d67482SBill Paul 165495d67482SBill Paul for (i = 0; i < 4; i++) 165595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1656fba8b109SMarcel Moolenaar 1657fba8b109SMarcel Moolenaar free(mta, M_DEVBUF); 165895d67482SBill Paul } 165995d67482SBill Paul 16608cb1383cSDoug Ambrisko static void 1661cb2eacc7SYaroslav Tykhiy bge_setvlan(struct bge_softc *sc) 1662cb2eacc7SYaroslav Tykhiy { 1663fba8b109SMarcel Moolenaar if_t ifp; 1664cb2eacc7SYaroslav Tykhiy 1665cb2eacc7SYaroslav Tykhiy BGE_LOCK_ASSERT(sc); 1666cb2eacc7SYaroslav Tykhiy 1667cb2eacc7SYaroslav Tykhiy ifp = sc->bge_ifp; 1668cb2eacc7SYaroslav Tykhiy 1669cb2eacc7SYaroslav Tykhiy /* Enable or disable VLAN tag stripping as needed. */ 1670fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1671cb2eacc7SYaroslav Tykhiy BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1672cb2eacc7SYaroslav Tykhiy else 1673cb2eacc7SYaroslav Tykhiy BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1674cb2eacc7SYaroslav Tykhiy } 1675cb2eacc7SYaroslav Tykhiy 1676cb2eacc7SYaroslav Tykhiy static void 1677797ab05eSPyun YongHyeon bge_sig_pre_reset(struct bge_softc *sc, int type) 16788cb1383cSDoug Ambrisko { 1679797ab05eSPyun YongHyeon 16808cb1383cSDoug Ambrisko /* 16818cb1383cSDoug Ambrisko * Some chips don't like this so only do this if ASF is enabled 16828cb1383cSDoug Ambrisko */ 16838cb1383cSDoug Ambrisko if (sc->bge_asf_mode) 1684888b47f0SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 16858cb1383cSDoug Ambrisko 16868cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 16878cb1383cSDoug Ambrisko switch (type) { 16888cb1383cSDoug Ambrisko case BGE_RESET_START: 1689224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1690224f8785SPyun YongHyeon BGE_FW_DRV_STATE_START); 16918cb1383cSDoug Ambrisko break; 1692548c8f1aSPyun YongHyeon case BGE_RESET_SHUTDOWN: 1693224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1694224f8785SPyun YongHyeon BGE_FW_DRV_STATE_UNLOAD); 16958cb1383cSDoug Ambrisko break; 1696548c8f1aSPyun YongHyeon case BGE_RESET_SUSPEND: 1697548c8f1aSPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1698548c8f1aSPyun YongHyeon BGE_FW_DRV_STATE_SUSPEND); 1699548c8f1aSPyun YongHyeon break; 17008cb1383cSDoug Ambrisko } 17018cb1383cSDoug Ambrisko } 1702548c8f1aSPyun YongHyeon 1703548c8f1aSPyun YongHyeon if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1704548c8f1aSPyun YongHyeon bge_ape_driver_state_change(sc, type); 17058cb1383cSDoug Ambrisko } 17068cb1383cSDoug Ambrisko 17078cb1383cSDoug Ambrisko static void 1708797ab05eSPyun YongHyeon bge_sig_post_reset(struct bge_softc *sc, int type) 17098cb1383cSDoug Ambrisko { 1710797ab05eSPyun YongHyeon 17118cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 17128cb1383cSDoug Ambrisko switch (type) { 17138cb1383cSDoug Ambrisko case BGE_RESET_START: 1714224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1715224f8785SPyun YongHyeon BGE_FW_DRV_STATE_START_DONE); 17168cb1383cSDoug Ambrisko /* START DONE */ 17178cb1383cSDoug Ambrisko break; 1718548c8f1aSPyun YongHyeon case BGE_RESET_SHUTDOWN: 1719224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1720224f8785SPyun YongHyeon BGE_FW_DRV_STATE_UNLOAD_DONE); 17218cb1383cSDoug Ambrisko break; 17228cb1383cSDoug Ambrisko } 17238cb1383cSDoug Ambrisko } 1724548c8f1aSPyun YongHyeon if (type == BGE_RESET_SHUTDOWN) 1725548c8f1aSPyun YongHyeon bge_ape_driver_state_change(sc, type); 17268cb1383cSDoug Ambrisko } 17278cb1383cSDoug Ambrisko 17288cb1383cSDoug Ambrisko static void 1729797ab05eSPyun YongHyeon bge_sig_legacy(struct bge_softc *sc, int type) 17308cb1383cSDoug Ambrisko { 1731797ab05eSPyun YongHyeon 17328cb1383cSDoug Ambrisko if (sc->bge_asf_mode) { 17338cb1383cSDoug Ambrisko switch (type) { 17348cb1383cSDoug Ambrisko case BGE_RESET_START: 1735224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1736224f8785SPyun YongHyeon BGE_FW_DRV_STATE_START); 17378cb1383cSDoug Ambrisko break; 1738548c8f1aSPyun YongHyeon case BGE_RESET_SHUTDOWN: 1739224f8785SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1740224f8785SPyun YongHyeon BGE_FW_DRV_STATE_UNLOAD); 17418cb1383cSDoug Ambrisko break; 17428cb1383cSDoug Ambrisko } 17438cb1383cSDoug Ambrisko } 17448cb1383cSDoug Ambrisko } 17458cb1383cSDoug Ambrisko 1746797ab05eSPyun YongHyeon static void 1747797ab05eSPyun YongHyeon bge_stop_fw(struct bge_softc *sc) 17488cb1383cSDoug Ambrisko { 17498cb1383cSDoug Ambrisko int i; 17508cb1383cSDoug Ambrisko 17518cb1383cSDoug Ambrisko if (sc->bge_asf_mode) { 17523c201200SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 17533fed2d5dSPyun YongHyeon CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 17549931ba85SPyun YongHyeon CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 17558cb1383cSDoug Ambrisko 17568cb1383cSDoug Ambrisko for (i = 0; i < 100; i++ ) { 17579931ba85SPyun YongHyeon if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 17589931ba85SPyun YongHyeon BGE_RX_CPU_DRV_EVENT)) 17598cb1383cSDoug Ambrisko break; 17608cb1383cSDoug Ambrisko DELAY(10); 17618cb1383cSDoug Ambrisko } 17628cb1383cSDoug Ambrisko } 17638cb1383cSDoug Ambrisko } 17648cb1383cSDoug Ambrisko 176550515680SPyun YongHyeon static uint32_t 176650515680SPyun YongHyeon bge_dma_swap_options(struct bge_softc *sc) 176750515680SPyun YongHyeon { 176850515680SPyun YongHyeon uint32_t dma_options; 176950515680SPyun YongHyeon 177050515680SPyun YongHyeon dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 177150515680SPyun YongHyeon BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 177250515680SPyun YongHyeon #if BYTE_ORDER == BIG_ENDIAN 177350515680SPyun YongHyeon dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 177450515680SPyun YongHyeon #endif 177550515680SPyun YongHyeon return (dma_options); 177650515680SPyun YongHyeon } 177750515680SPyun YongHyeon 177895d67482SBill Paul /* 1779c9ffd9f0SMarius Strobl * Do endian, PCI and DMA initialization. 178095d67482SBill Paul */ 178195d67482SBill Paul static int 17823f74909aSGleb Smirnoff bge_chipinit(struct bge_softc *sc) 178395d67482SBill Paul { 178450515680SPyun YongHyeon uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1785fbc374afSPyun YongHyeon uint16_t val; 178695d67482SBill Paul int i; 178795d67482SBill Paul 17888cb1383cSDoug Ambrisko /* Set endianness before we access any non-PCI registers. */ 17891108273aSPyun YongHyeon misc_ctl = BGE_INIT; 17901108273aSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 17911108273aSPyun YongHyeon misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 17921108273aSPyun YongHyeon pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 179395d67482SBill Paul 179495d67482SBill Paul /* 179595d67482SBill Paul * Clear the MAC statistics block in the NIC's 179695d67482SBill Paul * internal memory. 179795d67482SBill Paul */ 179895d67482SBill Paul for (i = BGE_STATS_BLOCK; 17993f74909aSGleb Smirnoff i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 180095d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 180195d67482SBill Paul 180295d67482SBill Paul for (i = BGE_STATUS_BLOCK; 18033f74909aSGleb Smirnoff i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 180495d67482SBill Paul BGE_MEMWIN_WRITE(sc, i, 0); 180595d67482SBill Paul 1806fbc374afSPyun YongHyeon if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1807fbc374afSPyun YongHyeon /* 1808d896b3feSPyun YongHyeon * Fix data corruption caused by non-qword write with WB. 1809fbc374afSPyun YongHyeon * Fix master abort in PCI mode. 1810fbc374afSPyun YongHyeon * Fix PCI latency timer. 1811fbc374afSPyun YongHyeon */ 1812fbc374afSPyun YongHyeon val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1813fbc374afSPyun YongHyeon val |= (1 << 10) | (1 << 12) | (1 << 13); 1814fbc374afSPyun YongHyeon pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1815fbc374afSPyun YongHyeon } 1816fbc374afSPyun YongHyeon 1817f8bb33c3SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1818f8bb33c3SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1819f8bb33c3SPyun YongHyeon /* 1820f8bb33c3SPyun YongHyeon * For the 57766 and non Ax versions of 57765, bootcode 1821f8bb33c3SPyun YongHyeon * needs to setup the PCIE Fast Training Sequence (FTS) 1822f8bb33c3SPyun YongHyeon * value to prevent transmit hangs. 1823f8bb33c3SPyun YongHyeon */ 1824f8bb33c3SPyun YongHyeon if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1825f8bb33c3SPyun YongHyeon CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1826f8bb33c3SPyun YongHyeon CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1827f8bb33c3SPyun YongHyeon BGE_CPMU_PADRNG_CTL_RDIV2); 1828f8bb33c3SPyun YongHyeon } 1829f8bb33c3SPyun YongHyeon } 1830f8bb33c3SPyun YongHyeon 1831186f842bSJung-uk Kim /* 1832186f842bSJung-uk Kim * Set up the PCI DMA control register. 1833186f842bSJung-uk Kim */ 1834186f842bSJung-uk Kim dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1835186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1836652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 183748630d79SPyun YongHyeon if (sc->bge_mps >= 256) 183848630d79SPyun YongHyeon dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 183948630d79SPyun YongHyeon else 1840186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1841652ae483SGleb Smirnoff } else if (sc->bge_flags & BGE_FLAG_PCIX) { 18424c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 1843186f842bSJung-uk Kim /* 256 bytes for read and write. */ 1844186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1845186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1846186f842bSJung-uk Kim dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1847186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1848186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1849cbb2b2feSPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1850cbb2b2feSPyun YongHyeon /* 1851cbb2b2feSPyun YongHyeon * In the BCM5703, the DMA read watermark should 1852cbb2b2feSPyun YongHyeon * be set to less than or equal to the maximum 1853cbb2b2feSPyun YongHyeon * memory read byte count of the PCI-X command 1854cbb2b2feSPyun YongHyeon * register. 1855cbb2b2feSPyun YongHyeon */ 1856cbb2b2feSPyun YongHyeon dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1857cbb2b2feSPyun YongHyeon BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1858186f842bSJung-uk Kim } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1859186f842bSJung-uk Kim /* 1536 bytes for read, 384 bytes for write. */ 1860186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1861186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1862186f842bSJung-uk Kim } else { 1863186f842bSJung-uk Kim /* 384 bytes for read and write. */ 1864186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1865186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 18660c8aa4eaSJung-uk Kim 0x0F; 1867186f842bSJung-uk Kim } 1868e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1869e0ced696SPaul Saab sc->bge_asicrev == BGE_ASICREV_BCM5704) { 18703f74909aSGleb Smirnoff uint32_t tmp; 18715cba12d3SPaul Saab 1872186f842bSJung-uk Kim /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 18730c8aa4eaSJung-uk Kim tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1874186f842bSJung-uk Kim if (tmp == 6 || tmp == 7) 1875186f842bSJung-uk Kim dma_rw_ctl |= 1876186f842bSJung-uk Kim BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 18775cba12d3SPaul Saab 1878186f842bSJung-uk Kim /* Set PCI-X DMA write workaround. */ 1879186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1880186f842bSJung-uk Kim } 1881186f842bSJung-uk Kim } else { 1882186f842bSJung-uk Kim /* Conventional PCI bus: 256 bytes for read and write. */ 1883186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1884186f842bSJung-uk Kim BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1885186f842bSJung-uk Kim 1886186f842bSJung-uk Kim if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1887186f842bSJung-uk Kim sc->bge_asicrev != BGE_ASICREV_BCM5750) 1888186f842bSJung-uk Kim dma_rw_ctl |= 0x0F; 1889186f842bSJung-uk Kim } 1890186f842bSJung-uk Kim if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1891186f842bSJung-uk Kim sc->bge_asicrev == BGE_ASICREV_BCM5701) 1892186f842bSJung-uk Kim dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1893186f842bSJung-uk Kim BGE_PCIDMARWCTL_ASRT_ALL_BE; 1894e0ced696SPaul Saab if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1895186f842bSJung-uk Kim sc->bge_asicrev == BGE_ASICREV_BCM5704) 18965cba12d3SPaul Saab dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1897b4a256acSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 18981108273aSPyun YongHyeon dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1899b4a256acSPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1900b4a256acSPyun YongHyeon dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1901bbe2ca75SPyun YongHyeon /* 1902bbe2ca75SPyun YongHyeon * Enable HW workaround for controllers that misinterpret 1903bbe2ca75SPyun YongHyeon * a status tag update and leave interrupts permanently 1904bbe2ca75SPyun YongHyeon * disabled. 1905bbe2ca75SPyun YongHyeon */ 19062927f01fSPyun YongHyeon if (!BGE_IS_57765_PLUS(sc) && 19072927f01fSPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5717 && 19082927f01fSPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5762) 1909bbe2ca75SPyun YongHyeon dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1910b4a256acSPyun YongHyeon } 19115cba12d3SPaul Saab pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 191295d67482SBill Paul 191395d67482SBill Paul /* 191495d67482SBill Paul * Set up general mode register. 191595d67482SBill Paul */ 1916548c8f1aSPyun YongHyeon mode_ctl = bge_dma_swap_options(sc); 19172927f01fSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 19182927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1919548c8f1aSPyun YongHyeon /* Retain Host-2-BMC settings written by APE firmware. */ 1920548c8f1aSPyun YongHyeon mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1921548c8f1aSPyun YongHyeon (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1922548c8f1aSPyun YongHyeon BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1923548c8f1aSPyun YongHyeon BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1924548c8f1aSPyun YongHyeon } 1925548c8f1aSPyun YongHyeon mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1926548c8f1aSPyun YongHyeon BGE_MODECTL_TX_NO_PHDR_CSUM; 192795d67482SBill Paul 192895d67482SBill Paul /* 192990447aadSMarius Strobl * BCM5701 B5 have a bug causing data corruption when using 193090447aadSMarius Strobl * 64-bit DMA reads, which can be terminated early and then 193190447aadSMarius Strobl * completed later as 32-bit accesses, in combination with 193290447aadSMarius Strobl * certain bridges. 193390447aadSMarius Strobl */ 193490447aadSMarius Strobl if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 193590447aadSMarius Strobl sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 193650515680SPyun YongHyeon mode_ctl |= BGE_MODECTL_FORCE_PCI32; 193790447aadSMarius Strobl 193890447aadSMarius Strobl /* 19398cb1383cSDoug Ambrisko * Tell the firmware the driver is running 19408cb1383cSDoug Ambrisko */ 19418cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 194250515680SPyun YongHyeon mode_ctl |= BGE_MODECTL_STACKUP; 194350515680SPyun YongHyeon 194450515680SPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 19458cb1383cSDoug Ambrisko 19468cb1383cSDoug Ambrisko /* 1947ea13bdd5SJohn Polstra * Disable memory write invalidate. Apparently it is not supported 1948c9ffd9f0SMarius Strobl * properly by these devices. Also ensure that INTx isn't disabled, 1949c9ffd9f0SMarius Strobl * as these chips need it even when using MSI. 195095d67482SBill Paul */ 1951c9ffd9f0SMarius Strobl PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1952c9ffd9f0SMarius Strobl PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 195395d67482SBill Paul 1954d7acafa1SMarius Strobl /* Set the timer prescaler (always 66 MHz). */ 19550c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 195695d67482SBill Paul 195738cc658fSJohn Baldwin /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 195838cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 195938cc658fSJohn Baldwin DELAY(40); /* XXX */ 196038cc658fSJohn Baldwin 196138cc658fSJohn Baldwin /* Put PHY into ready state */ 196238cc658fSJohn Baldwin BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 196338cc658fSJohn Baldwin CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 196438cc658fSJohn Baldwin DELAY(40); 196538cc658fSJohn Baldwin } 196638cc658fSJohn Baldwin 196795d67482SBill Paul return (0); 196895d67482SBill Paul } 196995d67482SBill Paul 197095d67482SBill Paul static int 19713f74909aSGleb Smirnoff bge_blockinit(struct bge_softc *sc) 197295d67482SBill Paul { 197395d67482SBill Paul struct bge_rcb *rcb; 1974e907febfSPyun YongHyeon bus_size_t vrcb; 1975e907febfSPyun YongHyeon bge_hostaddr taddr; 19762927f01fSPyun YongHyeon uint32_t dmactl, rdmareg, val; 19778a315a6dSPyun YongHyeon int i, limit; 197895d67482SBill Paul 197995d67482SBill Paul /* 198095d67482SBill Paul * Initialize the memory window pointer register so that 198195d67482SBill Paul * we can access the first 32K of internal NIC RAM. This will 198295d67482SBill Paul * allow us to set up the TX send ring RCBs and the RX return 198395d67482SBill Paul * ring RCBs, plus other things which live in NIC memory. 198495d67482SBill Paul */ 198595d67482SBill Paul CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 198695d67482SBill Paul 1987822f63fcSBill Paul /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1988822f63fcSBill Paul 19897ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 199095d67482SBill Paul /* Configure mbuf memory pool */ 19910dae9719SJung-uk Kim CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1992822f63fcSBill Paul if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1993822f63fcSBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1994822f63fcSBill Paul else 199595d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 199695d67482SBill Paul 199795d67482SBill Paul /* Configure DMA resource pool */ 19980434d1b8SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 19990434d1b8SBill Paul BGE_DMA_DESCRIPTORS); 200095d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 20010434d1b8SBill Paul } 200295d67482SBill Paul 200395d67482SBill Paul /* Configure mbuf pool watermarks */ 200450515680SPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 20051108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2006fba8b109SMarcel Moolenaar if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 20071108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 20081108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 20091108273aSPyun YongHyeon } else { 20101108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 20111108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 20121108273aSPyun YongHyeon } 20131108273aSPyun YongHyeon } else if (!BGE_IS_5705_PLUS(sc)) { 2014fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2015fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2016fa228020SPaul Saab CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 201738cc658fSJohn Baldwin } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 201838cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 201938cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 202038cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 202138cc658fSJohn Baldwin } else { 202238cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 202338cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 202438cc658fSJohn Baldwin CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 202538cc658fSJohn Baldwin } 202695d67482SBill Paul 202795d67482SBill Paul /* Configure DMA resource watermarks */ 202895d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 202995d67482SBill Paul CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 203095d67482SBill Paul 203195d67482SBill Paul /* Enable buffer manager */ 2032bbe2ca75SPyun YongHyeon val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2033bbe2ca75SPyun YongHyeon /* 2034bbe2ca75SPyun YongHyeon * Change the arbitration algorithm of TXMBUF read request to 2035bbe2ca75SPyun YongHyeon * round-robin instead of priority based for BCM5719. When 2036bbe2ca75SPyun YongHyeon * TXFIFO is almost empty, RDMA will hold its request until 2037bbe2ca75SPyun YongHyeon * TXFIFO is not almost empty. 2038bbe2ca75SPyun YongHyeon */ 2039bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2040bbe2ca75SPyun YongHyeon val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2041bbe2ca75SPyun YongHyeon CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 204295d67482SBill Paul 204395d67482SBill Paul /* Poll for buffer manager start indication */ 204495d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 2045d5d23857SJung-uk Kim DELAY(10); 20460c8aa4eaSJung-uk Kim if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 204795d67482SBill Paul break; 204895d67482SBill Paul } 204995d67482SBill Paul 205095d67482SBill Paul if (i == BGE_TIMEOUT) { 20515a147ba6SPyun YongHyeon device_printf(sc->bge_dev, "buffer manager failed to start\n"); 205295d67482SBill Paul return (ENXIO); 205395d67482SBill Paul } 205495d67482SBill Paul 205595d67482SBill Paul /* Enable flow-through queues */ 20560c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 205795d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 205895d67482SBill Paul 205995d67482SBill Paul /* Wait until queue initialization is complete */ 206095d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 2061d5d23857SJung-uk Kim DELAY(10); 206295d67482SBill Paul if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 206395d67482SBill Paul break; 206495d67482SBill Paul } 206595d67482SBill Paul 206695d67482SBill Paul if (i == BGE_TIMEOUT) { 2067fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "flow-through queue init failed\n"); 206895d67482SBill Paul return (ENXIO); 206995d67482SBill Paul } 207095d67482SBill Paul 20718a315a6dSPyun YongHyeon /* 20728a315a6dSPyun YongHyeon * Summary of rings supported by the controller: 20738a315a6dSPyun YongHyeon * 20748a315a6dSPyun YongHyeon * Standard Receive Producer Ring 20758a315a6dSPyun YongHyeon * - This ring is used to feed receive buffers for "standard" 20768a315a6dSPyun YongHyeon * sized frames (typically 1536 bytes) to the controller. 20778a315a6dSPyun YongHyeon * 20788a315a6dSPyun YongHyeon * Jumbo Receive Producer Ring 20798a315a6dSPyun YongHyeon * - This ring is used to feed receive buffers for jumbo sized 20808a315a6dSPyun YongHyeon * frames (i.e. anything bigger than the "standard" frames) 20818a315a6dSPyun YongHyeon * to the controller. 20828a315a6dSPyun YongHyeon * 20838a315a6dSPyun YongHyeon * Mini Receive Producer Ring 20848a315a6dSPyun YongHyeon * - This ring is used to feed receive buffers for "mini" 20858a315a6dSPyun YongHyeon * sized frames to the controller. 20868a315a6dSPyun YongHyeon * - This feature required external memory for the controller 20878a315a6dSPyun YongHyeon * but was never used in a production system. Should always 20888a315a6dSPyun YongHyeon * be disabled. 20898a315a6dSPyun YongHyeon * 20908a315a6dSPyun YongHyeon * Receive Return Ring 20918a315a6dSPyun YongHyeon * - After the controller has placed an incoming frame into a 20928a315a6dSPyun YongHyeon * receive buffer that buffer is moved into a receive return 20938a315a6dSPyun YongHyeon * ring. The driver is then responsible to passing the 20948a315a6dSPyun YongHyeon * buffer up to the stack. Many versions of the controller 20958a315a6dSPyun YongHyeon * support multiple RR rings. 20968a315a6dSPyun YongHyeon * 20978a315a6dSPyun YongHyeon * Send Ring 20988a315a6dSPyun YongHyeon * - This ring is used for outgoing frames. Many versions of 20998a315a6dSPyun YongHyeon * the controller support multiple send rings. 21008a315a6dSPyun YongHyeon */ 21018a315a6dSPyun YongHyeon 21028a315a6dSPyun YongHyeon /* Initialize the standard receive producer ring control block. */ 2103f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2104f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 2105f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2106f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 2107f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2108f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2109f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 21101108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 21111108273aSPyun YongHyeon /* 21121108273aSPyun YongHyeon * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 21131108273aSPyun YongHyeon * Bits 15-2 : Maximum RX frame size 21141108273aSPyun YongHyeon * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 21151108273aSPyun YongHyeon * Bit 0 : Reserved 21161108273aSPyun YongHyeon */ 21171108273aSPyun YongHyeon rcb->bge_maxlen_flags = 21181108273aSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 21191108273aSPyun YongHyeon } else if (BGE_IS_5705_PLUS(sc)) { 21208a315a6dSPyun YongHyeon /* 21218a315a6dSPyun YongHyeon * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 21228a315a6dSPyun YongHyeon * Bits 15-2 : Reserved (should be 0) 21238a315a6dSPyun YongHyeon * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 21248a315a6dSPyun YongHyeon * Bit 0 : Reserved 21258a315a6dSPyun YongHyeon */ 21260434d1b8SBill Paul rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 21278a315a6dSPyun YongHyeon } else { 21288a315a6dSPyun YongHyeon /* 21298a315a6dSPyun YongHyeon * Ring size is always XXX entries 21308a315a6dSPyun YongHyeon * Bits 31-16: Maximum RX frame size 21318a315a6dSPyun YongHyeon * Bits 15-2 : Reserved (should be 0) 21328a315a6dSPyun YongHyeon * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 21338a315a6dSPyun YongHyeon * Bit 0 : Reserved 21348a315a6dSPyun YongHyeon */ 21350434d1b8SBill Paul rcb->bge_maxlen_flags = 21360434d1b8SBill Paul BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 21378a315a6dSPyun YongHyeon } 2138bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 213950515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5719 || 214050515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) 21411108273aSPyun YongHyeon rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 21421108273aSPyun YongHyeon else 214395d67482SBill Paul rcb->bge_nicaddr = BGE_STD_RX_RINGS; 21448a315a6dSPyun YongHyeon /* Write the standard receive producer ring control block. */ 21450c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 21460c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 214767111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 214867111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 214995d67482SBill Paul 21508a315a6dSPyun YongHyeon /* Reset the standard receive producer ring producer index. */ 21518a315a6dSPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 21528a315a6dSPyun YongHyeon 215395d67482SBill Paul /* 21548a315a6dSPyun YongHyeon * Initialize the jumbo RX producer ring control 21558a315a6dSPyun YongHyeon * block. We set the 'ring disabled' bit in the 21568a315a6dSPyun YongHyeon * flags field until we're actually ready to start 215795d67482SBill Paul * using this ring (i.e. once we set the MTU 215895d67482SBill Paul * high enough to require it). 215995d67482SBill Paul */ 21604c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 2161f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 21628a315a6dSPyun YongHyeon /* Get the jumbo receive producer ring RCB parameters. */ 2163f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_lo = 2164f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2165f41ac2beSBill Paul rcb->bge_hostaddr.bge_addr_hi = 2166f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2167f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2168f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map, 2169f41ac2beSBill Paul BUS_DMASYNC_PREREAD); 21701be6acb7SGleb Smirnoff rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 21711be6acb7SGleb Smirnoff BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2172bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 217350515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5719 || 217450515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) 21751108273aSPyun YongHyeon rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 21761108273aSPyun YongHyeon else 217795d67482SBill Paul rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 217867111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 217967111612SJohn Polstra rcb->bge_hostaddr.bge_addr_hi); 218067111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 218167111612SJohn Polstra rcb->bge_hostaddr.bge_addr_lo); 21828a315a6dSPyun YongHyeon /* Program the jumbo receive producer ring RCB parameters. */ 21830434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 21840434d1b8SBill Paul rcb->bge_maxlen_flags); 218567111612SJohn Polstra CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 21868a315a6dSPyun YongHyeon /* Reset the jumbo receive producer ring producer index. */ 21878a315a6dSPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 21888a315a6dSPyun YongHyeon } 218995d67482SBill Paul 21908a315a6dSPyun YongHyeon /* Disable the mini receive producer ring RCB. */ 21915e2f96bfSPyun YongHyeon if (BGE_IS_5700_FAMILY(sc)) { 2192f41ac2beSBill Paul rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 219367111612SJohn Polstra rcb->bge_maxlen_flags = 219467111612SJohn Polstra BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 21950434d1b8SBill Paul CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 21960434d1b8SBill Paul rcb->bge_maxlen_flags); 21978a315a6dSPyun YongHyeon /* Reset the mini receive producer ring producer index. */ 21988a315a6dSPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 21990434d1b8SBill Paul } 220095d67482SBill Paul 2201ca4f8986SPyun YongHyeon /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2202ca4f8986SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2203427d3f33SPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2204427d3f33SPyun YongHyeon sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2205427d3f33SPyun YongHyeon sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 22068d5f7181SPyun YongHyeon CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 22078d5f7181SPyun YongHyeon (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2208ca4f8986SPyun YongHyeon } 220995d67482SBill Paul /* 22108a315a6dSPyun YongHyeon * The BD ring replenish thresholds control how often the 22118a315a6dSPyun YongHyeon * hardware fetches new BD's from the producer rings in host 22128a315a6dSPyun YongHyeon * memory. Setting the value too low on a busy system can 22138a315a6dSPyun YongHyeon * starve the hardware and recue the throughpout. 22148a315a6dSPyun YongHyeon * 221595d67482SBill Paul * Set the BD ring replentish thresholds. The recommended 221695d67482SBill Paul * values are 1/8th the number of descriptors allocated to 221795d67482SBill Paul * each ring. 22189ba784dbSScott Long * XXX The 5754 requires a lower threshold, so it might be a 22199ba784dbSScott Long * requirement of all 575x family chips. The Linux driver sets 22209ba784dbSScott Long * the lower threshold for all 5705 family chips as well, but there 22219ba784dbSScott Long * are reports that it might not need to be so strict. 222238cc658fSJohn Baldwin * 222338cc658fSJohn Baldwin * XXX Linux does some extra fiddling here for the 5906 parts as 222438cc658fSJohn Baldwin * well. 222595d67482SBill Paul */ 22265345bad0SScott Long if (BGE_IS_5705_PLUS(sc)) 22276f8718a3SScott Long val = 8; 22286f8718a3SScott Long else 22296f8718a3SScott Long val = BGE_STD_RX_RING_CNT / 8; 22306f8718a3SScott Long CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 22312a141b94SPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc)) 22322a141b94SPyun YongHyeon CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 22332a141b94SPyun YongHyeon BGE_JUMBO_RX_RING_CNT/8); 22341108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 22351108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 22361108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 22371108273aSPyun YongHyeon } 223895d67482SBill Paul 223995d67482SBill Paul /* 22408a315a6dSPyun YongHyeon * Disable all send rings by setting the 'ring disabled' bit 22418a315a6dSPyun YongHyeon * in the flags field of all the TX send ring control blocks, 22428a315a6dSPyun YongHyeon * located in NIC memory. 224395d67482SBill Paul */ 22448a315a6dSPyun YongHyeon if (!BGE_IS_5705_PLUS(sc)) 22458a315a6dSPyun YongHyeon /* 5700 to 5704 had 16 send rings. */ 22468a315a6dSPyun YongHyeon limit = BGE_TX_RINGS_EXTSSRAM_MAX; 22472927f01fSPyun YongHyeon else if (BGE_IS_57765_PLUS(sc) || 22482927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) 22492927f01fSPyun YongHyeon limit = 2; 22502927f01fSPyun YongHyeon else if (BGE_IS_5717_PLUS(sc)) 22512927f01fSPyun YongHyeon limit = 4; 22528a315a6dSPyun YongHyeon else 22538a315a6dSPyun YongHyeon limit = 1; 2254e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 22558a315a6dSPyun YongHyeon for (i = 0; i < limit; i++) { 2256e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2257e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2258e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2259e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 226095d67482SBill Paul } 226195d67482SBill Paul 22628a315a6dSPyun YongHyeon /* Configure send ring RCB 0 (we use only the first ring) */ 2263e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2264e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2265e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2266e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2267bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 226850515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5719 || 226950515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) 22701108273aSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 22711108273aSPyun YongHyeon else 2272e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2273e907febfSPyun YongHyeon BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2274e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2275e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 227695d67482SBill Paul 22778a315a6dSPyun YongHyeon /* 22788a315a6dSPyun YongHyeon * Disable all receive return rings by setting the 22798a315a6dSPyun YongHyeon * 'ring diabled' bit in the flags field of all the receive 22808a315a6dSPyun YongHyeon * return ring control blocks, located in NIC memory. 22818a315a6dSPyun YongHyeon */ 2282bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 228350515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5719 || 228450515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) { 22851108273aSPyun YongHyeon /* Should be 17, use 16 until we get an SRAM map. */ 22861108273aSPyun YongHyeon limit = 16; 22871108273aSPyun YongHyeon } else if (!BGE_IS_5705_PLUS(sc)) 22888a315a6dSPyun YongHyeon limit = BGE_RX_RINGS_MAX; 2289b4a256acSPyun YongHyeon else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 22902927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2291fe26ad88SPyun YongHyeon BGE_IS_57765_PLUS(sc)) 22928a315a6dSPyun YongHyeon limit = 4; 22938a315a6dSPyun YongHyeon else 22948a315a6dSPyun YongHyeon limit = 1; 22958a315a6dSPyun YongHyeon /* Disable all receive return rings. */ 2296e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 22978a315a6dSPyun YongHyeon for (i = 0; i < limit; i++) { 2298e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2299e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2300e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 23018a315a6dSPyun YongHyeon BGE_RCB_FLAG_RING_DISABLED); 2302e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 230338cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 23043f74909aSGleb Smirnoff (i * (sizeof(uint64_t))), 0); 2305e907febfSPyun YongHyeon vrcb += sizeof(struct bge_rcb); 230695d67482SBill Paul } 230795d67482SBill Paul 230895d67482SBill Paul /* 23098a315a6dSPyun YongHyeon * Set up receive return ring 0. Note that the NIC address 23108a315a6dSPyun YongHyeon * for RX return rings is 0x0. The return rings live entirely 23118a315a6dSPyun YongHyeon * within the host, so the nicaddr field in the RCB isn't used. 231295d67482SBill Paul */ 2313e907febfSPyun YongHyeon vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2314e907febfSPyun YongHyeon BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2315e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2316e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 23178a315a6dSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2318e907febfSPyun YongHyeon RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2319e907febfSPyun YongHyeon BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 232095d67482SBill Paul 232195d67482SBill Paul /* Set random backoff seed for TX */ 232295d67482SBill Paul CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 23230a2cc827SPyun YongHyeon (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 23244a0d6638SRuslan Ermilov IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 23250a2cc827SPyun YongHyeon IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 232695d67482SBill Paul BGE_TX_BACKOFF_SEED_MASK); 232795d67482SBill Paul 232895d67482SBill Paul /* Set inter-packet gap */ 232950515680SPyun YongHyeon val = 0x2620; 23302927f01fSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 23312927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) 233250515680SPyun YongHyeon val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 233350515680SPyun YongHyeon (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 233450515680SPyun YongHyeon CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 233595d67482SBill Paul 233695d67482SBill Paul /* 233795d67482SBill Paul * Specify which ring to use for packets that don't match 233895d67482SBill Paul * any RX rules. 233995d67482SBill Paul */ 234095d67482SBill Paul CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 234195d67482SBill Paul 234295d67482SBill Paul /* 234395d67482SBill Paul * Configure number of RX lists. One interrupt distribution 234495d67482SBill Paul * list, sixteen active lists, one bad frames class. 234595d67482SBill Paul */ 234695d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 234795d67482SBill Paul 234895d67482SBill Paul /* Inialize RX list placement stats mask. */ 23490c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 235095d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 235195d67482SBill Paul 235295d67482SBill Paul /* Disable host coalescing until we get it set up */ 235395d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 235495d67482SBill Paul 235595d67482SBill Paul /* Poll to make sure it's shut down. */ 235695d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 2357d5d23857SJung-uk Kim DELAY(10); 235895d67482SBill Paul if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 235995d67482SBill Paul break; 236095d67482SBill Paul } 236195d67482SBill Paul 236295d67482SBill Paul if (i == BGE_TIMEOUT) { 2363fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2364fe806fdaSPyun YongHyeon "host coalescing engine failed to idle\n"); 236595d67482SBill Paul return (ENXIO); 236695d67482SBill Paul } 236795d67482SBill Paul 236895d67482SBill Paul /* Set up host coalescing defaults */ 236995d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 237095d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 237195d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 237295d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 23737ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 237495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 237595d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 23760434d1b8SBill Paul } 2377b64728e5SBruce Evans CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2378b64728e5SBruce Evans CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 237995d67482SBill Paul 238095d67482SBill Paul /* Set up address of statistics block */ 23817ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 2382f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2383f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 238495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2385f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 23860434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 238795d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 23880434d1b8SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 23890434d1b8SBill Paul } 23900434d1b8SBill Paul 23910434d1b8SBill Paul /* Set up address of status block */ 2392f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2393f41ac2beSBill Paul BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 239495d67482SBill Paul CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2395f41ac2beSBill Paul BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 239695d67482SBill Paul 239730f57f61SPyun YongHyeon /* Set up status block size. */ 239830f57f61SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2399864104feSPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 240030f57f61SPyun YongHyeon val = BGE_STATBLKSZ_FULL; 2401864104feSPyun YongHyeon bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2402864104feSPyun YongHyeon } else { 240330f57f61SPyun YongHyeon val = BGE_STATBLKSZ_32BYTE; 2404864104feSPyun YongHyeon bzero(sc->bge_ldata.bge_status_block, 32); 2405864104feSPyun YongHyeon } 2406864104feSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2407864104feSPyun YongHyeon sc->bge_cdata.bge_status_map, 2408864104feSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 240930f57f61SPyun YongHyeon 241095d67482SBill Paul /* Turn on host coalescing state machine */ 241130f57f61SPyun YongHyeon CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 241295d67482SBill Paul 241395d67482SBill Paul /* Turn on RX BD completion state machine and enable attentions */ 241495d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDC_MODE, 241595d67482SBill Paul BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 241695d67482SBill Paul 241795d67482SBill Paul /* Turn on RX list placement state machine */ 241895d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 241995d67482SBill Paul 242095d67482SBill Paul /* Turn on RX list selector state machine. */ 24217ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 242295d67482SBill Paul CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 242395d67482SBill Paul 24242246e8c6SPyun YongHyeon /* Turn on DMA, clear stats. */ 2425ea3b4127SPyun YongHyeon val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2426ea3b4127SPyun YongHyeon BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2427ea3b4127SPyun YongHyeon BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2428ea3b4127SPyun YongHyeon BGE_MACMODE_FRMHDR_DMA_ENB; 2429ea3b4127SPyun YongHyeon 2430ea3b4127SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TBI) 2431ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_TBI; 2432ea3b4127SPyun YongHyeon else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2433ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_GMII; 2434ea3b4127SPyun YongHyeon else 2435ea3b4127SPyun YongHyeon val |= BGE_PORTMODE_MII; 2436ea3b4127SPyun YongHyeon 2437548c8f1aSPyun YongHyeon /* Allow APE to send/receive frames. */ 2438548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2439548c8f1aSPyun YongHyeon val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2440548c8f1aSPyun YongHyeon 2441ea3b4127SPyun YongHyeon CSR_WRITE_4(sc, BGE_MAC_MODE, val); 24429b80ffe7SPyun YongHyeon DELAY(40); 244395d67482SBill Paul 244495d67482SBill Paul /* Set misc. local control, enable interrupts on attentions */ 244591bd90d8SPyun YongHyeon BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 244695d67482SBill Paul 244795d67482SBill Paul #ifdef notdef 244895d67482SBill Paul /* Assert GPIO pins for PHY reset */ 244995d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 245095d67482SBill Paul BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 245195d67482SBill Paul BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 245295d67482SBill Paul BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 245395d67482SBill Paul #endif 245495d67482SBill Paul 245595d67482SBill Paul /* Turn on DMA completion state machine */ 24567ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 245795d67482SBill Paul CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 245895d67482SBill Paul 24596f8718a3SScott Long val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 24606f8718a3SScott Long 24616f8718a3SScott Long /* Enable host coalescing bug fix. */ 2462a5779553SStanislav Sedov if (BGE_IS_5755_PLUS(sc)) 24633889907fSStanislav Sedov val |= BGE_WDMAMODE_STATUS_TAG_FIX; 24646f8718a3SScott Long 24657aa4b937SPyun YongHyeon /* Request larger DMA burst size to get better performance. */ 24667aa4b937SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 24677aa4b937SPyun YongHyeon val |= BGE_WDMAMODE_BURST_ALL_DATA; 24687aa4b937SPyun YongHyeon 246995d67482SBill Paul /* Turn on write DMA state machine */ 24706f8718a3SScott Long CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 24714f09c4c7SMarius Strobl DELAY(40); 247295d67482SBill Paul 247395d67482SBill Paul /* Turn on read DMA state machine */ 24744f09c4c7SMarius Strobl val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 24751108273aSPyun YongHyeon 24761108273aSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 24771108273aSPyun YongHyeon val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 24781108273aSPyun YongHyeon 2479a5779553SStanislav Sedov if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2480a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2481a5779553SStanislav Sedov sc->bge_asicrev == BGE_ASICREV_BCM57780) 2482a5779553SStanislav Sedov val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2483a5779553SStanislav Sedov BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2484a5779553SStanislav Sedov BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 24854f09c4c7SMarius Strobl if (sc->bge_flags & BGE_FLAG_PCIE) 24864f09c4c7SMarius Strobl val |= BGE_RDMAMODE_FIFO_LONG_BURST; 24871108273aSPyun YongHyeon if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2488ca3f1187SPyun YongHyeon val |= BGE_RDMAMODE_TSO4_ENABLE; 24891108273aSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TSO3 || 24901108273aSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5785 || 249155a24a05SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM57780) 249255a24a05SPyun YongHyeon val |= BGE_RDMAMODE_TSO6_ENABLE; 249355a24a05SPyun YongHyeon } 249450515680SPyun YongHyeon 24952927f01fSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 24962927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) { 249750515680SPyun YongHyeon val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 249850515680SPyun YongHyeon BGE_RDMAMODE_H2BNC_VLAN_DET; 2499e3215f76SPyun YongHyeon /* 2500e3215f76SPyun YongHyeon * Allow multiple outstanding read requests from 2501e3215f76SPyun YongHyeon * non-LSO read DMA engine. 2502e3215f76SPyun YongHyeon */ 2503e3215f76SPyun YongHyeon val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2504e3215f76SPyun YongHyeon } 250550515680SPyun YongHyeon 2506d255f2a9SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2507d255f2a9SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2508d255f2a9SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5785 || 25091108273aSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM57780 || 25102927f01fSPyun YongHyeon BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 25112927f01fSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 25122927f01fSPyun YongHyeon rdmareg = BGE_RDMA_RSRVCTRL_REG2; 25132927f01fSPyun YongHyeon else 25142927f01fSPyun YongHyeon rdmareg = BGE_RDMA_RSRVCTRL; 25152927f01fSPyun YongHyeon dmactl = CSR_READ_4(sc, rdmareg); 2516bbe2ca75SPyun YongHyeon /* 2517bbe2ca75SPyun YongHyeon * Adjust tx margin to prevent TX data corruption and 2518bbe2ca75SPyun YongHyeon * fix internal FIFO overflow. 2519bbe2ca75SPyun YongHyeon */ 25202927f01fSPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 25212927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2522bbe2ca75SPyun YongHyeon dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2523bbe2ca75SPyun YongHyeon BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2524bbe2ca75SPyun YongHyeon BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2525bbe2ca75SPyun YongHyeon dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2526bbe2ca75SPyun YongHyeon BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2527bbe2ca75SPyun YongHyeon BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2528bbe2ca75SPyun YongHyeon } 2529d255f2a9SPyun YongHyeon /* 2530d255f2a9SPyun YongHyeon * Enable fix for read DMA FIFO overruns. 2531d255f2a9SPyun YongHyeon * The fix is to limit the number of RX BDs 2532d255f2a9SPyun YongHyeon * the hardware would fetch at a fime. 2533d255f2a9SPyun YongHyeon */ 25342927f01fSPyun YongHyeon CSR_WRITE_4(sc, rdmareg, dmactl | 2535d255f2a9SPyun YongHyeon BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2536d255f2a9SPyun YongHyeon } 2537bbe2ca75SPyun YongHyeon 2538e3215f76SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2539bbe2ca75SPyun YongHyeon CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2540bbe2ca75SPyun YongHyeon CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2541bbe2ca75SPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2542bbe2ca75SPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2543e3215f76SPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2544e3215f76SPyun YongHyeon /* 2545e3215f76SPyun YongHyeon * Allow 4KB burst length reads for non-LSO frames. 2546e3215f76SPyun YongHyeon * Enable 512B burst length reads for buffer descriptors. 2547e3215f76SPyun YongHyeon */ 2548e3215f76SPyun YongHyeon CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2549e3215f76SPyun YongHyeon CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2550e3215f76SPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2551e3215f76SPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 25522927f01fSPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 25532927f01fSPyun YongHyeon CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 25542927f01fSPyun YongHyeon CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 25552927f01fSPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 25562927f01fSPyun YongHyeon BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2557bbe2ca75SPyun YongHyeon } 2558bbe2ca75SPyun YongHyeon 25594f09c4c7SMarius Strobl CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 25604f09c4c7SMarius Strobl DELAY(40); 256195d67482SBill Paul 256229b44b09SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 256329b44b09SPyun YongHyeon for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 256429b44b09SPyun YongHyeon val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 256529b44b09SPyun YongHyeon if ((val & 0xFFFF) > BGE_FRAMELEN) 256629b44b09SPyun YongHyeon break; 256729b44b09SPyun YongHyeon if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 256829b44b09SPyun YongHyeon break; 256929b44b09SPyun YongHyeon } 257029b44b09SPyun YongHyeon if (i != BGE_NUM_RDMA_CHANNELS / 2) { 257129b44b09SPyun YongHyeon val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 257229b44b09SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 257329b44b09SPyun YongHyeon val |= BGE_RDMA_TX_LENGTH_WA_5719; 257429b44b09SPyun YongHyeon else 257529b44b09SPyun YongHyeon val |= BGE_RDMA_TX_LENGTH_WA_5720; 257629b44b09SPyun YongHyeon CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 257729b44b09SPyun YongHyeon } 257829b44b09SPyun YongHyeon } 257929b44b09SPyun YongHyeon 258095d67482SBill Paul /* Turn on RX data completion state machine */ 258195d67482SBill Paul CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 258295d67482SBill Paul 258395d67482SBill Paul /* Turn on RX BD initiator state machine */ 258495d67482SBill Paul CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 258595d67482SBill Paul 258695d67482SBill Paul /* Turn on RX data and RX BD initiator state machine */ 258795d67482SBill Paul CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 258895d67482SBill Paul 258995d67482SBill Paul /* Turn on Mbuf cluster free state machine */ 25907ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) 259195d67482SBill Paul CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 259295d67482SBill Paul 259395d67482SBill Paul /* Turn on send BD completion state machine */ 259495d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 259595d67482SBill Paul 259695d67482SBill Paul /* Turn on send data completion state machine */ 2597a5779553SStanislav Sedov val = BGE_SDCMODE_ENABLE; 2598a5779553SStanislav Sedov if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2599a5779553SStanislav Sedov val |= BGE_SDCMODE_CDELAY; 2600a5779553SStanislav Sedov CSR_WRITE_4(sc, BGE_SDC_MODE, val); 260195d67482SBill Paul 260295d67482SBill Paul /* Turn on send data initiator state machine */ 26031108273aSPyun YongHyeon if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 26041108273aSPyun YongHyeon CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 26051108273aSPyun YongHyeon BGE_SDIMODE_HW_LSO_PRE_DMA); 2606ca3f1187SPyun YongHyeon else 260795d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 260895d67482SBill Paul 260995d67482SBill Paul /* Turn on send BD initiator state machine */ 261095d67482SBill Paul CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 261195d67482SBill Paul 261295d67482SBill Paul /* Turn on send BD selector state machine */ 261395d67482SBill Paul CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 261495d67482SBill Paul 26150c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 261695d67482SBill Paul CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 261795d67482SBill Paul BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 261895d67482SBill Paul 261995d67482SBill Paul /* ack/clear link change events */ 262095d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 26210434d1b8SBill Paul BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 26220434d1b8SBill Paul BGE_MACSTAT_LINK_CHANGED); 2623f41ac2beSBill Paul CSR_WRITE_4(sc, BGE_MI_STS, 0); 262495d67482SBill Paul 26256ede2cfaSPyun YongHyeon /* 26266ede2cfaSPyun YongHyeon * Enable attention when the link has changed state for 26276ede2cfaSPyun YongHyeon * devices that use auto polling. 26286ede2cfaSPyun YongHyeon */ 2629652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 263095d67482SBill Paul CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2631a1d52896SBill Paul } else { 26327ed3f0f0SPyun YongHyeon if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 26337ed3f0f0SPyun YongHyeon CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 26347ed3f0f0SPyun YongHyeon DELAY(80); 26357ed3f0f0SPyun YongHyeon } 26361f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 26374c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2638a1d52896SBill Paul CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2639a1d52896SBill Paul BGE_EVTENB_MI_INTERRUPT); 2640a1d52896SBill Paul } 264195d67482SBill Paul 26421f313773SOleg Bulyzhin /* 26431f313773SOleg Bulyzhin * Clear any pending link state attention. 26441f313773SOleg Bulyzhin * Otherwise some link state change events may be lost until attention 26451f313773SOleg Bulyzhin * is cleared by bge_intr() -> bge_link_upd() sequence. 26461f313773SOleg Bulyzhin * It's not necessary on newer BCM chips - perhaps enabling link 26471f313773SOleg Bulyzhin * state change attentions implies clearing pending attention. 26481f313773SOleg Bulyzhin */ 26491f313773SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 26501f313773SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 26511f313773SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 26521f313773SOleg Bulyzhin 265395d67482SBill Paul /* Enable link state change attentions. */ 265495d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 265595d67482SBill Paul 265695d67482SBill Paul return (0); 265795d67482SBill Paul } 265895d67482SBill Paul 2659d7acafa1SMarius Strobl static const struct bge_revision * 26604c0da0ffSGleb Smirnoff bge_lookup_rev(uint32_t chipid) 26614c0da0ffSGleb Smirnoff { 26624c0da0ffSGleb Smirnoff const struct bge_revision *br; 26634c0da0ffSGleb Smirnoff 26644c0da0ffSGleb Smirnoff for (br = bge_revisions; br->br_name != NULL; br++) { 26654c0da0ffSGleb Smirnoff if (br->br_chipid == chipid) 26664c0da0ffSGleb Smirnoff return (br); 26674c0da0ffSGleb Smirnoff } 26684c0da0ffSGleb Smirnoff 26694c0da0ffSGleb Smirnoff for (br = bge_majorrevs; br->br_name != NULL; br++) { 26704c0da0ffSGleb Smirnoff if (br->br_chipid == BGE_ASICREV(chipid)) 26714c0da0ffSGleb Smirnoff return (br); 26724c0da0ffSGleb Smirnoff } 26734c0da0ffSGleb Smirnoff 26744c0da0ffSGleb Smirnoff return (NULL); 26754c0da0ffSGleb Smirnoff } 26764c0da0ffSGleb Smirnoff 2677d7acafa1SMarius Strobl static const struct bge_vendor * 26784c0da0ffSGleb Smirnoff bge_lookup_vendor(uint16_t vid) 26794c0da0ffSGleb Smirnoff { 26804c0da0ffSGleb Smirnoff const struct bge_vendor *v; 26814c0da0ffSGleb Smirnoff 26824c0da0ffSGleb Smirnoff for (v = bge_vendors; v->v_name != NULL; v++) 26834c0da0ffSGleb Smirnoff if (v->v_id == vid) 26844c0da0ffSGleb Smirnoff return (v); 26854c0da0ffSGleb Smirnoff 26864c0da0ffSGleb Smirnoff return (NULL); 26874c0da0ffSGleb Smirnoff } 26884c0da0ffSGleb Smirnoff 2689d7acafa1SMarius Strobl static uint32_t 2690d7acafa1SMarius Strobl bge_chipid(device_t dev) 269195d67482SBill Paul { 2692978f2704SMarius Strobl uint32_t id; 269395d67482SBill Paul 2694a5779553SStanislav Sedov id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2695a5779553SStanislav Sedov BGE_PCIMISCCTL_ASICREV_SHIFT; 26961108273aSPyun YongHyeon if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 26971108273aSPyun YongHyeon /* 2698d7acafa1SMarius Strobl * Find the ASCI revision. Different chips use different 2699d7acafa1SMarius Strobl * registers. 27001108273aSPyun YongHyeon */ 27011108273aSPyun YongHyeon switch (pci_get_device(dev)) { 27021108273aSPyun YongHyeon case BCOM_DEVICEID_BCM5717: 27031108273aSPyun YongHyeon case BCOM_DEVICEID_BCM5718: 2704bbe2ca75SPyun YongHyeon case BCOM_DEVICEID_BCM5719: 270550515680SPyun YongHyeon case BCOM_DEVICEID_BCM5720: 27062927f01fSPyun YongHyeon case BCOM_DEVICEID_BCM5725: 27072927f01fSPyun YongHyeon case BCOM_DEVICEID_BCM5727: 27082927f01fSPyun YongHyeon case BCOM_DEVICEID_BCM5762: 270967129934SPyun YongHyeon case BCOM_DEVICEID_BCM57764: 271067129934SPyun YongHyeon case BCOM_DEVICEID_BCM57767: 271167129934SPyun YongHyeon case BCOM_DEVICEID_BCM57787: 27121108273aSPyun YongHyeon id = pci_read_config(dev, 27131108273aSPyun YongHyeon BGE_PCI_GEN2_PRODID_ASICREV, 4); 27141108273aSPyun YongHyeon break; 2715b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57761: 2716fe26ad88SPyun YongHyeon case BCOM_DEVICEID_BCM57762: 2717b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57765: 2718fe26ad88SPyun YongHyeon case BCOM_DEVICEID_BCM57766: 2719b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57781: 272067129934SPyun YongHyeon case BCOM_DEVICEID_BCM57782: 2721b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57785: 272267129934SPyun YongHyeon case BCOM_DEVICEID_BCM57786: 2723b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57791: 2724b4a256acSPyun YongHyeon case BCOM_DEVICEID_BCM57795: 2725b4a256acSPyun YongHyeon id = pci_read_config(dev, 2726b4a256acSPyun YongHyeon BGE_PCI_GEN15_PRODID_ASICREV, 4); 2727b4a256acSPyun YongHyeon break; 27281108273aSPyun YongHyeon default: 2729d7acafa1SMarius Strobl id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 27301108273aSPyun YongHyeon } 27311108273aSPyun YongHyeon } 2732d7acafa1SMarius Strobl return (id); 2733d7acafa1SMarius Strobl } 2734d7acafa1SMarius Strobl 2735d7acafa1SMarius Strobl /* 2736d7acafa1SMarius Strobl * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2737d7acafa1SMarius Strobl * against our list and return its name if we find a match. 2738d7acafa1SMarius Strobl * 2739d7acafa1SMarius Strobl * Note that since the Broadcom controller contains VPD support, we 2740d7acafa1SMarius Strobl * try to get the device name string from the controller itself instead 2741d7acafa1SMarius Strobl * of the compiled-in string. It guarantees we'll always announce the 2742d7acafa1SMarius Strobl * right product name. We fall back to the compiled-in string when 2743d7acafa1SMarius Strobl * VPD is unavailable or corrupt. 2744d7acafa1SMarius Strobl */ 2745d7acafa1SMarius Strobl static int 2746d7acafa1SMarius Strobl bge_probe(device_t dev) 2747d7acafa1SMarius Strobl { 2748d7acafa1SMarius Strobl char buf[96]; 2749d7acafa1SMarius Strobl char model[64]; 2750d7acafa1SMarius Strobl const struct bge_revision *br; 2751d7acafa1SMarius Strobl const char *pname; 2752d7acafa1SMarius Strobl struct bge_softc *sc; 2753d7acafa1SMarius Strobl const struct bge_type *t = bge_devs; 2754d7acafa1SMarius Strobl const struct bge_vendor *v; 2755d7acafa1SMarius Strobl uint32_t id; 2756d7acafa1SMarius Strobl uint16_t did, vid; 2757d7acafa1SMarius Strobl 2758d7acafa1SMarius Strobl sc = device_get_softc(dev); 2759d7acafa1SMarius Strobl sc->bge_dev = dev; 2760d7acafa1SMarius Strobl vid = pci_get_vendor(dev); 2761d7acafa1SMarius Strobl did = pci_get_device(dev); 2762d7acafa1SMarius Strobl while(t->bge_vid != 0) { 2763d7acafa1SMarius Strobl if ((vid == t->bge_vid) && (did == t->bge_did)) { 2764d7acafa1SMarius Strobl id = bge_chipid(dev); 27654c0da0ffSGleb Smirnoff br = bge_lookup_rev(id); 2766852c67f9SMarius Strobl if (bge_has_eaddr(sc) && 2767852c67f9SMarius Strobl pci_get_vpd_ident(dev, &pname) == 0) 2768d7acafa1SMarius Strobl snprintf(model, sizeof(model), "%s", pname); 2769d7acafa1SMarius Strobl else { 2770d7acafa1SMarius Strobl v = bge_lookup_vendor(vid); 2771d7acafa1SMarius Strobl snprintf(model, sizeof(model), "%s %s", 2772d7acafa1SMarius Strobl v != NULL ? v->v_name : "Unknown", 27737c929cf9SJung-uk Kim br != NULL ? br->br_name : 27742ad1b396SMarius Strobl "NetXtreme/NetLink Ethernet Controller"); 2775d7acafa1SMarius Strobl } 2776d7acafa1SMarius Strobl snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2777d7acafa1SMarius Strobl model, br != NULL ? "" : "unknown ", id); 27784c0da0ffSGleb Smirnoff device_set_desc_copy(dev, buf); 2779d7acafa1SMarius Strobl return (BUS_PROBE_DEFAULT); 278095d67482SBill Paul } 278195d67482SBill Paul t++; 278295d67482SBill Paul } 278395d67482SBill Paul 278495d67482SBill Paul return (ENXIO); 278595d67482SBill Paul } 278695d67482SBill Paul 2787f41ac2beSBill Paul static void 27883f74909aSGleb Smirnoff bge_dma_free(struct bge_softc *sc) 2789f41ac2beSBill Paul { 2790f41ac2beSBill Paul int i; 2791f41ac2beSBill Paul 27923f74909aSGleb Smirnoff /* Destroy DMA maps for RX buffers. */ 2793f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2794f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_dmamap[i]) 27950ac56796SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2796f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_dmamap[i]); 2797f41ac2beSBill Paul } 2798943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_std_sparemap) 2799943787f3SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2800943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_std_sparemap); 2801f41ac2beSBill Paul 28023f74909aSGleb Smirnoff /* Destroy DMA maps for jumbo RX buffers. */ 2803f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2804f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2805f41ac2beSBill Paul bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2806f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2807f41ac2beSBill Paul } 2808943787f3SPyun YongHyeon if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2809943787f3SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2810943787f3SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_sparemap); 2811f41ac2beSBill Paul 28123f74909aSGleb Smirnoff /* Destroy DMA maps for TX buffers. */ 2813f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 2814f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_dmamap[i]) 28150ac56796SPyun YongHyeon bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2816f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[i]); 2817f41ac2beSBill Paul } 2818f41ac2beSBill Paul 28190ac56796SPyun YongHyeon if (sc->bge_cdata.bge_rx_mtag) 28200ac56796SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2821c0220d81SPyun YongHyeon if (sc->bge_cdata.bge_mtag_jumbo) 2822c0220d81SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 28230ac56796SPyun YongHyeon if (sc->bge_cdata.bge_tx_mtag) 28240ac56796SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2825f41ac2beSBill Paul 28263f74909aSGleb Smirnoff /* Destroy standard RX ring. */ 2827068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_std_ring_paddr) 2828e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2829e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map); 2830068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_std_ring) 2831f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2832f41ac2beSBill Paul sc->bge_ldata.bge_rx_std_ring, 2833f41ac2beSBill Paul sc->bge_cdata.bge_rx_std_ring_map); 2834f41ac2beSBill Paul 2835f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_std_ring_tag) 2836f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2837f41ac2beSBill Paul 28383f74909aSGleb Smirnoff /* Destroy jumbo RX ring. */ 2839068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2840e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2841e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_jumbo_ring_map); 2842e65bed95SPyun YongHyeon 2843068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_jumbo_ring) 2844f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2845f41ac2beSBill Paul sc->bge_ldata.bge_rx_jumbo_ring, 2846f41ac2beSBill Paul sc->bge_cdata.bge_rx_jumbo_ring_map); 2847f41ac2beSBill Paul 2848f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2849f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2850f41ac2beSBill Paul 28513f74909aSGleb Smirnoff /* Destroy RX return ring. */ 2852068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_return_ring_paddr) 2853e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2854e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map); 2855e65bed95SPyun YongHyeon 2856068d8643SJohn Baldwin if (sc->bge_ldata.bge_rx_return_ring) 2857f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2858f41ac2beSBill Paul sc->bge_ldata.bge_rx_return_ring, 2859f41ac2beSBill Paul sc->bge_cdata.bge_rx_return_ring_map); 2860f41ac2beSBill Paul 2861f41ac2beSBill Paul if (sc->bge_cdata.bge_rx_return_ring_tag) 2862f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2863f41ac2beSBill Paul 28643f74909aSGleb Smirnoff /* Destroy TX ring. */ 2865068d8643SJohn Baldwin if (sc->bge_ldata.bge_tx_ring_paddr) 2866e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2867e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_ring_map); 2868e65bed95SPyun YongHyeon 2869068d8643SJohn Baldwin if (sc->bge_ldata.bge_tx_ring) 2870f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2871f41ac2beSBill Paul sc->bge_ldata.bge_tx_ring, 2872f41ac2beSBill Paul sc->bge_cdata.bge_tx_ring_map); 2873f41ac2beSBill Paul 2874f41ac2beSBill Paul if (sc->bge_cdata.bge_tx_ring_tag) 2875f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2876f41ac2beSBill Paul 28773f74909aSGleb Smirnoff /* Destroy status block. */ 2878068d8643SJohn Baldwin if (sc->bge_ldata.bge_status_block_paddr) 2879e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2880e65bed95SPyun YongHyeon sc->bge_cdata.bge_status_map); 2881e65bed95SPyun YongHyeon 2882068d8643SJohn Baldwin if (sc->bge_ldata.bge_status_block) 2883f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2884f41ac2beSBill Paul sc->bge_ldata.bge_status_block, 2885f41ac2beSBill Paul sc->bge_cdata.bge_status_map); 2886f41ac2beSBill Paul 2887f41ac2beSBill Paul if (sc->bge_cdata.bge_status_tag) 2888f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2889f41ac2beSBill Paul 28903f74909aSGleb Smirnoff /* Destroy statistics block. */ 2891068d8643SJohn Baldwin if (sc->bge_ldata.bge_stats_paddr) 2892e65bed95SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2893e65bed95SPyun YongHyeon sc->bge_cdata.bge_stats_map); 2894e65bed95SPyun YongHyeon 2895068d8643SJohn Baldwin if (sc->bge_ldata.bge_stats) 2896f41ac2beSBill Paul bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2897f41ac2beSBill Paul sc->bge_ldata.bge_stats, 2898f41ac2beSBill Paul sc->bge_cdata.bge_stats_map); 2899f41ac2beSBill Paul 2900f41ac2beSBill Paul if (sc->bge_cdata.bge_stats_tag) 2901f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2902f41ac2beSBill Paul 29035b610048SPyun YongHyeon if (sc->bge_cdata.bge_buffer_tag) 29045b610048SPyun YongHyeon bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 29055b610048SPyun YongHyeon 29063f74909aSGleb Smirnoff /* Destroy the parent tag. */ 2907f41ac2beSBill Paul if (sc->bge_cdata.bge_parent_tag) 2908f41ac2beSBill Paul bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2909f41ac2beSBill Paul } 2910f41ac2beSBill Paul 2911f41ac2beSBill Paul static int 29125b610048SPyun YongHyeon bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 29135b610048SPyun YongHyeon bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 29145b610048SPyun YongHyeon bus_addr_t *paddr, const char *msg) 2915f41ac2beSBill Paul { 29163f74909aSGleb Smirnoff struct bge_dmamap_arg ctx; 29175b610048SPyun YongHyeon int error; 2918f41ac2beSBill Paul 29195b610048SPyun YongHyeon error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2920fdd45796SPyun YongHyeon alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 29215b610048SPyun YongHyeon NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 29225b610048SPyun YongHyeon if (error != 0) { 29235b610048SPyun YongHyeon device_printf(sc->bge_dev, 29245b610048SPyun YongHyeon "could not create %s dma tag\n", msg); 29255b610048SPyun YongHyeon return (ENOMEM); 29265b610048SPyun YongHyeon } 29275b610048SPyun YongHyeon /* Allocate DMA'able memory for ring. */ 29285b610048SPyun YongHyeon error = bus_dmamem_alloc(*tag, (void **)ring, 29295b610048SPyun YongHyeon BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 29305b610048SPyun YongHyeon if (error != 0) { 29315b610048SPyun YongHyeon device_printf(sc->bge_dev, 29325b610048SPyun YongHyeon "could not allocate DMA'able memory for %s\n", msg); 29335b610048SPyun YongHyeon return (ENOMEM); 29345b610048SPyun YongHyeon } 29355b610048SPyun YongHyeon /* Load the address of the ring. */ 29365b610048SPyun YongHyeon ctx.bge_busaddr = 0; 29375b610048SPyun YongHyeon error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 29385b610048SPyun YongHyeon &ctx, BUS_DMA_NOWAIT); 29395b610048SPyun YongHyeon if (error != 0) { 29405b610048SPyun YongHyeon device_printf(sc->bge_dev, 29415b610048SPyun YongHyeon "could not load DMA'able memory for %s\n", msg); 29425b610048SPyun YongHyeon return (ENOMEM); 29435b610048SPyun YongHyeon } 29445b610048SPyun YongHyeon *paddr = ctx.bge_busaddr; 29455b610048SPyun YongHyeon return (0); 29465b610048SPyun YongHyeon } 29475b610048SPyun YongHyeon 29485b610048SPyun YongHyeon static int 29495b610048SPyun YongHyeon bge_dma_alloc(struct bge_softc *sc) 29505b610048SPyun YongHyeon { 29515b610048SPyun YongHyeon bus_addr_t lowaddr; 2952fdd45796SPyun YongHyeon bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 29535b610048SPyun YongHyeon int i, error; 2954f41ac2beSBill Paul 2955f681b29aSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 2956f681b29aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2957f681b29aSPyun YongHyeon lowaddr = BGE_DMA_MAXADDR; 2958f41ac2beSBill Paul /* 2959f41ac2beSBill Paul * Allocate the parent bus DMA tag appropriate for PCI. 2960f41ac2beSBill Paul */ 29614eee14cbSMarius Strobl error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2962f681b29aSPyun YongHyeon 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 29634eee14cbSMarius Strobl NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 29644eee14cbSMarius Strobl 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2965e65bed95SPyun YongHyeon if (error != 0) { 2966fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 2967fe806fdaSPyun YongHyeon "could not allocate parent dma tag\n"); 2968e65bed95SPyun YongHyeon return (ENOMEM); 2969e65bed95SPyun YongHyeon } 2970e65bed95SPyun YongHyeon 29715b610048SPyun YongHyeon /* Create tag for standard RX ring. */ 29725b610048SPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 29735b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_std_ring_tag, 29745b610048SPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 29755b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_std_ring_map, 29765b610048SPyun YongHyeon &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 29775b610048SPyun YongHyeon if (error) 29785b610048SPyun YongHyeon return (error); 29795b610048SPyun YongHyeon 29805b610048SPyun YongHyeon /* Create tag for RX return ring. */ 29815b610048SPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 29825b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_return_ring_tag, 29835b610048SPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 29845b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_return_ring_map, 29855b610048SPyun YongHyeon &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 29865b610048SPyun YongHyeon if (error) 29875b610048SPyun YongHyeon return (error); 29885b610048SPyun YongHyeon 29895b610048SPyun YongHyeon /* Create tag for TX ring. */ 29905b610048SPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 29915b610048SPyun YongHyeon &sc->bge_cdata.bge_tx_ring_tag, 29925b610048SPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_tx_ring, 29935b610048SPyun YongHyeon &sc->bge_cdata.bge_tx_ring_map, 29945b610048SPyun YongHyeon &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 29955b610048SPyun YongHyeon if (error) 29965b610048SPyun YongHyeon return (error); 29975b610048SPyun YongHyeon 2998f41ac2beSBill Paul /* 29995b610048SPyun YongHyeon * Create tag for status block. 30005b610048SPyun YongHyeon * Because we only use single Tx/Rx/Rx return ring, use 30015b610048SPyun YongHyeon * minimum status block size except BCM5700 AX/BX which 30025b610048SPyun YongHyeon * seems to want to see full status block size regardless 30035b610048SPyun YongHyeon * of configured number of ring. 3004f41ac2beSBill Paul */ 30055b610048SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 30065b610048SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 30075b610048SPyun YongHyeon sbsz = BGE_STATUS_BLK_SZ; 30085b610048SPyun YongHyeon else 30095b610048SPyun YongHyeon sbsz = 32; 30105b610048SPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 30115b610048SPyun YongHyeon &sc->bge_cdata.bge_status_tag, 30125b610048SPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_status_block, 30135b610048SPyun YongHyeon &sc->bge_cdata.bge_status_map, 30145b610048SPyun YongHyeon &sc->bge_ldata.bge_status_block_paddr, "status block"); 30155b610048SPyun YongHyeon if (error) 30165b610048SPyun YongHyeon return (error); 30175b610048SPyun YongHyeon 301812c65daeSPyun YongHyeon /* Create tag for statistics block. */ 301912c65daeSPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 302012c65daeSPyun YongHyeon &sc->bge_cdata.bge_stats_tag, 302112c65daeSPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_stats, 302212c65daeSPyun YongHyeon &sc->bge_cdata.bge_stats_map, 302312c65daeSPyun YongHyeon &sc->bge_ldata.bge_stats_paddr, "statistics block"); 302412c65daeSPyun YongHyeon if (error) 302512c65daeSPyun YongHyeon return (error); 302612c65daeSPyun YongHyeon 30275b610048SPyun YongHyeon /* Create tag for jumbo RX ring. */ 30285b610048SPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc)) { 30295b610048SPyun YongHyeon error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 30305b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_jumbo_ring_tag, 30315b610048SPyun YongHyeon (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 30325b610048SPyun YongHyeon &sc->bge_cdata.bge_rx_jumbo_ring_map, 30335b610048SPyun YongHyeon &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 30345b610048SPyun YongHyeon if (error) 30355b610048SPyun YongHyeon return (error); 30365b610048SPyun YongHyeon } 30375b610048SPyun YongHyeon 30385b610048SPyun YongHyeon /* Create parent tag for buffers. */ 3039d2ffe15aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3040d2ffe15aSPyun YongHyeon /* 3041d2ffe15aSPyun YongHyeon * XXX 3042d2ffe15aSPyun YongHyeon * watchdog timeout issue was observed on BCM5704 which 3043d2ffe15aSPyun YongHyeon * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3044062af0b0SPyun YongHyeon * Both limiting DMA address space to 32bits and flushing 3045062af0b0SPyun YongHyeon * mailbox write seem to address the issue. 3046d2ffe15aSPyun YongHyeon */ 3047062af0b0SPyun YongHyeon if (sc->bge_pcixcap != 0) 3048d2ffe15aSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 3049d2ffe15aSPyun YongHyeon } 3050fdd45796SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3051fdd45796SPyun YongHyeon BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3052fdd45796SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3053fdd45796SPyun YongHyeon &sc->bge_cdata.bge_buffer_tag); 30545b610048SPyun YongHyeon if (error != 0) { 30555b610048SPyun YongHyeon device_printf(sc->bge_dev, 30565b610048SPyun YongHyeon "could not allocate buffer dma tag\n"); 30575b610048SPyun YongHyeon return (ENOMEM); 30585b610048SPyun YongHyeon } 30595b610048SPyun YongHyeon /* Create tag for Tx mbufs. */ 30601108273aSPyun YongHyeon if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3061ca3f1187SPyun YongHyeon txsegsz = BGE_TSOSEG_SZ; 3062ca3f1187SPyun YongHyeon txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3063ca3f1187SPyun YongHyeon } else { 3064ca3f1187SPyun YongHyeon txsegsz = MCLBYTES; 3065ca3f1187SPyun YongHyeon txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3066ca3f1187SPyun YongHyeon } 30675b610048SPyun YongHyeon error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3068ca3f1187SPyun YongHyeon 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3069ca3f1187SPyun YongHyeon txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3070ca3f1187SPyun YongHyeon &sc->bge_cdata.bge_tx_mtag); 3071f41ac2beSBill Paul 3072f41ac2beSBill Paul if (error) { 30730ac56796SPyun YongHyeon device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 30740ac56796SPyun YongHyeon return (ENOMEM); 30750ac56796SPyun YongHyeon } 30760ac56796SPyun YongHyeon 30775b610048SPyun YongHyeon /* Create tag for Rx mbufs. */ 3078f5459d4cSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3079f5459d4cSPyun YongHyeon rxmaxsegsz = MJUM9BYTES; 3080f5459d4cSPyun YongHyeon else 3081f5459d4cSPyun YongHyeon rxmaxsegsz = MCLBYTES; 30825b610048SPyun YongHyeon error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3083f5459d4cSPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3084f5459d4cSPyun YongHyeon rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 30850ac56796SPyun YongHyeon 30860ac56796SPyun YongHyeon if (error) { 30870ac56796SPyun YongHyeon device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3088f41ac2beSBill Paul return (ENOMEM); 3089f41ac2beSBill Paul } 3090f41ac2beSBill Paul 30913f74909aSGleb Smirnoff /* Create DMA maps for RX buffers. */ 3092943787f3SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3093943787f3SPyun YongHyeon &sc->bge_cdata.bge_rx_std_sparemap); 3094943787f3SPyun YongHyeon if (error) { 3095943787f3SPyun YongHyeon device_printf(sc->bge_dev, 3096943787f3SPyun YongHyeon "can't create spare DMA map for RX\n"); 3097943787f3SPyun YongHyeon return (ENOMEM); 3098943787f3SPyun YongHyeon } 3099f41ac2beSBill Paul for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 31000ac56796SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3101f41ac2beSBill Paul &sc->bge_cdata.bge_rx_std_dmamap[i]); 3102f41ac2beSBill Paul if (error) { 3103fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 3104fe806fdaSPyun YongHyeon "can't create DMA map for RX\n"); 3105f41ac2beSBill Paul return (ENOMEM); 3106f41ac2beSBill Paul } 3107f41ac2beSBill Paul } 3108f41ac2beSBill Paul 31093f74909aSGleb Smirnoff /* Create DMA maps for TX buffers. */ 3110f41ac2beSBill Paul for (i = 0; i < BGE_TX_RING_CNT; i++) { 31110ac56796SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3112f41ac2beSBill Paul &sc->bge_cdata.bge_tx_dmamap[i]); 3113f41ac2beSBill Paul if (error) { 3114fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 31150ac56796SPyun YongHyeon "can't create DMA map for TX\n"); 3116f41ac2beSBill Paul return (ENOMEM); 3117f41ac2beSBill Paul } 3118f41ac2beSBill Paul } 3119f41ac2beSBill Paul 31205b610048SPyun YongHyeon /* Create tags for jumbo RX buffers. */ 31214c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) { 31225b610048SPyun YongHyeon error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 31238a2e22deSScott Long 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 31241be6acb7SGleb Smirnoff NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 31251be6acb7SGleb Smirnoff 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3126f41ac2beSBill Paul if (error) { 3127fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 31283f74909aSGleb Smirnoff "could not allocate jumbo dma tag\n"); 3129f41ac2beSBill Paul return (ENOMEM); 3130f41ac2beSBill Paul } 31313f74909aSGleb Smirnoff /* Create DMA maps for jumbo RX buffers. */ 3132943787f3SPyun YongHyeon error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3133943787f3SPyun YongHyeon 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3134943787f3SPyun YongHyeon if (error) { 3135943787f3SPyun YongHyeon device_printf(sc->bge_dev, 31361b90d0bdSPyun YongHyeon "can't create spare DMA map for jumbo RX\n"); 3137943787f3SPyun YongHyeon return (ENOMEM); 3138943787f3SPyun YongHyeon } 3139f41ac2beSBill Paul for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3140f41ac2beSBill Paul error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3141f41ac2beSBill Paul 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3142f41ac2beSBill Paul if (error) { 3143fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 31443f74909aSGleb Smirnoff "can't create DMA map for jumbo RX\n"); 3145f41ac2beSBill Paul return (ENOMEM); 3146f41ac2beSBill Paul } 3147f41ac2beSBill Paul } 3148f41ac2beSBill Paul } 3149f41ac2beSBill Paul 3150f41ac2beSBill Paul return (0); 3151f41ac2beSBill Paul } 3152f41ac2beSBill Paul 3153bf6ef57aSJohn Polstra /* 3154bf6ef57aSJohn Polstra * Return true if this device has more than one port. 3155bf6ef57aSJohn Polstra */ 3156bf6ef57aSJohn Polstra static int 3157bf6ef57aSJohn Polstra bge_has_multiple_ports(struct bge_softc *sc) 3158bf6ef57aSJohn Polstra { 3159bf6ef57aSJohn Polstra device_t dev = sc->bge_dev; 316055aaf894SMarius Strobl u_int b, d, f, fscan, s; 3161bf6ef57aSJohn Polstra 316255aaf894SMarius Strobl d = pci_get_domain(dev); 3163bf6ef57aSJohn Polstra b = pci_get_bus(dev); 3164bf6ef57aSJohn Polstra s = pci_get_slot(dev); 3165bf6ef57aSJohn Polstra f = pci_get_function(dev); 3166bf6ef57aSJohn Polstra for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 316755aaf894SMarius Strobl if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3168bf6ef57aSJohn Polstra return (1); 3169bf6ef57aSJohn Polstra return (0); 3170bf6ef57aSJohn Polstra } 3171bf6ef57aSJohn Polstra 3172bf6ef57aSJohn Polstra /* 3173bf6ef57aSJohn Polstra * Return true if MSI can be used with this device. 3174bf6ef57aSJohn Polstra */ 3175bf6ef57aSJohn Polstra static int 3176bf6ef57aSJohn Polstra bge_can_use_msi(struct bge_softc *sc) 3177bf6ef57aSJohn Polstra { 3178bf6ef57aSJohn Polstra int can_use_msi = 0; 3179bf6ef57aSJohn Polstra 3180d9fc28e4SPyun YongHyeon if (sc->bge_msi == 0) 31815c952e8dSPyun YongHyeon return (0); 31825c952e8dSPyun YongHyeon 31831108273aSPyun YongHyeon /* Disable MSI for polling(4). */ 31841108273aSPyun YongHyeon #ifdef DEVICE_POLLING 31851108273aSPyun YongHyeon return (0); 31861108273aSPyun YongHyeon #endif 3187bf6ef57aSJohn Polstra switch (sc->bge_asicrev) { 3188a8376f70SMarius Strobl case BGE_ASICREV_BCM5714_A0: 3189bf6ef57aSJohn Polstra case BGE_ASICREV_BCM5714: 3190bf6ef57aSJohn Polstra /* 3191a8376f70SMarius Strobl * Apparently, MSI doesn't work when these chips are 3192a8376f70SMarius Strobl * configured in single-port mode. 3193bf6ef57aSJohn Polstra */ 3194bf6ef57aSJohn Polstra if (bge_has_multiple_ports(sc)) 3195bf6ef57aSJohn Polstra can_use_msi = 1; 3196bf6ef57aSJohn Polstra break; 3197bf6ef57aSJohn Polstra case BGE_ASICREV_BCM5750: 3198bf6ef57aSJohn Polstra if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3199bf6ef57aSJohn Polstra sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3200bf6ef57aSJohn Polstra can_use_msi = 1; 3201bf6ef57aSJohn Polstra break; 3202a8376f70SMarius Strobl default: 3203a8376f70SMarius Strobl if (BGE_IS_575X_PLUS(sc)) 3204bf6ef57aSJohn Polstra can_use_msi = 1; 3205bf6ef57aSJohn Polstra } 3206bf6ef57aSJohn Polstra return (can_use_msi); 3207bf6ef57aSJohn Polstra } 3208bf6ef57aSJohn Polstra 320995d67482SBill Paul static int 3210062af0b0SPyun YongHyeon bge_mbox_reorder(struct bge_softc *sc) 3211062af0b0SPyun YongHyeon { 3212062af0b0SPyun YongHyeon /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3213062af0b0SPyun YongHyeon static const struct mbox_reorder { 3214062af0b0SPyun YongHyeon const uint16_t vendor; 3215062af0b0SPyun YongHyeon const uint16_t device; 3216062af0b0SPyun YongHyeon const char *desc; 321729658c96SDimitry Andric } mbox_reorder_lists[] = { 3218062af0b0SPyun YongHyeon { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3219062af0b0SPyun YongHyeon }; 3220062af0b0SPyun YongHyeon devclass_t pci, pcib; 3221062af0b0SPyun YongHyeon device_t bus, dev; 322247f4a4dcSMarius Strobl int i; 3223062af0b0SPyun YongHyeon 3224062af0b0SPyun YongHyeon pci = devclass_find("pci"); 3225062af0b0SPyun YongHyeon pcib = devclass_find("pcib"); 3226062af0b0SPyun YongHyeon dev = sc->bge_dev; 3227062af0b0SPyun YongHyeon bus = device_get_parent(dev); 3228062af0b0SPyun YongHyeon for (;;) { 3229062af0b0SPyun YongHyeon dev = device_get_parent(bus); 3230062af0b0SPyun YongHyeon bus = device_get_parent(dev); 3231062af0b0SPyun YongHyeon if (device_get_devclass(dev) != pcib) 3232062af0b0SPyun YongHyeon break; 323347f4a4dcSMarius Strobl for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3234062af0b0SPyun YongHyeon if (pci_get_vendor(dev) == 3235062af0b0SPyun YongHyeon mbox_reorder_lists[i].vendor && 3236062af0b0SPyun YongHyeon pci_get_device(dev) == 3237062af0b0SPyun YongHyeon mbox_reorder_lists[i].device) { 3238062af0b0SPyun YongHyeon device_printf(sc->bge_dev, 3239062af0b0SPyun YongHyeon "enabling MBOX workaround for %s\n", 3240062af0b0SPyun YongHyeon mbox_reorder_lists[i].desc); 3241062af0b0SPyun YongHyeon return (1); 3242062af0b0SPyun YongHyeon } 3243062af0b0SPyun YongHyeon } 3244062af0b0SPyun YongHyeon if (device_get_devclass(bus) != pci) 3245062af0b0SPyun YongHyeon break; 3246062af0b0SPyun YongHyeon } 3247062af0b0SPyun YongHyeon return (0); 3248062af0b0SPyun YongHyeon } 3249062af0b0SPyun YongHyeon 3250ea9c3a30SPyun YongHyeon static void 3251ea9c3a30SPyun YongHyeon bge_devinfo(struct bge_softc *sc) 3252ea9c3a30SPyun YongHyeon { 3253ea9c3a30SPyun YongHyeon uint32_t cfg, clk; 3254ea9c3a30SPyun YongHyeon 3255ea9c3a30SPyun YongHyeon device_printf(sc->bge_dev, 3256ea9c3a30SPyun YongHyeon "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3257ea9c3a30SPyun YongHyeon sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3258ea9c3a30SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_PCIE) 3259ea9c3a30SPyun YongHyeon printf("PCI-E\n"); 3260ea9c3a30SPyun YongHyeon else if (sc->bge_flags & BGE_FLAG_PCIX) { 3261ea9c3a30SPyun YongHyeon printf("PCI-X "); 3262ea9c3a30SPyun YongHyeon cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3263ea9c3a30SPyun YongHyeon if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3264ea9c3a30SPyun YongHyeon clk = 133; 3265ea9c3a30SPyun YongHyeon else { 3266ea9c3a30SPyun YongHyeon clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3267ea9c3a30SPyun YongHyeon switch (clk) { 3268ea9c3a30SPyun YongHyeon case 0: 3269ea9c3a30SPyun YongHyeon clk = 33; 3270ea9c3a30SPyun YongHyeon break; 3271ea9c3a30SPyun YongHyeon case 2: 3272ea9c3a30SPyun YongHyeon clk = 50; 3273ea9c3a30SPyun YongHyeon break; 3274ea9c3a30SPyun YongHyeon case 4: 3275ea9c3a30SPyun YongHyeon clk = 66; 3276ea9c3a30SPyun YongHyeon break; 3277ea9c3a30SPyun YongHyeon case 6: 3278ea9c3a30SPyun YongHyeon clk = 100; 3279ea9c3a30SPyun YongHyeon break; 3280ea9c3a30SPyun YongHyeon case 7: 3281ea9c3a30SPyun YongHyeon clk = 133; 3282ea9c3a30SPyun YongHyeon break; 3283ea9c3a30SPyun YongHyeon } 3284ea9c3a30SPyun YongHyeon } 3285ea9c3a30SPyun YongHyeon printf("%u MHz\n", clk); 3286ea9c3a30SPyun YongHyeon } else { 3287ea9c3a30SPyun YongHyeon if (sc->bge_pcixcap != 0) 3288ea9c3a30SPyun YongHyeon printf("PCI on PCI-X "); 3289ea9c3a30SPyun YongHyeon else 3290ea9c3a30SPyun YongHyeon printf("PCI "); 3291ea9c3a30SPyun YongHyeon cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3292ea9c3a30SPyun YongHyeon if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3293ea9c3a30SPyun YongHyeon clk = 66; 3294ea9c3a30SPyun YongHyeon else 3295ea9c3a30SPyun YongHyeon clk = 33; 3296ea9c3a30SPyun YongHyeon if (cfg & BGE_PCISTATE_32BIT_BUS) 3297ea9c3a30SPyun YongHyeon printf("%u MHz; 32bit\n", clk); 3298ea9c3a30SPyun YongHyeon else 3299ea9c3a30SPyun YongHyeon printf("%u MHz; 64bit\n", clk); 3300ea9c3a30SPyun YongHyeon } 3301ea9c3a30SPyun YongHyeon } 3302ea9c3a30SPyun YongHyeon 3303062af0b0SPyun YongHyeon static int 33043f74909aSGleb Smirnoff bge_attach(device_t dev) 330595d67482SBill Paul { 3306fba8b109SMarcel Moolenaar if_t ifp; 330795d67482SBill Paul struct bge_softc *sc; 3308548c8f1aSPyun YongHyeon uint32_t hwcfg = 0, misccfg, pcistate; 330908013fd3SMarius Strobl u_char eaddr[ETHER_ADDR_LEN]; 3310ad4328baSMarius Strobl int capmask, error, reg, rid, trys; 331195d67482SBill Paul 331295d67482SBill Paul sc = device_get_softc(dev); 331395d67482SBill Paul sc->bge_dev = dev; 331495d67482SBill Paul 3315e010b055SPyun YongHyeon BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3316dfe0df9aSPyun YongHyeon TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3317e010b055SPyun YongHyeon callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3318dfe0df9aSPyun YongHyeon 331995d67482SBill Paul pci_enable_busmaster(dev); 332095d67482SBill Paul 3321ad4328baSMarius Strobl /* 3322ad4328baSMarius Strobl * Allocate control/status registers. 3323ad4328baSMarius Strobl */ 3324736b9319SPyun YongHyeon rid = PCIR_BAR(0); 33255f96beb9SNate Lawson sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 332644f8f2fcSMarius Strobl RF_ACTIVE); 332795d67482SBill Paul 332895d67482SBill Paul if (sc->bge_res == NULL) { 3329548c8f1aSPyun YongHyeon device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 333095d67482SBill Paul error = ENXIO; 333195d67482SBill Paul goto fail; 333295d67482SBill Paul } 333395d67482SBill Paul 33344f09c4c7SMarius Strobl /* Save various chip information. */ 3335548c8f1aSPyun YongHyeon sc->bge_func_addr = pci_get_function(dev); 3336d7acafa1SMarius Strobl sc->bge_chipid = bge_chipid(dev); 3337e53d81eeSPaul Saab sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3338e53d81eeSPaul Saab sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3339e53d81eeSPaul Saab 3340a813ed78SPyun YongHyeon /* Set default PHY address. */ 3341daeeb75cSPyun YongHyeon sc->bge_phy_addr = 1; 33421108273aSPyun YongHyeon /* 33431108273aSPyun YongHyeon * PHY address mapping for various devices. 33441108273aSPyun YongHyeon * 33451108273aSPyun YongHyeon * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 33461108273aSPyun YongHyeon * ---------+-------+-------+-------+-------+ 33471108273aSPyun YongHyeon * BCM57XX | 1 | X | X | X | 33481108273aSPyun YongHyeon * BCM5704 | 1 | X | 1 | X | 33491108273aSPyun YongHyeon * BCM5717 | 1 | 8 | 2 | 9 | 3350bbe2ca75SPyun YongHyeon * BCM5719 | 1 | 8 | 2 | 9 | 335150515680SPyun YongHyeon * BCM5720 | 1 | 8 | 2 | 9 | 33521108273aSPyun YongHyeon * 3353548c8f1aSPyun YongHyeon * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3354548c8f1aSPyun YongHyeon * ---------+-------+-------+-------+-------+ 3355548c8f1aSPyun YongHyeon * BCM57XX | X | X | X | X | 3356548c8f1aSPyun YongHyeon * BCM5704 | X | X | X | X | 3357548c8f1aSPyun YongHyeon * BCM5717 | X | X | X | X | 3358548c8f1aSPyun YongHyeon * BCM5719 | 3 | 10 | 4 | 11 | 3359548c8f1aSPyun YongHyeon * BCM5720 | X | X | X | X | 3360548c8f1aSPyun YongHyeon * 33611108273aSPyun YongHyeon * Other addresses may respond but they are not 33621108273aSPyun YongHyeon * IEEE compliant PHYs and should be ignored. 33631108273aSPyun YongHyeon */ 3364bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 336550515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5719 || 336650515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3367548c8f1aSPyun YongHyeon if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 33681108273aSPyun YongHyeon if (CSR_READ_4(sc, BGE_SGDIG_STS) & 33691108273aSPyun YongHyeon BGE_SGDIGSTS_IS_SERDES) 3370daeeb75cSPyun YongHyeon sc->bge_phy_addr = sc->bge_func_addr + 8; 33711108273aSPyun YongHyeon else 3372daeeb75cSPyun YongHyeon sc->bge_phy_addr = sc->bge_func_addr + 1; 3373bbe2ca75SPyun YongHyeon } else { 33741108273aSPyun YongHyeon if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 33751108273aSPyun YongHyeon BGE_CPMU_PHY_STRAP_IS_SERDES) 3376daeeb75cSPyun YongHyeon sc->bge_phy_addr = sc->bge_func_addr + 8; 33771108273aSPyun YongHyeon else 3378daeeb75cSPyun YongHyeon sc->bge_phy_addr = sc->bge_func_addr + 1; 33791108273aSPyun YongHyeon } 33801108273aSPyun YongHyeon } 3381a813ed78SPyun YongHyeon 33825fea260fSMarius Strobl if (bge_has_eaddr(sc)) 33835fea260fSMarius Strobl sc->bge_flags |= BGE_FLAG_EADDR; 338408013fd3SMarius Strobl 33850dae9719SJung-uk Kim /* Save chipset family. */ 33860dae9719SJung-uk Kim switch (sc->bge_asicrev) { 33872927f01fSPyun YongHyeon case BGE_ASICREV_BCM5762: 3388fe26ad88SPyun YongHyeon case BGE_ASICREV_BCM57765: 3389fe26ad88SPyun YongHyeon case BGE_ASICREV_BCM57766: 3390fe26ad88SPyun YongHyeon sc->bge_flags |= BGE_FLAG_57765_PLUS; 3391fe26ad88SPyun YongHyeon /* FALLTHROUGH */ 33921108273aSPyun YongHyeon case BGE_ASICREV_BCM5717: 3393bbe2ca75SPyun YongHyeon case BGE_ASICREV_BCM5719: 339450515680SPyun YongHyeon case BGE_ASICREV_BCM5720: 33951108273aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 33961108273aSPyun YongHyeon BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3397b4a256acSPyun YongHyeon BGE_FLAG_JUMBO_FRAME; 339829b44b09SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 339929b44b09SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) { 340029b44b09SPyun YongHyeon /* 340129b44b09SPyun YongHyeon * Enable work around for DMA engine miscalculation 340229b44b09SPyun YongHyeon * of TXMBUF available space. 340329b44b09SPyun YongHyeon */ 340429b44b09SPyun YongHyeon sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3405bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3406bbe2ca75SPyun YongHyeon sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3407bbe2ca75SPyun YongHyeon /* Jumbo frame on BCM5719 A0 does not work. */ 3408463a7e27SPyun YongHyeon sc->bge_flags &= ~BGE_FLAG_JUMBO; 3409bbe2ca75SPyun YongHyeon } 341029b44b09SPyun YongHyeon } 34111108273aSPyun YongHyeon break; 3412a5779553SStanislav Sedov case BGE_ASICREV_BCM5755: 3413a5779553SStanislav Sedov case BGE_ASICREV_BCM5761: 3414a5779553SStanislav Sedov case BGE_ASICREV_BCM5784: 3415a5779553SStanislav Sedov case BGE_ASICREV_BCM5785: 3416a5779553SStanislav Sedov case BGE_ASICREV_BCM5787: 3417a5779553SStanislav Sedov case BGE_ASICREV_BCM57780: 3418a5779553SStanislav Sedov sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3419a5779553SStanislav Sedov BGE_FLAG_5705_PLUS; 3420a5779553SStanislav Sedov break; 34210dae9719SJung-uk Kim case BGE_ASICREV_BCM5700: 34220dae9719SJung-uk Kim case BGE_ASICREV_BCM5701: 34230dae9719SJung-uk Kim case BGE_ASICREV_BCM5703: 34240dae9719SJung-uk Kim case BGE_ASICREV_BCM5704: 34257ee00338SJung-uk Kim sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 34260dae9719SJung-uk Kim break; 34270dae9719SJung-uk Kim case BGE_ASICREV_BCM5714_A0: 34280dae9719SJung-uk Kim case BGE_ASICREV_BCM5780: 34290dae9719SJung-uk Kim case BGE_ASICREV_BCM5714: 3430f5459d4cSPyun YongHyeon sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 34319fe569d8SXin LI /* FALLTHROUGH */ 34320dae9719SJung-uk Kim case BGE_ASICREV_BCM5750: 34330dae9719SJung-uk Kim case BGE_ASICREV_BCM5752: 343438cc658fSJohn Baldwin case BGE_ASICREV_BCM5906: 34350dae9719SJung-uk Kim sc->bge_flags |= BGE_FLAG_575X_PLUS; 34369fe569d8SXin LI /* FALLTHROUGH */ 34370dae9719SJung-uk Kim case BGE_ASICREV_BCM5705: 34380dae9719SJung-uk Kim sc->bge_flags |= BGE_FLAG_5705_PLUS; 34390dae9719SJung-uk Kim break; 34400dae9719SJung-uk Kim } 34410dae9719SJung-uk Kim 3442548c8f1aSPyun YongHyeon /* Identify chips with APE processor. */ 3443548c8f1aSPyun YongHyeon switch (sc->bge_asicrev) { 3444548c8f1aSPyun YongHyeon case BGE_ASICREV_BCM5717: 3445548c8f1aSPyun YongHyeon case BGE_ASICREV_BCM5719: 3446548c8f1aSPyun YongHyeon case BGE_ASICREV_BCM5720: 3447548c8f1aSPyun YongHyeon case BGE_ASICREV_BCM5761: 34482927f01fSPyun YongHyeon case BGE_ASICREV_BCM5762: 3449548c8f1aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_APE; 3450548c8f1aSPyun YongHyeon break; 3451548c8f1aSPyun YongHyeon } 3452548c8f1aSPyun YongHyeon 3453548c8f1aSPyun YongHyeon /* Chips with APE need BAR2 access for APE registers/memory. */ 3454548c8f1aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3455548c8f1aSPyun YongHyeon rid = PCIR_BAR(2); 3456548c8f1aSPyun YongHyeon sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3457548c8f1aSPyun YongHyeon RF_ACTIVE); 3458548c8f1aSPyun YongHyeon if (sc->bge_res2 == NULL) { 3459548c8f1aSPyun YongHyeon device_printf (sc->bge_dev, 3460548c8f1aSPyun YongHyeon "couldn't map BAR2 memory\n"); 3461548c8f1aSPyun YongHyeon error = ENXIO; 3462548c8f1aSPyun YongHyeon goto fail; 3463548c8f1aSPyun YongHyeon } 3464548c8f1aSPyun YongHyeon 3465548c8f1aSPyun YongHyeon /* Enable APE register/memory access by host driver. */ 3466548c8f1aSPyun YongHyeon pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3467548c8f1aSPyun YongHyeon pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3468548c8f1aSPyun YongHyeon BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3469548c8f1aSPyun YongHyeon BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3470548c8f1aSPyun YongHyeon pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3471548c8f1aSPyun YongHyeon 3472548c8f1aSPyun YongHyeon bge_ape_lock_init(sc); 3473548c8f1aSPyun YongHyeon bge_ape_read_fw_ver(sc); 3474548c8f1aSPyun YongHyeon } 3475548c8f1aSPyun YongHyeon 3476749a5269SMarius Strobl /* Add SYSCTLs, requires the chipset family to be set. */ 3477749a5269SMarius Strobl bge_add_sysctls(sc); 3478749a5269SMarius Strobl 3479a813ed78SPyun YongHyeon /* Identify the chips that use an CPMU. */ 34801108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc) || 34811108273aSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3482a813ed78SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3483a813ed78SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3484a813ed78SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM57780) 3485a813ed78SPyun YongHyeon sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3486a813ed78SPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3487a813ed78SPyun YongHyeon sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3488a813ed78SPyun YongHyeon else 3489a813ed78SPyun YongHyeon sc->bge_mi_mode = BGE_MIMODE_BASE; 34907ed3f0f0SPyun YongHyeon /* Enable auto polling for BCM570[0-5]. */ 34917ed3f0f0SPyun YongHyeon if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 34927ed3f0f0SPyun YongHyeon sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3493a813ed78SPyun YongHyeon 3494f681b29aSPyun YongHyeon /* 3495d4622124SPyun YongHyeon * All Broadcom controllers have 4GB boundary DMA bug. 3496f681b29aSPyun YongHyeon * Whenever an address crosses a multiple of the 4GB boundary 3497f681b29aSPyun YongHyeon * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3498f681b29aSPyun YongHyeon * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3499f681b29aSPyun YongHyeon * state machine will lockup and cause the device to hang. 3500f681b29aSPyun YongHyeon */ 3501f681b29aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 35024f0794ffSBjoern A. Zeeb 3503d9820cd8SPyun YongHyeon /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3504d9820cd8SPyun YongHyeon if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3505d9820cd8SPyun YongHyeon sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3506d9820cd8SPyun YongHyeon 3507a7fcfcf3SPyun YongHyeon /* 3508a7fcfcf3SPyun YongHyeon * BCM5719 cannot handle DMA requests for DMA segments that 3509a7fcfcf3SPyun YongHyeon * have larger than 4KB in size. However the maximum DMA 3510a7fcfcf3SPyun YongHyeon * segment size created in DMA tag is 4KB for TSO, so we 3511a7fcfcf3SPyun YongHyeon * wouldn't encounter the issue here. 3512a7fcfcf3SPyun YongHyeon */ 3513a7fcfcf3SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3514a7fcfcf3SPyun YongHyeon sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3515a7fcfcf3SPyun YongHyeon 3516ea9c3a30SPyun YongHyeon misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3517fb772a6cSMarius Strobl if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 35184f0794ffSBjoern A. Zeeb if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 35194f0794ffSBjoern A. Zeeb misccfg == BGE_MISCCFG_BOARD_ID_5788M) 35204f0794ffSBjoern A. Zeeb sc->bge_flags |= BGE_FLAG_5788; 352184ac96f8SPyun YongHyeon } 35224f0794ffSBjoern A. Zeeb 3523fb772a6cSMarius Strobl capmask = BMSR_DEFCAPMASK; 3524fb772a6cSMarius Strobl if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3525fb772a6cSMarius Strobl (misccfg == 0x4000 || misccfg == 0x8000)) || 3526fb772a6cSMarius Strobl (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3527fb772a6cSMarius Strobl pci_get_vendor(dev) == BCOM_VENDORID && 3528fb772a6cSMarius Strobl (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3529fb772a6cSMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3530fb772a6cSMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3531fb772a6cSMarius Strobl (pci_get_vendor(dev) == BCOM_VENDORID && 3532fb772a6cSMarius Strobl (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3533fb772a6cSMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3534fb772a6cSMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3535fb772a6cSMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3536d7acafa1SMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3537d7acafa1SMarius Strobl pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3538fb772a6cSMarius Strobl sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3539fb772a6cSMarius Strobl /* These chips are 10/100 only. */ 3540fb772a6cSMarius Strobl capmask &= ~BMSR_EXTSTAT; 3541d73ea7c6SPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3542fb772a6cSMarius Strobl } 3543fb772a6cSMarius Strobl 3544e53d81eeSPaul Saab /* 3545ca3f1187SPyun YongHyeon * Some controllers seem to require a special firmware to use 3546ca3f1187SPyun YongHyeon * TSO. But the firmware is not available to FreeBSD and Linux 3547ca3f1187SPyun YongHyeon * claims that the TSO performed by the firmware is slower than 3548ca3f1187SPyun YongHyeon * hardware based TSO. Moreover the firmware based TSO has one 3549d7acafa1SMarius Strobl * known bug which can't handle TSO if Ethernet header + IP/TCP 3550d7acafa1SMarius Strobl * header is greater than 80 bytes. A workaround for the TSO 3551ca3f1187SPyun YongHyeon * bug exist but it seems it's too expensive than not using 3552ca3f1187SPyun YongHyeon * TSO at all. Some hardwares also have the TSO bug so limit 3553ca3f1187SPyun YongHyeon * the TSO to the controllers that are not affected TSO issues 3554ca3f1187SPyun YongHyeon * (e.g. 5755 or higher). 3555ca3f1187SPyun YongHyeon */ 35561108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 35571108273aSPyun YongHyeon /* BCM5717 requires different TSO configuration. */ 35581108273aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_TSO3; 3559bbe2ca75SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3560bbe2ca75SPyun YongHyeon sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3561bbe2ca75SPyun YongHyeon /* TSO on BCM5719 A0 does not work. */ 3562bbe2ca75SPyun YongHyeon sc->bge_flags &= ~BGE_FLAG_TSO3; 3563bbe2ca75SPyun YongHyeon } 35641108273aSPyun YongHyeon } else if (BGE_IS_5755_PLUS(sc)) { 35654f4a16e1SPyun YongHyeon /* 35664f4a16e1SPyun YongHyeon * BCM5754 and BCM5787 shares the same ASIC id so 35674f4a16e1SPyun YongHyeon * explicit device id check is required. 3568be95548dSPyun YongHyeon * Due to unknown reason TSO does not work on BCM5755M. 35694f4a16e1SPyun YongHyeon */ 35704f4a16e1SPyun YongHyeon if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3571be95548dSPyun YongHyeon pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3572be95548dSPyun YongHyeon pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3573ca3f1187SPyun YongHyeon sc->bge_flags |= BGE_FLAG_TSO; 35744f4a16e1SPyun YongHyeon } 3575ca3f1187SPyun YongHyeon 3576ca3f1187SPyun YongHyeon /* 35776f8718a3SScott Long * Check if this is a PCI-X or PCI Express device. 3578e53d81eeSPaul Saab */ 35793b0a4aefSJohn Baldwin if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 35804c0da0ffSGleb Smirnoff /* 35816f8718a3SScott Long * Found a PCI Express capabilities register, this 35826f8718a3SScott Long * must be a PCI Express device. 35836f8718a3SScott Long */ 35846f8718a3SScott Long sc->bge_flags |= BGE_FLAG_PCIE; 35850aaf1057SPyun YongHyeon sc->bge_expcap = reg; 358648630d79SPyun YongHyeon /* Extract supported maximum payload size. */ 358748630d79SPyun YongHyeon sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 358848630d79SPyun YongHyeon PCIER_DEVICE_CAP, 2); 358948630d79SPyun YongHyeon sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 359050515680SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 359150515680SPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5720) 359248630d79SPyun YongHyeon sc->bge_expmrq = 2048; 359348630d79SPyun YongHyeon else 359448630d79SPyun YongHyeon sc->bge_expmrq = 4096; 359548630d79SPyun YongHyeon pci_set_max_read_req(dev, sc->bge_expmrq); 35966f8718a3SScott Long } else { 35976f8718a3SScott Long /* 35986f8718a3SScott Long * Check if the device is in PCI-X Mode. 35996f8718a3SScott Long * (This bit is not valid on PCI Express controllers.) 36004c0da0ffSGleb Smirnoff */ 36013b0a4aefSJohn Baldwin if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 36020aaf1057SPyun YongHyeon sc->bge_pcixcap = reg; 360390447aadSMarius Strobl if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 36044c0da0ffSGleb Smirnoff BGE_PCISTATE_PCI_BUSMODE) == 0) 3605652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_PCIX; 36066f8718a3SScott Long } 36074c0da0ffSGleb Smirnoff 3608bf6ef57aSJohn Polstra /* 3609fd4d32feSPyun YongHyeon * The 40bit DMA bug applies to the 5714/5715 controllers and is 3610fd4d32feSPyun YongHyeon * not actually a MAC controller bug but an issue with the embedded 3611fd4d32feSPyun YongHyeon * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3612fd4d32feSPyun YongHyeon */ 3613fd4d32feSPyun YongHyeon if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3614fd4d32feSPyun YongHyeon sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3615fd4d32feSPyun YongHyeon /* 3616062af0b0SPyun YongHyeon * Some PCI-X bridges are known to trigger write reordering to 3617062af0b0SPyun YongHyeon * the mailbox registers. Typical phenomena is watchdog timeouts 3618062af0b0SPyun YongHyeon * caused by out-of-order TX completions. Enable workaround for 3619062af0b0SPyun YongHyeon * PCI-X devices that live behind these bridges. 3620062af0b0SPyun YongHyeon * Note, PCI-X controllers can run in PCI mode so we can't use 3621062af0b0SPyun YongHyeon * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3622062af0b0SPyun YongHyeon */ 3623062af0b0SPyun YongHyeon if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3624062af0b0SPyun YongHyeon sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3625062af0b0SPyun YongHyeon /* 3626bf6ef57aSJohn Polstra * Allocate the interrupt, using MSI if possible. These devices 3627bf6ef57aSJohn Polstra * support 8 MSI messages, but only the first one is used in 3628bf6ef57aSJohn Polstra * normal operation. 3629bf6ef57aSJohn Polstra */ 36300aaf1057SPyun YongHyeon rid = 0; 36313b0a4aefSJohn Baldwin if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 36320aaf1057SPyun YongHyeon sc->bge_msicap = reg; 3633ad4328baSMarius Strobl reg = 1; 3634ad4328baSMarius Strobl if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3635bf6ef57aSJohn Polstra rid = 1; 3636bf6ef57aSJohn Polstra sc->bge_flags |= BGE_FLAG_MSI; 36370aaf1057SPyun YongHyeon } 36380aaf1057SPyun YongHyeon } 3639bf6ef57aSJohn Polstra 36401108273aSPyun YongHyeon /* 36411108273aSPyun YongHyeon * All controllers except BCM5700 supports tagged status but 36421108273aSPyun YongHyeon * we use tagged status only for MSI case on BCM5717. Otherwise 36431108273aSPyun YongHyeon * MSI on BCM5717 does not work. 36441108273aSPyun YongHyeon */ 36451108273aSPyun YongHyeon #ifndef DEVICE_POLLING 36461108273aSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 36471108273aSPyun YongHyeon sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 36481108273aSPyun YongHyeon #endif 36491108273aSPyun YongHyeon 3650bf6ef57aSJohn Polstra sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3651ad4328baSMarius Strobl RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3652bf6ef57aSJohn Polstra 3653bf6ef57aSJohn Polstra if (sc->bge_irq == NULL) { 3654bf6ef57aSJohn Polstra device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3655bf6ef57aSJohn Polstra error = ENXIO; 3656bf6ef57aSJohn Polstra goto fail; 3657bf6ef57aSJohn Polstra } 3658bf6ef57aSJohn Polstra 3659ea9c3a30SPyun YongHyeon bge_devinfo(sc); 36604f09c4c7SMarius Strobl 36618cb1383cSDoug Ambrisko sc->bge_asf_mode = 0; 3662548c8f1aSPyun YongHyeon /* No ASF if APE present. */ 3663548c8f1aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3664888b47f0SPyun YongHyeon if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3665888b47f0SPyun YongHyeon BGE_SRAM_DATA_SIG_MAGIC)) { 3666548c8f1aSPyun YongHyeon if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3667548c8f1aSPyun YongHyeon BGE_HWCFG_ASF) { 36688cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_ENABLE; 36698cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_STACKUP; 3670d67eba2fSPyun YongHyeon if (BGE_IS_575X_PLUS(sc)) 36718cb1383cSDoug Ambrisko sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 36728cb1383cSDoug Ambrisko } 36738cb1383cSDoug Ambrisko } 3674548c8f1aSPyun YongHyeon } 36758cb1383cSDoug Ambrisko 36768cb1383cSDoug Ambrisko bge_stop_fw(sc); 36773dd76c98SPyun YongHyeon bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 36788cb1383cSDoug Ambrisko if (bge_reset(sc)) { 36798cb1383cSDoug Ambrisko device_printf(sc->bge_dev, "chip reset failed\n"); 36808cb1383cSDoug Ambrisko error = ENXIO; 36818cb1383cSDoug Ambrisko goto fail; 36828cb1383cSDoug Ambrisko } 36838cb1383cSDoug Ambrisko 36843dd76c98SPyun YongHyeon bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 36853dd76c98SPyun YongHyeon bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 368695d67482SBill Paul 368795d67482SBill Paul if (bge_chipinit(sc)) { 3688fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "chip initialization failed\n"); 368995d67482SBill Paul error = ENXIO; 369095d67482SBill Paul goto fail; 369195d67482SBill Paul } 369295d67482SBill Paul 369338cc658fSJohn Baldwin error = bge_get_eaddr(sc, eaddr); 369438cc658fSJohn Baldwin if (error) { 369508013fd3SMarius Strobl device_printf(sc->bge_dev, 369608013fd3SMarius Strobl "failed to read station address\n"); 369795d67482SBill Paul error = ENXIO; 369895d67482SBill Paul goto fail; 369995d67482SBill Paul } 370095d67482SBill Paul 3701f41ac2beSBill Paul /* 5705 limits RX return ring to 512 entries. */ 37021108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) 37031108273aSPyun YongHyeon sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 37041108273aSPyun YongHyeon else if (BGE_IS_5705_PLUS(sc)) 3705f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3706f41ac2beSBill Paul else 3707f41ac2beSBill Paul sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3708f41ac2beSBill Paul 37095b610048SPyun YongHyeon if (bge_dma_alloc(sc)) { 3710fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, 3711fe806fdaSPyun YongHyeon "failed to allocate DMA resources\n"); 3712f41ac2beSBill Paul error = ENXIO; 3713f41ac2beSBill Paul goto fail; 3714f41ac2beSBill Paul } 3715f41ac2beSBill Paul 371695d67482SBill Paul /* Set default tuneable values. */ 371795d67482SBill Paul sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 371895d67482SBill Paul sc->bge_rx_coal_ticks = 150; 371995d67482SBill Paul sc->bge_tx_coal_ticks = 150; 37206f8718a3SScott Long sc->bge_rx_max_coal_bds = 10; 37216f8718a3SScott Long sc->bge_tx_max_coal_bds = 10; 372295d67482SBill Paul 372335f945cdSPyun YongHyeon /* Initialize checksum features to use. */ 372435f945cdSPyun YongHyeon sc->bge_csum_features = BGE_CSUM_FEATURES; 372535f945cdSPyun YongHyeon if (sc->bge_forced_udpcsum != 0) 372635f945cdSPyun YongHyeon sc->bge_csum_features |= CSUM_UDP; 372735f945cdSPyun YongHyeon 372895d67482SBill Paul /* Set up ifnet structure */ 3729fc74a9f9SBrooks Davis ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3730fc74a9f9SBrooks Davis if (ifp == NULL) { 3731fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3732fc74a9f9SBrooks Davis error = ENXIO; 3733fc74a9f9SBrooks Davis goto fail; 3734fc74a9f9SBrooks Davis } 3735fba8b109SMarcel Moolenaar if_setsoftc(ifp, sc); 37369bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3737fba8b109SMarcel Moolenaar if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3738fba8b109SMarcel Moolenaar if_setioctlfn(ifp, bge_ioctl); 3739fba8b109SMarcel Moolenaar if_setstartfn(ifp, bge_start); 3740fba8b109SMarcel Moolenaar if_setinitfn(ifp, bge_init); 37414a81240cSMarcel Moolenaar if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3742fba8b109SMarcel Moolenaar if_setsendqready(ifp); 3743fba8b109SMarcel Moolenaar if_sethwassist(ifp, sc->bge_csum_features); 3744fba8b109SMarcel Moolenaar if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3745fba8b109SMarcel Moolenaar IFCAP_VLAN_MTU); 37461108273aSPyun YongHyeon if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3747fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, CSUM_TSO, 0); 3748fba8b109SMarcel Moolenaar if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3749ca3f1187SPyun YongHyeon } 37504e35d186SJung-uk Kim #ifdef IFCAP_VLAN_HWCSUM 3751fba8b109SMarcel Moolenaar if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 37524e35d186SJung-uk Kim #endif 3753fba8b109SMarcel Moolenaar if_setcapenable(ifp, if_getcapabilities(ifp)); 375475719184SGleb Smirnoff #ifdef DEVICE_POLLING 3755fba8b109SMarcel Moolenaar if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 375675719184SGleb Smirnoff #endif 375795d67482SBill Paul 3758a1d52896SBill Paul /* 3759d375e524SGleb Smirnoff * 5700 B0 chips do not support checksumming correctly due 3760d375e524SGleb Smirnoff * to hardware bugs. 3761d375e524SGleb Smirnoff */ 3762d375e524SGleb Smirnoff if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3763fba8b109SMarcel Moolenaar if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3764fba8b109SMarcel Moolenaar if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3765fba8b109SMarcel Moolenaar if_sethwassist(ifp, 0); 3766d375e524SGleb Smirnoff } 3767d375e524SGleb Smirnoff 3768d375e524SGleb Smirnoff /* 3769a1d52896SBill Paul * Figure out what sort of media we have by checking the 377041abcc1bSPaul Saab * hardware config word in the first 32k of NIC internal memory, 377141abcc1bSPaul Saab * or fall back to examining the EEPROM if necessary. 377241abcc1bSPaul Saab * Note: on some BCM5700 cards, this value appears to be unset. 377341abcc1bSPaul Saab * If that's the case, we have to rely on identifying the NIC 377441abcc1bSPaul Saab * by its PCI subsystem ID, as we do below for the SysKonnect 377541abcc1bSPaul Saab * SK-9D41. 3776a1d52896SBill Paul */ 3777888b47f0SPyun YongHyeon if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3778888b47f0SPyun YongHyeon hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 37795fea260fSMarius Strobl else if ((sc->bge_flags & BGE_FLAG_EADDR) && 37805fea260fSMarius Strobl (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3781f6789fbaSPyun YongHyeon if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3782f6789fbaSPyun YongHyeon sizeof(hwcfg))) { 3783fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3784f6789fbaSPyun YongHyeon error = ENXIO; 3785f6789fbaSPyun YongHyeon goto fail; 3786f6789fbaSPyun YongHyeon } 378741abcc1bSPaul Saab hwcfg = ntohl(hwcfg); 378841abcc1bSPaul Saab } 378941abcc1bSPaul Saab 379095d67482SBill Paul /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3791ea3b4127SPyun YongHyeon if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3792ea3b4127SPyun YongHyeon SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 379370c2071bSPyun YongHyeon if (BGE_IS_5705_PLUS(sc)) { 3794ea3b4127SPyun YongHyeon sc->bge_flags |= BGE_FLAG_MII_SERDES; 379570c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 379670c2071bSPyun YongHyeon } else 3797652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_TBI; 3798ea3b4127SPyun YongHyeon } 379995d67482SBill Paul 380070c2071bSPyun YongHyeon /* Set various PHY bug flags. */ 380170c2071bSPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 380270c2071bSPyun YongHyeon sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 380370c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 380470c2071bSPyun YongHyeon if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 380570c2071bSPyun YongHyeon sc->bge_chiprev == BGE_CHIPREV_5704_AX) 380670c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 380770c2071bSPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 380870c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 380970c2071bSPyun YongHyeon if (pci_get_subvendor(dev) == DELL_VENDORID) 381070c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_NO_3LED; 381170c2071bSPyun YongHyeon if ((BGE_IS_5705_PLUS(sc)) && 381270c2071bSPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5906 && 381370c2071bSPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3814fe26ad88SPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3815fe26ad88SPyun YongHyeon !BGE_IS_5717_PLUS(sc)) { 381670c2071bSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 381770c2071bSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5761 || 381870c2071bSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5784 || 381970c2071bSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5787) { 382070c2071bSPyun YongHyeon if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 382170c2071bSPyun YongHyeon pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 382270c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 382370c2071bSPyun YongHyeon if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 382470c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 382570c2071bSPyun YongHyeon } else 382670c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_BER_BUG; 382770c2071bSPyun YongHyeon } 382870c2071bSPyun YongHyeon 382970c2071bSPyun YongHyeon /* 3830d73ea7c6SPyun YongHyeon * Don't enable Ethernet@WireSpeed for the 5700 or the 383170c2071bSPyun YongHyeon * 5705 A0 and A1 chips. 383270c2071bSPyun YongHyeon */ 383370c2071bSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 383470c2071bSPyun YongHyeon (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 383570c2071bSPyun YongHyeon (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3836d73ea7c6SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 383770c2071bSPyun YongHyeon sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 383870c2071bSPyun YongHyeon 3839652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 3840*09a8241fSGleb Smirnoff ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 38410c8aa4eaSJung-uk Kim bge_ifmedia_sts); 38420c8aa4eaSJung-uk Kim ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 38436098821cSJung-uk Kim ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 38446098821cSJung-uk Kim 0, NULL); 384595d67482SBill Paul ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 384695d67482SBill Paul ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3847da3003f0SBill Paul sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 384895d67482SBill Paul } else { 384995d67482SBill Paul /* 38508cb1383cSDoug Ambrisko * Do transceiver setup and tell the firmware the 38518cb1383cSDoug Ambrisko * driver is down so we can try to get access the 38528cb1383cSDoug Ambrisko * probe if ASF is running. Retry a couple of times 38538cb1383cSDoug Ambrisko * if we get a conflict with the ASF firmware accessing 38548cb1383cSDoug Ambrisko * the PHY. 385595d67482SBill Paul */ 38564012d104SMarius Strobl trys = 0; 38578cb1383cSDoug Ambrisko BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 38588cb1383cSDoug Ambrisko again: 38598cb1383cSDoug Ambrisko bge_asf_driver_up(sc); 38608cb1383cSDoug Ambrisko 3861fba8b109SMarcel Moolenaar error = mii_attach(dev, &sc->bge_miibus, ifp, 3862fba8b109SMarcel Moolenaar (ifm_change_cb_t)bge_ifmedia_upd, 3863fba8b109SMarcel Moolenaar (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3864fba8b109SMarcel Moolenaar MII_OFFSET_ANY, MIIF_DOPAUSE); 38658e5d93dbSMarius Strobl if (error != 0) { 38668cb1383cSDoug Ambrisko if (trys++ < 4) { 38678cb1383cSDoug Ambrisko device_printf(sc->bge_dev, "Try again\n"); 3868daeeb75cSPyun YongHyeon bge_miibus_writereg(sc->bge_dev, 3869daeeb75cSPyun YongHyeon sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 38708cb1383cSDoug Ambrisko goto again; 38718cb1383cSDoug Ambrisko } 38728e5d93dbSMarius Strobl device_printf(sc->bge_dev, "attaching PHYs failed\n"); 387395d67482SBill Paul goto fail; 387495d67482SBill Paul } 38758cb1383cSDoug Ambrisko 38768cb1383cSDoug Ambrisko /* 38778cb1383cSDoug Ambrisko * Now tell the firmware we are going up after probing the PHY 38788cb1383cSDoug Ambrisko */ 38798cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 38808cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 388195d67482SBill Paul } 388295d67482SBill Paul 388395d67482SBill Paul /* 3884e255b776SJohn Polstra * When using the BCM5701 in PCI-X mode, data corruption has 3885e255b776SJohn Polstra * been observed in the first few bytes of some received packets. 3886e255b776SJohn Polstra * Aligning the packet buffer in memory eliminates the corruption. 3887e255b776SJohn Polstra * Unfortunately, this misaligns the packet payloads. On platforms 3888e255b776SJohn Polstra * which do not support unaligned accesses, we will realign the 3889e255b776SJohn Polstra * payloads by copying the received packets. 3890e255b776SJohn Polstra */ 3891652ae483SGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3892652ae483SGleb Smirnoff sc->bge_flags & BGE_FLAG_PCIX) 3893652ae483SGleb Smirnoff sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3894e255b776SJohn Polstra 3895e255b776SJohn Polstra /* 389695d67482SBill Paul * Call MI attach routine. 389795d67482SBill Paul */ 3898fc74a9f9SBrooks Davis ether_ifattach(ifp, eaddr); 38990f9bd73bSSam Leffler 390061ccb9daSPyun YongHyeon /* Tell upper layer we support long frames. */ 3901fba8b109SMarcel Moolenaar if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 390261ccb9daSPyun YongHyeon 39030f9bd73bSSam Leffler /* 39040f9bd73bSSam Leffler * Hookup IRQ last. 39050f9bd73bSSam Leffler */ 3906dfe0df9aSPyun YongHyeon if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3907dfe0df9aSPyun YongHyeon /* Take advantage of single-shot MSI. */ 39087e6acdf1SPyun YongHyeon CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 39097e6acdf1SPyun YongHyeon ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3910dfe0df9aSPyun YongHyeon sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3911dfe0df9aSPyun YongHyeon taskqueue_thread_enqueue, &sc->bge_tq); 3912dfe0df9aSPyun YongHyeon if (sc->bge_tq == NULL) { 3913dfe0df9aSPyun YongHyeon device_printf(dev, "could not create taskqueue.\n"); 3914dfe0df9aSPyun YongHyeon ether_ifdetach(ifp); 3915e010b055SPyun YongHyeon error = ENOMEM; 3916dfe0df9aSPyun YongHyeon goto fail; 3917dfe0df9aSPyun YongHyeon } 3918d7acafa1SMarius Strobl error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3919d7acafa1SMarius Strobl "%s taskq", device_get_nameunit(sc->bge_dev)); 3920d7acafa1SMarius Strobl if (error != 0) { 3921d7acafa1SMarius Strobl device_printf(dev, "could not start threads.\n"); 3922d7acafa1SMarius Strobl ether_ifdetach(ifp); 3923d7acafa1SMarius Strobl goto fail; 3924d7acafa1SMarius Strobl } 3925dfe0df9aSPyun YongHyeon error = bus_setup_intr(dev, sc->bge_irq, 3926dfe0df9aSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3927dfe0df9aSPyun YongHyeon &sc->bge_intrhand); 3928dfe0df9aSPyun YongHyeon } else 3929dfe0df9aSPyun YongHyeon error = bus_setup_intr(dev, sc->bge_irq, 3930dfe0df9aSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3931dfe0df9aSPyun YongHyeon &sc->bge_intrhand); 39320f9bd73bSSam Leffler 39330f9bd73bSSam Leffler if (error) { 3934e010b055SPyun YongHyeon ether_ifdetach(ifp); 3935fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "couldn't set up irq\n"); 39360f9bd73bSSam Leffler } 393795d67482SBill Paul 393895d67482SBill Paul fail: 3939e010b055SPyun YongHyeon if (error) 3940e010b055SPyun YongHyeon bge_detach(dev); 394195d67482SBill Paul return (error); 394295d67482SBill Paul } 394395d67482SBill Paul 394495d67482SBill Paul static int 39453f74909aSGleb Smirnoff bge_detach(device_t dev) 394695d67482SBill Paul { 394795d67482SBill Paul struct bge_softc *sc; 3948fba8b109SMarcel Moolenaar if_t ifp; 394995d67482SBill Paul 395095d67482SBill Paul sc = device_get_softc(dev); 3951fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 395295d67482SBill Paul 395375719184SGleb Smirnoff #ifdef DEVICE_POLLING 3954fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_POLLING) 395575719184SGleb Smirnoff ether_poll_deregister(ifp); 395675719184SGleb Smirnoff #endif 395775719184SGleb Smirnoff 3958e010b055SPyun YongHyeon if (device_is_attached(dev)) { 3959e010b055SPyun YongHyeon ether_ifdetach(ifp); 39600f9bd73bSSam Leffler BGE_LOCK(sc); 396195d67482SBill Paul bge_stop(sc); 39620f9bd73bSSam Leffler BGE_UNLOCK(sc); 39635dda8085SOleg Bulyzhin callout_drain(&sc->bge_stat_ch); 3964e010b055SPyun YongHyeon } 39655dda8085SOleg Bulyzhin 3966dfe0df9aSPyun YongHyeon if (sc->bge_tq) 3967dfe0df9aSPyun YongHyeon taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 396895d67482SBill Paul 39690aba72ddSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TBI) 397095d67482SBill Paul ifmedia_removeall(&sc->bge_ifmedia); 39710aba72ddSPyun YongHyeon else if (sc->bge_miibus != NULL) { 397295d67482SBill Paul bus_generic_detach(dev); 397395d67482SBill Paul device_delete_child(dev, sc->bge_miibus); 397495d67482SBill Paul } 397595d67482SBill Paul 397695d67482SBill Paul bge_release_resources(sc); 397795d67482SBill Paul 397895d67482SBill Paul return (0); 397995d67482SBill Paul } 398095d67482SBill Paul 398195d67482SBill Paul static void 39823f74909aSGleb Smirnoff bge_release_resources(struct bge_softc *sc) 398395d67482SBill Paul { 398495d67482SBill Paul device_t dev; 398595d67482SBill Paul 398695d67482SBill Paul dev = sc->bge_dev; 398795d67482SBill Paul 3988dfe0df9aSPyun YongHyeon if (sc->bge_tq != NULL) 3989dfe0df9aSPyun YongHyeon taskqueue_free(sc->bge_tq); 3990dfe0df9aSPyun YongHyeon 399195d67482SBill Paul if (sc->bge_intrhand != NULL) 399295d67482SBill Paul bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 399395d67482SBill Paul 3994ad4328baSMarius Strobl if (sc->bge_irq != NULL) { 3995724bd939SJohn Polstra bus_release_resource(dev, SYS_RES_IRQ, 3996ad4328baSMarius Strobl rman_get_rid(sc->bge_irq), sc->bge_irq); 3997724bd939SJohn Polstra pci_release_msi(dev); 3998ad4328baSMarius Strobl } 399995d67482SBill Paul 400095d67482SBill Paul if (sc->bge_res != NULL) 400195d67482SBill Paul bus_release_resource(dev, SYS_RES_MEMORY, 4002ad4328baSMarius Strobl rman_get_rid(sc->bge_res), sc->bge_res); 400395d67482SBill Paul 4004548c8f1aSPyun YongHyeon if (sc->bge_res2 != NULL) 4005548c8f1aSPyun YongHyeon bus_release_resource(dev, SYS_RES_MEMORY, 4006ad4328baSMarius Strobl rman_get_rid(sc->bge_res2), sc->bge_res2); 4007548c8f1aSPyun YongHyeon 4008ad61f896SRuslan Ermilov if (sc->bge_ifp != NULL) 4009ad61f896SRuslan Ermilov if_free(sc->bge_ifp); 4010ad61f896SRuslan Ermilov 4011f41ac2beSBill Paul bge_dma_free(sc); 401295d67482SBill Paul 40130f9bd73bSSam Leffler if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 40140f9bd73bSSam Leffler BGE_LOCK_DESTROY(sc); 401595d67482SBill Paul } 401695d67482SBill Paul 40178cb1383cSDoug Ambrisko static int 40183f74909aSGleb Smirnoff bge_reset(struct bge_softc *sc) 401995d67482SBill Paul { 402095d67482SBill Paul device_t dev; 4021cc085b36SPyun YongHyeon uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 40226f8718a3SScott Long void (*write_op)(struct bge_softc *, int, int); 40230aaf1057SPyun YongHyeon uint16_t devctl; 40245fea260fSMarius Strobl int i; 402595d67482SBill Paul 402695d67482SBill Paul dev = sc->bge_dev; 402795d67482SBill Paul 4028cc085b36SPyun YongHyeon mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4029548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4030548c8f1aSPyun YongHyeon mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4031cc085b36SPyun YongHyeon mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4032cc085b36SPyun YongHyeon 403338cc658fSJohn Baldwin if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 403438cc658fSJohn Baldwin (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 40356f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIE) 40366f8718a3SScott Long write_op = bge_writemem_direct; 40376f8718a3SScott Long else 40386f8718a3SScott Long write_op = bge_writemem_ind; 40399ba784dbSScott Long } else 40406f8718a3SScott Long write_op = bge_writereg_ind; 40416f8718a3SScott Long 40423dd76c98SPyun YongHyeon if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 40433dd76c98SPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5701) { 40443dd76c98SPyun YongHyeon CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 40453dd76c98SPyun YongHyeon for (i = 0; i < 8000; i++) { 40463dd76c98SPyun YongHyeon if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 40473dd76c98SPyun YongHyeon BGE_NVRAMSWARB_GNT1) 40483dd76c98SPyun YongHyeon break; 40493dd76c98SPyun YongHyeon DELAY(20); 40503dd76c98SPyun YongHyeon } 40513dd76c98SPyun YongHyeon if (i == 8000) { 40523dd76c98SPyun YongHyeon if (bootverbose) 40533dd76c98SPyun YongHyeon device_printf(dev, "NVRAM lock timedout!\n"); 40543dd76c98SPyun YongHyeon } 40553dd76c98SPyun YongHyeon } 4056548c8f1aSPyun YongHyeon /* Take APE lock when performing reset. */ 4057548c8f1aSPyun YongHyeon bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4058548c8f1aSPyun YongHyeon 405995d67482SBill Paul /* Save some important PCI state. */ 406095d67482SBill Paul cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 406195d67482SBill Paul command = pci_read_config(dev, BGE_PCI_CMD, 4); 406295d67482SBill Paul 406395d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 406495d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4065e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 406695d67482SBill Paul 40676f8718a3SScott Long /* Disable fastboot on controllers that support it. */ 40686f8718a3SScott Long if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4069a5779553SStanislav Sedov BGE_IS_5755_PLUS(sc)) { 40706f8718a3SScott Long if (bootverbose) 4071333704a3SPyun YongHyeon device_printf(dev, "Disabling fastboot\n"); 40726f8718a3SScott Long CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 40736f8718a3SScott Long } 40746f8718a3SScott Long 40756f8718a3SScott Long /* 40766f8718a3SScott Long * Write the magic number to SRAM at offset 0xB50. 40776f8718a3SScott Long * When firmware finishes its initialization it will 4078888b47f0SPyun YongHyeon * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 40796f8718a3SScott Long */ 4080888b47f0SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 40816f8718a3SScott Long 40820c8aa4eaSJung-uk Kim reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4083e53d81eeSPaul Saab 4084e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 4085652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 4086ad49eccfSPyun YongHyeon if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4087ad49eccfSPyun YongHyeon (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 40880c8aa4eaSJung-uk Kim if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 40890c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, 0x7E2C, 0x20); 4090ad49eccfSPyun YongHyeon } 4091e53d81eeSPaul Saab if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4092e53d81eeSPaul Saab /* Prevent PCIE link training during global reset */ 40930c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 40940c8aa4eaSJung-uk Kim reset |= 1 << 29; 4095e53d81eeSPaul Saab } 4096e53d81eeSPaul Saab } 4097e53d81eeSPaul Saab 4098df4db538SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4099df4db538SPyun YongHyeon val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4100df4db538SPyun YongHyeon CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4101df4db538SPyun YongHyeon val | BGE_VCPU_STATUS_DRV_RESET); 4102df4db538SPyun YongHyeon val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4103df4db538SPyun YongHyeon CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4104df4db538SPyun YongHyeon val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4105df4db538SPyun YongHyeon } 4106df4db538SPyun YongHyeon 410721c9e407SDavid Christensen /* 41086f8718a3SScott Long * Set GPHY Power Down Override to leave GPHY 41096f8718a3SScott Long * powered up in D0 uninitialized. 41106f8718a3SScott Long */ 41115512ca01SPyun YongHyeon if (BGE_IS_5705_PLUS(sc) && 41125512ca01SPyun YongHyeon (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4113caf088fcSPyun YongHyeon reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 41146f8718a3SScott Long 411595d67482SBill Paul /* Issue global reset */ 41166f8718a3SScott Long write_op(sc, BGE_MISC_CFG, reset); 411795d67482SBill Paul 4118cc085b36SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_PCIE) 4119cc085b36SPyun YongHyeon DELAY(100 * 1000); 4120cc085b36SPyun YongHyeon else 412195d67482SBill Paul DELAY(1000); 412295d67482SBill Paul 4123e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 4124652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE) { 4125e53d81eeSPaul Saab if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4126e53d81eeSPaul Saab DELAY(500000); /* wait for link training to complete */ 41275fea260fSMarius Strobl val = pci_read_config(dev, 0xC4, 4); 41285fea260fSMarius Strobl pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4129e53d81eeSPaul Saab } 41300aaf1057SPyun YongHyeon devctl = pci_read_config(dev, 4131389c8bd5SGavin Atkinson sc->bge_expcap + PCIER_DEVICE_CTL, 2); 41320aaf1057SPyun YongHyeon /* Clear enable no snoop and disable relaxed ordering. */ 4133389c8bd5SGavin Atkinson devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4134389c8bd5SGavin Atkinson PCIEM_CTL_NOSNOOP_ENABLE); 4135389c8bd5SGavin Atkinson pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 41360aaf1057SPyun YongHyeon devctl, 2); 413748630d79SPyun YongHyeon pci_set_max_read_req(dev, sc->bge_expmrq); 41380aaf1057SPyun YongHyeon /* Clear error status. */ 4139389c8bd5SGavin Atkinson pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4140389c8bd5SGavin Atkinson PCIEM_STA_CORRECTABLE_ERROR | 4141389c8bd5SGavin Atkinson PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4142389c8bd5SGavin Atkinson PCIEM_STA_UNSUPPORTED_REQ, 2); 4143e53d81eeSPaul Saab } 4144e53d81eeSPaul Saab 41453f74909aSGleb Smirnoff /* Reset some of the PCI state that got zapped by reset. */ 414695d67482SBill Paul pci_write_config(dev, BGE_PCI_MISC_CTL, 414795d67482SBill Paul BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4148e907febfSPyun YongHyeon BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4149cc085b36SPyun YongHyeon val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4150cc085b36SPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4151cc085b36SPyun YongHyeon (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4152cc085b36SPyun YongHyeon val |= BGE_PCISTATE_RETRY_SAME_DMA; 4153548c8f1aSPyun YongHyeon if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4154548c8f1aSPyun YongHyeon val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4155548c8f1aSPyun YongHyeon BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4156548c8f1aSPyun YongHyeon BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4157cc085b36SPyun YongHyeon pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 415895d67482SBill Paul pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 415995d67482SBill Paul pci_write_config(dev, BGE_PCI_CMD, command, 4); 4160cbb2b2feSPyun YongHyeon /* 4161cbb2b2feSPyun YongHyeon * Disable PCI-X relaxed ordering to ensure status block update 4162fa8b4d63SPyun YongHyeon * comes first then packet buffer DMA. Otherwise driver may 4163cbb2b2feSPyun YongHyeon * read stale status block. 4164cbb2b2feSPyun YongHyeon */ 4165cbb2b2feSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_PCIX) { 4166cbb2b2feSPyun YongHyeon devctl = pci_read_config(dev, 4167cbb2b2feSPyun YongHyeon sc->bge_pcixcap + PCIXR_COMMAND, 2); 4168cbb2b2feSPyun YongHyeon devctl &= ~PCIXM_COMMAND_ERO; 4169cbb2b2feSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4170cbb2b2feSPyun YongHyeon devctl &= ~PCIXM_COMMAND_MAX_READ; 4171cbb2b2feSPyun YongHyeon devctl |= PCIXM_COMMAND_MAX_READ_2048; 4172cbb2b2feSPyun YongHyeon } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4173cbb2b2feSPyun YongHyeon devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4174cbb2b2feSPyun YongHyeon PCIXM_COMMAND_MAX_READ); 4175cbb2b2feSPyun YongHyeon devctl |= PCIXM_COMMAND_MAX_READ_2048; 4176cbb2b2feSPyun YongHyeon } 4177cbb2b2feSPyun YongHyeon pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4178cbb2b2feSPyun YongHyeon devctl, 2); 4179cbb2b2feSPyun YongHyeon } 418022a4ecedSMarius Strobl /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 41814c0da0ffSGleb Smirnoff if (BGE_IS_5714_FAMILY(sc)) { 4182bf6ef57aSJohn Polstra /* This chip disables MSI on reset. */ 4183bf6ef57aSJohn Polstra if (sc->bge_flags & BGE_FLAG_MSI) { 41840aaf1057SPyun YongHyeon val = pci_read_config(dev, 41850aaf1057SPyun YongHyeon sc->bge_msicap + PCIR_MSI_CTRL, 2); 41860aaf1057SPyun YongHyeon pci_write_config(dev, 41870aaf1057SPyun YongHyeon sc->bge_msicap + PCIR_MSI_CTRL, 4188bf6ef57aSJohn Polstra val | PCIM_MSICTRL_MSI_ENABLE, 2); 4189bf6ef57aSJohn Polstra val = CSR_READ_4(sc, BGE_MSI_MODE); 4190bf6ef57aSJohn Polstra CSR_WRITE_4(sc, BGE_MSI_MODE, 4191bf6ef57aSJohn Polstra val | BGE_MSIMODE_ENABLE); 4192bf6ef57aSJohn Polstra } 41934c0da0ffSGleb Smirnoff val = CSR_READ_4(sc, BGE_MARB_MODE); 41944c0da0ffSGleb Smirnoff CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 41954c0da0ffSGleb Smirnoff } else 4196a7b0c314SPaul Saab CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4197a7b0c314SPaul Saab 4198cc085b36SPyun YongHyeon /* Fix up byte swapping. */ 4199cc085b36SPyun YongHyeon CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4200cc085b36SPyun YongHyeon 4201cc085b36SPyun YongHyeon val = CSR_READ_4(sc, BGE_MAC_MODE); 4202cc085b36SPyun YongHyeon val = (val & ~mac_mode_mask) | mac_mode; 4203cc085b36SPyun YongHyeon CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4204cc085b36SPyun YongHyeon DELAY(40); 4205cc085b36SPyun YongHyeon 4206548c8f1aSPyun YongHyeon bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4207548c8f1aSPyun YongHyeon 420838cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 420938cc658fSJohn Baldwin for (i = 0; i < BGE_TIMEOUT; i++) { 421038cc658fSJohn Baldwin val = CSR_READ_4(sc, BGE_VCPU_STATUS); 421138cc658fSJohn Baldwin if (val & BGE_VCPU_STATUS_INIT_DONE) 421238cc658fSJohn Baldwin break; 421338cc658fSJohn Baldwin DELAY(100); 421438cc658fSJohn Baldwin } 421538cc658fSJohn Baldwin if (i == BGE_TIMEOUT) { 4216333704a3SPyun YongHyeon device_printf(dev, "reset timed out\n"); 421738cc658fSJohn Baldwin return (1); 421838cc658fSJohn Baldwin } 421938cc658fSJohn Baldwin } else { 422095d67482SBill Paul /* 42216f8718a3SScott Long * Poll until we see the 1's complement of the magic number. 422208013fd3SMarius Strobl * This indicates that the firmware initialization is complete. 42235fea260fSMarius Strobl * We expect this to fail if no chip containing the Ethernet 42245fea260fSMarius Strobl * address is fitted though. 422595d67482SBill Paul */ 422695d67482SBill Paul for (i = 0; i < BGE_TIMEOUT; i++) { 4227d5d23857SJung-uk Kim DELAY(10); 4228888b47f0SPyun YongHyeon val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4229888b47f0SPyun YongHyeon if (val == ~BGE_SRAM_FW_MB_MAGIC) 423095d67482SBill Paul break; 423195d67482SBill Paul } 423295d67482SBill Paul 42335fea260fSMarius Strobl if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4234333704a3SPyun YongHyeon device_printf(dev, 4235333704a3SPyun YongHyeon "firmware handshake timed out, found 0x%08x\n", 4236333704a3SPyun YongHyeon val); 4237b4a256acSPyun YongHyeon /* BCM57765 A0 needs additional time before accessing. */ 4238b4a256acSPyun YongHyeon if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4239b4a256acSPyun YongHyeon DELAY(10 * 1000); /* XXX */ 424038cc658fSJohn Baldwin } 424195d67482SBill Paul 424295d67482SBill Paul /* 4243da3003f0SBill Paul * The 5704 in TBI mode apparently needs some special 4244da3003f0SBill Paul * adjustment to insure the SERDES drive level is set 4245da3003f0SBill Paul * to 1.2V. 4246da3003f0SBill Paul */ 4247652ae483SGleb Smirnoff if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4248652ae483SGleb Smirnoff sc->bge_flags & BGE_FLAG_TBI) { 42495fea260fSMarius Strobl val = CSR_READ_4(sc, BGE_SERDES_CFG); 42505fea260fSMarius Strobl val = (val & ~0xFFF) | 0x880; 42515fea260fSMarius Strobl CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4252da3003f0SBill Paul } 4253da3003f0SBill Paul 4254e53d81eeSPaul Saab /* XXX: Broadcom Linux driver. */ 4255652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_PCIE && 4256b4a256acSPyun YongHyeon !BGE_IS_5717_PLUS(sc) && 4257a5ad2f15SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4258a5ad2f15SPyun YongHyeon sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4259a5ad2f15SPyun YongHyeon /* Enable Data FIFO protection. */ 42605fea260fSMarius Strobl val = CSR_READ_4(sc, 0x7C00); 42615fea260fSMarius Strobl CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4262e53d81eeSPaul Saab } 42638cb1383cSDoug Ambrisko 426450515680SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 426550515680SPyun YongHyeon BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 426650515680SPyun YongHyeon CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 426750515680SPyun YongHyeon 42688cb1383cSDoug Ambrisko return (0); 426995d67482SBill Paul } 427095d67482SBill Paul 4271e0b7b101SPyun YongHyeon static __inline void 4272e0b7b101SPyun YongHyeon bge_rxreuse_std(struct bge_softc *sc, int i) 4273e0b7b101SPyun YongHyeon { 4274e0b7b101SPyun YongHyeon struct bge_rx_bd *r; 4275e0b7b101SPyun YongHyeon 4276e0b7b101SPyun YongHyeon r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4277e0b7b101SPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_END; 4278e0b7b101SPyun YongHyeon r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4279e0b7b101SPyun YongHyeon r->bge_idx = i; 4280e0b7b101SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4281e0b7b101SPyun YongHyeon } 4282e0b7b101SPyun YongHyeon 4283e0b7b101SPyun YongHyeon static __inline void 4284e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4285e0b7b101SPyun YongHyeon { 4286e0b7b101SPyun YongHyeon struct bge_extrx_bd *r; 4287e0b7b101SPyun YongHyeon 4288e0b7b101SPyun YongHyeon r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4289e0b7b101SPyun YongHyeon r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4290e0b7b101SPyun YongHyeon r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4291e0b7b101SPyun YongHyeon r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4292e0b7b101SPyun YongHyeon r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4293e0b7b101SPyun YongHyeon r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4294e0b7b101SPyun YongHyeon r->bge_idx = i; 4295e0b7b101SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4296e0b7b101SPyun YongHyeon } 4297e0b7b101SPyun YongHyeon 429895d67482SBill Paul /* 429995d67482SBill Paul * Frame reception handling. This is called if there's a frame 430095d67482SBill Paul * on the receive return list. 430195d67482SBill Paul * 430295d67482SBill Paul * Note: we have to be able to handle two possibilities here: 43031be6acb7SGleb Smirnoff * 1) the frame is from the jumbo receive ring 430495d67482SBill Paul * 2) the frame is from the standard receive ring 430595d67482SBill Paul */ 430695d67482SBill Paul 43071abcdbd1SAttilio Rao static int 4308dfe0df9aSPyun YongHyeon bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 430995d67482SBill Paul { 4310fba8b109SMarcel Moolenaar if_t ifp; 43111abcdbd1SAttilio Rao int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4312b9c05fa5SPyun YongHyeon uint16_t rx_cons; 431395d67482SBill Paul 43147f21e273SStanislav Sedov rx_cons = sc->bge_rx_saved_considx; 43150f9bd73bSSam Leffler 43163f74909aSGleb Smirnoff /* Nothing to do. */ 43177f21e273SStanislav Sedov if (rx_cons == rx_prod) 43181abcdbd1SAttilio Rao return (rx_npkts); 4319cfcb5025SOleg Bulyzhin 4320fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 432195d67482SBill Paul 4322f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4323e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4324f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 432515eda801SStanislav Sedov sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4326f5459d4cSPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc) && 4327fba8b109SMarcel Moolenaar if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4328fba8b109SMarcel Moolenaar ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4329f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 433015eda801SStanislav Sedov sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4331f41ac2beSBill Paul 43327f21e273SStanislav Sedov while (rx_cons != rx_prod) { 433395d67482SBill Paul struct bge_rx_bd *cur_rx; 43343f74909aSGleb Smirnoff uint32_t rxidx; 433595d67482SBill Paul struct mbuf *m = NULL; 43363f74909aSGleb Smirnoff uint16_t vlan_tag = 0; 433795d67482SBill Paul int have_tag = 0; 433895d67482SBill Paul 433975719184SGleb Smirnoff #ifdef DEVICE_POLLING 4340fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_POLLING) { 434175719184SGleb Smirnoff if (sc->rxcycles <= 0) 434275719184SGleb Smirnoff break; 434375719184SGleb Smirnoff sc->rxcycles--; 434475719184SGleb Smirnoff } 434575719184SGleb Smirnoff #endif 434675719184SGleb Smirnoff 43477f21e273SStanislav Sedov cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 434895d67482SBill Paul 434995d67482SBill Paul rxidx = cur_rx->bge_idx; 43507f21e273SStanislav Sedov BGE_INC(rx_cons, sc->bge_return_ring_cnt); 435195d67482SBill Paul 4352fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4353cb2eacc7SYaroslav Tykhiy cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 435495d67482SBill Paul have_tag = 1; 435595d67482SBill Paul vlan_tag = cur_rx->bge_vlan_tag; 435695d67482SBill Paul } 435795d67482SBill Paul 435895d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 435995d67482SBill Paul jumbocnt++; 4360943787f3SPyun YongHyeon m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 436195d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4362e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(sc, rxidx); 436395d67482SBill Paul continue; 436495d67482SBill Paul } 4365943787f3SPyun YongHyeon if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4366e0b7b101SPyun YongHyeon bge_rxreuse_jumbo(sc, rxidx); 4367fba8b109SMarcel Moolenaar if_inciqdrops(ifp, 1); 436895d67482SBill Paul continue; 436995d67482SBill Paul } 437003e78bd0SPyun YongHyeon BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 437195d67482SBill Paul } else { 437295d67482SBill Paul stdcnt++; 4373e0b7b101SPyun YongHyeon m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 437495d67482SBill Paul if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4375e0b7b101SPyun YongHyeon bge_rxreuse_std(sc, rxidx); 437695d67482SBill Paul continue; 437795d67482SBill Paul } 4378943787f3SPyun YongHyeon if (bge_newbuf_std(sc, rxidx) != 0) { 4379e0b7b101SPyun YongHyeon bge_rxreuse_std(sc, rxidx); 4380fba8b109SMarcel Moolenaar if_inciqdrops(ifp, 1); 438195d67482SBill Paul continue; 438295d67482SBill Paul } 438303e78bd0SPyun YongHyeon BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 438495d67482SBill Paul } 438595d67482SBill Paul 4386fba8b109SMarcel Moolenaar if_incipackets(ifp, 1); 4387e65bed95SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 4388e255b776SJohn Polstra /* 4389e65bed95SPyun YongHyeon * For architectures with strict alignment we must make sure 4390e65bed95SPyun YongHyeon * the payload is aligned. 4391e255b776SJohn Polstra */ 4392652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4393e255b776SJohn Polstra bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4394e255b776SJohn Polstra cur_rx->bge_len); 4395e255b776SJohn Polstra m->m_data += ETHER_ALIGN; 4396e255b776SJohn Polstra } 4397e255b776SJohn Polstra #endif 4398473851baSPaul Saab m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 439995d67482SBill Paul m->m_pkthdr.rcvif = ifp; 440095d67482SBill Paul 4401fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_RXCSUM) 44021108273aSPyun YongHyeon bge_rxcsum(sc, cur_rx, m); 440395d67482SBill Paul 440495d67482SBill Paul /* 4405673d9191SSam Leffler * If we received a packet with a vlan tag, 4406673d9191SSam Leffler * attach that information to the packet. 440795d67482SBill Paul */ 4408d147662cSGleb Smirnoff if (have_tag) { 440978ba57b9SAndre Oppermann m->m_pkthdr.ether_vtag = vlan_tag; 441078ba57b9SAndre Oppermann m->m_flags |= M_VLANTAG; 4411d147662cSGleb Smirnoff } 441295d67482SBill Paul 4413dfe0df9aSPyun YongHyeon if (holdlck != 0) { 44140f9bd73bSSam Leffler BGE_UNLOCK(sc); 4415fba8b109SMarcel Moolenaar if_input(ifp, m); 44160f9bd73bSSam Leffler BGE_LOCK(sc); 4417dfe0df9aSPyun YongHyeon } else 4418fba8b109SMarcel Moolenaar if_input(ifp, m); 4419d4da719cSAttilio Rao rx_npkts++; 442025e13e68SXin LI 4421fba8b109SMarcel Moolenaar if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 44228cf7d13dSAttilio Rao return (rx_npkts); 442395d67482SBill Paul } 442495d67482SBill Paul 442515eda801SStanislav Sedov bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 442615eda801SStanislav Sedov sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4427e65bed95SPyun YongHyeon if (stdcnt > 0) 4428f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4429e65bed95SPyun YongHyeon sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 44304c0da0ffSGleb Smirnoff 4431c215fd77SPyun YongHyeon if (jumbocnt > 0) 4432f41ac2beSBill Paul bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 44334c0da0ffSGleb Smirnoff sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4434f41ac2beSBill Paul 44357f21e273SStanislav Sedov sc->bge_rx_saved_considx = rx_cons; 443638cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 443795d67482SBill Paul if (stdcnt) 4438767c3593SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4439767c3593SPyun YongHyeon BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 444095d67482SBill Paul if (jumbocnt) 4441767c3593SPyun YongHyeon bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4442767c3593SPyun YongHyeon BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4443f5a034f9SPyun YongHyeon #ifdef notyet 4444f5a034f9SPyun YongHyeon /* 4445f5a034f9SPyun YongHyeon * This register wraps very quickly under heavy packet drops. 4446f5a034f9SPyun YongHyeon * If you need correct statistics, you can enable this check. 4447f5a034f9SPyun YongHyeon */ 4448f5a034f9SPyun YongHyeon if (BGE_IS_5705_PLUS(sc)) 4449fba8b109SMarcel Moolenaar if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4450f5a034f9SPyun YongHyeon #endif 44511abcdbd1SAttilio Rao return (rx_npkts); 445295d67482SBill Paul } 445395d67482SBill Paul 445495d67482SBill Paul static void 44551108273aSPyun YongHyeon bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 44561108273aSPyun YongHyeon { 44571108273aSPyun YongHyeon 44581108273aSPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) { 44591108273aSPyun YongHyeon if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 44601108273aSPyun YongHyeon if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 44611108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 44621108273aSPyun YongHyeon if ((cur_rx->bge_error_flag & 44631108273aSPyun YongHyeon BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 44641108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 44651108273aSPyun YongHyeon } 44661108273aSPyun YongHyeon if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 44671108273aSPyun YongHyeon m->m_pkthdr.csum_data = 44681108273aSPyun YongHyeon cur_rx->bge_tcp_udp_csum; 44691108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 44701108273aSPyun YongHyeon CSUM_PSEUDO_HDR; 44711108273aSPyun YongHyeon } 44721108273aSPyun YongHyeon } 44731108273aSPyun YongHyeon } else { 44741108273aSPyun YongHyeon if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 44751108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 44761108273aSPyun YongHyeon if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 44771108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 44781108273aSPyun YongHyeon } 44791108273aSPyun YongHyeon if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 44801108273aSPyun YongHyeon m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 44811108273aSPyun YongHyeon m->m_pkthdr.csum_data = 44821108273aSPyun YongHyeon cur_rx->bge_tcp_udp_csum; 44831108273aSPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 44841108273aSPyun YongHyeon CSUM_PSEUDO_HDR; 44851108273aSPyun YongHyeon } 44861108273aSPyun YongHyeon } 44871108273aSPyun YongHyeon } 44881108273aSPyun YongHyeon 44891108273aSPyun YongHyeon static void 4490b9c05fa5SPyun YongHyeon bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 449195d67482SBill Paul { 449295a0a340SPyun YongHyeon struct bge_tx_bd *cur_tx; 4493fba8b109SMarcel Moolenaar if_t ifp; 449495d67482SBill Paul 44950f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 44960f9bd73bSSam Leffler 44973f74909aSGleb Smirnoff /* Nothing to do. */ 4498b9c05fa5SPyun YongHyeon if (sc->bge_tx_saved_considx == tx_cons) 4499cfcb5025SOleg Bulyzhin return; 4500cfcb5025SOleg Bulyzhin 4501fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 450295d67482SBill Paul 4503e65bed95SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 45045c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 450595d67482SBill Paul /* 450695d67482SBill Paul * Go through our tx ring and free mbufs for those 450795d67482SBill Paul * frames that have been sent. 450895d67482SBill Paul */ 4509b9c05fa5SPyun YongHyeon while (sc->bge_tx_saved_considx != tx_cons) { 451095a0a340SPyun YongHyeon uint32_t idx; 451195d67482SBill Paul 451295d67482SBill Paul idx = sc->bge_tx_saved_considx; 4513f41ac2beSBill Paul cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 451495d67482SBill Paul if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4515fba8b109SMarcel Moolenaar if_incopackets(ifp, 1); 451695d67482SBill Paul if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 45170ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4518e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_dmamap[idx], 4519e65bed95SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 45200ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4521f41ac2beSBill Paul sc->bge_cdata.bge_tx_dmamap[idx]); 4522e65bed95SPyun YongHyeon m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4523e65bed95SPyun YongHyeon sc->bge_cdata.bge_tx_chain[idx] = NULL; 452495d67482SBill Paul } 452595d67482SBill Paul sc->bge_txcnt--; 452695d67482SBill Paul BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 452795d67482SBill Paul } 452895d67482SBill Paul 4529fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 45305b01e77cSBruce Evans if (sc->bge_txcnt == 0) 45315b01e77cSBruce Evans sc->bge_timer = 0; 453295d67482SBill Paul } 453395d67482SBill Paul 453475719184SGleb Smirnoff #ifdef DEVICE_POLLING 45351abcdbd1SAttilio Rao static int 4536fba8b109SMarcel Moolenaar bge_poll(if_t ifp, enum poll_cmd cmd, int count) 453775719184SGleb Smirnoff { 4538fba8b109SMarcel Moolenaar struct bge_softc *sc = if_getsoftc(ifp); 4539b9c05fa5SPyun YongHyeon uint16_t rx_prod, tx_cons; 4540366454f2SOleg Bulyzhin uint32_t statusword; 45411abcdbd1SAttilio Rao int rx_npkts = 0; 454275719184SGleb Smirnoff 45433f74909aSGleb Smirnoff BGE_LOCK(sc); 4544fba8b109SMarcel Moolenaar if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 45453f74909aSGleb Smirnoff BGE_UNLOCK(sc); 45461abcdbd1SAttilio Rao return (rx_npkts); 45473f74909aSGleb Smirnoff } 454875719184SGleb Smirnoff 4549dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4550b9c05fa5SPyun YongHyeon sc->bge_cdata.bge_status_map, 4551b9c05fa5SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 45522246e8c6SPyun YongHyeon /* Fetch updates from the status block. */ 4553b9c05fa5SPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4554b9c05fa5SPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4555dab5cd05SOleg Bulyzhin 4556175f8742SPyun YongHyeon statusword = sc->bge_ldata.bge_status_block->bge_status; 45572246e8c6SPyun YongHyeon /* Clear the status so the next pass only sees the changes. */ 4558175f8742SPyun YongHyeon sc->bge_ldata.bge_status_block->bge_status = 0; 4559dab5cd05SOleg Bulyzhin 4560dab5cd05SOleg Bulyzhin bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4561b9c05fa5SPyun YongHyeon sc->bge_cdata.bge_status_map, 4562b9c05fa5SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4563366454f2SOleg Bulyzhin 45640c8aa4eaSJung-uk Kim /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4565366454f2SOleg Bulyzhin if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4566366454f2SOleg Bulyzhin sc->bge_link_evt++; 4567366454f2SOleg Bulyzhin 4568366454f2SOleg Bulyzhin if (cmd == POLL_AND_CHECK_STATUS) 4569366454f2SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 45704c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4571652ae483SGleb Smirnoff sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4572366454f2SOleg Bulyzhin bge_link_upd(sc); 4573366454f2SOleg Bulyzhin 4574366454f2SOleg Bulyzhin sc->rxcycles = count; 4575dfe0df9aSPyun YongHyeon rx_npkts = bge_rxeof(sc, rx_prod, 1); 4576fba8b109SMarcel Moolenaar if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 457725e13e68SXin LI BGE_UNLOCK(sc); 45788cf7d13dSAttilio Rao return (rx_npkts); 457925e13e68SXin LI } 4580b9c05fa5SPyun YongHyeon bge_txeof(sc, tx_cons); 4581fba8b109SMarcel Moolenaar if (!if_sendq_empty(ifp)) 4582366454f2SOleg Bulyzhin bge_start_locked(ifp); 45833f74909aSGleb Smirnoff 45843f74909aSGleb Smirnoff BGE_UNLOCK(sc); 45851abcdbd1SAttilio Rao return (rx_npkts); 458675719184SGleb Smirnoff } 458775719184SGleb Smirnoff #endif /* DEVICE_POLLING */ 458875719184SGleb Smirnoff 4589dfe0df9aSPyun YongHyeon static int 4590dfe0df9aSPyun YongHyeon bge_msi_intr(void *arg) 4591dfe0df9aSPyun YongHyeon { 4592dfe0df9aSPyun YongHyeon struct bge_softc *sc; 4593dfe0df9aSPyun YongHyeon 4594dfe0df9aSPyun YongHyeon sc = (struct bge_softc *)arg; 4595dfe0df9aSPyun YongHyeon /* 4596dfe0df9aSPyun YongHyeon * This interrupt is not shared and controller already 4597dfe0df9aSPyun YongHyeon * disabled further interrupt. 4598dfe0df9aSPyun YongHyeon */ 4599dfe0df9aSPyun YongHyeon taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4600dfe0df9aSPyun YongHyeon return (FILTER_HANDLED); 4601dfe0df9aSPyun YongHyeon } 4602dfe0df9aSPyun YongHyeon 4603dfe0df9aSPyun YongHyeon static void 4604dfe0df9aSPyun YongHyeon bge_intr_task(void *arg, int pending) 4605dfe0df9aSPyun YongHyeon { 4606dfe0df9aSPyun YongHyeon struct bge_softc *sc; 4607fba8b109SMarcel Moolenaar if_t ifp; 46081108273aSPyun YongHyeon uint32_t status, status_tag; 4609dfe0df9aSPyun YongHyeon uint16_t rx_prod, tx_cons; 4610dfe0df9aSPyun YongHyeon 4611dfe0df9aSPyun YongHyeon sc = (struct bge_softc *)arg; 4612dfe0df9aSPyun YongHyeon ifp = sc->bge_ifp; 4613dfe0df9aSPyun YongHyeon 461466151edfSPyun YongHyeon BGE_LOCK(sc); 4615fba8b109SMarcel Moolenaar if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 461666151edfSPyun YongHyeon BGE_UNLOCK(sc); 4617dfe0df9aSPyun YongHyeon return; 461866151edfSPyun YongHyeon } 4619dfe0df9aSPyun YongHyeon 4620dfe0df9aSPyun YongHyeon /* Get updated status block. */ 4621dfe0df9aSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4622dfe0df9aSPyun YongHyeon sc->bge_cdata.bge_status_map, 4623dfe0df9aSPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4624dfe0df9aSPyun YongHyeon 46252246e8c6SPyun YongHyeon /* Save producer/consumer indices. */ 4626dfe0df9aSPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4627dfe0df9aSPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4628dfe0df9aSPyun YongHyeon status = sc->bge_ldata.bge_status_block->bge_status; 46291108273aSPyun YongHyeon status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 46302246e8c6SPyun YongHyeon /* Dirty the status flag. */ 4631dfe0df9aSPyun YongHyeon sc->bge_ldata.bge_status_block->bge_status = 0; 4632dfe0df9aSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4633dfe0df9aSPyun YongHyeon sc->bge_cdata.bge_status_map, 4634dfe0df9aSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 46351108273aSPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 46361108273aSPyun YongHyeon status_tag = 0; 463766151edfSPyun YongHyeon 463866151edfSPyun YongHyeon if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 463966151edfSPyun YongHyeon bge_link_upd(sc); 464066151edfSPyun YongHyeon 4641dfe0df9aSPyun YongHyeon /* Let controller work. */ 46421108273aSPyun YongHyeon bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4643dfe0df9aSPyun YongHyeon 4644fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 464566151edfSPyun YongHyeon sc->bge_rx_saved_considx != rx_prod) { 4646dfe0df9aSPyun YongHyeon /* Check RX return ring producer/consumer. */ 464766151edfSPyun YongHyeon BGE_UNLOCK(sc); 4648dfe0df9aSPyun YongHyeon bge_rxeof(sc, rx_prod, 0); 464966151edfSPyun YongHyeon BGE_LOCK(sc); 4650dfe0df9aSPyun YongHyeon } 4651fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4652dfe0df9aSPyun YongHyeon /* Check TX ring producer/consumer. */ 4653dfe0df9aSPyun YongHyeon bge_txeof(sc, tx_cons); 4654fba8b109SMarcel Moolenaar if (!if_sendq_empty(ifp)) 4655dfe0df9aSPyun YongHyeon bge_start_locked(ifp); 4656dfe0df9aSPyun YongHyeon } 465766151edfSPyun YongHyeon BGE_UNLOCK(sc); 4658dfe0df9aSPyun YongHyeon } 4659dfe0df9aSPyun YongHyeon 466095d67482SBill Paul static void 46613f74909aSGleb Smirnoff bge_intr(void *xsc) 466295d67482SBill Paul { 466395d67482SBill Paul struct bge_softc *sc; 4664fba8b109SMarcel Moolenaar if_t ifp; 4665dab5cd05SOleg Bulyzhin uint32_t statusword; 4666b9c05fa5SPyun YongHyeon uint16_t rx_prod, tx_cons; 466795d67482SBill Paul 466895d67482SBill Paul sc = xsc; 4669f41ac2beSBill Paul 46700f9bd73bSSam Leffler BGE_LOCK(sc); 46710f9bd73bSSam Leffler 4672dab5cd05SOleg Bulyzhin ifp = sc->bge_ifp; 4673dab5cd05SOleg Bulyzhin 467475719184SGleb Smirnoff #ifdef DEVICE_POLLING 4675fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_POLLING) { 467675719184SGleb Smirnoff BGE_UNLOCK(sc); 467775719184SGleb Smirnoff return; 467875719184SGleb Smirnoff } 467975719184SGleb Smirnoff #endif 468075719184SGleb Smirnoff 4681f30cbfc6SScott Long /* 4682b848e032SBruce Evans * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4683b848e032SBruce Evans * disable interrupts by writing nonzero like we used to, since with 4684b848e032SBruce Evans * our current organization this just gives complications and 4685b848e032SBruce Evans * pessimizations for re-enabling interrupts. We used to have races 4686b848e032SBruce Evans * instead of the necessary complications. Disabling interrupts 4687b848e032SBruce Evans * would just reduce the chance of a status update while we are 4688b848e032SBruce Evans * running (by switching to the interrupt-mode coalescence 4689b848e032SBruce Evans * parameters), but this chance is already very low so it is more 4690b848e032SBruce Evans * efficient to get another interrupt than prevent it. 4691b848e032SBruce Evans * 4692b848e032SBruce Evans * We do the ack first to ensure another interrupt if there is a 4693b848e032SBruce Evans * status update after the ack. We don't check for the status 4694b848e032SBruce Evans * changing later because it is more efficient to get another 4695b848e032SBruce Evans * interrupt than prevent it, not quite as above (not checking is 4696b848e032SBruce Evans * a smaller optimization than not toggling the interrupt enable, 4697b848e032SBruce Evans * since checking doesn't involve PCI accesses and toggling require 4698b848e032SBruce Evans * the status check). So toggling would probably be a pessimization 4699b848e032SBruce Evans * even with MSI. It would only be needed for using a task queue. 4700b848e032SBruce Evans */ 470138cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4702b848e032SBruce Evans 4703f584dfd1SPyun YongHyeon /* 4704f584dfd1SPyun YongHyeon * Do the mandatory PCI flush as well as get the link status. 4705f584dfd1SPyun YongHyeon */ 4706f584dfd1SPyun YongHyeon statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4707f584dfd1SPyun YongHyeon 4708f584dfd1SPyun YongHyeon /* Make sure the descriptor ring indexes are coherent. */ 4709f584dfd1SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4710f584dfd1SPyun YongHyeon sc->bge_cdata.bge_status_map, 4711f584dfd1SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4712f584dfd1SPyun YongHyeon rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4713f584dfd1SPyun YongHyeon tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4714f584dfd1SPyun YongHyeon sc->bge_ldata.bge_status_block->bge_status = 0; 4715f584dfd1SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4716f584dfd1SPyun YongHyeon sc->bge_cdata.bge_status_map, 4717f584dfd1SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4718f584dfd1SPyun YongHyeon 47191f313773SOleg Bulyzhin if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 47204c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4721f30cbfc6SScott Long statusword || sc->bge_link_evt) 4722dab5cd05SOleg Bulyzhin bge_link_upd(sc); 472395d67482SBill Paul 4724fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 47253f74909aSGleb Smirnoff /* Check RX return ring producer/consumer. */ 4726dfe0df9aSPyun YongHyeon bge_rxeof(sc, rx_prod, 1); 472725e13e68SXin LI } 472895d67482SBill Paul 4729fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 47303f74909aSGleb Smirnoff /* Check TX ring producer/consumer. */ 4731b9c05fa5SPyun YongHyeon bge_txeof(sc, tx_cons); 473295d67482SBill Paul } 473395d67482SBill Paul 4734fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4735fba8b109SMarcel Moolenaar !if_sendq_empty(ifp)) 47360f9bd73bSSam Leffler bge_start_locked(ifp); 47370f9bd73bSSam Leffler 47380f9bd73bSSam Leffler BGE_UNLOCK(sc); 473995d67482SBill Paul } 474095d67482SBill Paul 474195d67482SBill Paul static void 47428cb1383cSDoug Ambrisko bge_asf_driver_up(struct bge_softc *sc) 47438cb1383cSDoug Ambrisko { 47448cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) { 47458cb1383cSDoug Ambrisko /* Send ASF heartbeat aprox. every 2s */ 47468cb1383cSDoug Ambrisko if (sc->bge_asf_count) 47478cb1383cSDoug Ambrisko sc->bge_asf_count --; 47488cb1383cSDoug Ambrisko else { 4749899d6846SPyun YongHyeon sc->bge_asf_count = 2; 4750888b47f0SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 47513c201200SPyun YongHyeon BGE_FW_CMD_DRV_ALIVE); 4752888b47f0SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4753941a6e13SPyun YongHyeon bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4754941a6e13SPyun YongHyeon BGE_FW_HB_TIMEOUT_SEC); 47553fed2d5dSPyun YongHyeon CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 47569931ba85SPyun YongHyeon CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 47579931ba85SPyun YongHyeon BGE_RX_CPU_DRV_EVENT); 47588cb1383cSDoug Ambrisko } 47598cb1383cSDoug Ambrisko } 47608cb1383cSDoug Ambrisko } 47618cb1383cSDoug Ambrisko 47628cb1383cSDoug Ambrisko static void 4763b74e67fbSGleb Smirnoff bge_tick(void *xsc) 47640f9bd73bSSam Leffler { 4765b74e67fbSGleb Smirnoff struct bge_softc *sc = xsc; 476695d67482SBill Paul struct mii_data *mii = NULL; 476795d67482SBill Paul 47680f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 476995d67482SBill Paul 47705dda8085SOleg Bulyzhin /* Synchronize with possible callout reset/stop. */ 47715dda8085SOleg Bulyzhin if (callout_pending(&sc->bge_stat_ch) || 47725dda8085SOleg Bulyzhin !callout_active(&sc->bge_stat_ch)) 47735dda8085SOleg Bulyzhin return; 47745dda8085SOleg Bulyzhin 47757ee00338SJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 47760434d1b8SBill Paul bge_stats_update_regs(sc); 47770434d1b8SBill Paul else 477895d67482SBill Paul bge_stats_update(sc); 477995d67482SBill Paul 4780548c8f1aSPyun YongHyeon /* XXX Add APE heartbeat check here? */ 4781548c8f1aSPyun YongHyeon 4782652ae483SGleb Smirnoff if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 478395d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 478482b67c01SOleg Bulyzhin /* 478582b67c01SOleg Bulyzhin * Do not touch PHY if we have link up. This could break 478682b67c01SOleg Bulyzhin * IPMI/ASF mode or produce extra input errors 478782b67c01SOleg Bulyzhin * (extra errors was reported for bcm5701 & bcm5704). 478882b67c01SOleg Bulyzhin */ 478982b67c01SOleg Bulyzhin if (!sc->bge_link) 479095d67482SBill Paul mii_tick(mii); 47917b97099dSOleg Bulyzhin } else { 47927b97099dSOleg Bulyzhin /* 47937b97099dSOleg Bulyzhin * Since in TBI mode auto-polling can't be used we should poll 47947b97099dSOleg Bulyzhin * link status manually. Here we register pending link event 47957b97099dSOleg Bulyzhin * and trigger interrupt. 47967b97099dSOleg Bulyzhin */ 47977b97099dSOleg Bulyzhin #ifdef DEVICE_POLLING 47983f74909aSGleb Smirnoff /* In polling mode we poll link state in bge_poll(). */ 479959578ee0SSergey Kandaurov if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 48007b97099dSOleg Bulyzhin #endif 48017b97099dSOleg Bulyzhin { 48027b97099dSOleg Bulyzhin sc->bge_link_evt++; 48034f0794ffSBjoern A. Zeeb if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 48044f0794ffSBjoern A. Zeeb sc->bge_flags & BGE_FLAG_5788) 48057b97099dSOleg Bulyzhin BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 48064f0794ffSBjoern A. Zeeb else 48074f0794ffSBjoern A. Zeeb BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 48087b97099dSOleg Bulyzhin } 4809dab5cd05SOleg Bulyzhin } 481095d67482SBill Paul 48118cb1383cSDoug Ambrisko bge_asf_driver_up(sc); 4812b74e67fbSGleb Smirnoff bge_watchdog(sc); 48138cb1383cSDoug Ambrisko 4814dab5cd05SOleg Bulyzhin callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 481595d67482SBill Paul } 481695d67482SBill Paul 481795d67482SBill Paul static void 48183f74909aSGleb Smirnoff bge_stats_update_regs(struct bge_softc *sc) 48190434d1b8SBill Paul { 4820fba8b109SMarcel Moolenaar if_t ifp; 48212280c16bSPyun YongHyeon struct bge_mac_stats *stats; 482229b44b09SPyun YongHyeon uint32_t val; 48230434d1b8SBill Paul 4824fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 48252280c16bSPyun YongHyeon stats = &sc->bge_mac_stats; 48260434d1b8SBill Paul 48272280c16bSPyun YongHyeon stats->ifHCOutOctets += 48282280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 48292280c16bSPyun YongHyeon stats->etherStatsCollisions += 48302280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 48312280c16bSPyun YongHyeon stats->outXonSent += 48322280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 48332280c16bSPyun YongHyeon stats->outXoffSent += 48342280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 48352280c16bSPyun YongHyeon stats->dot3StatsInternalMacTransmitErrors += 48362280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 48372280c16bSPyun YongHyeon stats->dot3StatsSingleCollisionFrames += 48382280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 48392280c16bSPyun YongHyeon stats->dot3StatsMultipleCollisionFrames += 48402280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 48412280c16bSPyun YongHyeon stats->dot3StatsDeferredTransmissions += 48422280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 48432280c16bSPyun YongHyeon stats->dot3StatsExcessiveCollisions += 48442280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 48452280c16bSPyun YongHyeon stats->dot3StatsLateCollisions += 48462280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 48472280c16bSPyun YongHyeon stats->ifHCOutUcastPkts += 48482280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 48492280c16bSPyun YongHyeon stats->ifHCOutMulticastPkts += 48502280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 48512280c16bSPyun YongHyeon stats->ifHCOutBroadcastPkts += 48522280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 48537e6e2507SJung-uk Kim 48542280c16bSPyun YongHyeon stats->ifHCInOctets += 48552280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 48562280c16bSPyun YongHyeon stats->etherStatsFragments += 48572280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 48582280c16bSPyun YongHyeon stats->ifHCInUcastPkts += 48592280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 48602280c16bSPyun YongHyeon stats->ifHCInMulticastPkts += 48612280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 48622280c16bSPyun YongHyeon stats->ifHCInBroadcastPkts += 48632280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 48642280c16bSPyun YongHyeon stats->dot3StatsFCSErrors += 48652280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 48662280c16bSPyun YongHyeon stats->dot3StatsAlignmentErrors += 48672280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 48682280c16bSPyun YongHyeon stats->xonPauseFramesReceived += 48692280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 48702280c16bSPyun YongHyeon stats->xoffPauseFramesReceived += 48712280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 48722280c16bSPyun YongHyeon stats->macControlFramesReceived += 48732280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 48742280c16bSPyun YongHyeon stats->xoffStateEntered += 48752280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 48762280c16bSPyun YongHyeon stats->dot3StatsFramesTooLong += 48772280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 48782280c16bSPyun YongHyeon stats->etherStatsJabbers += 48792280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 48802280c16bSPyun YongHyeon stats->etherStatsUndersizePkts += 48812280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 48822280c16bSPyun YongHyeon 48832280c16bSPyun YongHyeon stats->FramesDroppedDueToFilters += 48842280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 48852280c16bSPyun YongHyeon stats->DmaWriteQueueFull += 48862280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 48872280c16bSPyun YongHyeon stats->DmaWriteHighPriQueueFull += 48882280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 48892280c16bSPyun YongHyeon stats->NoMoreRxBDs += 48902280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4891f78094a5SPyun YongHyeon /* 4892f78094a5SPyun YongHyeon * XXX 4893f78094a5SPyun YongHyeon * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4894f78094a5SPyun YongHyeon * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4895f78094a5SPyun YongHyeon * includes number of unwanted multicast frames. This comes 4896f78094a5SPyun YongHyeon * from silicon bug and known workaround to get rough(not 4897f78094a5SPyun YongHyeon * exact) counter is to enable interrupt on MBUF low water 4898f78094a5SPyun YongHyeon * attention. This can be accomplished by setting 4899f78094a5SPyun YongHyeon * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4900f78094a5SPyun YongHyeon * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4901f78094a5SPyun YongHyeon * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4902f78094a5SPyun YongHyeon * However that change would generate more interrupts and 4903f78094a5SPyun YongHyeon * there are still possibilities of losing multiple frames 4904f78094a5SPyun YongHyeon * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4905f78094a5SPyun YongHyeon * Given that the workaround still would not get correct 4906f78094a5SPyun YongHyeon * counter I don't think it's worth to implement it. So 4907f78094a5SPyun YongHyeon * ignore reading the counter on controllers that have the 4908f78094a5SPyun YongHyeon * silicon bug. 4909f78094a5SPyun YongHyeon */ 4910f78094a5SPyun YongHyeon if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4911f78094a5SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4912f78094a5SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 49132280c16bSPyun YongHyeon stats->InputDiscards += 49142280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 49152280c16bSPyun YongHyeon stats->InputErrors += 49162280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 49172280c16bSPyun YongHyeon stats->RecvThresholdHit += 49182280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 49192280c16bSPyun YongHyeon 4920fba8b109SMarcel Moolenaar if_setcollisions(ifp, (u_long)stats->etherStatsCollisions); 4921fba8b109SMarcel Moolenaar if_setierrors(ifp, (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4922fba8b109SMarcel Moolenaar stats->InputErrors)); 492329b44b09SPyun YongHyeon 492429b44b09SPyun YongHyeon if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 492529b44b09SPyun YongHyeon /* 492629b44b09SPyun YongHyeon * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 492729b44b09SPyun YongHyeon * frames, it's safe to disable workaround for DMA engine's 492829b44b09SPyun YongHyeon * miscalculation of TXMBUF space. 492929b44b09SPyun YongHyeon */ 493029b44b09SPyun YongHyeon if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 493129b44b09SPyun YongHyeon stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 493229b44b09SPyun YongHyeon val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 493329b44b09SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 493429b44b09SPyun YongHyeon val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 493529b44b09SPyun YongHyeon else 493629b44b09SPyun YongHyeon val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 493729b44b09SPyun YongHyeon CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 493829b44b09SPyun YongHyeon sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 493929b44b09SPyun YongHyeon } 494029b44b09SPyun YongHyeon } 49412280c16bSPyun YongHyeon } 49422280c16bSPyun YongHyeon 49432280c16bSPyun YongHyeon static void 49442280c16bSPyun YongHyeon bge_stats_clear_regs(struct bge_softc *sc) 49452280c16bSPyun YongHyeon { 49462280c16bSPyun YongHyeon 49472280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 49482280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 49492280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 49502280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 49512280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 49522280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 49532280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 49542280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 49552280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 49562280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 49572280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 49582280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 49592280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 49602280c16bSPyun YongHyeon 49612280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 49622280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 49632280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 49642280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 49652280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 49662280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 49672280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 49682280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 49692280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 49702280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 49712280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 49722280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 49732280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 49742280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 49752280c16bSPyun YongHyeon 49762280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 49772280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 49782280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 49792280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 49802280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 49812280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 49822280c16bSPyun YongHyeon CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 49830434d1b8SBill Paul } 49840434d1b8SBill Paul 49850434d1b8SBill Paul static void 49863f74909aSGleb Smirnoff bge_stats_update(struct bge_softc *sc) 498795d67482SBill Paul { 4988fba8b109SMarcel Moolenaar if_t ifp; 4989e907febfSPyun YongHyeon bus_size_t stats; 49907e6e2507SJung-uk Kim uint32_t cnt; /* current register value */ 499195d67482SBill Paul 4992fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 499395d67482SBill Paul 4994e907febfSPyun YongHyeon stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4995e907febfSPyun YongHyeon 4996e907febfSPyun YongHyeon #define READ_STAT(sc, stats, stat) \ 4997e907febfSPyun YongHyeon CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 499895d67482SBill Paul 49998634dfffSJung-uk Kim cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 5000fba8b109SMarcel Moolenaar if_inccollisions(ifp, (uint32_t)(cnt - sc->bge_tx_collisions)); 50016fb34dd2SOleg Bulyzhin sc->bge_tx_collisions = cnt; 50026fb34dd2SOleg Bulyzhin 500337ee7cc7SPyun YongHyeon cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 5004fba8b109SMarcel Moolenaar if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_nobds)); 500537ee7cc7SPyun YongHyeon sc->bge_rx_nobds = cnt; 500637ee7cc7SPyun YongHyeon cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5007fba8b109SMarcel Moolenaar if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_inerrs)); 500837ee7cc7SPyun YongHyeon sc->bge_rx_inerrs = cnt; 50096fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5010fba8b109SMarcel Moolenaar if_incierrors(ifp, (uint32_t)(cnt - sc->bge_rx_discards)); 50116fb34dd2SOleg Bulyzhin sc->bge_rx_discards = cnt; 50126fb34dd2SOleg Bulyzhin 50136fb34dd2SOleg Bulyzhin cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5014fba8b109SMarcel Moolenaar if_incoerrors(ifp, (uint32_t)(cnt - sc->bge_tx_discards)); 50156fb34dd2SOleg Bulyzhin sc->bge_tx_discards = cnt; 501695d67482SBill Paul 5017e907febfSPyun YongHyeon #undef READ_STAT 501895d67482SBill Paul } 501995d67482SBill Paul 502095d67482SBill Paul /* 5021d375e524SGleb Smirnoff * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5022d375e524SGleb Smirnoff * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5023d375e524SGleb Smirnoff * but when such padded frames employ the bge IP/TCP checksum offload, 5024d375e524SGleb Smirnoff * the hardware checksum assist gives incorrect results (possibly 5025d375e524SGleb Smirnoff * from incorporating its own padding into the UDP/TCP checksum; who knows). 5026d375e524SGleb Smirnoff * If we pad such runts with zeros, the onboard checksum comes out correct. 5027d375e524SGleb Smirnoff */ 5028d375e524SGleb Smirnoff static __inline int 5029d375e524SGleb Smirnoff bge_cksum_pad(struct mbuf *m) 5030d375e524SGleb Smirnoff { 5031d375e524SGleb Smirnoff int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5032d375e524SGleb Smirnoff struct mbuf *last; 5033d375e524SGleb Smirnoff 5034d375e524SGleb Smirnoff /* If there's only the packet-header and we can pad there, use it. */ 5035d375e524SGleb Smirnoff if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5036d375e524SGleb Smirnoff M_TRAILINGSPACE(m) >= padlen) { 5037d375e524SGleb Smirnoff last = m; 5038d375e524SGleb Smirnoff } else { 5039d375e524SGleb Smirnoff /* 5040d375e524SGleb Smirnoff * Walk packet chain to find last mbuf. We will either 5041d375e524SGleb Smirnoff * pad there, or append a new mbuf and pad it. 5042d375e524SGleb Smirnoff */ 5043d375e524SGleb Smirnoff for (last = m; last->m_next != NULL; last = last->m_next); 5044d375e524SGleb Smirnoff if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5045d375e524SGleb Smirnoff /* Allocate new empty mbuf, pad it. Compact later. */ 5046d375e524SGleb Smirnoff struct mbuf *n; 5047d375e524SGleb Smirnoff 5048c6499eccSGleb Smirnoff MGET(n, M_NOWAIT, MT_DATA); 5049d375e524SGleb Smirnoff if (n == NULL) 5050d375e524SGleb Smirnoff return (ENOBUFS); 5051d375e524SGleb Smirnoff n->m_len = 0; 5052d375e524SGleb Smirnoff last->m_next = n; 5053d375e524SGleb Smirnoff last = n; 5054d375e524SGleb Smirnoff } 5055d375e524SGleb Smirnoff } 5056d375e524SGleb Smirnoff 5057d375e524SGleb Smirnoff /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5058d375e524SGleb Smirnoff memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5059d375e524SGleb Smirnoff last->m_len += padlen; 5060d375e524SGleb Smirnoff m->m_pkthdr.len += padlen; 5061d375e524SGleb Smirnoff 5062d375e524SGleb Smirnoff return (0); 5063d375e524SGleb Smirnoff } 5064d375e524SGleb Smirnoff 5065ca3f1187SPyun YongHyeon static struct mbuf * 5066d598b626SPyun YongHyeon bge_check_short_dma(struct mbuf *m) 5067d598b626SPyun YongHyeon { 5068d598b626SPyun YongHyeon struct mbuf *n; 5069d598b626SPyun YongHyeon int found; 5070d598b626SPyun YongHyeon 5071d598b626SPyun YongHyeon /* 5072d598b626SPyun YongHyeon * If device receive two back-to-back send BDs with less than 5073d598b626SPyun YongHyeon * or equal to 8 total bytes then the device may hang. The two 5074d598b626SPyun YongHyeon * back-to-back send BDs must in the same frame for this failure 5075d598b626SPyun YongHyeon * to occur. Scan mbuf chains and see whether two back-to-back 5076d598b626SPyun YongHyeon * send BDs are there. If this is the case, allocate new mbuf 5077d598b626SPyun YongHyeon * and copy the frame to workaround the silicon bug. 5078d598b626SPyun YongHyeon */ 5079d598b626SPyun YongHyeon for (n = m, found = 0; n != NULL; n = n->m_next) { 5080d598b626SPyun YongHyeon if (n->m_len < 8) { 5081d598b626SPyun YongHyeon found++; 5082d598b626SPyun YongHyeon if (found > 1) 5083d598b626SPyun YongHyeon break; 5084d598b626SPyun YongHyeon continue; 5085d598b626SPyun YongHyeon } 5086d598b626SPyun YongHyeon found = 0; 5087d598b626SPyun YongHyeon } 5088d598b626SPyun YongHyeon 5089d598b626SPyun YongHyeon if (found > 1) { 5090c6499eccSGleb Smirnoff n = m_defrag(m, M_NOWAIT); 5091d598b626SPyun YongHyeon if (n == NULL) 5092d598b626SPyun YongHyeon m_freem(m); 5093d598b626SPyun YongHyeon } else 5094d598b626SPyun YongHyeon n = m; 5095d598b626SPyun YongHyeon return (n); 5096d598b626SPyun YongHyeon } 5097d598b626SPyun YongHyeon 5098d598b626SPyun YongHyeon static struct mbuf * 50991108273aSPyun YongHyeon bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 51001108273aSPyun YongHyeon uint16_t *flags) 5101ca3f1187SPyun YongHyeon { 5102ca3f1187SPyun YongHyeon struct ip *ip; 5103ca3f1187SPyun YongHyeon struct tcphdr *tcp; 5104ca3f1187SPyun YongHyeon struct mbuf *n; 5105ca3f1187SPyun YongHyeon uint16_t hlen; 51065b355c4fSPyun YongHyeon uint32_t poff; 5107ca3f1187SPyun YongHyeon 5108ca3f1187SPyun YongHyeon if (M_WRITABLE(m) == 0) { 5109ca3f1187SPyun YongHyeon /* Get a writable copy. */ 5110c6499eccSGleb Smirnoff n = m_dup(m, M_NOWAIT); 5111ca3f1187SPyun YongHyeon m_freem(m); 5112ca3f1187SPyun YongHyeon if (n == NULL) 5113ca3f1187SPyun YongHyeon return (NULL); 5114ca3f1187SPyun YongHyeon m = n; 5115ca3f1187SPyun YongHyeon } 51165b355c4fSPyun YongHyeon m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5117ca3f1187SPyun YongHyeon if (m == NULL) 5118ca3f1187SPyun YongHyeon return (NULL); 51195b355c4fSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 51205b355c4fSPyun YongHyeon poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5121ca3f1187SPyun YongHyeon m = m_pullup(m, poff + sizeof(struct tcphdr)); 5122ca3f1187SPyun YongHyeon if (m == NULL) 5123ca3f1187SPyun YongHyeon return (NULL); 5124ca3f1187SPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 51255b355c4fSPyun YongHyeon m = m_pullup(m, poff + (tcp->th_off << 2)); 5126ca3f1187SPyun YongHyeon if (m == NULL) 5127ca3f1187SPyun YongHyeon return (NULL); 5128ca3f1187SPyun YongHyeon /* 5129ca3f1187SPyun YongHyeon * It seems controller doesn't modify IP length and TCP pseudo 5130ca3f1187SPyun YongHyeon * checksum. These checksum computed by upper stack should be 0. 5131ca3f1187SPyun YongHyeon */ 5132ca3f1187SPyun YongHyeon *mss = m->m_pkthdr.tso_segsz; 513396486faaSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5134ca3f1187SPyun YongHyeon ip->ip_sum = 0; 5135ca3f1187SPyun YongHyeon ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5136ca3f1187SPyun YongHyeon /* Clear pseudo checksum computed by TCP stack. */ 513796486faaSPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5138ca3f1187SPyun YongHyeon tcp->th_sum = 0; 5139ca3f1187SPyun YongHyeon /* 5140ca3f1187SPyun YongHyeon * Broadcom controllers uses different descriptor format for 5141ca3f1187SPyun YongHyeon * TSO depending on ASIC revision. Due to TSO-capable firmware 5142ca3f1187SPyun YongHyeon * license issue and lower performance of firmware based TSO 51431108273aSPyun YongHyeon * we only support hardware based TSO. 5144ca3f1187SPyun YongHyeon */ 51451108273aSPyun YongHyeon /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5146ca3f1187SPyun YongHyeon hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 51471108273aSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_TSO3) { 51481108273aSPyun YongHyeon /* 51491108273aSPyun YongHyeon * For BCM5717 and newer controllers, hardware based TSO 51501108273aSPyun YongHyeon * uses the 14 lower bits of the bge_mss field to store the 51511108273aSPyun YongHyeon * MSS and the upper 2 bits to store the lowest 2 bits of 51521108273aSPyun YongHyeon * the IP/TCP header length. The upper 6 bits of the header 51531108273aSPyun YongHyeon * length are stored in the bge_flags[14:10,4] field. Jumbo 51541108273aSPyun YongHyeon * frames are supported. 51551108273aSPyun YongHyeon */ 51561108273aSPyun YongHyeon *mss |= ((hlen & 0x3) << 14); 51571108273aSPyun YongHyeon *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 51581108273aSPyun YongHyeon } else { 51591108273aSPyun YongHyeon /* 51601108273aSPyun YongHyeon * For BCM5755 and newer controllers, hardware based TSO uses 51611108273aSPyun YongHyeon * the lower 11 bits to store the MSS and the upper 5 bits to 51621108273aSPyun YongHyeon * store the IP/TCP header length. Jumbo frames are not 51631108273aSPyun YongHyeon * supported. 51641108273aSPyun YongHyeon */ 5165ca3f1187SPyun YongHyeon *mss |= (hlen << 11); 51661108273aSPyun YongHyeon } 5167ca3f1187SPyun YongHyeon return (m); 5168ca3f1187SPyun YongHyeon } 5169ca3f1187SPyun YongHyeon 5170d375e524SGleb Smirnoff /* 517195d67482SBill Paul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 517295d67482SBill Paul * pointers to descriptors. 517395d67482SBill Paul */ 517495d67482SBill Paul static int 5175676ad2c9SGleb Smirnoff bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 517695d67482SBill Paul { 51777e27542aSGleb Smirnoff bus_dma_segment_t segs[BGE_NSEG_NEW]; 5178f41ac2beSBill Paul bus_dmamap_t map; 5179676ad2c9SGleb Smirnoff struct bge_tx_bd *d; 5180676ad2c9SGleb Smirnoff struct mbuf *m = *m_head; 51817e27542aSGleb Smirnoff uint32_t idx = *txidx; 5182ca3f1187SPyun YongHyeon uint16_t csum_flags, mss, vlan_tag; 51837e27542aSGleb Smirnoff int nsegs, i, error; 518495d67482SBill Paul 51856909dc43SGleb Smirnoff csum_flags = 0; 5186ca3f1187SPyun YongHyeon mss = 0; 5187ca3f1187SPyun YongHyeon vlan_tag = 0; 5188d598b626SPyun YongHyeon if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5189d598b626SPyun YongHyeon m->m_next != NULL) { 5190d598b626SPyun YongHyeon *m_head = bge_check_short_dma(m); 5191d598b626SPyun YongHyeon if (*m_head == NULL) 5192d598b626SPyun YongHyeon return (ENOBUFS); 5193d598b626SPyun YongHyeon m = *m_head; 5194d598b626SPyun YongHyeon } 5195ca3f1187SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 51961108273aSPyun YongHyeon *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5197ca3f1187SPyun YongHyeon if (*m_head == NULL) 5198ca3f1187SPyun YongHyeon return (ENOBUFS); 5199ca3f1187SPyun YongHyeon csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5200ca3f1187SPyun YongHyeon BGE_TXBDFLAG_CPU_POST_DMA; 520135f945cdSPyun YongHyeon } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 52026909dc43SGleb Smirnoff if (m->m_pkthdr.csum_flags & CSUM_IP) 52036909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_IP_CSUM; 52046909dc43SGleb Smirnoff if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 52056909dc43SGleb Smirnoff csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 52066909dc43SGleb Smirnoff if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 52076909dc43SGleb Smirnoff (error = bge_cksum_pad(m)) != 0) { 52086909dc43SGleb Smirnoff m_freem(m); 52096909dc43SGleb Smirnoff *m_head = NULL; 52106909dc43SGleb Smirnoff return (error); 52116909dc43SGleb Smirnoff } 52126909dc43SGleb Smirnoff } 52136909dc43SGleb Smirnoff } 52146909dc43SGleb Smirnoff 52151108273aSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 52161108273aSPyun YongHyeon if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 52171108273aSPyun YongHyeon m->m_pkthdr.len > ETHER_MAX_LEN) 52181108273aSPyun YongHyeon csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 52191108273aSPyun YongHyeon if (sc->bge_forced_collapse > 0 && 5220beaa2ae1SPyun YongHyeon (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5221d94f2b85SPyun YongHyeon /* 5222d94f2b85SPyun YongHyeon * Forcedly collapse mbuf chains to overcome hardware 5223d94f2b85SPyun YongHyeon * limitation which only support a single outstanding 5224d94f2b85SPyun YongHyeon * DMA read operation. 5225d94f2b85SPyun YongHyeon */ 5226beaa2ae1SPyun YongHyeon if (sc->bge_forced_collapse == 1) 5227c6499eccSGleb Smirnoff m = m_defrag(m, M_NOWAIT); 5228d94f2b85SPyun YongHyeon else 5229c6499eccSGleb Smirnoff m = m_collapse(m, M_NOWAIT, 52301108273aSPyun YongHyeon sc->bge_forced_collapse); 5231261f04d6SPyun YongHyeon if (m == NULL) 5232261f04d6SPyun YongHyeon m = *m_head; 5233d94f2b85SPyun YongHyeon *m_head = m; 5234d94f2b85SPyun YongHyeon } 52351108273aSPyun YongHyeon } 5236d94f2b85SPyun YongHyeon 52377e27542aSGleb Smirnoff map = sc->bge_cdata.bge_tx_dmamap[idx]; 52380ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5239676ad2c9SGleb Smirnoff &nsegs, BUS_DMA_NOWAIT); 52407e27542aSGleb Smirnoff if (error == EFBIG) { 5241c6499eccSGleb Smirnoff m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5242676ad2c9SGleb Smirnoff if (m == NULL) { 5243676ad2c9SGleb Smirnoff m_freem(*m_head); 5244676ad2c9SGleb Smirnoff *m_head = NULL; 52457e27542aSGleb Smirnoff return (ENOBUFS); 52467e27542aSGleb Smirnoff } 5247676ad2c9SGleb Smirnoff *m_head = m; 52480ac56796SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 52490ac56796SPyun YongHyeon m, segs, &nsegs, BUS_DMA_NOWAIT); 5250676ad2c9SGleb Smirnoff if (error) { 5251676ad2c9SGleb Smirnoff m_freem(m); 5252676ad2c9SGleb Smirnoff *m_head = NULL; 52537e27542aSGleb Smirnoff return (error); 52547e27542aSGleb Smirnoff } 5255676ad2c9SGleb Smirnoff } else if (error != 0) 5256676ad2c9SGleb Smirnoff return (error); 52577e27542aSGleb Smirnoff 5258167fdb62SPyun YongHyeon /* Check if we have enough free send BDs. */ 5259167fdb62SPyun YongHyeon if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 52600ac56796SPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 526195d67482SBill Paul return (ENOBUFS); 52627e27542aSGleb Smirnoff } 52637e27542aSGleb Smirnoff 52640ac56796SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5265e65bed95SPyun YongHyeon 5266ca3f1187SPyun YongHyeon if (m->m_flags & M_VLANTAG) { 5267ca3f1187SPyun YongHyeon csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5268ca3f1187SPyun YongHyeon vlan_tag = m->m_pkthdr.ether_vtag; 5269ca3f1187SPyun YongHyeon } 5270b77d3a3bSPyun YongHyeon 5271b77d3a3bSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5272b77d3a3bSPyun YongHyeon (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5273b77d3a3bSPyun YongHyeon /* 5274b77d3a3bSPyun YongHyeon * 5725 family of devices corrupts TSO packets when TSO DMA 5275b77d3a3bSPyun YongHyeon * buffers cross into regions which are within MSS bytes of 5276b77d3a3bSPyun YongHyeon * a 4GB boundary. If we encounter the condition, drop the 5277b77d3a3bSPyun YongHyeon * packet. 5278b77d3a3bSPyun YongHyeon */ 5279b77d3a3bSPyun YongHyeon for (i = 0; ; i++) { 5280b77d3a3bSPyun YongHyeon d = &sc->bge_ldata.bge_tx_ring[idx]; 5281b77d3a3bSPyun YongHyeon d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5282b77d3a3bSPyun YongHyeon d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5283b77d3a3bSPyun YongHyeon d->bge_len = segs[i].ds_len; 5284b77d3a3bSPyun YongHyeon if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5285b77d3a3bSPyun YongHyeon d->bge_addr.bge_addr_lo) 5286b77d3a3bSPyun YongHyeon break; 5287b77d3a3bSPyun YongHyeon d->bge_flags = csum_flags; 5288b77d3a3bSPyun YongHyeon d->bge_vlan_tag = vlan_tag; 5289b77d3a3bSPyun YongHyeon d->bge_mss = mss; 5290b77d3a3bSPyun YongHyeon if (i == nsegs - 1) 5291b77d3a3bSPyun YongHyeon break; 5292b77d3a3bSPyun YongHyeon BGE_INC(idx, BGE_TX_RING_CNT); 5293b77d3a3bSPyun YongHyeon } 5294b77d3a3bSPyun YongHyeon if (i != nsegs - 1) { 5295b77d3a3bSPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5296b77d3a3bSPyun YongHyeon BUS_DMASYNC_POSTWRITE); 5297b77d3a3bSPyun YongHyeon bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5298b77d3a3bSPyun YongHyeon m_freem(*m_head); 5299b77d3a3bSPyun YongHyeon *m_head = NULL; 5300b77d3a3bSPyun YongHyeon return (EIO); 5301b77d3a3bSPyun YongHyeon } 5302b77d3a3bSPyun YongHyeon } else { 53037e27542aSGleb Smirnoff for (i = 0; ; i++) { 53047e27542aSGleb Smirnoff d = &sc->bge_ldata.bge_tx_ring[idx]; 53057e27542aSGleb Smirnoff d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 53067e27542aSGleb Smirnoff d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 53077e27542aSGleb Smirnoff d->bge_len = segs[i].ds_len; 53087e27542aSGleb Smirnoff d->bge_flags = csum_flags; 5309ca3f1187SPyun YongHyeon d->bge_vlan_tag = vlan_tag; 5310ca3f1187SPyun YongHyeon d->bge_mss = mss; 53117e27542aSGleb Smirnoff if (i == nsegs - 1) 53127e27542aSGleb Smirnoff break; 53137e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 53147e27542aSGleb Smirnoff } 5315b77d3a3bSPyun YongHyeon } 53167e27542aSGleb Smirnoff 53177e27542aSGleb Smirnoff /* Mark the last segment as end of packet... */ 53187e27542aSGleb Smirnoff d->bge_flags |= BGE_TXBDFLAG_END; 5319676ad2c9SGleb Smirnoff 5320f41ac2beSBill Paul /* 5321f41ac2beSBill Paul * Insure that the map for this transmission 5322f41ac2beSBill Paul * is placed at the array index of the last descriptor 5323f41ac2beSBill Paul * in this chain. 5324f41ac2beSBill Paul */ 53257e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 53267e27542aSGleb Smirnoff sc->bge_cdata.bge_tx_dmamap[idx] = map; 5327676ad2c9SGleb Smirnoff sc->bge_cdata.bge_tx_chain[idx] = m; 53287e27542aSGleb Smirnoff sc->bge_txcnt += nsegs; 532995d67482SBill Paul 53307e27542aSGleb Smirnoff BGE_INC(idx, BGE_TX_RING_CNT); 53317e27542aSGleb Smirnoff *txidx = idx; 533295d67482SBill Paul 533395d67482SBill Paul return (0); 533495d67482SBill Paul } 533595d67482SBill Paul 533695d67482SBill Paul /* 533795d67482SBill Paul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 533895d67482SBill Paul * to the mbuf data regions directly in the transmit descriptors. 533995d67482SBill Paul */ 534095d67482SBill Paul static void 5341fba8b109SMarcel Moolenaar bge_start_locked(if_t ifp) 534295d67482SBill Paul { 534395d67482SBill Paul struct bge_softc *sc; 5344167fdb62SPyun YongHyeon struct mbuf *m_head; 534514bbd30fSGleb Smirnoff uint32_t prodidx; 5346167fdb62SPyun YongHyeon int count; 534795d67482SBill Paul 5348fba8b109SMarcel Moolenaar sc = if_getsoftc(ifp); 5349167fdb62SPyun YongHyeon BGE_LOCK_ASSERT(sc); 535095d67482SBill Paul 5351167fdb62SPyun YongHyeon if (!sc->bge_link || 5352fba8b109SMarcel Moolenaar (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5353167fdb62SPyun YongHyeon IFF_DRV_RUNNING) 535495d67482SBill Paul return; 535595d67482SBill Paul 535614bbd30fSGleb Smirnoff prodidx = sc->bge_tx_prodidx; 535795d67482SBill Paul 5358fba8b109SMarcel Moolenaar for (count = 0; !if_sendq_empty(ifp);) { 5359167fdb62SPyun YongHyeon if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5360fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5361167fdb62SPyun YongHyeon break; 5362167fdb62SPyun YongHyeon } 5363fba8b109SMarcel Moolenaar m_head = if_dequeue(ifp); 536495d67482SBill Paul if (m_head == NULL) 536595d67482SBill Paul break; 536695d67482SBill Paul 536795d67482SBill Paul /* 536895d67482SBill Paul * Pack the data into the transmit ring. If we 536995d67482SBill Paul * don't have room, set the OACTIVE flag and wait 537095d67482SBill Paul * for the NIC to drain the ring. 537195d67482SBill Paul */ 5372676ad2c9SGleb Smirnoff if (bge_encap(sc, &m_head, &prodidx)) { 5373676ad2c9SGleb Smirnoff if (m_head == NULL) 5374676ad2c9SGleb Smirnoff break; 5375fba8b109SMarcel Moolenaar if_sendq_prepend(ifp, m_head); 5376fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 537795d67482SBill Paul break; 537895d67482SBill Paul } 5379303a718cSDag-Erling Smørgrav ++count; 538095d67482SBill Paul 538195d67482SBill Paul /* 538295d67482SBill Paul * If there's a BPF listener, bounce a copy of this frame 538395d67482SBill Paul * to him. 538495d67482SBill Paul */ 5385fba8b109SMarcel Moolenaar if_bpfmtap(ifp, m_head); 538695d67482SBill Paul } 538795d67482SBill Paul 5388167fdb62SPyun YongHyeon if (count > 0) { 5389aa94f333SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 53905c1da2faSPyun YongHyeon sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 53913f74909aSGleb Smirnoff /* Transmit. */ 539238cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 53933927098fSPaul Saab /* 5700 b2 errata */ 5394e0ced696SPaul Saab if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 539538cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 539695d67482SBill Paul 539714bbd30fSGleb Smirnoff sc->bge_tx_prodidx = prodidx; 539814bbd30fSGleb Smirnoff 539995d67482SBill Paul /* 540095d67482SBill Paul * Set a timeout in case the chip goes out to lunch. 540195d67482SBill Paul */ 5402b584d2b3SPyun YongHyeon sc->bge_timer = BGE_TX_TIMEOUT; 540395d67482SBill Paul } 5404167fdb62SPyun YongHyeon } 540595d67482SBill Paul 54060f9bd73bSSam Leffler /* 54070f9bd73bSSam Leffler * Main transmit routine. To avoid having to do mbuf copies, we put pointers 54080f9bd73bSSam Leffler * to the mbuf data regions directly in the transmit descriptors. 54090f9bd73bSSam Leffler */ 541095d67482SBill Paul static void 5411fba8b109SMarcel Moolenaar bge_start(if_t ifp) 541295d67482SBill Paul { 54130f9bd73bSSam Leffler struct bge_softc *sc; 54140f9bd73bSSam Leffler 5415fba8b109SMarcel Moolenaar sc = if_getsoftc(ifp); 54160f9bd73bSSam Leffler BGE_LOCK(sc); 54170f9bd73bSSam Leffler bge_start_locked(ifp); 54180f9bd73bSSam Leffler BGE_UNLOCK(sc); 54190f9bd73bSSam Leffler } 54200f9bd73bSSam Leffler 54210f9bd73bSSam Leffler static void 54223f74909aSGleb Smirnoff bge_init_locked(struct bge_softc *sc) 54230f9bd73bSSam Leffler { 5424fba8b109SMarcel Moolenaar if_t ifp; 54253f74909aSGleb Smirnoff uint16_t *m; 5426f6a65488SPyun YongHyeon uint32_t mode; 542795d67482SBill Paul 54280f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 542995d67482SBill Paul 5430fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 543195d67482SBill Paul 5432fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 543395d67482SBill Paul return; 543495d67482SBill Paul 543595d67482SBill Paul /* Cancel pending I/O and flush buffers. */ 543695d67482SBill Paul bge_stop(sc); 54378cb1383cSDoug Ambrisko 54388cb1383cSDoug Ambrisko bge_stop_fw(sc); 54398cb1383cSDoug Ambrisko bge_sig_pre_reset(sc, BGE_RESET_START); 544095d67482SBill Paul bge_reset(sc); 54418cb1383cSDoug Ambrisko bge_sig_legacy(sc, BGE_RESET_START); 54428cb1383cSDoug Ambrisko bge_sig_post_reset(sc, BGE_RESET_START); 54438cb1383cSDoug Ambrisko 544495d67482SBill Paul bge_chipinit(sc); 544595d67482SBill Paul 544695d67482SBill Paul /* 544795d67482SBill Paul * Init the various state machines, ring 544895d67482SBill Paul * control blocks and firmware. 544995d67482SBill Paul */ 545095d67482SBill Paul if (bge_blockinit(sc)) { 5451fe806fdaSPyun YongHyeon device_printf(sc->bge_dev, "initialization failure\n"); 545295d67482SBill Paul return; 545395d67482SBill Paul } 545495d67482SBill Paul 5455fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 545695d67482SBill Paul 545795d67482SBill Paul /* Specify MTU. */ 5458fba8b109SMarcel Moolenaar CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5459cb2eacc7SYaroslav Tykhiy ETHER_HDR_LEN + ETHER_CRC_LEN + 5460fba8b109SMarcel Moolenaar (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 546195d67482SBill Paul 546295d67482SBill Paul /* Load our MAC address. */ 54633f74909aSGleb Smirnoff m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 546495d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 546595d67482SBill Paul CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 546695d67482SBill Paul 54673e9b1bcaSJung-uk Kim /* Program promiscuous mode. */ 54683e9b1bcaSJung-uk Kim bge_setpromisc(sc); 546995d67482SBill Paul 547095d67482SBill Paul /* Program multicast filter. */ 547195d67482SBill Paul bge_setmulti(sc); 547295d67482SBill Paul 5473cb2eacc7SYaroslav Tykhiy /* Program VLAN tag stripping. */ 5474cb2eacc7SYaroslav Tykhiy bge_setvlan(sc); 5475cb2eacc7SYaroslav Tykhiy 547635f945cdSPyun YongHyeon /* Override UDP checksum offloading. */ 547735f945cdSPyun YongHyeon if (sc->bge_forced_udpcsum == 0) 547835f945cdSPyun YongHyeon sc->bge_csum_features &= ~CSUM_UDP; 547935f945cdSPyun YongHyeon else 548035f945cdSPyun YongHyeon sc->bge_csum_features |= CSUM_UDP; 5481fba8b109SMarcel Moolenaar if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5482fba8b109SMarcel Moolenaar if_getcapenable(ifp) & IFCAP_TXCSUM) { 5483fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5484fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, sc->bge_csum_features, 0); 548535f945cdSPyun YongHyeon } 548635f945cdSPyun YongHyeon 548795d67482SBill Paul /* Init RX ring. */ 54883ee5d7daSPyun YongHyeon if (bge_init_rx_ring_std(sc) != 0) { 54893ee5d7daSPyun YongHyeon device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 54903ee5d7daSPyun YongHyeon bge_stop(sc); 54913ee5d7daSPyun YongHyeon return; 54923ee5d7daSPyun YongHyeon } 549395d67482SBill Paul 54940434d1b8SBill Paul /* 54950434d1b8SBill Paul * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 54960434d1b8SBill Paul * memory to insure that the chip has in fact read the first 54970434d1b8SBill Paul * entry of the ring. 54980434d1b8SBill Paul */ 54990434d1b8SBill Paul if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 55003f74909aSGleb Smirnoff uint32_t v, i; 55010434d1b8SBill Paul for (i = 0; i < 10; i++) { 55020434d1b8SBill Paul DELAY(20); 55030434d1b8SBill Paul v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 55040434d1b8SBill Paul if (v == (MCLBYTES - ETHER_ALIGN)) 55050434d1b8SBill Paul break; 55060434d1b8SBill Paul } 55070434d1b8SBill Paul if (i == 10) 5508fe806fdaSPyun YongHyeon device_printf (sc->bge_dev, 5509fe806fdaSPyun YongHyeon "5705 A0 chip failed to load RX ring\n"); 55100434d1b8SBill Paul } 55110434d1b8SBill Paul 551295d67482SBill Paul /* Init jumbo RX ring. */ 5513f5459d4cSPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc) && 5514fba8b109SMarcel Moolenaar if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5515fba8b109SMarcel Moolenaar ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 55163ee5d7daSPyun YongHyeon if (bge_init_rx_ring_jumbo(sc) != 0) { 5517333704a3SPyun YongHyeon device_printf(sc->bge_dev, 5518b65256d7SPyun YongHyeon "no memory for jumbo Rx buffers.\n"); 55193ee5d7daSPyun YongHyeon bge_stop(sc); 55203ee5d7daSPyun YongHyeon return; 55213ee5d7daSPyun YongHyeon } 55223ee5d7daSPyun YongHyeon } 552395d67482SBill Paul 55243f74909aSGleb Smirnoff /* Init our RX return ring index. */ 552595d67482SBill Paul sc->bge_rx_saved_considx = 0; 552695d67482SBill Paul 55277e6e2507SJung-uk Kim /* Init our RX/TX stat counters. */ 55287e6e2507SJung-uk Kim sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 55297e6e2507SJung-uk Kim 553095d67482SBill Paul /* Init TX ring. */ 553195d67482SBill Paul bge_init_tx_ring(sc); 553295d67482SBill Paul 5533f6a65488SPyun YongHyeon /* Enable TX MAC state machine lockup fix. */ 5534f6a65488SPyun YongHyeon mode = CSR_READ_4(sc, BGE_TX_MODE); 5535f6a65488SPyun YongHyeon if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5536f6a65488SPyun YongHyeon mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 55372927f01fSPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 55382927f01fSPyun YongHyeon sc->bge_asicrev == BGE_ASICREV_BCM5762) { 553950515680SPyun YongHyeon mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 554050515680SPyun YongHyeon mode |= CSR_READ_4(sc, BGE_TX_MODE) & 554150515680SPyun YongHyeon (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 554250515680SPyun YongHyeon } 55433f74909aSGleb Smirnoff /* Turn on transmitter. */ 5544f6a65488SPyun YongHyeon CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5545a6e66cd2SPyun YongHyeon DELAY(100); 554695d67482SBill Paul 55473f74909aSGleb Smirnoff /* Turn on receiver. */ 5548548c8f1aSPyun YongHyeon mode = CSR_READ_4(sc, BGE_RX_MODE); 5549548c8f1aSPyun YongHyeon if (BGE_IS_5755_PLUS(sc)) 5550548c8f1aSPyun YongHyeon mode |= BGE_RXMODE_IPV6_ENABLE; 555169b1f509SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 555269b1f509SPyun YongHyeon mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5553548c8f1aSPyun YongHyeon CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5554a6e66cd2SPyun YongHyeon DELAY(10); 555595d67482SBill Paul 5556dedcdf57SPyun YongHyeon /* 5557dedcdf57SPyun YongHyeon * Set the number of good frames to receive after RX MBUF 5558dedcdf57SPyun YongHyeon * Low Watermark has been reached. After the RX MAC receives 5559dedcdf57SPyun YongHyeon * this number of frames, it will drop subsequent incoming 5560dedcdf57SPyun YongHyeon * frames until the MBUF High Watermark is reached. 5561dedcdf57SPyun YongHyeon */ 55623fc5fbfbSPyun YongHyeon if (BGE_IS_57765_PLUS(sc)) 5563b4a256acSPyun YongHyeon CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5564b4a256acSPyun YongHyeon else 5565dedcdf57SPyun YongHyeon CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5566dedcdf57SPyun YongHyeon 55672280c16bSPyun YongHyeon /* Clear MAC statistics. */ 55682280c16bSPyun YongHyeon if (BGE_IS_5705_PLUS(sc)) 55692280c16bSPyun YongHyeon bge_stats_clear_regs(sc); 55702280c16bSPyun YongHyeon 557195d67482SBill Paul /* Tell firmware we're alive. */ 557295d67482SBill Paul BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 557395d67482SBill Paul 557475719184SGleb Smirnoff #ifdef DEVICE_POLLING 557575719184SGleb Smirnoff /* Disable interrupts if we are polling. */ 5576fba8b109SMarcel Moolenaar if (if_getcapenable(ifp) & IFCAP_POLLING) { 557775719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 557875719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 557938cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 558075719184SGleb Smirnoff } else 558175719184SGleb Smirnoff #endif 558275719184SGleb Smirnoff 558395d67482SBill Paul /* Enable host interrupts. */ 558475719184SGleb Smirnoff { 558595d67482SBill Paul BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 558695d67482SBill Paul BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 558738cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 558875719184SGleb Smirnoff } 558995d67482SBill Paul 5590fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5591fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 559295d67482SBill Paul 5593e4146b95SPyun YongHyeon bge_ifmedia_upd_locked(ifp); 5594e4146b95SPyun YongHyeon 55950f9bd73bSSam Leffler callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 55960f9bd73bSSam Leffler } 55970f9bd73bSSam Leffler 55980f9bd73bSSam Leffler static void 55993f74909aSGleb Smirnoff bge_init(void *xsc) 56000f9bd73bSSam Leffler { 56010f9bd73bSSam Leffler struct bge_softc *sc = xsc; 56020f9bd73bSSam Leffler 56030f9bd73bSSam Leffler BGE_LOCK(sc); 56040f9bd73bSSam Leffler bge_init_locked(sc); 56050f9bd73bSSam Leffler BGE_UNLOCK(sc); 560695d67482SBill Paul } 560795d67482SBill Paul 560895d67482SBill Paul /* 560995d67482SBill Paul * Set media options. 561095d67482SBill Paul */ 561195d67482SBill Paul static int 5612fba8b109SMarcel Moolenaar bge_ifmedia_upd(if_t ifp) 561395d67482SBill Paul { 5614fba8b109SMarcel Moolenaar struct bge_softc *sc = if_getsoftc(ifp); 561567d5e043SOleg Bulyzhin int res; 561667d5e043SOleg Bulyzhin 561767d5e043SOleg Bulyzhin BGE_LOCK(sc); 561867d5e043SOleg Bulyzhin res = bge_ifmedia_upd_locked(ifp); 561967d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 562067d5e043SOleg Bulyzhin 562167d5e043SOleg Bulyzhin return (res); 562267d5e043SOleg Bulyzhin } 562367d5e043SOleg Bulyzhin 562467d5e043SOleg Bulyzhin static int 5625fba8b109SMarcel Moolenaar bge_ifmedia_upd_locked(if_t ifp) 562667d5e043SOleg Bulyzhin { 5627fba8b109SMarcel Moolenaar struct bge_softc *sc = if_getsoftc(ifp); 562895d67482SBill Paul struct mii_data *mii; 56294f09c4c7SMarius Strobl struct mii_softc *miisc; 563095d67482SBill Paul struct ifmedia *ifm; 563195d67482SBill Paul 563267d5e043SOleg Bulyzhin BGE_LOCK_ASSERT(sc); 563367d5e043SOleg Bulyzhin 563495d67482SBill Paul ifm = &sc->bge_ifmedia; 563595d67482SBill Paul 563695d67482SBill Paul /* If this is a 1000baseX NIC, enable the TBI port. */ 5637652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 563895d67482SBill Paul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 563995d67482SBill Paul return (EINVAL); 564095d67482SBill Paul switch(IFM_SUBTYPE(ifm->ifm_media)) { 564195d67482SBill Paul case IFM_AUTO: 5642ff50922bSDoug White /* 5643ff50922bSDoug White * The BCM5704 ASIC appears to have a special 5644ff50922bSDoug White * mechanism for programming the autoneg 5645ff50922bSDoug White * advertisement registers in TBI mode. 5646ff50922bSDoug White */ 56470f89fde2SJung-uk Kim if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5648ff50922bSDoug White uint32_t sgdig; 56490f89fde2SJung-uk Kim sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 56500f89fde2SJung-uk Kim if (sgdig & BGE_SGDIGSTS_DONE) { 5651ff50922bSDoug White CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5652ff50922bSDoug White sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5653ff50922bSDoug White sgdig |= BGE_SGDIGCFG_AUTO | 5654ff50922bSDoug White BGE_SGDIGCFG_PAUSE_CAP | 5655ff50922bSDoug White BGE_SGDIGCFG_ASYM_PAUSE; 5656ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5657ff50922bSDoug White sgdig | BGE_SGDIGCFG_SEND); 5658ff50922bSDoug White DELAY(5); 5659ff50922bSDoug White CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5660ff50922bSDoug White } 56610f89fde2SJung-uk Kim } 566295d67482SBill Paul break; 566395d67482SBill Paul case IFM_1000_SX: 566495d67482SBill Paul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 566595d67482SBill Paul BGE_CLRBIT(sc, BGE_MAC_MODE, 566695d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 566795d67482SBill Paul } else { 566895d67482SBill Paul BGE_SETBIT(sc, BGE_MAC_MODE, 566995d67482SBill Paul BGE_MACMODE_HALF_DUPLEX); 567095d67482SBill Paul } 56719b80ffe7SPyun YongHyeon DELAY(40); 567295d67482SBill Paul break; 567395d67482SBill Paul default: 567495d67482SBill Paul return (EINVAL); 567595d67482SBill Paul } 567695d67482SBill Paul return (0); 567795d67482SBill Paul } 567895d67482SBill Paul 56791493e883SOleg Bulyzhin sc->bge_link_evt++; 568095d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 56814f09c4c7SMarius Strobl LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 56823fcb7a53SMarius Strobl PHY_RESET(miisc); 568395d67482SBill Paul mii_mediachg(mii); 568495d67482SBill Paul 5685902827f6SBjoern A. Zeeb /* 5686902827f6SBjoern A. Zeeb * Force an interrupt so that we will call bge_link_upd 5687902827f6SBjoern A. Zeeb * if needed and clear any pending link state attention. 5688902827f6SBjoern A. Zeeb * Without this we are not getting any further interrupts 5689902827f6SBjoern A. Zeeb * for link state changes and thus will not UP the link and 5690902827f6SBjoern A. Zeeb * not be able to send in bge_start_locked. The only 5691902827f6SBjoern A. Zeeb * way to get things working was to receive a packet and 5692902827f6SBjoern A. Zeeb * get an RX intr. 5693902827f6SBjoern A. Zeeb * bge_tick should help for fiber cards and we might not 5694902827f6SBjoern A. Zeeb * need to do this here if BGE_FLAG_TBI is set but as 5695902827f6SBjoern A. Zeeb * we poll for fiber anyway it should not harm. 5696902827f6SBjoern A. Zeeb */ 56974f0794ffSBjoern A. Zeeb if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 56984f0794ffSBjoern A. Zeeb sc->bge_flags & BGE_FLAG_5788) 5699902827f6SBjoern A. Zeeb BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 57004f0794ffSBjoern A. Zeeb else 570163ccfe30SBjoern A. Zeeb BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5702902827f6SBjoern A. Zeeb 570395d67482SBill Paul return (0); 570495d67482SBill Paul } 570595d67482SBill Paul 570695d67482SBill Paul /* 570795d67482SBill Paul * Report current media status. 570895d67482SBill Paul */ 570995d67482SBill Paul static void 5710fba8b109SMarcel Moolenaar bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 571195d67482SBill Paul { 5712fba8b109SMarcel Moolenaar struct bge_softc *sc = if_getsoftc(ifp); 571395d67482SBill Paul struct mii_data *mii; 571495d67482SBill Paul 571567d5e043SOleg Bulyzhin BGE_LOCK(sc); 571695d67482SBill Paul 5717fba8b109SMarcel Moolenaar if ((if_getflags(ifp) & IFF_UP) == 0) { 5718b9d2edd7SPyun YongHyeon BGE_UNLOCK(sc); 5719b9d2edd7SPyun YongHyeon return; 5720b9d2edd7SPyun YongHyeon } 5721652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 572295d67482SBill Paul ifmr->ifm_status = IFM_AVALID; 572395d67482SBill Paul ifmr->ifm_active = IFM_ETHER; 572495d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_STS) & 572595d67482SBill Paul BGE_MACSTAT_TBI_PCS_SYNCHED) 572695d67482SBill Paul ifmr->ifm_status |= IFM_ACTIVE; 57274c0da0ffSGleb Smirnoff else { 57284c0da0ffSGleb Smirnoff ifmr->ifm_active |= IFM_NONE; 572967d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 57304c0da0ffSGleb Smirnoff return; 57314c0da0ffSGleb Smirnoff } 573295d67482SBill Paul ifmr->ifm_active |= IFM_1000_SX; 573395d67482SBill Paul if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 573495d67482SBill Paul ifmr->ifm_active |= IFM_HDX; 573595d67482SBill Paul else 573695d67482SBill Paul ifmr->ifm_active |= IFM_FDX; 573767d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 573895d67482SBill Paul return; 573995d67482SBill Paul } 574095d67482SBill Paul 574195d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 574295d67482SBill Paul mii_pollstat(mii); 574395d67482SBill Paul ifmr->ifm_active = mii->mii_media_active; 574495d67482SBill Paul ifmr->ifm_status = mii->mii_media_status; 574567d5e043SOleg Bulyzhin 574667d5e043SOleg Bulyzhin BGE_UNLOCK(sc); 574795d67482SBill Paul } 574895d67482SBill Paul 574995d67482SBill Paul static int 5750fba8b109SMarcel Moolenaar bge_ioctl(if_t ifp, u_long command, caddr_t data) 575195d67482SBill Paul { 5752fba8b109SMarcel Moolenaar struct bge_softc *sc = if_getsoftc(ifp); 575395d67482SBill Paul struct ifreq *ifr = (struct ifreq *) data; 575495d67482SBill Paul struct mii_data *mii; 5755f9004b6dSJung-uk Kim int flags, mask, error = 0; 575695d67482SBill Paul 575795d67482SBill Paul switch (command) { 575895d67482SBill Paul case SIOCSIFMTU: 5759f5459d4cSPyun YongHyeon if (BGE_IS_JUMBO_CAPABLE(sc) || 5760f5459d4cSPyun YongHyeon (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 57614c0da0ffSGleb Smirnoff if (ifr->ifr_mtu < ETHERMIN || 5762f5459d4cSPyun YongHyeon ifr->ifr_mtu > BGE_JUMBO_MTU) { 576395d67482SBill Paul error = EINVAL; 5764f5459d4cSPyun YongHyeon break; 5765f5459d4cSPyun YongHyeon } 5766f5459d4cSPyun YongHyeon } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5767f5459d4cSPyun YongHyeon error = EINVAL; 5768f5459d4cSPyun YongHyeon break; 5769f5459d4cSPyun YongHyeon } 5770f5459d4cSPyun YongHyeon BGE_LOCK(sc); 5771fba8b109SMarcel Moolenaar if (if_getmtu(ifp) != ifr->ifr_mtu) { 5772fba8b109SMarcel Moolenaar if_setmtu(ifp, ifr->ifr_mtu); 5773fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5774fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 57753a429c8fSPyun YongHyeon bge_init_locked(sc); 577695d67482SBill Paul } 57773a429c8fSPyun YongHyeon } 57783a429c8fSPyun YongHyeon BGE_UNLOCK(sc); 577995d67482SBill Paul break; 578095d67482SBill Paul case SIOCSIFFLAGS: 57810f9bd73bSSam Leffler BGE_LOCK(sc); 5782fba8b109SMarcel Moolenaar if (if_getflags(ifp) & IFF_UP) { 578395d67482SBill Paul /* 578495d67482SBill Paul * If only the state of the PROMISC flag changed, 578595d67482SBill Paul * then just use the 'set promisc mode' command 578695d67482SBill Paul * instead of reinitializing the entire NIC. Doing 578795d67482SBill Paul * a full re-init means reloading the firmware and 578895d67482SBill Paul * waiting for it to start up, which may take a 5789d183af7fSRuslan Ermilov * second or two. Similarly for ALLMULTI. 579095d67482SBill Paul */ 5791fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5792fba8b109SMarcel Moolenaar flags = if_getflags(ifp) ^ sc->bge_if_flags; 57933e9b1bcaSJung-uk Kim if (flags & IFF_PROMISC) 57943e9b1bcaSJung-uk Kim bge_setpromisc(sc); 5795f9004b6dSJung-uk Kim if (flags & IFF_ALLMULTI) 5796d183af7fSRuslan Ermilov bge_setmulti(sc); 579795d67482SBill Paul } else 57980f9bd73bSSam Leffler bge_init_locked(sc); 579995d67482SBill Paul } else { 5800fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 580195d67482SBill Paul bge_stop(sc); 580295d67482SBill Paul } 580395d67482SBill Paul } 5804fba8b109SMarcel Moolenaar sc->bge_if_flags = if_getflags(ifp); 58050f9bd73bSSam Leffler BGE_UNLOCK(sc); 580695d67482SBill Paul error = 0; 580795d67482SBill Paul break; 580895d67482SBill Paul case SIOCADDMULTI: 580995d67482SBill Paul case SIOCDELMULTI: 5810fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 58110f9bd73bSSam Leffler BGE_LOCK(sc); 581295d67482SBill Paul bge_setmulti(sc); 58130f9bd73bSSam Leffler BGE_UNLOCK(sc); 581495d67482SBill Paul error = 0; 581595d67482SBill Paul } 581695d67482SBill Paul break; 581795d67482SBill Paul case SIOCSIFMEDIA: 581895d67482SBill Paul case SIOCGIFMEDIA: 5819652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 582095d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 582195d67482SBill Paul &sc->bge_ifmedia, command); 582295d67482SBill Paul } else { 582395d67482SBill Paul mii = device_get_softc(sc->bge_miibus); 582495d67482SBill Paul error = ifmedia_ioctl(ifp, ifr, 582595d67482SBill Paul &mii->mii_media, command); 582695d67482SBill Paul } 582795d67482SBill Paul break; 582895d67482SBill Paul case SIOCSIFCAP: 5829fba8b109SMarcel Moolenaar mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 583075719184SGleb Smirnoff #ifdef DEVICE_POLLING 583175719184SGleb Smirnoff if (mask & IFCAP_POLLING) { 583275719184SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING) { 583359578ee0SSergey Kandaurov error = ether_poll_register_drv(bge_poll, ifp); 583475719184SGleb Smirnoff if (error) 583575719184SGleb Smirnoff return (error); 583675719184SGleb Smirnoff BGE_LOCK(sc); 583775719184SGleb Smirnoff BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 583875719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 583938cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5840fba8b109SMarcel Moolenaar if_setcapenablebit(ifp, IFCAP_POLLING, 0); 584175719184SGleb Smirnoff BGE_UNLOCK(sc); 584275719184SGleb Smirnoff } else { 584375719184SGleb Smirnoff error = ether_poll_deregister(ifp); 584475719184SGleb Smirnoff /* Enable interrupt even in error case */ 584575719184SGleb Smirnoff BGE_LOCK(sc); 584675719184SGleb Smirnoff BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 584775719184SGleb Smirnoff BGE_PCIMISCCTL_MASK_PCI_INTR); 584838cc658fSJohn Baldwin bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5849fba8b109SMarcel Moolenaar if_setcapenablebit(ifp, 0, IFCAP_POLLING); 585075719184SGleb Smirnoff BGE_UNLOCK(sc); 585175719184SGleb Smirnoff } 585275719184SGleb Smirnoff } 585375719184SGleb Smirnoff #endif 5854d8b57f98SPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 5855fba8b109SMarcel Moolenaar (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5856fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_TXCSUM); 5857fba8b109SMarcel Moolenaar if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5858fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, 5859fba8b109SMarcel Moolenaar sc->bge_csum_features, 0); 586095d67482SBill Paul else 5861fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, 0, 5862fba8b109SMarcel Moolenaar sc->bge_csum_features); 586395d67482SBill Paul } 5864cb2eacc7SYaroslav Tykhiy 5865d8b57f98SPyun YongHyeon if ((mask & IFCAP_RXCSUM) != 0 && 5866fba8b109SMarcel Moolenaar (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5867fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_RXCSUM); 5868d8b57f98SPyun YongHyeon 5869ca3f1187SPyun YongHyeon if ((mask & IFCAP_TSO4) != 0 && 5870fba8b109SMarcel Moolenaar (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5871fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_TSO4); 5872fba8b109SMarcel Moolenaar if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5873fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, CSUM_TSO, 0); 5874ca3f1187SPyun YongHyeon else 5875fba8b109SMarcel Moolenaar if_sethwassistbits(ifp, 0, CSUM_TSO); 5876ca3f1187SPyun YongHyeon } 5877ca3f1187SPyun YongHyeon 5878cb2eacc7SYaroslav Tykhiy if (mask & IFCAP_VLAN_MTU) { 5879fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5880fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5881cb2eacc7SYaroslav Tykhiy bge_init(sc); 5882cb2eacc7SYaroslav Tykhiy } 5883cb2eacc7SYaroslav Tykhiy 588404bde852SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5885fba8b109SMarcel Moolenaar (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5886fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 588704bde852SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5888fba8b109SMarcel Moolenaar (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5889fba8b109SMarcel Moolenaar if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5890fba8b109SMarcel Moolenaar if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5891fba8b109SMarcel Moolenaar if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5892cb2eacc7SYaroslav Tykhiy BGE_LOCK(sc); 5893cb2eacc7SYaroslav Tykhiy bge_setvlan(sc); 5894cb2eacc7SYaroslav Tykhiy BGE_UNLOCK(sc); 589504bde852SPyun YongHyeon } 5896cb2eacc7SYaroslav Tykhiy #ifdef VLAN_CAPABILITIES 5897fba8b109SMarcel Moolenaar if_vlancap(ifp); 5898cb2eacc7SYaroslav Tykhiy #endif 589995d67482SBill Paul break; 590095d67482SBill Paul default: 5901673d9191SSam Leffler error = ether_ioctl(ifp, command, data); 590295d67482SBill Paul break; 590395d67482SBill Paul } 590495d67482SBill Paul 590595d67482SBill Paul return (error); 590695d67482SBill Paul } 590795d67482SBill Paul 590895d67482SBill Paul static void 5909b74e67fbSGleb Smirnoff bge_watchdog(struct bge_softc *sc) 591095d67482SBill Paul { 5911fba8b109SMarcel Moolenaar if_t ifp; 5912b584d2b3SPyun YongHyeon uint32_t status; 591395d67482SBill Paul 5914b74e67fbSGleb Smirnoff BGE_LOCK_ASSERT(sc); 5915b74e67fbSGleb Smirnoff 5916b74e67fbSGleb Smirnoff if (sc->bge_timer == 0 || --sc->bge_timer) 5917b74e67fbSGleb Smirnoff return; 5918b74e67fbSGleb Smirnoff 5919b584d2b3SPyun YongHyeon /* If pause frames are active then don't reset the hardware. */ 5920b584d2b3SPyun YongHyeon if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5921b584d2b3SPyun YongHyeon status = CSR_READ_4(sc, BGE_RX_STS); 5922b584d2b3SPyun YongHyeon if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5923b584d2b3SPyun YongHyeon /* 5924b584d2b3SPyun YongHyeon * If link partner has us in XOFF state then wait for 5925b584d2b3SPyun YongHyeon * the condition to clear. 5926b584d2b3SPyun YongHyeon */ 5927b584d2b3SPyun YongHyeon CSR_WRITE_4(sc, BGE_RX_STS, status); 5928b584d2b3SPyun YongHyeon sc->bge_timer = BGE_TX_TIMEOUT; 5929b584d2b3SPyun YongHyeon return; 5930b584d2b3SPyun YongHyeon } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5931b584d2b3SPyun YongHyeon (status & BGE_RXSTAT_RCVD_XON) != 0) { 5932b584d2b3SPyun YongHyeon /* 5933b584d2b3SPyun YongHyeon * If link partner has us in XOFF state then wait for 5934b584d2b3SPyun YongHyeon * the condition to clear. 5935b584d2b3SPyun YongHyeon */ 5936b584d2b3SPyun YongHyeon CSR_WRITE_4(sc, BGE_RX_STS, status); 5937b584d2b3SPyun YongHyeon sc->bge_timer = BGE_TX_TIMEOUT; 5938b584d2b3SPyun YongHyeon return; 5939b584d2b3SPyun YongHyeon } 5940b584d2b3SPyun YongHyeon /* 5941b584d2b3SPyun YongHyeon * Any other condition is unexpected and the controller 5942b584d2b3SPyun YongHyeon * should be reset. 5943b584d2b3SPyun YongHyeon */ 5944b584d2b3SPyun YongHyeon } 5945b584d2b3SPyun YongHyeon 5946b74e67fbSGleb Smirnoff ifp = sc->bge_ifp; 594795d67482SBill Paul 5948fe806fdaSPyun YongHyeon if_printf(ifp, "watchdog timeout -- resetting\n"); 594995d67482SBill Paul 5950fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5951426742bfSGleb Smirnoff bge_init_locked(sc); 595295d67482SBill Paul 5953fba8b109SMarcel Moolenaar if_incoerrors(ifp, 1); 595495d67482SBill Paul } 595595d67482SBill Paul 59565a147ba6SPyun YongHyeon static void 59575a147ba6SPyun YongHyeon bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 59585a147ba6SPyun YongHyeon { 59595a147ba6SPyun YongHyeon int i; 59605a147ba6SPyun YongHyeon 59615a147ba6SPyun YongHyeon BGE_CLRBIT(sc, reg, bit); 59625a147ba6SPyun YongHyeon 59635a147ba6SPyun YongHyeon for (i = 0; i < BGE_TIMEOUT; i++) { 59645a147ba6SPyun YongHyeon if ((CSR_READ_4(sc, reg) & bit) == 0) 59655a147ba6SPyun YongHyeon return; 59665a147ba6SPyun YongHyeon DELAY(100); 59675a147ba6SPyun YongHyeon } 59685a147ba6SPyun YongHyeon } 59695a147ba6SPyun YongHyeon 597095d67482SBill Paul /* 597195d67482SBill Paul * Stop the adapter and free any mbufs allocated to the 597295d67482SBill Paul * RX and TX lists. 597395d67482SBill Paul */ 597495d67482SBill Paul static void 59753f74909aSGleb Smirnoff bge_stop(struct bge_softc *sc) 597695d67482SBill Paul { 5977fba8b109SMarcel Moolenaar if_t ifp; 597895d67482SBill Paul 59790f9bd73bSSam Leffler BGE_LOCK_ASSERT(sc); 59800f9bd73bSSam Leffler 5981fc74a9f9SBrooks Davis ifp = sc->bge_ifp; 598295d67482SBill Paul 59830f9bd73bSSam Leffler callout_stop(&sc->bge_stat_ch); 598495d67482SBill Paul 598544b63691SBjoern A. Zeeb /* Disable host interrupts. */ 598644b63691SBjoern A. Zeeb BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 598744b63691SBjoern A. Zeeb bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 598844b63691SBjoern A. Zeeb 598944b63691SBjoern A. Zeeb /* 599044b63691SBjoern A. Zeeb * Tell firmware we're shutting down. 599144b63691SBjoern A. Zeeb */ 599244b63691SBjoern A. Zeeb bge_stop_fw(sc); 5993548c8f1aSPyun YongHyeon bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 599444b63691SBjoern A. Zeeb 599595d67482SBill Paul /* 59963f74909aSGleb Smirnoff * Disable all of the receiver blocks. 599795d67482SBill Paul */ 59985a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 59995a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 60005a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 60015a147ba6SPyun YongHyeon if (BGE_IS_5700_FAMILY(sc)) 60025a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 60035a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 60045a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 60055a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 600695d67482SBill Paul 600795d67482SBill Paul /* 60083f74909aSGleb Smirnoff * Disable all of the transmit blocks. 600995d67482SBill Paul */ 60105a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 60115a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 60125a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 60135a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 60145a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 60155a147ba6SPyun YongHyeon if (BGE_IS_5700_FAMILY(sc)) 60165a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 60175a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 601895d67482SBill Paul 601995d67482SBill Paul /* 602095d67482SBill Paul * Shut down all of the memory managers and related 602195d67482SBill Paul * state machines. 602295d67482SBill Paul */ 60235a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 60245a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 60255a147ba6SPyun YongHyeon if (BGE_IS_5700_FAMILY(sc)) 60265a147ba6SPyun YongHyeon bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 60275a147ba6SPyun YongHyeon 60280c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 602995d67482SBill Paul CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 60307ee00338SJung-uk Kim if (!(BGE_IS_5705_PLUS(sc))) { 603195d67482SBill Paul BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 603295d67482SBill Paul BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 60330434d1b8SBill Paul } 60342280c16bSPyun YongHyeon /* Update MAC statistics. */ 60352280c16bSPyun YongHyeon if (BGE_IS_5705_PLUS(sc)) 60362280c16bSPyun YongHyeon bge_stats_update_regs(sc); 603795d67482SBill Paul 60388cb1383cSDoug Ambrisko bge_reset(sc); 6039548c8f1aSPyun YongHyeon bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6040548c8f1aSPyun YongHyeon bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 60418cb1383cSDoug Ambrisko 60428cb1383cSDoug Ambrisko /* 60438cb1383cSDoug Ambrisko * Keep the ASF firmware running if up. 60448cb1383cSDoug Ambrisko */ 60458cb1383cSDoug Ambrisko if (sc->bge_asf_mode & ASF_STACKUP) 60468cb1383cSDoug Ambrisko BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 60478cb1383cSDoug Ambrisko else 604895d67482SBill Paul BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 604995d67482SBill Paul 605095d67482SBill Paul /* Free the RX lists. */ 605195d67482SBill Paul bge_free_rx_ring_std(sc); 605295d67482SBill Paul 605395d67482SBill Paul /* Free jumbo RX list. */ 60544c0da0ffSGleb Smirnoff if (BGE_IS_JUMBO_CAPABLE(sc)) 605595d67482SBill Paul bge_free_rx_ring_jumbo(sc); 605695d67482SBill Paul 605795d67482SBill Paul /* Free TX buffers. */ 605895d67482SBill Paul bge_free_tx_ring(sc); 605995d67482SBill Paul 606095d67482SBill Paul sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 606195d67482SBill Paul 60625dda8085SOleg Bulyzhin /* Clear MAC's link state (PHY may still have link UP). */ 60631493e883SOleg Bulyzhin if (bootverbose && sc->bge_link) 60641493e883SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 60651493e883SOleg Bulyzhin sc->bge_link = 0; 606695d67482SBill Paul 6067fba8b109SMarcel Moolenaar if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 606895d67482SBill Paul } 606995d67482SBill Paul 607095d67482SBill Paul /* 607195d67482SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 607295d67482SBill Paul * get confused by errant DMAs when rebooting. 607395d67482SBill Paul */ 6074b6c974e8SWarner Losh static int 60753f74909aSGleb Smirnoff bge_shutdown(device_t dev) 607695d67482SBill Paul { 607795d67482SBill Paul struct bge_softc *sc; 607895d67482SBill Paul 607995d67482SBill Paul sc = device_get_softc(dev); 60800f9bd73bSSam Leffler BGE_LOCK(sc); 608195d67482SBill Paul bge_stop(sc); 60820f9bd73bSSam Leffler BGE_UNLOCK(sc); 6083b6c974e8SWarner Losh 6084b6c974e8SWarner Losh return (0); 608595d67482SBill Paul } 608614afefa3SPawel Jakub Dawidek 608714afefa3SPawel Jakub Dawidek static int 608814afefa3SPawel Jakub Dawidek bge_suspend(device_t dev) 608914afefa3SPawel Jakub Dawidek { 609014afefa3SPawel Jakub Dawidek struct bge_softc *sc; 609114afefa3SPawel Jakub Dawidek 609214afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 609314afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 609414afefa3SPawel Jakub Dawidek bge_stop(sc); 609514afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 609614afefa3SPawel Jakub Dawidek 609714afefa3SPawel Jakub Dawidek return (0); 609814afefa3SPawel Jakub Dawidek } 609914afefa3SPawel Jakub Dawidek 610014afefa3SPawel Jakub Dawidek static int 610114afefa3SPawel Jakub Dawidek bge_resume(device_t dev) 610214afefa3SPawel Jakub Dawidek { 610314afefa3SPawel Jakub Dawidek struct bge_softc *sc; 6104fba8b109SMarcel Moolenaar if_t ifp; 610514afefa3SPawel Jakub Dawidek 610614afefa3SPawel Jakub Dawidek sc = device_get_softc(dev); 610714afefa3SPawel Jakub Dawidek BGE_LOCK(sc); 610814afefa3SPawel Jakub Dawidek ifp = sc->bge_ifp; 6109fba8b109SMarcel Moolenaar if (if_getflags(ifp) & IFF_UP) { 611014afefa3SPawel Jakub Dawidek bge_init_locked(sc); 6111fba8b109SMarcel Moolenaar if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 611214afefa3SPawel Jakub Dawidek bge_start_locked(ifp); 611314afefa3SPawel Jakub Dawidek } 611414afefa3SPawel Jakub Dawidek BGE_UNLOCK(sc); 611514afefa3SPawel Jakub Dawidek 611614afefa3SPawel Jakub Dawidek return (0); 611714afefa3SPawel Jakub Dawidek } 6118dab5cd05SOleg Bulyzhin 6119dab5cd05SOleg Bulyzhin static void 61203f74909aSGleb Smirnoff bge_link_upd(struct bge_softc *sc) 6121dab5cd05SOleg Bulyzhin { 61221f313773SOleg Bulyzhin struct mii_data *mii; 61231f313773SOleg Bulyzhin uint32_t link, status; 6124dab5cd05SOleg Bulyzhin 6125dab5cd05SOleg Bulyzhin BGE_LOCK_ASSERT(sc); 61261f313773SOleg Bulyzhin 61273f74909aSGleb Smirnoff /* Clear 'pending link event' flag. */ 61287b97099dSOleg Bulyzhin sc->bge_link_evt = 0; 61297b97099dSOleg Bulyzhin 6130dab5cd05SOleg Bulyzhin /* 6131dab5cd05SOleg Bulyzhin * Process link state changes. 6132dab5cd05SOleg Bulyzhin * Grrr. The link status word in the status block does 6133dab5cd05SOleg Bulyzhin * not work correctly on the BCM5700 rev AX and BX chips, 6134dab5cd05SOleg Bulyzhin * according to all available information. Hence, we have 6135dab5cd05SOleg Bulyzhin * to enable MII interrupts in order to properly obtain 6136dab5cd05SOleg Bulyzhin * async link changes. Unfortunately, this also means that 6137dab5cd05SOleg Bulyzhin * we have to read the MAC status register to detect link 6138dab5cd05SOleg Bulyzhin * changes, thereby adding an additional register access to 6139dab5cd05SOleg Bulyzhin * the interrupt handler. 61401f313773SOleg Bulyzhin * 61411f313773SOleg Bulyzhin * XXX: perhaps link state detection procedure used for 61424c0da0ffSGleb Smirnoff * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6143dab5cd05SOleg Bulyzhin */ 6144dab5cd05SOleg Bulyzhin 61451f313773SOleg Bulyzhin if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 61464c0da0ffSGleb Smirnoff sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6147dab5cd05SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 6148dab5cd05SOleg Bulyzhin if (status & BGE_MACSTAT_MI_INTERRUPT) { 61491f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 61505dda8085SOleg Bulyzhin mii_pollstat(mii); 61511f313773SOleg Bulyzhin if (!sc->bge_link && 61521f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 61531f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 61541f313773SOleg Bulyzhin sc->bge_link++; 61551f313773SOleg Bulyzhin if (bootverbose) 61561f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 61571f313773SOleg Bulyzhin } else if (sc->bge_link && 61581f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 61591f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 61601f313773SOleg Bulyzhin sc->bge_link = 0; 61611f313773SOleg Bulyzhin if (bootverbose) 61621f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 61631f313773SOleg Bulyzhin } 61641f313773SOleg Bulyzhin 61653f74909aSGleb Smirnoff /* Clear the interrupt. */ 6166dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6167dab5cd05SOleg Bulyzhin BGE_EVTENB_MI_INTERRUPT); 6168daeeb75cSPyun YongHyeon bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6169daeeb75cSPyun YongHyeon BRGPHY_MII_ISR); 6170daeeb75cSPyun YongHyeon bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6171daeeb75cSPyun YongHyeon BRGPHY_MII_IMR, BRGPHY_INTRS); 6172dab5cd05SOleg Bulyzhin } 6173dab5cd05SOleg Bulyzhin return; 6174dab5cd05SOleg Bulyzhin } 6175dab5cd05SOleg Bulyzhin 6176652ae483SGleb Smirnoff if (sc->bge_flags & BGE_FLAG_TBI) { 61771f313773SOleg Bulyzhin status = CSR_READ_4(sc, BGE_MAC_STS); 61787b97099dSOleg Bulyzhin if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 61797b97099dSOleg Bulyzhin if (!sc->bge_link) { 61801f313773SOleg Bulyzhin sc->bge_link++; 61819b80ffe7SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 61821f313773SOleg Bulyzhin BGE_CLRBIT(sc, BGE_MAC_MODE, 61831f313773SOleg Bulyzhin BGE_MACMODE_TBI_SEND_CFGS); 61849b80ffe7SPyun YongHyeon DELAY(40); 61859b80ffe7SPyun YongHyeon } 61860c8aa4eaSJung-uk Kim CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 61871f313773SOleg Bulyzhin if (bootverbose) 61881f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 61893f74909aSGleb Smirnoff if_link_state_change(sc->bge_ifp, 61903f74909aSGleb Smirnoff LINK_STATE_UP); 61917b97099dSOleg Bulyzhin } 61921f313773SOleg Bulyzhin } else if (sc->bge_link) { 6193dab5cd05SOleg Bulyzhin sc->bge_link = 0; 61941f313773SOleg Bulyzhin if (bootverbose) 61951f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 61967b97099dSOleg Bulyzhin if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 61971f313773SOleg Bulyzhin } 61986ede2cfaSPyun YongHyeon } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 61991f313773SOleg Bulyzhin /* 62000c8aa4eaSJung-uk Kim * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 62010c8aa4eaSJung-uk Kim * in status word always set. Workaround this bug by reading 62020c8aa4eaSJung-uk Kim * PHY link status directly. 62031f313773SOleg Bulyzhin */ 62041f313773SOleg Bulyzhin link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 62051f313773SOleg Bulyzhin 62061f313773SOleg Bulyzhin if (link != sc->bge_link || 62071f313773SOleg Bulyzhin sc->bge_asicrev == BGE_ASICREV_BCM5700) { 62081f313773SOleg Bulyzhin mii = device_get_softc(sc->bge_miibus); 62095dda8085SOleg Bulyzhin mii_pollstat(mii); 62101f313773SOleg Bulyzhin if (!sc->bge_link && 62111f313773SOleg Bulyzhin mii->mii_media_status & IFM_ACTIVE && 62121f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 62131f313773SOleg Bulyzhin sc->bge_link++; 62141f313773SOleg Bulyzhin if (bootverbose) 62151f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link UP\n"); 62161f313773SOleg Bulyzhin } else if (sc->bge_link && 62171f313773SOleg Bulyzhin (!(mii->mii_media_status & IFM_ACTIVE) || 62181f313773SOleg Bulyzhin IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 62191f313773SOleg Bulyzhin sc->bge_link = 0; 62201f313773SOleg Bulyzhin if (bootverbose) 62211f313773SOleg Bulyzhin if_printf(sc->bge_ifp, "link DOWN\n"); 62221f313773SOleg Bulyzhin } 62231f313773SOleg Bulyzhin } 62240c8aa4eaSJung-uk Kim } else { 62250c8aa4eaSJung-uk Kim /* 62266ede2cfaSPyun YongHyeon * For controllers that call mii_tick, we have to poll 62276ede2cfaSPyun YongHyeon * link status. 62280c8aa4eaSJung-uk Kim */ 62296ede2cfaSPyun YongHyeon mii = device_get_softc(sc->bge_miibus); 62306ede2cfaSPyun YongHyeon mii_pollstat(mii); 62316ede2cfaSPyun YongHyeon bge_miibus_statchg(sc->bge_dev); 6232dab5cd05SOleg Bulyzhin } 6233dab5cd05SOleg Bulyzhin 62342246e8c6SPyun YongHyeon /* Disable MAC attention when link is up. */ 6235dab5cd05SOleg Bulyzhin CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6236dab5cd05SOleg Bulyzhin BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6237dab5cd05SOleg Bulyzhin BGE_MACSTAT_LINK_CHANGED); 6238dab5cd05SOleg Bulyzhin } 62396f8718a3SScott Long 62406f8718a3SScott Long static void 62416f8718a3SScott Long bge_add_sysctls(struct bge_softc *sc) 62426f8718a3SScott Long { 62436f8718a3SScott Long struct sysctl_ctx_list *ctx; 62442280c16bSPyun YongHyeon struct sysctl_oid_list *children; 62457e32f79aSPyun YongHyeon int unit; 62466f8718a3SScott Long 62476f8718a3SScott Long ctx = device_get_sysctl_ctx(sc->bge_dev); 62486f8718a3SScott Long children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 62496f8718a3SScott Long 62506f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 62516f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 62526f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 62536f8718a3SScott Long "Debug Information"); 62546f8718a3SScott Long 62556f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 62566f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6257548c8f1aSPyun YongHyeon "MAC Register Read"); 6258548c8f1aSPyun YongHyeon 6259548c8f1aSPyun YongHyeon SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6260548c8f1aSPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6261548c8f1aSPyun YongHyeon "APE Register Read"); 62626f8718a3SScott Long 62636f8718a3SScott Long SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 62646f8718a3SScott Long CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 62656f8718a3SScott Long "Memory Read"); 62666f8718a3SScott Long 62676f8718a3SScott Long #endif 6268763757b2SScott Long 62697e32f79aSPyun YongHyeon unit = device_get_unit(sc->bge_dev); 6270beaa2ae1SPyun YongHyeon /* 6271beaa2ae1SPyun YongHyeon * A common design characteristic for many Broadcom client controllers 6272beaa2ae1SPyun YongHyeon * is that they only support a single outstanding DMA read operation 6273beaa2ae1SPyun YongHyeon * on the PCIe bus. This means that it will take twice as long to fetch 6274beaa2ae1SPyun YongHyeon * a TX frame that is split into header and payload buffers as it does 6275beaa2ae1SPyun YongHyeon * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6276beaa2ae1SPyun YongHyeon * these controllers, coalescing buffers to reduce the number of memory 6277beaa2ae1SPyun YongHyeon * reads is effective way to get maximum performance(about 940Mbps). 6278beaa2ae1SPyun YongHyeon * Without collapsing TX buffers the maximum TCP bulk transfer 6279beaa2ae1SPyun YongHyeon * performance is about 850Mbps. However forcing coalescing mbufs 6280beaa2ae1SPyun YongHyeon * consumes a lot of CPU cycles, so leave it off by default. 6281beaa2ae1SPyun YongHyeon */ 62827e32f79aSPyun YongHyeon sc->bge_forced_collapse = 0; 6283beaa2ae1SPyun YongHyeon SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6284af3b2549SHans Petter Selasky CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6285beaa2ae1SPyun YongHyeon "Number of fragmented TX buffers of a frame allowed before " 6286beaa2ae1SPyun YongHyeon "forced collapsing"); 6287beaa2ae1SPyun YongHyeon 62882ae7f64bSPyun YongHyeon sc->bge_msi = 1; 62892ae7f64bSPyun YongHyeon SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6290af3b2549SHans Petter Selasky CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 62915c952e8dSPyun YongHyeon 629235f945cdSPyun YongHyeon /* 629335f945cdSPyun YongHyeon * It seems all Broadcom controllers have a bug that can generate UDP 629435f945cdSPyun YongHyeon * datagrams with checksum value 0 when TX UDP checksum offloading is 629535f945cdSPyun YongHyeon * enabled. Generating UDP checksum value 0 is RFC 768 violation. 629635f945cdSPyun YongHyeon * Even though the probability of generating such UDP datagrams is 629735f945cdSPyun YongHyeon * low, I don't want to see FreeBSD boxes to inject such datagrams 629835f945cdSPyun YongHyeon * into network so disable UDP checksum offloading by default. Users 629935f945cdSPyun YongHyeon * still override this behavior by setting a sysctl variable, 630035f945cdSPyun YongHyeon * dev.bge.0.forced_udpcsum. 630135f945cdSPyun YongHyeon */ 630235f945cdSPyun YongHyeon sc->bge_forced_udpcsum = 0; 630335f945cdSPyun YongHyeon SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6304af3b2549SHans Petter Selasky CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 630535f945cdSPyun YongHyeon "Enable UDP checksum offloading even if controller can " 630635f945cdSPyun YongHyeon "generate UDP checksum value 0"); 630735f945cdSPyun YongHyeon 6308d949071dSJung-uk Kim if (BGE_IS_5705_PLUS(sc)) 63092280c16bSPyun YongHyeon bge_add_sysctl_stats_regs(sc, ctx, children); 63102280c16bSPyun YongHyeon else 63112280c16bSPyun YongHyeon bge_add_sysctl_stats(sc, ctx, children); 63122280c16bSPyun YongHyeon } 6313d949071dSJung-uk Kim 63142280c16bSPyun YongHyeon #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 63152280c16bSPyun YongHyeon SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 63162280c16bSPyun YongHyeon sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 63172280c16bSPyun YongHyeon desc) 63182280c16bSPyun YongHyeon 63192280c16bSPyun YongHyeon static void 63202280c16bSPyun YongHyeon bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 63212280c16bSPyun YongHyeon struct sysctl_oid_list *parent) 63222280c16bSPyun YongHyeon { 63232280c16bSPyun YongHyeon struct sysctl_oid *tree; 63242280c16bSPyun YongHyeon struct sysctl_oid_list *children, *schildren; 63252280c16bSPyun YongHyeon 63262280c16bSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6327763757b2SScott Long NULL, "BGE Statistics"); 6328763757b2SScott Long schildren = children = SYSCTL_CHILDREN(tree); 6329763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6330763757b2SScott Long children, COSFramesDroppedDueToFilters, 6331763757b2SScott Long "FramesDroppedDueToFilters"); 6332763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6333763757b2SScott Long children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6334763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6335763757b2SScott Long children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6336763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6337763757b2SScott Long children, nicNoMoreRxBDs, "NoMoreRxBDs"); 633806e83c7eSScott Long BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 633906e83c7eSScott Long children, ifInDiscards, "InputDiscards"); 634006e83c7eSScott Long BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 634106e83c7eSScott Long children, ifInErrors, "InputErrors"); 6342763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6343763757b2SScott Long children, nicRecvThresholdHit, "RecvThresholdHit"); 6344763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6345763757b2SScott Long children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6346763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6347763757b2SScott Long children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6348763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6349763757b2SScott Long children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6350763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6351763757b2SScott Long children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6352763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6353763757b2SScott Long children, nicRingStatusUpdate, "RingStatusUpdate"); 6354763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6355763757b2SScott Long children, nicInterrupts, "Interrupts"); 6356763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6357763757b2SScott Long children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6358763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6359763757b2SScott Long children, nicSendThresholdHit, "SendThresholdHit"); 6360763757b2SScott Long 6361763757b2SScott Long tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6362763757b2SScott Long NULL, "BGE RX Statistics"); 6363763757b2SScott Long children = SYSCTL_CHILDREN(tree); 6364763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 63651cd4773bSPyun YongHyeon children, rxstats.ifHCInOctets, "ifHCInOctets"); 6366763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6367763757b2SScott Long children, rxstats.etherStatsFragments, "Fragments"); 6368763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 63691cd4773bSPyun YongHyeon children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6370763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6371763757b2SScott Long children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6372763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6373763757b2SScott Long children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6374763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6375763757b2SScott Long children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6376763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6377763757b2SScott Long children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6378763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6379763757b2SScott Long children, rxstats.xoffPauseFramesReceived, 6380763757b2SScott Long "xoffPauseFramesReceived"); 6381763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6382763757b2SScott Long children, rxstats.macControlFramesReceived, 6383763757b2SScott Long "ControlFramesReceived"); 6384763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6385763757b2SScott Long children, rxstats.xoffStateEntered, "xoffStateEntered"); 6386763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6387763757b2SScott Long children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6388763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6389763757b2SScott Long children, rxstats.etherStatsJabbers, "Jabbers"); 6390763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6391763757b2SScott Long children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6392763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 639306e83c7eSScott Long children, rxstats.inRangeLengthError, "inRangeLengthError"); 6394763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 639506e83c7eSScott Long children, rxstats.outRangeLengthError, "outRangeLengthError"); 6396763757b2SScott Long 6397763757b2SScott Long tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6398763757b2SScott Long NULL, "BGE TX Statistics"); 6399763757b2SScott Long children = SYSCTL_CHILDREN(tree); 6400763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 64011cd4773bSPyun YongHyeon children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6402763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6403763757b2SScott Long children, txstats.etherStatsCollisions, "Collisions"); 6404763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6405763757b2SScott Long children, txstats.outXonSent, "XonSent"); 6406763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6407763757b2SScott Long children, txstats.outXoffSent, "XoffSent"); 6408763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6409763757b2SScott Long children, txstats.flowControlDone, "flowControlDone"); 6410763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6411763757b2SScott Long children, txstats.dot3StatsInternalMacTransmitErrors, 6412763757b2SScott Long "InternalMacTransmitErrors"); 6413763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6414763757b2SScott Long children, txstats.dot3StatsSingleCollisionFrames, 6415763757b2SScott Long "SingleCollisionFrames"); 6416763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6417763757b2SScott Long children, txstats.dot3StatsMultipleCollisionFrames, 6418763757b2SScott Long "MultipleCollisionFrames"); 6419763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6420763757b2SScott Long children, txstats.dot3StatsDeferredTransmissions, 6421763757b2SScott Long "DeferredTransmissions"); 6422763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6423763757b2SScott Long children, txstats.dot3StatsExcessiveCollisions, 6424763757b2SScott Long "ExcessiveCollisions"); 6425763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 642606e83c7eSScott Long children, txstats.dot3StatsLateCollisions, 642706e83c7eSScott Long "LateCollisions"); 6428763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 64291cd4773bSPyun YongHyeon children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6430763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6431763757b2SScott Long children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6432763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6433763757b2SScott Long children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6434763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6435763757b2SScott Long children, txstats.dot3StatsCarrierSenseErrors, 6436763757b2SScott Long "CarrierSenseErrors"); 6437763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6438763757b2SScott Long children, txstats.ifOutDiscards, "Discards"); 6439763757b2SScott Long BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6440763757b2SScott Long children, txstats.ifOutErrors, "Errors"); 6441763757b2SScott Long } 6442763757b2SScott Long 64432280c16bSPyun YongHyeon #undef BGE_SYSCTL_STAT 64442280c16bSPyun YongHyeon 64452280c16bSPyun YongHyeon #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 64466dc7dc9aSMatthew D Fleming SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 64472280c16bSPyun YongHyeon 64482280c16bSPyun YongHyeon static void 64492280c16bSPyun YongHyeon bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 64502280c16bSPyun YongHyeon struct sysctl_oid_list *parent) 64512280c16bSPyun YongHyeon { 64522280c16bSPyun YongHyeon struct sysctl_oid *tree; 64532280c16bSPyun YongHyeon struct sysctl_oid_list *child, *schild; 64542280c16bSPyun YongHyeon struct bge_mac_stats *stats; 64552280c16bSPyun YongHyeon 64562280c16bSPyun YongHyeon stats = &sc->bge_mac_stats; 64572280c16bSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 64582280c16bSPyun YongHyeon NULL, "BGE Statistics"); 64592280c16bSPyun YongHyeon schild = child = SYSCTL_CHILDREN(tree); 64602280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 64612280c16bSPyun YongHyeon &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 64622280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 64632280c16bSPyun YongHyeon &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 64642280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 64652280c16bSPyun YongHyeon &stats->DmaWriteHighPriQueueFull, 64662280c16bSPyun YongHyeon "NIC DMA Write High Priority Queue Full"); 64672280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 64682280c16bSPyun YongHyeon &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 64692280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 64702280c16bSPyun YongHyeon &stats->InputDiscards, "Discarded Input Frames"); 64712280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 64722280c16bSPyun YongHyeon &stats->InputErrors, "Input Errors"); 64732280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 64742280c16bSPyun YongHyeon &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 64752280c16bSPyun YongHyeon 64762280c16bSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 64772280c16bSPyun YongHyeon NULL, "BGE RX Statistics"); 64782280c16bSPyun YongHyeon child = SYSCTL_CHILDREN(tree); 64792280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 64802280c16bSPyun YongHyeon &stats->ifHCInOctets, "Inbound Octets"); 64812280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 64822280c16bSPyun YongHyeon &stats->etherStatsFragments, "Fragments"); 64831cd4773bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 64842280c16bSPyun YongHyeon &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 64852280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 64862280c16bSPyun YongHyeon &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 64872280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 64882280c16bSPyun YongHyeon &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 64892280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 64902280c16bSPyun YongHyeon &stats->dot3StatsFCSErrors, "FCS Errors"); 64912280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 64922280c16bSPyun YongHyeon &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 64932280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 64942280c16bSPyun YongHyeon &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 64952280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 64962280c16bSPyun YongHyeon &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 64972280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 64982280c16bSPyun YongHyeon &stats->macControlFramesReceived, "MAC Control Frames Received"); 64992280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 65002280c16bSPyun YongHyeon &stats->xoffStateEntered, "XOFF State Entered"); 65012280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 65022280c16bSPyun YongHyeon &stats->dot3StatsFramesTooLong, "Frames Too Long"); 65032280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 65042280c16bSPyun YongHyeon &stats->etherStatsJabbers, "Jabbers"); 65052280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 65062280c16bSPyun YongHyeon &stats->etherStatsUndersizePkts, "Undersized Packets"); 65072280c16bSPyun YongHyeon 65082280c16bSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 65092280c16bSPyun YongHyeon NULL, "BGE TX Statistics"); 65102280c16bSPyun YongHyeon child = SYSCTL_CHILDREN(tree); 65111cd4773bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 65122280c16bSPyun YongHyeon &stats->ifHCOutOctets, "Outbound Octets"); 65132280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 65142280c16bSPyun YongHyeon &stats->etherStatsCollisions, "TX Collisions"); 65152280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 65162280c16bSPyun YongHyeon &stats->outXonSent, "XON Sent"); 65172280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 65182280c16bSPyun YongHyeon &stats->outXoffSent, "XOFF Sent"); 65192280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 65202280c16bSPyun YongHyeon &stats->dot3StatsInternalMacTransmitErrors, 65212280c16bSPyun YongHyeon "Internal MAC TX Errors"); 65222280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 65232280c16bSPyun YongHyeon &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 65242280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 65252280c16bSPyun YongHyeon &stats->dot3StatsMultipleCollisionFrames, 65262280c16bSPyun YongHyeon "Multiple Collision Frames"); 65272280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 65282280c16bSPyun YongHyeon &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 65292280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 65302280c16bSPyun YongHyeon &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 65312280c16bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 65322280c16bSPyun YongHyeon &stats->dot3StatsLateCollisions, "Late Collisions"); 65331cd4773bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 65342280c16bSPyun YongHyeon &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 65351cd4773bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 65362280c16bSPyun YongHyeon &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 65371cd4773bSPyun YongHyeon BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 65382280c16bSPyun YongHyeon &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 65392280c16bSPyun YongHyeon } 65402280c16bSPyun YongHyeon 65412280c16bSPyun YongHyeon #undef BGE_SYSCTL_STAT_ADD64 65422280c16bSPyun YongHyeon 6543763757b2SScott Long static int 6544763757b2SScott Long bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6545763757b2SScott Long { 6546763757b2SScott Long struct bge_softc *sc; 654706e83c7eSScott Long uint32_t result; 6548d949071dSJung-uk Kim int offset; 6549763757b2SScott Long 6550763757b2SScott Long sc = (struct bge_softc *)arg1; 6551763757b2SScott Long offset = arg2; 6552d949071dSJung-uk Kim result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6553d949071dSJung-uk Kim offsetof(bge_hostaddr, bge_addr_lo)); 6554041b706bSDavid Malone return (sysctl_handle_int(oidp, &result, 0, req)); 65556f8718a3SScott Long } 65566f8718a3SScott Long 65576f8718a3SScott Long #ifdef BGE_REGISTER_DEBUG 65586f8718a3SScott Long static int 65596f8718a3SScott Long bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 65606f8718a3SScott Long { 65616f8718a3SScott Long struct bge_softc *sc; 65626f8718a3SScott Long uint16_t *sbdata; 656328276ad6SPyun YongHyeon int error, result, sbsz; 65646f8718a3SScott Long int i, j; 65656f8718a3SScott Long 65666f8718a3SScott Long result = -1; 65676f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 65686f8718a3SScott Long if (error || (req->newptr == NULL)) 65696f8718a3SScott Long return (error); 65706f8718a3SScott Long 65716f8718a3SScott Long if (result == 1) { 65726f8718a3SScott Long sc = (struct bge_softc *)arg1; 65736f8718a3SScott Long 657428276ad6SPyun YongHyeon if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 657528276ad6SPyun YongHyeon sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 657628276ad6SPyun YongHyeon sbsz = BGE_STATUS_BLK_SZ; 657728276ad6SPyun YongHyeon else 657828276ad6SPyun YongHyeon sbsz = 32; 65796f8718a3SScott Long sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 65806f8718a3SScott Long printf("Status Block:\n"); 658128276ad6SPyun YongHyeon BGE_LOCK(sc); 658228276ad6SPyun YongHyeon bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 658328276ad6SPyun YongHyeon sc->bge_cdata.bge_status_map, 658428276ad6SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 658528276ad6SPyun YongHyeon for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 65866f8718a3SScott Long printf("%06x:", i); 658728276ad6SPyun YongHyeon for (j = 0; j < 8; j++) 658828276ad6SPyun YongHyeon printf(" %04x", sbdata[i++]); 65896f8718a3SScott Long printf("\n"); 65906f8718a3SScott Long } 65916f8718a3SScott Long 65926f8718a3SScott Long printf("Registers:\n"); 65930c8aa4eaSJung-uk Kim for (i = 0x800; i < 0xA00; ) { 65946f8718a3SScott Long printf("%06x:", i); 65956f8718a3SScott Long for (j = 0; j < 8; j++) { 65966f8718a3SScott Long printf(" %08x", CSR_READ_4(sc, i)); 65976f8718a3SScott Long i += 4; 65986f8718a3SScott Long } 65996f8718a3SScott Long printf("\n"); 66006f8718a3SScott Long } 660128276ad6SPyun YongHyeon BGE_UNLOCK(sc); 66026f8718a3SScott Long 66036f8718a3SScott Long printf("Hardware Flags:\n"); 660428276ad6SPyun YongHyeon if (BGE_IS_5717_PLUS(sc)) 660528276ad6SPyun YongHyeon printf(" - 5717 Plus\n"); 6606a5779553SStanislav Sedov if (BGE_IS_5755_PLUS(sc)) 6607a5779553SStanislav Sedov printf(" - 5755 Plus\n"); 66085345bad0SScott Long if (BGE_IS_575X_PLUS(sc)) 66096f8718a3SScott Long printf(" - 575X Plus\n"); 66105345bad0SScott Long if (BGE_IS_5705_PLUS(sc)) 66116f8718a3SScott Long printf(" - 5705 Plus\n"); 66125345bad0SScott Long if (BGE_IS_5714_FAMILY(sc)) 66135345bad0SScott Long printf(" - 5714 Family\n"); 66145345bad0SScott Long if (BGE_IS_5700_FAMILY(sc)) 66155345bad0SScott Long printf(" - 5700 Family\n"); 66166f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_JUMBO) 66176f8718a3SScott Long printf(" - Supports Jumbo Frames\n"); 66186f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIX) 66196f8718a3SScott Long printf(" - PCI-X Bus\n"); 66206f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_PCIE) 66216f8718a3SScott Long printf(" - PCI Express Bus\n"); 66227d3d9608SPyun YongHyeon if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 66236f8718a3SScott Long printf(" - No 3 LEDs\n"); 66246f8718a3SScott Long if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 66256f8718a3SScott Long printf(" - RX Alignment Bug\n"); 66266f8718a3SScott Long } 66276f8718a3SScott Long 66286f8718a3SScott Long return (error); 66296f8718a3SScott Long } 66306f8718a3SScott Long 66316f8718a3SScott Long static int 66326f8718a3SScott Long bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 66336f8718a3SScott Long { 66346f8718a3SScott Long struct bge_softc *sc; 66356f8718a3SScott Long int error; 66366f8718a3SScott Long uint16_t result; 66376f8718a3SScott Long uint32_t val; 66386f8718a3SScott Long 66396f8718a3SScott Long result = -1; 66406f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 66416f8718a3SScott Long if (error || (req->newptr == NULL)) 66426f8718a3SScott Long return (error); 66436f8718a3SScott Long 66446f8718a3SScott Long if (result < 0x8000) { 66456f8718a3SScott Long sc = (struct bge_softc *)arg1; 66466f8718a3SScott Long val = CSR_READ_4(sc, result); 66476f8718a3SScott Long printf("reg 0x%06X = 0x%08X\n", result, val); 66486f8718a3SScott Long } 66496f8718a3SScott Long 66506f8718a3SScott Long return (error); 66516f8718a3SScott Long } 66526f8718a3SScott Long 66536f8718a3SScott Long static int 6654548c8f1aSPyun YongHyeon bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6655548c8f1aSPyun YongHyeon { 6656548c8f1aSPyun YongHyeon struct bge_softc *sc; 6657548c8f1aSPyun YongHyeon int error; 6658548c8f1aSPyun YongHyeon uint16_t result; 6659548c8f1aSPyun YongHyeon uint32_t val; 6660548c8f1aSPyun YongHyeon 6661548c8f1aSPyun YongHyeon result = -1; 6662548c8f1aSPyun YongHyeon error = sysctl_handle_int(oidp, &result, 0, req); 6663548c8f1aSPyun YongHyeon if (error || (req->newptr == NULL)) 6664548c8f1aSPyun YongHyeon return (error); 6665548c8f1aSPyun YongHyeon 6666548c8f1aSPyun YongHyeon if (result < 0x8000) { 6667548c8f1aSPyun YongHyeon sc = (struct bge_softc *)arg1; 6668548c8f1aSPyun YongHyeon val = APE_READ_4(sc, result); 6669548c8f1aSPyun YongHyeon printf("reg 0x%06X = 0x%08X\n", result, val); 6670548c8f1aSPyun YongHyeon } 6671548c8f1aSPyun YongHyeon 6672548c8f1aSPyun YongHyeon return (error); 6673548c8f1aSPyun YongHyeon } 6674548c8f1aSPyun YongHyeon 6675548c8f1aSPyun YongHyeon static int 66766f8718a3SScott Long bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 66776f8718a3SScott Long { 66786f8718a3SScott Long struct bge_softc *sc; 66796f8718a3SScott Long int error; 66806f8718a3SScott Long uint16_t result; 66816f8718a3SScott Long uint32_t val; 66826f8718a3SScott Long 66836f8718a3SScott Long result = -1; 66846f8718a3SScott Long error = sysctl_handle_int(oidp, &result, 0, req); 66856f8718a3SScott Long if (error || (req->newptr == NULL)) 66866f8718a3SScott Long return (error); 66876f8718a3SScott Long 66886f8718a3SScott Long if (result < 0x8000) { 66896f8718a3SScott Long sc = (struct bge_softc *)arg1; 66906f8718a3SScott Long val = bge_readmem_ind(sc, result); 66916f8718a3SScott Long printf("mem 0x%06X = 0x%08X\n", result, val); 66926f8718a3SScott Long } 66936f8718a3SScott Long 66946f8718a3SScott Long return (error); 66956f8718a3SScott Long } 66966f8718a3SScott Long #endif 669738cc658fSJohn Baldwin 669838cc658fSJohn Baldwin static int 66995fea260fSMarius Strobl bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 67005fea260fSMarius Strobl { 67015fea260fSMarius Strobl 67025fea260fSMarius Strobl if (sc->bge_flags & BGE_FLAG_EADDR) 67035fea260fSMarius Strobl return (1); 67045fea260fSMarius Strobl 67055fea260fSMarius Strobl #ifdef __sparc64__ 67065fea260fSMarius Strobl OF_getetheraddr(sc->bge_dev, ether_addr); 67075fea260fSMarius Strobl return (0); 67085fea260fSMarius Strobl #endif 67095fea260fSMarius Strobl return (1); 67105fea260fSMarius Strobl } 67115fea260fSMarius Strobl 67125fea260fSMarius Strobl static int 671338cc658fSJohn Baldwin bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 671438cc658fSJohn Baldwin { 671538cc658fSJohn Baldwin uint32_t mac_addr; 671638cc658fSJohn Baldwin 671773635418SPyun YongHyeon mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 671838cc658fSJohn Baldwin if ((mac_addr >> 16) == 0x484b) { 671938cc658fSJohn Baldwin ether_addr[0] = (uint8_t)(mac_addr >> 8); 672038cc658fSJohn Baldwin ether_addr[1] = (uint8_t)mac_addr; 672173635418SPyun YongHyeon mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 672238cc658fSJohn Baldwin ether_addr[2] = (uint8_t)(mac_addr >> 24); 672338cc658fSJohn Baldwin ether_addr[3] = (uint8_t)(mac_addr >> 16); 672438cc658fSJohn Baldwin ether_addr[4] = (uint8_t)(mac_addr >> 8); 672538cc658fSJohn Baldwin ether_addr[5] = (uint8_t)mac_addr; 67265fea260fSMarius Strobl return (0); 672738cc658fSJohn Baldwin } 67285fea260fSMarius Strobl return (1); 672938cc658fSJohn Baldwin } 673038cc658fSJohn Baldwin 673138cc658fSJohn Baldwin static int 673238cc658fSJohn Baldwin bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 673338cc658fSJohn Baldwin { 673438cc658fSJohn Baldwin int mac_offset = BGE_EE_MAC_OFFSET; 673538cc658fSJohn Baldwin 673638cc658fSJohn Baldwin if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 673738cc658fSJohn Baldwin mac_offset = BGE_EE_MAC_OFFSET_5906; 673838cc658fSJohn Baldwin 67395fea260fSMarius Strobl return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 67405fea260fSMarius Strobl ETHER_ADDR_LEN)); 674138cc658fSJohn Baldwin } 674238cc658fSJohn Baldwin 674338cc658fSJohn Baldwin static int 674438cc658fSJohn Baldwin bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 674538cc658fSJohn Baldwin { 674638cc658fSJohn Baldwin 67475fea260fSMarius Strobl if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 67485fea260fSMarius Strobl return (1); 67495fea260fSMarius Strobl 67505fea260fSMarius Strobl return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 67515fea260fSMarius Strobl ETHER_ADDR_LEN)); 675238cc658fSJohn Baldwin } 675338cc658fSJohn Baldwin 675438cc658fSJohn Baldwin static int 675538cc658fSJohn Baldwin bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 675638cc658fSJohn Baldwin { 675738cc658fSJohn Baldwin static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 675838cc658fSJohn Baldwin /* NOTE: Order is critical */ 67595fea260fSMarius Strobl bge_get_eaddr_fw, 676038cc658fSJohn Baldwin bge_get_eaddr_mem, 676138cc658fSJohn Baldwin bge_get_eaddr_nvram, 676238cc658fSJohn Baldwin bge_get_eaddr_eeprom, 676338cc658fSJohn Baldwin NULL 676438cc658fSJohn Baldwin }; 676538cc658fSJohn Baldwin const bge_eaddr_fcn_t *func; 676638cc658fSJohn Baldwin 676738cc658fSJohn Baldwin for (func = bge_eaddr_funcs; *func != NULL; ++func) { 676838cc658fSJohn Baldwin if ((*func)(sc, eaddr) == 0) 676938cc658fSJohn Baldwin break; 677038cc658fSJohn Baldwin } 677138cc658fSJohn Baldwin return (*func == NULL ? ENXIO : 0); 677238cc658fSJohn Baldwin } 6773