1 /*- 2 * Copyright (c) 2003 Stuart Walsh 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 /* $FreeBSD$ */ 26 27 #ifndef _BFE_H 28 #define _BFE_H 29 30 /* PCI registers */ 31 #define BFE_PCI_MEMLO 0x10 32 #define BFE_PCI_MEMHIGH 0x14 33 #define BFE_PCI_INTLINE 0x3C 34 35 /* Register layout. */ 36 #define BFE_DEVCTRL 0x00000000 /* Device Control */ 37 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 38 #define BFE_IPP 0x00000400 /* Internal EPHY Present */ 39 #define BFE_EPR 0x00008000 /* EPHY Reset */ 40 #define BFE_PME 0x00001000 /* PHY Mode Enable */ 41 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 42 #define BFE_PADDR 0x0007c000 /* PHY Address */ 43 #define BFE_PADDR_SHIFT 18 44 45 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 46 #define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 47 48 #define BFE_ISTAT 0x00000020 /* Interrupt Status */ 49 #define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 50 #define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 51 #define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 52 #define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 53 #define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 54 #define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 55 #define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 56 #define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 57 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 58 #define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 59 #define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 60 #define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 61 #define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 62 #define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 63 BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 64 65 #define BFE_IMASK 0x00000024 /* Interrupt Mask */ 66 #define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 67 BFE_ISTAT_TX) 68 69 #define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 70 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 71 #define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 72 #define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 73 #define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 74 #define BFE_CTRL_LED_SHIFT 5 75 76 #define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 77 #define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 78 #define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 79 #define BFE_LAZY_FC_SHIFT 24 80 81 #define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 82 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 83 #define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 84 #define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 85 #define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 86 #define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 87 88 #define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 89 #define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 90 #define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 91 #define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 92 #define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 93 #define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 94 #define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 95 #define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 96 #define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 97 #define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 98 #define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 99 #define BFE_STAT_ENONE 0x00000000 /* Error None */ 100 #define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 101 #define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 102 #define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 103 #define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 104 #define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 105 106 #define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 107 #define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 108 #define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 109 #define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 110 111 #define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 112 #define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 113 #define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 114 115 #define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 116 #define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 117 #define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 118 #define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 119 #define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 120 #define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 121 #define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 122 #define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 123 #define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 124 125 #define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 126 #define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 127 128 #define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 129 #define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 130 #define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 131 132 #define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 133 #define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 134 #define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 135 #define BFE_MDIO_TA_SHIFT 16 136 #define BFE_MDIO_TA_VALID 2 137 138 #define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 139 #define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 140 #define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 141 #define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 142 #define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 143 #define BFE_MDIO_RA_SHIFT 18 144 #define BFE_MDIO_PMD_SHIFT 23 145 #define BFE_MDIO_OP_SHIFT 28 146 #define BFE_MDIO_OP_WRITE 1 147 #define BFE_MDIO_OP_READ 2 148 #define BFE_MDIO_SB_SHIFT 30 149 150 #define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 151 #define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 152 #define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 153 #define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 154 #define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 155 156 #define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 157 #define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 158 #define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 159 160 #define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 161 #define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 162 #define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 163 #define BFE_CAM_READ 0x00000004 /* Read */ 164 #define BFE_CAM_WRITE 0x00000008 /* Read */ 165 #define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 166 #define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 167 #define BFE_CAM_INDEX_SHIFT 16 168 169 #define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 170 #define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 171 #define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 172 #define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 173 #define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 174 175 #define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 176 #define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 177 #define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 178 #define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 179 #define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 180 181 #define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 182 183 #define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 184 #define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 185 186 /* Status registers */ 187 #define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 188 #define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 189 #define BFE_TX_O 0x00000508 /* MIB TX Octets */ 190 #define BFE_TX_P 0x0000050C /* MIB TX Packets */ 191 #define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 192 #define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 193 #define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 194 #define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 195 #define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 196 #define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 197 #define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 198 #define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 199 #define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 200 #define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 201 #define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 202 #define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 203 #define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 204 #define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 205 #define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 206 #define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 207 #define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 208 #define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 209 #define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 210 #define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 211 #define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 212 #define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 213 #define BFE_RX_O 0x00000588 /* MIB RX Octets */ 214 #define BFE_RX_P 0x0000058C /* MIB RX Packets */ 215 #define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 216 #define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 217 #define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 218 #define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 219 #define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 220 #define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 221 #define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 222 #define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 223 #define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 224 #define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 225 #define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 226 #define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 227 #define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 228 #define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 229 #define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 230 #define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 231 #define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 232 #define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 233 #define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 234 235 #define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 236 #define BFE_PC 0x0000000f /* Pipe Count */ 237 #define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 238 #define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 239 #define BFE_AP_TS 0x00000010 /* Use timeslices only */ 240 #define BFE_AP_TK 0x00000020 /* Use token only */ 241 #define BFE_AP_RSV 0x00000030 /* Reserved */ 242 #define BFE_IBE 0x00020000 /* In Band Error */ 243 #define BFE_TO 0x00040000 /* Timeout */ 244 245 246 /* Seems the bcm440x has a fairly generic core, we only need be concerned with 247 * a couple of these 248 */ 249 #define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 250 #define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 251 #define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 252 #define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 253 #define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 254 #define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 255 #define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 256 #define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 257 258 #define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 259 #define BFE_RESET 0x00000001 /* Reset */ 260 #define BFE_REJECT 0x00000002 /* Reject */ 261 #define BFE_CLOCK 0x00010000 /* Clock Enable */ 262 #define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 263 #define BFE_PE 0x40000000 /* Power Management Enable */ 264 #define BFE_BE 0x80000000 /* BIST Enable */ 265 266 #define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 267 #define BFE_SERR 0x00000001 /* S-error */ 268 #define BFE_INT 0x00000002 /* Interrupt */ 269 #define BFE_BUSY 0x00000004 /* Busy */ 270 #define BFE_GCR 0x20000000 /* Gated Clock Request */ 271 #define BFE_BISTF 0x40000000 /* BIST Failed */ 272 #define BFE_BISTD 0x80000000 /* BIST Done */ 273 274 #define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 275 #define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 276 #define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 277 #define BFE_TAB0_SHIFT 0 278 #define BFE_TAB1_SHIFT 16 279 280 #define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 281 #define BFE_STO_MASK 0x00000003 /* Service Timeout */ 282 #define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 283 #define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 284 #define BFE_RTO_SHIFT 4 285 #define BFE_CID_SHIFT 16 286 287 #define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 288 #define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 289 #define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 290 #define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 291 #define BFE_TEM_SHIFT 4 292 #define BFE_BEM_SHIFT 6 293 294 #define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 295 #define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 296 #define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 297 #define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 298 #define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 299 #define BFE_LOW_CO_SHIFT 11 300 #define BFE_LOW_IF_SHIFT 18 301 #define BFE_LOW_IM_SHIFT 24 302 303 #define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 304 #define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 305 #define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 306 #define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 307 #define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 308 #define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 309 #define BFE_HIGH_RM_SHIFT 2 310 #define BFE_HIGH_SM_SHIFT 4 311 #define BFE_HIGH_EM_SHIFT 8 312 #define BFE_HIGH_IM_SHIFT 10 313 314 #define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 315 #define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 316 #define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 317 #define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 318 #define BFE_MAX0_SHIFT 16 319 #define BFE_MAX1_SHIFT 20 320 321 #define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 322 #define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 323 #define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 324 325 #define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 326 #define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 327 328 #define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 329 #define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 330 #define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 331 #define BFE_SYNCH 0x00000040 /* Sync */ 332 #define BFE_INIT 0x00000080 /* Initiator */ 333 #define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 334 #define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 335 #define BFE_FIRST 0x00010000 /* This Initiator is First */ 336 #define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 337 #define BFE_TP_MASK 0x00f00000 /* Target Ports */ 338 #define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 339 #define BFE_AR_SHIFT 3 340 #define BFE_MINLAT_SHIFT 8 341 #define BFE_MAXLAT_SHIFT 12 342 #define BFE_CW_SHIFT 18 343 #define BFE_TP_SHIFT 20 344 #define BFE_IP_SHIFT 24 345 346 #define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 347 #define BFE_RC_MASK 0x0000000f /* Revision Code */ 348 #define BFE_CC_MASK 0x0000fff0 /* Core Code */ 349 #define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 350 #define BFE_CC_SHIFT 4 351 #define BFE_VC_SHIFT 16 352 353 #define BFE_CORE_ILINE20 0x801 354 #define BFE_CORE_SDRAM 0x803 355 #define BFE_CORE_PCI 0x804 356 #define BFE_CORE_MIPS 0x805 357 #define BFE_CORE_ENET 0x806 358 #define BFE_CORE_CODEC 0x807 359 #define BFE_CORE_USB 0x808 360 #define BFE_CORE_ILINE100 0x80a 361 #define BFE_CORE_EXTIF 0x811 362 363 /* SSB PCI config space registers. */ 364 #define BFE_BAR0_WIN 0x80 365 #define BFE_BAR1_WIN 0x84 366 #define BFE_SPROM_CONTROL 0x88 367 #define BFE_BAR1_CONTROL 0x8c 368 369 /* SSB core and hsot control registers. */ 370 #define BFE_SSB_CONTROL 0x00000000 371 #define BFE_SSB_ARBCONTROL 0x00000010 372 #define BFE_SSB_ISTAT 0x00000020 373 #define BFE_SSB_IMASK 0x00000024 374 #define BFE_SSB_MBOX 0x00000028 375 #define BFE_SSB_BCAST_ADDR 0x00000050 376 #define BFE_SSB_BCAST_DATA 0x00000054 377 #define BFE_SSB_PCI_TRANS_0 0x00000100 378 #define BFE_SSB_PCI_TRANS_1 0x00000104 379 #define BFE_SSB_PCI_TRANS_2 0x00000108 380 #define BFE_SSB_SPROM 0x00000800 381 382 #define BFE_SSB_PCI_MEM 0x00000000 383 #define BFE_SSB_PCI_IO 0x00000001 384 #define BFE_SSB_PCI_CFG0 0x00000002 385 #define BFE_SSB_PCI_CFG1 0x00000003 386 #define BFE_SSB_PCI_PREF 0x00000004 387 #define BFE_SSB_PCI_BURST 0x00000008 388 #define BFE_SSB_PCI_MASK0 0xfc000000 389 #define BFE_SSB_PCI_MASK1 0xfc000000 390 #define BFE_SSB_PCI_MASK2 0xc0000000 391 392 #define BFE_DESC_LEN 0x00001fff 393 #define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 394 #define BFE_DESC_EOT 0x10000000 /* End of Table */ 395 #define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 396 #define BFE_DESC_EOF 0x40000000 /* End of Frame */ 397 #define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 398 399 #define BFE_RX_CP_THRESHOLD 256 400 #define BFE_RX_HEADER_LEN 28 401 402 #define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 403 #define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 404 #define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 405 #define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 406 #define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 407 #define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 408 #define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 409 #define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 410 #define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 411 #define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 412 BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 413 414 #define BFE_MCAST_TBL_SIZE 32 415 #define BFE_PCI_DMA 0x40000000 416 #define BFE_REG_PCI 0x18002000 417 418 #define BCOM_VENDORID 0x14E4 419 #define BCOM_DEVICEID_BCM4401 0x4401 420 #define BCOM_DEVICEID_BCM4401B0 0x170c 421 422 #define PCI_SETBIT(dev, reg, x, s) \ 423 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 424 #define PCI_CLRBIT(dev, reg, x, s) \ 425 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 426 427 #define BFE_RX_RING_SIZE 512 428 #define BFE_TX_RING_SIZE 512 429 #define BFE_LINK_DOWN 5 430 #define BFE_TX_LIST_CNT 511 431 #define BFE_RX_LIST_CNT 511 432 #define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 433 #define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 434 #define BFE_RX_OFFSET 30 435 #define BFE_TX_QLEN 256 436 437 #define CSR_READ_4(sc, reg) \ 438 bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg) 439 440 #define CSR_WRITE_4(sc, reg, val) \ 441 bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val) 442 443 #define BFE_OR(sc, name, val) \ 444 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 445 446 #define BFE_AND(sc, name, val) \ 447 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 448 449 #define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) 450 #define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) 451 #define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) 452 453 #define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 454 455 struct bfe_data { 456 struct mbuf *bfe_mbuf; 457 bus_dmamap_t bfe_map; 458 }; 459 460 struct bfe_desc { 461 u_int32_t bfe_ctrl; 462 u_int32_t bfe_addr; 463 }; 464 465 struct bfe_rxheader { 466 u_int16_t len; 467 u_int16_t flags; 468 u_int16_t pad[12]; 469 }; 470 471 struct bfe_hw_stats { 472 u_int32_t tx_good_octets, tx_good_pkts, tx_octets; 473 u_int32_t tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; 474 u_int32_t tx_len_64, tx_len_65_to_127, tx_len_128_to_255; 475 u_int32_t tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; 476 u_int32_t tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; 477 u_int32_t tx_underruns, tx_total_cols, tx_single_cols; 478 u_int32_t tx_multiple_cols, tx_excessive_cols, tx_late_cols; 479 u_int32_t tx_defered, tx_carrier_lost, tx_pause_pkts; 480 u_int32_t __pad1[8]; 481 482 u_int32_t rx_good_octets, rx_good_pkts, rx_octets; 483 u_int32_t rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; 484 u_int32_t rx_len_64, rx_len_65_to_127, rx_len_128_to_255; 485 u_int32_t rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; 486 u_int32_t rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; 487 u_int32_t rx_missed_pkts, rx_crc_align_errs, rx_undersize; 488 u_int32_t rx_crc_errs, rx_align_errs, rx_symbol_errs; 489 u_int32_t rx_pause_pkts, rx_nonpause_pkts; 490 }; 491 492 struct bfe_softc 493 { 494 struct ifnet *bfe_ifp; /* interface info */ 495 device_t bfe_dev; 496 device_t bfe_miibus; 497 bus_space_handle_t bfe_bhandle; 498 vm_offset_t bfe_vhandle; 499 bus_space_tag_t bfe_btag; 500 bus_dma_tag_t bfe_tag; 501 bus_dma_tag_t bfe_parent_tag; 502 bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 503 bus_dmamap_t bfe_tx_map, bfe_rx_map; 504 void *bfe_intrhand; 505 struct resource *bfe_irq; 506 struct resource *bfe_res; 507 struct callout_handle bfe_stat_ch; 508 struct bfe_hw_stats bfe_hwstats; 509 struct bfe_desc *bfe_tx_list, *bfe_rx_list; 510 struct bfe_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 511 struct bfe_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 512 struct mtx bfe_mtx; 513 u_int32_t bfe_flags; 514 u_int32_t bfe_imask; 515 u_int32_t bfe_dma_offset; 516 u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 517 u_int32_t bfe_rx_cnt, bfe_rx_prod, bfe_rx_cons; 518 u_int32_t bfe_tx_dma, bfe_rx_dma; 519 u_int32_t bfe_link; 520 u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 521 u_int8_t bfe_mdc_port; 522 u_int8_t bfe_unit; /* interface number */ 523 u_int8_t bfe_core_unit; 524 u_int8_t bfe_up; 525 u_char bfe_enaddr[6]; 526 int bfe_if_flags; 527 char *bfe_vpd_prodname; 528 char *bfe_vpd_readonly; 529 }; 530 531 struct bfe_type 532 { 533 u_int16_t bfe_vid; 534 u_int16_t bfe_did; 535 char *bfe_name; 536 }; 537 538 #endif /* _BFE_H */ 539