1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 354 355 /* Allocate interrupt */ 356 rid = 0; 357 358 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 359 RF_SHAREABLE | RF_ACTIVE); 360 if (sc->bfe_irq == NULL) { 361 printf("bfe%d: couldn't map interrupt\n", unit); 362 error = ENXIO; 363 goto fail; 364 } 365 366 if (bfe_dma_alloc(dev)) { 367 printf("bfe%d: failed to allocate DMA resources\n", 368 sc->bfe_unit); 369 bfe_release_resources(sc); 370 error = ENXIO; 371 goto fail; 372 } 373 374 /* Set up ifnet structure */ 375 ifp = &sc->arpcom.ac_if; 376 ifp->if_softc = sc; 377 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 379 ifp->if_ioctl = bfe_ioctl; 380 ifp->if_start = bfe_start; 381 ifp->if_watchdog = bfe_watchdog; 382 ifp->if_init = bfe_init; 383 ifp->if_mtu = ETHERMTU; 384 ifp->if_baudrate = 100000000; 385 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 386 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 387 IFQ_SET_READY(&ifp->if_snd); 388 389 bfe_get_config(sc); 390 391 /* Reset the chip and turn on the PHY */ 392 BFE_LOCK(sc); 393 bfe_chip_reset(sc); 394 BFE_UNLOCK(sc); 395 396 if (mii_phy_probe(dev, &sc->bfe_miibus, 397 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 398 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 399 error = ENXIO; 400 goto fail; 401 } 402 403 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 404 callout_handle_init(&sc->bfe_stat_ch); 405 406 /* 407 * Tell the upper layer(s) we support long frames. 408 */ 409 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 410 ifp->if_capabilities |= IFCAP_VLAN_MTU; 411 ifp->if_capenable |= IFCAP_VLAN_MTU; 412 413 /* 414 * Hook interrupt last to avoid having to lock softc 415 */ 416 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 417 bfe_intr, sc, &sc->bfe_intrhand); 418 419 if (error) { 420 bfe_release_resources(sc); 421 printf("bfe%d: couldn't set up irq\n", unit); 422 goto fail; 423 } 424 fail: 425 if(error) 426 bfe_release_resources(sc); 427 return (error); 428 } 429 430 static int 431 bfe_detach(device_t dev) 432 { 433 struct bfe_softc *sc; 434 struct ifnet *ifp; 435 436 sc = device_get_softc(dev); 437 438 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 439 BFE_LOCK(sc); 440 441 ifp = &sc->arpcom.ac_if; 442 443 if (device_is_attached(dev)) { 444 bfe_stop(sc); 445 ether_ifdetach(ifp); 446 } 447 448 bfe_chip_reset(sc); 449 450 bus_generic_detach(dev); 451 if(sc->bfe_miibus != NULL) 452 device_delete_child(dev, sc->bfe_miibus); 453 454 bfe_release_resources(sc); 455 BFE_UNLOCK(sc); 456 mtx_destroy(&sc->bfe_mtx); 457 458 return (0); 459 } 460 461 /* 462 * Stop all chip I/O so that the kernel's probe routines don't 463 * get confused by errant DMAs when rebooting. 464 */ 465 static void 466 bfe_shutdown(device_t dev) 467 { 468 struct bfe_softc *sc; 469 470 sc = device_get_softc(dev); 471 BFE_LOCK(sc); 472 bfe_stop(sc); 473 474 BFE_UNLOCK(sc); 475 return; 476 } 477 478 static int 479 bfe_miibus_readreg(device_t dev, int phy, int reg) 480 { 481 struct bfe_softc *sc; 482 u_int32_t ret; 483 484 sc = device_get_softc(dev); 485 if(phy != sc->bfe_phyaddr) 486 return (0); 487 bfe_readphy(sc, reg, &ret); 488 489 return (ret); 490 } 491 492 static int 493 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 494 { 495 struct bfe_softc *sc; 496 497 sc = device_get_softc(dev); 498 if(phy != sc->bfe_phyaddr) 499 return (0); 500 bfe_writephy(sc, reg, val); 501 502 return (0); 503 } 504 505 static void 506 bfe_miibus_statchg(device_t dev) 507 { 508 return; 509 } 510 511 static void 512 bfe_tx_ring_free(struct bfe_softc *sc) 513 { 514 int i; 515 516 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 517 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 518 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 519 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 520 bus_dmamap_unload(sc->bfe_tag, 521 sc->bfe_tx_ring[i].bfe_map); 522 } 523 } 524 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 525 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 526 } 527 528 static void 529 bfe_rx_ring_free(struct bfe_softc *sc) 530 { 531 int i; 532 533 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 534 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 535 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 536 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 537 bus_dmamap_unload(sc->bfe_tag, 538 sc->bfe_rx_ring[i].bfe_map); 539 } 540 } 541 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 542 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 543 } 544 545 static int 546 bfe_list_rx_init(struct bfe_softc *sc) 547 { 548 int i; 549 550 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 551 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 552 return (ENOBUFS); 553 } 554 555 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 556 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 557 558 sc->bfe_rx_cons = 0; 559 560 return (0); 561 } 562 563 static int 564 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 565 { 566 struct bfe_rxheader *rx_header; 567 struct bfe_desc *d; 568 struct bfe_data *r; 569 u_int32_t ctrl; 570 571 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 572 return (EINVAL); 573 574 if(m == NULL) { 575 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 576 if(m == NULL) 577 return (ENOBUFS); 578 m->m_len = m->m_pkthdr.len = MCLBYTES; 579 } 580 else 581 m->m_data = m->m_ext.ext_buf; 582 583 rx_header = mtod(m, struct bfe_rxheader *); 584 rx_header->len = 0; 585 rx_header->flags = 0; 586 587 /* Map the mbuf into DMA */ 588 sc->bfe_rx_cnt = c; 589 d = &sc->bfe_rx_list[c]; 590 r = &sc->bfe_rx_ring[c]; 591 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 592 MCLBYTES, bfe_dma_map_desc, d, 0); 593 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 594 595 ctrl = ETHER_MAX_LEN + 32; 596 597 if(c == BFE_RX_LIST_CNT - 1) 598 ctrl |= BFE_DESC_EOT; 599 600 d->bfe_ctrl = ctrl; 601 r->bfe_mbuf = m; 602 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 603 return (0); 604 } 605 606 static void 607 bfe_get_config(struct bfe_softc *sc) 608 { 609 u_int8_t eeprom[128]; 610 611 bfe_read_eeprom(sc, eeprom); 612 613 sc->arpcom.ac_enaddr[0] = eeprom[79]; 614 sc->arpcom.ac_enaddr[1] = eeprom[78]; 615 sc->arpcom.ac_enaddr[2] = eeprom[81]; 616 sc->arpcom.ac_enaddr[3] = eeprom[80]; 617 sc->arpcom.ac_enaddr[4] = eeprom[83]; 618 sc->arpcom.ac_enaddr[5] = eeprom[82]; 619 620 sc->bfe_phyaddr = eeprom[90] & 0x1f; 621 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 622 623 sc->bfe_core_unit = 0; 624 sc->bfe_dma_offset = BFE_PCI_DMA; 625 } 626 627 static void 628 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 629 { 630 u_int32_t bar_orig, pci_rev, val; 631 632 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 633 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 634 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 635 636 val = CSR_READ_4(sc, BFE_SBINTVEC); 637 val |= cores; 638 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 639 640 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 641 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 642 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 643 644 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 645 } 646 647 static void 648 bfe_clear_stats(struct bfe_softc *sc) 649 { 650 u_long reg; 651 652 BFE_LOCK_ASSERT(sc); 653 654 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 655 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 656 CSR_READ_4(sc, reg); 657 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 658 CSR_READ_4(sc, reg); 659 } 660 661 static int 662 bfe_resetphy(struct bfe_softc *sc) 663 { 664 u_int32_t val; 665 666 bfe_writephy(sc, 0, BMCR_RESET); 667 DELAY(100); 668 bfe_readphy(sc, 0, &val); 669 if (val & BMCR_RESET) { 670 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 671 return (ENXIO); 672 } 673 return (0); 674 } 675 676 static void 677 bfe_chip_halt(struct bfe_softc *sc) 678 { 679 BFE_LOCK_ASSERT(sc); 680 /* disable interrupts - not that it actually does..*/ 681 CSR_WRITE_4(sc, BFE_IMASK, 0); 682 CSR_READ_4(sc, BFE_IMASK); 683 684 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 685 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 686 687 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 688 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 689 DELAY(10); 690 } 691 692 static void 693 bfe_chip_reset(struct bfe_softc *sc) 694 { 695 u_int32_t val; 696 697 BFE_LOCK_ASSERT(sc); 698 699 /* Set the interrupt vector for the enet core */ 700 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 701 702 /* is core up? */ 703 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 704 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 705 if (val == BFE_CLOCK) { 706 /* It is, so shut it down */ 707 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 708 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 709 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 712 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 713 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 714 100, 0); 715 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 716 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 717 } 718 719 bfe_core_reset(sc); 720 bfe_clear_stats(sc); 721 722 /* 723 * We want the phy registers to be accessible even when 724 * the driver is "downed" so initialize MDC preamble, frequency, 725 * and whether internal or external phy here. 726 */ 727 728 /* 4402 has 62.5Mhz SB clock and internal phy */ 729 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 730 731 /* Internal or external PHY? */ 732 val = CSR_READ_4(sc, BFE_DEVCTRL); 733 if(!(val & BFE_IPP)) 734 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 735 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 736 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 737 DELAY(100); 738 } 739 740 /* Enable CRC32 generation and set proper LED modes */ 741 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 742 743 /* Reset or clear powerdown control bit */ 744 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 745 746 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 747 BFE_LAZY_FC_MASK)); 748 749 /* 750 * We don't want lazy interrupts, so just send them at 751 * the end of a frame, please 752 */ 753 BFE_OR(sc, BFE_RCV_LAZY, 0); 754 755 /* Set max lengths, accounting for VLAN tags */ 756 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 757 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 758 759 /* Set watermark XXX - magic */ 760 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 761 762 /* 763 * Initialise DMA channels 764 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 765 */ 766 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 767 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 768 769 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 770 BFE_RX_CTRL_ENABLE); 771 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 772 773 bfe_resetphy(sc); 774 bfe_setupphy(sc); 775 } 776 777 static void 778 bfe_core_disable(struct bfe_softc *sc) 779 { 780 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 781 return; 782 783 /* 784 * Set reject, wait for it set, then wait for the core to stop 785 * being busy, then set reset and reject and enable the clocks. 786 */ 787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 788 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 789 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 790 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 791 BFE_RESET)); 792 CSR_READ_4(sc, BFE_SBTMSLOW); 793 DELAY(10); 794 /* Leave reset and reject set */ 795 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 796 DELAY(10); 797 } 798 799 static void 800 bfe_core_reset(struct bfe_softc *sc) 801 { 802 u_int32_t val; 803 804 /* Disable the core */ 805 bfe_core_disable(sc); 806 807 /* and bring it back up */ 808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 809 CSR_READ_4(sc, BFE_SBTMSLOW); 810 DELAY(10); 811 812 /* Chip bug, clear SERR, IB and TO if they are set. */ 813 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 814 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 815 val = CSR_READ_4(sc, BFE_SBIMSTATE); 816 if (val & (BFE_IBE | BFE_TO)) 817 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 818 819 /* Clear reset and allow it to move through the core */ 820 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 821 CSR_READ_4(sc, BFE_SBTMSLOW); 822 DELAY(10); 823 824 /* Leave the clock set */ 825 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 826 CSR_READ_4(sc, BFE_SBTMSLOW); 827 DELAY(10); 828 } 829 830 static void 831 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 832 { 833 u_int32_t val; 834 835 val = ((u_int32_t) data[2]) << 24; 836 val |= ((u_int32_t) data[3]) << 16; 837 val |= ((u_int32_t) data[4]) << 8; 838 val |= ((u_int32_t) data[5]); 839 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 840 val = (BFE_CAM_HI_VALID | 841 (((u_int32_t) data[0]) << 8) | 842 (((u_int32_t) data[1]))); 843 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 844 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 845 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 846 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 847 } 848 849 static void 850 bfe_set_rx_mode(struct bfe_softc *sc) 851 { 852 struct ifnet *ifp = &sc->arpcom.ac_if; 853 struct ifmultiaddr *ifma; 854 u_int32_t val; 855 int i = 0; 856 857 val = CSR_READ_4(sc, BFE_RXCONF); 858 859 if (ifp->if_flags & IFF_PROMISC) 860 val |= BFE_RXCONF_PROMISC; 861 else 862 val &= ~BFE_RXCONF_PROMISC; 863 864 if (ifp->if_flags & IFF_BROADCAST) 865 val &= ~BFE_RXCONF_DBCAST; 866 else 867 val |= BFE_RXCONF_DBCAST; 868 869 870 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 871 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 872 873 if (ifp->if_flags & IFF_ALLMULTI) 874 val |= BFE_RXCONF_ALLMULTI; 875 else { 876 val &= ~BFE_RXCONF_ALLMULTI; 877 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 878 if (ifma->ifma_addr->sa_family != AF_LINK) 879 continue; 880 bfe_cam_write(sc, 881 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 882 } 883 } 884 885 CSR_WRITE_4(sc, BFE_RXCONF, val); 886 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 887 } 888 889 static void 890 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 891 { 892 u_int32_t *ptr; 893 894 ptr = arg; 895 *ptr = segs->ds_addr; 896 } 897 898 static void 899 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 900 { 901 struct bfe_desc *d; 902 903 d = arg; 904 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 905 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 906 } 907 908 static void 909 bfe_release_resources(struct bfe_softc *sc) 910 { 911 device_t dev; 912 int i; 913 914 dev = sc->bfe_dev; 915 916 if (sc->bfe_vpd_prodname != NULL) 917 free(sc->bfe_vpd_prodname, M_DEVBUF); 918 919 if (sc->bfe_vpd_readonly != NULL) 920 free(sc->bfe_vpd_readonly, M_DEVBUF); 921 922 if (sc->bfe_intrhand != NULL) 923 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 924 925 if (sc->bfe_irq != NULL) 926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 927 928 if (sc->bfe_res != NULL) 929 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 930 931 if(sc->bfe_tx_tag != NULL) { 932 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 933 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 934 sc->bfe_tx_map); 935 bus_dma_tag_destroy(sc->bfe_tx_tag); 936 sc->bfe_tx_tag = NULL; 937 } 938 939 if(sc->bfe_rx_tag != NULL) { 940 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 941 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 942 sc->bfe_rx_map); 943 bus_dma_tag_destroy(sc->bfe_rx_tag); 944 sc->bfe_rx_tag = NULL; 945 } 946 947 if(sc->bfe_tag != NULL) { 948 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 949 bus_dmamap_destroy(sc->bfe_tag, 950 sc->bfe_tx_ring[i].bfe_map); 951 } 952 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 953 bus_dmamap_destroy(sc->bfe_tag, 954 sc->bfe_rx_ring[i].bfe_map); 955 } 956 bus_dma_tag_destroy(sc->bfe_tag); 957 sc->bfe_tag = NULL; 958 } 959 960 if(sc->bfe_parent_tag != NULL) 961 bus_dma_tag_destroy(sc->bfe_parent_tag); 962 963 return; 964 } 965 966 static void 967 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 968 { 969 long i; 970 u_int16_t *ptr = (u_int16_t *)data; 971 972 for(i = 0; i < 128; i += 2) 973 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 974 } 975 976 static int 977 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 978 u_long timeout, const int clear) 979 { 980 u_long i; 981 982 for (i = 0; i < timeout; i++) { 983 u_int32_t val = CSR_READ_4(sc, reg); 984 985 if (clear && !(val & bit)) 986 break; 987 if (!clear && (val & bit)) 988 break; 989 DELAY(10); 990 } 991 if (i == timeout) { 992 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 993 "%x to %s.\n", sc->bfe_unit, bit, reg, 994 (clear ? "clear" : "set")); 995 return (-1); 996 } 997 return (0); 998 } 999 1000 static int 1001 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1002 { 1003 int err; 1004 1005 /* Clear MII ISR */ 1006 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1007 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1008 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1009 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1010 (reg << BFE_MDIO_RA_SHIFT) | 1011 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1012 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1013 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1014 1015 return (err); 1016 } 1017 1018 static int 1019 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1020 { 1021 int status; 1022 1023 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1024 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1025 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1026 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1027 (reg << BFE_MDIO_RA_SHIFT) | 1028 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1029 (val & BFE_MDIO_DATA_DATA))); 1030 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1031 1032 return (status); 1033 } 1034 1035 /* 1036 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1037 * twice 1038 */ 1039 static int 1040 bfe_setupphy(struct bfe_softc *sc) 1041 { 1042 u_int32_t val; 1043 1044 /* Enable activity LED */ 1045 bfe_readphy(sc, 26, &val); 1046 bfe_writephy(sc, 26, val & 0x7fff); 1047 bfe_readphy(sc, 26, &val); 1048 1049 /* Enable traffic meter LED mode */ 1050 bfe_readphy(sc, 27, &val); 1051 bfe_writephy(sc, 27, val | (1 << 6)); 1052 1053 return (0); 1054 } 1055 1056 static void 1057 bfe_stats_update(struct bfe_softc *sc) 1058 { 1059 u_long reg; 1060 u_int32_t *val; 1061 1062 val = &sc->bfe_hwstats.tx_good_octets; 1063 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1064 *val++ += CSR_READ_4(sc, reg); 1065 } 1066 val = &sc->bfe_hwstats.rx_good_octets; 1067 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1068 *val++ += CSR_READ_4(sc, reg); 1069 } 1070 } 1071 1072 static void 1073 bfe_txeof(struct bfe_softc *sc) 1074 { 1075 struct ifnet *ifp; 1076 int i, chipidx; 1077 1078 BFE_LOCK_ASSERT(sc); 1079 1080 ifp = &sc->arpcom.ac_if; 1081 1082 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1083 chipidx /= sizeof(struct bfe_desc); 1084 1085 i = sc->bfe_tx_cons; 1086 /* Go through the mbufs and free those that have been transmitted */ 1087 while(i != chipidx) { 1088 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1089 if(r->bfe_mbuf != NULL) { 1090 ifp->if_opackets++; 1091 m_freem(r->bfe_mbuf); 1092 r->bfe_mbuf = NULL; 1093 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1094 } 1095 sc->bfe_tx_cnt--; 1096 BFE_INC(i, BFE_TX_LIST_CNT); 1097 } 1098 1099 if(i != sc->bfe_tx_cons) { 1100 /* we freed up some mbufs */ 1101 sc->bfe_tx_cons = i; 1102 ifp->if_flags &= ~IFF_OACTIVE; 1103 } 1104 if(sc->bfe_tx_cnt == 0) 1105 ifp->if_timer = 0; 1106 else 1107 ifp->if_timer = 5; 1108 } 1109 1110 /* Pass a received packet up the stack */ 1111 static void 1112 bfe_rxeof(struct bfe_softc *sc) 1113 { 1114 struct mbuf *m; 1115 struct ifnet *ifp; 1116 struct bfe_rxheader *rxheader; 1117 struct bfe_data *r; 1118 int cons; 1119 u_int32_t status, current, len, flags; 1120 1121 BFE_LOCK_ASSERT(sc); 1122 cons = sc->bfe_rx_cons; 1123 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1124 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1125 1126 ifp = &sc->arpcom.ac_if; 1127 1128 while(current != cons) { 1129 r = &sc->bfe_rx_ring[cons]; 1130 m = r->bfe_mbuf; 1131 rxheader = mtod(m, struct bfe_rxheader*); 1132 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1133 len = rxheader->len; 1134 r->bfe_mbuf = NULL; 1135 1136 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1137 flags = rxheader->flags; 1138 1139 len -= ETHER_CRC_LEN; 1140 1141 /* flag an error and try again */ 1142 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1143 ifp->if_ierrors++; 1144 if (flags & BFE_RX_FLAG_SERR) 1145 ifp->if_collisions++; 1146 bfe_list_newbuf(sc, cons, m); 1147 BFE_INC(cons, BFE_RX_LIST_CNT); 1148 continue; 1149 } 1150 1151 /* Go past the rx header */ 1152 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1153 m_adj(m, BFE_RX_OFFSET); 1154 m->m_len = m->m_pkthdr.len = len; 1155 } else { 1156 bfe_list_newbuf(sc, cons, m); 1157 ifp->if_ierrors++; 1158 BFE_INC(cons, BFE_RX_LIST_CNT); 1159 continue; 1160 } 1161 1162 ifp->if_ipackets++; 1163 m->m_pkthdr.rcvif = ifp; 1164 BFE_UNLOCK(sc); 1165 (*ifp->if_input)(ifp, m); 1166 BFE_LOCK(sc); 1167 1168 BFE_INC(cons, BFE_RX_LIST_CNT); 1169 } 1170 sc->bfe_rx_cons = cons; 1171 } 1172 1173 static void 1174 bfe_intr(void *xsc) 1175 { 1176 struct bfe_softc *sc = xsc; 1177 struct ifnet *ifp; 1178 u_int32_t istat, imask, flag; 1179 1180 ifp = &sc->arpcom.ac_if; 1181 1182 BFE_LOCK(sc); 1183 1184 istat = CSR_READ_4(sc, BFE_ISTAT); 1185 imask = CSR_READ_4(sc, BFE_IMASK); 1186 1187 /* 1188 * Defer unsolicited interrupts - This is necessary because setting the 1189 * chips interrupt mask register to 0 doesn't actually stop the 1190 * interrupts 1191 */ 1192 istat &= imask; 1193 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1194 CSR_READ_4(sc, BFE_ISTAT); 1195 1196 /* not expecting this interrupt, disregard it */ 1197 if(istat == 0) { 1198 BFE_UNLOCK(sc); 1199 return; 1200 } 1201 1202 if(istat & BFE_ISTAT_ERRORS) { 1203 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1204 if(flag & BFE_STAT_EMASK) 1205 ifp->if_oerrors++; 1206 1207 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1208 if(flag & BFE_RX_FLAG_ERRORS) 1209 ifp->if_ierrors++; 1210 1211 ifp->if_flags &= ~IFF_RUNNING; 1212 bfe_init_locked(sc); 1213 } 1214 1215 /* A packet was received */ 1216 if(istat & BFE_ISTAT_RX) 1217 bfe_rxeof(sc); 1218 1219 /* A packet was sent */ 1220 if(istat & BFE_ISTAT_TX) 1221 bfe_txeof(sc); 1222 1223 /* We have packets pending, fire them out */ 1224 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1225 bfe_start_locked(ifp); 1226 1227 BFE_UNLOCK(sc); 1228 } 1229 1230 static int 1231 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1232 { 1233 struct bfe_desc *d = NULL; 1234 struct bfe_data *r = NULL; 1235 struct mbuf *m; 1236 u_int32_t frag, cur, cnt = 0; 1237 int chainlen = 0; 1238 1239 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1240 return (ENOBUFS); 1241 1242 /* 1243 * Count the number of frags in this chain to see if 1244 * we need to m_defrag. Since the descriptor list is shared 1245 * by all packets, we'll m_defrag long chains so that they 1246 * do not use up the entire list, even if they would fit. 1247 */ 1248 for(m = m_head; m != NULL; m = m->m_next) 1249 chainlen++; 1250 1251 1252 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1253 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1254 m = m_defrag(m_head, M_DONTWAIT); 1255 if (m == NULL) 1256 return (ENOBUFS); 1257 m_head = m; 1258 } 1259 1260 /* 1261 * Start packing the mbufs in this chain into 1262 * the fragment pointers. Stop when we run out 1263 * of fragments or hit the end of the mbuf chain. 1264 */ 1265 m = m_head; 1266 cur = frag = *txidx; 1267 cnt = 0; 1268 1269 for(m = m_head; m != NULL; m = m->m_next) { 1270 if(m->m_len != 0) { 1271 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1272 return (ENOBUFS); 1273 1274 d = &sc->bfe_tx_list[cur]; 1275 r = &sc->bfe_tx_ring[cur]; 1276 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1277 /* always intterupt on completion */ 1278 d->bfe_ctrl |= BFE_DESC_IOC; 1279 if(cnt == 0) 1280 /* Set start of frame */ 1281 d->bfe_ctrl |= BFE_DESC_SOF; 1282 if(cur == BFE_TX_LIST_CNT - 1) 1283 /* 1284 * Tell the chip to wrap to the start of 1285 * the descriptor list 1286 */ 1287 d->bfe_ctrl |= BFE_DESC_EOT; 1288 1289 bus_dmamap_load(sc->bfe_tag, 1290 r->bfe_map, mtod(m, void*), m->m_len, 1291 bfe_dma_map_desc, d, 0); 1292 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1293 BUS_DMASYNC_PREREAD); 1294 1295 frag = cur; 1296 BFE_INC(cur, BFE_TX_LIST_CNT); 1297 cnt++; 1298 } 1299 } 1300 1301 if (m != NULL) 1302 return (ENOBUFS); 1303 1304 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1305 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1306 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1307 1308 *txidx = cur; 1309 sc->bfe_tx_cnt += cnt; 1310 return (0); 1311 } 1312 1313 /* 1314 * Set up to transmit a packet. 1315 */ 1316 static void 1317 bfe_start(struct ifnet *ifp) 1318 { 1319 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1320 bfe_start_locked(ifp); 1321 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1322 } 1323 1324 /* 1325 * Set up to transmit a packet. The softc is already locked. 1326 */ 1327 static void 1328 bfe_start_locked(struct ifnet *ifp) 1329 { 1330 struct bfe_softc *sc; 1331 struct mbuf *m_head = NULL; 1332 int idx, queued = 0; 1333 1334 sc = ifp->if_softc; 1335 idx = sc->bfe_tx_prod; 1336 1337 BFE_LOCK_ASSERT(sc); 1338 1339 /* 1340 * Not much point trying to send if the link is down 1341 * or we have nothing to send. 1342 */ 1343 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1344 return; 1345 1346 if (ifp->if_flags & IFF_OACTIVE) 1347 return; 1348 1349 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1350 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1351 if(m_head == NULL) 1352 break; 1353 1354 /* 1355 * Pack the data into the tx ring. If we dont have 1356 * enough room, let the chip drain the ring. 1357 */ 1358 if(bfe_encap(sc, m_head, &idx)) { 1359 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1360 ifp->if_flags |= IFF_OACTIVE; 1361 break; 1362 } 1363 1364 queued++; 1365 1366 /* 1367 * If there's a BPF listener, bounce a copy of this frame 1368 * to him. 1369 */ 1370 BPF_MTAP(ifp, m_head); 1371 } 1372 1373 if (queued) { 1374 sc->bfe_tx_prod = idx; 1375 /* Transmit - twice due to apparent hardware bug */ 1376 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1377 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1378 1379 /* 1380 * Set a timeout in case the chip goes out to lunch. 1381 */ 1382 ifp->if_timer = 5; 1383 } 1384 } 1385 1386 static void 1387 bfe_init(void *xsc) 1388 { 1389 BFE_LOCK((struct bfe_softc *)xsc); 1390 bfe_init_locked(xsc); 1391 BFE_UNLOCK((struct bfe_softc *)xsc); 1392 } 1393 1394 static void 1395 bfe_init_locked(void *xsc) 1396 { 1397 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1398 struct ifnet *ifp = &sc->arpcom.ac_if; 1399 1400 BFE_LOCK_ASSERT(sc); 1401 1402 if (ifp->if_flags & IFF_RUNNING) 1403 return; 1404 1405 bfe_stop(sc); 1406 bfe_chip_reset(sc); 1407 1408 if (bfe_list_rx_init(sc) == ENOBUFS) { 1409 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1410 sc->bfe_unit); 1411 bfe_stop(sc); 1412 return; 1413 } 1414 1415 bfe_set_rx_mode(sc); 1416 1417 /* Enable the chip and core */ 1418 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1419 /* Enable interrupts */ 1420 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1421 1422 bfe_ifmedia_upd(ifp); 1423 ifp->if_flags |= IFF_RUNNING; 1424 ifp->if_flags &= ~IFF_OACTIVE; 1425 1426 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1427 } 1428 1429 /* 1430 * Set media options. 1431 */ 1432 static int 1433 bfe_ifmedia_upd(struct ifnet *ifp) 1434 { 1435 struct bfe_softc *sc; 1436 struct mii_data *mii; 1437 1438 sc = ifp->if_softc; 1439 1440 mii = device_get_softc(sc->bfe_miibus); 1441 sc->bfe_link = 0; 1442 if (mii->mii_instance) { 1443 struct mii_softc *miisc; 1444 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1445 miisc = LIST_NEXT(miisc, mii_list)) 1446 mii_phy_reset(miisc); 1447 } 1448 mii_mediachg(mii); 1449 1450 return (0); 1451 } 1452 1453 /* 1454 * Report current media status. 1455 */ 1456 static void 1457 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1458 { 1459 struct bfe_softc *sc = ifp->if_softc; 1460 struct mii_data *mii; 1461 1462 mii = device_get_softc(sc->bfe_miibus); 1463 mii_pollstat(mii); 1464 ifmr->ifm_active = mii->mii_media_active; 1465 ifmr->ifm_status = mii->mii_media_status; 1466 } 1467 1468 static int 1469 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1470 { 1471 struct bfe_softc *sc = ifp->if_softc; 1472 struct ifreq *ifr = (struct ifreq *) data; 1473 struct mii_data *mii; 1474 int error = 0; 1475 1476 switch(command) { 1477 case SIOCSIFFLAGS: 1478 BFE_LOCK(sc); 1479 if(ifp->if_flags & IFF_UP) 1480 if(ifp->if_flags & IFF_RUNNING) 1481 bfe_set_rx_mode(sc); 1482 else 1483 bfe_init_locked(sc); 1484 else if(ifp->if_flags & IFF_RUNNING) 1485 bfe_stop(sc); 1486 BFE_UNLOCK(sc); 1487 break; 1488 case SIOCADDMULTI: 1489 case SIOCDELMULTI: 1490 BFE_LOCK(sc); 1491 if(ifp->if_flags & IFF_RUNNING) 1492 bfe_set_rx_mode(sc); 1493 BFE_UNLOCK(sc); 1494 break; 1495 case SIOCGIFMEDIA: 1496 case SIOCSIFMEDIA: 1497 mii = device_get_softc(sc->bfe_miibus); 1498 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1499 command); 1500 break; 1501 default: 1502 error = ether_ioctl(ifp, command, data); 1503 break; 1504 } 1505 1506 return (error); 1507 } 1508 1509 static void 1510 bfe_watchdog(struct ifnet *ifp) 1511 { 1512 struct bfe_softc *sc; 1513 1514 sc = ifp->if_softc; 1515 1516 BFE_LOCK(sc); 1517 1518 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1519 1520 ifp->if_flags &= ~IFF_RUNNING; 1521 bfe_init_locked(sc); 1522 1523 ifp->if_oerrors++; 1524 1525 BFE_UNLOCK(sc); 1526 } 1527 1528 static void 1529 bfe_tick(void *xsc) 1530 { 1531 struct bfe_softc *sc = xsc; 1532 struct mii_data *mii; 1533 1534 if (sc == NULL) 1535 return; 1536 1537 BFE_LOCK(sc); 1538 1539 mii = device_get_softc(sc->bfe_miibus); 1540 1541 bfe_stats_update(sc); 1542 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1543 1544 if(sc->bfe_link) { 1545 BFE_UNLOCK(sc); 1546 return; 1547 } 1548 1549 mii_tick(mii); 1550 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1551 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1552 sc->bfe_link++; 1553 1554 BFE_UNLOCK(sc); 1555 } 1556 1557 /* 1558 * Stop the adapter and free any mbufs allocated to the 1559 * RX and TX lists. 1560 */ 1561 static void 1562 bfe_stop(struct bfe_softc *sc) 1563 { 1564 struct ifnet *ifp; 1565 1566 BFE_LOCK_ASSERT(sc); 1567 1568 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1569 1570 ifp = &sc->arpcom.ac_if; 1571 1572 bfe_chip_halt(sc); 1573 bfe_tx_ring_free(sc); 1574 bfe_rx_ring_free(sc); 1575 1576 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1577 } 1578