1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6 /* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #include <net/bpf.h> 49 50 #include <net/if_types.h> 51 #include <net/if_vlan_var.h> 52 53 #include <netinet/in_systm.h> 54 #include <netinet/in.h> 55 #include <netinet/ip.h> 56 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include "miidevs.h" 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <dev/bfe/if_bfereg.h> 72 73 MODULE_DEPEND(bfe, pci, 1, 1, 1); 74 MODULE_DEPEND(bfe, ether, 1, 1, 1); 75 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77 /* "controller miibus0" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82 static struct bfe_type bfe_devs[] = { 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95 static void bfe_init (void *); 96 static void bfe_stop (struct bfe_softc *); 97 static void bfe_watchdog (struct ifnet *); 98 static void bfe_shutdown (device_t); 99 static void bfe_tick (void *); 100 static void bfe_txeof (struct bfe_softc *); 101 static void bfe_rxeof (struct bfe_softc *); 102 static void bfe_set_rx_mode (struct bfe_softc *); 103 static int bfe_list_rx_init (struct bfe_softc *); 104 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105 static void bfe_rx_ring_free (struct bfe_softc *); 106 107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108 static int bfe_ifmedia_upd (struct ifnet *); 109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 static int bfe_miibus_readreg (device_t, int, int); 111 static int bfe_miibus_writereg (device_t, int, int, int); 112 static void bfe_miibus_statchg (device_t); 113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115 static void bfe_get_config (struct bfe_softc *sc); 116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117 static void bfe_stats_update (struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121 static int bfe_resetphy (struct bfe_softc *); 122 static int bfe_setupphy (struct bfe_softc *); 123 static void bfe_chip_reset (struct bfe_softc *); 124 static void bfe_chip_halt (struct bfe_softc *); 125 static void bfe_core_reset (struct bfe_softc *); 126 static void bfe_core_disable (struct bfe_softc *); 127 static int bfe_dma_alloc (device_t); 128 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149 }; 150 151 static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155 }; 156 157 static devclass_t bfe_devclass; 158 159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162 /* 163 * Probe for a Broadcom 4401 chip. 164 */ 165 static int 166 bfe_probe(device_t dev) 167 { 168 struct bfe_type *t; 169 struct bfe_softc *sc; 170 171 t = bfe_devs; 172 173 sc = device_get_softc(dev); 174 bzero(sc, sizeof(struct bfe_softc)); 175 sc->bfe_unit = device_get_unit(dev); 176 sc->bfe_dev = dev; 177 178 while(t->bfe_name != NULL) { 179 if ((pci_get_vendor(dev) == t->bfe_vid) && 180 (pci_get_device(dev) == t->bfe_did)) { 181 device_set_desc_copy(dev, t->bfe_name); 182 return(0); 183 } 184 t++; 185 } 186 187 return(ENXIO); 188 } 189 190 static int 191 bfe_dma_alloc(device_t dev) 192 { 193 struct bfe_softc *sc; 194 int error, i; 195 196 sc = device_get_softc(dev); 197 198 /* parent tag */ 199 error = bus_dma_tag_create(NULL, /* parent */ 200 PAGE_SIZE, 0, /* alignment, boundary */ 201 BUS_SPACE_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 MAXBSIZE, /* maxsize */ 205 BUS_SPACE_UNRESTRICTED, /* num of segments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207 BUS_DMA_ALLOCNOW, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 213 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 214 BUS_SPACE_MAXADDR, 215 BUS_SPACE_MAXADDR, 216 NULL, NULL, 217 BFE_TX_LIST_SIZE, 218 1, 219 BUS_SPACE_MAXSIZE_32BIT, 220 0, 221 NULL, NULL, 222 &sc->bfe_tx_tag); 223 224 if (error) { 225 device_printf(dev, "could not allocate dma tag\n"); 226 return(ENOMEM); 227 } 228 229 /* tag for RX ring */ 230 error = bus_dma_tag_create(sc->bfe_parent_tag, 231 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 232 BUS_SPACE_MAXADDR, 233 BUS_SPACE_MAXADDR, 234 NULL, NULL, 235 BFE_RX_LIST_SIZE, 236 1, 237 BUS_SPACE_MAXSIZE_32BIT, 238 0, 239 NULL, NULL, 240 &sc->bfe_rx_tag); 241 242 if (error) { 243 device_printf(dev, "could not allocate dma tag\n"); 244 return(ENOMEM); 245 } 246 247 /* tag for mbufs */ 248 error = bus_dma_tag_create(sc->bfe_parent_tag, 249 ETHER_ALIGN, 0, 250 BUS_SPACE_MAXADDR, 251 BUS_SPACE_MAXADDR, 252 NULL, NULL, 253 MCLBYTES, 254 1, 255 BUS_SPACE_MAXSIZE_32BIT, 256 0, 257 NULL, NULL, 258 &sc->bfe_tag); 259 260 if (error) { 261 device_printf(dev, "could not allocate dma tag\n"); 262 return(ENOMEM); 263 } 264 265 /* pre allocate dmamaps for RX list */ 266 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 267 error = bus_dmamap_create(sc->bfe_tag, 0, 268 &sc->bfe_rx_ring[i].bfe_map); 269 if (error) { 270 device_printf(dev, "cannot create DMA map for RX\n"); 271 return(ENOMEM); 272 } 273 } 274 275 /* pre allocate dmamaps for TX list */ 276 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 277 error = bus_dmamap_create(sc->bfe_tag, 0, 278 &sc->bfe_tx_ring[i].bfe_map); 279 if (error) { 280 device_printf(dev, "cannot create DMA map for TX\n"); 281 return(ENOMEM); 282 } 283 } 284 285 /* Alloc dma for rx ring */ 286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 287 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 288 289 if(error) 290 return(ENOMEM); 291 292 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 293 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 294 sc->bfe_rx_list, sizeof(struct bfe_desc), 295 bfe_dma_map, &sc->bfe_rx_dma, 0); 296 297 if(error) 298 return(ENOMEM); 299 300 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 301 302 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 303 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 304 if (error) 305 return(ENOMEM); 306 307 308 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 309 sc->bfe_tx_list, sizeof(struct bfe_desc), 310 bfe_dma_map, &sc->bfe_tx_dma, 0); 311 if(error) 312 return(ENOMEM); 313 314 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 316 317 return(0); 318 } 319 320 static int 321 bfe_attach(device_t dev) 322 { 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int unit, error = 0, rid; 326 327 sc = device_get_softc(dev); 328 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 329 MTX_DEF | MTX_RECURSE); 330 331 unit = device_get_unit(dev); 332 sc->bfe_dev = dev; 333 sc->bfe_unit = unit; 334 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 u_int32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 347 sc->bfe_unit, pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 printf ("bfe%d: couldn't map memory\n", unit); 366 error = ENXIO; 367 goto fail; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 373 374 /* Allocate interrupt */ 375 rid = 0; 376 377 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 378 RF_SHAREABLE | RF_ACTIVE); 379 if (sc->bfe_irq == NULL) { 380 printf("bfe%d: couldn't map interrupt\n", unit); 381 error = ENXIO; 382 goto fail; 383 } 384 385 if (bfe_dma_alloc(dev)) { 386 printf("bfe%d: failed to allocate DMA resources\n", 387 sc->bfe_unit); 388 bfe_release_resources(sc); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* Set up ifnet structure */ 394 ifp = &sc->arpcom.ac_if; 395 ifp->if_softc = sc; 396 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 398 ifp->if_ioctl = bfe_ioctl; 399 ifp->if_start = bfe_start; 400 ifp->if_watchdog = bfe_watchdog; 401 ifp->if_init = bfe_init; 402 ifp->if_mtu = ETHERMTU; 403 ifp->if_baudrate = 100000000; 404 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 405 406 bfe_get_config(sc); 407 408 /* Reset the chip and turn on the PHY */ 409 bfe_chip_reset(sc); 410 411 if (mii_phy_probe(dev, &sc->bfe_miibus, 412 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 413 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 414 error = ENXIO; 415 goto fail; 416 } 417 418 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 419 callout_handle_init(&sc->bfe_stat_ch); 420 421 /* 422 * Tell the upper layer(s) we support long frames. 423 */ 424 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 425 ifp->if_capabilities |= IFCAP_VLAN_MTU; 426 ifp->if_capenable |= IFCAP_VLAN_MTU; 427 428 /* 429 * Hook interrupt last to avoid having to lock softc 430 */ 431 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 432 bfe_intr, sc, &sc->bfe_intrhand); 433 434 if (error) { 435 bfe_release_resources(sc); 436 printf("bfe%d: couldn't set up irq\n", unit); 437 goto fail; 438 } 439 fail: 440 if(error) 441 bfe_release_resources(sc); 442 return(error); 443 } 444 445 static int 446 bfe_detach(device_t dev) 447 { 448 struct bfe_softc *sc; 449 struct ifnet *ifp; 450 451 sc = device_get_softc(dev); 452 453 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 454 BFE_LOCK(scp); 455 456 ifp = &sc->arpcom.ac_if; 457 458 if (device_is_attached(dev)) { 459 bfe_stop(sc); 460 ether_ifdetach(ifp); 461 } 462 463 bfe_chip_reset(sc); 464 465 bus_generic_detach(dev); 466 if(sc->bfe_miibus != NULL) 467 device_delete_child(dev, sc->bfe_miibus); 468 469 bfe_release_resources(sc); 470 BFE_UNLOCK(sc); 471 mtx_destroy(&sc->bfe_mtx); 472 473 return(0); 474 } 475 476 /* 477 * Stop all chip I/O so that the kernel's probe routines don't 478 * get confused by errant DMAs when rebooting. 479 */ 480 static void 481 bfe_shutdown(device_t dev) 482 { 483 struct bfe_softc *sc; 484 485 sc = device_get_softc(dev); 486 BFE_LOCK(sc); 487 bfe_stop(sc); 488 489 BFE_UNLOCK(sc); 490 return; 491 } 492 493 static int 494 bfe_miibus_readreg(device_t dev, int phy, int reg) 495 { 496 struct bfe_softc *sc; 497 u_int32_t ret; 498 499 sc = device_get_softc(dev); 500 if(phy != sc->bfe_phyaddr) 501 return(0); 502 bfe_readphy(sc, reg, &ret); 503 504 return(ret); 505 } 506 507 static int 508 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 509 { 510 struct bfe_softc *sc; 511 512 sc = device_get_softc(dev); 513 if(phy != sc->bfe_phyaddr) 514 return(0); 515 bfe_writephy(sc, reg, val); 516 517 return(0); 518 } 519 520 static void 521 bfe_miibus_statchg(device_t dev) 522 { 523 return; 524 } 525 526 static void 527 bfe_tx_ring_free(struct bfe_softc *sc) 528 { 529 int i; 530 531 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 532 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 533 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 534 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 535 bus_dmamap_unload(sc->bfe_tag, 536 sc->bfe_tx_ring[i].bfe_map); 537 bus_dmamap_destroy(sc->bfe_tag, 538 sc->bfe_tx_ring[i].bfe_map); 539 } 540 } 541 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 542 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 543 } 544 545 static void 546 bfe_rx_ring_free(struct bfe_softc *sc) 547 { 548 int i; 549 550 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 551 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 552 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 553 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 554 bus_dmamap_unload(sc->bfe_tag, 555 sc->bfe_rx_ring[i].bfe_map); 556 bus_dmamap_destroy(sc->bfe_tag, 557 sc->bfe_rx_ring[i].bfe_map); 558 } 559 } 560 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 561 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 562 } 563 564 565 static int 566 bfe_list_rx_init(struct bfe_softc *sc) 567 { 568 int i; 569 570 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 571 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 572 return ENOBUFS; 573 } 574 575 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 576 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 577 578 sc->bfe_rx_cons = 0; 579 580 return(0); 581 } 582 583 static int 584 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 585 { 586 struct bfe_rxheader *rx_header; 587 struct bfe_desc *d; 588 struct bfe_data *r; 589 u_int32_t ctrl; 590 591 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 592 return(EINVAL); 593 594 if(m == NULL) { 595 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 596 if(m == NULL) 597 return(ENOBUFS); 598 m->m_len = m->m_pkthdr.len = MCLBYTES; 599 } 600 else 601 m->m_data = m->m_ext.ext_buf; 602 603 rx_header = mtod(m, struct bfe_rxheader *); 604 rx_header->len = 0; 605 rx_header->flags = 0; 606 607 /* Map the mbuf into DMA */ 608 sc->bfe_rx_cnt = c; 609 d = &sc->bfe_rx_list[c]; 610 r = &sc->bfe_rx_ring[c]; 611 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 612 MCLBYTES, bfe_dma_map_desc, d, 0); 613 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 614 615 ctrl = ETHER_MAX_LEN + 32; 616 617 if(c == BFE_RX_LIST_CNT - 1) 618 ctrl |= BFE_DESC_EOT; 619 620 d->bfe_ctrl = ctrl; 621 r->bfe_mbuf = m; 622 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 623 return(0); 624 } 625 626 static void 627 bfe_get_config(struct bfe_softc *sc) 628 { 629 u_int8_t eeprom[128]; 630 631 bfe_read_eeprom(sc, eeprom); 632 633 sc->arpcom.ac_enaddr[0] = eeprom[79]; 634 sc->arpcom.ac_enaddr[1] = eeprom[78]; 635 sc->arpcom.ac_enaddr[2] = eeprom[81]; 636 sc->arpcom.ac_enaddr[3] = eeprom[80]; 637 sc->arpcom.ac_enaddr[4] = eeprom[83]; 638 sc->arpcom.ac_enaddr[5] = eeprom[82]; 639 640 sc->bfe_phyaddr = eeprom[90] & 0x1f; 641 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 642 643 sc->bfe_core_unit = 0; 644 sc->bfe_dma_offset = BFE_PCI_DMA; 645 } 646 647 static void 648 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 649 { 650 u_int32_t bar_orig, pci_rev, val; 651 652 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 653 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 654 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 655 656 val = CSR_READ_4(sc, BFE_SBINTVEC); 657 val |= cores; 658 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 659 660 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 661 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 662 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 663 664 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 665 } 666 667 static void 668 bfe_clear_stats(struct bfe_softc *sc) 669 { 670 u_long reg; 671 672 BFE_LOCK(sc); 673 674 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 675 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 676 CSR_READ_4(sc, reg); 677 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 678 CSR_READ_4(sc, reg); 679 680 BFE_UNLOCK(sc); 681 } 682 683 static int 684 bfe_resetphy(struct bfe_softc *sc) 685 { 686 u_int32_t val; 687 688 BFE_LOCK(sc); 689 bfe_writephy(sc, 0, BMCR_RESET); 690 DELAY(100); 691 bfe_readphy(sc, 0, &val); 692 if (val & BMCR_RESET) { 693 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 694 BFE_UNLOCK(sc); 695 return ENXIO; 696 } 697 BFE_UNLOCK(sc); 698 return 0; 699 } 700 701 static void 702 bfe_chip_halt(struct bfe_softc *sc) 703 { 704 BFE_LOCK(sc); 705 /* disable interrupts - not that it actually does..*/ 706 CSR_WRITE_4(sc, BFE_IMASK, 0); 707 CSR_READ_4(sc, BFE_IMASK); 708 709 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 710 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 711 712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 713 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 714 DELAY(10); 715 716 BFE_UNLOCK(sc); 717 } 718 719 static void 720 bfe_chip_reset(struct bfe_softc *sc) 721 { 722 u_int32_t val; 723 724 BFE_LOCK(sc); 725 726 /* Set the interrupt vector for the enet core */ 727 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 728 729 /* is core up? */ 730 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 731 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 732 if (val == BFE_CLOCK) { 733 /* It is, so shut it down */ 734 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 735 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 736 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 737 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 738 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 739 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 740 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 741 100, 0); 742 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 743 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 744 } 745 746 bfe_core_reset(sc); 747 bfe_clear_stats(sc); 748 749 /* 750 * We want the phy registers to be accessible even when 751 * the driver is "downed" so initialize MDC preamble, frequency, 752 * and whether internal or external phy here. 753 */ 754 755 /* 4402 has 62.5Mhz SB clock and internal phy */ 756 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 757 758 /* Internal or external PHY? */ 759 val = CSR_READ_4(sc, BFE_DEVCTRL); 760 if(!(val & BFE_IPP)) 761 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 762 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 763 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 764 DELAY(100); 765 } 766 767 /* Enable CRC32 generation and set proper LED modes */ 768 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 769 770 /* Reset or clear powerdown control bit */ 771 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 772 773 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 774 BFE_LAZY_FC_MASK)); 775 776 /* 777 * We don't want lazy interrupts, so just send them at 778 * the end of a frame, please 779 */ 780 BFE_OR(sc, BFE_RCV_LAZY, 0); 781 782 /* Set max lengths, accounting for VLAN tags */ 783 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 784 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 785 786 /* Set watermark XXX - magic */ 787 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 788 789 /* 790 * Initialise DMA channels 791 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 792 */ 793 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 794 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 795 796 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 797 BFE_RX_CTRL_ENABLE); 798 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 799 800 bfe_resetphy(sc); 801 bfe_setupphy(sc); 802 803 BFE_UNLOCK(sc); 804 } 805 806 static void 807 bfe_core_disable(struct bfe_softc *sc) 808 { 809 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 810 return; 811 812 /* 813 * Set reject, wait for it set, then wait for the core to stop 814 * being busy, then set reset and reject and enable the clocks. 815 */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 817 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 818 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 820 BFE_RESET)); 821 CSR_READ_4(sc, BFE_SBTMSLOW); 822 DELAY(10); 823 /* Leave reset and reject set */ 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 825 DELAY(10); 826 } 827 828 static void 829 bfe_core_reset(struct bfe_softc *sc) 830 { 831 u_int32_t val; 832 833 /* Disable the core */ 834 bfe_core_disable(sc); 835 836 /* and bring it back up */ 837 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 841 /* Chip bug, clear SERR, IB and TO if they are set. */ 842 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 843 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 844 val = CSR_READ_4(sc, BFE_SBIMSTATE); 845 if (val & (BFE_IBE | BFE_TO)) 846 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 847 848 /* Clear reset and allow it to move through the core */ 849 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 850 CSR_READ_4(sc, BFE_SBTMSLOW); 851 DELAY(10); 852 853 /* Leave the clock set */ 854 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 855 CSR_READ_4(sc, BFE_SBTMSLOW); 856 DELAY(10); 857 } 858 859 static void 860 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 861 { 862 u_int32_t val; 863 864 val = ((u_int32_t) data[2]) << 24; 865 val |= ((u_int32_t) data[3]) << 16; 866 val |= ((u_int32_t) data[4]) << 8; 867 val |= ((u_int32_t) data[5]); 868 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 869 val = (BFE_CAM_HI_VALID | 870 (((u_int32_t) data[0]) << 8) | 871 (((u_int32_t) data[1]))); 872 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 873 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 874 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 875 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 876 } 877 878 static void 879 bfe_set_rx_mode(struct bfe_softc *sc) 880 { 881 struct ifnet *ifp = &sc->arpcom.ac_if; 882 struct ifmultiaddr *ifma; 883 u_int32_t val; 884 int i = 0; 885 886 val = CSR_READ_4(sc, BFE_RXCONF); 887 888 if (ifp->if_flags & IFF_PROMISC) 889 val |= BFE_RXCONF_PROMISC; 890 else 891 val &= ~BFE_RXCONF_PROMISC; 892 893 if (ifp->if_flags & IFF_BROADCAST) 894 val &= ~BFE_RXCONF_DBCAST; 895 else 896 val |= BFE_RXCONF_DBCAST; 897 898 899 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 900 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 901 902 if (ifp->if_flags & IFF_ALLMULTI) 903 val |= BFE_RXCONF_ALLMULTI; 904 else { 905 val &= ~BFE_RXCONF_ALLMULTI; 906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 907 if (ifma->ifma_addr->sa_family != AF_LINK) 908 continue; 909 bfe_cam_write(sc, 910 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 911 } 912 } 913 914 CSR_WRITE_4(sc, BFE_RXCONF, val); 915 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 916 } 917 918 static void 919 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 920 { 921 u_int32_t *ptr; 922 923 ptr = arg; 924 *ptr = segs->ds_addr; 925 } 926 927 static void 928 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 929 { 930 struct bfe_desc *d; 931 932 d = arg; 933 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 934 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 935 } 936 937 static void 938 bfe_release_resources(struct bfe_softc *sc) 939 { 940 device_t dev; 941 int i; 942 943 dev = sc->bfe_dev; 944 945 if (sc->bfe_vpd_prodname != NULL) 946 free(sc->bfe_vpd_prodname, M_DEVBUF); 947 948 if (sc->bfe_vpd_readonly != NULL) 949 free(sc->bfe_vpd_readonly, M_DEVBUF); 950 951 if (sc->bfe_intrhand != NULL) 952 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 953 954 if (sc->bfe_irq != NULL) 955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 956 957 if (sc->bfe_res != NULL) 958 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 959 960 if(sc->bfe_tx_tag != NULL) { 961 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 962 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 963 sc->bfe_tx_map); 964 bus_dma_tag_destroy(sc->bfe_tx_tag); 965 sc->bfe_tx_tag = NULL; 966 } 967 968 if(sc->bfe_rx_tag != NULL) { 969 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 970 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 971 sc->bfe_rx_map); 972 bus_dma_tag_destroy(sc->bfe_rx_tag); 973 sc->bfe_rx_tag = NULL; 974 } 975 976 if(sc->bfe_tag != NULL) { 977 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 978 bus_dmamap_destroy(sc->bfe_tag, 979 sc->bfe_tx_ring[i].bfe_map); 980 } 981 bus_dma_tag_destroy(sc->bfe_tag); 982 sc->bfe_tag = NULL; 983 } 984 985 if(sc->bfe_parent_tag != NULL) 986 bus_dma_tag_destroy(sc->bfe_parent_tag); 987 988 return; 989 } 990 991 static void 992 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 993 { 994 long i; 995 u_int16_t *ptr = (u_int16_t *)data; 996 997 for(i = 0; i < 128; i += 2) 998 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 999 } 1000 1001 static int 1002 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1003 u_long timeout, const int clear) 1004 { 1005 u_long i; 1006 1007 for (i = 0; i < timeout; i++) { 1008 u_int32_t val = CSR_READ_4(sc, reg); 1009 1010 if (clear && !(val & bit)) 1011 break; 1012 if (!clear && (val & bit)) 1013 break; 1014 DELAY(10); 1015 } 1016 if (i == timeout) { 1017 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1018 "%x to %s.\n", sc->bfe_unit, bit, reg, 1019 (clear ? "clear" : "set")); 1020 return -1; 1021 } 1022 return 0; 1023 } 1024 1025 static int 1026 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1027 { 1028 int err; 1029 1030 BFE_LOCK(sc); 1031 /* Clear MII ISR */ 1032 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1033 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1034 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1035 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1036 (reg << BFE_MDIO_RA_SHIFT) | 1037 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1038 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1039 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1040 1041 BFE_UNLOCK(sc); 1042 return err; 1043 } 1044 1045 static int 1046 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1047 { 1048 int status; 1049 1050 BFE_LOCK(sc); 1051 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1052 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1053 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1054 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1055 (reg << BFE_MDIO_RA_SHIFT) | 1056 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1057 (val & BFE_MDIO_DATA_DATA))); 1058 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1059 BFE_UNLOCK(sc); 1060 1061 return status; 1062 } 1063 1064 /* 1065 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1066 * twice 1067 */ 1068 static int 1069 bfe_setupphy(struct bfe_softc *sc) 1070 { 1071 u_int32_t val; 1072 BFE_LOCK(sc); 1073 1074 /* Enable activity LED */ 1075 bfe_readphy(sc, 26, &val); 1076 bfe_writephy(sc, 26, val & 0x7fff); 1077 bfe_readphy(sc, 26, &val); 1078 1079 /* Enable traffic meter LED mode */ 1080 bfe_readphy(sc, 27, &val); 1081 bfe_writephy(sc, 27, val | (1 << 6)); 1082 1083 BFE_UNLOCK(sc); 1084 return 0; 1085 } 1086 1087 static void 1088 bfe_stats_update(struct bfe_softc *sc) 1089 { 1090 u_long reg; 1091 u_int32_t *val; 1092 1093 val = &sc->bfe_hwstats.tx_good_octets; 1094 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1095 *val++ += CSR_READ_4(sc, reg); 1096 } 1097 val = &sc->bfe_hwstats.rx_good_octets; 1098 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1099 *val++ += CSR_READ_4(sc, reg); 1100 } 1101 } 1102 1103 static void 1104 bfe_txeof(struct bfe_softc *sc) 1105 { 1106 struct ifnet *ifp; 1107 int i, chipidx; 1108 1109 BFE_LOCK(sc); 1110 1111 ifp = &sc->arpcom.ac_if; 1112 1113 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1114 chipidx /= sizeof(struct bfe_desc); 1115 1116 i = sc->bfe_tx_cons; 1117 /* Go through the mbufs and free those that have been transmitted */ 1118 while(i != chipidx) { 1119 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1120 if(r->bfe_mbuf != NULL) { 1121 ifp->if_opackets++; 1122 m_freem(r->bfe_mbuf); 1123 r->bfe_mbuf = NULL; 1124 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1125 } 1126 sc->bfe_tx_cnt--; 1127 BFE_INC(i, BFE_TX_LIST_CNT); 1128 } 1129 1130 if(i != sc->bfe_tx_cons) { 1131 /* we freed up some mbufs */ 1132 sc->bfe_tx_cons = i; 1133 ifp->if_flags &= ~IFF_OACTIVE; 1134 } 1135 if(sc->bfe_tx_cnt == 0) 1136 ifp->if_timer = 0; 1137 else 1138 ifp->if_timer = 5; 1139 1140 BFE_UNLOCK(sc); 1141 } 1142 1143 /* Pass a received packet up the stack */ 1144 static void 1145 bfe_rxeof(struct bfe_softc *sc) 1146 { 1147 struct mbuf *m; 1148 struct ifnet *ifp; 1149 struct bfe_rxheader *rxheader; 1150 struct bfe_data *r; 1151 int cons; 1152 u_int32_t status, current, len, flags; 1153 1154 BFE_LOCK(sc); 1155 cons = sc->bfe_rx_cons; 1156 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1157 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 while(current != cons) { 1162 r = &sc->bfe_rx_ring[cons]; 1163 m = r->bfe_mbuf; 1164 rxheader = mtod(m, struct bfe_rxheader*); 1165 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1166 len = rxheader->len; 1167 r->bfe_mbuf = NULL; 1168 1169 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1170 flags = rxheader->flags; 1171 1172 len -= ETHER_CRC_LEN; 1173 1174 /* flag an error and try again */ 1175 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1176 ifp->if_ierrors++; 1177 if (flags & BFE_RX_FLAG_SERR) 1178 ifp->if_collisions++; 1179 bfe_list_newbuf(sc, cons, m); 1180 BFE_INC(cons, BFE_RX_LIST_CNT); 1181 continue; 1182 } 1183 1184 /* Go past the rx header */ 1185 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1186 m_adj(m, BFE_RX_OFFSET); 1187 m->m_len = m->m_pkthdr.len = len; 1188 } else { 1189 bfe_list_newbuf(sc, cons, m); 1190 ifp->if_ierrors++; 1191 BFE_INC(cons, BFE_RX_LIST_CNT); 1192 continue; 1193 } 1194 1195 ifp->if_ipackets++; 1196 m->m_pkthdr.rcvif = ifp; 1197 BFE_UNLOCK(sc); 1198 (*ifp->if_input)(ifp, m); 1199 BFE_LOCK(sc); 1200 1201 BFE_INC(cons, BFE_RX_LIST_CNT); 1202 } 1203 sc->bfe_rx_cons = cons; 1204 BFE_UNLOCK(sc); 1205 } 1206 1207 static void 1208 bfe_intr(void *xsc) 1209 { 1210 struct bfe_softc *sc = xsc; 1211 struct ifnet *ifp; 1212 u_int32_t istat, imask, flag; 1213 1214 ifp = &sc->arpcom.ac_if; 1215 1216 BFE_LOCK(sc); 1217 1218 istat = CSR_READ_4(sc, BFE_ISTAT); 1219 imask = CSR_READ_4(sc, BFE_IMASK); 1220 1221 /* 1222 * Defer unsolicited interrupts - This is necessary because setting the 1223 * chips interrupt mask register to 0 doesn't actually stop the 1224 * interrupts 1225 */ 1226 istat &= imask; 1227 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1228 CSR_READ_4(sc, BFE_ISTAT); 1229 1230 /* not expecting this interrupt, disregard it */ 1231 if(istat == 0) { 1232 BFE_UNLOCK(sc); 1233 return; 1234 } 1235 1236 if(istat & BFE_ISTAT_ERRORS) { 1237 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1238 if(flag & BFE_STAT_EMASK) 1239 ifp->if_oerrors++; 1240 1241 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1242 if(flag & BFE_RX_FLAG_ERRORS) 1243 ifp->if_ierrors++; 1244 1245 ifp->if_flags &= ~IFF_RUNNING; 1246 bfe_init(sc); 1247 } 1248 1249 /* A packet was received */ 1250 if(istat & BFE_ISTAT_RX) 1251 bfe_rxeof(sc); 1252 1253 /* A packet was sent */ 1254 if(istat & BFE_ISTAT_TX) 1255 bfe_txeof(sc); 1256 1257 /* We have packets pending, fire them out */ 1258 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1259 bfe_start(ifp); 1260 1261 BFE_UNLOCK(sc); 1262 } 1263 1264 static int 1265 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1266 { 1267 struct bfe_desc *d = NULL; 1268 struct bfe_data *r = NULL; 1269 struct mbuf *m; 1270 u_int32_t frag, cur, cnt = 0; 1271 int chainlen = 0; 1272 1273 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1274 return(ENOBUFS); 1275 1276 /* 1277 * Count the number of frags in this chain to see if 1278 * we need to m_defrag. Since the descriptor list is shared 1279 * by all packets, we'll m_defrag long chains so that they 1280 * do not use up the entire list, even if they would fit. 1281 */ 1282 for(m = m_head; m != NULL; m = m->m_next) 1283 chainlen++; 1284 1285 1286 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1287 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1288 m = m_defrag(m_head, M_DONTWAIT); 1289 if (m == NULL) 1290 return(ENOBUFS); 1291 m_head = m; 1292 } 1293 1294 /* 1295 * Start packing the mbufs in this chain into 1296 * the fragment pointers. Stop when we run out 1297 * of fragments or hit the end of the mbuf chain. 1298 */ 1299 m = m_head; 1300 cur = frag = *txidx; 1301 cnt = 0; 1302 1303 for(m = m_head; m != NULL; m = m->m_next) { 1304 if(m->m_len != 0) { 1305 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1306 return(ENOBUFS); 1307 1308 d = &sc->bfe_tx_list[cur]; 1309 r = &sc->bfe_tx_ring[cur]; 1310 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1311 /* always intterupt on completion */ 1312 d->bfe_ctrl |= BFE_DESC_IOC; 1313 if(cnt == 0) 1314 /* Set start of frame */ 1315 d->bfe_ctrl |= BFE_DESC_SOF; 1316 if(cur == BFE_TX_LIST_CNT - 1) 1317 /* 1318 * Tell the chip to wrap to the start of 1319 * the descriptor list 1320 */ 1321 d->bfe_ctrl |= BFE_DESC_EOT; 1322 1323 bus_dmamap_load(sc->bfe_tag, 1324 r->bfe_map, mtod(m, void*), m->m_len, 1325 bfe_dma_map_desc, d, 0); 1326 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1327 BUS_DMASYNC_PREREAD); 1328 1329 frag = cur; 1330 BFE_INC(cur, BFE_TX_LIST_CNT); 1331 cnt++; 1332 } 1333 } 1334 1335 if (m != NULL) 1336 return(ENOBUFS); 1337 1338 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1339 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1340 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1341 1342 *txidx = cur; 1343 sc->bfe_tx_cnt += cnt; 1344 return (0); 1345 } 1346 1347 /* 1348 * Set up to transmit a packet 1349 */ 1350 static void 1351 bfe_start(struct ifnet *ifp) 1352 { 1353 struct bfe_softc *sc; 1354 struct mbuf *m_head = NULL; 1355 int idx; 1356 1357 sc = ifp->if_softc; 1358 idx = sc->bfe_tx_prod; 1359 1360 BFE_LOCK(sc); 1361 1362 /* 1363 * Not much point trying to send if the link is down 1364 * or we have nothing to send. 1365 */ 1366 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1367 BFE_UNLOCK(sc); 1368 return; 1369 } 1370 1371 if (ifp->if_flags & IFF_OACTIVE) { 1372 BFE_UNLOCK(sc); 1373 return; 1374 } 1375 1376 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1377 IF_DEQUEUE(&ifp->if_snd, m_head); 1378 if(m_head == NULL) 1379 break; 1380 1381 /* 1382 * Pack the data into the tx ring. If we dont have 1383 * enough room, let the chip drain the ring. 1384 */ 1385 if(bfe_encap(sc, m_head, &idx)) { 1386 IF_PREPEND(&ifp->if_snd, m_head); 1387 ifp->if_flags |= IFF_OACTIVE; 1388 break; 1389 } 1390 1391 /* 1392 * If there's a BPF listener, bounce a copy of this frame 1393 * to him. 1394 */ 1395 BPF_MTAP(ifp, m_head); 1396 } 1397 1398 sc->bfe_tx_prod = idx; 1399 /* Transmit - twice due to apparent hardware bug */ 1400 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1401 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1402 1403 /* 1404 * Set a timeout in case the chip goes out to lunch. 1405 */ 1406 ifp->if_timer = 5; 1407 BFE_UNLOCK(sc); 1408 } 1409 1410 static void 1411 bfe_init(void *xsc) 1412 { 1413 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1414 struct ifnet *ifp = &sc->arpcom.ac_if; 1415 1416 BFE_LOCK(sc); 1417 1418 if (ifp->if_flags & IFF_RUNNING) { 1419 BFE_UNLOCK(sc); 1420 return; 1421 } 1422 1423 bfe_stop(sc); 1424 bfe_chip_reset(sc); 1425 1426 if (bfe_list_rx_init(sc) == ENOBUFS) { 1427 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1428 sc->bfe_unit); 1429 bfe_stop(sc); 1430 return; 1431 } 1432 1433 bfe_set_rx_mode(sc); 1434 1435 /* Enable the chip and core */ 1436 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1437 /* Enable interrupts */ 1438 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1439 1440 bfe_ifmedia_upd(ifp); 1441 ifp->if_flags |= IFF_RUNNING; 1442 ifp->if_flags &= ~IFF_OACTIVE; 1443 1444 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1445 BFE_UNLOCK(sc); 1446 } 1447 1448 /* 1449 * Set media options. 1450 */ 1451 static int 1452 bfe_ifmedia_upd(struct ifnet *ifp) 1453 { 1454 struct bfe_softc *sc; 1455 struct mii_data *mii; 1456 1457 sc = ifp->if_softc; 1458 1459 BFE_LOCK(sc); 1460 1461 mii = device_get_softc(sc->bfe_miibus); 1462 sc->bfe_link = 0; 1463 if (mii->mii_instance) { 1464 struct mii_softc *miisc; 1465 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1466 miisc = LIST_NEXT(miisc, mii_list)) 1467 mii_phy_reset(miisc); 1468 } 1469 mii_mediachg(mii); 1470 1471 BFE_UNLOCK(sc); 1472 return(0); 1473 } 1474 1475 /* 1476 * Report current media status. 1477 */ 1478 static void 1479 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1480 { 1481 struct bfe_softc *sc = ifp->if_softc; 1482 struct mii_data *mii; 1483 1484 BFE_LOCK(sc); 1485 1486 mii = device_get_softc(sc->bfe_miibus); 1487 mii_pollstat(mii); 1488 ifmr->ifm_active = mii->mii_media_active; 1489 ifmr->ifm_status = mii->mii_media_status; 1490 1491 BFE_UNLOCK(sc); 1492 } 1493 1494 static int 1495 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1496 { 1497 struct bfe_softc *sc = ifp->if_softc; 1498 struct ifreq *ifr = (struct ifreq *) data; 1499 struct mii_data *mii; 1500 int error = 0; 1501 1502 BFE_LOCK(sc); 1503 1504 switch(command) { 1505 case SIOCSIFFLAGS: 1506 if(ifp->if_flags & IFF_UP) 1507 if(ifp->if_flags & IFF_RUNNING) 1508 bfe_set_rx_mode(sc); 1509 else 1510 bfe_init(sc); 1511 else if(ifp->if_flags & IFF_RUNNING) 1512 bfe_stop(sc); 1513 break; 1514 case SIOCADDMULTI: 1515 case SIOCDELMULTI: 1516 if(ifp->if_flags & IFF_RUNNING) 1517 bfe_set_rx_mode(sc); 1518 break; 1519 case SIOCGIFMEDIA: 1520 case SIOCSIFMEDIA: 1521 mii = device_get_softc(sc->bfe_miibus); 1522 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1523 command); 1524 break; 1525 default: 1526 error = ether_ioctl(ifp, command, data); 1527 break; 1528 } 1529 1530 BFE_UNLOCK(sc); 1531 return error; 1532 } 1533 1534 static void 1535 bfe_watchdog(struct ifnet *ifp) 1536 { 1537 struct bfe_softc *sc; 1538 1539 sc = ifp->if_softc; 1540 1541 BFE_LOCK(sc); 1542 1543 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1544 1545 ifp->if_flags &= ~IFF_RUNNING; 1546 bfe_init(sc); 1547 1548 ifp->if_oerrors++; 1549 1550 BFE_UNLOCK(sc); 1551 } 1552 1553 static void 1554 bfe_tick(void *xsc) 1555 { 1556 struct bfe_softc *sc = xsc; 1557 struct mii_data *mii; 1558 1559 if (sc == NULL) 1560 return; 1561 1562 BFE_LOCK(sc); 1563 1564 mii = device_get_softc(sc->bfe_miibus); 1565 1566 bfe_stats_update(sc); 1567 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1568 1569 if(sc->bfe_link) { 1570 BFE_UNLOCK(sc); 1571 return; 1572 } 1573 1574 mii_tick(mii); 1575 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1576 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1577 sc->bfe_link++; 1578 1579 BFE_UNLOCK(sc); 1580 } 1581 1582 /* 1583 * Stop the adapter and free any mbufs allocated to the 1584 * RX and TX lists. 1585 */ 1586 static void 1587 bfe_stop(struct bfe_softc *sc) 1588 { 1589 struct ifnet *ifp; 1590 1591 BFE_LOCK(sc); 1592 1593 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1594 1595 ifp = &sc->arpcom.ac_if; 1596 1597 bfe_chip_halt(sc); 1598 bfe_tx_ring_free(sc); 1599 bfe_rx_ring_free(sc); 1600 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 1603 BFE_UNLOCK(sc); 1604 } 1605