1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp = NULL; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 354 355 /* Allocate interrupt */ 356 rid = 0; 357 358 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 359 RF_SHAREABLE | RF_ACTIVE); 360 if (sc->bfe_irq == NULL) { 361 printf("bfe%d: couldn't map interrupt\n", unit); 362 error = ENXIO; 363 goto fail; 364 } 365 366 if (bfe_dma_alloc(dev)) { 367 printf("bfe%d: failed to allocate DMA resources\n", 368 sc->bfe_unit); 369 bfe_release_resources(sc); 370 error = ENXIO; 371 goto fail; 372 } 373 374 /* Set up ifnet structure */ 375 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 376 if (ifp == NULL) { 377 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 378 error = ENOSPC; 379 goto fail; 380 } 381 ifp->if_softc = sc; 382 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_ioctl = bfe_ioctl; 385 ifp->if_start = bfe_start; 386 ifp->if_watchdog = bfe_watchdog; 387 ifp->if_init = bfe_init; 388 ifp->if_mtu = ETHERMTU; 389 ifp->if_baudrate = 100000000; 390 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 391 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 392 IFQ_SET_READY(&ifp->if_snd); 393 394 bfe_get_config(sc); 395 396 /* Reset the chip and turn on the PHY */ 397 BFE_LOCK(sc); 398 bfe_chip_reset(sc); 399 BFE_UNLOCK(sc); 400 401 if (mii_phy_probe(dev, &sc->bfe_miibus, 402 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 403 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 404 error = ENXIO; 405 goto fail; 406 } 407 408 ether_ifattach(ifp, sc->bfe_enaddr); 409 callout_handle_init(&sc->bfe_stat_ch); 410 411 /* 412 * Tell the upper layer(s) we support long frames. 413 */ 414 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 415 ifp->if_capabilities |= IFCAP_VLAN_MTU; 416 ifp->if_capenable |= IFCAP_VLAN_MTU; 417 418 /* 419 * Hook interrupt last to avoid having to lock softc 420 */ 421 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 422 bfe_intr, sc, &sc->bfe_intrhand); 423 424 if (error) { 425 bfe_release_resources(sc); 426 printf("bfe%d: couldn't set up irq\n", unit); 427 goto fail; 428 } 429 fail: 430 if(error) { 431 bfe_release_resources(sc); 432 if (ifp != NULL) 433 if_free(ifp); 434 } 435 return (error); 436 } 437 438 static int 439 bfe_detach(device_t dev) 440 { 441 struct bfe_softc *sc; 442 struct ifnet *ifp; 443 444 sc = device_get_softc(dev); 445 446 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 447 BFE_LOCK(sc); 448 449 ifp = sc->bfe_ifp; 450 451 if (device_is_attached(dev)) { 452 bfe_stop(sc); 453 ether_ifdetach(ifp); 454 if_free(ifp); 455 } 456 457 bfe_chip_reset(sc); 458 459 bus_generic_detach(dev); 460 if(sc->bfe_miibus != NULL) 461 device_delete_child(dev, sc->bfe_miibus); 462 463 bfe_release_resources(sc); 464 BFE_UNLOCK(sc); 465 mtx_destroy(&sc->bfe_mtx); 466 467 return (0); 468 } 469 470 /* 471 * Stop all chip I/O so that the kernel's probe routines don't 472 * get confused by errant DMAs when rebooting. 473 */ 474 static void 475 bfe_shutdown(device_t dev) 476 { 477 struct bfe_softc *sc; 478 479 sc = device_get_softc(dev); 480 BFE_LOCK(sc); 481 bfe_stop(sc); 482 483 BFE_UNLOCK(sc); 484 return; 485 } 486 487 static int 488 bfe_miibus_readreg(device_t dev, int phy, int reg) 489 { 490 struct bfe_softc *sc; 491 u_int32_t ret; 492 493 sc = device_get_softc(dev); 494 if(phy != sc->bfe_phyaddr) 495 return (0); 496 bfe_readphy(sc, reg, &ret); 497 498 return (ret); 499 } 500 501 static int 502 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 503 { 504 struct bfe_softc *sc; 505 506 sc = device_get_softc(dev); 507 if(phy != sc->bfe_phyaddr) 508 return (0); 509 bfe_writephy(sc, reg, val); 510 511 return (0); 512 } 513 514 static void 515 bfe_miibus_statchg(device_t dev) 516 { 517 return; 518 } 519 520 static void 521 bfe_tx_ring_free(struct bfe_softc *sc) 522 { 523 int i; 524 525 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 526 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 527 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 528 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 529 bus_dmamap_unload(sc->bfe_tag, 530 sc->bfe_tx_ring[i].bfe_map); 531 } 532 } 533 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 534 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 535 } 536 537 static void 538 bfe_rx_ring_free(struct bfe_softc *sc) 539 { 540 int i; 541 542 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 543 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 544 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 545 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 546 bus_dmamap_unload(sc->bfe_tag, 547 sc->bfe_rx_ring[i].bfe_map); 548 } 549 } 550 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 551 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 552 } 553 554 static int 555 bfe_list_rx_init(struct bfe_softc *sc) 556 { 557 int i; 558 559 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 560 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 561 return (ENOBUFS); 562 } 563 564 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 565 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 566 567 sc->bfe_rx_cons = 0; 568 569 return (0); 570 } 571 572 static int 573 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 574 { 575 struct bfe_rxheader *rx_header; 576 struct bfe_desc *d; 577 struct bfe_data *r; 578 u_int32_t ctrl; 579 580 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 581 return (EINVAL); 582 583 if(m == NULL) { 584 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 585 if(m == NULL) 586 return (ENOBUFS); 587 m->m_len = m->m_pkthdr.len = MCLBYTES; 588 } 589 else 590 m->m_data = m->m_ext.ext_buf; 591 592 rx_header = mtod(m, struct bfe_rxheader *); 593 rx_header->len = 0; 594 rx_header->flags = 0; 595 596 /* Map the mbuf into DMA */ 597 sc->bfe_rx_cnt = c; 598 d = &sc->bfe_rx_list[c]; 599 r = &sc->bfe_rx_ring[c]; 600 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 601 MCLBYTES, bfe_dma_map_desc, d, 0); 602 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 603 604 ctrl = ETHER_MAX_LEN + 32; 605 606 if(c == BFE_RX_LIST_CNT - 1) 607 ctrl |= BFE_DESC_EOT; 608 609 d->bfe_ctrl = ctrl; 610 r->bfe_mbuf = m; 611 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 612 return (0); 613 } 614 615 static void 616 bfe_get_config(struct bfe_softc *sc) 617 { 618 u_int8_t eeprom[128]; 619 620 bfe_read_eeprom(sc, eeprom); 621 622 sc->bfe_enaddr[0] = eeprom[79]; 623 sc->bfe_enaddr[1] = eeprom[78]; 624 sc->bfe_enaddr[2] = eeprom[81]; 625 sc->bfe_enaddr[3] = eeprom[80]; 626 sc->bfe_enaddr[4] = eeprom[83]; 627 sc->bfe_enaddr[5] = eeprom[82]; 628 629 sc->bfe_phyaddr = eeprom[90] & 0x1f; 630 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 631 632 sc->bfe_core_unit = 0; 633 sc->bfe_dma_offset = BFE_PCI_DMA; 634 } 635 636 static void 637 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 638 { 639 u_int32_t bar_orig, pci_rev, val; 640 641 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 642 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 643 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 644 645 val = CSR_READ_4(sc, BFE_SBINTVEC); 646 val |= cores; 647 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 648 649 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 650 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 651 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 652 653 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 654 } 655 656 static void 657 bfe_clear_stats(struct bfe_softc *sc) 658 { 659 u_long reg; 660 661 BFE_LOCK_ASSERT(sc); 662 663 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 664 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 665 CSR_READ_4(sc, reg); 666 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 667 CSR_READ_4(sc, reg); 668 } 669 670 static int 671 bfe_resetphy(struct bfe_softc *sc) 672 { 673 u_int32_t val; 674 675 bfe_writephy(sc, 0, BMCR_RESET); 676 DELAY(100); 677 bfe_readphy(sc, 0, &val); 678 if (val & BMCR_RESET) { 679 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 680 return (ENXIO); 681 } 682 return (0); 683 } 684 685 static void 686 bfe_chip_halt(struct bfe_softc *sc) 687 { 688 BFE_LOCK_ASSERT(sc); 689 /* disable interrupts - not that it actually does..*/ 690 CSR_WRITE_4(sc, BFE_IMASK, 0); 691 CSR_READ_4(sc, BFE_IMASK); 692 693 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 694 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 695 696 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 697 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 698 DELAY(10); 699 } 700 701 static void 702 bfe_chip_reset(struct bfe_softc *sc) 703 { 704 u_int32_t val; 705 706 BFE_LOCK_ASSERT(sc); 707 708 /* Set the interrupt vector for the enet core */ 709 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 710 711 /* is core up? */ 712 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 713 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 714 if (val == BFE_CLOCK) { 715 /* It is, so shut it down */ 716 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 717 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 718 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 719 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 720 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 721 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 722 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 723 100, 0); 724 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 725 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 726 } 727 728 bfe_core_reset(sc); 729 bfe_clear_stats(sc); 730 731 /* 732 * We want the phy registers to be accessible even when 733 * the driver is "downed" so initialize MDC preamble, frequency, 734 * and whether internal or external phy here. 735 */ 736 737 /* 4402 has 62.5Mhz SB clock and internal phy */ 738 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 739 740 /* Internal or external PHY? */ 741 val = CSR_READ_4(sc, BFE_DEVCTRL); 742 if(!(val & BFE_IPP)) 743 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 744 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 745 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 746 DELAY(100); 747 } 748 749 /* Enable CRC32 generation and set proper LED modes */ 750 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 751 752 /* Reset or clear powerdown control bit */ 753 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 754 755 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 756 BFE_LAZY_FC_MASK)); 757 758 /* 759 * We don't want lazy interrupts, so just send them at 760 * the end of a frame, please 761 */ 762 BFE_OR(sc, BFE_RCV_LAZY, 0); 763 764 /* Set max lengths, accounting for VLAN tags */ 765 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 766 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 767 768 /* Set watermark XXX - magic */ 769 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 770 771 /* 772 * Initialise DMA channels 773 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 774 */ 775 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 776 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 777 778 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 779 BFE_RX_CTRL_ENABLE); 780 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 781 782 bfe_resetphy(sc); 783 bfe_setupphy(sc); 784 } 785 786 static void 787 bfe_core_disable(struct bfe_softc *sc) 788 { 789 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 790 return; 791 792 /* 793 * Set reject, wait for it set, then wait for the core to stop 794 * being busy, then set reset and reject and enable the clocks. 795 */ 796 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 797 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 798 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 799 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 800 BFE_RESET)); 801 CSR_READ_4(sc, BFE_SBTMSLOW); 802 DELAY(10); 803 /* Leave reset and reject set */ 804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 805 DELAY(10); 806 } 807 808 static void 809 bfe_core_reset(struct bfe_softc *sc) 810 { 811 u_int32_t val; 812 813 /* Disable the core */ 814 bfe_core_disable(sc); 815 816 /* and bring it back up */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 818 CSR_READ_4(sc, BFE_SBTMSLOW); 819 DELAY(10); 820 821 /* Chip bug, clear SERR, IB and TO if they are set. */ 822 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 823 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 824 val = CSR_READ_4(sc, BFE_SBIMSTATE); 825 if (val & (BFE_IBE | BFE_TO)) 826 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 827 828 /* Clear reset and allow it to move through the core */ 829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 830 CSR_READ_4(sc, BFE_SBTMSLOW); 831 DELAY(10); 832 833 /* Leave the clock set */ 834 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 835 CSR_READ_4(sc, BFE_SBTMSLOW); 836 DELAY(10); 837 } 838 839 static void 840 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 841 { 842 u_int32_t val; 843 844 val = ((u_int32_t) data[2]) << 24; 845 val |= ((u_int32_t) data[3]) << 16; 846 val |= ((u_int32_t) data[4]) << 8; 847 val |= ((u_int32_t) data[5]); 848 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 849 val = (BFE_CAM_HI_VALID | 850 (((u_int32_t) data[0]) << 8) | 851 (((u_int32_t) data[1]))); 852 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 853 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 854 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 855 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 856 } 857 858 static void 859 bfe_set_rx_mode(struct bfe_softc *sc) 860 { 861 struct ifnet *ifp = sc->bfe_ifp; 862 struct ifmultiaddr *ifma; 863 u_int32_t val; 864 int i = 0; 865 866 val = CSR_READ_4(sc, BFE_RXCONF); 867 868 if (ifp->if_flags & IFF_PROMISC) 869 val |= BFE_RXCONF_PROMISC; 870 else 871 val &= ~BFE_RXCONF_PROMISC; 872 873 if (ifp->if_flags & IFF_BROADCAST) 874 val &= ~BFE_RXCONF_DBCAST; 875 else 876 val |= BFE_RXCONF_DBCAST; 877 878 879 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 880 bfe_cam_write(sc, IFP2ENADDR(sc->bfe_ifp), i++); 881 882 if (ifp->if_flags & IFF_ALLMULTI) 883 val |= BFE_RXCONF_ALLMULTI; 884 else { 885 val &= ~BFE_RXCONF_ALLMULTI; 886 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 887 if (ifma->ifma_addr->sa_family != AF_LINK) 888 continue; 889 bfe_cam_write(sc, 890 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 891 } 892 } 893 894 CSR_WRITE_4(sc, BFE_RXCONF, val); 895 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 896 } 897 898 static void 899 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 900 { 901 u_int32_t *ptr; 902 903 ptr = arg; 904 *ptr = segs->ds_addr; 905 } 906 907 static void 908 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 909 { 910 struct bfe_desc *d; 911 912 d = arg; 913 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 914 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 915 } 916 917 static void 918 bfe_release_resources(struct bfe_softc *sc) 919 { 920 device_t dev; 921 int i; 922 923 dev = sc->bfe_dev; 924 925 if (sc->bfe_vpd_prodname != NULL) 926 free(sc->bfe_vpd_prodname, M_DEVBUF); 927 928 if (sc->bfe_vpd_readonly != NULL) 929 free(sc->bfe_vpd_readonly, M_DEVBUF); 930 931 if (sc->bfe_intrhand != NULL) 932 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 933 934 if (sc->bfe_irq != NULL) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 936 937 if (sc->bfe_res != NULL) 938 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 939 940 if(sc->bfe_tx_tag != NULL) { 941 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 942 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 943 sc->bfe_tx_map); 944 bus_dma_tag_destroy(sc->bfe_tx_tag); 945 sc->bfe_tx_tag = NULL; 946 } 947 948 if(sc->bfe_rx_tag != NULL) { 949 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 950 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 951 sc->bfe_rx_map); 952 bus_dma_tag_destroy(sc->bfe_rx_tag); 953 sc->bfe_rx_tag = NULL; 954 } 955 956 if(sc->bfe_tag != NULL) { 957 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 958 bus_dmamap_destroy(sc->bfe_tag, 959 sc->bfe_tx_ring[i].bfe_map); 960 } 961 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 962 bus_dmamap_destroy(sc->bfe_tag, 963 sc->bfe_rx_ring[i].bfe_map); 964 } 965 bus_dma_tag_destroy(sc->bfe_tag); 966 sc->bfe_tag = NULL; 967 } 968 969 if(sc->bfe_parent_tag != NULL) 970 bus_dma_tag_destroy(sc->bfe_parent_tag); 971 972 return; 973 } 974 975 static void 976 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 977 { 978 long i; 979 u_int16_t *ptr = (u_int16_t *)data; 980 981 for(i = 0; i < 128; i += 2) 982 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 983 } 984 985 static int 986 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 987 u_long timeout, const int clear) 988 { 989 u_long i; 990 991 for (i = 0; i < timeout; i++) { 992 u_int32_t val = CSR_READ_4(sc, reg); 993 994 if (clear && !(val & bit)) 995 break; 996 if (!clear && (val & bit)) 997 break; 998 DELAY(10); 999 } 1000 if (i == timeout) { 1001 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1002 "%x to %s.\n", sc->bfe_unit, bit, reg, 1003 (clear ? "clear" : "set")); 1004 return (-1); 1005 } 1006 return (0); 1007 } 1008 1009 static int 1010 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1011 { 1012 int err; 1013 1014 /* Clear MII ISR */ 1015 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1016 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1017 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1018 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1019 (reg << BFE_MDIO_RA_SHIFT) | 1020 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1021 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1022 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1023 1024 return (err); 1025 } 1026 1027 static int 1028 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1029 { 1030 int status; 1031 1032 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1033 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1034 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1035 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1036 (reg << BFE_MDIO_RA_SHIFT) | 1037 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1038 (val & BFE_MDIO_DATA_DATA))); 1039 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1040 1041 return (status); 1042 } 1043 1044 /* 1045 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1046 * twice 1047 */ 1048 static int 1049 bfe_setupphy(struct bfe_softc *sc) 1050 { 1051 u_int32_t val; 1052 1053 /* Enable activity LED */ 1054 bfe_readphy(sc, 26, &val); 1055 bfe_writephy(sc, 26, val & 0x7fff); 1056 bfe_readphy(sc, 26, &val); 1057 1058 /* Enable traffic meter LED mode */ 1059 bfe_readphy(sc, 27, &val); 1060 bfe_writephy(sc, 27, val | (1 << 6)); 1061 1062 return (0); 1063 } 1064 1065 static void 1066 bfe_stats_update(struct bfe_softc *sc) 1067 { 1068 u_long reg; 1069 u_int32_t *val; 1070 1071 val = &sc->bfe_hwstats.tx_good_octets; 1072 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1073 *val++ += CSR_READ_4(sc, reg); 1074 } 1075 val = &sc->bfe_hwstats.rx_good_octets; 1076 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1077 *val++ += CSR_READ_4(sc, reg); 1078 } 1079 } 1080 1081 static void 1082 bfe_txeof(struct bfe_softc *sc) 1083 { 1084 struct ifnet *ifp; 1085 int i, chipidx; 1086 1087 BFE_LOCK_ASSERT(sc); 1088 1089 ifp = sc->bfe_ifp; 1090 1091 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1092 chipidx /= sizeof(struct bfe_desc); 1093 1094 i = sc->bfe_tx_cons; 1095 /* Go through the mbufs and free those that have been transmitted */ 1096 while(i != chipidx) { 1097 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1098 if(r->bfe_mbuf != NULL) { 1099 ifp->if_opackets++; 1100 m_freem(r->bfe_mbuf); 1101 r->bfe_mbuf = NULL; 1102 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1103 } 1104 sc->bfe_tx_cnt--; 1105 BFE_INC(i, BFE_TX_LIST_CNT); 1106 } 1107 1108 if(i != sc->bfe_tx_cons) { 1109 /* we freed up some mbufs */ 1110 sc->bfe_tx_cons = i; 1111 ifp->if_flags &= ~IFF_OACTIVE; 1112 } 1113 if(sc->bfe_tx_cnt == 0) 1114 ifp->if_timer = 0; 1115 else 1116 ifp->if_timer = 5; 1117 } 1118 1119 /* Pass a received packet up the stack */ 1120 static void 1121 bfe_rxeof(struct bfe_softc *sc) 1122 { 1123 struct mbuf *m; 1124 struct ifnet *ifp; 1125 struct bfe_rxheader *rxheader; 1126 struct bfe_data *r; 1127 int cons; 1128 u_int32_t status, current, len, flags; 1129 1130 BFE_LOCK_ASSERT(sc); 1131 cons = sc->bfe_rx_cons; 1132 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1133 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1134 1135 ifp = sc->bfe_ifp; 1136 1137 while(current != cons) { 1138 r = &sc->bfe_rx_ring[cons]; 1139 m = r->bfe_mbuf; 1140 rxheader = mtod(m, struct bfe_rxheader*); 1141 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1142 len = rxheader->len; 1143 r->bfe_mbuf = NULL; 1144 1145 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1146 flags = rxheader->flags; 1147 1148 len -= ETHER_CRC_LEN; 1149 1150 /* flag an error and try again */ 1151 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1152 ifp->if_ierrors++; 1153 if (flags & BFE_RX_FLAG_SERR) 1154 ifp->if_collisions++; 1155 bfe_list_newbuf(sc, cons, m); 1156 BFE_INC(cons, BFE_RX_LIST_CNT); 1157 continue; 1158 } 1159 1160 /* Go past the rx header */ 1161 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1162 m_adj(m, BFE_RX_OFFSET); 1163 m->m_len = m->m_pkthdr.len = len; 1164 } else { 1165 bfe_list_newbuf(sc, cons, m); 1166 ifp->if_ierrors++; 1167 BFE_INC(cons, BFE_RX_LIST_CNT); 1168 continue; 1169 } 1170 1171 ifp->if_ipackets++; 1172 m->m_pkthdr.rcvif = ifp; 1173 BFE_UNLOCK(sc); 1174 (*ifp->if_input)(ifp, m); 1175 BFE_LOCK(sc); 1176 1177 BFE_INC(cons, BFE_RX_LIST_CNT); 1178 } 1179 sc->bfe_rx_cons = cons; 1180 } 1181 1182 static void 1183 bfe_intr(void *xsc) 1184 { 1185 struct bfe_softc *sc = xsc; 1186 struct ifnet *ifp; 1187 u_int32_t istat, imask, flag; 1188 1189 ifp = sc->bfe_ifp; 1190 1191 BFE_LOCK(sc); 1192 1193 istat = CSR_READ_4(sc, BFE_ISTAT); 1194 imask = CSR_READ_4(sc, BFE_IMASK); 1195 1196 /* 1197 * Defer unsolicited interrupts - This is necessary because setting the 1198 * chips interrupt mask register to 0 doesn't actually stop the 1199 * interrupts 1200 */ 1201 istat &= imask; 1202 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1203 CSR_READ_4(sc, BFE_ISTAT); 1204 1205 /* not expecting this interrupt, disregard it */ 1206 if(istat == 0) { 1207 BFE_UNLOCK(sc); 1208 return; 1209 } 1210 1211 if(istat & BFE_ISTAT_ERRORS) { 1212 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1213 if(flag & BFE_STAT_EMASK) 1214 ifp->if_oerrors++; 1215 1216 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1217 if(flag & BFE_RX_FLAG_ERRORS) 1218 ifp->if_ierrors++; 1219 1220 ifp->if_flags &= ~IFF_RUNNING; 1221 bfe_init_locked(sc); 1222 } 1223 1224 /* A packet was received */ 1225 if(istat & BFE_ISTAT_RX) 1226 bfe_rxeof(sc); 1227 1228 /* A packet was sent */ 1229 if(istat & BFE_ISTAT_TX) 1230 bfe_txeof(sc); 1231 1232 /* We have packets pending, fire them out */ 1233 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1234 bfe_start_locked(ifp); 1235 1236 BFE_UNLOCK(sc); 1237 } 1238 1239 static int 1240 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1241 { 1242 struct bfe_desc *d = NULL; 1243 struct bfe_data *r = NULL; 1244 struct mbuf *m; 1245 u_int32_t frag, cur, cnt = 0; 1246 int chainlen = 0; 1247 1248 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1249 return (ENOBUFS); 1250 1251 /* 1252 * Count the number of frags in this chain to see if 1253 * we need to m_defrag. Since the descriptor list is shared 1254 * by all packets, we'll m_defrag long chains so that they 1255 * do not use up the entire list, even if they would fit. 1256 */ 1257 for(m = m_head; m != NULL; m = m->m_next) 1258 chainlen++; 1259 1260 1261 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1262 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1263 m = m_defrag(m_head, M_DONTWAIT); 1264 if (m == NULL) 1265 return (ENOBUFS); 1266 m_head = m; 1267 } 1268 1269 /* 1270 * Start packing the mbufs in this chain into 1271 * the fragment pointers. Stop when we run out 1272 * of fragments or hit the end of the mbuf chain. 1273 */ 1274 m = m_head; 1275 cur = frag = *txidx; 1276 cnt = 0; 1277 1278 for(m = m_head; m != NULL; m = m->m_next) { 1279 if(m->m_len != 0) { 1280 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1281 return (ENOBUFS); 1282 1283 d = &sc->bfe_tx_list[cur]; 1284 r = &sc->bfe_tx_ring[cur]; 1285 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1286 /* always intterupt on completion */ 1287 d->bfe_ctrl |= BFE_DESC_IOC; 1288 if(cnt == 0) 1289 /* Set start of frame */ 1290 d->bfe_ctrl |= BFE_DESC_SOF; 1291 if(cur == BFE_TX_LIST_CNT - 1) 1292 /* 1293 * Tell the chip to wrap to the start of 1294 * the descriptor list 1295 */ 1296 d->bfe_ctrl |= BFE_DESC_EOT; 1297 1298 bus_dmamap_load(sc->bfe_tag, 1299 r->bfe_map, mtod(m, void*), m->m_len, 1300 bfe_dma_map_desc, d, 0); 1301 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1302 BUS_DMASYNC_PREREAD); 1303 1304 frag = cur; 1305 BFE_INC(cur, BFE_TX_LIST_CNT); 1306 cnt++; 1307 } 1308 } 1309 1310 if (m != NULL) 1311 return (ENOBUFS); 1312 1313 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1314 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1316 1317 *txidx = cur; 1318 sc->bfe_tx_cnt += cnt; 1319 return (0); 1320 } 1321 1322 /* 1323 * Set up to transmit a packet. 1324 */ 1325 static void 1326 bfe_start(struct ifnet *ifp) 1327 { 1328 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1329 bfe_start_locked(ifp); 1330 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1331 } 1332 1333 /* 1334 * Set up to transmit a packet. The softc is already locked. 1335 */ 1336 static void 1337 bfe_start_locked(struct ifnet *ifp) 1338 { 1339 struct bfe_softc *sc; 1340 struct mbuf *m_head = NULL; 1341 int idx, queued = 0; 1342 1343 sc = ifp->if_softc; 1344 idx = sc->bfe_tx_prod; 1345 1346 BFE_LOCK_ASSERT(sc); 1347 1348 /* 1349 * Not much point trying to send if the link is down 1350 * or we have nothing to send. 1351 */ 1352 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1353 return; 1354 1355 if (ifp->if_flags & IFF_OACTIVE) 1356 return; 1357 1358 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1359 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1360 if(m_head == NULL) 1361 break; 1362 1363 /* 1364 * Pack the data into the tx ring. If we dont have 1365 * enough room, let the chip drain the ring. 1366 */ 1367 if(bfe_encap(sc, m_head, &idx)) { 1368 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1369 ifp->if_flags |= IFF_OACTIVE; 1370 break; 1371 } 1372 1373 queued++; 1374 1375 /* 1376 * If there's a BPF listener, bounce a copy of this frame 1377 * to him. 1378 */ 1379 BPF_MTAP(ifp, m_head); 1380 } 1381 1382 if (queued) { 1383 sc->bfe_tx_prod = idx; 1384 /* Transmit - twice due to apparent hardware bug */ 1385 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1386 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1387 1388 /* 1389 * Set a timeout in case the chip goes out to lunch. 1390 */ 1391 ifp->if_timer = 5; 1392 } 1393 } 1394 1395 static void 1396 bfe_init(void *xsc) 1397 { 1398 BFE_LOCK((struct bfe_softc *)xsc); 1399 bfe_init_locked(xsc); 1400 BFE_UNLOCK((struct bfe_softc *)xsc); 1401 } 1402 1403 static void 1404 bfe_init_locked(void *xsc) 1405 { 1406 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1407 struct ifnet *ifp = sc->bfe_ifp; 1408 1409 BFE_LOCK_ASSERT(sc); 1410 1411 if (ifp->if_flags & IFF_RUNNING) 1412 return; 1413 1414 bfe_stop(sc); 1415 bfe_chip_reset(sc); 1416 1417 if (bfe_list_rx_init(sc) == ENOBUFS) { 1418 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1419 sc->bfe_unit); 1420 bfe_stop(sc); 1421 return; 1422 } 1423 1424 bfe_set_rx_mode(sc); 1425 1426 /* Enable the chip and core */ 1427 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1428 /* Enable interrupts */ 1429 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1430 1431 bfe_ifmedia_upd(ifp); 1432 ifp->if_flags |= IFF_RUNNING; 1433 ifp->if_flags &= ~IFF_OACTIVE; 1434 1435 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1436 } 1437 1438 /* 1439 * Set media options. 1440 */ 1441 static int 1442 bfe_ifmedia_upd(struct ifnet *ifp) 1443 { 1444 struct bfe_softc *sc; 1445 struct mii_data *mii; 1446 1447 sc = ifp->if_softc; 1448 1449 mii = device_get_softc(sc->bfe_miibus); 1450 sc->bfe_link = 0; 1451 if (mii->mii_instance) { 1452 struct mii_softc *miisc; 1453 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1454 miisc = LIST_NEXT(miisc, mii_list)) 1455 mii_phy_reset(miisc); 1456 } 1457 mii_mediachg(mii); 1458 1459 return (0); 1460 } 1461 1462 /* 1463 * Report current media status. 1464 */ 1465 static void 1466 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1467 { 1468 struct bfe_softc *sc = ifp->if_softc; 1469 struct mii_data *mii; 1470 1471 mii = device_get_softc(sc->bfe_miibus); 1472 mii_pollstat(mii); 1473 ifmr->ifm_active = mii->mii_media_active; 1474 ifmr->ifm_status = mii->mii_media_status; 1475 } 1476 1477 static int 1478 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1479 { 1480 struct bfe_softc *sc = ifp->if_softc; 1481 struct ifreq *ifr = (struct ifreq *) data; 1482 struct mii_data *mii; 1483 int error = 0; 1484 1485 switch(command) { 1486 case SIOCSIFFLAGS: 1487 BFE_LOCK(sc); 1488 if(ifp->if_flags & IFF_UP) 1489 if(ifp->if_flags & IFF_RUNNING) 1490 bfe_set_rx_mode(sc); 1491 else 1492 bfe_init_locked(sc); 1493 else if(ifp->if_flags & IFF_RUNNING) 1494 bfe_stop(sc); 1495 BFE_UNLOCK(sc); 1496 break; 1497 case SIOCADDMULTI: 1498 case SIOCDELMULTI: 1499 BFE_LOCK(sc); 1500 if(ifp->if_flags & IFF_RUNNING) 1501 bfe_set_rx_mode(sc); 1502 BFE_UNLOCK(sc); 1503 break; 1504 case SIOCGIFMEDIA: 1505 case SIOCSIFMEDIA: 1506 mii = device_get_softc(sc->bfe_miibus); 1507 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1508 command); 1509 break; 1510 default: 1511 error = ether_ioctl(ifp, command, data); 1512 break; 1513 } 1514 1515 return (error); 1516 } 1517 1518 static void 1519 bfe_watchdog(struct ifnet *ifp) 1520 { 1521 struct bfe_softc *sc; 1522 1523 sc = ifp->if_softc; 1524 1525 BFE_LOCK(sc); 1526 1527 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1528 1529 ifp->if_flags &= ~IFF_RUNNING; 1530 bfe_init_locked(sc); 1531 1532 ifp->if_oerrors++; 1533 1534 BFE_UNLOCK(sc); 1535 } 1536 1537 static void 1538 bfe_tick(void *xsc) 1539 { 1540 struct bfe_softc *sc = xsc; 1541 struct mii_data *mii; 1542 1543 if (sc == NULL) 1544 return; 1545 1546 BFE_LOCK(sc); 1547 1548 mii = device_get_softc(sc->bfe_miibus); 1549 1550 bfe_stats_update(sc); 1551 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1552 1553 if(sc->bfe_link) { 1554 BFE_UNLOCK(sc); 1555 return; 1556 } 1557 1558 mii_tick(mii); 1559 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1560 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1561 sc->bfe_link++; 1562 1563 BFE_UNLOCK(sc); 1564 } 1565 1566 /* 1567 * Stop the adapter and free any mbufs allocated to the 1568 * RX and TX lists. 1569 */ 1570 static void 1571 bfe_stop(struct bfe_softc *sc) 1572 { 1573 struct ifnet *ifp; 1574 1575 BFE_LOCK_ASSERT(sc); 1576 1577 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1578 1579 ifp = sc->bfe_ifp; 1580 1581 bfe_chip_halt(sc); 1582 bfe_tx_ring_free(sc); 1583 bfe_rx_ring_free(sc); 1584 1585 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1586 } 1587