1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include "miidevs.h" 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <dev/bfe/if_bfereg.h> 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, ether, 1, 1, 1); 74 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 75 76 /* "controller miibus0" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 80 81 static struct bfe_type bfe_devs[] = { 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 83 "Broadcom BCM4401 Fast Ethernet" }, 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 85 "Broadcom BCM4401-B0 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe (device_t); 90 static int bfe_attach (device_t); 91 static int bfe_detach (device_t); 92 static void bfe_release_resources (struct bfe_softc *); 93 static void bfe_intr (void *); 94 static void bfe_start (struct ifnet *); 95 static void bfe_start_locked (struct ifnet *); 96 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97 static void bfe_init (void *); 98 static void bfe_init_locked (void *); 99 static void bfe_stop (struct bfe_softc *); 100 static void bfe_watchdog (struct ifnet *); 101 static void bfe_shutdown (device_t); 102 static void bfe_tick (void *); 103 static void bfe_txeof (struct bfe_softc *); 104 static void bfe_rxeof (struct bfe_softc *); 105 static void bfe_set_rx_mode (struct bfe_softc *); 106 static int bfe_list_rx_init (struct bfe_softc *); 107 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free (struct bfe_softc *); 109 110 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111 static int bfe_ifmedia_upd (struct ifnet *); 112 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg (device_t, int, int); 114 static int bfe_miibus_writereg (device_t, int, int, int); 115 static void bfe_miibus_statchg (device_t); 116 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118 static void bfe_get_config (struct bfe_softc *sc); 119 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120 static void bfe_stats_update (struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124 static int bfe_resetphy (struct bfe_softc *); 125 static int bfe_setupphy (struct bfe_softc *); 126 static void bfe_chip_reset (struct bfe_softc *); 127 static void bfe_chip_halt (struct bfe_softc *); 128 static void bfe_core_reset (struct bfe_softc *); 129 static void bfe_core_disable (struct bfe_softc *); 130 static int bfe_dma_alloc (device_t); 131 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 148 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 149 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t bfe_driver = { 155 "bfe", 156 bfe_methods, 157 sizeof(struct bfe_softc) 158 }; 159 160 static devclass_t bfe_devclass; 161 162 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 163 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 164 165 /* 166 * Probe for a Broadcom 4401 chip. 167 */ 168 static int 169 bfe_probe(device_t dev) 170 { 171 struct bfe_type *t; 172 struct bfe_softc *sc; 173 174 t = bfe_devs; 175 176 sc = device_get_softc(dev); 177 bzero(sc, sizeof(struct bfe_softc)); 178 sc->bfe_unit = device_get_unit(dev); 179 sc->bfe_dev = dev; 180 181 while(t->bfe_name != NULL) { 182 if ((pci_get_vendor(dev) == t->bfe_vid) && 183 (pci_get_device(dev) == t->bfe_did)) { 184 device_set_desc_copy(dev, t->bfe_name); 185 return (BUS_PROBE_DEFAULT); 186 } 187 t++; 188 } 189 190 return (ENXIO); 191 } 192 193 static int 194 bfe_dma_alloc(device_t dev) 195 { 196 struct bfe_softc *sc; 197 int error, i; 198 199 sc = device_get_softc(dev); 200 201 /* parent tag */ 202 error = bus_dma_tag_create(NULL, /* parent */ 203 PAGE_SIZE, 0, /* alignment, boundary */ 204 BUS_SPACE_MAXADDR, /* lowaddr */ 205 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 206 NULL, NULL, /* filter, filterarg */ 207 MAXBSIZE, /* maxsize */ 208 BUS_SPACE_UNRESTRICTED, /* num of segments */ 209 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 210 BUS_DMA_ALLOCNOW, /* flags */ 211 NULL, NULL, /* lockfunc, lockarg */ 212 &sc->bfe_parent_tag); 213 214 /* tag for TX ring */ 215 error = bus_dma_tag_create(sc->bfe_parent_tag, 216 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 217 BUS_SPACE_MAXADDR, 218 BUS_SPACE_MAXADDR, 219 NULL, NULL, 220 BFE_TX_LIST_SIZE, 221 1, 222 BUS_SPACE_MAXSIZE_32BIT, 223 0, 224 NULL, NULL, 225 &sc->bfe_tx_tag); 226 227 if (error) { 228 device_printf(dev, "could not allocate dma tag\n"); 229 return (ENOMEM); 230 } 231 232 /* tag for RX ring */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, 234 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 235 BUS_SPACE_MAXADDR, 236 BUS_SPACE_MAXADDR, 237 NULL, NULL, 238 BFE_RX_LIST_SIZE, 239 1, 240 BUS_SPACE_MAXSIZE_32BIT, 241 0, 242 NULL, NULL, 243 &sc->bfe_rx_tag); 244 245 if (error) { 246 device_printf(dev, "could not allocate dma tag\n"); 247 return (ENOMEM); 248 } 249 250 /* tag for mbufs */ 251 error = bus_dma_tag_create(sc->bfe_parent_tag, 252 ETHER_ALIGN, 0, 253 BUS_SPACE_MAXADDR, 254 BUS_SPACE_MAXADDR, 255 NULL, NULL, 256 MCLBYTES, 257 1, 258 BUS_SPACE_MAXSIZE_32BIT, 259 0, 260 NULL, NULL, 261 &sc->bfe_tag); 262 263 if (error) { 264 device_printf(dev, "could not allocate dma tag\n"); 265 return (ENOMEM); 266 } 267 268 /* pre allocate dmamaps for RX list */ 269 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 270 error = bus_dmamap_create(sc->bfe_tag, 0, 271 &sc->bfe_rx_ring[i].bfe_map); 272 if (error) { 273 device_printf(dev, "cannot create DMA map for RX\n"); 274 return (ENOMEM); 275 } 276 } 277 278 /* pre allocate dmamaps for TX list */ 279 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 280 error = bus_dmamap_create(sc->bfe_tag, 0, 281 &sc->bfe_tx_ring[i].bfe_map); 282 if (error) { 283 device_printf(dev, "cannot create DMA map for TX\n"); 284 return (ENOMEM); 285 } 286 } 287 288 /* Alloc dma for rx ring */ 289 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 290 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 291 292 if(error) 293 return (ENOMEM); 294 295 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 296 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 297 sc->bfe_rx_list, sizeof(struct bfe_desc), 298 bfe_dma_map, &sc->bfe_rx_dma, 0); 299 300 if(error) 301 return (ENOMEM); 302 303 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 304 305 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 306 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 307 if (error) 308 return (ENOMEM); 309 310 311 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 312 sc->bfe_tx_list, sizeof(struct bfe_desc), 313 bfe_dma_map, &sc->bfe_tx_dma, 0); 314 if(error) 315 return (ENOMEM); 316 317 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 318 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 319 320 return (0); 321 } 322 323 static int 324 bfe_attach(device_t dev) 325 { 326 struct ifnet *ifp; 327 struct bfe_softc *sc; 328 int unit, error = 0, rid; 329 330 sc = device_get_softc(dev); 331 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 332 MTX_DEF); 333 334 unit = device_get_unit(dev); 335 sc->bfe_dev = dev; 336 sc->bfe_unit = unit; 337 338 /* 339 * Handle power management nonsense. 340 */ 341 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 342 u_int32_t membase, irq; 343 344 /* Save important PCI config data. */ 345 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 346 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 347 348 /* Reset the power state. */ 349 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 350 sc->bfe_unit, pci_get_powerstate(dev)); 351 352 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 353 354 /* Restore PCI config data. */ 355 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 356 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 357 } 358 359 /* 360 * Map control/status registers. 361 */ 362 pci_enable_busmaster(dev); 363 364 rid = BFE_PCI_MEMLO; 365 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 366 RF_ACTIVE); 367 if (sc->bfe_res == NULL) { 368 printf ("bfe%d: couldn't map memory\n", unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 374 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 375 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 376 377 /* Allocate interrupt */ 378 rid = 0; 379 380 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 381 RF_SHAREABLE | RF_ACTIVE); 382 if (sc->bfe_irq == NULL) { 383 printf("bfe%d: couldn't map interrupt\n", unit); 384 error = ENXIO; 385 goto fail; 386 } 387 388 if (bfe_dma_alloc(dev)) { 389 printf("bfe%d: failed to allocate DMA resources\n", 390 sc->bfe_unit); 391 bfe_release_resources(sc); 392 error = ENXIO; 393 goto fail; 394 } 395 396 /* Set up ifnet structure */ 397 ifp = &sc->arpcom.ac_if; 398 ifp->if_softc = sc; 399 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 401 ifp->if_ioctl = bfe_ioctl; 402 ifp->if_start = bfe_start; 403 ifp->if_watchdog = bfe_watchdog; 404 ifp->if_init = bfe_init; 405 ifp->if_mtu = ETHERMTU; 406 ifp->if_baudrate = 100000000; 407 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 408 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 409 IFQ_SET_READY(&ifp->if_snd); 410 411 bfe_get_config(sc); 412 413 /* Reset the chip and turn on the PHY */ 414 BFE_LOCK(sc); 415 bfe_chip_reset(sc); 416 BFE_UNLOCK(sc); 417 418 if (mii_phy_probe(dev, &sc->bfe_miibus, 419 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 420 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 421 error = ENXIO; 422 goto fail; 423 } 424 425 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 426 callout_handle_init(&sc->bfe_stat_ch); 427 428 /* 429 * Tell the upper layer(s) we support long frames. 430 */ 431 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 432 ifp->if_capabilities |= IFCAP_VLAN_MTU; 433 ifp->if_capenable |= IFCAP_VLAN_MTU; 434 435 /* 436 * Hook interrupt last to avoid having to lock softc 437 */ 438 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 439 bfe_intr, sc, &sc->bfe_intrhand); 440 441 if (error) { 442 bfe_release_resources(sc); 443 printf("bfe%d: couldn't set up irq\n", unit); 444 goto fail; 445 } 446 fail: 447 if(error) 448 bfe_release_resources(sc); 449 return (error); 450 } 451 452 static int 453 bfe_detach(device_t dev) 454 { 455 struct bfe_softc *sc; 456 struct ifnet *ifp; 457 458 sc = device_get_softc(dev); 459 460 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 461 BFE_LOCK(sc); 462 463 ifp = &sc->arpcom.ac_if; 464 465 if (device_is_attached(dev)) { 466 bfe_stop(sc); 467 ether_ifdetach(ifp); 468 } 469 470 bfe_chip_reset(sc); 471 472 bus_generic_detach(dev); 473 if(sc->bfe_miibus != NULL) 474 device_delete_child(dev, sc->bfe_miibus); 475 476 bfe_release_resources(sc); 477 BFE_UNLOCK(sc); 478 mtx_destroy(&sc->bfe_mtx); 479 480 return (0); 481 } 482 483 /* 484 * Stop all chip I/O so that the kernel's probe routines don't 485 * get confused by errant DMAs when rebooting. 486 */ 487 static void 488 bfe_shutdown(device_t dev) 489 { 490 struct bfe_softc *sc; 491 492 sc = device_get_softc(dev); 493 BFE_LOCK(sc); 494 bfe_stop(sc); 495 496 BFE_UNLOCK(sc); 497 return; 498 } 499 500 static int 501 bfe_miibus_readreg(device_t dev, int phy, int reg) 502 { 503 struct bfe_softc *sc; 504 u_int32_t ret; 505 506 sc = device_get_softc(dev); 507 if(phy != sc->bfe_phyaddr) 508 return (0); 509 bfe_readphy(sc, reg, &ret); 510 511 return (ret); 512 } 513 514 static int 515 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 516 { 517 struct bfe_softc *sc; 518 519 sc = device_get_softc(dev); 520 if(phy != sc->bfe_phyaddr) 521 return (0); 522 bfe_writephy(sc, reg, val); 523 524 return (0); 525 } 526 527 static void 528 bfe_miibus_statchg(device_t dev) 529 { 530 return; 531 } 532 533 static void 534 bfe_tx_ring_free(struct bfe_softc *sc) 535 { 536 int i; 537 538 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 539 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 540 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 541 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 542 bus_dmamap_unload(sc->bfe_tag, 543 sc->bfe_tx_ring[i].bfe_map); 544 } 545 } 546 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 547 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 548 } 549 550 static void 551 bfe_rx_ring_free(struct bfe_softc *sc) 552 { 553 int i; 554 555 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 556 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 557 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 558 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 559 bus_dmamap_unload(sc->bfe_tag, 560 sc->bfe_rx_ring[i].bfe_map); 561 } 562 } 563 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 564 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 565 } 566 567 static int 568 bfe_list_rx_init(struct bfe_softc *sc) 569 { 570 int i; 571 572 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 573 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 574 return (ENOBUFS); 575 } 576 577 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 578 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 579 580 sc->bfe_rx_cons = 0; 581 582 return (0); 583 } 584 585 static int 586 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 587 { 588 struct bfe_rxheader *rx_header; 589 struct bfe_desc *d; 590 struct bfe_data *r; 591 u_int32_t ctrl; 592 593 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 594 return (EINVAL); 595 596 if(m == NULL) { 597 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 598 if(m == NULL) 599 return (ENOBUFS); 600 m->m_len = m->m_pkthdr.len = MCLBYTES; 601 } 602 else 603 m->m_data = m->m_ext.ext_buf; 604 605 rx_header = mtod(m, struct bfe_rxheader *); 606 rx_header->len = 0; 607 rx_header->flags = 0; 608 609 /* Map the mbuf into DMA */ 610 sc->bfe_rx_cnt = c; 611 d = &sc->bfe_rx_list[c]; 612 r = &sc->bfe_rx_ring[c]; 613 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 614 MCLBYTES, bfe_dma_map_desc, d, 0); 615 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 616 617 ctrl = ETHER_MAX_LEN + 32; 618 619 if(c == BFE_RX_LIST_CNT - 1) 620 ctrl |= BFE_DESC_EOT; 621 622 d->bfe_ctrl = ctrl; 623 r->bfe_mbuf = m; 624 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 625 return (0); 626 } 627 628 static void 629 bfe_get_config(struct bfe_softc *sc) 630 { 631 u_int8_t eeprom[128]; 632 633 bfe_read_eeprom(sc, eeprom); 634 635 sc->arpcom.ac_enaddr[0] = eeprom[79]; 636 sc->arpcom.ac_enaddr[1] = eeprom[78]; 637 sc->arpcom.ac_enaddr[2] = eeprom[81]; 638 sc->arpcom.ac_enaddr[3] = eeprom[80]; 639 sc->arpcom.ac_enaddr[4] = eeprom[83]; 640 sc->arpcom.ac_enaddr[5] = eeprom[82]; 641 642 sc->bfe_phyaddr = eeprom[90] & 0x1f; 643 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 644 645 sc->bfe_core_unit = 0; 646 sc->bfe_dma_offset = BFE_PCI_DMA; 647 } 648 649 static void 650 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 651 { 652 u_int32_t bar_orig, pci_rev, val; 653 654 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 655 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 656 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 657 658 val = CSR_READ_4(sc, BFE_SBINTVEC); 659 val |= cores; 660 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 661 662 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 663 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 664 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 665 666 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 667 } 668 669 static void 670 bfe_clear_stats(struct bfe_softc *sc) 671 { 672 u_long reg; 673 674 BFE_LOCK_ASSERT(sc); 675 676 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 677 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 678 CSR_READ_4(sc, reg); 679 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 680 CSR_READ_4(sc, reg); 681 } 682 683 static int 684 bfe_resetphy(struct bfe_softc *sc) 685 { 686 u_int32_t val; 687 688 bfe_writephy(sc, 0, BMCR_RESET); 689 DELAY(100); 690 bfe_readphy(sc, 0, &val); 691 if (val & BMCR_RESET) { 692 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 693 return (ENXIO); 694 } 695 return (0); 696 } 697 698 static void 699 bfe_chip_halt(struct bfe_softc *sc) 700 { 701 BFE_LOCK_ASSERT(sc); 702 /* disable interrupts - not that it actually does..*/ 703 CSR_WRITE_4(sc, BFE_IMASK, 0); 704 CSR_READ_4(sc, BFE_IMASK); 705 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 708 709 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 DELAY(10); 712 } 713 714 static void 715 bfe_chip_reset(struct bfe_softc *sc) 716 { 717 u_int32_t val; 718 719 BFE_LOCK_ASSERT(sc); 720 721 /* Set the interrupt vector for the enet core */ 722 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 723 724 /* is core up? */ 725 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 726 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 727 if (val == BFE_CLOCK) { 728 /* It is, so shut it down */ 729 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 730 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 731 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 732 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 733 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 734 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 735 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 736 100, 0); 737 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 738 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 739 } 740 741 bfe_core_reset(sc); 742 bfe_clear_stats(sc); 743 744 /* 745 * We want the phy registers to be accessible even when 746 * the driver is "downed" so initialize MDC preamble, frequency, 747 * and whether internal or external phy here. 748 */ 749 750 /* 4402 has 62.5Mhz SB clock and internal phy */ 751 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 752 753 /* Internal or external PHY? */ 754 val = CSR_READ_4(sc, BFE_DEVCTRL); 755 if(!(val & BFE_IPP)) 756 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 757 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 758 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 759 DELAY(100); 760 } 761 762 /* Enable CRC32 generation and set proper LED modes */ 763 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 764 765 /* Reset or clear powerdown control bit */ 766 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 767 768 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 769 BFE_LAZY_FC_MASK)); 770 771 /* 772 * We don't want lazy interrupts, so just send them at 773 * the end of a frame, please 774 */ 775 BFE_OR(sc, BFE_RCV_LAZY, 0); 776 777 /* Set max lengths, accounting for VLAN tags */ 778 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 779 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 780 781 /* Set watermark XXX - magic */ 782 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 783 784 /* 785 * Initialise DMA channels 786 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 787 */ 788 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 789 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 790 791 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 792 BFE_RX_CTRL_ENABLE); 793 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 794 795 bfe_resetphy(sc); 796 bfe_setupphy(sc); 797 } 798 799 static void 800 bfe_core_disable(struct bfe_softc *sc) 801 { 802 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 803 return; 804 805 /* 806 * Set reject, wait for it set, then wait for the core to stop 807 * being busy, then set reset and reject and enable the clocks. 808 */ 809 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 810 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 811 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 813 BFE_RESET)); 814 CSR_READ_4(sc, BFE_SBTMSLOW); 815 DELAY(10); 816 /* Leave reset and reject set */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 818 DELAY(10); 819 } 820 821 static void 822 bfe_core_reset(struct bfe_softc *sc) 823 { 824 u_int32_t val; 825 826 /* Disable the core */ 827 bfe_core_disable(sc); 828 829 /* and bring it back up */ 830 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 831 CSR_READ_4(sc, BFE_SBTMSLOW); 832 DELAY(10); 833 834 /* Chip bug, clear SERR, IB and TO if they are set. */ 835 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 836 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 837 val = CSR_READ_4(sc, BFE_SBIMSTATE); 838 if (val & (BFE_IBE | BFE_TO)) 839 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 840 841 /* Clear reset and allow it to move through the core */ 842 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 843 CSR_READ_4(sc, BFE_SBTMSLOW); 844 DELAY(10); 845 846 /* Leave the clock set */ 847 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 848 CSR_READ_4(sc, BFE_SBTMSLOW); 849 DELAY(10); 850 } 851 852 static void 853 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 854 { 855 u_int32_t val; 856 857 val = ((u_int32_t) data[2]) << 24; 858 val |= ((u_int32_t) data[3]) << 16; 859 val |= ((u_int32_t) data[4]) << 8; 860 val |= ((u_int32_t) data[5]); 861 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 862 val = (BFE_CAM_HI_VALID | 863 (((u_int32_t) data[0]) << 8) | 864 (((u_int32_t) data[1]))); 865 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 866 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 867 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 868 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 869 } 870 871 static void 872 bfe_set_rx_mode(struct bfe_softc *sc) 873 { 874 struct ifnet *ifp = &sc->arpcom.ac_if; 875 struct ifmultiaddr *ifma; 876 u_int32_t val; 877 int i = 0; 878 879 val = CSR_READ_4(sc, BFE_RXCONF); 880 881 if (ifp->if_flags & IFF_PROMISC) 882 val |= BFE_RXCONF_PROMISC; 883 else 884 val &= ~BFE_RXCONF_PROMISC; 885 886 if (ifp->if_flags & IFF_BROADCAST) 887 val &= ~BFE_RXCONF_DBCAST; 888 else 889 val |= BFE_RXCONF_DBCAST; 890 891 892 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 893 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 894 895 if (ifp->if_flags & IFF_ALLMULTI) 896 val |= BFE_RXCONF_ALLMULTI; 897 else { 898 val &= ~BFE_RXCONF_ALLMULTI; 899 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 900 if (ifma->ifma_addr->sa_family != AF_LINK) 901 continue; 902 bfe_cam_write(sc, 903 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 904 } 905 } 906 907 CSR_WRITE_4(sc, BFE_RXCONF, val); 908 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 909 } 910 911 static void 912 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 913 { 914 u_int32_t *ptr; 915 916 ptr = arg; 917 *ptr = segs->ds_addr; 918 } 919 920 static void 921 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 922 { 923 struct bfe_desc *d; 924 925 d = arg; 926 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 927 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 928 } 929 930 static void 931 bfe_release_resources(struct bfe_softc *sc) 932 { 933 device_t dev; 934 int i; 935 936 dev = sc->bfe_dev; 937 938 if (sc->bfe_vpd_prodname != NULL) 939 free(sc->bfe_vpd_prodname, M_DEVBUF); 940 941 if (sc->bfe_vpd_readonly != NULL) 942 free(sc->bfe_vpd_readonly, M_DEVBUF); 943 944 if (sc->bfe_intrhand != NULL) 945 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 946 947 if (sc->bfe_irq != NULL) 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 949 950 if (sc->bfe_res != NULL) 951 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 952 953 if(sc->bfe_tx_tag != NULL) { 954 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 955 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 956 sc->bfe_tx_map); 957 bus_dma_tag_destroy(sc->bfe_tx_tag); 958 sc->bfe_tx_tag = NULL; 959 } 960 961 if(sc->bfe_rx_tag != NULL) { 962 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 963 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 964 sc->bfe_rx_map); 965 bus_dma_tag_destroy(sc->bfe_rx_tag); 966 sc->bfe_rx_tag = NULL; 967 } 968 969 if(sc->bfe_tag != NULL) { 970 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 971 bus_dmamap_destroy(sc->bfe_tag, 972 sc->bfe_tx_ring[i].bfe_map); 973 } 974 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 975 bus_dmamap_destroy(sc->bfe_tag, 976 sc->bfe_rx_ring[i].bfe_map); 977 } 978 bus_dma_tag_destroy(sc->bfe_tag); 979 sc->bfe_tag = NULL; 980 } 981 982 if(sc->bfe_parent_tag != NULL) 983 bus_dma_tag_destroy(sc->bfe_parent_tag); 984 985 return; 986 } 987 988 static void 989 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 990 { 991 long i; 992 u_int16_t *ptr = (u_int16_t *)data; 993 994 for(i = 0; i < 128; i += 2) 995 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 996 } 997 998 static int 999 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1000 u_long timeout, const int clear) 1001 { 1002 u_long i; 1003 1004 for (i = 0; i < timeout; i++) { 1005 u_int32_t val = CSR_READ_4(sc, reg); 1006 1007 if (clear && !(val & bit)) 1008 break; 1009 if (!clear && (val & bit)) 1010 break; 1011 DELAY(10); 1012 } 1013 if (i == timeout) { 1014 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1015 "%x to %s.\n", sc->bfe_unit, bit, reg, 1016 (clear ? "clear" : "set")); 1017 return (-1); 1018 } 1019 return (0); 1020 } 1021 1022 static int 1023 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1024 { 1025 int err; 1026 1027 /* Clear MII ISR */ 1028 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1029 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1030 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1031 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1032 (reg << BFE_MDIO_RA_SHIFT) | 1033 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1034 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1035 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1036 1037 return (err); 1038 } 1039 1040 static int 1041 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1042 { 1043 int status; 1044 1045 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1046 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1047 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1048 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1049 (reg << BFE_MDIO_RA_SHIFT) | 1050 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1051 (val & BFE_MDIO_DATA_DATA))); 1052 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1053 1054 return (status); 1055 } 1056 1057 /* 1058 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1059 * twice 1060 */ 1061 static int 1062 bfe_setupphy(struct bfe_softc *sc) 1063 { 1064 u_int32_t val; 1065 1066 /* Enable activity LED */ 1067 bfe_readphy(sc, 26, &val); 1068 bfe_writephy(sc, 26, val & 0x7fff); 1069 bfe_readphy(sc, 26, &val); 1070 1071 /* Enable traffic meter LED mode */ 1072 bfe_readphy(sc, 27, &val); 1073 bfe_writephy(sc, 27, val | (1 << 6)); 1074 1075 return (0); 1076 } 1077 1078 static void 1079 bfe_stats_update(struct bfe_softc *sc) 1080 { 1081 u_long reg; 1082 u_int32_t *val; 1083 1084 val = &sc->bfe_hwstats.tx_good_octets; 1085 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1086 *val++ += CSR_READ_4(sc, reg); 1087 } 1088 val = &sc->bfe_hwstats.rx_good_octets; 1089 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1090 *val++ += CSR_READ_4(sc, reg); 1091 } 1092 } 1093 1094 static void 1095 bfe_txeof(struct bfe_softc *sc) 1096 { 1097 struct ifnet *ifp; 1098 int i, chipidx; 1099 1100 BFE_LOCK_ASSERT(sc); 1101 1102 ifp = &sc->arpcom.ac_if; 1103 1104 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1105 chipidx /= sizeof(struct bfe_desc); 1106 1107 i = sc->bfe_tx_cons; 1108 /* Go through the mbufs and free those that have been transmitted */ 1109 while(i != chipidx) { 1110 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1111 if(r->bfe_mbuf != NULL) { 1112 ifp->if_opackets++; 1113 m_freem(r->bfe_mbuf); 1114 r->bfe_mbuf = NULL; 1115 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1116 } 1117 sc->bfe_tx_cnt--; 1118 BFE_INC(i, BFE_TX_LIST_CNT); 1119 } 1120 1121 if(i != sc->bfe_tx_cons) { 1122 /* we freed up some mbufs */ 1123 sc->bfe_tx_cons = i; 1124 ifp->if_flags &= ~IFF_OACTIVE; 1125 } 1126 if(sc->bfe_tx_cnt == 0) 1127 ifp->if_timer = 0; 1128 else 1129 ifp->if_timer = 5; 1130 } 1131 1132 /* Pass a received packet up the stack */ 1133 static void 1134 bfe_rxeof(struct bfe_softc *sc) 1135 { 1136 struct mbuf *m; 1137 struct ifnet *ifp; 1138 struct bfe_rxheader *rxheader; 1139 struct bfe_data *r; 1140 int cons; 1141 u_int32_t status, current, len, flags; 1142 1143 BFE_LOCK_ASSERT(sc); 1144 cons = sc->bfe_rx_cons; 1145 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1146 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1147 1148 ifp = &sc->arpcom.ac_if; 1149 1150 while(current != cons) { 1151 r = &sc->bfe_rx_ring[cons]; 1152 m = r->bfe_mbuf; 1153 rxheader = mtod(m, struct bfe_rxheader*); 1154 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1155 len = rxheader->len; 1156 r->bfe_mbuf = NULL; 1157 1158 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1159 flags = rxheader->flags; 1160 1161 len -= ETHER_CRC_LEN; 1162 1163 /* flag an error and try again */ 1164 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1165 ifp->if_ierrors++; 1166 if (flags & BFE_RX_FLAG_SERR) 1167 ifp->if_collisions++; 1168 bfe_list_newbuf(sc, cons, m); 1169 BFE_INC(cons, BFE_RX_LIST_CNT); 1170 continue; 1171 } 1172 1173 /* Go past the rx header */ 1174 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1175 m_adj(m, BFE_RX_OFFSET); 1176 m->m_len = m->m_pkthdr.len = len; 1177 } else { 1178 bfe_list_newbuf(sc, cons, m); 1179 ifp->if_ierrors++; 1180 BFE_INC(cons, BFE_RX_LIST_CNT); 1181 continue; 1182 } 1183 1184 ifp->if_ipackets++; 1185 m->m_pkthdr.rcvif = ifp; 1186 BFE_UNLOCK(sc); 1187 (*ifp->if_input)(ifp, m); 1188 BFE_LOCK(sc); 1189 1190 BFE_INC(cons, BFE_RX_LIST_CNT); 1191 } 1192 sc->bfe_rx_cons = cons; 1193 } 1194 1195 static void 1196 bfe_intr(void *xsc) 1197 { 1198 struct bfe_softc *sc = xsc; 1199 struct ifnet *ifp; 1200 u_int32_t istat, imask, flag; 1201 1202 ifp = &sc->arpcom.ac_if; 1203 1204 BFE_LOCK(sc); 1205 1206 istat = CSR_READ_4(sc, BFE_ISTAT); 1207 imask = CSR_READ_4(sc, BFE_IMASK); 1208 1209 /* 1210 * Defer unsolicited interrupts - This is necessary because setting the 1211 * chips interrupt mask register to 0 doesn't actually stop the 1212 * interrupts 1213 */ 1214 istat &= imask; 1215 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1216 CSR_READ_4(sc, BFE_ISTAT); 1217 1218 /* not expecting this interrupt, disregard it */ 1219 if(istat == 0) { 1220 BFE_UNLOCK(sc); 1221 return; 1222 } 1223 1224 if(istat & BFE_ISTAT_ERRORS) { 1225 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1226 if(flag & BFE_STAT_EMASK) 1227 ifp->if_oerrors++; 1228 1229 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1230 if(flag & BFE_RX_FLAG_ERRORS) 1231 ifp->if_ierrors++; 1232 1233 ifp->if_flags &= ~IFF_RUNNING; 1234 bfe_init_locked(sc); 1235 } 1236 1237 /* A packet was received */ 1238 if(istat & BFE_ISTAT_RX) 1239 bfe_rxeof(sc); 1240 1241 /* A packet was sent */ 1242 if(istat & BFE_ISTAT_TX) 1243 bfe_txeof(sc); 1244 1245 /* We have packets pending, fire them out */ 1246 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1247 bfe_start_locked(ifp); 1248 1249 BFE_UNLOCK(sc); 1250 } 1251 1252 static int 1253 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1254 { 1255 struct bfe_desc *d = NULL; 1256 struct bfe_data *r = NULL; 1257 struct mbuf *m; 1258 u_int32_t frag, cur, cnt = 0; 1259 int chainlen = 0; 1260 1261 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1262 return (ENOBUFS); 1263 1264 /* 1265 * Count the number of frags in this chain to see if 1266 * we need to m_defrag. Since the descriptor list is shared 1267 * by all packets, we'll m_defrag long chains so that they 1268 * do not use up the entire list, even if they would fit. 1269 */ 1270 for(m = m_head; m != NULL; m = m->m_next) 1271 chainlen++; 1272 1273 1274 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1275 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1276 m = m_defrag(m_head, M_DONTWAIT); 1277 if (m == NULL) 1278 return (ENOBUFS); 1279 m_head = m; 1280 } 1281 1282 /* 1283 * Start packing the mbufs in this chain into 1284 * the fragment pointers. Stop when we run out 1285 * of fragments or hit the end of the mbuf chain. 1286 */ 1287 m = m_head; 1288 cur = frag = *txidx; 1289 cnt = 0; 1290 1291 for(m = m_head; m != NULL; m = m->m_next) { 1292 if(m->m_len != 0) { 1293 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1294 return (ENOBUFS); 1295 1296 d = &sc->bfe_tx_list[cur]; 1297 r = &sc->bfe_tx_ring[cur]; 1298 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1299 /* always intterupt on completion */ 1300 d->bfe_ctrl |= BFE_DESC_IOC; 1301 if(cnt == 0) 1302 /* Set start of frame */ 1303 d->bfe_ctrl |= BFE_DESC_SOF; 1304 if(cur == BFE_TX_LIST_CNT - 1) 1305 /* 1306 * Tell the chip to wrap to the start of 1307 * the descriptor list 1308 */ 1309 d->bfe_ctrl |= BFE_DESC_EOT; 1310 1311 bus_dmamap_load(sc->bfe_tag, 1312 r->bfe_map, mtod(m, void*), m->m_len, 1313 bfe_dma_map_desc, d, 0); 1314 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1315 BUS_DMASYNC_PREREAD); 1316 1317 frag = cur; 1318 BFE_INC(cur, BFE_TX_LIST_CNT); 1319 cnt++; 1320 } 1321 } 1322 1323 if (m != NULL) 1324 return (ENOBUFS); 1325 1326 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1327 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1328 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1329 1330 *txidx = cur; 1331 sc->bfe_tx_cnt += cnt; 1332 return (0); 1333 } 1334 1335 /* 1336 * Set up to transmit a packet. 1337 */ 1338 static void 1339 bfe_start(struct ifnet *ifp) 1340 { 1341 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1342 bfe_start_locked(ifp); 1343 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1344 } 1345 1346 /* 1347 * Set up to transmit a packet. The softc is already locked. 1348 */ 1349 static void 1350 bfe_start_locked(struct ifnet *ifp) 1351 { 1352 struct bfe_softc *sc; 1353 struct mbuf *m_head = NULL; 1354 int idx, queued = 0; 1355 1356 sc = ifp->if_softc; 1357 idx = sc->bfe_tx_prod; 1358 1359 BFE_LOCK_ASSERT(sc); 1360 1361 /* 1362 * Not much point trying to send if the link is down 1363 * or we have nothing to send. 1364 */ 1365 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1366 return; 1367 1368 if (ifp->if_flags & IFF_OACTIVE) 1369 return; 1370 1371 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1372 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1373 if(m_head == NULL) 1374 break; 1375 1376 /* 1377 * Pack the data into the tx ring. If we dont have 1378 * enough room, let the chip drain the ring. 1379 */ 1380 if(bfe_encap(sc, m_head, &idx)) { 1381 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1382 ifp->if_flags |= IFF_OACTIVE; 1383 break; 1384 } 1385 1386 queued++; 1387 1388 /* 1389 * If there's a BPF listener, bounce a copy of this frame 1390 * to him. 1391 */ 1392 BPF_MTAP(ifp, m_head); 1393 } 1394 1395 if (queued) { 1396 sc->bfe_tx_prod = idx; 1397 /* Transmit - twice due to apparent hardware bug */ 1398 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1399 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1400 1401 /* 1402 * Set a timeout in case the chip goes out to lunch. 1403 */ 1404 ifp->if_timer = 5; 1405 } 1406 } 1407 1408 static void 1409 bfe_init(void *xsc) 1410 { 1411 BFE_LOCK((struct bfe_softc *)xsc); 1412 bfe_init_locked(xsc); 1413 BFE_UNLOCK((struct bfe_softc *)xsc); 1414 } 1415 1416 static void 1417 bfe_init_locked(void *xsc) 1418 { 1419 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1420 struct ifnet *ifp = &sc->arpcom.ac_if; 1421 1422 BFE_LOCK_ASSERT(sc); 1423 1424 if (ifp->if_flags & IFF_RUNNING) 1425 return; 1426 1427 bfe_stop(sc); 1428 bfe_chip_reset(sc); 1429 1430 if (bfe_list_rx_init(sc) == ENOBUFS) { 1431 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1432 sc->bfe_unit); 1433 bfe_stop(sc); 1434 return; 1435 } 1436 1437 bfe_set_rx_mode(sc); 1438 1439 /* Enable the chip and core */ 1440 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1441 /* Enable interrupts */ 1442 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1443 1444 bfe_ifmedia_upd(ifp); 1445 ifp->if_flags |= IFF_RUNNING; 1446 ifp->if_flags &= ~IFF_OACTIVE; 1447 1448 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1449 } 1450 1451 /* 1452 * Set media options. 1453 */ 1454 static int 1455 bfe_ifmedia_upd(struct ifnet *ifp) 1456 { 1457 struct bfe_softc *sc; 1458 struct mii_data *mii; 1459 1460 sc = ifp->if_softc; 1461 1462 mii = device_get_softc(sc->bfe_miibus); 1463 sc->bfe_link = 0; 1464 if (mii->mii_instance) { 1465 struct mii_softc *miisc; 1466 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1467 miisc = LIST_NEXT(miisc, mii_list)) 1468 mii_phy_reset(miisc); 1469 } 1470 mii_mediachg(mii); 1471 1472 return (0); 1473 } 1474 1475 /* 1476 * Report current media status. 1477 */ 1478 static void 1479 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1480 { 1481 struct bfe_softc *sc = ifp->if_softc; 1482 struct mii_data *mii; 1483 1484 mii = device_get_softc(sc->bfe_miibus); 1485 mii_pollstat(mii); 1486 ifmr->ifm_active = mii->mii_media_active; 1487 ifmr->ifm_status = mii->mii_media_status; 1488 } 1489 1490 static int 1491 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1492 { 1493 struct bfe_softc *sc = ifp->if_softc; 1494 struct ifreq *ifr = (struct ifreq *) data; 1495 struct mii_data *mii; 1496 int error = 0; 1497 1498 switch(command) { 1499 case SIOCSIFFLAGS: 1500 BFE_LOCK(sc); 1501 if(ifp->if_flags & IFF_UP) 1502 if(ifp->if_flags & IFF_RUNNING) 1503 bfe_set_rx_mode(sc); 1504 else 1505 bfe_init_locked(sc); 1506 else if(ifp->if_flags & IFF_RUNNING) 1507 bfe_stop(sc); 1508 BFE_UNLOCK(sc); 1509 break; 1510 case SIOCADDMULTI: 1511 case SIOCDELMULTI: 1512 BFE_LOCK(sc); 1513 if(ifp->if_flags & IFF_RUNNING) 1514 bfe_set_rx_mode(sc); 1515 BFE_UNLOCK(sc); 1516 break; 1517 case SIOCGIFMEDIA: 1518 case SIOCSIFMEDIA: 1519 mii = device_get_softc(sc->bfe_miibus); 1520 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1521 command); 1522 break; 1523 default: 1524 error = ether_ioctl(ifp, command, data); 1525 break; 1526 } 1527 1528 return (error); 1529 } 1530 1531 static void 1532 bfe_watchdog(struct ifnet *ifp) 1533 { 1534 struct bfe_softc *sc; 1535 1536 sc = ifp->if_softc; 1537 1538 BFE_LOCK(sc); 1539 1540 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1541 1542 ifp->if_flags &= ~IFF_RUNNING; 1543 bfe_init_locked(sc); 1544 1545 ifp->if_oerrors++; 1546 1547 BFE_UNLOCK(sc); 1548 } 1549 1550 static void 1551 bfe_tick(void *xsc) 1552 { 1553 struct bfe_softc *sc = xsc; 1554 struct mii_data *mii; 1555 1556 if (sc == NULL) 1557 return; 1558 1559 BFE_LOCK(sc); 1560 1561 mii = device_get_softc(sc->bfe_miibus); 1562 1563 bfe_stats_update(sc); 1564 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1565 1566 if(sc->bfe_link) { 1567 BFE_UNLOCK(sc); 1568 return; 1569 } 1570 1571 mii_tick(mii); 1572 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1573 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1574 sc->bfe_link++; 1575 1576 BFE_UNLOCK(sc); 1577 } 1578 1579 /* 1580 * Stop the adapter and free any mbufs allocated to the 1581 * RX and TX lists. 1582 */ 1583 static void 1584 bfe_stop(struct bfe_softc *sc) 1585 { 1586 struct ifnet *ifp; 1587 1588 BFE_LOCK_ASSERT(sc); 1589 1590 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1591 1592 ifp = &sc->arpcom.ac_if; 1593 1594 bfe_chip_halt(sc); 1595 bfe_tx_ring_free(sc); 1596 bfe_rx_ring_free(sc); 1597 1598 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1599 } 1600