1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 #include <sys/bus.h> 59 #include <sys/rman.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 #include "miidevs.h" 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <dev/bfe/if_bfereg.h> 69 70 MODULE_DEPEND(bfe, pci, 1, 1, 1); 71 MODULE_DEPEND(bfe, ether, 1, 1, 1); 72 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79 static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85 }; 86 87 static int bfe_probe (device_t); 88 static int bfe_attach (device_t); 89 static int bfe_detach (device_t); 90 static int bfe_suspend (device_t); 91 static int bfe_resume (device_t); 92 static void bfe_release_resources (struct bfe_softc *); 93 static void bfe_intr (void *); 94 static void bfe_start (struct ifnet *); 95 static void bfe_start_locked (struct ifnet *); 96 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97 static void bfe_init (void *); 98 static void bfe_init_locked (void *); 99 static void bfe_stop (struct bfe_softc *); 100 static void bfe_watchdog (struct bfe_softc *); 101 static int bfe_shutdown (device_t); 102 static void bfe_tick (void *); 103 static void bfe_txeof (struct bfe_softc *); 104 static void bfe_rxeof (struct bfe_softc *); 105 static void bfe_set_rx_mode (struct bfe_softc *); 106 static int bfe_list_rx_init (struct bfe_softc *); 107 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free (struct bfe_softc *); 109 110 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111 static int bfe_ifmedia_upd (struct ifnet *); 112 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg (device_t, int, int); 114 static int bfe_miibus_writereg (device_t, int, int, int); 115 static void bfe_miibus_statchg (device_t); 116 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118 static void bfe_get_config (struct bfe_softc *sc); 119 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120 static void bfe_stats_update (struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124 static int bfe_resetphy (struct bfe_softc *); 125 static int bfe_setupphy (struct bfe_softc *); 126 static void bfe_chip_reset (struct bfe_softc *); 127 static void bfe_chip_halt (struct bfe_softc *); 128 static void bfe_core_reset (struct bfe_softc *); 129 static void bfe_core_disable (struct bfe_softc *); 130 static int bfe_dma_alloc (device_t); 131 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 DEVMETHOD(device_suspend, bfe_suspend), 142 DEVMETHOD(device_resume, bfe_resume), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160 }; 161 162 static devclass_t bfe_devclass; 163 164 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167 /* 168 * Probe for a Broadcom 4401 chip. 169 */ 170 static int 171 bfe_probe(device_t dev) 172 { 173 struct bfe_type *t; 174 175 t = bfe_devs; 176 177 while (t->bfe_name != NULL) { 178 if (pci_get_vendor(dev) == t->bfe_vid && 179 pci_get_device(dev) == t->bfe_did) { 180 device_set_desc(dev, t->bfe_name); 181 return (BUS_PROBE_DEFAULT); 182 } 183 t++; 184 } 185 186 return (ENXIO); 187 } 188 189 static int 190 bfe_dma_alloc(device_t dev) 191 { 192 struct bfe_softc *sc; 193 int error, i; 194 195 sc = device_get_softc(dev); 196 197 /* 198 * parent tag. Apparently the chip cannot handle any DMA address 199 * greater than 1GB. 200 */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 4096, 0, /* alignment, boundary */ 203 0x3FFFFFFF, /* lowaddr */ 204 BUS_SPACE_MAXADDR, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 0, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 4096, 0, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 4096, 0, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 BUS_DMA_ALLOCNOW, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if (error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 298 299 if (error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 313 if (error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp = NULL; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 333 334 sc->bfe_dev = dev; 335 336 /* 337 * Map control/status registers. 338 */ 339 pci_enable_busmaster(dev); 340 341 rid = BFE_PCI_MEMLO; 342 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 343 RF_ACTIVE); 344 if (sc->bfe_res == NULL) { 345 device_printf(dev, "couldn't map memory\n"); 346 error = ENXIO; 347 goto fail; 348 } 349 350 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 351 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 352 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 353 354 /* Allocate interrupt */ 355 rid = 0; 356 357 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 358 RF_SHAREABLE | RF_ACTIVE); 359 if (sc->bfe_irq == NULL) { 360 device_printf(dev, "couldn't map interrupt\n"); 361 error = ENXIO; 362 goto fail; 363 } 364 365 if (bfe_dma_alloc(dev)) { 366 device_printf(dev, "failed to allocate DMA resources\n"); 367 error = ENXIO; 368 goto fail; 369 } 370 371 /* Set up ifnet structure */ 372 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 373 if (ifp == NULL) { 374 device_printf(dev, "failed to if_alloc()\n"); 375 error = ENOSPC; 376 goto fail; 377 } 378 ifp->if_softc = sc; 379 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 381 ifp->if_ioctl = bfe_ioctl; 382 ifp->if_start = bfe_start; 383 ifp->if_init = bfe_init; 384 ifp->if_mtu = ETHERMTU; 385 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 386 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 387 IFQ_SET_READY(&ifp->if_snd); 388 389 bfe_get_config(sc); 390 391 /* Reset the chip and turn on the PHY */ 392 BFE_LOCK(sc); 393 bfe_chip_reset(sc); 394 BFE_UNLOCK(sc); 395 396 if (mii_phy_probe(dev, &sc->bfe_miibus, 397 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 398 device_printf(dev, "MII without any PHY!\n"); 399 error = ENXIO; 400 goto fail; 401 } 402 403 ether_ifattach(ifp, sc->bfe_enaddr); 404 405 /* 406 * Tell the upper layer(s) we support long frames. 407 */ 408 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 409 ifp->if_capabilities |= IFCAP_VLAN_MTU; 410 ifp->if_capenable |= IFCAP_VLAN_MTU; 411 412 /* 413 * Hook interrupt last to avoid having to lock softc 414 */ 415 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 416 NULL, bfe_intr, sc, &sc->bfe_intrhand); 417 418 if (error) { 419 device_printf(dev, "couldn't set up irq\n"); 420 goto fail; 421 } 422 fail: 423 if (error) 424 bfe_release_resources(sc); 425 return (error); 426 } 427 428 static int 429 bfe_detach(device_t dev) 430 { 431 struct bfe_softc *sc; 432 struct ifnet *ifp; 433 434 sc = device_get_softc(dev); 435 436 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 437 438 ifp = sc->bfe_ifp; 439 440 if (device_is_attached(dev)) { 441 BFE_LOCK(sc); 442 bfe_stop(sc); 443 BFE_UNLOCK(sc); 444 callout_drain(&sc->bfe_stat_co); 445 if (ifp != NULL) 446 ether_ifdetach(ifp); 447 } 448 449 bfe_chip_reset(sc); 450 451 bus_generic_detach(dev); 452 if (sc->bfe_miibus != NULL) 453 device_delete_child(dev, sc->bfe_miibus); 454 455 bfe_release_resources(sc); 456 mtx_destroy(&sc->bfe_mtx); 457 458 return (0); 459 } 460 461 /* 462 * Stop all chip I/O so that the kernel's probe routines don't 463 * get confused by errant DMAs when rebooting. 464 */ 465 static int 466 bfe_shutdown(device_t dev) 467 { 468 struct bfe_softc *sc; 469 470 sc = device_get_softc(dev); 471 BFE_LOCK(sc); 472 bfe_stop(sc); 473 474 BFE_UNLOCK(sc); 475 476 return (0); 477 } 478 479 static int 480 bfe_suspend(device_t dev) 481 { 482 struct bfe_softc *sc; 483 484 sc = device_get_softc(dev); 485 BFE_LOCK(sc); 486 bfe_stop(sc); 487 BFE_UNLOCK(sc); 488 489 return (0); 490 } 491 492 static int 493 bfe_resume(device_t dev) 494 { 495 struct bfe_softc *sc; 496 struct ifnet *ifp; 497 498 sc = device_get_softc(dev); 499 ifp = sc->bfe_ifp; 500 BFE_LOCK(sc); 501 bfe_chip_reset(sc); 502 if (ifp->if_flags & IFF_UP) { 503 bfe_init_locked(sc); 504 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 505 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 506 bfe_start_locked(ifp); 507 } 508 BFE_UNLOCK(sc); 509 510 return (0); 511 } 512 513 static int 514 bfe_miibus_readreg(device_t dev, int phy, int reg) 515 { 516 struct bfe_softc *sc; 517 u_int32_t ret; 518 519 sc = device_get_softc(dev); 520 if (phy != sc->bfe_phyaddr) 521 return (0); 522 bfe_readphy(sc, reg, &ret); 523 524 return (ret); 525 } 526 527 static int 528 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 529 { 530 struct bfe_softc *sc; 531 532 sc = device_get_softc(dev); 533 if (phy != sc->bfe_phyaddr) 534 return (0); 535 bfe_writephy(sc, reg, val); 536 537 return (0); 538 } 539 540 static void 541 bfe_miibus_statchg(device_t dev) 542 { 543 struct bfe_softc *sc; 544 struct mii_data *mii; 545 u_int32_t val, flow; 546 547 sc = device_get_softc(dev); 548 mii = device_get_softc(sc->bfe_miibus); 549 550 if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 551 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 552 sc->bfe_link = 1; 553 } else 554 sc->bfe_link = 0; 555 556 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 557 val = CSR_READ_4(sc, BFE_TX_CTRL); 558 val &= ~BFE_TX_DUPLEX; 559 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 560 val |= BFE_TX_DUPLEX; 561 flow = 0; 562 #ifdef notyet 563 flow = CSR_READ_4(sc, BFE_RXCONF); 564 flow &= ~BFE_RXCONF_FLOW; 565 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 566 IFM_ETH_RXPAUSE) != 0) 567 flow |= BFE_RXCONF_FLOW; 568 CSR_WRITE_4(sc, BFE_RXCONF, flow); 569 /* 570 * It seems that the hardware has Tx pause issues 571 * so enable only Rx pause. 572 */ 573 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 574 flow &= ~BFE_FLOW_PAUSE_ENAB; 575 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 576 #endif 577 } 578 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 579 } 580 581 static void 582 bfe_tx_ring_free(struct bfe_softc *sc) 583 { 584 int i; 585 586 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 587 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 588 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 589 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 590 bus_dmamap_unload(sc->bfe_tag, 591 sc->bfe_tx_ring[i].bfe_map); 592 } 593 } 594 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 595 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 596 } 597 598 static void 599 bfe_rx_ring_free(struct bfe_softc *sc) 600 { 601 int i; 602 603 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 604 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 605 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 606 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 607 bus_dmamap_unload(sc->bfe_tag, 608 sc->bfe_rx_ring[i].bfe_map); 609 } 610 } 611 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 612 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 613 } 614 615 static int 616 bfe_list_rx_init(struct bfe_softc *sc) 617 { 618 int i; 619 620 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 621 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 622 return (ENOBUFS); 623 } 624 625 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 626 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 627 628 sc->bfe_rx_cons = 0; 629 630 return (0); 631 } 632 633 static int 634 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 635 { 636 struct bfe_rxheader *rx_header; 637 struct bfe_desc *d; 638 struct bfe_data *r; 639 u_int32_t ctrl; 640 int allocated, error; 641 642 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 643 return (EINVAL); 644 645 allocated = 0; 646 if (m == NULL) { 647 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 648 if (m == NULL) 649 return (ENOBUFS); 650 m->m_len = m->m_pkthdr.len = MCLBYTES; 651 allocated++; 652 } 653 else 654 m->m_data = m->m_ext.ext_buf; 655 656 rx_header = mtod(m, struct bfe_rxheader *); 657 rx_header->len = 0; 658 rx_header->flags = 0; 659 660 /* Map the mbuf into DMA */ 661 sc->bfe_rx_cnt = c; 662 d = &sc->bfe_rx_list[c]; 663 r = &sc->bfe_rx_ring[c]; 664 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 665 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 666 if (error != 0) { 667 if (allocated != 0) 668 m_free(m); 669 if (error != ENOMEM) 670 device_printf(sc->bfe_dev, 671 "failed to map RX buffer, error %d\n", error); 672 return (ENOBUFS); 673 } 674 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 675 676 ctrl = ETHER_MAX_LEN + 32; 677 678 if (c == BFE_RX_LIST_CNT - 1) 679 ctrl |= BFE_DESC_EOT; 680 681 d->bfe_ctrl = ctrl; 682 r->bfe_mbuf = m; 683 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 684 return (0); 685 } 686 687 static void 688 bfe_get_config(struct bfe_softc *sc) 689 { 690 u_int8_t eeprom[128]; 691 692 bfe_read_eeprom(sc, eeprom); 693 694 sc->bfe_enaddr[0] = eeprom[79]; 695 sc->bfe_enaddr[1] = eeprom[78]; 696 sc->bfe_enaddr[2] = eeprom[81]; 697 sc->bfe_enaddr[3] = eeprom[80]; 698 sc->bfe_enaddr[4] = eeprom[83]; 699 sc->bfe_enaddr[5] = eeprom[82]; 700 701 sc->bfe_phyaddr = eeprom[90] & 0x1f; 702 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 703 704 sc->bfe_core_unit = 0; 705 sc->bfe_dma_offset = BFE_PCI_DMA; 706 } 707 708 static void 709 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 710 { 711 u_int32_t bar_orig, pci_rev, val; 712 713 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 714 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 715 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 716 717 val = CSR_READ_4(sc, BFE_SBINTVEC); 718 val |= cores; 719 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 720 721 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 722 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 723 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 724 725 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 726 } 727 728 static void 729 bfe_clear_stats(struct bfe_softc *sc) 730 { 731 u_long reg; 732 733 BFE_LOCK_ASSERT(sc); 734 735 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 736 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 737 CSR_READ_4(sc, reg); 738 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 739 CSR_READ_4(sc, reg); 740 } 741 742 static int 743 bfe_resetphy(struct bfe_softc *sc) 744 { 745 u_int32_t val; 746 747 bfe_writephy(sc, 0, BMCR_RESET); 748 DELAY(100); 749 bfe_readphy(sc, 0, &val); 750 if (val & BMCR_RESET) { 751 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 752 return (ENXIO); 753 } 754 return (0); 755 } 756 757 static void 758 bfe_chip_halt(struct bfe_softc *sc) 759 { 760 BFE_LOCK_ASSERT(sc); 761 /* disable interrupts - not that it actually does..*/ 762 CSR_WRITE_4(sc, BFE_IMASK, 0); 763 CSR_READ_4(sc, BFE_IMASK); 764 765 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 766 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 767 768 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 769 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 770 DELAY(10); 771 } 772 773 static void 774 bfe_chip_reset(struct bfe_softc *sc) 775 { 776 u_int32_t val; 777 778 BFE_LOCK_ASSERT(sc); 779 780 /* Set the interrupt vector for the enet core */ 781 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 782 783 /* is core up? */ 784 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 785 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 786 if (val == BFE_CLOCK) { 787 /* It is, so shut it down */ 788 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 789 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 790 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 791 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 792 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 793 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 794 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 795 100, 0); 796 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 797 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 798 } 799 800 bfe_core_reset(sc); 801 bfe_clear_stats(sc); 802 803 /* 804 * We want the phy registers to be accessible even when 805 * the driver is "downed" so initialize MDC preamble, frequency, 806 * and whether internal or external phy here. 807 */ 808 809 /* 4402 has 62.5Mhz SB clock and internal phy */ 810 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 811 812 /* Internal or external PHY? */ 813 val = CSR_READ_4(sc, BFE_DEVCTRL); 814 if (!(val & BFE_IPP)) 815 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 816 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 817 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 818 DELAY(100); 819 } 820 821 /* Enable CRC32 generation and set proper LED modes */ 822 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 823 824 /* Reset or clear powerdown control bit */ 825 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 826 827 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 828 BFE_LAZY_FC_MASK)); 829 830 /* 831 * We don't want lazy interrupts, so just send them at 832 * the end of a frame, please 833 */ 834 BFE_OR(sc, BFE_RCV_LAZY, 0); 835 836 /* Set max lengths, accounting for VLAN tags */ 837 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 838 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 839 840 /* Set watermark XXX - magic */ 841 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 842 843 /* 844 * Initialise DMA channels 845 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 846 */ 847 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 848 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 849 850 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 851 BFE_RX_CTRL_ENABLE); 852 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 853 854 bfe_resetphy(sc); 855 bfe_setupphy(sc); 856 } 857 858 static void 859 bfe_core_disable(struct bfe_softc *sc) 860 { 861 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 862 return; 863 864 /* 865 * Set reject, wait for it set, then wait for the core to stop 866 * being busy, then set reset and reject and enable the clocks. 867 */ 868 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 869 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 870 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 871 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 872 BFE_RESET)); 873 CSR_READ_4(sc, BFE_SBTMSLOW); 874 DELAY(10); 875 /* Leave reset and reject set */ 876 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 877 DELAY(10); 878 } 879 880 static void 881 bfe_core_reset(struct bfe_softc *sc) 882 { 883 u_int32_t val; 884 885 /* Disable the core */ 886 bfe_core_disable(sc); 887 888 /* and bring it back up */ 889 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 890 CSR_READ_4(sc, BFE_SBTMSLOW); 891 DELAY(10); 892 893 /* Chip bug, clear SERR, IB and TO if they are set. */ 894 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 895 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 896 val = CSR_READ_4(sc, BFE_SBIMSTATE); 897 if (val & (BFE_IBE | BFE_TO)) 898 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 899 900 /* Clear reset and allow it to move through the core */ 901 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 902 CSR_READ_4(sc, BFE_SBTMSLOW); 903 DELAY(10); 904 905 /* Leave the clock set */ 906 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 907 CSR_READ_4(sc, BFE_SBTMSLOW); 908 DELAY(10); 909 } 910 911 static void 912 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 913 { 914 u_int32_t val; 915 916 val = ((u_int32_t) data[2]) << 24; 917 val |= ((u_int32_t) data[3]) << 16; 918 val |= ((u_int32_t) data[4]) << 8; 919 val |= ((u_int32_t) data[5]); 920 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 921 val = (BFE_CAM_HI_VALID | 922 (((u_int32_t) data[0]) << 8) | 923 (((u_int32_t) data[1]))); 924 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 925 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 926 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 927 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 928 } 929 930 static void 931 bfe_set_rx_mode(struct bfe_softc *sc) 932 { 933 struct ifnet *ifp = sc->bfe_ifp; 934 struct ifmultiaddr *ifma; 935 u_int32_t val; 936 int i = 0; 937 938 val = CSR_READ_4(sc, BFE_RXCONF); 939 940 if (ifp->if_flags & IFF_PROMISC) 941 val |= BFE_RXCONF_PROMISC; 942 else 943 val &= ~BFE_RXCONF_PROMISC; 944 945 if (ifp->if_flags & IFF_BROADCAST) 946 val &= ~BFE_RXCONF_DBCAST; 947 else 948 val |= BFE_RXCONF_DBCAST; 949 950 951 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 952 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 953 954 if (ifp->if_flags & IFF_ALLMULTI) 955 val |= BFE_RXCONF_ALLMULTI; 956 else { 957 val &= ~BFE_RXCONF_ALLMULTI; 958 IF_ADDR_LOCK(ifp); 959 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 960 if (ifma->ifma_addr->sa_family != AF_LINK) 961 continue; 962 bfe_cam_write(sc, 963 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 964 } 965 IF_ADDR_UNLOCK(ifp); 966 } 967 968 CSR_WRITE_4(sc, BFE_RXCONF, val); 969 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 970 } 971 972 static void 973 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 974 { 975 u_int32_t *ptr; 976 977 ptr = arg; 978 *ptr = segs->ds_addr; 979 } 980 981 static void 982 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 983 { 984 struct bfe_desc *d; 985 986 d = arg; 987 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 988 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 989 } 990 991 static void 992 bfe_release_resources(struct bfe_softc *sc) 993 { 994 device_t dev; 995 int i; 996 997 dev = sc->bfe_dev; 998 999 if (sc->bfe_vpd_prodname != NULL) 1000 free(sc->bfe_vpd_prodname, M_DEVBUF); 1001 1002 if (sc->bfe_vpd_readonly != NULL) 1003 free(sc->bfe_vpd_readonly, M_DEVBUF); 1004 1005 if (sc->bfe_intrhand != NULL) 1006 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 1007 1008 if (sc->bfe_irq != NULL) 1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1010 1011 if (sc->bfe_res != NULL) 1012 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 1013 1014 if (sc->bfe_ifp != NULL) 1015 if_free(sc->bfe_ifp); 1016 1017 if (sc->bfe_tx_tag != NULL) { 1018 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1019 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1020 sc->bfe_tx_map); 1021 bus_dma_tag_destroy(sc->bfe_tx_tag); 1022 sc->bfe_tx_tag = NULL; 1023 } 1024 1025 if (sc->bfe_rx_tag != NULL) { 1026 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1027 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1028 sc->bfe_rx_map); 1029 bus_dma_tag_destroy(sc->bfe_rx_tag); 1030 sc->bfe_rx_tag = NULL; 1031 } 1032 1033 if (sc->bfe_tag != NULL) { 1034 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1035 bus_dmamap_destroy(sc->bfe_tag, 1036 sc->bfe_tx_ring[i].bfe_map); 1037 } 1038 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1039 bus_dmamap_destroy(sc->bfe_tag, 1040 sc->bfe_rx_ring[i].bfe_map); 1041 } 1042 bus_dma_tag_destroy(sc->bfe_tag); 1043 sc->bfe_tag = NULL; 1044 } 1045 1046 if (sc->bfe_parent_tag != NULL) 1047 bus_dma_tag_destroy(sc->bfe_parent_tag); 1048 1049 return; 1050 } 1051 1052 static void 1053 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1054 { 1055 long i; 1056 u_int16_t *ptr = (u_int16_t *)data; 1057 1058 for(i = 0; i < 128; i += 2) 1059 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1060 } 1061 1062 static int 1063 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1064 u_long timeout, const int clear) 1065 { 1066 u_long i; 1067 1068 for (i = 0; i < timeout; i++) { 1069 u_int32_t val = CSR_READ_4(sc, reg); 1070 1071 if (clear && !(val & bit)) 1072 break; 1073 if (!clear && (val & bit)) 1074 break; 1075 DELAY(10); 1076 } 1077 if (i == timeout) { 1078 device_printf(sc->bfe_dev, 1079 "BUG! Timeout waiting for bit %08x of register " 1080 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1081 return (-1); 1082 } 1083 return (0); 1084 } 1085 1086 static int 1087 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1088 { 1089 int err; 1090 1091 /* Clear MII ISR */ 1092 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1093 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1094 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1095 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1096 (reg << BFE_MDIO_RA_SHIFT) | 1097 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1098 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1099 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1100 1101 return (err); 1102 } 1103 1104 static int 1105 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1106 { 1107 int status; 1108 1109 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1110 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1111 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1112 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1113 (reg << BFE_MDIO_RA_SHIFT) | 1114 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1115 (val & BFE_MDIO_DATA_DATA))); 1116 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1117 1118 return (status); 1119 } 1120 1121 /* 1122 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1123 * twice 1124 */ 1125 static int 1126 bfe_setupphy(struct bfe_softc *sc) 1127 { 1128 u_int32_t val; 1129 1130 /* Enable activity LED */ 1131 bfe_readphy(sc, 26, &val); 1132 bfe_writephy(sc, 26, val & 0x7fff); 1133 bfe_readphy(sc, 26, &val); 1134 1135 /* Enable traffic meter LED mode */ 1136 bfe_readphy(sc, 27, &val); 1137 bfe_writephy(sc, 27, val | (1 << 6)); 1138 1139 return (0); 1140 } 1141 1142 static void 1143 bfe_stats_update(struct bfe_softc *sc) 1144 { 1145 u_long reg; 1146 u_int32_t *val; 1147 1148 val = &sc->bfe_hwstats.tx_good_octets; 1149 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1150 *val++ += CSR_READ_4(sc, reg); 1151 } 1152 val = &sc->bfe_hwstats.rx_good_octets; 1153 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1154 *val++ += CSR_READ_4(sc, reg); 1155 } 1156 } 1157 1158 static void 1159 bfe_txeof(struct bfe_softc *sc) 1160 { 1161 struct ifnet *ifp; 1162 int i, chipidx; 1163 1164 BFE_LOCK_ASSERT(sc); 1165 1166 ifp = sc->bfe_ifp; 1167 1168 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1169 chipidx /= sizeof(struct bfe_desc); 1170 1171 i = sc->bfe_tx_cons; 1172 /* Go through the mbufs and free those that have been transmitted */ 1173 while (i != chipidx) { 1174 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1175 if (r->bfe_mbuf != NULL) { 1176 ifp->if_opackets++; 1177 m_freem(r->bfe_mbuf); 1178 r->bfe_mbuf = NULL; 1179 } 1180 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1181 sc->bfe_tx_cnt--; 1182 BFE_INC(i, BFE_TX_LIST_CNT); 1183 } 1184 1185 if (i != sc->bfe_tx_cons) { 1186 /* we freed up some mbufs */ 1187 sc->bfe_tx_cons = i; 1188 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1189 } 1190 1191 if (sc->bfe_tx_cnt == 0) 1192 sc->bfe_watchdog_timer = 0; 1193 } 1194 1195 /* Pass a received packet up the stack */ 1196 static void 1197 bfe_rxeof(struct bfe_softc *sc) 1198 { 1199 struct mbuf *m; 1200 struct ifnet *ifp; 1201 struct bfe_rxheader *rxheader; 1202 struct bfe_data *r; 1203 int cons; 1204 u_int32_t status, current, len, flags; 1205 1206 BFE_LOCK_ASSERT(sc); 1207 cons = sc->bfe_rx_cons; 1208 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1209 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1210 1211 ifp = sc->bfe_ifp; 1212 1213 while (current != cons) { 1214 r = &sc->bfe_rx_ring[cons]; 1215 m = r->bfe_mbuf; 1216 rxheader = mtod(m, struct bfe_rxheader*); 1217 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1218 len = rxheader->len; 1219 r->bfe_mbuf = NULL; 1220 1221 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1222 flags = rxheader->flags; 1223 1224 len -= ETHER_CRC_LEN; 1225 1226 /* flag an error and try again */ 1227 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1228 ifp->if_ierrors++; 1229 if (flags & BFE_RX_FLAG_SERR) 1230 ifp->if_collisions++; 1231 bfe_list_newbuf(sc, cons, m); 1232 BFE_INC(cons, BFE_RX_LIST_CNT); 1233 continue; 1234 } 1235 1236 /* Go past the rx header */ 1237 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1238 m_adj(m, BFE_RX_OFFSET); 1239 m->m_len = m->m_pkthdr.len = len; 1240 } else { 1241 bfe_list_newbuf(sc, cons, m); 1242 ifp->if_ierrors++; 1243 BFE_INC(cons, BFE_RX_LIST_CNT); 1244 continue; 1245 } 1246 1247 ifp->if_ipackets++; 1248 m->m_pkthdr.rcvif = ifp; 1249 BFE_UNLOCK(sc); 1250 (*ifp->if_input)(ifp, m); 1251 BFE_LOCK(sc); 1252 1253 BFE_INC(cons, BFE_RX_LIST_CNT); 1254 } 1255 sc->bfe_rx_cons = cons; 1256 } 1257 1258 static void 1259 bfe_intr(void *xsc) 1260 { 1261 struct bfe_softc *sc = xsc; 1262 struct ifnet *ifp; 1263 u_int32_t istat, imask, flag; 1264 1265 ifp = sc->bfe_ifp; 1266 1267 BFE_LOCK(sc); 1268 1269 istat = CSR_READ_4(sc, BFE_ISTAT); 1270 imask = CSR_READ_4(sc, BFE_IMASK); 1271 1272 /* 1273 * Defer unsolicited interrupts - This is necessary because setting the 1274 * chips interrupt mask register to 0 doesn't actually stop the 1275 * interrupts 1276 */ 1277 istat &= imask; 1278 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1279 CSR_READ_4(sc, BFE_ISTAT); 1280 1281 /* not expecting this interrupt, disregard it */ 1282 if (istat == 0) { 1283 BFE_UNLOCK(sc); 1284 return; 1285 } 1286 1287 if (istat & BFE_ISTAT_ERRORS) { 1288 1289 if (istat & BFE_ISTAT_DSCE) { 1290 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1291 bfe_stop(sc); 1292 BFE_UNLOCK(sc); 1293 return; 1294 } 1295 1296 if (istat & BFE_ISTAT_DPE) { 1297 device_printf(sc->bfe_dev, 1298 "Descriptor Protocol Error\n"); 1299 bfe_stop(sc); 1300 BFE_UNLOCK(sc); 1301 return; 1302 } 1303 1304 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1305 if (flag & BFE_STAT_EMASK) 1306 ifp->if_oerrors++; 1307 1308 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1309 if (flag & BFE_RX_FLAG_ERRORS) 1310 ifp->if_ierrors++; 1311 1312 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1313 bfe_init_locked(sc); 1314 } 1315 1316 /* A packet was received */ 1317 if (istat & BFE_ISTAT_RX) 1318 bfe_rxeof(sc); 1319 1320 /* A packet was sent */ 1321 if (istat & BFE_ISTAT_TX) 1322 bfe_txeof(sc); 1323 1324 /* We have packets pending, fire them out */ 1325 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1326 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1327 bfe_start_locked(ifp); 1328 1329 BFE_UNLOCK(sc); 1330 } 1331 1332 static int 1333 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1334 { 1335 struct bfe_desc *d = NULL; 1336 struct bfe_data *r = NULL; 1337 struct mbuf *m; 1338 u_int32_t frag, cur, cnt = 0; 1339 int chainlen = 0; 1340 int error; 1341 1342 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1343 return (ENOBUFS); 1344 1345 /* 1346 * Count the number of frags in this chain to see if 1347 * we need to m_defrag. Since the descriptor list is shared 1348 * by all packets, we'll m_defrag long chains so that they 1349 * do not use up the entire list, even if they would fit. 1350 */ 1351 for(m = *m_head; m != NULL; m = m->m_next) 1352 chainlen++; 1353 1354 1355 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1356 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1357 m = m_defrag(*m_head, M_DONTWAIT); 1358 if (m == NULL) 1359 return (ENOBUFS); 1360 *m_head = m; 1361 } 1362 1363 /* 1364 * Start packing the mbufs in this chain into 1365 * the fragment pointers. Stop when we run out 1366 * of fragments or hit the end of the mbuf chain. 1367 */ 1368 cur = frag = *txidx; 1369 cnt = 0; 1370 1371 for(m = *m_head; m != NULL; m = m->m_next) { 1372 if (m->m_len != 0) { 1373 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1374 return (ENOBUFS); 1375 1376 d = &sc->bfe_tx_list[cur]; 1377 r = &sc->bfe_tx_ring[cur]; 1378 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1379 /* always intterupt on completion */ 1380 d->bfe_ctrl |= BFE_DESC_IOC; 1381 if (cnt == 0) 1382 /* Set start of frame */ 1383 d->bfe_ctrl |= BFE_DESC_SOF; 1384 if (cur == BFE_TX_LIST_CNT - 1) 1385 /* 1386 * Tell the chip to wrap to the start of 1387 * the descriptor list 1388 */ 1389 d->bfe_ctrl |= BFE_DESC_EOT; 1390 1391 error = bus_dmamap_load(sc->bfe_tag, 1392 r->bfe_map, mtod(m, void*), m->m_len, 1393 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1394 if (error) 1395 return (ENOBUFS); 1396 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1397 BUS_DMASYNC_PREWRITE); 1398 1399 frag = cur; 1400 BFE_INC(cur, BFE_TX_LIST_CNT); 1401 cnt++; 1402 } 1403 } 1404 1405 if (m != NULL) 1406 return (ENOBUFS); 1407 1408 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1409 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1410 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1411 1412 *txidx = cur; 1413 sc->bfe_tx_cnt += cnt; 1414 return (0); 1415 } 1416 1417 /* 1418 * Set up to transmit a packet. 1419 */ 1420 static void 1421 bfe_start(struct ifnet *ifp) 1422 { 1423 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1424 bfe_start_locked(ifp); 1425 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1426 } 1427 1428 /* 1429 * Set up to transmit a packet. The softc is already locked. 1430 */ 1431 static void 1432 bfe_start_locked(struct ifnet *ifp) 1433 { 1434 struct bfe_softc *sc; 1435 struct mbuf *m_head = NULL; 1436 int idx, queued = 0; 1437 1438 sc = ifp->if_softc; 1439 idx = sc->bfe_tx_prod; 1440 1441 BFE_LOCK_ASSERT(sc); 1442 1443 /* 1444 * Not much point trying to send if the link is down 1445 * or we have nothing to send. 1446 */ 1447 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1448 return; 1449 1450 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1451 IFF_DRV_RUNNING) 1452 return; 1453 1454 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1455 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1456 if (m_head == NULL) 1457 break; 1458 1459 /* 1460 * Pack the data into the tx ring. If we dont have 1461 * enough room, let the chip drain the ring. 1462 */ 1463 if (bfe_encap(sc, &m_head, &idx)) { 1464 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1465 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1466 break; 1467 } 1468 1469 queued++; 1470 1471 /* 1472 * If there's a BPF listener, bounce a copy of this frame 1473 * to him. 1474 */ 1475 BPF_MTAP(ifp, m_head); 1476 } 1477 1478 if (queued) { 1479 sc->bfe_tx_prod = idx; 1480 /* Transmit - twice due to apparent hardware bug */ 1481 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1482 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1483 1484 /* 1485 * Set a timeout in case the chip goes out to lunch. 1486 */ 1487 sc->bfe_watchdog_timer = 5; 1488 } 1489 } 1490 1491 static void 1492 bfe_init(void *xsc) 1493 { 1494 BFE_LOCK((struct bfe_softc *)xsc); 1495 bfe_init_locked(xsc); 1496 BFE_UNLOCK((struct bfe_softc *)xsc); 1497 } 1498 1499 static void 1500 bfe_init_locked(void *xsc) 1501 { 1502 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1503 struct ifnet *ifp = sc->bfe_ifp; 1504 struct mii_data *mii; 1505 1506 BFE_LOCK_ASSERT(sc); 1507 1508 mii = device_get_softc(sc->bfe_miibus); 1509 1510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1511 return; 1512 1513 bfe_stop(sc); 1514 bfe_chip_reset(sc); 1515 1516 if (bfe_list_rx_init(sc) == ENOBUFS) { 1517 device_printf(sc->bfe_dev, 1518 "%s: Not enough memory for list buffers\n", __func__); 1519 bfe_stop(sc); 1520 return; 1521 } 1522 1523 bfe_set_rx_mode(sc); 1524 1525 /* Enable the chip and core */ 1526 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1527 /* Enable interrupts */ 1528 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1529 1530 /* Clear link state and change media. */ 1531 sc->bfe_link = 0; 1532 mii_mediachg(mii); 1533 1534 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1535 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1536 1537 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1538 } 1539 1540 /* 1541 * Set media options. 1542 */ 1543 static int 1544 bfe_ifmedia_upd(struct ifnet *ifp) 1545 { 1546 struct bfe_softc *sc; 1547 struct mii_data *mii; 1548 int error; 1549 1550 sc = ifp->if_softc; 1551 BFE_LOCK(sc); 1552 1553 mii = device_get_softc(sc->bfe_miibus); 1554 if (mii->mii_instance) { 1555 struct mii_softc *miisc; 1556 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1557 miisc = LIST_NEXT(miisc, mii_list)) 1558 mii_phy_reset(miisc); 1559 } 1560 error = mii_mediachg(mii); 1561 BFE_UNLOCK(sc); 1562 1563 return (error); 1564 } 1565 1566 /* 1567 * Report current media status. 1568 */ 1569 static void 1570 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1571 { 1572 struct bfe_softc *sc = ifp->if_softc; 1573 struct mii_data *mii; 1574 1575 BFE_LOCK(sc); 1576 mii = device_get_softc(sc->bfe_miibus); 1577 mii_pollstat(mii); 1578 ifmr->ifm_active = mii->mii_media_active; 1579 ifmr->ifm_status = mii->mii_media_status; 1580 BFE_UNLOCK(sc); 1581 } 1582 1583 static int 1584 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1585 { 1586 struct bfe_softc *sc = ifp->if_softc; 1587 struct ifreq *ifr = (struct ifreq *) data; 1588 struct mii_data *mii; 1589 int error = 0; 1590 1591 switch (command) { 1592 case SIOCSIFFLAGS: 1593 BFE_LOCK(sc); 1594 if (ifp->if_flags & IFF_UP) 1595 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1596 bfe_set_rx_mode(sc); 1597 else 1598 bfe_init_locked(sc); 1599 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1600 bfe_stop(sc); 1601 BFE_UNLOCK(sc); 1602 break; 1603 case SIOCADDMULTI: 1604 case SIOCDELMULTI: 1605 BFE_LOCK(sc); 1606 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1607 bfe_set_rx_mode(sc); 1608 BFE_UNLOCK(sc); 1609 break; 1610 case SIOCGIFMEDIA: 1611 case SIOCSIFMEDIA: 1612 mii = device_get_softc(sc->bfe_miibus); 1613 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1614 break; 1615 default: 1616 error = ether_ioctl(ifp, command, data); 1617 break; 1618 } 1619 1620 return (error); 1621 } 1622 1623 static void 1624 bfe_watchdog(struct bfe_softc *sc) 1625 { 1626 struct ifnet *ifp; 1627 1628 BFE_LOCK_ASSERT(sc); 1629 1630 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1631 return; 1632 1633 ifp = sc->bfe_ifp; 1634 1635 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1636 1637 ifp->if_oerrors++; 1638 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1639 bfe_init_locked(sc); 1640 1641 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1642 bfe_start_locked(ifp); 1643 } 1644 1645 static void 1646 bfe_tick(void *xsc) 1647 { 1648 struct bfe_softc *sc = xsc; 1649 struct mii_data *mii; 1650 1651 BFE_LOCK_ASSERT(sc); 1652 1653 mii = device_get_softc(sc->bfe_miibus); 1654 mii_tick(mii); 1655 bfe_stats_update(sc); 1656 bfe_watchdog(sc); 1657 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1658 } 1659 1660 /* 1661 * Stop the adapter and free any mbufs allocated to the 1662 * RX and TX lists. 1663 */ 1664 static void 1665 bfe_stop(struct bfe_softc *sc) 1666 { 1667 struct ifnet *ifp; 1668 1669 BFE_LOCK_ASSERT(sc); 1670 1671 ifp = sc->bfe_ifp; 1672 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1673 sc->bfe_link = 0; 1674 callout_stop(&sc->bfe_stat_co); 1675 sc->bfe_watchdog_timer = 0; 1676 1677 bfe_chip_halt(sc); 1678 bfe_tx_ring_free(sc); 1679 bfe_rx_ring_free(sc); 1680 } 1681