1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 #include <sys/bus.h> 59 #include <sys/rman.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 #include "miidevs.h" 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <dev/bfe/if_bfereg.h> 69 70 MODULE_DEPEND(bfe, pci, 1, 1, 1); 71 MODULE_DEPEND(bfe, ether, 1, 1, 1); 72 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79 static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85 }; 86 87 static int bfe_probe (device_t); 88 static int bfe_attach (device_t); 89 static int bfe_detach (device_t); 90 static int bfe_suspend (device_t); 91 static int bfe_resume (device_t); 92 static void bfe_release_resources (struct bfe_softc *); 93 static void bfe_intr (void *); 94 static void bfe_start (struct ifnet *); 95 static void bfe_start_locked (struct ifnet *); 96 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97 static void bfe_init (void *); 98 static void bfe_init_locked (void *); 99 static void bfe_stop (struct bfe_softc *); 100 static void bfe_watchdog (struct bfe_softc *); 101 static int bfe_shutdown (device_t); 102 static void bfe_tick (void *); 103 static void bfe_txeof (struct bfe_softc *); 104 static void bfe_rxeof (struct bfe_softc *); 105 static void bfe_set_rx_mode (struct bfe_softc *); 106 static int bfe_list_rx_init (struct bfe_softc *); 107 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free (struct bfe_softc *); 109 110 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111 static int bfe_ifmedia_upd (struct ifnet *); 112 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg (device_t, int, int); 114 static int bfe_miibus_writereg (device_t, int, int, int); 115 static void bfe_miibus_statchg (device_t); 116 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118 static void bfe_get_config (struct bfe_softc *sc); 119 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120 static void bfe_stats_update (struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124 static int bfe_resetphy (struct bfe_softc *); 125 static int bfe_setupphy (struct bfe_softc *); 126 static void bfe_chip_reset (struct bfe_softc *); 127 static void bfe_chip_halt (struct bfe_softc *); 128 static void bfe_core_reset (struct bfe_softc *); 129 static void bfe_core_disable (struct bfe_softc *); 130 static int bfe_dma_alloc (device_t); 131 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 DEVMETHOD(device_suspend, bfe_suspend), 142 DEVMETHOD(device_resume, bfe_resume), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160 }; 161 162 static devclass_t bfe_devclass; 163 164 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167 /* 168 * Probe for a Broadcom 4401 chip. 169 */ 170 static int 171 bfe_probe(device_t dev) 172 { 173 struct bfe_type *t; 174 struct bfe_softc *sc; 175 176 t = bfe_devs; 177 178 sc = device_get_softc(dev); 179 bzero(sc, sizeof(struct bfe_softc)); 180 sc->bfe_unit = device_get_unit(dev); 181 sc->bfe_dev = dev; 182 183 while(t->bfe_name != NULL) { 184 if ((pci_get_vendor(dev) == t->bfe_vid) && 185 (pci_get_device(dev) == t->bfe_did)) { 186 device_set_desc_copy(dev, t->bfe_name); 187 return (BUS_PROBE_DEFAULT); 188 } 189 t++; 190 } 191 192 return (ENXIO); 193 } 194 195 static int 196 bfe_dma_alloc(device_t dev) 197 { 198 struct bfe_softc *sc; 199 int error, i; 200 201 sc = device_get_softc(dev); 202 203 /* 204 * parent tag. Apparently the chip cannot handle any DMA address 205 * greater than 1GB. 206 */ 207 error = bus_dma_tag_create(NULL, /* parent */ 208 4096, 0, /* alignment, boundary */ 209 0x3FFFFFFF, /* lowaddr */ 210 BUS_SPACE_MAXADDR, /* highaddr */ 211 NULL, NULL, /* filter, filterarg */ 212 MAXBSIZE, /* maxsize */ 213 BUS_SPACE_UNRESTRICTED, /* num of segments */ 214 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 215 0, /* flags */ 216 NULL, NULL, /* lockfunc, lockarg */ 217 &sc->bfe_parent_tag); 218 219 /* tag for TX ring */ 220 error = bus_dma_tag_create(sc->bfe_parent_tag, 221 4096, 0, 222 BUS_SPACE_MAXADDR, 223 BUS_SPACE_MAXADDR, 224 NULL, NULL, 225 BFE_TX_LIST_SIZE, 226 1, 227 BUS_SPACE_MAXSIZE_32BIT, 228 0, 229 NULL, NULL, 230 &sc->bfe_tx_tag); 231 232 if (error) { 233 device_printf(dev, "could not allocate dma tag\n"); 234 return (ENOMEM); 235 } 236 237 /* tag for RX ring */ 238 error = bus_dma_tag_create(sc->bfe_parent_tag, 239 4096, 0, 240 BUS_SPACE_MAXADDR, 241 BUS_SPACE_MAXADDR, 242 NULL, NULL, 243 BFE_RX_LIST_SIZE, 244 1, 245 BUS_SPACE_MAXSIZE_32BIT, 246 0, 247 NULL, NULL, 248 &sc->bfe_rx_tag); 249 250 if (error) { 251 device_printf(dev, "could not allocate dma tag\n"); 252 return (ENOMEM); 253 } 254 255 /* tag for mbufs */ 256 error = bus_dma_tag_create(sc->bfe_parent_tag, 257 ETHER_ALIGN, 0, 258 BUS_SPACE_MAXADDR, 259 BUS_SPACE_MAXADDR, 260 NULL, NULL, 261 MCLBYTES, 262 1, 263 BUS_SPACE_MAXSIZE_32BIT, 264 BUS_DMA_ALLOCNOW, 265 NULL, NULL, 266 &sc->bfe_tag); 267 268 if (error) { 269 device_printf(dev, "could not allocate dma tag\n"); 270 return (ENOMEM); 271 } 272 273 /* pre allocate dmamaps for RX list */ 274 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 275 error = bus_dmamap_create(sc->bfe_tag, 0, 276 &sc->bfe_rx_ring[i].bfe_map); 277 if (error) { 278 device_printf(dev, "cannot create DMA map for RX\n"); 279 return (ENOMEM); 280 } 281 } 282 283 /* pre allocate dmamaps for TX list */ 284 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 285 error = bus_dmamap_create(sc->bfe_tag, 0, 286 &sc->bfe_tx_ring[i].bfe_map); 287 if (error) { 288 device_printf(dev, "cannot create DMA map for TX\n"); 289 return (ENOMEM); 290 } 291 } 292 293 /* Alloc dma for rx ring */ 294 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 295 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 296 297 if(error) 298 return (ENOMEM); 299 300 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 301 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 302 sc->bfe_rx_list, sizeof(struct bfe_desc), 303 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 304 305 if(error) 306 return (ENOMEM); 307 308 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 309 310 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 311 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 312 if (error) 313 return (ENOMEM); 314 315 316 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 317 sc->bfe_tx_list, sizeof(struct bfe_desc), 318 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 319 if(error) 320 return (ENOMEM); 321 322 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 323 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 324 325 return (0); 326 } 327 328 static int 329 bfe_attach(device_t dev) 330 { 331 struct ifnet *ifp = NULL; 332 struct bfe_softc *sc; 333 int unit, error = 0, rid; 334 335 sc = device_get_softc(dev); 336 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 337 MTX_DEF); 338 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 339 340 unit = device_get_unit(dev); 341 sc->bfe_dev = dev; 342 sc->bfe_unit = unit; 343 344 /* 345 * Map control/status registers. 346 */ 347 pci_enable_busmaster(dev); 348 349 rid = BFE_PCI_MEMLO; 350 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 351 RF_ACTIVE); 352 if (sc->bfe_res == NULL) { 353 printf ("bfe%d: couldn't map memory\n", unit); 354 error = ENXIO; 355 goto fail; 356 } 357 358 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 359 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 360 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 361 362 /* Allocate interrupt */ 363 rid = 0; 364 365 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 366 RF_SHAREABLE | RF_ACTIVE); 367 if (sc->bfe_irq == NULL) { 368 printf("bfe%d: couldn't map interrupt\n", unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 if (bfe_dma_alloc(dev)) { 374 printf("bfe%d: failed to allocate DMA resources\n", 375 sc->bfe_unit); 376 error = ENXIO; 377 goto fail; 378 } 379 380 /* Set up ifnet structure */ 381 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 382 if (ifp == NULL) { 383 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 384 error = ENOSPC; 385 goto fail; 386 } 387 ifp->if_softc = sc; 388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 390 ifp->if_ioctl = bfe_ioctl; 391 ifp->if_start = bfe_start; 392 ifp->if_init = bfe_init; 393 ifp->if_mtu = ETHERMTU; 394 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 395 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 396 IFQ_SET_READY(&ifp->if_snd); 397 398 bfe_get_config(sc); 399 400 /* Reset the chip and turn on the PHY */ 401 BFE_LOCK(sc); 402 bfe_chip_reset(sc); 403 BFE_UNLOCK(sc); 404 405 if (mii_phy_probe(dev, &sc->bfe_miibus, 406 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 407 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 408 error = ENXIO; 409 goto fail; 410 } 411 412 ether_ifattach(ifp, sc->bfe_enaddr); 413 414 /* 415 * Tell the upper layer(s) we support long frames. 416 */ 417 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 418 ifp->if_capabilities |= IFCAP_VLAN_MTU; 419 ifp->if_capenable |= IFCAP_VLAN_MTU; 420 421 /* 422 * Hook interrupt last to avoid having to lock softc 423 */ 424 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 425 NULL, bfe_intr, sc, &sc->bfe_intrhand); 426 427 if (error) { 428 printf("bfe%d: couldn't set up irq\n", unit); 429 goto fail; 430 } 431 fail: 432 if (error) 433 bfe_release_resources(sc); 434 return (error); 435 } 436 437 static int 438 bfe_detach(device_t dev) 439 { 440 struct bfe_softc *sc; 441 struct ifnet *ifp; 442 443 sc = device_get_softc(dev); 444 445 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 446 447 ifp = sc->bfe_ifp; 448 449 if (device_is_attached(dev)) { 450 BFE_LOCK(sc); 451 bfe_stop(sc); 452 BFE_UNLOCK(sc); 453 callout_drain(&sc->bfe_stat_co); 454 if (ifp != NULL) 455 ether_ifdetach(ifp); 456 } 457 458 bfe_chip_reset(sc); 459 460 bus_generic_detach(dev); 461 if(sc->bfe_miibus != NULL) 462 device_delete_child(dev, sc->bfe_miibus); 463 464 bfe_release_resources(sc); 465 mtx_destroy(&sc->bfe_mtx); 466 467 return (0); 468 } 469 470 /* 471 * Stop all chip I/O so that the kernel's probe routines don't 472 * get confused by errant DMAs when rebooting. 473 */ 474 static int 475 bfe_shutdown(device_t dev) 476 { 477 struct bfe_softc *sc; 478 479 sc = device_get_softc(dev); 480 BFE_LOCK(sc); 481 bfe_stop(sc); 482 483 BFE_UNLOCK(sc); 484 485 return (0); 486 } 487 488 static int 489 bfe_suspend(device_t dev) 490 { 491 struct bfe_softc *sc; 492 493 sc = device_get_softc(dev); 494 BFE_LOCK(sc); 495 bfe_stop(sc); 496 BFE_UNLOCK(sc); 497 498 return (0); 499 } 500 501 static int 502 bfe_resume(device_t dev) 503 { 504 struct bfe_softc *sc; 505 struct ifnet *ifp; 506 507 sc = device_get_softc(dev); 508 ifp = sc->bfe_ifp; 509 BFE_LOCK(sc); 510 bfe_chip_reset(sc); 511 if (ifp->if_flags & IFF_UP) { 512 bfe_init_locked(sc); 513 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 514 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 515 bfe_start_locked(ifp); 516 } 517 BFE_UNLOCK(sc); 518 519 return (0); 520 } 521 522 static int 523 bfe_miibus_readreg(device_t dev, int phy, int reg) 524 { 525 struct bfe_softc *sc; 526 u_int32_t ret; 527 528 sc = device_get_softc(dev); 529 if(phy != sc->bfe_phyaddr) 530 return (0); 531 bfe_readphy(sc, reg, &ret); 532 533 return (ret); 534 } 535 536 static int 537 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 538 { 539 struct bfe_softc *sc; 540 541 sc = device_get_softc(dev); 542 if(phy != sc->bfe_phyaddr) 543 return (0); 544 bfe_writephy(sc, reg, val); 545 546 return (0); 547 } 548 549 static void 550 bfe_miibus_statchg(device_t dev) 551 { 552 struct bfe_softc *sc; 553 struct mii_data *mii; 554 u_int32_t val, flow; 555 556 sc = device_get_softc(dev); 557 mii = device_get_softc(sc->bfe_miibus); 558 559 if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 560 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 561 sc->bfe_link = 1; 562 } else 563 sc->bfe_link = 0; 564 565 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 566 val = CSR_READ_4(sc, BFE_TX_CTRL); 567 val &= ~BFE_TX_DUPLEX; 568 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 569 val |= BFE_TX_DUPLEX; 570 flow = 0; 571 #ifdef notyet 572 flow = CSR_READ_4(sc, BFE_RXCONF); 573 flow &= ~BFE_RXCONF_FLOW; 574 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 575 IFM_ETH_RXPAUSE) != 0) 576 flow |= BFE_RXCONF_FLOW; 577 CSR_WRITE_4(sc, BFE_RXCONF, flow); 578 /* 579 * It seems that the hardware has Tx pause issues 580 * so enable only Rx pause. 581 */ 582 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 583 flow &= ~BFE_FLOW_PAUSE_ENAB; 584 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 585 #endif 586 } 587 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 588 } 589 590 static void 591 bfe_tx_ring_free(struct bfe_softc *sc) 592 { 593 int i; 594 595 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 596 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 597 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 598 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 599 bus_dmamap_unload(sc->bfe_tag, 600 sc->bfe_tx_ring[i].bfe_map); 601 } 602 } 603 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 604 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 605 } 606 607 static void 608 bfe_rx_ring_free(struct bfe_softc *sc) 609 { 610 int i; 611 612 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 613 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 614 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 615 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 616 bus_dmamap_unload(sc->bfe_tag, 617 sc->bfe_rx_ring[i].bfe_map); 618 } 619 } 620 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 621 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 622 } 623 624 static int 625 bfe_list_rx_init(struct bfe_softc *sc) 626 { 627 int i; 628 629 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 630 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 631 return (ENOBUFS); 632 } 633 634 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 635 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 636 637 sc->bfe_rx_cons = 0; 638 639 return (0); 640 } 641 642 static int 643 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 644 { 645 struct bfe_rxheader *rx_header; 646 struct bfe_desc *d; 647 struct bfe_data *r; 648 u_int32_t ctrl; 649 int error; 650 651 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 652 return (EINVAL); 653 654 if(m == NULL) { 655 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 656 if(m == NULL) 657 return (ENOBUFS); 658 m->m_len = m->m_pkthdr.len = MCLBYTES; 659 } 660 else 661 m->m_data = m->m_ext.ext_buf; 662 663 rx_header = mtod(m, struct bfe_rxheader *); 664 rx_header->len = 0; 665 rx_header->flags = 0; 666 667 /* Map the mbuf into DMA */ 668 sc->bfe_rx_cnt = c; 669 d = &sc->bfe_rx_list[c]; 670 r = &sc->bfe_rx_ring[c]; 671 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 672 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 673 if (error) 674 printf("Serious error: bfe failed to map RX buffer\n"); 675 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 676 677 ctrl = ETHER_MAX_LEN + 32; 678 679 if(c == BFE_RX_LIST_CNT - 1) 680 ctrl |= BFE_DESC_EOT; 681 682 d->bfe_ctrl = ctrl; 683 r->bfe_mbuf = m; 684 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 685 return (0); 686 } 687 688 static void 689 bfe_get_config(struct bfe_softc *sc) 690 { 691 u_int8_t eeprom[128]; 692 693 bfe_read_eeprom(sc, eeprom); 694 695 sc->bfe_enaddr[0] = eeprom[79]; 696 sc->bfe_enaddr[1] = eeprom[78]; 697 sc->bfe_enaddr[2] = eeprom[81]; 698 sc->bfe_enaddr[3] = eeprom[80]; 699 sc->bfe_enaddr[4] = eeprom[83]; 700 sc->bfe_enaddr[5] = eeprom[82]; 701 702 sc->bfe_phyaddr = eeprom[90] & 0x1f; 703 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 704 705 sc->bfe_core_unit = 0; 706 sc->bfe_dma_offset = BFE_PCI_DMA; 707 } 708 709 static void 710 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 711 { 712 u_int32_t bar_orig, pci_rev, val; 713 714 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 715 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 716 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 717 718 val = CSR_READ_4(sc, BFE_SBINTVEC); 719 val |= cores; 720 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 721 722 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 723 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 724 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 725 726 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 727 } 728 729 static void 730 bfe_clear_stats(struct bfe_softc *sc) 731 { 732 u_long reg; 733 734 BFE_LOCK_ASSERT(sc); 735 736 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 737 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 738 CSR_READ_4(sc, reg); 739 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 740 CSR_READ_4(sc, reg); 741 } 742 743 static int 744 bfe_resetphy(struct bfe_softc *sc) 745 { 746 u_int32_t val; 747 748 bfe_writephy(sc, 0, BMCR_RESET); 749 DELAY(100); 750 bfe_readphy(sc, 0, &val); 751 if (val & BMCR_RESET) { 752 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 753 return (ENXIO); 754 } 755 return (0); 756 } 757 758 static void 759 bfe_chip_halt(struct bfe_softc *sc) 760 { 761 BFE_LOCK_ASSERT(sc); 762 /* disable interrupts - not that it actually does..*/ 763 CSR_WRITE_4(sc, BFE_IMASK, 0); 764 CSR_READ_4(sc, BFE_IMASK); 765 766 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 767 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 768 769 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 770 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 771 DELAY(10); 772 } 773 774 static void 775 bfe_chip_reset(struct bfe_softc *sc) 776 { 777 u_int32_t val; 778 779 BFE_LOCK_ASSERT(sc); 780 781 /* Set the interrupt vector for the enet core */ 782 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 783 784 /* is core up? */ 785 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 786 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 787 if (val == BFE_CLOCK) { 788 /* It is, so shut it down */ 789 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 790 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 791 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 792 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 793 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 794 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 795 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 796 100, 0); 797 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 798 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 799 } 800 801 bfe_core_reset(sc); 802 bfe_clear_stats(sc); 803 804 /* 805 * We want the phy registers to be accessible even when 806 * the driver is "downed" so initialize MDC preamble, frequency, 807 * and whether internal or external phy here. 808 */ 809 810 /* 4402 has 62.5Mhz SB clock and internal phy */ 811 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 812 813 /* Internal or external PHY? */ 814 val = CSR_READ_4(sc, BFE_DEVCTRL); 815 if(!(val & BFE_IPP)) 816 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 817 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 818 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 819 DELAY(100); 820 } 821 822 /* Enable CRC32 generation and set proper LED modes */ 823 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 824 825 /* Reset or clear powerdown control bit */ 826 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 827 828 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 829 BFE_LAZY_FC_MASK)); 830 831 /* 832 * We don't want lazy interrupts, so just send them at 833 * the end of a frame, please 834 */ 835 BFE_OR(sc, BFE_RCV_LAZY, 0); 836 837 /* Set max lengths, accounting for VLAN tags */ 838 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 839 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 840 841 /* Set watermark XXX - magic */ 842 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 843 844 /* 845 * Initialise DMA channels 846 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 847 */ 848 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 849 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 850 851 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 852 BFE_RX_CTRL_ENABLE); 853 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 854 855 bfe_resetphy(sc); 856 bfe_setupphy(sc); 857 } 858 859 static void 860 bfe_core_disable(struct bfe_softc *sc) 861 { 862 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 863 return; 864 865 /* 866 * Set reject, wait for it set, then wait for the core to stop 867 * being busy, then set reset and reject and enable the clocks. 868 */ 869 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 870 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 871 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 872 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 873 BFE_RESET)); 874 CSR_READ_4(sc, BFE_SBTMSLOW); 875 DELAY(10); 876 /* Leave reset and reject set */ 877 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 878 DELAY(10); 879 } 880 881 static void 882 bfe_core_reset(struct bfe_softc *sc) 883 { 884 u_int32_t val; 885 886 /* Disable the core */ 887 bfe_core_disable(sc); 888 889 /* and bring it back up */ 890 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 891 CSR_READ_4(sc, BFE_SBTMSLOW); 892 DELAY(10); 893 894 /* Chip bug, clear SERR, IB and TO if they are set. */ 895 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 896 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 897 val = CSR_READ_4(sc, BFE_SBIMSTATE); 898 if (val & (BFE_IBE | BFE_TO)) 899 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 900 901 /* Clear reset and allow it to move through the core */ 902 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 903 CSR_READ_4(sc, BFE_SBTMSLOW); 904 DELAY(10); 905 906 /* Leave the clock set */ 907 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 908 CSR_READ_4(sc, BFE_SBTMSLOW); 909 DELAY(10); 910 } 911 912 static void 913 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 914 { 915 u_int32_t val; 916 917 val = ((u_int32_t) data[2]) << 24; 918 val |= ((u_int32_t) data[3]) << 16; 919 val |= ((u_int32_t) data[4]) << 8; 920 val |= ((u_int32_t) data[5]); 921 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 922 val = (BFE_CAM_HI_VALID | 923 (((u_int32_t) data[0]) << 8) | 924 (((u_int32_t) data[1]))); 925 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 926 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 927 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 928 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 929 } 930 931 static void 932 bfe_set_rx_mode(struct bfe_softc *sc) 933 { 934 struct ifnet *ifp = sc->bfe_ifp; 935 struct ifmultiaddr *ifma; 936 u_int32_t val; 937 int i = 0; 938 939 val = CSR_READ_4(sc, BFE_RXCONF); 940 941 if (ifp->if_flags & IFF_PROMISC) 942 val |= BFE_RXCONF_PROMISC; 943 else 944 val &= ~BFE_RXCONF_PROMISC; 945 946 if (ifp->if_flags & IFF_BROADCAST) 947 val &= ~BFE_RXCONF_DBCAST; 948 else 949 val |= BFE_RXCONF_DBCAST; 950 951 952 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 953 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 954 955 if (ifp->if_flags & IFF_ALLMULTI) 956 val |= BFE_RXCONF_ALLMULTI; 957 else { 958 val &= ~BFE_RXCONF_ALLMULTI; 959 IF_ADDR_LOCK(ifp); 960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 961 if (ifma->ifma_addr->sa_family != AF_LINK) 962 continue; 963 bfe_cam_write(sc, 964 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 965 } 966 IF_ADDR_UNLOCK(ifp); 967 } 968 969 CSR_WRITE_4(sc, BFE_RXCONF, val); 970 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 971 } 972 973 static void 974 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 975 { 976 u_int32_t *ptr; 977 978 ptr = arg; 979 *ptr = segs->ds_addr; 980 } 981 982 static void 983 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 984 { 985 struct bfe_desc *d; 986 987 d = arg; 988 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 989 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 990 } 991 992 static void 993 bfe_release_resources(struct bfe_softc *sc) 994 { 995 device_t dev; 996 int i; 997 998 dev = sc->bfe_dev; 999 1000 if (sc->bfe_vpd_prodname != NULL) 1001 free(sc->bfe_vpd_prodname, M_DEVBUF); 1002 1003 if (sc->bfe_vpd_readonly != NULL) 1004 free(sc->bfe_vpd_readonly, M_DEVBUF); 1005 1006 if (sc->bfe_intrhand != NULL) 1007 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 1008 1009 if (sc->bfe_irq != NULL) 1010 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1011 1012 if (sc->bfe_res != NULL) 1013 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 1014 1015 if (sc->bfe_ifp != NULL) 1016 if_free(sc->bfe_ifp); 1017 1018 if(sc->bfe_tx_tag != NULL) { 1019 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1020 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1021 sc->bfe_tx_map); 1022 bus_dma_tag_destroy(sc->bfe_tx_tag); 1023 sc->bfe_tx_tag = NULL; 1024 } 1025 1026 if(sc->bfe_rx_tag != NULL) { 1027 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1028 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1029 sc->bfe_rx_map); 1030 bus_dma_tag_destroy(sc->bfe_rx_tag); 1031 sc->bfe_rx_tag = NULL; 1032 } 1033 1034 if(sc->bfe_tag != NULL) { 1035 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1036 bus_dmamap_destroy(sc->bfe_tag, 1037 sc->bfe_tx_ring[i].bfe_map); 1038 } 1039 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1040 bus_dmamap_destroy(sc->bfe_tag, 1041 sc->bfe_rx_ring[i].bfe_map); 1042 } 1043 bus_dma_tag_destroy(sc->bfe_tag); 1044 sc->bfe_tag = NULL; 1045 } 1046 1047 if(sc->bfe_parent_tag != NULL) 1048 bus_dma_tag_destroy(sc->bfe_parent_tag); 1049 1050 return; 1051 } 1052 1053 static void 1054 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1055 { 1056 long i; 1057 u_int16_t *ptr = (u_int16_t *)data; 1058 1059 for(i = 0; i < 128; i += 2) 1060 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1061 } 1062 1063 static int 1064 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1065 u_long timeout, const int clear) 1066 { 1067 u_long i; 1068 1069 for (i = 0; i < timeout; i++) { 1070 u_int32_t val = CSR_READ_4(sc, reg); 1071 1072 if (clear && !(val & bit)) 1073 break; 1074 if (!clear && (val & bit)) 1075 break; 1076 DELAY(10); 1077 } 1078 if (i == timeout) { 1079 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1080 "%x to %s.\n", sc->bfe_unit, bit, reg, 1081 (clear ? "clear" : "set")); 1082 return (-1); 1083 } 1084 return (0); 1085 } 1086 1087 static int 1088 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1089 { 1090 int err; 1091 1092 /* Clear MII ISR */ 1093 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1094 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1095 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1096 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1097 (reg << BFE_MDIO_RA_SHIFT) | 1098 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1099 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1100 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1101 1102 return (err); 1103 } 1104 1105 static int 1106 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1107 { 1108 int status; 1109 1110 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1111 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1112 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1113 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1114 (reg << BFE_MDIO_RA_SHIFT) | 1115 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1116 (val & BFE_MDIO_DATA_DATA))); 1117 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1118 1119 return (status); 1120 } 1121 1122 /* 1123 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1124 * twice 1125 */ 1126 static int 1127 bfe_setupphy(struct bfe_softc *sc) 1128 { 1129 u_int32_t val; 1130 1131 /* Enable activity LED */ 1132 bfe_readphy(sc, 26, &val); 1133 bfe_writephy(sc, 26, val & 0x7fff); 1134 bfe_readphy(sc, 26, &val); 1135 1136 /* Enable traffic meter LED mode */ 1137 bfe_readphy(sc, 27, &val); 1138 bfe_writephy(sc, 27, val | (1 << 6)); 1139 1140 return (0); 1141 } 1142 1143 static void 1144 bfe_stats_update(struct bfe_softc *sc) 1145 { 1146 u_long reg; 1147 u_int32_t *val; 1148 1149 val = &sc->bfe_hwstats.tx_good_octets; 1150 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1151 *val++ += CSR_READ_4(sc, reg); 1152 } 1153 val = &sc->bfe_hwstats.rx_good_octets; 1154 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1155 *val++ += CSR_READ_4(sc, reg); 1156 } 1157 } 1158 1159 static void 1160 bfe_txeof(struct bfe_softc *sc) 1161 { 1162 struct ifnet *ifp; 1163 int i, chipidx; 1164 1165 BFE_LOCK_ASSERT(sc); 1166 1167 ifp = sc->bfe_ifp; 1168 1169 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1170 chipidx /= sizeof(struct bfe_desc); 1171 1172 i = sc->bfe_tx_cons; 1173 /* Go through the mbufs and free those that have been transmitted */ 1174 while(i != chipidx) { 1175 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1176 if(r->bfe_mbuf != NULL) { 1177 ifp->if_opackets++; 1178 m_freem(r->bfe_mbuf); 1179 r->bfe_mbuf = NULL; 1180 } 1181 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1182 sc->bfe_tx_cnt--; 1183 BFE_INC(i, BFE_TX_LIST_CNT); 1184 } 1185 1186 if(i != sc->bfe_tx_cons) { 1187 /* we freed up some mbufs */ 1188 sc->bfe_tx_cons = i; 1189 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1190 } 1191 1192 if (sc->bfe_tx_cnt == 0) 1193 sc->bfe_watchdog_timer = 0; 1194 } 1195 1196 /* Pass a received packet up the stack */ 1197 static void 1198 bfe_rxeof(struct bfe_softc *sc) 1199 { 1200 struct mbuf *m; 1201 struct ifnet *ifp; 1202 struct bfe_rxheader *rxheader; 1203 struct bfe_data *r; 1204 int cons; 1205 u_int32_t status, current, len, flags; 1206 1207 BFE_LOCK_ASSERT(sc); 1208 cons = sc->bfe_rx_cons; 1209 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1210 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1211 1212 ifp = sc->bfe_ifp; 1213 1214 while(current != cons) { 1215 r = &sc->bfe_rx_ring[cons]; 1216 m = r->bfe_mbuf; 1217 rxheader = mtod(m, struct bfe_rxheader*); 1218 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1219 len = rxheader->len; 1220 r->bfe_mbuf = NULL; 1221 1222 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1223 flags = rxheader->flags; 1224 1225 len -= ETHER_CRC_LEN; 1226 1227 /* flag an error and try again */ 1228 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1229 ifp->if_ierrors++; 1230 if (flags & BFE_RX_FLAG_SERR) 1231 ifp->if_collisions++; 1232 bfe_list_newbuf(sc, cons, m); 1233 BFE_INC(cons, BFE_RX_LIST_CNT); 1234 continue; 1235 } 1236 1237 /* Go past the rx header */ 1238 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1239 m_adj(m, BFE_RX_OFFSET); 1240 m->m_len = m->m_pkthdr.len = len; 1241 } else { 1242 bfe_list_newbuf(sc, cons, m); 1243 ifp->if_ierrors++; 1244 BFE_INC(cons, BFE_RX_LIST_CNT); 1245 continue; 1246 } 1247 1248 ifp->if_ipackets++; 1249 m->m_pkthdr.rcvif = ifp; 1250 BFE_UNLOCK(sc); 1251 (*ifp->if_input)(ifp, m); 1252 BFE_LOCK(sc); 1253 1254 BFE_INC(cons, BFE_RX_LIST_CNT); 1255 } 1256 sc->bfe_rx_cons = cons; 1257 } 1258 1259 static void 1260 bfe_intr(void *xsc) 1261 { 1262 struct bfe_softc *sc = xsc; 1263 struct ifnet *ifp; 1264 u_int32_t istat, imask, flag; 1265 1266 ifp = sc->bfe_ifp; 1267 1268 BFE_LOCK(sc); 1269 1270 istat = CSR_READ_4(sc, BFE_ISTAT); 1271 imask = CSR_READ_4(sc, BFE_IMASK); 1272 1273 /* 1274 * Defer unsolicited interrupts - This is necessary because setting the 1275 * chips interrupt mask register to 0 doesn't actually stop the 1276 * interrupts 1277 */ 1278 istat &= imask; 1279 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1280 CSR_READ_4(sc, BFE_ISTAT); 1281 1282 /* not expecting this interrupt, disregard it */ 1283 if(istat == 0) { 1284 BFE_UNLOCK(sc); 1285 return; 1286 } 1287 1288 if(istat & BFE_ISTAT_ERRORS) { 1289 1290 if (istat & BFE_ISTAT_DSCE) { 1291 printf("if_bfe Descriptor Error\n"); 1292 bfe_stop(sc); 1293 BFE_UNLOCK(sc); 1294 return; 1295 } 1296 1297 if (istat & BFE_ISTAT_DPE) { 1298 printf("if_bfe Descriptor Protocol Error\n"); 1299 bfe_stop(sc); 1300 BFE_UNLOCK(sc); 1301 return; 1302 } 1303 1304 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1305 if(flag & BFE_STAT_EMASK) 1306 ifp->if_oerrors++; 1307 1308 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1309 if(flag & BFE_RX_FLAG_ERRORS) 1310 ifp->if_ierrors++; 1311 1312 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1313 bfe_init_locked(sc); 1314 } 1315 1316 /* A packet was received */ 1317 if(istat & BFE_ISTAT_RX) 1318 bfe_rxeof(sc); 1319 1320 /* A packet was sent */ 1321 if(istat & BFE_ISTAT_TX) 1322 bfe_txeof(sc); 1323 1324 /* We have packets pending, fire them out */ 1325 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1326 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1327 bfe_start_locked(ifp); 1328 1329 BFE_UNLOCK(sc); 1330 } 1331 1332 static int 1333 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1334 { 1335 struct bfe_desc *d = NULL; 1336 struct bfe_data *r = NULL; 1337 struct mbuf *m; 1338 u_int32_t frag, cur, cnt = 0; 1339 int chainlen = 0; 1340 int error; 1341 1342 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1343 return (ENOBUFS); 1344 1345 /* 1346 * Count the number of frags in this chain to see if 1347 * we need to m_defrag. Since the descriptor list is shared 1348 * by all packets, we'll m_defrag long chains so that they 1349 * do not use up the entire list, even if they would fit. 1350 */ 1351 for(m = *m_head; m != NULL; m = m->m_next) 1352 chainlen++; 1353 1354 1355 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1356 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1357 m = m_defrag(*m_head, M_DONTWAIT); 1358 if (m == NULL) 1359 return (ENOBUFS); 1360 *m_head = m; 1361 } 1362 1363 /* 1364 * Start packing the mbufs in this chain into 1365 * the fragment pointers. Stop when we run out 1366 * of fragments or hit the end of the mbuf chain. 1367 */ 1368 cur = frag = *txidx; 1369 cnt = 0; 1370 1371 for(m = *m_head; m != NULL; m = m->m_next) { 1372 if(m->m_len != 0) { 1373 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1374 return (ENOBUFS); 1375 1376 d = &sc->bfe_tx_list[cur]; 1377 r = &sc->bfe_tx_ring[cur]; 1378 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1379 /* always intterupt on completion */ 1380 d->bfe_ctrl |= BFE_DESC_IOC; 1381 if(cnt == 0) 1382 /* Set start of frame */ 1383 d->bfe_ctrl |= BFE_DESC_SOF; 1384 if(cur == BFE_TX_LIST_CNT - 1) 1385 /* 1386 * Tell the chip to wrap to the start of 1387 * the descriptor list 1388 */ 1389 d->bfe_ctrl |= BFE_DESC_EOT; 1390 1391 error = bus_dmamap_load(sc->bfe_tag, 1392 r->bfe_map, mtod(m, void*), m->m_len, 1393 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1394 if (error) 1395 return (ENOBUFS); 1396 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1397 BUS_DMASYNC_PREWRITE); 1398 1399 frag = cur; 1400 BFE_INC(cur, BFE_TX_LIST_CNT); 1401 cnt++; 1402 } 1403 } 1404 1405 if (m != NULL) 1406 return (ENOBUFS); 1407 1408 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1409 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1410 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1411 1412 *txidx = cur; 1413 sc->bfe_tx_cnt += cnt; 1414 return (0); 1415 } 1416 1417 /* 1418 * Set up to transmit a packet. 1419 */ 1420 static void 1421 bfe_start(struct ifnet *ifp) 1422 { 1423 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1424 bfe_start_locked(ifp); 1425 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1426 } 1427 1428 /* 1429 * Set up to transmit a packet. The softc is already locked. 1430 */ 1431 static void 1432 bfe_start_locked(struct ifnet *ifp) 1433 { 1434 struct bfe_softc *sc; 1435 struct mbuf *m_head = NULL; 1436 int idx, queued = 0; 1437 1438 sc = ifp->if_softc; 1439 idx = sc->bfe_tx_prod; 1440 1441 BFE_LOCK_ASSERT(sc); 1442 1443 /* 1444 * Not much point trying to send if the link is down 1445 * or we have nothing to send. 1446 */ 1447 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1448 return; 1449 1450 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1451 IFF_DRV_RUNNING) 1452 return; 1453 1454 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1455 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1456 if(m_head == NULL) 1457 break; 1458 1459 /* 1460 * Pack the data into the tx ring. If we dont have 1461 * enough room, let the chip drain the ring. 1462 */ 1463 if(bfe_encap(sc, &m_head, &idx)) { 1464 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1465 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1466 break; 1467 } 1468 1469 queued++; 1470 1471 /* 1472 * If there's a BPF listener, bounce a copy of this frame 1473 * to him. 1474 */ 1475 BPF_MTAP(ifp, m_head); 1476 } 1477 1478 if (queued) { 1479 sc->bfe_tx_prod = idx; 1480 /* Transmit - twice due to apparent hardware bug */ 1481 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1482 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1483 1484 /* 1485 * Set a timeout in case the chip goes out to lunch. 1486 */ 1487 sc->bfe_watchdog_timer = 5; 1488 } 1489 } 1490 1491 static void 1492 bfe_init(void *xsc) 1493 { 1494 BFE_LOCK((struct bfe_softc *)xsc); 1495 bfe_init_locked(xsc); 1496 BFE_UNLOCK((struct bfe_softc *)xsc); 1497 } 1498 1499 static void 1500 bfe_init_locked(void *xsc) 1501 { 1502 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1503 struct ifnet *ifp = sc->bfe_ifp; 1504 struct mii_data *mii; 1505 1506 BFE_LOCK_ASSERT(sc); 1507 1508 mii = device_get_softc(sc->bfe_miibus); 1509 1510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1511 return; 1512 1513 bfe_stop(sc); 1514 bfe_chip_reset(sc); 1515 1516 if (bfe_list_rx_init(sc) == ENOBUFS) { 1517 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1518 sc->bfe_unit); 1519 bfe_stop(sc); 1520 return; 1521 } 1522 1523 bfe_set_rx_mode(sc); 1524 1525 /* Enable the chip and core */ 1526 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1527 /* Enable interrupts */ 1528 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1529 1530 /* Clear link state and change media. */ 1531 sc->bfe_link = 0; 1532 mii_mediachg(mii); 1533 1534 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1535 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1536 1537 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1538 } 1539 1540 /* 1541 * Set media options. 1542 */ 1543 static int 1544 bfe_ifmedia_upd(struct ifnet *ifp) 1545 { 1546 struct bfe_softc *sc; 1547 struct mii_data *mii; 1548 int error; 1549 1550 sc = ifp->if_softc; 1551 BFE_LOCK(sc); 1552 1553 mii = device_get_softc(sc->bfe_miibus); 1554 if (mii->mii_instance) { 1555 struct mii_softc *miisc; 1556 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1557 miisc = LIST_NEXT(miisc, mii_list)) 1558 mii_phy_reset(miisc); 1559 } 1560 error = mii_mediachg(mii); 1561 BFE_UNLOCK(sc); 1562 1563 return (error); 1564 } 1565 1566 /* 1567 * Report current media status. 1568 */ 1569 static void 1570 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1571 { 1572 struct bfe_softc *sc = ifp->if_softc; 1573 struct mii_data *mii; 1574 1575 BFE_LOCK(sc); 1576 mii = device_get_softc(sc->bfe_miibus); 1577 mii_pollstat(mii); 1578 ifmr->ifm_active = mii->mii_media_active; 1579 ifmr->ifm_status = mii->mii_media_status; 1580 BFE_UNLOCK(sc); 1581 } 1582 1583 static int 1584 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1585 { 1586 struct bfe_softc *sc = ifp->if_softc; 1587 struct ifreq *ifr = (struct ifreq *) data; 1588 struct mii_data *mii; 1589 int error = 0; 1590 1591 switch(command) { 1592 case SIOCSIFFLAGS: 1593 BFE_LOCK(sc); 1594 if(ifp->if_flags & IFF_UP) 1595 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1596 bfe_set_rx_mode(sc); 1597 else 1598 bfe_init_locked(sc); 1599 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1600 bfe_stop(sc); 1601 BFE_UNLOCK(sc); 1602 break; 1603 case SIOCADDMULTI: 1604 case SIOCDELMULTI: 1605 BFE_LOCK(sc); 1606 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1607 bfe_set_rx_mode(sc); 1608 BFE_UNLOCK(sc); 1609 break; 1610 case SIOCGIFMEDIA: 1611 case SIOCSIFMEDIA: 1612 mii = device_get_softc(sc->bfe_miibus); 1613 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1614 command); 1615 break; 1616 default: 1617 error = ether_ioctl(ifp, command, data); 1618 break; 1619 } 1620 1621 return (error); 1622 } 1623 1624 static void 1625 bfe_watchdog(struct bfe_softc *sc) 1626 { 1627 struct ifnet *ifp; 1628 1629 BFE_LOCK_ASSERT(sc); 1630 1631 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1632 return; 1633 1634 ifp = sc->bfe_ifp; 1635 1636 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1637 1638 ifp->if_oerrors++; 1639 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1640 bfe_init_locked(sc); 1641 1642 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1643 bfe_start_locked(ifp); 1644 } 1645 1646 static void 1647 bfe_tick(void *xsc) 1648 { 1649 struct bfe_softc *sc = xsc; 1650 struct mii_data *mii; 1651 1652 BFE_LOCK_ASSERT(sc); 1653 1654 mii = device_get_softc(sc->bfe_miibus); 1655 mii_tick(mii); 1656 bfe_stats_update(sc); 1657 bfe_watchdog(sc); 1658 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1659 } 1660 1661 /* 1662 * Stop the adapter and free any mbufs allocated to the 1663 * RX and TX lists. 1664 */ 1665 static void 1666 bfe_stop(struct bfe_softc *sc) 1667 { 1668 struct ifnet *ifp; 1669 1670 BFE_LOCK_ASSERT(sc); 1671 1672 ifp = sc->bfe_ifp; 1673 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1674 sc->bfe_link = 0; 1675 callout_stop(&sc->bfe_stat_co); 1676 sc->bfe_watchdog_timer = 0; 1677 1678 bfe_chip_halt(sc); 1679 bfe_tx_ring_free(sc); 1680 bfe_rx_ring_free(sc); 1681 } 1682