xref: /freebsd/sys/dev/bfe/if_bfe.c (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
5  * and Duncan Barclay<dmlb@dmlb.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
44 
45 #include <net/bpf.h>
46 #include <net/if.h>
47 #include <net/if_var.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52 #include <net/if_vlan_var.h>
53 
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56 
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcivar.h>
59 
60 #include <machine/bus.h>
61 
62 #include <dev/bfe/if_bfereg.h>
63 
64 MODULE_DEPEND(bfe, pci, 1, 1, 1);
65 MODULE_DEPEND(bfe, ether, 1, 1, 1);
66 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
67 
68 /* "device miibus" required.  See GENERIC if you get errors here. */
69 #include "miibus_if.h"
70 
71 #define BFE_DEVDESC_MAX		64	/* Maximum device description length */
72 
73 static struct bfe_type bfe_devs[] = {
74 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
75 		"Broadcom BCM4401 Fast Ethernet" },
76 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
77 		"Broadcom BCM4401-B0 Fast Ethernet" },
78 		{ 0, 0, NULL }
79 };
80 
81 static int  bfe_probe				(device_t);
82 static int  bfe_attach				(device_t);
83 static int  bfe_detach				(device_t);
84 static int  bfe_suspend				(device_t);
85 static int  bfe_resume				(device_t);
86 static void bfe_release_resources	(struct bfe_softc *);
87 static void bfe_intr				(void *);
88 static int  bfe_encap				(struct bfe_softc *, struct mbuf **);
89 static void bfe_start				(if_t);
90 static void bfe_start_locked			(if_t);
91 static int  bfe_ioctl				(if_t, u_long, caddr_t);
92 static void bfe_init				(void *);
93 static void bfe_init_locked			(void *);
94 static void bfe_stop				(struct bfe_softc *);
95 static void bfe_watchdog			(struct bfe_softc *);
96 static int  bfe_shutdown			(device_t);
97 static void bfe_tick				(void *);
98 static void bfe_txeof				(struct bfe_softc *);
99 static void bfe_rxeof				(struct bfe_softc *);
100 static void bfe_set_rx_mode			(struct bfe_softc *);
101 static int  bfe_list_rx_init		(struct bfe_softc *);
102 static void bfe_list_tx_init		(struct bfe_softc *);
103 static void bfe_discard_buf		(struct bfe_softc *, int);
104 static int  bfe_list_newbuf			(struct bfe_softc *, int);
105 static void bfe_rx_ring_free		(struct bfe_softc *);
106 
107 static void bfe_pci_setup			(struct bfe_softc *, u_int32_t);
108 static int  bfe_ifmedia_upd			(if_t);
109 static void bfe_ifmedia_sts			(if_t, struct ifmediareq *);
110 static int  bfe_miibus_readreg		(device_t, int, int);
111 static int  bfe_miibus_writereg		(device_t, int, int, int);
112 static void bfe_miibus_statchg		(device_t);
113 static int  bfe_wait_bit			(struct bfe_softc *, u_int32_t, u_int32_t,
114 		u_long, const int);
115 static void bfe_get_config			(struct bfe_softc *sc);
116 static void bfe_read_eeprom			(struct bfe_softc *, u_int8_t *);
117 static void bfe_stats_update		(struct bfe_softc *);
118 static void bfe_clear_stats			(struct bfe_softc *);
119 static int  bfe_readphy				(struct bfe_softc *, u_int32_t, u_int32_t*);
120 static int  bfe_writephy			(struct bfe_softc *, u_int32_t, u_int32_t);
121 static int  bfe_resetphy			(struct bfe_softc *);
122 static int  bfe_setupphy			(struct bfe_softc *);
123 static void bfe_chip_reset			(struct bfe_softc *);
124 static void bfe_chip_halt			(struct bfe_softc *);
125 static void bfe_core_reset			(struct bfe_softc *);
126 static void bfe_core_disable		(struct bfe_softc *);
127 static int  bfe_dma_alloc			(struct bfe_softc *);
128 static void bfe_dma_free		(struct bfe_softc *sc);
129 static void bfe_dma_map				(void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write			(struct bfe_softc *, u_char *, int);
131 static int  sysctl_bfe_stats		(SYSCTL_HANDLER_ARGS);
132 
133 static device_method_t bfe_methods[] = {
134 	/* Device interface */
135 	DEVMETHOD(device_probe,		bfe_probe),
136 	DEVMETHOD(device_attach,	bfe_attach),
137 	DEVMETHOD(device_detach,	bfe_detach),
138 	DEVMETHOD(device_shutdown,	bfe_shutdown),
139 	DEVMETHOD(device_suspend,	bfe_suspend),
140 	DEVMETHOD(device_resume,	bfe_resume),
141 
142 	/* MII interface */
143 	DEVMETHOD(miibus_readreg,	bfe_miibus_readreg),
144 	DEVMETHOD(miibus_writereg,	bfe_miibus_writereg),
145 	DEVMETHOD(miibus_statchg,	bfe_miibus_statchg),
146 
147 	DEVMETHOD_END
148 };
149 
150 static driver_t bfe_driver = {
151 	"bfe",
152 	bfe_methods,
153 	sizeof(struct bfe_softc)
154 };
155 
156 DRIVER_MODULE(bfe, pci, bfe_driver, 0, 0);
157 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
158     nitems(bfe_devs) - 1);
159 DRIVER_MODULE(miibus, bfe, miibus_driver, 0, 0);
160 
161 /*
162  * Probe for a Broadcom 4401 chip.
163  */
164 static int
165 bfe_probe(device_t dev)
166 {
167 	struct bfe_type *t;
168 
169 	t = bfe_devs;
170 
171 	while (t->bfe_name != NULL) {
172 		if (pci_get_vendor(dev) == t->bfe_vid &&
173 		    pci_get_device(dev) == t->bfe_did) {
174 			device_set_desc(dev, t->bfe_name);
175 			return (BUS_PROBE_DEFAULT);
176 		}
177 		t++;
178 	}
179 
180 	return (ENXIO);
181 }
182 
183 struct bfe_dmamap_arg {
184 	bus_addr_t	bfe_busaddr;
185 };
186 
187 static int
188 bfe_dma_alloc(struct bfe_softc *sc)
189 {
190 	struct bfe_dmamap_arg ctx;
191 	struct bfe_rx_data *rd;
192 	struct bfe_tx_data *td;
193 	int error, i;
194 
195 	/*
196 	 * parent tag.  Apparently the chip cannot handle any DMA address
197 	 * greater than 1GB.
198 	 */
199 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
200 	    1, 0,			/* alignment, boundary */
201 	    BFE_DMA_MAXADDR, 		/* lowaddr */
202 	    BUS_SPACE_MAXADDR,		/* highaddr */
203 	    NULL, NULL,			/* filter, filterarg */
204 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
205 	    0,				/* nsegments */
206 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
207 	    0,				/* flags */
208 	    NULL, NULL,			/* lockfunc, lockarg */
209 	    &sc->bfe_parent_tag);
210 	if (error != 0) {
211 		device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
212 		goto fail;
213 	}
214 
215 	/* Create tag for Tx ring. */
216 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
217 	    BFE_TX_RING_ALIGN, 0,	/* alignment, boundary */
218 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
219 	    BUS_SPACE_MAXADDR,		/* highaddr */
220 	    NULL, NULL,			/* filter, filterarg */
221 	    BFE_TX_LIST_SIZE,		/* maxsize */
222 	    1,				/* nsegments */
223 	    BFE_TX_LIST_SIZE,		/* maxsegsize */
224 	    0,				/* flags */
225 	    NULL, NULL,			/* lockfunc, lockarg */
226 	    &sc->bfe_tx_tag);
227 	if (error != 0) {
228 		device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
229 		goto fail;
230 	}
231 
232 	/* Create tag for Rx ring. */
233 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
234 	    BFE_RX_RING_ALIGN, 0,	/* alignment, boundary */
235 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
236 	    BUS_SPACE_MAXADDR,		/* highaddr */
237 	    NULL, NULL,			/* filter, filterarg */
238 	    BFE_RX_LIST_SIZE,		/* maxsize */
239 	    1,				/* nsegments */
240 	    BFE_RX_LIST_SIZE,		/* maxsegsize */
241 	    0,				/* flags */
242 	    NULL, NULL,			/* lockfunc, lockarg */
243 	    &sc->bfe_rx_tag);
244 	if (error != 0) {
245 		device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
246 		goto fail;
247 	}
248 
249 	/* Create tag for Tx buffers. */
250 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
251 	    1, 0,			/* alignment, boundary */
252 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
253 	    BUS_SPACE_MAXADDR,		/* highaddr */
254 	    NULL, NULL,			/* filter, filterarg */
255 	    MCLBYTES * BFE_MAXTXSEGS,	/* maxsize */
256 	    BFE_MAXTXSEGS,		/* nsegments */
257 	    MCLBYTES,			/* maxsegsize */
258 	    0,				/* flags */
259 	    NULL, NULL,			/* lockfunc, lockarg */
260 	    &sc->bfe_txmbuf_tag);
261 	if (error != 0) {
262 		device_printf(sc->bfe_dev,
263 		    "cannot create Tx buffer DMA tag.\n");
264 		goto fail;
265 	}
266 
267 	/* Create tag for Rx buffers. */
268 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
269 	    1, 0,			/* alignment, boundary */
270 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
271 	    BUS_SPACE_MAXADDR,		/* highaddr */
272 	    NULL, NULL,			/* filter, filterarg */
273 	    MCLBYTES,			/* maxsize */
274 	    1,				/* nsegments */
275 	    MCLBYTES,			/* maxsegsize */
276 	    0,				/* flags */
277 	    NULL, NULL,			/* lockfunc, lockarg */
278 	    &sc->bfe_rxmbuf_tag);
279 	if (error != 0) {
280 		device_printf(sc->bfe_dev,
281 		    "cannot create Rx buffer DMA tag.\n");
282 		goto fail;
283 	}
284 
285 	/* Allocate DMA'able memory and load DMA map. */
286 	error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
287 	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
288 	if (error != 0) {
289 		device_printf(sc->bfe_dev,
290 		    "cannot allocate DMA'able memory for Tx ring.\n");
291 		goto fail;
292 	}
293 	ctx.bfe_busaddr = 0;
294 	error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
295 	    sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
296 	    BUS_DMA_NOWAIT);
297 	if (error != 0 || ctx.bfe_busaddr == 0) {
298 		device_printf(sc->bfe_dev,
299 		    "cannot load DMA'able memory for Tx ring.\n");
300 		goto fail;
301 	}
302 	sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
303 
304 	error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
305 	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
306 	if (error != 0) {
307 		device_printf(sc->bfe_dev,
308 		    "cannot allocate DMA'able memory for Rx ring.\n");
309 		goto fail;
310 	}
311 	ctx.bfe_busaddr = 0;
312 	error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
313 	    sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
314 	    BUS_DMA_NOWAIT);
315 	if (error != 0 || ctx.bfe_busaddr == 0) {
316 		device_printf(sc->bfe_dev,
317 		    "cannot load DMA'able memory for Rx ring.\n");
318 		goto fail;
319 	}
320 	sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
321 
322 	/* Create DMA maps for Tx buffers. */
323 	for (i = 0; i < BFE_TX_LIST_CNT; i++) {
324 		td = &sc->bfe_tx_ring[i];
325 		td->bfe_mbuf = NULL;
326 		td->bfe_map = NULL;
327 		error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
328 		if (error != 0) {
329 			device_printf(sc->bfe_dev,
330 			    "cannot create DMA map for Tx.\n");
331 			goto fail;
332 		}
333 	}
334 
335 	/* Create spare DMA map for Rx buffers. */
336 	error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
337 	if (error != 0) {
338 		device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
339 		goto fail;
340 	}
341 	/* Create DMA maps for Rx buffers. */
342 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
343 		rd = &sc->bfe_rx_ring[i];
344 		rd->bfe_mbuf = NULL;
345 		rd->bfe_map = NULL;
346 		rd->bfe_ctrl = 0;
347 		error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
348 		if (error != 0) {
349 			device_printf(sc->bfe_dev,
350 			    "cannot create DMA map for Rx.\n");
351 			goto fail;
352 		}
353 	}
354 
355 fail:
356 	return (error);
357 }
358 
359 static void
360 bfe_dma_free(struct bfe_softc *sc)
361 {
362 	struct bfe_tx_data *td;
363 	struct bfe_rx_data *rd;
364 	int i;
365 
366 	/* Tx ring. */
367 	if (sc->bfe_tx_tag != NULL) {
368 		if (sc->bfe_tx_dma != 0)
369 			bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
370 		if (sc->bfe_tx_list != NULL)
371 			bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
372 			    sc->bfe_tx_map);
373 		sc->bfe_tx_dma = 0;
374 		sc->bfe_tx_list = NULL;
375 		bus_dma_tag_destroy(sc->bfe_tx_tag);
376 		sc->bfe_tx_tag = NULL;
377 	}
378 
379 	/* Rx ring. */
380 	if (sc->bfe_rx_tag != NULL) {
381 		if (sc->bfe_rx_dma != 0)
382 			bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
383 		if (sc->bfe_rx_list != NULL)
384 			bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
385 			    sc->bfe_rx_map);
386 		sc->bfe_rx_dma = 0;
387 		sc->bfe_rx_list = NULL;
388 		bus_dma_tag_destroy(sc->bfe_rx_tag);
389 		sc->bfe_rx_tag = NULL;
390 	}
391 
392 	/* Tx buffers. */
393 	if (sc->bfe_txmbuf_tag != NULL) {
394 		for (i = 0; i < BFE_TX_LIST_CNT; i++) {
395 			td = &sc->bfe_tx_ring[i];
396 			if (td->bfe_map != NULL) {
397 				bus_dmamap_destroy(sc->bfe_txmbuf_tag,
398 				    td->bfe_map);
399 				td->bfe_map = NULL;
400 			}
401 		}
402 		bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
403 		sc->bfe_txmbuf_tag = NULL;
404 	}
405 
406 	/* Rx buffers. */
407 	if (sc->bfe_rxmbuf_tag != NULL) {
408 		for (i = 0; i < BFE_RX_LIST_CNT; i++) {
409 			rd = &sc->bfe_rx_ring[i];
410 			if (rd->bfe_map != NULL) {
411 				bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
412 				    rd->bfe_map);
413 				rd->bfe_map = NULL;
414 			}
415 		}
416 		if (sc->bfe_rx_sparemap != NULL) {
417 			bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
418 			    sc->bfe_rx_sparemap);
419 			sc->bfe_rx_sparemap = NULL;
420 		}
421 		bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
422 		sc->bfe_rxmbuf_tag = NULL;
423 	}
424 
425 	if (sc->bfe_parent_tag != NULL) {
426 		bus_dma_tag_destroy(sc->bfe_parent_tag);
427 		sc->bfe_parent_tag = NULL;
428 	}
429 }
430 
431 static int
432 bfe_attach(device_t dev)
433 {
434 	if_t ifp = NULL;
435 	struct bfe_softc *sc;
436 	int error = 0, rid;
437 
438 	sc = device_get_softc(dev);
439 	mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 			MTX_DEF);
441 	callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
442 
443 	sc->bfe_dev = dev;
444 
445 	/*
446 	 * Map control/status registers.
447 	 */
448 	pci_enable_busmaster(dev);
449 
450 	rid = PCIR_BAR(0);
451 	sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
452 			RF_ACTIVE);
453 	if (sc->bfe_res == NULL) {
454 		device_printf(dev, "couldn't map memory\n");
455 		error = ENXIO;
456 		goto fail;
457 	}
458 
459 	/* Allocate interrupt */
460 	rid = 0;
461 
462 	sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
463 			RF_SHAREABLE | RF_ACTIVE);
464 	if (sc->bfe_irq == NULL) {
465 		device_printf(dev, "couldn't map interrupt\n");
466 		error = ENXIO;
467 		goto fail;
468 	}
469 
470 	if (bfe_dma_alloc(sc) != 0) {
471 		device_printf(dev, "failed to allocate DMA resources\n");
472 		error = ENXIO;
473 		goto fail;
474 	}
475 
476 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
477 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
478 	    "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
479 	    sysctl_bfe_stats, "I", "Statistics");
480 
481 	/* Set up ifnet structure */
482 	ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
483 	if (ifp == NULL) {
484 		device_printf(dev, "failed to if_alloc()\n");
485 		error = ENOSPC;
486 		goto fail;
487 	}
488 	if_setsoftc(ifp, sc);
489 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
490 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
491 	if_setioctlfn(ifp, bfe_ioctl);
492 	if_setstartfn(ifp, bfe_start);
493 	if_setinitfn(ifp, bfe_init);
494 	if_setsendqlen(ifp, BFE_TX_QLEN);
495 	if_setsendqready(ifp);
496 
497 	bfe_get_config(sc);
498 
499 	/* Reset the chip and turn on the PHY */
500 	BFE_LOCK(sc);
501 	bfe_chip_reset(sc);
502 	BFE_UNLOCK(sc);
503 
504 	error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
505 	    bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
506 	    0);
507 	if (error != 0) {
508 		device_printf(dev, "attaching PHYs failed\n");
509 		goto fail;
510 	}
511 
512 	ether_ifattach(ifp, sc->bfe_enaddr);
513 
514 	/*
515 	 * Tell the upper layer(s) we support long frames.
516 	 */
517 	if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
518 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
519 	if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
520 
521 	/*
522 	 * Hook interrupt last to avoid having to lock softc
523 	 */
524 	error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
525 			NULL, bfe_intr, sc, &sc->bfe_intrhand);
526 
527 	if (error) {
528 		device_printf(dev, "couldn't set up irq\n");
529 		goto fail;
530 	}
531 fail:
532 	if (error != 0)
533 		bfe_detach(dev);
534 	return (error);
535 }
536 
537 static int
538 bfe_detach(device_t dev)
539 {
540 	struct bfe_softc *sc;
541 	if_t ifp;
542 
543 	sc = device_get_softc(dev);
544 
545 	ifp = sc->bfe_ifp;
546 
547 	if (device_is_attached(dev)) {
548 		BFE_LOCK(sc);
549 		sc->bfe_flags |= BFE_FLAG_DETACH;
550 		bfe_stop(sc);
551 		BFE_UNLOCK(sc);
552 		callout_drain(&sc->bfe_stat_co);
553 		if (ifp != NULL)
554 			ether_ifdetach(ifp);
555 	}
556 
557 	BFE_LOCK(sc);
558 	bfe_chip_reset(sc);
559 	BFE_UNLOCK(sc);
560 
561 	bus_generic_detach(dev);
562 	if (sc->bfe_miibus != NULL)
563 		device_delete_child(dev, sc->bfe_miibus);
564 
565 	bfe_release_resources(sc);
566 	bfe_dma_free(sc);
567 	mtx_destroy(&sc->bfe_mtx);
568 
569 	return (0);
570 }
571 
572 /*
573  * Stop all chip I/O so that the kernel's probe routines don't
574  * get confused by errant DMAs when rebooting.
575  */
576 static int
577 bfe_shutdown(device_t dev)
578 {
579 	struct bfe_softc *sc;
580 
581 	sc = device_get_softc(dev);
582 	BFE_LOCK(sc);
583 	bfe_stop(sc);
584 
585 	BFE_UNLOCK(sc);
586 
587 	return (0);
588 }
589 
590 static int
591 bfe_suspend(device_t dev)
592 {
593 	struct bfe_softc *sc;
594 
595 	sc = device_get_softc(dev);
596 	BFE_LOCK(sc);
597 	bfe_stop(sc);
598 	BFE_UNLOCK(sc);
599 
600 	return (0);
601 }
602 
603 static int
604 bfe_resume(device_t dev)
605 {
606 	struct bfe_softc *sc;
607 	if_t ifp;
608 
609 	sc = device_get_softc(dev);
610 	ifp = sc->bfe_ifp;
611 	BFE_LOCK(sc);
612 	bfe_chip_reset(sc);
613 	if (if_getflags(ifp) & IFF_UP) {
614 		bfe_init_locked(sc);
615 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
616 		    !if_sendq_empty(ifp))
617 			bfe_start_locked(ifp);
618 	}
619 	BFE_UNLOCK(sc);
620 
621 	return (0);
622 }
623 
624 static int
625 bfe_miibus_readreg(device_t dev, int phy, int reg)
626 {
627 	struct bfe_softc *sc;
628 	u_int32_t ret;
629 
630 	sc = device_get_softc(dev);
631 	bfe_readphy(sc, reg, &ret);
632 
633 	return (ret);
634 }
635 
636 static int
637 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
638 {
639 	struct bfe_softc *sc;
640 
641 	sc = device_get_softc(dev);
642 	bfe_writephy(sc, reg, val);
643 
644 	return (0);
645 }
646 
647 static void
648 bfe_miibus_statchg(device_t dev)
649 {
650 	struct bfe_softc *sc;
651 	struct mii_data *mii;
652 	u_int32_t val;
653 #ifdef notyet
654 	u_int32_t flow;
655 #endif
656 
657 	sc = device_get_softc(dev);
658 	mii = device_get_softc(sc->bfe_miibus);
659 
660 	sc->bfe_flags &= ~BFE_FLAG_LINK;
661 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
662 	    (IFM_ACTIVE | IFM_AVALID)) {
663 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
664 		case IFM_10_T:
665 		case IFM_100_TX:
666 			sc->bfe_flags |= BFE_FLAG_LINK;
667 			break;
668 		default:
669 			break;
670 		}
671 	}
672 
673 	/* XXX Should stop Rx/Tx engine prior to touching MAC. */
674 	val = CSR_READ_4(sc, BFE_TX_CTRL);
675 	val &= ~BFE_TX_DUPLEX;
676 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
677 		val |= BFE_TX_DUPLEX;
678 #ifdef notyet
679 		flow = CSR_READ_4(sc, BFE_RXCONF);
680 		flow &= ~BFE_RXCONF_FLOW;
681 		if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
682 		    IFM_ETH_RXPAUSE) != 0)
683 			flow |= BFE_RXCONF_FLOW;
684 		CSR_WRITE_4(sc, BFE_RXCONF, flow);
685 		/*
686 		 * It seems that the hardware has Tx pause issues
687 		 * so enable only Rx pause.
688 		 */
689 		flow = CSR_READ_4(sc, BFE_MAC_FLOW);
690 		flow &= ~BFE_FLOW_PAUSE_ENAB;
691 		CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
692 #endif
693 	}
694 	CSR_WRITE_4(sc, BFE_TX_CTRL, val);
695 }
696 
697 static void
698 bfe_tx_ring_free(struct bfe_softc *sc)
699 {
700 	int i;
701 
702 	for(i = 0; i < BFE_TX_LIST_CNT; i++) {
703 		if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
704 			bus_dmamap_sync(sc->bfe_txmbuf_tag,
705 			    sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
706 			bus_dmamap_unload(sc->bfe_txmbuf_tag,
707 			    sc->bfe_tx_ring[i].bfe_map);
708 			m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
709 			sc->bfe_tx_ring[i].bfe_mbuf = NULL;
710 		}
711 	}
712 	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
713 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
714 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
715 }
716 
717 static void
718 bfe_rx_ring_free(struct bfe_softc *sc)
719 {
720 	int i;
721 
722 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
723 		if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
724 			bus_dmamap_sync(sc->bfe_rxmbuf_tag,
725 			    sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
726 			bus_dmamap_unload(sc->bfe_rxmbuf_tag,
727 			    sc->bfe_rx_ring[i].bfe_map);
728 			m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
729 			sc->bfe_rx_ring[i].bfe_mbuf = NULL;
730 		}
731 	}
732 	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
733 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
734 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
735 }
736 
737 static int
738 bfe_list_rx_init(struct bfe_softc *sc)
739 {
740 	struct bfe_rx_data *rd;
741 	int i;
742 
743 	sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
744 	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
745 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
746 		rd = &sc->bfe_rx_ring[i];
747 		rd->bfe_mbuf = NULL;
748 		rd->bfe_ctrl = 0;
749 		if (bfe_list_newbuf(sc, i) != 0)
750 			return (ENOBUFS);
751 	}
752 
753 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
754 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
755 	CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
756 
757 	return (0);
758 }
759 
760 static void
761 bfe_list_tx_init(struct bfe_softc *sc)
762 {
763 	int i;
764 
765 	sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
766 	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
767 	for (i = 0; i < BFE_TX_LIST_CNT; i++)
768 		sc->bfe_tx_ring[i].bfe_mbuf = NULL;
769 
770 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
771 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
772 }
773 
774 static void
775 bfe_discard_buf(struct bfe_softc *sc, int c)
776 {
777 	struct bfe_rx_data *r;
778 	struct bfe_desc *d;
779 
780 	r = &sc->bfe_rx_ring[c];
781 	d = &sc->bfe_rx_list[c];
782 	d->bfe_ctrl = htole32(r->bfe_ctrl);
783 }
784 
785 static int
786 bfe_list_newbuf(struct bfe_softc *sc, int c)
787 {
788 	struct bfe_rxheader *rx_header;
789 	struct bfe_desc *d;
790 	struct bfe_rx_data *r;
791 	struct mbuf *m;
792 	bus_dma_segment_t segs[1];
793 	bus_dmamap_t map;
794 	u_int32_t ctrl;
795 	int nsegs;
796 
797 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
798 	if (m == NULL)
799 		return (ENOBUFS);
800 	m->m_len = m->m_pkthdr.len = MCLBYTES;
801 
802 	if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
803 	    m, segs, &nsegs, 0) != 0) {
804 		m_freem(m);
805 		return (ENOBUFS);
806 	}
807 
808 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
809 	r = &sc->bfe_rx_ring[c];
810 	if (r->bfe_mbuf != NULL) {
811 		bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
812 		    BUS_DMASYNC_POSTREAD);
813 		bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
814 	}
815 	map = r->bfe_map;
816 	r->bfe_map = sc->bfe_rx_sparemap;
817 	sc->bfe_rx_sparemap = map;
818 	r->bfe_mbuf = m;
819 
820 	rx_header = mtod(m, struct bfe_rxheader *);
821 	rx_header->len = 0;
822 	rx_header->flags = 0;
823 	bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
824 
825 	ctrl = segs[0].ds_len & BFE_DESC_LEN;
826 	KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
827 	    __func__, ctrl));
828 	if (c == BFE_RX_LIST_CNT - 1)
829 		ctrl |= BFE_DESC_EOT;
830 	r->bfe_ctrl = ctrl;
831 
832 	d = &sc->bfe_rx_list[c];
833 	d->bfe_ctrl = htole32(ctrl);
834 	/* The chip needs all addresses to be added to BFE_PCI_DMA. */
835 	d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
836 
837 	return (0);
838 }
839 
840 static void
841 bfe_get_config(struct bfe_softc *sc)
842 {
843 	u_int8_t eeprom[128];
844 
845 	bfe_read_eeprom(sc, eeprom);
846 
847 	sc->bfe_enaddr[0] = eeprom[79];
848 	sc->bfe_enaddr[1] = eeprom[78];
849 	sc->bfe_enaddr[2] = eeprom[81];
850 	sc->bfe_enaddr[3] = eeprom[80];
851 	sc->bfe_enaddr[4] = eeprom[83];
852 	sc->bfe_enaddr[5] = eeprom[82];
853 
854 	sc->bfe_phyaddr = eeprom[90] & 0x1f;
855 	sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
856 
857 	sc->bfe_core_unit = 0;
858 	sc->bfe_dma_offset = BFE_PCI_DMA;
859 }
860 
861 static void
862 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
863 {
864 	u_int32_t bar_orig, val;
865 
866 	bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
867 	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
868 
869 	val = CSR_READ_4(sc, BFE_SBINTVEC);
870 	val |= cores;
871 	CSR_WRITE_4(sc, BFE_SBINTVEC, val);
872 
873 	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
874 	val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
875 	CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
876 
877 	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
878 }
879 
880 static void
881 bfe_clear_stats(struct bfe_softc *sc)
882 {
883 	uint32_t reg;
884 
885 	BFE_LOCK_ASSERT(sc);
886 
887 	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
888 	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
889 		CSR_READ_4(sc, reg);
890 	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
891 		CSR_READ_4(sc, reg);
892 }
893 
894 static int
895 bfe_resetphy(struct bfe_softc *sc)
896 {
897 	u_int32_t val;
898 
899 	bfe_writephy(sc, 0, BMCR_RESET);
900 	DELAY(100);
901 	bfe_readphy(sc, 0, &val);
902 	if (val & BMCR_RESET) {
903 		device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
904 		return (ENXIO);
905 	}
906 	return (0);
907 }
908 
909 static void
910 bfe_chip_halt(struct bfe_softc *sc)
911 {
912 	BFE_LOCK_ASSERT(sc);
913 	/* disable interrupts - not that it actually does..*/
914 	CSR_WRITE_4(sc, BFE_IMASK, 0);
915 	CSR_READ_4(sc, BFE_IMASK);
916 
917 	CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
918 	bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
919 
920 	CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
921 	CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
922 	DELAY(10);
923 }
924 
925 static void
926 bfe_chip_reset(struct bfe_softc *sc)
927 {
928 	u_int32_t val;
929 
930 	BFE_LOCK_ASSERT(sc);
931 
932 	/* Set the interrupt vector for the enet core */
933 	bfe_pci_setup(sc, BFE_INTVEC_ENET0);
934 
935 	/* is core up? */
936 	val = CSR_READ_4(sc, BFE_SBTMSLOW) &
937 	    (BFE_RESET | BFE_REJECT | BFE_CLOCK);
938 	if (val == BFE_CLOCK) {
939 		/* It is, so shut it down */
940 		CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
941 		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
942 		bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
943 		CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
944 		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
945 			bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
946 			    100, 0);
947 		CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
948 	}
949 
950 	bfe_core_reset(sc);
951 	bfe_clear_stats(sc);
952 
953 	/*
954 	 * We want the phy registers to be accessible even when
955 	 * the driver is "downed" so initialize MDC preamble, frequency,
956 	 * and whether internal or external phy here.
957 	 */
958 
959 	/* 4402 has 62.5Mhz SB clock and internal phy */
960 	CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
961 
962 	/* Internal or external PHY? */
963 	val = CSR_READ_4(sc, BFE_DEVCTRL);
964 	if (!(val & BFE_IPP))
965 		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
966 	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
967 		BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
968 		DELAY(100);
969 	}
970 
971 	/* Enable CRC32 generation and set proper LED modes */
972 	BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
973 
974 	/* Reset or clear powerdown control bit  */
975 	BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
976 
977 	CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
978 				BFE_LAZY_FC_MASK));
979 
980 	/*
981 	 * We don't want lazy interrupts, so just send them at
982 	 * the end of a frame, please
983 	 */
984 	BFE_OR(sc, BFE_RCV_LAZY, 0);
985 
986 	/* Set max lengths, accounting for VLAN tags */
987 	CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
988 	CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
989 
990 	/* Set watermark XXX - magic */
991 	CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
992 
993 	/*
994 	 * Initialise DMA channels
995 	 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
996 	 */
997 	CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
998 	CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
999 
1000 	CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1001 			BFE_RX_CTRL_ENABLE);
1002 	CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1003 
1004 	bfe_resetphy(sc);
1005 	bfe_setupphy(sc);
1006 }
1007 
1008 static void
1009 bfe_core_disable(struct bfe_softc *sc)
1010 {
1011 	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1012 		return;
1013 
1014 	/*
1015 	 * Set reject, wait for it set, then wait for the core to stop
1016 	 * being busy, then set reset and reject and enable the clocks.
1017 	 */
1018 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1019 	bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1020 	bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1021 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1022 				BFE_RESET));
1023 	CSR_READ_4(sc, BFE_SBTMSLOW);
1024 	DELAY(10);
1025 	/* Leave reset and reject set */
1026 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1027 	DELAY(10);
1028 }
1029 
1030 static void
1031 bfe_core_reset(struct bfe_softc *sc)
1032 {
1033 	u_int32_t val;
1034 
1035 	/* Disable the core */
1036 	bfe_core_disable(sc);
1037 
1038 	/* and bring it back up */
1039 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1040 	CSR_READ_4(sc, BFE_SBTMSLOW);
1041 	DELAY(10);
1042 
1043 	/* Chip bug, clear SERR, IB and TO if they are set. */
1044 	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1045 		CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1046 	val = CSR_READ_4(sc, BFE_SBIMSTATE);
1047 	if (val & (BFE_IBE | BFE_TO))
1048 		CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1049 
1050 	/* Clear reset and allow it to move through the core */
1051 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1052 	CSR_READ_4(sc, BFE_SBTMSLOW);
1053 	DELAY(10);
1054 
1055 	/* Leave the clock set */
1056 	CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1057 	CSR_READ_4(sc, BFE_SBTMSLOW);
1058 	DELAY(10);
1059 }
1060 
1061 static void
1062 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1063 {
1064 	u_int32_t val;
1065 
1066 	val  = ((u_int32_t) data[2]) << 24;
1067 	val |= ((u_int32_t) data[3]) << 16;
1068 	val |= ((u_int32_t) data[4]) <<  8;
1069 	val |= ((u_int32_t) data[5]);
1070 	CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1071 	val = (BFE_CAM_HI_VALID |
1072 			(((u_int32_t) data[0]) << 8) |
1073 			(((u_int32_t) data[1])));
1074 	CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1075 	CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1076 				((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1077 	bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1078 }
1079 
1080 static u_int
1081 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1082 {
1083 	struct bfe_softc *sc = arg;
1084 
1085 	bfe_cam_write(sc, LLADDR(sdl), cnt + 1);
1086 
1087 	return (1);
1088 }
1089 
1090 static void
1091 bfe_set_rx_mode(struct bfe_softc *sc)
1092 {
1093 	if_t ifp = sc->bfe_ifp;
1094 	u_int32_t val;
1095 
1096 	BFE_LOCK_ASSERT(sc);
1097 
1098 	val = CSR_READ_4(sc, BFE_RXCONF);
1099 
1100 	if (if_getflags(ifp) & IFF_PROMISC)
1101 		val |= BFE_RXCONF_PROMISC;
1102 	else
1103 		val &= ~BFE_RXCONF_PROMISC;
1104 
1105 	if (if_getflags(ifp) & IFF_BROADCAST)
1106 		val &= ~BFE_RXCONF_DBCAST;
1107 	else
1108 		val |= BFE_RXCONF_DBCAST;
1109 
1110 	CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1111 	bfe_cam_write(sc, if_getlladdr(sc->bfe_ifp), 0);
1112 
1113 	if (if_getflags(ifp) & IFF_ALLMULTI)
1114 		val |= BFE_RXCONF_ALLMULTI;
1115 	else {
1116 		val &= ~BFE_RXCONF_ALLMULTI;
1117 		if_foreach_llmaddr(ifp, bfe_write_maddr, sc);
1118 	}
1119 
1120 	CSR_WRITE_4(sc, BFE_RXCONF, val);
1121 	BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1122 }
1123 
1124 static void
1125 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1126 {
1127 	struct bfe_dmamap_arg *ctx;
1128 
1129 	if (error != 0)
1130 		return;
1131 
1132 	KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1133 
1134 	ctx = (struct bfe_dmamap_arg *)arg;
1135 	ctx->bfe_busaddr = segs[0].ds_addr;
1136 }
1137 
1138 static void
1139 bfe_release_resources(struct bfe_softc *sc)
1140 {
1141 
1142 	if (sc->bfe_intrhand != NULL)
1143 		bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1144 
1145 	if (sc->bfe_irq != NULL)
1146 		bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1147 
1148 	if (sc->bfe_res != NULL)
1149 		bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1150 		    sc->bfe_res);
1151 
1152 	if (sc->bfe_ifp != NULL)
1153 		if_free(sc->bfe_ifp);
1154 }
1155 
1156 static void
1157 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1158 {
1159 	long i;
1160 	u_int16_t *ptr = (u_int16_t *)data;
1161 
1162 	for(i = 0; i < 128; i += 2)
1163 		ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1164 }
1165 
1166 static int
1167 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1168 		u_long timeout, const int clear)
1169 {
1170 	u_long i;
1171 
1172 	for (i = 0; i < timeout; i++) {
1173 		u_int32_t val = CSR_READ_4(sc, reg);
1174 
1175 		if (clear && !(val & bit))
1176 			break;
1177 		if (!clear && (val & bit))
1178 			break;
1179 		DELAY(10);
1180 	}
1181 	if (i == timeout) {
1182 		device_printf(sc->bfe_dev,
1183 		    "BUG!  Timeout waiting for bit %08x of register "
1184 		    "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1185 		return (-1);
1186 	}
1187 	return (0);
1188 }
1189 
1190 static int
1191 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1192 {
1193 	int err;
1194 
1195 	/* Clear MII ISR */
1196 	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1197 	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1198 				(BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1199 				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1200 				(reg << BFE_MDIO_RA_SHIFT) |
1201 				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1202 	err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1203 	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1204 
1205 	return (err);
1206 }
1207 
1208 static int
1209 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1210 {
1211 	int status;
1212 
1213 	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1214 	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1215 				(BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1216 				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1217 				(reg << BFE_MDIO_RA_SHIFT) |
1218 				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1219 				(val & BFE_MDIO_DATA_DATA)));
1220 	status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1221 
1222 	return (status);
1223 }
1224 
1225 /*
1226  * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1227  * twice
1228  */
1229 static int
1230 bfe_setupphy(struct bfe_softc *sc)
1231 {
1232 	u_int32_t val;
1233 
1234 	/* Enable activity LED */
1235 	bfe_readphy(sc, 26, &val);
1236 	bfe_writephy(sc, 26, val & 0x7fff);
1237 	bfe_readphy(sc, 26, &val);
1238 
1239 	/* Enable traffic meter LED mode */
1240 	bfe_readphy(sc, 27, &val);
1241 	bfe_writephy(sc, 27, val | (1 << 6));
1242 
1243 	return (0);
1244 }
1245 
1246 static void
1247 bfe_stats_update(struct bfe_softc *sc)
1248 {
1249 	struct bfe_hw_stats *stats;
1250 	if_t ifp;
1251 	uint32_t mib[BFE_MIB_CNT];
1252 	uint32_t reg, *val;
1253 
1254 	BFE_LOCK_ASSERT(sc);
1255 
1256 	val = mib;
1257 	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1258 	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1259 		*val++ = CSR_READ_4(sc, reg);
1260 	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1261 		*val++ = CSR_READ_4(sc, reg);
1262 
1263 	ifp = sc->bfe_ifp;
1264 	stats = &sc->bfe_stats;
1265 	/* Tx stat. */
1266 	stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1267 	stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1268 	stats->tx_octets += mib[MIB_TX_O];
1269 	stats->tx_frames += mib[MIB_TX_P];
1270 	stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1271 	stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1272 	stats->tx_pkts_64 += mib[MIB_TX_64];
1273 	stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1274 	stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1275 	stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1276 	stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1277 	stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1278 	stats->tx_jabbers += mib[MIB_TX_JABBER];
1279 	stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1280 	stats->tx_frag_frames += mib[MIB_TX_FRAG];
1281 	stats->tx_underruns += mib[MIB_TX_URUNS];
1282 	stats->tx_colls += mib[MIB_TX_TCOLS];
1283 	stats->tx_single_colls += mib[MIB_TX_SCOLS];
1284 	stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1285 	stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1286 	stats->tx_late_colls += mib[MIB_TX_LCOLS];
1287 	stats->tx_deferrals += mib[MIB_TX_DEFERED];
1288 	stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1289 	stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1290 	/* Rx stat. */
1291 	stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1292 	stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1293 	stats->rx_octets += mib[MIB_RX_O];
1294 	stats->rx_frames += mib[MIB_RX_P];
1295 	stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1296 	stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1297 	stats->rx_pkts_64 += mib[MIB_RX_64];
1298 	stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1299 	stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1300 	stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1301 	stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1302 	stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1303 	stats->rx_jabbers += mib[MIB_RX_JABBER];
1304 	stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1305 	stats->rx_frag_frames += mib[MIB_RX_FRAG];
1306 	stats->rx_missed_frames += mib[MIB_RX_MISS];
1307 	stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1308 	stats->rx_runts += mib[MIB_RX_USIZE];
1309 	stats->rx_crc_errs += mib[MIB_RX_CRC];
1310 	stats->rx_align_errs += mib[MIB_RX_ALIGN];
1311 	stats->rx_symbol_errs += mib[MIB_RX_SYM];
1312 	stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1313 	stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1314 
1315 	/* Update counters in ifnet. */
1316 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1317 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1318 	if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1319 	    (u_long)mib[MIB_TX_ECOLS] +
1320 	    (u_long)mib[MIB_TX_DEFERED] +
1321 	    (u_long)mib[MIB_TX_CLOST]);
1322 
1323 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1324 
1325 	if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1326 	    mib[MIB_RX_MISS] +
1327 	    mib[MIB_RX_CRCA] +
1328 	    mib[MIB_RX_USIZE] +
1329 	    mib[MIB_RX_CRC] +
1330 	    mib[MIB_RX_ALIGN] +
1331 	    mib[MIB_RX_SYM]);
1332 }
1333 
1334 static void
1335 bfe_txeof(struct bfe_softc *sc)
1336 {
1337 	struct bfe_tx_data *r;
1338 	if_t ifp;
1339 	int i, chipidx;
1340 
1341 	BFE_LOCK_ASSERT(sc);
1342 
1343 	ifp = sc->bfe_ifp;
1344 
1345 	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1346 	chipidx /= sizeof(struct bfe_desc);
1347 
1348 	i = sc->bfe_tx_cons;
1349 	if (i == chipidx)
1350 		return;
1351 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1352 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1353 	/* Go through the mbufs and free those that have been transmitted */
1354 	for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1355 		r = &sc->bfe_tx_ring[i];
1356 		sc->bfe_tx_cnt--;
1357 		if (r->bfe_mbuf == NULL)
1358 			continue;
1359 		bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1360 		    BUS_DMASYNC_POSTWRITE);
1361 		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1362 
1363 		m_freem(r->bfe_mbuf);
1364 		r->bfe_mbuf = NULL;
1365 	}
1366 
1367 	if (i != sc->bfe_tx_cons) {
1368 		/* we freed up some mbufs */
1369 		sc->bfe_tx_cons = i;
1370 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1371 	}
1372 
1373 	if (sc->bfe_tx_cnt == 0)
1374 		sc->bfe_watchdog_timer = 0;
1375 }
1376 
1377 /* Pass a received packet up the stack */
1378 static void
1379 bfe_rxeof(struct bfe_softc *sc)
1380 {
1381 	struct mbuf *m;
1382 	if_t ifp;
1383 	struct bfe_rxheader *rxheader;
1384 	struct bfe_rx_data *r;
1385 	int cons, prog;
1386 	u_int32_t status, current, len, flags;
1387 
1388 	BFE_LOCK_ASSERT(sc);
1389 	cons = sc->bfe_rx_cons;
1390 	status = CSR_READ_4(sc, BFE_DMARX_STAT);
1391 	current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1392 
1393 	ifp = sc->bfe_ifp;
1394 
1395 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1396 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1397 
1398 	for (prog = 0; current != cons; prog++,
1399 	    BFE_INC(cons, BFE_RX_LIST_CNT)) {
1400 		r = &sc->bfe_rx_ring[cons];
1401 		m = r->bfe_mbuf;
1402 		/*
1403 		 * Rx status should be read from mbuf such that we can't
1404 		 * delay bus_dmamap_sync(9). This hardware limiation
1405 		 * results in inefficient mbuf usage as bfe(4) couldn't
1406 		 * reuse mapped buffer from errored frame.
1407 		 */
1408 		if (bfe_list_newbuf(sc, cons) != 0) {
1409 			if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1410 			bfe_discard_buf(sc, cons);
1411 			continue;
1412 		}
1413 		rxheader = mtod(m, struct bfe_rxheader*);
1414 		len = le16toh(rxheader->len);
1415 		flags = le16toh(rxheader->flags);
1416 
1417 		/* Remove CRC bytes. */
1418 		len -= ETHER_CRC_LEN;
1419 
1420 		/* flag an error and try again */
1421 		if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1422 			m_freem(m);
1423 			continue;
1424 		}
1425 
1426 		/* Make sure to skip header bytes written by hardware. */
1427 		m_adj(m, BFE_RX_OFFSET);
1428 		m->m_len = m->m_pkthdr.len = len;
1429 
1430 		m->m_pkthdr.rcvif = ifp;
1431 		BFE_UNLOCK(sc);
1432 		if_input(ifp, m);
1433 		BFE_LOCK(sc);
1434 	}
1435 
1436 	if (prog > 0) {
1437 		sc->bfe_rx_cons = cons;
1438 		bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1439 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1440 	}
1441 }
1442 
1443 static void
1444 bfe_intr(void *xsc)
1445 {
1446 	struct bfe_softc *sc = xsc;
1447 	if_t ifp;
1448 	u_int32_t istat;
1449 
1450 	ifp = sc->bfe_ifp;
1451 
1452 	BFE_LOCK(sc);
1453 
1454 	istat = CSR_READ_4(sc, BFE_ISTAT);
1455 
1456 	/*
1457 	 * Defer unsolicited interrupts - This is necessary because setting the
1458 	 * chips interrupt mask register to 0 doesn't actually stop the
1459 	 * interrupts
1460 	 */
1461 	istat &= BFE_IMASK_DEF;
1462 	CSR_WRITE_4(sc, BFE_ISTAT, istat);
1463 	CSR_READ_4(sc, BFE_ISTAT);
1464 
1465 	/* not expecting this interrupt, disregard it */
1466 	if (istat == 0 || (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1467 		BFE_UNLOCK(sc);
1468 		return;
1469 	}
1470 
1471 	/* A packet was received */
1472 	if (istat & BFE_ISTAT_RX)
1473 		bfe_rxeof(sc);
1474 
1475 	/* A packet was sent */
1476 	if (istat & BFE_ISTAT_TX)
1477 		bfe_txeof(sc);
1478 
1479 	if (istat & BFE_ISTAT_ERRORS) {
1480 		if (istat & BFE_ISTAT_DSCE) {
1481 			device_printf(sc->bfe_dev, "Descriptor Error\n");
1482 			bfe_stop(sc);
1483 			BFE_UNLOCK(sc);
1484 			return;
1485 		}
1486 
1487 		if (istat & BFE_ISTAT_DPE) {
1488 			device_printf(sc->bfe_dev,
1489 			    "Descriptor Protocol Error\n");
1490 			bfe_stop(sc);
1491 			BFE_UNLOCK(sc);
1492 			return;
1493 		}
1494 		if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1495 		bfe_init_locked(sc);
1496 	}
1497 
1498 	/* We have packets pending, fire them out */
1499 	if (!if_sendq_empty(ifp))
1500 		bfe_start_locked(ifp);
1501 
1502 	BFE_UNLOCK(sc);
1503 }
1504 
1505 static int
1506 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1507 {
1508 	struct bfe_desc *d;
1509 	struct bfe_tx_data *r, *r1;
1510 	struct mbuf *m;
1511 	bus_dmamap_t map;
1512 	bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1513 	uint32_t cur, si;
1514 	int error, i, nsegs;
1515 
1516 	BFE_LOCK_ASSERT(sc);
1517 
1518 	M_ASSERTPKTHDR((*m_head));
1519 
1520 	si = cur = sc->bfe_tx_prod;
1521 	r = &sc->bfe_tx_ring[cur];
1522 	error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1523 	    txsegs, &nsegs, 0);
1524 	if (error == EFBIG) {
1525 		m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1526 		if (m == NULL) {
1527 			m_freem(*m_head);
1528 			*m_head = NULL;
1529 			return (ENOMEM);
1530 		}
1531 		*m_head = m;
1532 		error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1533 		    *m_head, txsegs, &nsegs, 0);
1534 		if (error != 0) {
1535 			m_freem(*m_head);
1536 			*m_head = NULL;
1537 			return (error);
1538 		}
1539 	} else if (error != 0)
1540 		return (error);
1541 	if (nsegs == 0) {
1542 		m_freem(*m_head);
1543 		*m_head = NULL;
1544 		return (EIO);
1545 	}
1546 
1547 	if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1548 		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1549 		return (ENOBUFS);
1550 	}
1551 
1552 	for (i = 0; i < nsegs; i++) {
1553 		d = &sc->bfe_tx_list[cur];
1554 		d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1555 		d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1556 		if (cur == BFE_TX_LIST_CNT - 1)
1557 			/*
1558 			 * Tell the chip to wrap to the start of
1559 			 * the descriptor list.
1560 			 */
1561 			d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1562 		/* The chip needs all addresses to be added to BFE_PCI_DMA. */
1563 		d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1564 		    BFE_PCI_DMA);
1565 		BFE_INC(cur, BFE_TX_LIST_CNT);
1566 	}
1567 
1568 	/* Update producer index. */
1569 	sc->bfe_tx_prod = cur;
1570 
1571 	/* Set EOF on the last descriptor. */
1572 	cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1573 	d = &sc->bfe_tx_list[cur];
1574 	d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1575 
1576 	/* Lastly set SOF on the first descriptor to avoid races. */
1577 	d = &sc->bfe_tx_list[si];
1578 	d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1579 
1580 	r1 = &sc->bfe_tx_ring[cur];
1581 	map = r->bfe_map;
1582 	r->bfe_map = r1->bfe_map;
1583 	r1->bfe_map = map;
1584 	r1->bfe_mbuf = *m_head;
1585 	sc->bfe_tx_cnt += nsegs;
1586 
1587 	bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1588 
1589 	return (0);
1590 }
1591 
1592 /*
1593  * Set up to transmit a packet.
1594  */
1595 static void
1596 bfe_start(if_t ifp)
1597 {
1598 	BFE_LOCK((struct bfe_softc *)if_getsoftc(ifp));
1599 	bfe_start_locked(ifp);
1600 	BFE_UNLOCK((struct bfe_softc *)if_getsoftc(ifp));
1601 }
1602 
1603 /*
1604  * Set up to transmit a packet. The softc is already locked.
1605  */
1606 static void
1607 bfe_start_locked(if_t ifp)
1608 {
1609 	struct bfe_softc *sc;
1610 	struct mbuf *m_head;
1611 	int queued;
1612 
1613 	sc = if_getsoftc(ifp);
1614 
1615 	BFE_LOCK_ASSERT(sc);
1616 
1617 	/*
1618 	 * Not much point trying to send if the link is down
1619 	 * or we have nothing to send.
1620 	 */
1621 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1622 	    IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1623 		return;
1624 
1625 	for (queued = 0; !if_sendq_empty(ifp) &&
1626 	    sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1627 		m_head = if_dequeue(ifp);
1628 		if (m_head == NULL)
1629 			break;
1630 
1631 		/*
1632 		 * Pack the data into the tx ring.  If we dont have
1633 		 * enough room, let the chip drain the ring.
1634 		 */
1635 		if (bfe_encap(sc, &m_head)) {
1636 			if (m_head == NULL)
1637 				break;
1638 			if_sendq_prepend(ifp, m_head);
1639 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1640 			break;
1641 		}
1642 
1643 		queued++;
1644 
1645 		/*
1646 		 * If there's a BPF listener, bounce a copy of this frame
1647 		 * to him.
1648 		 */
1649 		BPF_MTAP(ifp, m_head);
1650 	}
1651 
1652 	if (queued) {
1653 		bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1654 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1655 		/* Transmit - twice due to apparent hardware bug */
1656 		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1657 		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1658 		/*
1659 		 * XXX It seems the following write is not necessary
1660 		 * to kick Tx command. What might be required would be
1661 		 * a way flushing PCI posted write. Reading the register
1662 		 * back ensures the flush operation. In addition,
1663 		 * hardware will execute PCI posted write in the long
1664 		 * run and watchdog timer for the kick command was set
1665 		 * to 5 seconds. Therefore I think the second write
1666 		 * access is not necessary or could be replaced with
1667 		 * read operation.
1668 		 */
1669 		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1670 		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1671 
1672 		/*
1673 		 * Set a timeout in case the chip goes out to lunch.
1674 		 */
1675 		sc->bfe_watchdog_timer = 5;
1676 	}
1677 }
1678 
1679 static void
1680 bfe_init(void *xsc)
1681 {
1682 	BFE_LOCK((struct bfe_softc *)xsc);
1683 	bfe_init_locked(xsc);
1684 	BFE_UNLOCK((struct bfe_softc *)xsc);
1685 }
1686 
1687 static void
1688 bfe_init_locked(void *xsc)
1689 {
1690 	struct bfe_softc *sc = (struct bfe_softc*)xsc;
1691 	if_t ifp = sc->bfe_ifp;
1692 	struct mii_data *mii;
1693 
1694 	BFE_LOCK_ASSERT(sc);
1695 
1696 	mii = device_get_softc(sc->bfe_miibus);
1697 
1698 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1699 		return;
1700 
1701 	bfe_stop(sc);
1702 	bfe_chip_reset(sc);
1703 
1704 	if (bfe_list_rx_init(sc) == ENOBUFS) {
1705 		device_printf(sc->bfe_dev,
1706 		    "%s: Not enough memory for list buffers\n", __func__);
1707 		bfe_stop(sc);
1708 		return;
1709 	}
1710 	bfe_list_tx_init(sc);
1711 
1712 	bfe_set_rx_mode(sc);
1713 
1714 	/* Enable the chip and core */
1715 	BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1716 	/* Enable interrupts */
1717 	CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1718 
1719 	/* Clear link state and change media. */
1720 	sc->bfe_flags &= ~BFE_FLAG_LINK;
1721 	mii_mediachg(mii);
1722 
1723 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1724 	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1725 
1726 	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1727 }
1728 
1729 /*
1730  * Set media options.
1731  */
1732 static int
1733 bfe_ifmedia_upd(if_t ifp)
1734 {
1735 	struct bfe_softc *sc;
1736 	struct mii_data *mii;
1737 	struct mii_softc *miisc;
1738 	int error;
1739 
1740 	sc = if_getsoftc(ifp);
1741 	BFE_LOCK(sc);
1742 
1743 	mii = device_get_softc(sc->bfe_miibus);
1744 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1745 		PHY_RESET(miisc);
1746 	error = mii_mediachg(mii);
1747 	BFE_UNLOCK(sc);
1748 
1749 	return (error);
1750 }
1751 
1752 /*
1753  * Report current media status.
1754  */
1755 static void
1756 bfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1757 {
1758 	struct bfe_softc *sc = if_getsoftc(ifp);
1759 	struct mii_data *mii;
1760 
1761 	BFE_LOCK(sc);
1762 	mii = device_get_softc(sc->bfe_miibus);
1763 	mii_pollstat(mii);
1764 	ifmr->ifm_active = mii->mii_media_active;
1765 	ifmr->ifm_status = mii->mii_media_status;
1766 	BFE_UNLOCK(sc);
1767 }
1768 
1769 static int
1770 bfe_ioctl(if_t ifp, u_long command, caddr_t data)
1771 {
1772 	struct bfe_softc *sc = if_getsoftc(ifp);
1773 	struct ifreq *ifr = (struct ifreq *) data;
1774 	struct mii_data *mii;
1775 	int error = 0;
1776 
1777 	switch (command) {
1778 	case SIOCSIFFLAGS:
1779 		BFE_LOCK(sc);
1780 		if (if_getflags(ifp) & IFF_UP) {
1781 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1782 				bfe_set_rx_mode(sc);
1783 			else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1784 				bfe_init_locked(sc);
1785 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1786 			bfe_stop(sc);
1787 		BFE_UNLOCK(sc);
1788 		break;
1789 	case SIOCADDMULTI:
1790 	case SIOCDELMULTI:
1791 		BFE_LOCK(sc);
1792 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1793 			bfe_set_rx_mode(sc);
1794 		BFE_UNLOCK(sc);
1795 		break;
1796 	case SIOCGIFMEDIA:
1797 	case SIOCSIFMEDIA:
1798 		mii = device_get_softc(sc->bfe_miibus);
1799 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1800 		break;
1801 	default:
1802 		error = ether_ioctl(ifp, command, data);
1803 		break;
1804 	}
1805 
1806 	return (error);
1807 }
1808 
1809 static void
1810 bfe_watchdog(struct bfe_softc *sc)
1811 {
1812 	if_t ifp;
1813 
1814 	BFE_LOCK_ASSERT(sc);
1815 
1816 	if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1817 		return;
1818 
1819 	ifp = sc->bfe_ifp;
1820 
1821 	device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1822 
1823 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1824 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1825 	bfe_init_locked(sc);
1826 
1827 	if (!if_sendq_empty(ifp))
1828 		bfe_start_locked(ifp);
1829 }
1830 
1831 static void
1832 bfe_tick(void *xsc)
1833 {
1834 	struct bfe_softc *sc = xsc;
1835 	struct mii_data *mii;
1836 
1837 	BFE_LOCK_ASSERT(sc);
1838 
1839 	mii = device_get_softc(sc->bfe_miibus);
1840 	mii_tick(mii);
1841 	bfe_stats_update(sc);
1842 	bfe_watchdog(sc);
1843 	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1844 }
1845 
1846 /*
1847  * Stop the adapter and free any mbufs allocated to the
1848  * RX and TX lists.
1849  */
1850 static void
1851 bfe_stop(struct bfe_softc *sc)
1852 {
1853 	if_t ifp;
1854 
1855 	BFE_LOCK_ASSERT(sc);
1856 
1857 	ifp = sc->bfe_ifp;
1858 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1859 	sc->bfe_flags &= ~BFE_FLAG_LINK;
1860 	callout_stop(&sc->bfe_stat_co);
1861 	sc->bfe_watchdog_timer = 0;
1862 
1863 	bfe_chip_halt(sc);
1864 	bfe_tx_ring_free(sc);
1865 	bfe_rx_ring_free(sc);
1866 }
1867 
1868 static int
1869 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1870 {
1871 	struct bfe_softc *sc;
1872 	struct bfe_hw_stats *stats;
1873 	int error, result;
1874 
1875 	result = -1;
1876 	error = sysctl_handle_int(oidp, &result, 0, req);
1877 
1878 	if (error != 0 || req->newptr == NULL)
1879 		return (error);
1880 
1881 	if (result != 1)
1882 		return (error);
1883 
1884 	sc = (struct bfe_softc *)arg1;
1885 	stats = &sc->bfe_stats;
1886 
1887 	printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1888 	printf("Transmit good octets : %ju\n",
1889 	    (uintmax_t)stats->tx_good_octets);
1890 	printf("Transmit good frames : %ju\n",
1891 	    (uintmax_t)stats->tx_good_frames);
1892 	printf("Transmit octets : %ju\n",
1893 	    (uintmax_t)stats->tx_octets);
1894 	printf("Transmit frames : %ju\n",
1895 	    (uintmax_t)stats->tx_frames);
1896 	printf("Transmit broadcast frames : %ju\n",
1897 	    (uintmax_t)stats->tx_bcast_frames);
1898 	printf("Transmit multicast frames : %ju\n",
1899 	    (uintmax_t)stats->tx_mcast_frames);
1900 	printf("Transmit frames 64 bytes : %ju\n",
1901 	    (uint64_t)stats->tx_pkts_64);
1902 	printf("Transmit frames 65 to 127 bytes : %ju\n",
1903 	    (uint64_t)stats->tx_pkts_65_127);
1904 	printf("Transmit frames 128 to 255 bytes : %ju\n",
1905 	    (uint64_t)stats->tx_pkts_128_255);
1906 	printf("Transmit frames 256 to 511 bytes : %ju\n",
1907 	    (uint64_t)stats->tx_pkts_256_511);
1908 	printf("Transmit frames 512 to 1023 bytes : %ju\n",
1909 	    (uint64_t)stats->tx_pkts_512_1023);
1910 	printf("Transmit frames 1024 to max bytes : %ju\n",
1911 	    (uint64_t)stats->tx_pkts_1024_max);
1912 	printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1913 	printf("Transmit oversized frames : %ju\n",
1914 	    (uint64_t)stats->tx_oversize_frames);
1915 	printf("Transmit fragmented frames : %ju\n",
1916 	    (uint64_t)stats->tx_frag_frames);
1917 	printf("Transmit underruns : %u\n", stats->tx_colls);
1918 	printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1919 	printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1920 	printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1921 	printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1922 	printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1923 	printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1924 	printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1925 	printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1926 
1927 	printf("Receive good octets : %ju\n",
1928 	    (uintmax_t)stats->rx_good_octets);
1929 	printf("Receive good frames : %ju\n",
1930 	    (uintmax_t)stats->rx_good_frames);
1931 	printf("Receive octets : %ju\n",
1932 	    (uintmax_t)stats->rx_octets);
1933 	printf("Receive frames : %ju\n",
1934 	    (uintmax_t)stats->rx_frames);
1935 	printf("Receive broadcast frames : %ju\n",
1936 	    (uintmax_t)stats->rx_bcast_frames);
1937 	printf("Receive multicast frames : %ju\n",
1938 	    (uintmax_t)stats->rx_mcast_frames);
1939 	printf("Receive frames 64 bytes : %ju\n",
1940 	    (uint64_t)stats->rx_pkts_64);
1941 	printf("Receive frames 65 to 127 bytes : %ju\n",
1942 	    (uint64_t)stats->rx_pkts_65_127);
1943 	printf("Receive frames 128 to 255 bytes : %ju\n",
1944 	    (uint64_t)stats->rx_pkts_128_255);
1945 	printf("Receive frames 256 to 511 bytes : %ju\n",
1946 	    (uint64_t)stats->rx_pkts_256_511);
1947 	printf("Receive frames 512 to 1023 bytes : %ju\n",
1948 	    (uint64_t)stats->rx_pkts_512_1023);
1949 	printf("Receive frames 1024 to max bytes : %ju\n",
1950 	    (uint64_t)stats->rx_pkts_1024_max);
1951 	printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1952 	printf("Receive oversized frames : %ju\n",
1953 	    (uint64_t)stats->rx_oversize_frames);
1954 	printf("Receive fragmented frames : %ju\n",
1955 	    (uint64_t)stats->rx_frag_frames);
1956 	printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1957 	printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1958 	printf("Receive undersized frames : %u\n", stats->rx_runts);
1959 	printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1960 	printf("Receive align errors : %u\n", stats->rx_align_errs);
1961 	printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1962 	printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1963 	printf("Receive control frames : %u\n", stats->rx_control_frames);
1964 
1965 	return (error);
1966 }
1967