1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* 201 * parent tag. Apparently the chip cannot handle any DMA address 202 * greater than 1GB. 203 */ 204 error = bus_dma_tag_create(NULL, /* parent */ 205 PAGE_SIZE, 0, /* alignment, boundary */ 206 0x3FFFFFFF, /* lowaddr */ 207 BUS_SPACE_MAXADDR, /* highaddr */ 208 NULL, NULL, /* filter, filterarg */ 209 MAXBSIZE, /* maxsize */ 210 BUS_SPACE_UNRESTRICTED, /* num of segments */ 211 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 212 0, /* flags */ 213 NULL, NULL, /* lockfunc, lockarg */ 214 &sc->bfe_parent_tag); 215 216 /* tag for TX ring */ 217 error = bus_dma_tag_create(sc->bfe_parent_tag, 218 1, 0, 219 BUS_SPACE_MAXADDR, 220 BUS_SPACE_MAXADDR, 221 NULL, NULL, 222 BFE_TX_LIST_SIZE, 223 1, 224 BUS_SPACE_MAXSIZE_32BIT, 225 0, 226 NULL, NULL, 227 &sc->bfe_tx_tag); 228 229 if (error) { 230 device_printf(dev, "could not allocate dma tag\n"); 231 return (ENOMEM); 232 } 233 234 /* tag for RX ring */ 235 error = bus_dma_tag_create(sc->bfe_parent_tag, 236 1, 0, 237 BUS_SPACE_MAXADDR, 238 BUS_SPACE_MAXADDR, 239 NULL, NULL, 240 BFE_RX_LIST_SIZE, 241 1, 242 BUS_SPACE_MAXSIZE_32BIT, 243 0, 244 NULL, NULL, 245 &sc->bfe_rx_tag); 246 247 if (error) { 248 device_printf(dev, "could not allocate dma tag\n"); 249 return (ENOMEM); 250 } 251 252 /* tag for mbufs */ 253 error = bus_dma_tag_create(sc->bfe_parent_tag, 254 ETHER_ALIGN, 0, 255 BUS_SPACE_MAXADDR, 256 BUS_SPACE_MAXADDR, 257 NULL, NULL, 258 MCLBYTES, 259 1, 260 BUS_SPACE_MAXSIZE_32BIT, 261 BUS_DMA_ALLOCNOW, 262 NULL, NULL, 263 &sc->bfe_tag); 264 265 if (error) { 266 device_printf(dev, "could not allocate dma tag\n"); 267 return (ENOMEM); 268 } 269 270 /* pre allocate dmamaps for RX list */ 271 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 272 error = bus_dmamap_create(sc->bfe_tag, 0, 273 &sc->bfe_rx_ring[i].bfe_map); 274 if (error) { 275 device_printf(dev, "cannot create DMA map for RX\n"); 276 return (ENOMEM); 277 } 278 } 279 280 /* pre allocate dmamaps for TX list */ 281 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 282 error = bus_dmamap_create(sc->bfe_tag, 0, 283 &sc->bfe_tx_ring[i].bfe_map); 284 if (error) { 285 device_printf(dev, "cannot create DMA map for TX\n"); 286 return (ENOMEM); 287 } 288 } 289 290 /* Alloc dma for rx ring */ 291 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 292 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 293 294 if(error) 295 return (ENOMEM); 296 297 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 298 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 299 sc->bfe_rx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 301 302 if(error) 303 return (ENOMEM); 304 305 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 306 307 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 308 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 309 if (error) 310 return (ENOMEM); 311 312 313 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 314 sc->bfe_tx_list, sizeof(struct bfe_desc), 315 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 316 if(error) 317 return (ENOMEM); 318 319 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 320 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 321 322 return (0); 323 } 324 325 static int 326 bfe_attach(device_t dev) 327 { 328 struct ifnet *ifp = NULL; 329 struct bfe_softc *sc; 330 int unit, error = 0, rid; 331 332 sc = device_get_softc(dev); 333 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 334 MTX_DEF); 335 336 unit = device_get_unit(dev); 337 sc->bfe_dev = dev; 338 sc->bfe_unit = unit; 339 340 /* 341 * Map control/status registers. 342 */ 343 pci_enable_busmaster(dev); 344 345 rid = BFE_PCI_MEMLO; 346 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 347 RF_ACTIVE); 348 if (sc->bfe_res == NULL) { 349 printf ("bfe%d: couldn't map memory\n", unit); 350 error = ENXIO; 351 goto fail; 352 } 353 354 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 355 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 356 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 357 358 /* Allocate interrupt */ 359 rid = 0; 360 361 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 362 RF_SHAREABLE | RF_ACTIVE); 363 if (sc->bfe_irq == NULL) { 364 printf("bfe%d: couldn't map interrupt\n", unit); 365 error = ENXIO; 366 goto fail; 367 } 368 369 if (bfe_dma_alloc(dev)) { 370 printf("bfe%d: failed to allocate DMA resources\n", 371 sc->bfe_unit); 372 error = ENXIO; 373 goto fail; 374 } 375 376 /* Set up ifnet structure */ 377 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 378 if (ifp == NULL) { 379 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 380 error = ENOSPC; 381 goto fail; 382 } 383 ifp->if_softc = sc; 384 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = bfe_ioctl; 387 ifp->if_start = bfe_start; 388 ifp->if_watchdog = bfe_watchdog; 389 ifp->if_init = bfe_init; 390 ifp->if_mtu = ETHERMTU; 391 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 392 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 393 IFQ_SET_READY(&ifp->if_snd); 394 395 bfe_get_config(sc); 396 397 /* Reset the chip and turn on the PHY */ 398 BFE_LOCK(sc); 399 bfe_chip_reset(sc); 400 BFE_UNLOCK(sc); 401 402 if (mii_phy_probe(dev, &sc->bfe_miibus, 403 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 404 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 405 error = ENXIO; 406 goto fail; 407 } 408 409 ether_ifattach(ifp, sc->bfe_enaddr); 410 callout_handle_init(&sc->bfe_stat_ch); 411 412 /* 413 * Tell the upper layer(s) we support long frames. 414 */ 415 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 416 ifp->if_capabilities |= IFCAP_VLAN_MTU; 417 ifp->if_capenable |= IFCAP_VLAN_MTU; 418 419 /* 420 * Hook interrupt last to avoid having to lock softc 421 */ 422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 423 bfe_intr, sc, &sc->bfe_intrhand); 424 425 if (error) { 426 printf("bfe%d: couldn't set up irq\n", unit); 427 goto fail; 428 } 429 fail: 430 if (error) 431 bfe_release_resources(sc); 432 return (error); 433 } 434 435 static int 436 bfe_detach(device_t dev) 437 { 438 struct bfe_softc *sc; 439 struct ifnet *ifp; 440 441 sc = device_get_softc(dev); 442 443 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 444 BFE_LOCK(sc); 445 446 ifp = sc->bfe_ifp; 447 448 if (device_is_attached(dev)) { 449 bfe_stop(sc); 450 ether_ifdetach(ifp); 451 } 452 453 bfe_chip_reset(sc); 454 455 bus_generic_detach(dev); 456 if(sc->bfe_miibus != NULL) 457 device_delete_child(dev, sc->bfe_miibus); 458 459 bfe_release_resources(sc); 460 BFE_UNLOCK(sc); 461 mtx_destroy(&sc->bfe_mtx); 462 463 return (0); 464 } 465 466 /* 467 * Stop all chip I/O so that the kernel's probe routines don't 468 * get confused by errant DMAs when rebooting. 469 */ 470 static void 471 bfe_shutdown(device_t dev) 472 { 473 struct bfe_softc *sc; 474 475 sc = device_get_softc(dev); 476 BFE_LOCK(sc); 477 bfe_stop(sc); 478 479 BFE_UNLOCK(sc); 480 return; 481 } 482 483 static int 484 bfe_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bfe_softc *sc; 487 u_int32_t ret; 488 489 sc = device_get_softc(dev); 490 if(phy != sc->bfe_phyaddr) 491 return (0); 492 bfe_readphy(sc, reg, &ret); 493 494 return (ret); 495 } 496 497 static int 498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 499 { 500 struct bfe_softc *sc; 501 502 sc = device_get_softc(dev); 503 if(phy != sc->bfe_phyaddr) 504 return (0); 505 bfe_writephy(sc, reg, val); 506 507 return (0); 508 } 509 510 static void 511 bfe_miibus_statchg(device_t dev) 512 { 513 return; 514 } 515 516 static void 517 bfe_tx_ring_free(struct bfe_softc *sc) 518 { 519 int i; 520 521 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 522 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 524 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 525 bus_dmamap_unload(sc->bfe_tag, 526 sc->bfe_tx_ring[i].bfe_map); 527 } 528 } 529 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 530 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 531 } 532 533 static void 534 bfe_rx_ring_free(struct bfe_softc *sc) 535 { 536 int i; 537 538 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 539 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 541 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 542 bus_dmamap_unload(sc->bfe_tag, 543 sc->bfe_rx_ring[i].bfe_map); 544 } 545 } 546 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 548 } 549 550 static int 551 bfe_list_rx_init(struct bfe_softc *sc) 552 { 553 int i; 554 555 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 556 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 557 return (ENOBUFS); 558 } 559 560 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 561 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 562 563 sc->bfe_rx_cons = 0; 564 565 return (0); 566 } 567 568 static int 569 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 570 { 571 struct bfe_rxheader *rx_header; 572 struct bfe_desc *d; 573 struct bfe_data *r; 574 u_int32_t ctrl; 575 int error; 576 577 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 578 return (EINVAL); 579 580 if(m == NULL) { 581 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 582 if(m == NULL) 583 return (ENOBUFS); 584 m->m_len = m->m_pkthdr.len = MCLBYTES; 585 } 586 else 587 m->m_data = m->m_ext.ext_buf; 588 589 rx_header = mtod(m, struct bfe_rxheader *); 590 rx_header->len = 0; 591 rx_header->flags = 0; 592 593 /* Map the mbuf into DMA */ 594 sc->bfe_rx_cnt = c; 595 d = &sc->bfe_rx_list[c]; 596 r = &sc->bfe_rx_ring[c]; 597 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 598 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 599 if (error) 600 printf("Serious error: bfe failed to map RX buffer\n"); 601 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 602 603 ctrl = ETHER_MAX_LEN + 32; 604 605 if(c == BFE_RX_LIST_CNT - 1) 606 ctrl |= BFE_DESC_EOT; 607 608 d->bfe_ctrl = ctrl; 609 r->bfe_mbuf = m; 610 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 611 return (0); 612 } 613 614 static void 615 bfe_get_config(struct bfe_softc *sc) 616 { 617 u_int8_t eeprom[128]; 618 619 bfe_read_eeprom(sc, eeprom); 620 621 sc->bfe_enaddr[0] = eeprom[79]; 622 sc->bfe_enaddr[1] = eeprom[78]; 623 sc->bfe_enaddr[2] = eeprom[81]; 624 sc->bfe_enaddr[3] = eeprom[80]; 625 sc->bfe_enaddr[4] = eeprom[83]; 626 sc->bfe_enaddr[5] = eeprom[82]; 627 628 sc->bfe_phyaddr = eeprom[90] & 0x1f; 629 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 630 631 sc->bfe_core_unit = 0; 632 sc->bfe_dma_offset = BFE_PCI_DMA; 633 } 634 635 static void 636 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 637 { 638 u_int32_t bar_orig, pci_rev, val; 639 640 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 641 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 642 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 643 644 val = CSR_READ_4(sc, BFE_SBINTVEC); 645 val |= cores; 646 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 647 648 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 649 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 650 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 651 652 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 653 } 654 655 static void 656 bfe_clear_stats(struct bfe_softc *sc) 657 { 658 u_long reg; 659 660 BFE_LOCK_ASSERT(sc); 661 662 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 663 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 664 CSR_READ_4(sc, reg); 665 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 666 CSR_READ_4(sc, reg); 667 } 668 669 static int 670 bfe_resetphy(struct bfe_softc *sc) 671 { 672 u_int32_t val; 673 674 bfe_writephy(sc, 0, BMCR_RESET); 675 DELAY(100); 676 bfe_readphy(sc, 0, &val); 677 if (val & BMCR_RESET) { 678 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 679 return (ENXIO); 680 } 681 return (0); 682 } 683 684 static void 685 bfe_chip_halt(struct bfe_softc *sc) 686 { 687 BFE_LOCK_ASSERT(sc); 688 /* disable interrupts - not that it actually does..*/ 689 CSR_WRITE_4(sc, BFE_IMASK, 0); 690 CSR_READ_4(sc, BFE_IMASK); 691 692 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 693 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 694 695 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 696 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 697 DELAY(10); 698 } 699 700 static void 701 bfe_chip_reset(struct bfe_softc *sc) 702 { 703 u_int32_t val; 704 705 BFE_LOCK_ASSERT(sc); 706 707 /* Set the interrupt vector for the enet core */ 708 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 709 710 /* is core up? */ 711 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 712 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 713 if (val == BFE_CLOCK) { 714 /* It is, so shut it down */ 715 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 716 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 717 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 718 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 719 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 720 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 721 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 722 100, 0); 723 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 724 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 725 } 726 727 bfe_core_reset(sc); 728 bfe_clear_stats(sc); 729 730 /* 731 * We want the phy registers to be accessible even when 732 * the driver is "downed" so initialize MDC preamble, frequency, 733 * and whether internal or external phy here. 734 */ 735 736 /* 4402 has 62.5Mhz SB clock and internal phy */ 737 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 738 739 /* Internal or external PHY? */ 740 val = CSR_READ_4(sc, BFE_DEVCTRL); 741 if(!(val & BFE_IPP)) 742 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 743 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 744 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 745 DELAY(100); 746 } 747 748 /* Enable CRC32 generation and set proper LED modes */ 749 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 750 751 /* Reset or clear powerdown control bit */ 752 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 753 754 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 755 BFE_LAZY_FC_MASK)); 756 757 /* 758 * We don't want lazy interrupts, so just send them at 759 * the end of a frame, please 760 */ 761 BFE_OR(sc, BFE_RCV_LAZY, 0); 762 763 /* Set max lengths, accounting for VLAN tags */ 764 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 765 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 766 767 /* Set watermark XXX - magic */ 768 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 769 770 /* 771 * Initialise DMA channels 772 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 773 */ 774 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 775 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 776 777 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 778 BFE_RX_CTRL_ENABLE); 779 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 780 781 bfe_resetphy(sc); 782 bfe_setupphy(sc); 783 } 784 785 static void 786 bfe_core_disable(struct bfe_softc *sc) 787 { 788 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 789 return; 790 791 /* 792 * Set reject, wait for it set, then wait for the core to stop 793 * being busy, then set reset and reject and enable the clocks. 794 */ 795 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 796 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 797 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 798 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 799 BFE_RESET)); 800 CSR_READ_4(sc, BFE_SBTMSLOW); 801 DELAY(10); 802 /* Leave reset and reject set */ 803 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 804 DELAY(10); 805 } 806 807 static void 808 bfe_core_reset(struct bfe_softc *sc) 809 { 810 u_int32_t val; 811 812 /* Disable the core */ 813 bfe_core_disable(sc); 814 815 /* and bring it back up */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 817 CSR_READ_4(sc, BFE_SBTMSLOW); 818 DELAY(10); 819 820 /* Chip bug, clear SERR, IB and TO if they are set. */ 821 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 822 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 823 val = CSR_READ_4(sc, BFE_SBIMSTATE); 824 if (val & (BFE_IBE | BFE_TO)) 825 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 826 827 /* Clear reset and allow it to move through the core */ 828 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 829 CSR_READ_4(sc, BFE_SBTMSLOW); 830 DELAY(10); 831 832 /* Leave the clock set */ 833 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 834 CSR_READ_4(sc, BFE_SBTMSLOW); 835 DELAY(10); 836 } 837 838 static void 839 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 840 { 841 u_int32_t val; 842 843 val = ((u_int32_t) data[2]) << 24; 844 val |= ((u_int32_t) data[3]) << 16; 845 val |= ((u_int32_t) data[4]) << 8; 846 val |= ((u_int32_t) data[5]); 847 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 848 val = (BFE_CAM_HI_VALID | 849 (((u_int32_t) data[0]) << 8) | 850 (((u_int32_t) data[1]))); 851 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 852 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 853 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 854 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 855 } 856 857 static void 858 bfe_set_rx_mode(struct bfe_softc *sc) 859 { 860 struct ifnet *ifp = sc->bfe_ifp; 861 struct ifmultiaddr *ifma; 862 u_int32_t val; 863 int i = 0; 864 865 val = CSR_READ_4(sc, BFE_RXCONF); 866 867 if (ifp->if_flags & IFF_PROMISC) 868 val |= BFE_RXCONF_PROMISC; 869 else 870 val &= ~BFE_RXCONF_PROMISC; 871 872 if (ifp->if_flags & IFF_BROADCAST) 873 val &= ~BFE_RXCONF_DBCAST; 874 else 875 val |= BFE_RXCONF_DBCAST; 876 877 878 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 879 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 880 881 if (ifp->if_flags & IFF_ALLMULTI) 882 val |= BFE_RXCONF_ALLMULTI; 883 else { 884 val &= ~BFE_RXCONF_ALLMULTI; 885 IF_ADDR_LOCK(ifp); 886 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 887 if (ifma->ifma_addr->sa_family != AF_LINK) 888 continue; 889 bfe_cam_write(sc, 890 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 891 } 892 IF_ADDR_UNLOCK(ifp); 893 } 894 895 CSR_WRITE_4(sc, BFE_RXCONF, val); 896 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 897 } 898 899 static void 900 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 901 { 902 u_int32_t *ptr; 903 904 ptr = arg; 905 *ptr = segs->ds_addr; 906 } 907 908 static void 909 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 910 { 911 struct bfe_desc *d; 912 913 d = arg; 914 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 915 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 916 } 917 918 static void 919 bfe_release_resources(struct bfe_softc *sc) 920 { 921 device_t dev; 922 int i; 923 924 dev = sc->bfe_dev; 925 926 if (sc->bfe_vpd_prodname != NULL) 927 free(sc->bfe_vpd_prodname, M_DEVBUF); 928 929 if (sc->bfe_vpd_readonly != NULL) 930 free(sc->bfe_vpd_readonly, M_DEVBUF); 931 932 if (sc->bfe_intrhand != NULL) 933 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 934 935 if (sc->bfe_irq != NULL) 936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 937 938 if (sc->bfe_res != NULL) 939 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 940 941 if (sc->bfe_ifp != NULL) 942 if_free(sc->bfe_ifp); 943 944 if(sc->bfe_tx_tag != NULL) { 945 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 946 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 947 sc->bfe_tx_map); 948 bus_dma_tag_destroy(sc->bfe_tx_tag); 949 sc->bfe_tx_tag = NULL; 950 } 951 952 if(sc->bfe_rx_tag != NULL) { 953 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 954 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 955 sc->bfe_rx_map); 956 bus_dma_tag_destroy(sc->bfe_rx_tag); 957 sc->bfe_rx_tag = NULL; 958 } 959 960 if(sc->bfe_tag != NULL) { 961 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 962 bus_dmamap_destroy(sc->bfe_tag, 963 sc->bfe_tx_ring[i].bfe_map); 964 } 965 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 966 bus_dmamap_destroy(sc->bfe_tag, 967 sc->bfe_rx_ring[i].bfe_map); 968 } 969 bus_dma_tag_destroy(sc->bfe_tag); 970 sc->bfe_tag = NULL; 971 } 972 973 if(sc->bfe_parent_tag != NULL) 974 bus_dma_tag_destroy(sc->bfe_parent_tag); 975 976 return; 977 } 978 979 static void 980 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 981 { 982 long i; 983 u_int16_t *ptr = (u_int16_t *)data; 984 985 for(i = 0; i < 128; i += 2) 986 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 987 } 988 989 static int 990 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 991 u_long timeout, const int clear) 992 { 993 u_long i; 994 995 for (i = 0; i < timeout; i++) { 996 u_int32_t val = CSR_READ_4(sc, reg); 997 998 if (clear && !(val & bit)) 999 break; 1000 if (!clear && (val & bit)) 1001 break; 1002 DELAY(10); 1003 } 1004 if (i == timeout) { 1005 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1006 "%x to %s.\n", sc->bfe_unit, bit, reg, 1007 (clear ? "clear" : "set")); 1008 return (-1); 1009 } 1010 return (0); 1011 } 1012 1013 static int 1014 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1015 { 1016 int err; 1017 1018 /* Clear MII ISR */ 1019 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1020 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1021 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1022 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1023 (reg << BFE_MDIO_RA_SHIFT) | 1024 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1025 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1026 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1027 1028 return (err); 1029 } 1030 1031 static int 1032 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1033 { 1034 int status; 1035 1036 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1037 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1038 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1039 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1040 (reg << BFE_MDIO_RA_SHIFT) | 1041 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1042 (val & BFE_MDIO_DATA_DATA))); 1043 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1044 1045 return (status); 1046 } 1047 1048 /* 1049 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1050 * twice 1051 */ 1052 static int 1053 bfe_setupphy(struct bfe_softc *sc) 1054 { 1055 u_int32_t val; 1056 1057 /* Enable activity LED */ 1058 bfe_readphy(sc, 26, &val); 1059 bfe_writephy(sc, 26, val & 0x7fff); 1060 bfe_readphy(sc, 26, &val); 1061 1062 /* Enable traffic meter LED mode */ 1063 bfe_readphy(sc, 27, &val); 1064 bfe_writephy(sc, 27, val | (1 << 6)); 1065 1066 return (0); 1067 } 1068 1069 static void 1070 bfe_stats_update(struct bfe_softc *sc) 1071 { 1072 u_long reg; 1073 u_int32_t *val; 1074 1075 val = &sc->bfe_hwstats.tx_good_octets; 1076 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1077 *val++ += CSR_READ_4(sc, reg); 1078 } 1079 val = &sc->bfe_hwstats.rx_good_octets; 1080 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1081 *val++ += CSR_READ_4(sc, reg); 1082 } 1083 } 1084 1085 static void 1086 bfe_txeof(struct bfe_softc *sc) 1087 { 1088 struct ifnet *ifp; 1089 int i, chipidx; 1090 1091 BFE_LOCK_ASSERT(sc); 1092 1093 ifp = sc->bfe_ifp; 1094 1095 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1096 chipidx /= sizeof(struct bfe_desc); 1097 1098 i = sc->bfe_tx_cons; 1099 /* Go through the mbufs and free those that have been transmitted */ 1100 while(i != chipidx) { 1101 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1102 if(r->bfe_mbuf != NULL) { 1103 ifp->if_opackets++; 1104 m_freem(r->bfe_mbuf); 1105 r->bfe_mbuf = NULL; 1106 } 1107 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1108 sc->bfe_tx_cnt--; 1109 BFE_INC(i, BFE_TX_LIST_CNT); 1110 } 1111 1112 if(i != sc->bfe_tx_cons) { 1113 /* we freed up some mbufs */ 1114 sc->bfe_tx_cons = i; 1115 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1116 } 1117 if(sc->bfe_tx_cnt == 0) 1118 ifp->if_timer = 0; 1119 else 1120 ifp->if_timer = 5; 1121 } 1122 1123 /* Pass a received packet up the stack */ 1124 static void 1125 bfe_rxeof(struct bfe_softc *sc) 1126 { 1127 struct mbuf *m; 1128 struct ifnet *ifp; 1129 struct bfe_rxheader *rxheader; 1130 struct bfe_data *r; 1131 int cons; 1132 u_int32_t status, current, len, flags; 1133 1134 BFE_LOCK_ASSERT(sc); 1135 cons = sc->bfe_rx_cons; 1136 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1137 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1138 1139 ifp = sc->bfe_ifp; 1140 1141 while(current != cons) { 1142 r = &sc->bfe_rx_ring[cons]; 1143 m = r->bfe_mbuf; 1144 rxheader = mtod(m, struct bfe_rxheader*); 1145 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1146 len = rxheader->len; 1147 r->bfe_mbuf = NULL; 1148 1149 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1150 flags = rxheader->flags; 1151 1152 len -= ETHER_CRC_LEN; 1153 1154 /* flag an error and try again */ 1155 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1156 ifp->if_ierrors++; 1157 if (flags & BFE_RX_FLAG_SERR) 1158 ifp->if_collisions++; 1159 bfe_list_newbuf(sc, cons, m); 1160 BFE_INC(cons, BFE_RX_LIST_CNT); 1161 continue; 1162 } 1163 1164 /* Go past the rx header */ 1165 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1166 m_adj(m, BFE_RX_OFFSET); 1167 m->m_len = m->m_pkthdr.len = len; 1168 } else { 1169 bfe_list_newbuf(sc, cons, m); 1170 ifp->if_ierrors++; 1171 BFE_INC(cons, BFE_RX_LIST_CNT); 1172 continue; 1173 } 1174 1175 ifp->if_ipackets++; 1176 m->m_pkthdr.rcvif = ifp; 1177 BFE_UNLOCK(sc); 1178 (*ifp->if_input)(ifp, m); 1179 BFE_LOCK(sc); 1180 1181 BFE_INC(cons, BFE_RX_LIST_CNT); 1182 } 1183 sc->bfe_rx_cons = cons; 1184 } 1185 1186 static void 1187 bfe_intr(void *xsc) 1188 { 1189 struct bfe_softc *sc = xsc; 1190 struct ifnet *ifp; 1191 u_int32_t istat, imask, flag; 1192 1193 ifp = sc->bfe_ifp; 1194 1195 BFE_LOCK(sc); 1196 1197 istat = CSR_READ_4(sc, BFE_ISTAT); 1198 imask = CSR_READ_4(sc, BFE_IMASK); 1199 1200 /* 1201 * Defer unsolicited interrupts - This is necessary because setting the 1202 * chips interrupt mask register to 0 doesn't actually stop the 1203 * interrupts 1204 */ 1205 istat &= imask; 1206 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1207 CSR_READ_4(sc, BFE_ISTAT); 1208 1209 /* not expecting this interrupt, disregard it */ 1210 if(istat == 0) { 1211 BFE_UNLOCK(sc); 1212 return; 1213 } 1214 1215 if(istat & BFE_ISTAT_ERRORS) { 1216 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1217 if(flag & BFE_STAT_EMASK) 1218 ifp->if_oerrors++; 1219 1220 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1221 if(flag & BFE_RX_FLAG_ERRORS) 1222 ifp->if_ierrors++; 1223 1224 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1225 bfe_init_locked(sc); 1226 } 1227 1228 /* A packet was received */ 1229 if(istat & BFE_ISTAT_RX) 1230 bfe_rxeof(sc); 1231 1232 /* A packet was sent */ 1233 if(istat & BFE_ISTAT_TX) 1234 bfe_txeof(sc); 1235 1236 /* We have packets pending, fire them out */ 1237 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1238 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1239 bfe_start_locked(ifp); 1240 1241 BFE_UNLOCK(sc); 1242 } 1243 1244 static int 1245 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1246 { 1247 struct bfe_desc *d = NULL; 1248 struct bfe_data *r = NULL; 1249 struct mbuf *m; 1250 u_int32_t frag, cur, cnt = 0; 1251 int chainlen = 0; 1252 int error; 1253 1254 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1255 return (ENOBUFS); 1256 1257 /* 1258 * Count the number of frags in this chain to see if 1259 * we need to m_defrag. Since the descriptor list is shared 1260 * by all packets, we'll m_defrag long chains so that they 1261 * do not use up the entire list, even if they would fit. 1262 */ 1263 for(m = *m_head; m != NULL; m = m->m_next) 1264 chainlen++; 1265 1266 1267 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1268 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1269 m = m_defrag(*m_head, M_DONTWAIT); 1270 if (m == NULL) 1271 return (ENOBUFS); 1272 *m_head = m; 1273 } 1274 1275 /* 1276 * Start packing the mbufs in this chain into 1277 * the fragment pointers. Stop when we run out 1278 * of fragments or hit the end of the mbuf chain. 1279 */ 1280 cur = frag = *txidx; 1281 cnt = 0; 1282 1283 for(m = *m_head; m != NULL; m = m->m_next) { 1284 if(m->m_len != 0) { 1285 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1286 return (ENOBUFS); 1287 1288 d = &sc->bfe_tx_list[cur]; 1289 r = &sc->bfe_tx_ring[cur]; 1290 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1291 /* always intterupt on completion */ 1292 d->bfe_ctrl |= BFE_DESC_IOC; 1293 if(cnt == 0) 1294 /* Set start of frame */ 1295 d->bfe_ctrl |= BFE_DESC_SOF; 1296 if(cur == BFE_TX_LIST_CNT - 1) 1297 /* 1298 * Tell the chip to wrap to the start of 1299 * the descriptor list 1300 */ 1301 d->bfe_ctrl |= BFE_DESC_EOT; 1302 1303 error = bus_dmamap_load(sc->bfe_tag, 1304 r->bfe_map, mtod(m, void*), m->m_len, 1305 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1306 if (error) 1307 return (ENOBUFS); 1308 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1309 BUS_DMASYNC_PREWRITE); 1310 1311 frag = cur; 1312 BFE_INC(cur, BFE_TX_LIST_CNT); 1313 cnt++; 1314 } 1315 } 1316 1317 if (m != NULL) 1318 return (ENOBUFS); 1319 1320 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1321 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1322 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1323 1324 *txidx = cur; 1325 sc->bfe_tx_cnt += cnt; 1326 return (0); 1327 } 1328 1329 /* 1330 * Set up to transmit a packet. 1331 */ 1332 static void 1333 bfe_start(struct ifnet *ifp) 1334 { 1335 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1336 bfe_start_locked(ifp); 1337 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1338 } 1339 1340 /* 1341 * Set up to transmit a packet. The softc is already locked. 1342 */ 1343 static void 1344 bfe_start_locked(struct ifnet *ifp) 1345 { 1346 struct bfe_softc *sc; 1347 struct mbuf *m_head = NULL; 1348 int idx, queued = 0; 1349 1350 sc = ifp->if_softc; 1351 idx = sc->bfe_tx_prod; 1352 1353 BFE_LOCK_ASSERT(sc); 1354 1355 /* 1356 * Not much point trying to send if the link is down 1357 * or we have nothing to send. 1358 */ 1359 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1360 return; 1361 1362 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1363 return; 1364 1365 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1366 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1367 if(m_head == NULL) 1368 break; 1369 1370 /* 1371 * Pack the data into the tx ring. If we dont have 1372 * enough room, let the chip drain the ring. 1373 */ 1374 if(bfe_encap(sc, &m_head, &idx)) { 1375 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1376 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1377 break; 1378 } 1379 1380 queued++; 1381 1382 /* 1383 * If there's a BPF listener, bounce a copy of this frame 1384 * to him. 1385 */ 1386 BPF_MTAP(ifp, m_head); 1387 } 1388 1389 if (queued) { 1390 sc->bfe_tx_prod = idx; 1391 /* Transmit - twice due to apparent hardware bug */ 1392 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1393 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1394 1395 /* 1396 * Set a timeout in case the chip goes out to lunch. 1397 */ 1398 ifp->if_timer = 5; 1399 } 1400 } 1401 1402 static void 1403 bfe_init(void *xsc) 1404 { 1405 BFE_LOCK((struct bfe_softc *)xsc); 1406 bfe_init_locked(xsc); 1407 BFE_UNLOCK((struct bfe_softc *)xsc); 1408 } 1409 1410 static void 1411 bfe_init_locked(void *xsc) 1412 { 1413 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1414 struct ifnet *ifp = sc->bfe_ifp; 1415 1416 BFE_LOCK_ASSERT(sc); 1417 1418 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1419 return; 1420 1421 bfe_stop(sc); 1422 bfe_chip_reset(sc); 1423 1424 if (bfe_list_rx_init(sc) == ENOBUFS) { 1425 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1426 sc->bfe_unit); 1427 bfe_stop(sc); 1428 return; 1429 } 1430 1431 bfe_set_rx_mode(sc); 1432 1433 /* Enable the chip and core */ 1434 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1435 /* Enable interrupts */ 1436 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1437 1438 bfe_ifmedia_upd(ifp); 1439 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1440 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1441 1442 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1443 } 1444 1445 /* 1446 * Set media options. 1447 */ 1448 static int 1449 bfe_ifmedia_upd(struct ifnet *ifp) 1450 { 1451 struct bfe_softc *sc; 1452 struct mii_data *mii; 1453 1454 sc = ifp->if_softc; 1455 1456 mii = device_get_softc(sc->bfe_miibus); 1457 sc->bfe_link = 0; 1458 if (mii->mii_instance) { 1459 struct mii_softc *miisc; 1460 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1461 miisc = LIST_NEXT(miisc, mii_list)) 1462 mii_phy_reset(miisc); 1463 } 1464 mii_mediachg(mii); 1465 1466 return (0); 1467 } 1468 1469 /* 1470 * Report current media status. 1471 */ 1472 static void 1473 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1474 { 1475 struct bfe_softc *sc = ifp->if_softc; 1476 struct mii_data *mii; 1477 1478 mii = device_get_softc(sc->bfe_miibus); 1479 mii_pollstat(mii); 1480 ifmr->ifm_active = mii->mii_media_active; 1481 ifmr->ifm_status = mii->mii_media_status; 1482 } 1483 1484 static int 1485 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1486 { 1487 struct bfe_softc *sc = ifp->if_softc; 1488 struct ifreq *ifr = (struct ifreq *) data; 1489 struct mii_data *mii; 1490 int error = 0; 1491 1492 switch(command) { 1493 case SIOCSIFFLAGS: 1494 BFE_LOCK(sc); 1495 if(ifp->if_flags & IFF_UP) 1496 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1497 bfe_set_rx_mode(sc); 1498 else 1499 bfe_init_locked(sc); 1500 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1501 bfe_stop(sc); 1502 BFE_UNLOCK(sc); 1503 break; 1504 case SIOCADDMULTI: 1505 case SIOCDELMULTI: 1506 BFE_LOCK(sc); 1507 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1508 bfe_set_rx_mode(sc); 1509 BFE_UNLOCK(sc); 1510 break; 1511 case SIOCGIFMEDIA: 1512 case SIOCSIFMEDIA: 1513 mii = device_get_softc(sc->bfe_miibus); 1514 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1515 command); 1516 break; 1517 default: 1518 error = ether_ioctl(ifp, command, data); 1519 break; 1520 } 1521 1522 return (error); 1523 } 1524 1525 static void 1526 bfe_watchdog(struct ifnet *ifp) 1527 { 1528 struct bfe_softc *sc; 1529 1530 sc = ifp->if_softc; 1531 1532 BFE_LOCK(sc); 1533 1534 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1535 1536 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1537 bfe_init_locked(sc); 1538 1539 ifp->if_oerrors++; 1540 1541 BFE_UNLOCK(sc); 1542 } 1543 1544 static void 1545 bfe_tick(void *xsc) 1546 { 1547 struct bfe_softc *sc = xsc; 1548 struct mii_data *mii; 1549 1550 if (sc == NULL) 1551 return; 1552 1553 BFE_LOCK(sc); 1554 1555 mii = device_get_softc(sc->bfe_miibus); 1556 1557 bfe_stats_update(sc); 1558 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1559 1560 if(sc->bfe_link) { 1561 BFE_UNLOCK(sc); 1562 return; 1563 } 1564 1565 mii_tick(mii); 1566 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1567 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1568 sc->bfe_link++; 1569 1570 BFE_UNLOCK(sc); 1571 } 1572 1573 /* 1574 * Stop the adapter and free any mbufs allocated to the 1575 * RX and TX lists. 1576 */ 1577 static void 1578 bfe_stop(struct bfe_softc *sc) 1579 { 1580 struct ifnet *ifp; 1581 1582 BFE_LOCK_ASSERT(sc); 1583 1584 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1585 1586 ifp = sc->bfe_ifp; 1587 1588 bfe_chip_halt(sc); 1589 bfe_tx_ring_free(sc); 1590 bfe_rx_ring_free(sc); 1591 1592 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1593 } 1594