1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Handle power management nonsense. 339 */ 340 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 341 u_int32_t membase, irq; 342 343 /* Save important PCI config data. */ 344 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 345 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 346 347 /* Reset the power state. */ 348 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 349 sc->bfe_unit, pci_get_powerstate(dev)); 350 351 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 352 353 /* Restore PCI config data. */ 354 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 355 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 356 } 357 358 /* 359 * Map control/status registers. 360 */ 361 pci_enable_busmaster(dev); 362 363 rid = BFE_PCI_MEMLO; 364 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 365 RF_ACTIVE); 366 if (sc->bfe_res == NULL) { 367 printf ("bfe%d: couldn't map memory\n", unit); 368 error = ENXIO; 369 goto fail; 370 } 371 372 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 373 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 374 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 375 376 /* Allocate interrupt */ 377 rid = 0; 378 379 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 380 RF_SHAREABLE | RF_ACTIVE); 381 if (sc->bfe_irq == NULL) { 382 printf("bfe%d: couldn't map interrupt\n", unit); 383 error = ENXIO; 384 goto fail; 385 } 386 387 if (bfe_dma_alloc(dev)) { 388 printf("bfe%d: failed to allocate DMA resources\n", 389 sc->bfe_unit); 390 bfe_release_resources(sc); 391 error = ENXIO; 392 goto fail; 393 } 394 395 /* Set up ifnet structure */ 396 ifp = &sc->arpcom.ac_if; 397 ifp->if_softc = sc; 398 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 399 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 400 ifp->if_ioctl = bfe_ioctl; 401 ifp->if_start = bfe_start; 402 ifp->if_watchdog = bfe_watchdog; 403 ifp->if_init = bfe_init; 404 ifp->if_mtu = ETHERMTU; 405 ifp->if_baudrate = 100000000; 406 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 407 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 408 IFQ_SET_READY(&ifp->if_snd); 409 410 bfe_get_config(sc); 411 412 /* Reset the chip and turn on the PHY */ 413 BFE_LOCK(sc); 414 bfe_chip_reset(sc); 415 BFE_UNLOCK(sc); 416 417 if (mii_phy_probe(dev, &sc->bfe_miibus, 418 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 419 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 420 error = ENXIO; 421 goto fail; 422 } 423 424 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 425 callout_handle_init(&sc->bfe_stat_ch); 426 427 /* 428 * Tell the upper layer(s) we support long frames. 429 */ 430 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 431 ifp->if_capabilities |= IFCAP_VLAN_MTU; 432 ifp->if_capenable |= IFCAP_VLAN_MTU; 433 434 /* 435 * Hook interrupt last to avoid having to lock softc 436 */ 437 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 438 bfe_intr, sc, &sc->bfe_intrhand); 439 440 if (error) { 441 bfe_release_resources(sc); 442 printf("bfe%d: couldn't set up irq\n", unit); 443 goto fail; 444 } 445 fail: 446 if(error) 447 bfe_release_resources(sc); 448 return (error); 449 } 450 451 static int 452 bfe_detach(device_t dev) 453 { 454 struct bfe_softc *sc; 455 struct ifnet *ifp; 456 457 sc = device_get_softc(dev); 458 459 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 460 BFE_LOCK(sc); 461 462 ifp = &sc->arpcom.ac_if; 463 464 if (device_is_attached(dev)) { 465 bfe_stop(sc); 466 ether_ifdetach(ifp); 467 } 468 469 bfe_chip_reset(sc); 470 471 bus_generic_detach(dev); 472 if(sc->bfe_miibus != NULL) 473 device_delete_child(dev, sc->bfe_miibus); 474 475 bfe_release_resources(sc); 476 BFE_UNLOCK(sc); 477 mtx_destroy(&sc->bfe_mtx); 478 479 return (0); 480 } 481 482 /* 483 * Stop all chip I/O so that the kernel's probe routines don't 484 * get confused by errant DMAs when rebooting. 485 */ 486 static void 487 bfe_shutdown(device_t dev) 488 { 489 struct bfe_softc *sc; 490 491 sc = device_get_softc(dev); 492 BFE_LOCK(sc); 493 bfe_stop(sc); 494 495 BFE_UNLOCK(sc); 496 return; 497 } 498 499 static int 500 bfe_miibus_readreg(device_t dev, int phy, int reg) 501 { 502 struct bfe_softc *sc; 503 u_int32_t ret; 504 505 sc = device_get_softc(dev); 506 if(phy != sc->bfe_phyaddr) 507 return (0); 508 bfe_readphy(sc, reg, &ret); 509 510 return (ret); 511 } 512 513 static int 514 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 515 { 516 struct bfe_softc *sc; 517 518 sc = device_get_softc(dev); 519 if(phy != sc->bfe_phyaddr) 520 return (0); 521 bfe_writephy(sc, reg, val); 522 523 return (0); 524 } 525 526 static void 527 bfe_miibus_statchg(device_t dev) 528 { 529 return; 530 } 531 532 static void 533 bfe_tx_ring_free(struct bfe_softc *sc) 534 { 535 int i; 536 537 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 538 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 539 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 540 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 541 bus_dmamap_unload(sc->bfe_tag, 542 sc->bfe_tx_ring[i].bfe_map); 543 } 544 } 545 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 546 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 547 } 548 549 static void 550 bfe_rx_ring_free(struct bfe_softc *sc) 551 { 552 int i; 553 554 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 555 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 556 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 557 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 558 bus_dmamap_unload(sc->bfe_tag, 559 sc->bfe_rx_ring[i].bfe_map); 560 } 561 } 562 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 563 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 564 } 565 566 static int 567 bfe_list_rx_init(struct bfe_softc *sc) 568 { 569 int i; 570 571 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 572 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 573 return (ENOBUFS); 574 } 575 576 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 577 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 578 579 sc->bfe_rx_cons = 0; 580 581 return (0); 582 } 583 584 static int 585 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 586 { 587 struct bfe_rxheader *rx_header; 588 struct bfe_desc *d; 589 struct bfe_data *r; 590 u_int32_t ctrl; 591 592 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 593 return (EINVAL); 594 595 if(m == NULL) { 596 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 597 if(m == NULL) 598 return (ENOBUFS); 599 m->m_len = m->m_pkthdr.len = MCLBYTES; 600 } 601 else 602 m->m_data = m->m_ext.ext_buf; 603 604 rx_header = mtod(m, struct bfe_rxheader *); 605 rx_header->len = 0; 606 rx_header->flags = 0; 607 608 /* Map the mbuf into DMA */ 609 sc->bfe_rx_cnt = c; 610 d = &sc->bfe_rx_list[c]; 611 r = &sc->bfe_rx_ring[c]; 612 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 613 MCLBYTES, bfe_dma_map_desc, d, 0); 614 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 615 616 ctrl = ETHER_MAX_LEN + 32; 617 618 if(c == BFE_RX_LIST_CNT - 1) 619 ctrl |= BFE_DESC_EOT; 620 621 d->bfe_ctrl = ctrl; 622 r->bfe_mbuf = m; 623 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 624 return (0); 625 } 626 627 static void 628 bfe_get_config(struct bfe_softc *sc) 629 { 630 u_int8_t eeprom[128]; 631 632 bfe_read_eeprom(sc, eeprom); 633 634 sc->arpcom.ac_enaddr[0] = eeprom[79]; 635 sc->arpcom.ac_enaddr[1] = eeprom[78]; 636 sc->arpcom.ac_enaddr[2] = eeprom[81]; 637 sc->arpcom.ac_enaddr[3] = eeprom[80]; 638 sc->arpcom.ac_enaddr[4] = eeprom[83]; 639 sc->arpcom.ac_enaddr[5] = eeprom[82]; 640 641 sc->bfe_phyaddr = eeprom[90] & 0x1f; 642 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 643 644 sc->bfe_core_unit = 0; 645 sc->bfe_dma_offset = BFE_PCI_DMA; 646 } 647 648 static void 649 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 650 { 651 u_int32_t bar_orig, pci_rev, val; 652 653 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 654 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 655 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 656 657 val = CSR_READ_4(sc, BFE_SBINTVEC); 658 val |= cores; 659 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 660 661 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 662 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 663 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 664 665 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 666 } 667 668 static void 669 bfe_clear_stats(struct bfe_softc *sc) 670 { 671 u_long reg; 672 673 BFE_LOCK_ASSERT(sc); 674 675 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 676 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 677 CSR_READ_4(sc, reg); 678 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 679 CSR_READ_4(sc, reg); 680 } 681 682 static int 683 bfe_resetphy(struct bfe_softc *sc) 684 { 685 u_int32_t val; 686 687 bfe_writephy(sc, 0, BMCR_RESET); 688 DELAY(100); 689 bfe_readphy(sc, 0, &val); 690 if (val & BMCR_RESET) { 691 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 692 return (ENXIO); 693 } 694 return (0); 695 } 696 697 static void 698 bfe_chip_halt(struct bfe_softc *sc) 699 { 700 BFE_LOCK_ASSERT(sc); 701 /* disable interrupts - not that it actually does..*/ 702 CSR_WRITE_4(sc, BFE_IMASK, 0); 703 CSR_READ_4(sc, BFE_IMASK); 704 705 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 706 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 707 708 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 710 DELAY(10); 711 } 712 713 static void 714 bfe_chip_reset(struct bfe_softc *sc) 715 { 716 u_int32_t val; 717 718 BFE_LOCK_ASSERT(sc); 719 720 /* Set the interrupt vector for the enet core */ 721 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 722 723 /* is core up? */ 724 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 725 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 726 if (val == BFE_CLOCK) { 727 /* It is, so shut it down */ 728 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 729 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 730 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 731 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 732 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 733 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 734 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 735 100, 0); 736 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 737 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 738 } 739 740 bfe_core_reset(sc); 741 bfe_clear_stats(sc); 742 743 /* 744 * We want the phy registers to be accessible even when 745 * the driver is "downed" so initialize MDC preamble, frequency, 746 * and whether internal or external phy here. 747 */ 748 749 /* 4402 has 62.5Mhz SB clock and internal phy */ 750 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 751 752 /* Internal or external PHY? */ 753 val = CSR_READ_4(sc, BFE_DEVCTRL); 754 if(!(val & BFE_IPP)) 755 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 756 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 757 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 758 DELAY(100); 759 } 760 761 /* Enable CRC32 generation and set proper LED modes */ 762 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 763 764 /* Reset or clear powerdown control bit */ 765 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 766 767 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 768 BFE_LAZY_FC_MASK)); 769 770 /* 771 * We don't want lazy interrupts, so just send them at 772 * the end of a frame, please 773 */ 774 BFE_OR(sc, BFE_RCV_LAZY, 0); 775 776 /* Set max lengths, accounting for VLAN tags */ 777 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 778 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 779 780 /* Set watermark XXX - magic */ 781 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 782 783 /* 784 * Initialise DMA channels 785 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 786 */ 787 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 788 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 789 790 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 791 BFE_RX_CTRL_ENABLE); 792 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 793 794 bfe_resetphy(sc); 795 bfe_setupphy(sc); 796 } 797 798 static void 799 bfe_core_disable(struct bfe_softc *sc) 800 { 801 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 802 return; 803 804 /* 805 * Set reject, wait for it set, then wait for the core to stop 806 * being busy, then set reset and reject and enable the clocks. 807 */ 808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 809 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 810 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 811 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 812 BFE_RESET)); 813 CSR_READ_4(sc, BFE_SBTMSLOW); 814 DELAY(10); 815 /* Leave reset and reject set */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 817 DELAY(10); 818 } 819 820 static void 821 bfe_core_reset(struct bfe_softc *sc) 822 { 823 u_int32_t val; 824 825 /* Disable the core */ 826 bfe_core_disable(sc); 827 828 /* and bring it back up */ 829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 830 CSR_READ_4(sc, BFE_SBTMSLOW); 831 DELAY(10); 832 833 /* Chip bug, clear SERR, IB and TO if they are set. */ 834 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 835 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 836 val = CSR_READ_4(sc, BFE_SBIMSTATE); 837 if (val & (BFE_IBE | BFE_TO)) 838 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 839 840 /* Clear reset and allow it to move through the core */ 841 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 842 CSR_READ_4(sc, BFE_SBTMSLOW); 843 DELAY(10); 844 845 /* Leave the clock set */ 846 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 847 CSR_READ_4(sc, BFE_SBTMSLOW); 848 DELAY(10); 849 } 850 851 static void 852 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 853 { 854 u_int32_t val; 855 856 val = ((u_int32_t) data[2]) << 24; 857 val |= ((u_int32_t) data[3]) << 16; 858 val |= ((u_int32_t) data[4]) << 8; 859 val |= ((u_int32_t) data[5]); 860 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 861 val = (BFE_CAM_HI_VALID | 862 (((u_int32_t) data[0]) << 8) | 863 (((u_int32_t) data[1]))); 864 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 865 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 866 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 867 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 868 } 869 870 static void 871 bfe_set_rx_mode(struct bfe_softc *sc) 872 { 873 struct ifnet *ifp = &sc->arpcom.ac_if; 874 struct ifmultiaddr *ifma; 875 u_int32_t val; 876 int i = 0; 877 878 val = CSR_READ_4(sc, BFE_RXCONF); 879 880 if (ifp->if_flags & IFF_PROMISC) 881 val |= BFE_RXCONF_PROMISC; 882 else 883 val &= ~BFE_RXCONF_PROMISC; 884 885 if (ifp->if_flags & IFF_BROADCAST) 886 val &= ~BFE_RXCONF_DBCAST; 887 else 888 val |= BFE_RXCONF_DBCAST; 889 890 891 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 892 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 893 894 if (ifp->if_flags & IFF_ALLMULTI) 895 val |= BFE_RXCONF_ALLMULTI; 896 else { 897 val &= ~BFE_RXCONF_ALLMULTI; 898 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 899 if (ifma->ifma_addr->sa_family != AF_LINK) 900 continue; 901 bfe_cam_write(sc, 902 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 903 } 904 } 905 906 CSR_WRITE_4(sc, BFE_RXCONF, val); 907 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 908 } 909 910 static void 911 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 912 { 913 u_int32_t *ptr; 914 915 ptr = arg; 916 *ptr = segs->ds_addr; 917 } 918 919 static void 920 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 921 { 922 struct bfe_desc *d; 923 924 d = arg; 925 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 926 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 927 } 928 929 static void 930 bfe_release_resources(struct bfe_softc *sc) 931 { 932 device_t dev; 933 int i; 934 935 dev = sc->bfe_dev; 936 937 if (sc->bfe_vpd_prodname != NULL) 938 free(sc->bfe_vpd_prodname, M_DEVBUF); 939 940 if (sc->bfe_vpd_readonly != NULL) 941 free(sc->bfe_vpd_readonly, M_DEVBUF); 942 943 if (sc->bfe_intrhand != NULL) 944 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 945 946 if (sc->bfe_irq != NULL) 947 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 948 949 if (sc->bfe_res != NULL) 950 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 951 952 if(sc->bfe_tx_tag != NULL) { 953 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 954 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 955 sc->bfe_tx_map); 956 bus_dma_tag_destroy(sc->bfe_tx_tag); 957 sc->bfe_tx_tag = NULL; 958 } 959 960 if(sc->bfe_rx_tag != NULL) { 961 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 962 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 963 sc->bfe_rx_map); 964 bus_dma_tag_destroy(sc->bfe_rx_tag); 965 sc->bfe_rx_tag = NULL; 966 } 967 968 if(sc->bfe_tag != NULL) { 969 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 970 bus_dmamap_destroy(sc->bfe_tag, 971 sc->bfe_tx_ring[i].bfe_map); 972 } 973 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 974 bus_dmamap_destroy(sc->bfe_tag, 975 sc->bfe_rx_ring[i].bfe_map); 976 } 977 bus_dma_tag_destroy(sc->bfe_tag); 978 sc->bfe_tag = NULL; 979 } 980 981 if(sc->bfe_parent_tag != NULL) 982 bus_dma_tag_destroy(sc->bfe_parent_tag); 983 984 return; 985 } 986 987 static void 988 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 989 { 990 long i; 991 u_int16_t *ptr = (u_int16_t *)data; 992 993 for(i = 0; i < 128; i += 2) 994 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 995 } 996 997 static int 998 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 999 u_long timeout, const int clear) 1000 { 1001 u_long i; 1002 1003 for (i = 0; i < timeout; i++) { 1004 u_int32_t val = CSR_READ_4(sc, reg); 1005 1006 if (clear && !(val & bit)) 1007 break; 1008 if (!clear && (val & bit)) 1009 break; 1010 DELAY(10); 1011 } 1012 if (i == timeout) { 1013 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1014 "%x to %s.\n", sc->bfe_unit, bit, reg, 1015 (clear ? "clear" : "set")); 1016 return (-1); 1017 } 1018 return (0); 1019 } 1020 1021 static int 1022 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1023 { 1024 int err; 1025 1026 /* Clear MII ISR */ 1027 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1028 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1029 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1030 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1031 (reg << BFE_MDIO_RA_SHIFT) | 1032 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1033 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1034 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1035 1036 return (err); 1037 } 1038 1039 static int 1040 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1041 { 1042 int status; 1043 1044 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1045 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1046 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1047 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1048 (reg << BFE_MDIO_RA_SHIFT) | 1049 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1050 (val & BFE_MDIO_DATA_DATA))); 1051 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1052 1053 return (status); 1054 } 1055 1056 /* 1057 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1058 * twice 1059 */ 1060 static int 1061 bfe_setupphy(struct bfe_softc *sc) 1062 { 1063 u_int32_t val; 1064 1065 /* Enable activity LED */ 1066 bfe_readphy(sc, 26, &val); 1067 bfe_writephy(sc, 26, val & 0x7fff); 1068 bfe_readphy(sc, 26, &val); 1069 1070 /* Enable traffic meter LED mode */ 1071 bfe_readphy(sc, 27, &val); 1072 bfe_writephy(sc, 27, val | (1 << 6)); 1073 1074 return (0); 1075 } 1076 1077 static void 1078 bfe_stats_update(struct bfe_softc *sc) 1079 { 1080 u_long reg; 1081 u_int32_t *val; 1082 1083 val = &sc->bfe_hwstats.tx_good_octets; 1084 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1085 *val++ += CSR_READ_4(sc, reg); 1086 } 1087 val = &sc->bfe_hwstats.rx_good_octets; 1088 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1089 *val++ += CSR_READ_4(sc, reg); 1090 } 1091 } 1092 1093 static void 1094 bfe_txeof(struct bfe_softc *sc) 1095 { 1096 struct ifnet *ifp; 1097 int i, chipidx; 1098 1099 BFE_LOCK_ASSERT(sc); 1100 1101 ifp = &sc->arpcom.ac_if; 1102 1103 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1104 chipidx /= sizeof(struct bfe_desc); 1105 1106 i = sc->bfe_tx_cons; 1107 /* Go through the mbufs and free those that have been transmitted */ 1108 while(i != chipidx) { 1109 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1110 if(r->bfe_mbuf != NULL) { 1111 ifp->if_opackets++; 1112 m_freem(r->bfe_mbuf); 1113 r->bfe_mbuf = NULL; 1114 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1115 } 1116 sc->bfe_tx_cnt--; 1117 BFE_INC(i, BFE_TX_LIST_CNT); 1118 } 1119 1120 if(i != sc->bfe_tx_cons) { 1121 /* we freed up some mbufs */ 1122 sc->bfe_tx_cons = i; 1123 ifp->if_flags &= ~IFF_OACTIVE; 1124 } 1125 if(sc->bfe_tx_cnt == 0) 1126 ifp->if_timer = 0; 1127 else 1128 ifp->if_timer = 5; 1129 } 1130 1131 /* Pass a received packet up the stack */ 1132 static void 1133 bfe_rxeof(struct bfe_softc *sc) 1134 { 1135 struct mbuf *m; 1136 struct ifnet *ifp; 1137 struct bfe_rxheader *rxheader; 1138 struct bfe_data *r; 1139 int cons; 1140 u_int32_t status, current, len, flags; 1141 1142 BFE_LOCK_ASSERT(sc); 1143 cons = sc->bfe_rx_cons; 1144 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1145 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1146 1147 ifp = &sc->arpcom.ac_if; 1148 1149 while(current != cons) { 1150 r = &sc->bfe_rx_ring[cons]; 1151 m = r->bfe_mbuf; 1152 rxheader = mtod(m, struct bfe_rxheader*); 1153 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1154 len = rxheader->len; 1155 r->bfe_mbuf = NULL; 1156 1157 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1158 flags = rxheader->flags; 1159 1160 len -= ETHER_CRC_LEN; 1161 1162 /* flag an error and try again */ 1163 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1164 ifp->if_ierrors++; 1165 if (flags & BFE_RX_FLAG_SERR) 1166 ifp->if_collisions++; 1167 bfe_list_newbuf(sc, cons, m); 1168 BFE_INC(cons, BFE_RX_LIST_CNT); 1169 continue; 1170 } 1171 1172 /* Go past the rx header */ 1173 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1174 m_adj(m, BFE_RX_OFFSET); 1175 m->m_len = m->m_pkthdr.len = len; 1176 } else { 1177 bfe_list_newbuf(sc, cons, m); 1178 ifp->if_ierrors++; 1179 BFE_INC(cons, BFE_RX_LIST_CNT); 1180 continue; 1181 } 1182 1183 ifp->if_ipackets++; 1184 m->m_pkthdr.rcvif = ifp; 1185 BFE_UNLOCK(sc); 1186 (*ifp->if_input)(ifp, m); 1187 BFE_LOCK(sc); 1188 1189 BFE_INC(cons, BFE_RX_LIST_CNT); 1190 } 1191 sc->bfe_rx_cons = cons; 1192 } 1193 1194 static void 1195 bfe_intr(void *xsc) 1196 { 1197 struct bfe_softc *sc = xsc; 1198 struct ifnet *ifp; 1199 u_int32_t istat, imask, flag; 1200 1201 ifp = &sc->arpcom.ac_if; 1202 1203 BFE_LOCK(sc); 1204 1205 istat = CSR_READ_4(sc, BFE_ISTAT); 1206 imask = CSR_READ_4(sc, BFE_IMASK); 1207 1208 /* 1209 * Defer unsolicited interrupts - This is necessary because setting the 1210 * chips interrupt mask register to 0 doesn't actually stop the 1211 * interrupts 1212 */ 1213 istat &= imask; 1214 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1215 CSR_READ_4(sc, BFE_ISTAT); 1216 1217 /* not expecting this interrupt, disregard it */ 1218 if(istat == 0) { 1219 BFE_UNLOCK(sc); 1220 return; 1221 } 1222 1223 if(istat & BFE_ISTAT_ERRORS) { 1224 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1225 if(flag & BFE_STAT_EMASK) 1226 ifp->if_oerrors++; 1227 1228 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1229 if(flag & BFE_RX_FLAG_ERRORS) 1230 ifp->if_ierrors++; 1231 1232 ifp->if_flags &= ~IFF_RUNNING; 1233 bfe_init_locked(sc); 1234 } 1235 1236 /* A packet was received */ 1237 if(istat & BFE_ISTAT_RX) 1238 bfe_rxeof(sc); 1239 1240 /* A packet was sent */ 1241 if(istat & BFE_ISTAT_TX) 1242 bfe_txeof(sc); 1243 1244 /* We have packets pending, fire them out */ 1245 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1246 bfe_start_locked(ifp); 1247 1248 BFE_UNLOCK(sc); 1249 } 1250 1251 static int 1252 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1253 { 1254 struct bfe_desc *d = NULL; 1255 struct bfe_data *r = NULL; 1256 struct mbuf *m; 1257 u_int32_t frag, cur, cnt = 0; 1258 int chainlen = 0; 1259 1260 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1261 return (ENOBUFS); 1262 1263 /* 1264 * Count the number of frags in this chain to see if 1265 * we need to m_defrag. Since the descriptor list is shared 1266 * by all packets, we'll m_defrag long chains so that they 1267 * do not use up the entire list, even if they would fit. 1268 */ 1269 for(m = m_head; m != NULL; m = m->m_next) 1270 chainlen++; 1271 1272 1273 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1274 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1275 m = m_defrag(m_head, M_DONTWAIT); 1276 if (m == NULL) 1277 return (ENOBUFS); 1278 m_head = m; 1279 } 1280 1281 /* 1282 * Start packing the mbufs in this chain into 1283 * the fragment pointers. Stop when we run out 1284 * of fragments or hit the end of the mbuf chain. 1285 */ 1286 m = m_head; 1287 cur = frag = *txidx; 1288 cnt = 0; 1289 1290 for(m = m_head; m != NULL; m = m->m_next) { 1291 if(m->m_len != 0) { 1292 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1293 return (ENOBUFS); 1294 1295 d = &sc->bfe_tx_list[cur]; 1296 r = &sc->bfe_tx_ring[cur]; 1297 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1298 /* always intterupt on completion */ 1299 d->bfe_ctrl |= BFE_DESC_IOC; 1300 if(cnt == 0) 1301 /* Set start of frame */ 1302 d->bfe_ctrl |= BFE_DESC_SOF; 1303 if(cur == BFE_TX_LIST_CNT - 1) 1304 /* 1305 * Tell the chip to wrap to the start of 1306 * the descriptor list 1307 */ 1308 d->bfe_ctrl |= BFE_DESC_EOT; 1309 1310 bus_dmamap_load(sc->bfe_tag, 1311 r->bfe_map, mtod(m, void*), m->m_len, 1312 bfe_dma_map_desc, d, 0); 1313 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1314 BUS_DMASYNC_PREREAD); 1315 1316 frag = cur; 1317 BFE_INC(cur, BFE_TX_LIST_CNT); 1318 cnt++; 1319 } 1320 } 1321 1322 if (m != NULL) 1323 return (ENOBUFS); 1324 1325 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1326 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1327 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1328 1329 *txidx = cur; 1330 sc->bfe_tx_cnt += cnt; 1331 return (0); 1332 } 1333 1334 /* 1335 * Set up to transmit a packet. 1336 */ 1337 static void 1338 bfe_start(struct ifnet *ifp) 1339 { 1340 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1341 bfe_start_locked(ifp); 1342 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1343 } 1344 1345 /* 1346 * Set up to transmit a packet. The softc is already locked. 1347 */ 1348 static void 1349 bfe_start_locked(struct ifnet *ifp) 1350 { 1351 struct bfe_softc *sc; 1352 struct mbuf *m_head = NULL; 1353 int idx, queued = 0; 1354 1355 sc = ifp->if_softc; 1356 idx = sc->bfe_tx_prod; 1357 1358 BFE_LOCK_ASSERT(sc); 1359 1360 /* 1361 * Not much point trying to send if the link is down 1362 * or we have nothing to send. 1363 */ 1364 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1365 return; 1366 1367 if (ifp->if_flags & IFF_OACTIVE) 1368 return; 1369 1370 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1371 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1372 if(m_head == NULL) 1373 break; 1374 1375 /* 1376 * Pack the data into the tx ring. If we dont have 1377 * enough room, let the chip drain the ring. 1378 */ 1379 if(bfe_encap(sc, m_head, &idx)) { 1380 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1381 ifp->if_flags |= IFF_OACTIVE; 1382 break; 1383 } 1384 1385 queued++; 1386 1387 /* 1388 * If there's a BPF listener, bounce a copy of this frame 1389 * to him. 1390 */ 1391 BPF_MTAP(ifp, m_head); 1392 } 1393 1394 if (queued) { 1395 sc->bfe_tx_prod = idx; 1396 /* Transmit - twice due to apparent hardware bug */ 1397 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1398 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1399 1400 /* 1401 * Set a timeout in case the chip goes out to lunch. 1402 */ 1403 ifp->if_timer = 5; 1404 } 1405 } 1406 1407 static void 1408 bfe_init(void *xsc) 1409 { 1410 BFE_LOCK((struct bfe_softc *)xsc); 1411 bfe_init_locked(xsc); 1412 BFE_UNLOCK((struct bfe_softc *)xsc); 1413 } 1414 1415 static void 1416 bfe_init_locked(void *xsc) 1417 { 1418 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1419 struct ifnet *ifp = &sc->arpcom.ac_if; 1420 1421 BFE_LOCK_ASSERT(sc); 1422 1423 if (ifp->if_flags & IFF_RUNNING) 1424 return; 1425 1426 bfe_stop(sc); 1427 bfe_chip_reset(sc); 1428 1429 if (bfe_list_rx_init(sc) == ENOBUFS) { 1430 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1431 sc->bfe_unit); 1432 bfe_stop(sc); 1433 return; 1434 } 1435 1436 bfe_set_rx_mode(sc); 1437 1438 /* Enable the chip and core */ 1439 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1440 /* Enable interrupts */ 1441 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1442 1443 bfe_ifmedia_upd(ifp); 1444 ifp->if_flags |= IFF_RUNNING; 1445 ifp->if_flags &= ~IFF_OACTIVE; 1446 1447 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1448 } 1449 1450 /* 1451 * Set media options. 1452 */ 1453 static int 1454 bfe_ifmedia_upd(struct ifnet *ifp) 1455 { 1456 struct bfe_softc *sc; 1457 struct mii_data *mii; 1458 1459 sc = ifp->if_softc; 1460 1461 mii = device_get_softc(sc->bfe_miibus); 1462 sc->bfe_link = 0; 1463 if (mii->mii_instance) { 1464 struct mii_softc *miisc; 1465 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1466 miisc = LIST_NEXT(miisc, mii_list)) 1467 mii_phy_reset(miisc); 1468 } 1469 mii_mediachg(mii); 1470 1471 return (0); 1472 } 1473 1474 /* 1475 * Report current media status. 1476 */ 1477 static void 1478 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1479 { 1480 struct bfe_softc *sc = ifp->if_softc; 1481 struct mii_data *mii; 1482 1483 mii = device_get_softc(sc->bfe_miibus); 1484 mii_pollstat(mii); 1485 ifmr->ifm_active = mii->mii_media_active; 1486 ifmr->ifm_status = mii->mii_media_status; 1487 } 1488 1489 static int 1490 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1491 { 1492 struct bfe_softc *sc = ifp->if_softc; 1493 struct ifreq *ifr = (struct ifreq *) data; 1494 struct mii_data *mii; 1495 int error = 0; 1496 1497 switch(command) { 1498 case SIOCSIFFLAGS: 1499 BFE_LOCK(sc); 1500 if(ifp->if_flags & IFF_UP) 1501 if(ifp->if_flags & IFF_RUNNING) 1502 bfe_set_rx_mode(sc); 1503 else 1504 bfe_init_locked(sc); 1505 else if(ifp->if_flags & IFF_RUNNING) 1506 bfe_stop(sc); 1507 BFE_UNLOCK(sc); 1508 break; 1509 case SIOCADDMULTI: 1510 case SIOCDELMULTI: 1511 BFE_LOCK(sc); 1512 if(ifp->if_flags & IFF_RUNNING) 1513 bfe_set_rx_mode(sc); 1514 BFE_UNLOCK(sc); 1515 break; 1516 case SIOCGIFMEDIA: 1517 case SIOCSIFMEDIA: 1518 mii = device_get_softc(sc->bfe_miibus); 1519 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1520 command); 1521 break; 1522 default: 1523 error = ether_ioctl(ifp, command, data); 1524 break; 1525 } 1526 1527 return (error); 1528 } 1529 1530 static void 1531 bfe_watchdog(struct ifnet *ifp) 1532 { 1533 struct bfe_softc *sc; 1534 1535 sc = ifp->if_softc; 1536 1537 BFE_LOCK(sc); 1538 1539 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1540 1541 ifp->if_flags &= ~IFF_RUNNING; 1542 bfe_init_locked(sc); 1543 1544 ifp->if_oerrors++; 1545 1546 BFE_UNLOCK(sc); 1547 } 1548 1549 static void 1550 bfe_tick(void *xsc) 1551 { 1552 struct bfe_softc *sc = xsc; 1553 struct mii_data *mii; 1554 1555 if (sc == NULL) 1556 return; 1557 1558 BFE_LOCK(sc); 1559 1560 mii = device_get_softc(sc->bfe_miibus); 1561 1562 bfe_stats_update(sc); 1563 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1564 1565 if(sc->bfe_link) { 1566 BFE_UNLOCK(sc); 1567 return; 1568 } 1569 1570 mii_tick(mii); 1571 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1572 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1573 sc->bfe_link++; 1574 1575 BFE_UNLOCK(sc); 1576 } 1577 1578 /* 1579 * Stop the adapter and free any mbufs allocated to the 1580 * RX and TX lists. 1581 */ 1582 static void 1583 bfe_stop(struct bfe_softc *sc) 1584 { 1585 struct ifnet *ifp; 1586 1587 BFE_LOCK_ASSERT(sc); 1588 1589 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1590 1591 ifp = &sc->arpcom.ac_if; 1592 1593 bfe_chip_halt(sc); 1594 bfe_tx_ring_free(sc); 1595 bfe_rx_ring_free(sc); 1596 1597 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1598 } 1599