1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6 /* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #include <net/bpf.h> 49 50 #include <net/if_types.h> 51 #include <net/if_vlan_var.h> 52 53 #include <netinet/in_systm.h> 54 #include <netinet/in.h> 55 #include <netinet/ip.h> 56 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include "miidevs.h" 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <dev/bfe/if_bfereg.h> 72 73 MODULE_DEPEND(bfe, pci, 1, 1, 1); 74 MODULE_DEPEND(bfe, ether, 1, 1, 1); 75 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77 /* "controller miibus0" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82 static struct bfe_type bfe_devs[] = { 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95 static void bfe_init (void *); 96 static void bfe_stop (struct bfe_softc *); 97 static void bfe_watchdog (struct ifnet *); 98 static void bfe_shutdown (device_t); 99 static void bfe_tick (void *); 100 static void bfe_txeof (struct bfe_softc *); 101 static void bfe_rxeof (struct bfe_softc *); 102 static void bfe_set_rx_mode (struct bfe_softc *); 103 static int bfe_list_rx_init (struct bfe_softc *); 104 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105 static void bfe_rx_ring_free (struct bfe_softc *); 106 107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108 static int bfe_ifmedia_upd (struct ifnet *); 109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 static int bfe_miibus_readreg (device_t, int, int); 111 static int bfe_miibus_writereg (device_t, int, int, int); 112 static void bfe_miibus_statchg (device_t); 113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115 static void bfe_get_config (struct bfe_softc *sc); 116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117 static void bfe_stats_update (struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121 static int bfe_resetphy (struct bfe_softc *); 122 static int bfe_setupphy (struct bfe_softc *); 123 static void bfe_chip_reset (struct bfe_softc *); 124 static void bfe_chip_halt (struct bfe_softc *); 125 static void bfe_core_reset (struct bfe_softc *); 126 static void bfe_core_disable (struct bfe_softc *); 127 static int bfe_dma_alloc (device_t); 128 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149 }; 150 151 static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155 }; 156 157 static devclass_t bfe_devclass; 158 159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162 /* 163 * Probe for a Broadcom 4401 chip. 164 */ 165 static int 166 bfe_probe(device_t dev) 167 { 168 struct bfe_type *t; 169 struct bfe_softc *sc; 170 171 t = bfe_devs; 172 173 sc = device_get_softc(dev); 174 bzero(sc, sizeof(struct bfe_softc)); 175 sc->bfe_unit = device_get_unit(dev); 176 sc->bfe_dev = dev; 177 178 while(t->bfe_name != NULL) { 179 if ((pci_get_vendor(dev) == t->bfe_vid) && 180 (pci_get_device(dev) == t->bfe_did)) { 181 device_set_desc_copy(dev, t->bfe_name); 182 return(0); 183 } 184 t++; 185 } 186 187 return(ENXIO); 188 } 189 190 static int 191 bfe_dma_alloc(device_t dev) 192 { 193 struct bfe_softc *sc; 194 int error, i; 195 196 sc = device_get_softc(dev); 197 198 /* parent tag */ 199 error = bus_dma_tag_create(NULL, /* parent */ 200 PAGE_SIZE, 0, /* alignment, boundary */ 201 BUS_SPACE_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 MAXBSIZE, /* maxsize */ 205 BUS_SPACE_UNRESTRICTED, /* num of segments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207 BUS_DMA_ALLOCNOW, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 213 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 214 NULL, NULL, BFE_TX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 215 0, NULL, NULL, &sc->bfe_tx_tag); 216 217 if (error) { 218 device_printf(dev, "could not allocate dma tag\n"); 219 return(ENOMEM); 220 } 221 222 /* tag for RX ring */ 223 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 224 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 225 NULL, NULL, BFE_RX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 226 0, NULL, NULL, &sc->bfe_rx_tag); 227 228 if (error) { 229 device_printf(dev, "could not allocate dma tag\n"); 230 return(ENOMEM); 231 } 232 233 /* tag for mbufs */ 234 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 236 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->bfe_tag); 237 238 if (error) { 239 device_printf(dev, "could not allocate dma tag\n"); 240 return(ENOMEM); 241 } 242 243 /* pre allocate dmamaps for RX list */ 244 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 245 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 246 if (error) { 247 device_printf(dev, "cannot create DMA map for RX\n"); 248 return(ENOMEM); 249 } 250 } 251 252 /* pre allocate dmamaps for TX list */ 253 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 254 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 255 if (error) { 256 device_printf(dev, "cannot create DMA map for TX\n"); 257 return(ENOMEM); 258 } 259 } 260 261 /* Alloc dma for rx ring */ 262 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 263 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 264 265 if(error) 266 return(ENOMEM); 267 268 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 269 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 270 sc->bfe_rx_list, sizeof(struct bfe_desc), 271 bfe_dma_map, &sc->bfe_rx_dma, 0); 272 273 if(error) 274 return(ENOMEM); 275 276 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 277 278 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 279 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 280 if (error) 281 return(ENOMEM); 282 283 284 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 285 sc->bfe_tx_list, sizeof(struct bfe_desc), 286 bfe_dma_map, &sc->bfe_tx_dma, 0); 287 if(error) 288 return(ENOMEM); 289 290 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 291 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 292 293 return(0); 294 } 295 296 static int 297 bfe_attach(device_t dev) 298 { 299 struct ifnet *ifp; 300 struct bfe_softc *sc; 301 int unit, error = 0, rid; 302 303 sc = device_get_softc(dev); 304 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 305 MTX_DEF | MTX_RECURSE); 306 307 unit = device_get_unit(dev); 308 sc->bfe_dev = dev; 309 sc->bfe_unit = unit; 310 311 /* 312 * Handle power management nonsense. 313 */ 314 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 315 u_int32_t membase, irq; 316 317 /* Save important PCI config data. */ 318 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 319 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 320 321 /* Reset the power state. */ 322 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 323 sc->bfe_unit, pci_get_powerstate(dev)); 324 325 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 326 327 /* Restore PCI config data. */ 328 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 329 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 330 } 331 332 /* 333 * Map control/status registers. 334 */ 335 pci_enable_busmaster(dev); 336 337 rid = BFE_PCI_MEMLO; 338 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 339 RF_ACTIVE); 340 if (sc->bfe_res == NULL) { 341 printf ("bfe%d: couldn't map memory\n", unit); 342 error = ENXIO; 343 goto fail; 344 } 345 346 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 347 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 348 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 349 350 /* Allocate interrupt */ 351 rid = 0; 352 353 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 354 RF_SHAREABLE | RF_ACTIVE); 355 if (sc->bfe_irq == NULL) { 356 printf("bfe%d: couldn't map interrupt\n", unit); 357 error = ENXIO; 358 goto fail; 359 } 360 361 if (bfe_dma_alloc(dev)) { 362 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit); 363 bfe_release_resources(sc); 364 error = ENXIO; 365 goto fail; 366 } 367 368 /* Set up ifnet structure */ 369 ifp = &sc->arpcom.ac_if; 370 ifp->if_softc = sc; 371 ifp->if_unit = sc->bfe_unit; 372 ifp->if_name = "bfe"; 373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 374 ifp->if_ioctl = bfe_ioctl; 375 ifp->if_output = ether_output; 376 ifp->if_start = bfe_start; 377 ifp->if_watchdog = bfe_watchdog; 378 ifp->if_init = bfe_init; 379 ifp->if_mtu = ETHERMTU; 380 ifp->if_baudrate = 10000000; 381 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 382 383 bfe_get_config(sc); 384 385 printf("bfe%d: Ethernet address: %6D\n", unit, sc->arpcom.ac_enaddr, ":"); 386 387 /* Reset the chip and turn on the PHY */ 388 bfe_chip_reset(sc); 389 390 if (mii_phy_probe(dev, &sc->bfe_miibus, 391 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 392 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 393 error = ENXIO; 394 goto fail; 395 } 396 397 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 398 callout_handle_init(&sc->bfe_stat_ch); 399 400 /* 401 * Hook interrupt last to avoid having to lock softc 402 */ 403 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 404 bfe_intr, sc, &sc->bfe_intrhand); 405 406 if (error) { 407 bfe_release_resources(sc); 408 printf("bfe%d: couldn't set up irq\n", unit); 409 goto fail; 410 } 411 fail: 412 if(error) 413 bfe_release_resources(sc); 414 return(error); 415 } 416 417 static int 418 bfe_detach(device_t dev) 419 { 420 struct bfe_softc *sc; 421 struct ifnet *ifp; 422 423 sc = device_get_softc(dev); 424 425 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 426 BFE_LOCK(scp); 427 428 ifp = &sc->arpcom.ac_if; 429 430 if (device_is_attached(dev)) { 431 bfe_stop(sc); 432 ether_ifdetach(ifp); 433 } 434 435 bfe_chip_reset(sc); 436 437 bus_generic_detach(dev); 438 if(sc->bfe_miibus != NULL) 439 device_delete_child(dev, sc->bfe_miibus); 440 441 bfe_release_resources(sc); 442 BFE_UNLOCK(sc); 443 mtx_destroy(&sc->bfe_mtx); 444 445 return(0); 446 } 447 448 /* 449 * Stop all chip I/O so that the kernel's probe routines don't 450 * get confused by errant DMAs when rebooting. 451 */ 452 static void 453 bfe_shutdown(device_t dev) 454 { 455 struct bfe_softc *sc; 456 457 sc = device_get_softc(dev); 458 BFE_LOCK(sc); 459 bfe_stop(sc); 460 461 BFE_UNLOCK(sc); 462 return; 463 } 464 465 static int 466 bfe_miibus_readreg(device_t dev, int phy, int reg) 467 { 468 struct bfe_softc *sc; 469 u_int32_t ret; 470 471 sc = device_get_softc(dev); 472 if(phy != sc->bfe_phyaddr) 473 return(0); 474 bfe_readphy(sc, reg, &ret); 475 476 return(ret); 477 } 478 479 static int 480 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 481 { 482 struct bfe_softc *sc; 483 484 sc = device_get_softc(dev); 485 if(phy != sc->bfe_phyaddr) 486 return(0); 487 bfe_writephy(sc, reg, val); 488 489 return(0); 490 } 491 492 static void 493 bfe_miibus_statchg(device_t dev) 494 { 495 return; 496 } 497 498 static void 499 bfe_tx_ring_free(struct bfe_softc *sc) 500 { 501 int i; 502 503 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 504 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 505 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 506 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 507 bus_dmamap_unload(sc->bfe_tag, 508 sc->bfe_tx_ring[i].bfe_map); 509 bus_dmamap_destroy(sc->bfe_tag, 510 sc->bfe_tx_ring[i].bfe_map); 511 } 512 } 513 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 514 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 515 } 516 517 static void 518 bfe_rx_ring_free(struct bfe_softc *sc) 519 { 520 int i; 521 522 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 523 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 524 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 525 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 526 bus_dmamap_unload(sc->bfe_tag, 527 sc->bfe_rx_ring[i].bfe_map); 528 bus_dmamap_destroy(sc->bfe_tag, 529 sc->bfe_rx_ring[i].bfe_map); 530 } 531 } 532 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 533 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 534 } 535 536 537 static int 538 bfe_list_rx_init(struct bfe_softc *sc) 539 { 540 int i; 541 542 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 543 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 544 return ENOBUFS; 545 } 546 547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 548 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 549 550 sc->bfe_rx_cons = 0; 551 552 return(0); 553 } 554 555 static int 556 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 557 { 558 struct bfe_rxheader *rx_header; 559 struct bfe_desc *d; 560 struct bfe_data *r; 561 u_int32_t ctrl; 562 563 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 564 return(EINVAL); 565 566 if(m == NULL) { 567 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 568 if(m == NULL) 569 return(ENOBUFS); 570 m->m_len = m->m_pkthdr.len = MCLBYTES; 571 } 572 else 573 m->m_data = m->m_ext.ext_buf; 574 575 rx_header = mtod(m, struct bfe_rxheader *); 576 rx_header->len = 0; 577 rx_header->flags = 0; 578 579 /* Map the mbuf into DMA */ 580 sc->bfe_rx_cnt = c; 581 d = &sc->bfe_rx_list[c]; 582 r = &sc->bfe_rx_ring[c]; 583 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 584 MCLBYTES, bfe_dma_map_desc, d, 0); 585 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 586 587 ctrl = ETHER_MAX_LEN + 32; 588 589 if(c == BFE_RX_LIST_CNT - 1) 590 ctrl |= BFE_DESC_EOT; 591 592 d->bfe_ctrl = ctrl; 593 r->bfe_mbuf = m; 594 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 595 return(0); 596 } 597 598 static void 599 bfe_get_config(struct bfe_softc *sc) 600 { 601 u_int8_t eeprom[128]; 602 603 bfe_read_eeprom(sc, eeprom); 604 605 sc->arpcom.ac_enaddr[0] = eeprom[79]; 606 sc->arpcom.ac_enaddr[1] = eeprom[78]; 607 sc->arpcom.ac_enaddr[2] = eeprom[81]; 608 sc->arpcom.ac_enaddr[3] = eeprom[80]; 609 sc->arpcom.ac_enaddr[4] = eeprom[83]; 610 sc->arpcom.ac_enaddr[5] = eeprom[82]; 611 612 sc->bfe_phyaddr = eeprom[90] & 0x1f; 613 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 614 615 sc->bfe_core_unit = 0; 616 sc->bfe_dma_offset = BFE_PCI_DMA; 617 } 618 619 static void 620 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 621 { 622 u_int32_t bar_orig, pci_rev, val; 623 624 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 625 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 626 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 627 628 val = CSR_READ_4(sc, BFE_SBINTVEC); 629 val |= cores; 630 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 631 632 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 633 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 634 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 635 636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 637 } 638 639 static void 640 bfe_clear_stats(struct bfe_softc *sc) 641 { 642 u_long reg; 643 644 BFE_LOCK(sc); 645 646 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 647 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 648 CSR_READ_4(sc, reg); 649 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 650 CSR_READ_4(sc, reg); 651 652 BFE_UNLOCK(sc); 653 } 654 655 static int 656 bfe_resetphy(struct bfe_softc *sc) 657 { 658 u_int32_t val; 659 660 BFE_LOCK(sc); 661 bfe_writephy(sc, 0, BMCR_RESET); 662 DELAY(100); 663 bfe_readphy(sc, 0, &val); 664 if (val & BMCR_RESET) { 665 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 666 BFE_UNLOCK(sc); 667 return ENXIO; 668 } 669 BFE_UNLOCK(sc); 670 return 0; 671 } 672 673 static void 674 bfe_chip_halt(struct bfe_softc *sc) 675 { 676 BFE_LOCK(sc); 677 /* disable interrupts - not that it actually does..*/ 678 CSR_WRITE_4(sc, BFE_IMASK, 0); 679 CSR_READ_4(sc, BFE_IMASK); 680 681 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 682 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 683 684 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 685 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 686 DELAY(10); 687 688 BFE_UNLOCK(sc); 689 } 690 691 static void 692 bfe_chip_reset(struct bfe_softc *sc) 693 { 694 u_int32_t val; 695 696 BFE_LOCK(sc); 697 698 /* Set the interrupt vector for the enet core */ 699 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 700 701 /* is core up? */ 702 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 703 if (val == BFE_CLOCK) { 704 /* It is, so shut it down */ 705 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 709 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 710 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 711 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 713 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 714 } 715 716 bfe_core_reset(sc); 717 bfe_clear_stats(sc); 718 719 /* 720 * We want the phy registers to be accessible even when 721 * the driver is "downed" so initialize MDC preamble, frequency, 722 * and whether internal or external phy here. 723 */ 724 725 /* 4402 has 62.5Mhz SB clock and internal phy */ 726 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 727 728 /* Internal or external PHY? */ 729 val = CSR_READ_4(sc, BFE_DEVCTRL); 730 if(!(val & BFE_IPP)) 731 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 732 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 733 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 734 DELAY(100); 735 } 736 737 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 738 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 739 BFE_LAZY_FC_MASK)); 740 741 /* 742 * We don't want lazy interrupts, so just send them at the end of a frame, 743 * please 744 */ 745 BFE_OR(sc, BFE_RCV_LAZY, 0); 746 747 /* Set max lengths, accounting for VLAN tags */ 748 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 749 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 750 751 /* Set watermark XXX - magic */ 752 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 753 754 /* 755 * Initialise DMA channels - not forgetting dma addresses need to be added 756 * to BFE_PCI_DMA 757 */ 758 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 759 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 760 761 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 762 BFE_RX_CTRL_ENABLE); 763 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 764 765 bfe_resetphy(sc); 766 bfe_setupphy(sc); 767 768 BFE_UNLOCK(sc); 769 } 770 771 static void 772 bfe_core_disable(struct bfe_softc *sc) 773 { 774 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 775 return; 776 777 /* 778 * Set reject, wait for it set, then wait for the core to stop being busy 779 * Then set reset and reject and enable the clocks 780 */ 781 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 782 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 783 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 785 BFE_RESET)); 786 CSR_READ_4(sc, BFE_SBTMSLOW); 787 DELAY(10); 788 /* Leave reset and reject set */ 789 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 790 DELAY(10); 791 } 792 793 static void 794 bfe_core_reset(struct bfe_softc *sc) 795 { 796 u_int32_t val; 797 798 /* Disable the core */ 799 bfe_core_disable(sc); 800 801 /* and bring it back up */ 802 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 803 CSR_READ_4(sc, BFE_SBTMSLOW); 804 DELAY(10); 805 806 /* Chip bug, clear SERR, IB and TO if they are set. */ 807 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 808 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 809 val = CSR_READ_4(sc, BFE_SBIMSTATE); 810 if (val & (BFE_IBE | BFE_TO)) 811 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 812 813 /* Clear reset and allow it to move through the core */ 814 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 815 CSR_READ_4(sc, BFE_SBTMSLOW); 816 DELAY(10); 817 818 /* Leave the clock set */ 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 820 CSR_READ_4(sc, BFE_SBTMSLOW); 821 DELAY(10); 822 } 823 824 static void 825 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 826 { 827 u_int32_t val; 828 829 val = ((u_int32_t) data[2]) << 24; 830 val |= ((u_int32_t) data[3]) << 16; 831 val |= ((u_int32_t) data[4]) << 8; 832 val |= ((u_int32_t) data[5]); 833 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 834 val = (BFE_CAM_HI_VALID | 835 (((u_int32_t) data[0]) << 8) | 836 (((u_int32_t) data[1]))); 837 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 838 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 839 (index << BFE_CAM_INDEX_SHIFT))); 840 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 841 } 842 843 static void 844 bfe_set_rx_mode(struct bfe_softc *sc) 845 { 846 struct ifnet *ifp = &sc->arpcom.ac_if; 847 struct ifmultiaddr *ifma; 848 u_int32_t val; 849 int i = 0; 850 851 val = CSR_READ_4(sc, BFE_RXCONF); 852 853 if (ifp->if_flags & IFF_PROMISC) 854 val |= BFE_RXCONF_PROMISC; 855 else 856 val &= ~BFE_RXCONF_PROMISC; 857 858 if (ifp->if_flags & IFF_BROADCAST) 859 val &= ~BFE_RXCONF_DBCAST; 860 else 861 val |= BFE_RXCONF_DBCAST; 862 863 864 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 865 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 866 867 if (ifp->if_flags & IFF_ALLMULTI) 868 val |= BFE_RXCONF_ALLMULTI; 869 else { 870 val &= ~BFE_RXCONF_ALLMULTI; 871 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 872 if (ifma->ifma_addr->sa_family != AF_LINK) 873 continue; 874 bfe_cam_write(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 875 i++); 876 } 877 } 878 879 CSR_WRITE_4(sc, BFE_RXCONF, val); 880 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 881 } 882 883 static void 884 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 885 { 886 u_int32_t *ptr; 887 888 ptr = arg; 889 *ptr = segs->ds_addr; 890 } 891 892 static void 893 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 894 { 895 struct bfe_desc *d; 896 897 d = arg; 898 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 899 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 900 } 901 902 static void 903 bfe_release_resources(struct bfe_softc *sc) 904 { 905 device_t dev; 906 int i; 907 908 dev = sc->bfe_dev; 909 910 if (sc->bfe_vpd_prodname != NULL) 911 free(sc->bfe_vpd_prodname, M_DEVBUF); 912 913 if (sc->bfe_vpd_readonly != NULL) 914 free(sc->bfe_vpd_readonly, M_DEVBUF); 915 916 if (sc->bfe_intrhand != NULL) 917 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 918 919 if (sc->bfe_irq != NULL) 920 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 921 922 if (sc->bfe_res != NULL) 923 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 924 925 if(sc->bfe_tx_tag != NULL) { 926 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 927 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map); 928 bus_dma_tag_destroy(sc->bfe_tx_tag); 929 sc->bfe_tx_tag = NULL; 930 } 931 932 if(sc->bfe_rx_tag != NULL) { 933 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 934 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map); 935 bus_dma_tag_destroy(sc->bfe_rx_tag); 936 sc->bfe_rx_tag = NULL; 937 } 938 939 if(sc->bfe_tag != NULL) { 940 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 941 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 942 } 943 bus_dma_tag_destroy(sc->bfe_tag); 944 sc->bfe_tag = NULL; 945 } 946 947 if(sc->bfe_parent_tag != NULL) 948 bus_dma_tag_destroy(sc->bfe_parent_tag); 949 950 return; 951 } 952 953 static void 954 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 955 { 956 long i; 957 u_int16_t *ptr = (u_int16_t *)data; 958 959 for(i = 0; i < 128; i += 2) 960 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 961 } 962 963 static int 964 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 965 u_long timeout, const int clear) 966 { 967 u_long i; 968 969 for (i = 0; i < timeout; i++) { 970 u_int32_t val = CSR_READ_4(sc, reg); 971 972 if (clear && !(val & bit)) 973 break; 974 if (!clear && (val & bit)) 975 break; 976 DELAY(10); 977 } 978 if (i == timeout) { 979 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 980 "%x to %s.\n", sc->bfe_unit, bit, reg, 981 (clear ? "clear" : "set")); 982 return -1; 983 } 984 return 0; 985 } 986 987 static int 988 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 989 { 990 int err; 991 992 BFE_LOCK(sc); 993 /* Clear MII ISR */ 994 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 995 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 996 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 997 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 998 (reg << BFE_MDIO_RA_SHIFT) | 999 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1000 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1001 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1002 1003 BFE_UNLOCK(sc); 1004 return err; 1005 } 1006 1007 static int 1008 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1009 { 1010 int status; 1011 1012 BFE_LOCK(sc); 1013 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1014 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1015 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1016 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1017 (reg << BFE_MDIO_RA_SHIFT) | 1018 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1019 (val & BFE_MDIO_DATA_DATA))); 1020 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1021 BFE_UNLOCK(sc); 1022 1023 return status; 1024 } 1025 1026 /* 1027 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1028 * twice 1029 */ 1030 static int 1031 bfe_setupphy(struct bfe_softc *sc) 1032 { 1033 u_int32_t val; 1034 BFE_LOCK(sc); 1035 1036 /* Enable activity LED */ 1037 bfe_readphy(sc, 26, &val); 1038 bfe_writephy(sc, 26, val & 0x7fff); 1039 bfe_readphy(sc, 26, &val); 1040 1041 /* Enable traffic meter LED mode */ 1042 bfe_readphy(sc, 27, &val); 1043 bfe_writephy(sc, 27, val | (1 << 6)); 1044 1045 BFE_UNLOCK(sc); 1046 return 0; 1047 } 1048 1049 static void 1050 bfe_stats_update(struct bfe_softc *sc) 1051 { 1052 u_long reg; 1053 u_int32_t *val; 1054 1055 val = &sc->bfe_hwstats.tx_good_octets; 1056 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1057 *val++ += CSR_READ_4(sc, reg); 1058 } 1059 val = &sc->bfe_hwstats.rx_good_octets; 1060 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1061 *val++ += CSR_READ_4(sc, reg); 1062 } 1063 } 1064 1065 static void 1066 bfe_txeof(struct bfe_softc *sc) 1067 { 1068 struct ifnet *ifp; 1069 int i, chipidx; 1070 1071 BFE_LOCK(sc); 1072 1073 ifp = &sc->arpcom.ac_if; 1074 1075 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1076 chipidx /= sizeof(struct bfe_desc); 1077 1078 i = sc->bfe_tx_cons; 1079 /* Go through the mbufs and free those that have been transmitted */ 1080 while(i != chipidx) { 1081 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1082 if(r->bfe_mbuf != NULL) { 1083 ifp->if_opackets++; 1084 m_freem(r->bfe_mbuf); 1085 r->bfe_mbuf = NULL; 1086 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1087 } 1088 sc->bfe_tx_cnt--; 1089 BFE_INC(i, BFE_TX_LIST_CNT); 1090 } 1091 1092 if(i != sc->bfe_tx_cons) { 1093 /* we freed up some mbufs */ 1094 sc->bfe_tx_cons = i; 1095 ifp->if_flags &= ~IFF_OACTIVE; 1096 } 1097 if(sc->bfe_tx_cnt == 0) 1098 ifp->if_timer = 0; 1099 else 1100 ifp->if_timer = 5; 1101 1102 BFE_UNLOCK(sc); 1103 } 1104 1105 /* Pass a received packet up the stack */ 1106 static void 1107 bfe_rxeof(struct bfe_softc *sc) 1108 { 1109 struct mbuf *m; 1110 struct ifnet *ifp; 1111 struct bfe_rxheader *rxheader; 1112 struct bfe_data *r; 1113 int cons; 1114 u_int32_t status, current, len, flags; 1115 1116 BFE_LOCK(sc); 1117 cons = sc->bfe_rx_cons; 1118 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1119 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1120 1121 ifp = &sc->arpcom.ac_if; 1122 1123 while(current != cons) { 1124 r = &sc->bfe_rx_ring[cons]; 1125 m = r->bfe_mbuf; 1126 rxheader = mtod(m, struct bfe_rxheader*); 1127 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1128 len = rxheader->len; 1129 r->bfe_mbuf = NULL; 1130 1131 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1132 flags = rxheader->flags; 1133 1134 len -= ETHER_CRC_LEN; 1135 1136 /* flag an error and try again */ 1137 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1138 ifp->if_ierrors++; 1139 if (flags & BFE_RX_FLAG_SERR) 1140 ifp->if_collisions++; 1141 bfe_list_newbuf(sc, cons, m); 1142 continue; 1143 } 1144 1145 /* Go past the rx header */ 1146 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1147 m_adj(m, BFE_RX_OFFSET); 1148 m->m_len = m->m_pkthdr.len = len; 1149 } else { 1150 bfe_list_newbuf(sc, cons, m); 1151 ifp->if_ierrors++; 1152 continue; 1153 } 1154 1155 ifp->if_ipackets++; 1156 m->m_pkthdr.rcvif = ifp; 1157 (*ifp->if_input)(ifp, m); 1158 1159 BFE_INC(cons, BFE_RX_LIST_CNT); 1160 } 1161 sc->bfe_rx_cons = cons; 1162 BFE_UNLOCK(sc); 1163 } 1164 1165 static void 1166 bfe_intr(void *xsc) 1167 { 1168 struct bfe_softc *sc = xsc; 1169 struct ifnet *ifp; 1170 u_int32_t istat, imask, flag; 1171 1172 ifp = &sc->arpcom.ac_if; 1173 1174 BFE_LOCK(sc); 1175 1176 istat = CSR_READ_4(sc, BFE_ISTAT); 1177 imask = CSR_READ_4(sc, BFE_IMASK); 1178 1179 /* 1180 * Defer unsolicited interrupts - This is necessary because setting the 1181 * chips interrupt mask register to 0 doesn't actually stop the 1182 * interrupts 1183 */ 1184 istat &= imask; 1185 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1186 CSR_READ_4(sc, BFE_ISTAT); 1187 1188 /* not expecting this interrupt, disregard it */ 1189 if(istat == 0) { 1190 BFE_UNLOCK(sc); 1191 return; 1192 } 1193 1194 if(istat & BFE_ISTAT_ERRORS) { 1195 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1196 if(flag & BFE_STAT_EMASK) 1197 ifp->if_oerrors++; 1198 1199 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1200 if(flag & BFE_RX_FLAG_ERRORS) 1201 ifp->if_ierrors++; 1202 1203 ifp->if_flags &= ~IFF_RUNNING; 1204 bfe_init(sc); 1205 } 1206 1207 /* A packet was received */ 1208 if(istat & BFE_ISTAT_RX) 1209 bfe_rxeof(sc); 1210 1211 /* A packet was sent */ 1212 if(istat & BFE_ISTAT_TX) 1213 bfe_txeof(sc); 1214 1215 /* We have packets pending, fire them out */ 1216 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1217 bfe_start(ifp); 1218 1219 BFE_UNLOCK(sc); 1220 } 1221 1222 static int 1223 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1224 { 1225 struct bfe_desc *d = NULL; 1226 struct bfe_data *r = NULL; 1227 struct mbuf *m; 1228 u_int32_t frag, cur, cnt = 0; 1229 int chainlen = 0; 1230 1231 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1232 return(ENOBUFS); 1233 1234 /* 1235 * Count the number of frags in this chain to see if 1236 * we need to m_defrag. Since the descriptor list is shared 1237 * by all packets, we'll m_defrag long chains so that they 1238 * do not use up the entire list, even if they would fit. 1239 */ 1240 for(m = m_head; m != NULL; m = m->m_next) 1241 chainlen++; 1242 1243 1244 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1245 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1246 m = m_defrag(m_head, M_DONTWAIT); 1247 if (m == NULL) 1248 return(ENOBUFS); 1249 m_head = m; 1250 } 1251 1252 /* 1253 * Start packing the mbufs in this chain into 1254 * the fragment pointers. Stop when we run out 1255 * of fragments or hit the end of the mbuf chain. 1256 */ 1257 m = m_head; 1258 cur = frag = *txidx; 1259 cnt = 0; 1260 1261 for(m = m_head; m != NULL; m = m->m_next) { 1262 if(m->m_len != 0) { 1263 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1264 return(ENOBUFS); 1265 1266 d = &sc->bfe_tx_list[cur]; 1267 r = &sc->bfe_tx_ring[cur]; 1268 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1269 /* always intterupt on completion */ 1270 d->bfe_ctrl |= BFE_DESC_IOC; 1271 if(cnt == 0) 1272 /* Set start of frame */ 1273 d->bfe_ctrl |= BFE_DESC_SOF; 1274 if(cur == BFE_TX_LIST_CNT - 1) 1275 /* Tell the chip to wrap to the start of the descriptor list */ 1276 d->bfe_ctrl |= BFE_DESC_EOT; 1277 1278 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), m->m_len, 1279 bfe_dma_map_desc, d, 0); 1280 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 1281 1282 frag = cur; 1283 BFE_INC(cur, BFE_TX_LIST_CNT); 1284 cnt++; 1285 } 1286 } 1287 1288 if (m != NULL) 1289 return(ENOBUFS); 1290 1291 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1292 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1293 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1294 1295 *txidx = cur; 1296 sc->bfe_tx_cnt += cnt; 1297 return (0); 1298 } 1299 1300 /* 1301 * Set up to transmit a packet 1302 */ 1303 static void 1304 bfe_start(struct ifnet *ifp) 1305 { 1306 struct bfe_softc *sc; 1307 struct mbuf *m_head = NULL; 1308 int idx; 1309 1310 sc = ifp->if_softc; 1311 idx = sc->bfe_tx_prod; 1312 1313 BFE_LOCK(sc); 1314 1315 /* 1316 * not much point trying to send if the link is down or we have nothing to 1317 * send 1318 */ 1319 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1320 BFE_UNLOCK(sc); 1321 return; 1322 } 1323 1324 if (ifp->if_flags & IFF_OACTIVE) { 1325 BFE_UNLOCK(sc); 1326 return; 1327 } 1328 1329 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1330 IF_DEQUEUE(&ifp->if_snd, m_head); 1331 if(m_head == NULL) 1332 break; 1333 1334 /* 1335 * Pack the data into the tx ring. If we dont have enough room, let 1336 * the chip drain the ring 1337 */ 1338 if(bfe_encap(sc, m_head, &idx)) { 1339 IF_PREPEND(&ifp->if_snd, m_head); 1340 ifp->if_flags |= IFF_OACTIVE; 1341 break; 1342 } 1343 1344 /* 1345 * If there's a BPF listener, bounce a copy of this frame 1346 * to him. 1347 */ 1348 BPF_MTAP(ifp, m_head); 1349 } 1350 1351 sc->bfe_tx_prod = idx; 1352 /* Transmit - twice due to apparent hardware bug */ 1353 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1355 1356 /* 1357 * Set a timeout in case the chip goes out to lunch. 1358 */ 1359 ifp->if_timer = 5; 1360 BFE_UNLOCK(sc); 1361 } 1362 1363 static void 1364 bfe_init(void *xsc) 1365 { 1366 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1367 struct ifnet *ifp = &sc->arpcom.ac_if; 1368 1369 BFE_LOCK(sc); 1370 1371 if (ifp->if_flags & IFF_RUNNING) { 1372 BFE_UNLOCK(sc); 1373 return; 1374 } 1375 1376 bfe_stop(sc); 1377 bfe_chip_reset(sc); 1378 1379 if (bfe_list_rx_init(sc) == ENOBUFS) { 1380 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n", 1381 sc->bfe_unit); 1382 bfe_stop(sc); 1383 return; 1384 } 1385 1386 bfe_set_rx_mode(sc); 1387 1388 /* Enable the chip and core */ 1389 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1390 /* Enable interrupts */ 1391 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1392 1393 bfe_ifmedia_upd(ifp); 1394 ifp->if_flags |= IFF_RUNNING; 1395 ifp->if_flags &= ~IFF_OACTIVE; 1396 1397 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1398 BFE_UNLOCK(sc); 1399 } 1400 1401 /* 1402 * Set media options. 1403 */ 1404 static int 1405 bfe_ifmedia_upd(struct ifnet *ifp) 1406 { 1407 struct bfe_softc *sc; 1408 struct mii_data *mii; 1409 1410 sc = ifp->if_softc; 1411 1412 BFE_LOCK(sc); 1413 1414 mii = device_get_softc(sc->bfe_miibus); 1415 sc->bfe_link = 0; 1416 if (mii->mii_instance) { 1417 struct mii_softc *miisc; 1418 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1419 miisc = LIST_NEXT(miisc, mii_list)) 1420 mii_phy_reset(miisc); 1421 } 1422 mii_mediachg(mii); 1423 1424 BFE_UNLOCK(sc); 1425 return(0); 1426 } 1427 1428 /* 1429 * Report current media status. 1430 */ 1431 static void 1432 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1433 { 1434 struct bfe_softc *sc = ifp->if_softc; 1435 struct mii_data *mii; 1436 1437 BFE_LOCK(sc); 1438 1439 mii = device_get_softc(sc->bfe_miibus); 1440 mii_pollstat(mii); 1441 ifmr->ifm_active = mii->mii_media_active; 1442 ifmr->ifm_status = mii->mii_media_status; 1443 1444 BFE_UNLOCK(sc); 1445 } 1446 1447 static int 1448 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1449 { 1450 struct bfe_softc *sc = ifp->if_softc; 1451 struct ifreq *ifr = (struct ifreq *) data; 1452 struct mii_data *mii; 1453 int error = 0; 1454 1455 BFE_LOCK(sc); 1456 1457 switch(command) { 1458 case SIOCSIFFLAGS: 1459 if(ifp->if_flags & IFF_UP) 1460 if(ifp->if_flags & IFF_RUNNING) 1461 bfe_set_rx_mode(sc); 1462 else 1463 bfe_init(sc); 1464 else if(ifp->if_flags & IFF_RUNNING) 1465 bfe_stop(sc); 1466 break; 1467 case SIOCADDMULTI: 1468 case SIOCDELMULTI: 1469 if(ifp->if_flags & IFF_RUNNING) 1470 bfe_set_rx_mode(sc); 1471 break; 1472 case SIOCGIFMEDIA: 1473 case SIOCSIFMEDIA: 1474 mii = device_get_softc(sc->bfe_miibus); 1475 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1476 break; 1477 default: 1478 error = ether_ioctl(ifp, command, data); 1479 break; 1480 } 1481 1482 BFE_UNLOCK(sc); 1483 return error; 1484 } 1485 1486 static void 1487 bfe_watchdog(struct ifnet *ifp) 1488 { 1489 struct bfe_softc *sc; 1490 1491 sc = ifp->if_softc; 1492 1493 BFE_LOCK(sc); 1494 1495 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1496 1497 ifp->if_flags &= ~IFF_RUNNING; 1498 bfe_init(sc); 1499 1500 ifp->if_oerrors++; 1501 1502 BFE_UNLOCK(sc); 1503 } 1504 1505 static void 1506 bfe_tick(void *xsc) 1507 { 1508 struct bfe_softc *sc = xsc; 1509 struct mii_data *mii; 1510 1511 if (sc == NULL) 1512 return; 1513 1514 BFE_LOCK(sc); 1515 1516 mii = device_get_softc(sc->bfe_miibus); 1517 1518 bfe_stats_update(sc); 1519 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1520 1521 if(sc->bfe_link) { 1522 BFE_UNLOCK(sc); 1523 return; 1524 } 1525 1526 mii_tick(mii); 1527 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1528 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1529 sc->bfe_link++; 1530 1531 BFE_UNLOCK(sc); 1532 } 1533 1534 /* 1535 * Stop the adapter and free any mbufs allocated to the 1536 * RX and TX lists. 1537 */ 1538 static void 1539 bfe_stop(struct bfe_softc *sc) 1540 { 1541 struct ifnet *ifp; 1542 1543 BFE_LOCK(sc); 1544 1545 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1546 1547 ifp = &sc->arpcom.ac_if; 1548 1549 bfe_chip_halt(sc); 1550 bfe_tx_ring_free(sc); 1551 bfe_rx_ring_free(sc); 1552 1553 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1554 1555 BFE_UNLOCK(sc); 1556 } 1557