xref: /freebsd/sys/dev/bfe/if_bfe.c (revision 681ce946f33e75c590e97c53076e86dff1fe8f4a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
5  * and Duncan Barclay<dmlb@dmlb.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
44 
45 #include <net/bpf.h>
46 #include <net/if.h>
47 #include <net/if_var.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52 #include <net/if_vlan_var.h>
53 
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56 
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcivar.h>
59 
60 #include <machine/bus.h>
61 
62 #include <dev/bfe/if_bfereg.h>
63 
64 MODULE_DEPEND(bfe, pci, 1, 1, 1);
65 MODULE_DEPEND(bfe, ether, 1, 1, 1);
66 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
67 
68 /* "device miibus" required.  See GENERIC if you get errors here. */
69 #include "miibus_if.h"
70 
71 #define BFE_DEVDESC_MAX		64	/* Maximum device description length */
72 
73 static struct bfe_type bfe_devs[] = {
74 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
75 		"Broadcom BCM4401 Fast Ethernet" },
76 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
77 		"Broadcom BCM4401-B0 Fast Ethernet" },
78 		{ 0, 0, NULL }
79 };
80 
81 static int  bfe_probe				(device_t);
82 static int  bfe_attach				(device_t);
83 static int  bfe_detach				(device_t);
84 static int  bfe_suspend				(device_t);
85 static int  bfe_resume				(device_t);
86 static void bfe_release_resources	(struct bfe_softc *);
87 static void bfe_intr				(void *);
88 static int  bfe_encap				(struct bfe_softc *, struct mbuf **);
89 static void bfe_start				(struct ifnet *);
90 static void bfe_start_locked			(struct ifnet *);
91 static int  bfe_ioctl				(struct ifnet *, u_long, caddr_t);
92 static void bfe_init				(void *);
93 static void bfe_init_locked			(void *);
94 static void bfe_stop				(struct bfe_softc *);
95 static void bfe_watchdog			(struct bfe_softc *);
96 static int  bfe_shutdown			(device_t);
97 static void bfe_tick				(void *);
98 static void bfe_txeof				(struct bfe_softc *);
99 static void bfe_rxeof				(struct bfe_softc *);
100 static void bfe_set_rx_mode			(struct bfe_softc *);
101 static int  bfe_list_rx_init		(struct bfe_softc *);
102 static void bfe_list_tx_init		(struct bfe_softc *);
103 static void bfe_discard_buf		(struct bfe_softc *, int);
104 static int  bfe_list_newbuf			(struct bfe_softc *, int);
105 static void bfe_rx_ring_free		(struct bfe_softc *);
106 
107 static void bfe_pci_setup			(struct bfe_softc *, u_int32_t);
108 static int  bfe_ifmedia_upd			(struct ifnet *);
109 static void bfe_ifmedia_sts			(struct ifnet *, struct ifmediareq *);
110 static int  bfe_miibus_readreg		(device_t, int, int);
111 static int  bfe_miibus_writereg		(device_t, int, int, int);
112 static void bfe_miibus_statchg		(device_t);
113 static int  bfe_wait_bit			(struct bfe_softc *, u_int32_t, u_int32_t,
114 		u_long, const int);
115 static void bfe_get_config			(struct bfe_softc *sc);
116 static void bfe_read_eeprom			(struct bfe_softc *, u_int8_t *);
117 static void bfe_stats_update		(struct bfe_softc *);
118 static void bfe_clear_stats			(struct bfe_softc *);
119 static int  bfe_readphy				(struct bfe_softc *, u_int32_t, u_int32_t*);
120 static int  bfe_writephy			(struct bfe_softc *, u_int32_t, u_int32_t);
121 static int  bfe_resetphy			(struct bfe_softc *);
122 static int  bfe_setupphy			(struct bfe_softc *);
123 static void bfe_chip_reset			(struct bfe_softc *);
124 static void bfe_chip_halt			(struct bfe_softc *);
125 static void bfe_core_reset			(struct bfe_softc *);
126 static void bfe_core_disable		(struct bfe_softc *);
127 static int  bfe_dma_alloc			(struct bfe_softc *);
128 static void bfe_dma_free		(struct bfe_softc *sc);
129 static void bfe_dma_map				(void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write			(struct bfe_softc *, u_char *, int);
131 static int  sysctl_bfe_stats		(SYSCTL_HANDLER_ARGS);
132 
133 static device_method_t bfe_methods[] = {
134 	/* Device interface */
135 	DEVMETHOD(device_probe,		bfe_probe),
136 	DEVMETHOD(device_attach,	bfe_attach),
137 	DEVMETHOD(device_detach,	bfe_detach),
138 	DEVMETHOD(device_shutdown,	bfe_shutdown),
139 	DEVMETHOD(device_suspend,	bfe_suspend),
140 	DEVMETHOD(device_resume,	bfe_resume),
141 
142 	/* MII interface */
143 	DEVMETHOD(miibus_readreg,	bfe_miibus_readreg),
144 	DEVMETHOD(miibus_writereg,	bfe_miibus_writereg),
145 	DEVMETHOD(miibus_statchg,	bfe_miibus_statchg),
146 
147 	DEVMETHOD_END
148 };
149 
150 static driver_t bfe_driver = {
151 	"bfe",
152 	bfe_methods,
153 	sizeof(struct bfe_softc)
154 };
155 
156 static devclass_t bfe_devclass;
157 
158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
159 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
160     nitems(bfe_devs) - 1);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
162 
163 /*
164  * Probe for a Broadcom 4401 chip.
165  */
166 static int
167 bfe_probe(device_t dev)
168 {
169 	struct bfe_type *t;
170 
171 	t = bfe_devs;
172 
173 	while (t->bfe_name != NULL) {
174 		if (pci_get_vendor(dev) == t->bfe_vid &&
175 		    pci_get_device(dev) == t->bfe_did) {
176 			device_set_desc(dev, t->bfe_name);
177 			return (BUS_PROBE_DEFAULT);
178 		}
179 		t++;
180 	}
181 
182 	return (ENXIO);
183 }
184 
185 struct bfe_dmamap_arg {
186 	bus_addr_t	bfe_busaddr;
187 };
188 
189 static int
190 bfe_dma_alloc(struct bfe_softc *sc)
191 {
192 	struct bfe_dmamap_arg ctx;
193 	struct bfe_rx_data *rd;
194 	struct bfe_tx_data *td;
195 	int error, i;
196 
197 	/*
198 	 * parent tag.  Apparently the chip cannot handle any DMA address
199 	 * greater than 1GB.
200 	 */
201 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
202 	    1, 0,			/* alignment, boundary */
203 	    BFE_DMA_MAXADDR, 		/* lowaddr */
204 	    BUS_SPACE_MAXADDR,		/* highaddr */
205 	    NULL, NULL,			/* filter, filterarg */
206 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
207 	    0,				/* nsegments */
208 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
209 	    0,				/* flags */
210 	    NULL, NULL,			/* lockfunc, lockarg */
211 	    &sc->bfe_parent_tag);
212 	if (error != 0) {
213 		device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
214 		goto fail;
215 	}
216 
217 	/* Create tag for Tx ring. */
218 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
219 	    BFE_TX_RING_ALIGN, 0,	/* alignment, boundary */
220 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
221 	    BUS_SPACE_MAXADDR,		/* highaddr */
222 	    NULL, NULL,			/* filter, filterarg */
223 	    BFE_TX_LIST_SIZE,		/* maxsize */
224 	    1,				/* nsegments */
225 	    BFE_TX_LIST_SIZE,		/* maxsegsize */
226 	    0,				/* flags */
227 	    NULL, NULL,			/* lockfunc, lockarg */
228 	    &sc->bfe_tx_tag);
229 	if (error != 0) {
230 		device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
231 		goto fail;
232 	}
233 
234 	/* Create tag for Rx ring. */
235 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
236 	    BFE_RX_RING_ALIGN, 0,	/* alignment, boundary */
237 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
238 	    BUS_SPACE_MAXADDR,		/* highaddr */
239 	    NULL, NULL,			/* filter, filterarg */
240 	    BFE_RX_LIST_SIZE,		/* maxsize */
241 	    1,				/* nsegments */
242 	    BFE_RX_LIST_SIZE,		/* maxsegsize */
243 	    0,				/* flags */
244 	    NULL, NULL,			/* lockfunc, lockarg */
245 	    &sc->bfe_rx_tag);
246 	if (error != 0) {
247 		device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
248 		goto fail;
249 	}
250 
251 	/* Create tag for Tx buffers. */
252 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
253 	    1, 0,			/* alignment, boundary */
254 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
255 	    BUS_SPACE_MAXADDR,		/* highaddr */
256 	    NULL, NULL,			/* filter, filterarg */
257 	    MCLBYTES * BFE_MAXTXSEGS,	/* maxsize */
258 	    BFE_MAXTXSEGS,		/* nsegments */
259 	    MCLBYTES,			/* maxsegsize */
260 	    0,				/* flags */
261 	    NULL, NULL,			/* lockfunc, lockarg */
262 	    &sc->bfe_txmbuf_tag);
263 	if (error != 0) {
264 		device_printf(sc->bfe_dev,
265 		    "cannot create Tx buffer DMA tag.\n");
266 		goto fail;
267 	}
268 
269 	/* Create tag for Rx buffers. */
270 	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
271 	    1, 0,			/* alignment, boundary */
272 	    BUS_SPACE_MAXADDR, 		/* lowaddr */
273 	    BUS_SPACE_MAXADDR,		/* highaddr */
274 	    NULL, NULL,			/* filter, filterarg */
275 	    MCLBYTES,			/* maxsize */
276 	    1,				/* nsegments */
277 	    MCLBYTES,			/* maxsegsize */
278 	    0,				/* flags */
279 	    NULL, NULL,			/* lockfunc, lockarg */
280 	    &sc->bfe_rxmbuf_tag);
281 	if (error != 0) {
282 		device_printf(sc->bfe_dev,
283 		    "cannot create Rx buffer DMA tag.\n");
284 		goto fail;
285 	}
286 
287 	/* Allocate DMA'able memory and load DMA map. */
288 	error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
289 	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
290 	if (error != 0) {
291 		device_printf(sc->bfe_dev,
292 		    "cannot allocate DMA'able memory for Tx ring.\n");
293 		goto fail;
294 	}
295 	ctx.bfe_busaddr = 0;
296 	error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
297 	    sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
298 	    BUS_DMA_NOWAIT);
299 	if (error != 0 || ctx.bfe_busaddr == 0) {
300 		device_printf(sc->bfe_dev,
301 		    "cannot load DMA'able memory for Tx ring.\n");
302 		goto fail;
303 	}
304 	sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
305 
306 	error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
307 	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
308 	if (error != 0) {
309 		device_printf(sc->bfe_dev,
310 		    "cannot allocate DMA'able memory for Rx ring.\n");
311 		goto fail;
312 	}
313 	ctx.bfe_busaddr = 0;
314 	error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
315 	    sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
316 	    BUS_DMA_NOWAIT);
317 	if (error != 0 || ctx.bfe_busaddr == 0) {
318 		device_printf(sc->bfe_dev,
319 		    "cannot load DMA'able memory for Rx ring.\n");
320 		goto fail;
321 	}
322 	sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
323 
324 	/* Create DMA maps for Tx buffers. */
325 	for (i = 0; i < BFE_TX_LIST_CNT; i++) {
326 		td = &sc->bfe_tx_ring[i];
327 		td->bfe_mbuf = NULL;
328 		td->bfe_map = NULL;
329 		error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
330 		if (error != 0) {
331 			device_printf(sc->bfe_dev,
332 			    "cannot create DMA map for Tx.\n");
333 			goto fail;
334 		}
335 	}
336 
337 	/* Create spare DMA map for Rx buffers. */
338 	error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
339 	if (error != 0) {
340 		device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
341 		goto fail;
342 	}
343 	/* Create DMA maps for Rx buffers. */
344 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
345 		rd = &sc->bfe_rx_ring[i];
346 		rd->bfe_mbuf = NULL;
347 		rd->bfe_map = NULL;
348 		rd->bfe_ctrl = 0;
349 		error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
350 		if (error != 0) {
351 			device_printf(sc->bfe_dev,
352 			    "cannot create DMA map for Rx.\n");
353 			goto fail;
354 		}
355 	}
356 
357 fail:
358 	return (error);
359 }
360 
361 static void
362 bfe_dma_free(struct bfe_softc *sc)
363 {
364 	struct bfe_tx_data *td;
365 	struct bfe_rx_data *rd;
366 	int i;
367 
368 	/* Tx ring. */
369 	if (sc->bfe_tx_tag != NULL) {
370 		if (sc->bfe_tx_dma != 0)
371 			bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
372 		if (sc->bfe_tx_list != NULL)
373 			bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
374 			    sc->bfe_tx_map);
375 		sc->bfe_tx_dma = 0;
376 		sc->bfe_tx_list = NULL;
377 		bus_dma_tag_destroy(sc->bfe_tx_tag);
378 		sc->bfe_tx_tag = NULL;
379 	}
380 
381 	/* Rx ring. */
382 	if (sc->bfe_rx_tag != NULL) {
383 		if (sc->bfe_rx_dma != 0)
384 			bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
385 		if (sc->bfe_rx_list != NULL)
386 			bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
387 			    sc->bfe_rx_map);
388 		sc->bfe_rx_dma = 0;
389 		sc->bfe_rx_list = NULL;
390 		bus_dma_tag_destroy(sc->bfe_rx_tag);
391 		sc->bfe_rx_tag = NULL;
392 	}
393 
394 	/* Tx buffers. */
395 	if (sc->bfe_txmbuf_tag != NULL) {
396 		for (i = 0; i < BFE_TX_LIST_CNT; i++) {
397 			td = &sc->bfe_tx_ring[i];
398 			if (td->bfe_map != NULL) {
399 				bus_dmamap_destroy(sc->bfe_txmbuf_tag,
400 				    td->bfe_map);
401 				td->bfe_map = NULL;
402 			}
403 		}
404 		bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
405 		sc->bfe_txmbuf_tag = NULL;
406 	}
407 
408 	/* Rx buffers. */
409 	if (sc->bfe_rxmbuf_tag != NULL) {
410 		for (i = 0; i < BFE_RX_LIST_CNT; i++) {
411 			rd = &sc->bfe_rx_ring[i];
412 			if (rd->bfe_map != NULL) {
413 				bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
414 				    rd->bfe_map);
415 				rd->bfe_map = NULL;
416 			}
417 		}
418 		if (sc->bfe_rx_sparemap != NULL) {
419 			bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
420 			    sc->bfe_rx_sparemap);
421 			sc->bfe_rx_sparemap = NULL;
422 		}
423 		bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
424 		sc->bfe_rxmbuf_tag = NULL;
425 	}
426 
427 	if (sc->bfe_parent_tag != NULL) {
428 		bus_dma_tag_destroy(sc->bfe_parent_tag);
429 		sc->bfe_parent_tag = NULL;
430 	}
431 }
432 
433 static int
434 bfe_attach(device_t dev)
435 {
436 	struct ifnet *ifp = NULL;
437 	struct bfe_softc *sc;
438 	int error = 0, rid;
439 
440 	sc = device_get_softc(dev);
441 	mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
442 			MTX_DEF);
443 	callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
444 
445 	sc->bfe_dev = dev;
446 
447 	/*
448 	 * Map control/status registers.
449 	 */
450 	pci_enable_busmaster(dev);
451 
452 	rid = PCIR_BAR(0);
453 	sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
454 			RF_ACTIVE);
455 	if (sc->bfe_res == NULL) {
456 		device_printf(dev, "couldn't map memory\n");
457 		error = ENXIO;
458 		goto fail;
459 	}
460 
461 	/* Allocate interrupt */
462 	rid = 0;
463 
464 	sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
465 			RF_SHAREABLE | RF_ACTIVE);
466 	if (sc->bfe_irq == NULL) {
467 		device_printf(dev, "couldn't map interrupt\n");
468 		error = ENXIO;
469 		goto fail;
470 	}
471 
472 	if (bfe_dma_alloc(sc) != 0) {
473 		device_printf(dev, "failed to allocate DMA resources\n");
474 		error = ENXIO;
475 		goto fail;
476 	}
477 
478 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
479 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
480 	    "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
481 	    sysctl_bfe_stats, "I", "Statistics");
482 
483 	/* Set up ifnet structure */
484 	ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
485 	if (ifp == NULL) {
486 		device_printf(dev, "failed to if_alloc()\n");
487 		error = ENOSPC;
488 		goto fail;
489 	}
490 	ifp->if_softc = sc;
491 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
492 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
493 	ifp->if_ioctl = bfe_ioctl;
494 	ifp->if_start = bfe_start;
495 	ifp->if_init = bfe_init;
496 	IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
497 	ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
498 	IFQ_SET_READY(&ifp->if_snd);
499 
500 	bfe_get_config(sc);
501 
502 	/* Reset the chip and turn on the PHY */
503 	BFE_LOCK(sc);
504 	bfe_chip_reset(sc);
505 	BFE_UNLOCK(sc);
506 
507 	error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
508 	    bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
509 	    0);
510 	if (error != 0) {
511 		device_printf(dev, "attaching PHYs failed\n");
512 		goto fail;
513 	}
514 
515 	ether_ifattach(ifp, sc->bfe_enaddr);
516 
517 	/*
518 	 * Tell the upper layer(s) we support long frames.
519 	 */
520 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
521 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
522 	ifp->if_capenable |= IFCAP_VLAN_MTU;
523 
524 	/*
525 	 * Hook interrupt last to avoid having to lock softc
526 	 */
527 	error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
528 			NULL, bfe_intr, sc, &sc->bfe_intrhand);
529 
530 	if (error) {
531 		device_printf(dev, "couldn't set up irq\n");
532 		goto fail;
533 	}
534 fail:
535 	if (error != 0)
536 		bfe_detach(dev);
537 	return (error);
538 }
539 
540 static int
541 bfe_detach(device_t dev)
542 {
543 	struct bfe_softc *sc;
544 	struct ifnet *ifp;
545 
546 	sc = device_get_softc(dev);
547 
548 	ifp = sc->bfe_ifp;
549 
550 	if (device_is_attached(dev)) {
551 		BFE_LOCK(sc);
552 		sc->bfe_flags |= BFE_FLAG_DETACH;
553 		bfe_stop(sc);
554 		BFE_UNLOCK(sc);
555 		callout_drain(&sc->bfe_stat_co);
556 		if (ifp != NULL)
557 			ether_ifdetach(ifp);
558 	}
559 
560 	BFE_LOCK(sc);
561 	bfe_chip_reset(sc);
562 	BFE_UNLOCK(sc);
563 
564 	bus_generic_detach(dev);
565 	if (sc->bfe_miibus != NULL)
566 		device_delete_child(dev, sc->bfe_miibus);
567 
568 	bfe_release_resources(sc);
569 	bfe_dma_free(sc);
570 	mtx_destroy(&sc->bfe_mtx);
571 
572 	return (0);
573 }
574 
575 /*
576  * Stop all chip I/O so that the kernel's probe routines don't
577  * get confused by errant DMAs when rebooting.
578  */
579 static int
580 bfe_shutdown(device_t dev)
581 {
582 	struct bfe_softc *sc;
583 
584 	sc = device_get_softc(dev);
585 	BFE_LOCK(sc);
586 	bfe_stop(sc);
587 
588 	BFE_UNLOCK(sc);
589 
590 	return (0);
591 }
592 
593 static int
594 bfe_suspend(device_t dev)
595 {
596 	struct bfe_softc *sc;
597 
598 	sc = device_get_softc(dev);
599 	BFE_LOCK(sc);
600 	bfe_stop(sc);
601 	BFE_UNLOCK(sc);
602 
603 	return (0);
604 }
605 
606 static int
607 bfe_resume(device_t dev)
608 {
609 	struct bfe_softc *sc;
610 	struct ifnet *ifp;
611 
612 	sc = device_get_softc(dev);
613 	ifp = sc->bfe_ifp;
614 	BFE_LOCK(sc);
615 	bfe_chip_reset(sc);
616 	if (ifp->if_flags & IFF_UP) {
617 		bfe_init_locked(sc);
618 		if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
619 		    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
620 			bfe_start_locked(ifp);
621 	}
622 	BFE_UNLOCK(sc);
623 
624 	return (0);
625 }
626 
627 static int
628 bfe_miibus_readreg(device_t dev, int phy, int reg)
629 {
630 	struct bfe_softc *sc;
631 	u_int32_t ret;
632 
633 	sc = device_get_softc(dev);
634 	bfe_readphy(sc, reg, &ret);
635 
636 	return (ret);
637 }
638 
639 static int
640 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
641 {
642 	struct bfe_softc *sc;
643 
644 	sc = device_get_softc(dev);
645 	bfe_writephy(sc, reg, val);
646 
647 	return (0);
648 }
649 
650 static void
651 bfe_miibus_statchg(device_t dev)
652 {
653 	struct bfe_softc *sc;
654 	struct mii_data *mii;
655 	u_int32_t val;
656 #ifdef notyet
657 	u_int32_t flow;
658 #endif
659 
660 	sc = device_get_softc(dev);
661 	mii = device_get_softc(sc->bfe_miibus);
662 
663 	sc->bfe_flags &= ~BFE_FLAG_LINK;
664 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
665 	    (IFM_ACTIVE | IFM_AVALID)) {
666 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
667 		case IFM_10_T:
668 		case IFM_100_TX:
669 			sc->bfe_flags |= BFE_FLAG_LINK;
670 			break;
671 		default:
672 			break;
673 		}
674 	}
675 
676 	/* XXX Should stop Rx/Tx engine prior to touching MAC. */
677 	val = CSR_READ_4(sc, BFE_TX_CTRL);
678 	val &= ~BFE_TX_DUPLEX;
679 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
680 		val |= BFE_TX_DUPLEX;
681 #ifdef notyet
682 		flow = CSR_READ_4(sc, BFE_RXCONF);
683 		flow &= ~BFE_RXCONF_FLOW;
684 		if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
685 		    IFM_ETH_RXPAUSE) != 0)
686 			flow |= BFE_RXCONF_FLOW;
687 		CSR_WRITE_4(sc, BFE_RXCONF, flow);
688 		/*
689 		 * It seems that the hardware has Tx pause issues
690 		 * so enable only Rx pause.
691 		 */
692 		flow = CSR_READ_4(sc, BFE_MAC_FLOW);
693 		flow &= ~BFE_FLOW_PAUSE_ENAB;
694 		CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
695 #endif
696 	}
697 	CSR_WRITE_4(sc, BFE_TX_CTRL, val);
698 }
699 
700 static void
701 bfe_tx_ring_free(struct bfe_softc *sc)
702 {
703 	int i;
704 
705 	for(i = 0; i < BFE_TX_LIST_CNT; i++) {
706 		if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
707 			bus_dmamap_sync(sc->bfe_txmbuf_tag,
708 			    sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
709 			bus_dmamap_unload(sc->bfe_txmbuf_tag,
710 			    sc->bfe_tx_ring[i].bfe_map);
711 			m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
712 			sc->bfe_tx_ring[i].bfe_mbuf = NULL;
713 		}
714 	}
715 	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
716 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
717 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
718 }
719 
720 static void
721 bfe_rx_ring_free(struct bfe_softc *sc)
722 {
723 	int i;
724 
725 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
726 		if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
727 			bus_dmamap_sync(sc->bfe_rxmbuf_tag,
728 			    sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
729 			bus_dmamap_unload(sc->bfe_rxmbuf_tag,
730 			    sc->bfe_rx_ring[i].bfe_map);
731 			m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
732 			sc->bfe_rx_ring[i].bfe_mbuf = NULL;
733 		}
734 	}
735 	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
736 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
737 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
738 }
739 
740 static int
741 bfe_list_rx_init(struct bfe_softc *sc)
742 {
743 	struct bfe_rx_data *rd;
744 	int i;
745 
746 	sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
747 	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
748 	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
749 		rd = &sc->bfe_rx_ring[i];
750 		rd->bfe_mbuf = NULL;
751 		rd->bfe_ctrl = 0;
752 		if (bfe_list_newbuf(sc, i) != 0)
753 			return (ENOBUFS);
754 	}
755 
756 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
757 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
758 	CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
759 
760 	return (0);
761 }
762 
763 static void
764 bfe_list_tx_init(struct bfe_softc *sc)
765 {
766 	int i;
767 
768 	sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
769 	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
770 	for (i = 0; i < BFE_TX_LIST_CNT; i++)
771 		sc->bfe_tx_ring[i].bfe_mbuf = NULL;
772 
773 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
774 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
775 }
776 
777 static void
778 bfe_discard_buf(struct bfe_softc *sc, int c)
779 {
780 	struct bfe_rx_data *r;
781 	struct bfe_desc *d;
782 
783 	r = &sc->bfe_rx_ring[c];
784 	d = &sc->bfe_rx_list[c];
785 	d->bfe_ctrl = htole32(r->bfe_ctrl);
786 }
787 
788 static int
789 bfe_list_newbuf(struct bfe_softc *sc, int c)
790 {
791 	struct bfe_rxheader *rx_header;
792 	struct bfe_desc *d;
793 	struct bfe_rx_data *r;
794 	struct mbuf *m;
795 	bus_dma_segment_t segs[1];
796 	bus_dmamap_t map;
797 	u_int32_t ctrl;
798 	int nsegs;
799 
800 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
801 	if (m == NULL)
802 		return (ENOBUFS);
803 	m->m_len = m->m_pkthdr.len = MCLBYTES;
804 
805 	if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
806 	    m, segs, &nsegs, 0) != 0) {
807 		m_freem(m);
808 		return (ENOBUFS);
809 	}
810 
811 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
812 	r = &sc->bfe_rx_ring[c];
813 	if (r->bfe_mbuf != NULL) {
814 		bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
815 		    BUS_DMASYNC_POSTREAD);
816 		bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
817 	}
818 	map = r->bfe_map;
819 	r->bfe_map = sc->bfe_rx_sparemap;
820 	sc->bfe_rx_sparemap = map;
821 	r->bfe_mbuf = m;
822 
823 	rx_header = mtod(m, struct bfe_rxheader *);
824 	rx_header->len = 0;
825 	rx_header->flags = 0;
826 	bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
827 
828 	ctrl = segs[0].ds_len & BFE_DESC_LEN;
829 	KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
830 	    __func__, ctrl));
831 	if (c == BFE_RX_LIST_CNT - 1)
832 		ctrl |= BFE_DESC_EOT;
833 	r->bfe_ctrl = ctrl;
834 
835 	d = &sc->bfe_rx_list[c];
836 	d->bfe_ctrl = htole32(ctrl);
837 	/* The chip needs all addresses to be added to BFE_PCI_DMA. */
838 	d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
839 
840 	return (0);
841 }
842 
843 static void
844 bfe_get_config(struct bfe_softc *sc)
845 {
846 	u_int8_t eeprom[128];
847 
848 	bfe_read_eeprom(sc, eeprom);
849 
850 	sc->bfe_enaddr[0] = eeprom[79];
851 	sc->bfe_enaddr[1] = eeprom[78];
852 	sc->bfe_enaddr[2] = eeprom[81];
853 	sc->bfe_enaddr[3] = eeprom[80];
854 	sc->bfe_enaddr[4] = eeprom[83];
855 	sc->bfe_enaddr[5] = eeprom[82];
856 
857 	sc->bfe_phyaddr = eeprom[90] & 0x1f;
858 	sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
859 
860 	sc->bfe_core_unit = 0;
861 	sc->bfe_dma_offset = BFE_PCI_DMA;
862 }
863 
864 static void
865 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
866 {
867 	u_int32_t bar_orig, pci_rev, val;
868 
869 	bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
870 	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
871 	pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
872 
873 	val = CSR_READ_4(sc, BFE_SBINTVEC);
874 	val |= cores;
875 	CSR_WRITE_4(sc, BFE_SBINTVEC, val);
876 
877 	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
878 	val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
879 	CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
880 
881 	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
882 }
883 
884 static void
885 bfe_clear_stats(struct bfe_softc *sc)
886 {
887 	uint32_t reg;
888 
889 	BFE_LOCK_ASSERT(sc);
890 
891 	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
892 	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
893 		CSR_READ_4(sc, reg);
894 	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
895 		CSR_READ_4(sc, reg);
896 }
897 
898 static int
899 bfe_resetphy(struct bfe_softc *sc)
900 {
901 	u_int32_t val;
902 
903 	bfe_writephy(sc, 0, BMCR_RESET);
904 	DELAY(100);
905 	bfe_readphy(sc, 0, &val);
906 	if (val & BMCR_RESET) {
907 		device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
908 		return (ENXIO);
909 	}
910 	return (0);
911 }
912 
913 static void
914 bfe_chip_halt(struct bfe_softc *sc)
915 {
916 	BFE_LOCK_ASSERT(sc);
917 	/* disable interrupts - not that it actually does..*/
918 	CSR_WRITE_4(sc, BFE_IMASK, 0);
919 	CSR_READ_4(sc, BFE_IMASK);
920 
921 	CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
922 	bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
923 
924 	CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
925 	CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
926 	DELAY(10);
927 }
928 
929 static void
930 bfe_chip_reset(struct bfe_softc *sc)
931 {
932 	u_int32_t val;
933 
934 	BFE_LOCK_ASSERT(sc);
935 
936 	/* Set the interrupt vector for the enet core */
937 	bfe_pci_setup(sc, BFE_INTVEC_ENET0);
938 
939 	/* is core up? */
940 	val = CSR_READ_4(sc, BFE_SBTMSLOW) &
941 	    (BFE_RESET | BFE_REJECT | BFE_CLOCK);
942 	if (val == BFE_CLOCK) {
943 		/* It is, so shut it down */
944 		CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
945 		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
946 		bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
947 		CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
948 		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
949 			bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
950 			    100, 0);
951 		CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
952 	}
953 
954 	bfe_core_reset(sc);
955 	bfe_clear_stats(sc);
956 
957 	/*
958 	 * We want the phy registers to be accessible even when
959 	 * the driver is "downed" so initialize MDC preamble, frequency,
960 	 * and whether internal or external phy here.
961 	 */
962 
963 	/* 4402 has 62.5Mhz SB clock and internal phy */
964 	CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
965 
966 	/* Internal or external PHY? */
967 	val = CSR_READ_4(sc, BFE_DEVCTRL);
968 	if (!(val & BFE_IPP))
969 		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
970 	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
971 		BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
972 		DELAY(100);
973 	}
974 
975 	/* Enable CRC32 generation and set proper LED modes */
976 	BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
977 
978 	/* Reset or clear powerdown control bit  */
979 	BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
980 
981 	CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
982 				BFE_LAZY_FC_MASK));
983 
984 	/*
985 	 * We don't want lazy interrupts, so just send them at
986 	 * the end of a frame, please
987 	 */
988 	BFE_OR(sc, BFE_RCV_LAZY, 0);
989 
990 	/* Set max lengths, accounting for VLAN tags */
991 	CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
992 	CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
993 
994 	/* Set watermark XXX - magic */
995 	CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
996 
997 	/*
998 	 * Initialise DMA channels
999 	 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
1000 	 */
1001 	CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
1002 	CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
1003 
1004 	CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1005 			BFE_RX_CTRL_ENABLE);
1006 	CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1007 
1008 	bfe_resetphy(sc);
1009 	bfe_setupphy(sc);
1010 }
1011 
1012 static void
1013 bfe_core_disable(struct bfe_softc *sc)
1014 {
1015 	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1016 		return;
1017 
1018 	/*
1019 	 * Set reject, wait for it set, then wait for the core to stop
1020 	 * being busy, then set reset and reject and enable the clocks.
1021 	 */
1022 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1023 	bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1024 	bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1025 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1026 				BFE_RESET));
1027 	CSR_READ_4(sc, BFE_SBTMSLOW);
1028 	DELAY(10);
1029 	/* Leave reset and reject set */
1030 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1031 	DELAY(10);
1032 }
1033 
1034 static void
1035 bfe_core_reset(struct bfe_softc *sc)
1036 {
1037 	u_int32_t val;
1038 
1039 	/* Disable the core */
1040 	bfe_core_disable(sc);
1041 
1042 	/* and bring it back up */
1043 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1044 	CSR_READ_4(sc, BFE_SBTMSLOW);
1045 	DELAY(10);
1046 
1047 	/* Chip bug, clear SERR, IB and TO if they are set. */
1048 	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1049 		CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1050 	val = CSR_READ_4(sc, BFE_SBIMSTATE);
1051 	if (val & (BFE_IBE | BFE_TO))
1052 		CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1053 
1054 	/* Clear reset and allow it to move through the core */
1055 	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1056 	CSR_READ_4(sc, BFE_SBTMSLOW);
1057 	DELAY(10);
1058 
1059 	/* Leave the clock set */
1060 	CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1061 	CSR_READ_4(sc, BFE_SBTMSLOW);
1062 	DELAY(10);
1063 }
1064 
1065 static void
1066 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1067 {
1068 	u_int32_t val;
1069 
1070 	val  = ((u_int32_t) data[2]) << 24;
1071 	val |= ((u_int32_t) data[3]) << 16;
1072 	val |= ((u_int32_t) data[4]) <<  8;
1073 	val |= ((u_int32_t) data[5]);
1074 	CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1075 	val = (BFE_CAM_HI_VALID |
1076 			(((u_int32_t) data[0]) << 8) |
1077 			(((u_int32_t) data[1])));
1078 	CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1079 	CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1080 				((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1081 	bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1082 }
1083 
1084 static u_int
1085 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1086 {
1087 	struct bfe_softc *sc = arg;
1088 
1089 	bfe_cam_write(sc, LLADDR(sdl), cnt + 1);
1090 
1091 	return (1);
1092 }
1093 
1094 static void
1095 bfe_set_rx_mode(struct bfe_softc *sc)
1096 {
1097 	struct ifnet *ifp = sc->bfe_ifp;
1098 	u_int32_t val;
1099 
1100 	BFE_LOCK_ASSERT(sc);
1101 
1102 	val = CSR_READ_4(sc, BFE_RXCONF);
1103 
1104 	if (ifp->if_flags & IFF_PROMISC)
1105 		val |= BFE_RXCONF_PROMISC;
1106 	else
1107 		val &= ~BFE_RXCONF_PROMISC;
1108 
1109 	if (ifp->if_flags & IFF_BROADCAST)
1110 		val &= ~BFE_RXCONF_DBCAST;
1111 	else
1112 		val |= BFE_RXCONF_DBCAST;
1113 
1114 	CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1115 	bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), 0);
1116 
1117 	if (ifp->if_flags & IFF_ALLMULTI)
1118 		val |= BFE_RXCONF_ALLMULTI;
1119 	else {
1120 		val &= ~BFE_RXCONF_ALLMULTI;
1121 		if_foreach_llmaddr(ifp, bfe_write_maddr, sc);
1122 	}
1123 
1124 	CSR_WRITE_4(sc, BFE_RXCONF, val);
1125 	BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1126 }
1127 
1128 static void
1129 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1130 {
1131 	struct bfe_dmamap_arg *ctx;
1132 
1133 	if (error != 0)
1134 		return;
1135 
1136 	KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1137 
1138 	ctx = (struct bfe_dmamap_arg *)arg;
1139 	ctx->bfe_busaddr = segs[0].ds_addr;
1140 }
1141 
1142 static void
1143 bfe_release_resources(struct bfe_softc *sc)
1144 {
1145 
1146 	if (sc->bfe_intrhand != NULL)
1147 		bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1148 
1149 	if (sc->bfe_irq != NULL)
1150 		bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1151 
1152 	if (sc->bfe_res != NULL)
1153 		bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1154 		    sc->bfe_res);
1155 
1156 	if (sc->bfe_ifp != NULL)
1157 		if_free(sc->bfe_ifp);
1158 }
1159 
1160 static void
1161 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1162 {
1163 	long i;
1164 	u_int16_t *ptr = (u_int16_t *)data;
1165 
1166 	for(i = 0; i < 128; i += 2)
1167 		ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1168 }
1169 
1170 static int
1171 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1172 		u_long timeout, const int clear)
1173 {
1174 	u_long i;
1175 
1176 	for (i = 0; i < timeout; i++) {
1177 		u_int32_t val = CSR_READ_4(sc, reg);
1178 
1179 		if (clear && !(val & bit))
1180 			break;
1181 		if (!clear && (val & bit))
1182 			break;
1183 		DELAY(10);
1184 	}
1185 	if (i == timeout) {
1186 		device_printf(sc->bfe_dev,
1187 		    "BUG!  Timeout waiting for bit %08x of register "
1188 		    "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1189 		return (-1);
1190 	}
1191 	return (0);
1192 }
1193 
1194 static int
1195 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1196 {
1197 	int err;
1198 
1199 	/* Clear MII ISR */
1200 	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1201 	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1202 				(BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1203 				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1204 				(reg << BFE_MDIO_RA_SHIFT) |
1205 				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1206 	err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1207 	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1208 
1209 	return (err);
1210 }
1211 
1212 static int
1213 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1214 {
1215 	int status;
1216 
1217 	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1218 	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1219 				(BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1220 				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1221 				(reg << BFE_MDIO_RA_SHIFT) |
1222 				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1223 				(val & BFE_MDIO_DATA_DATA)));
1224 	status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1225 
1226 	return (status);
1227 }
1228 
1229 /*
1230  * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1231  * twice
1232  */
1233 static int
1234 bfe_setupphy(struct bfe_softc *sc)
1235 {
1236 	u_int32_t val;
1237 
1238 	/* Enable activity LED */
1239 	bfe_readphy(sc, 26, &val);
1240 	bfe_writephy(sc, 26, val & 0x7fff);
1241 	bfe_readphy(sc, 26, &val);
1242 
1243 	/* Enable traffic meter LED mode */
1244 	bfe_readphy(sc, 27, &val);
1245 	bfe_writephy(sc, 27, val | (1 << 6));
1246 
1247 	return (0);
1248 }
1249 
1250 static void
1251 bfe_stats_update(struct bfe_softc *sc)
1252 {
1253 	struct bfe_hw_stats *stats;
1254 	struct ifnet *ifp;
1255 	uint32_t mib[BFE_MIB_CNT];
1256 	uint32_t reg, *val;
1257 
1258 	BFE_LOCK_ASSERT(sc);
1259 
1260 	val = mib;
1261 	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1262 	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1263 		*val++ = CSR_READ_4(sc, reg);
1264 	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1265 		*val++ = CSR_READ_4(sc, reg);
1266 
1267 	ifp = sc->bfe_ifp;
1268 	stats = &sc->bfe_stats;
1269 	/* Tx stat. */
1270 	stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1271 	stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1272 	stats->tx_octets += mib[MIB_TX_O];
1273 	stats->tx_frames += mib[MIB_TX_P];
1274 	stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1275 	stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1276 	stats->tx_pkts_64 += mib[MIB_TX_64];
1277 	stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1278 	stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1279 	stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1280 	stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1281 	stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1282 	stats->tx_jabbers += mib[MIB_TX_JABBER];
1283 	stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1284 	stats->tx_frag_frames += mib[MIB_TX_FRAG];
1285 	stats->tx_underruns += mib[MIB_TX_URUNS];
1286 	stats->tx_colls += mib[MIB_TX_TCOLS];
1287 	stats->tx_single_colls += mib[MIB_TX_SCOLS];
1288 	stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1289 	stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1290 	stats->tx_late_colls += mib[MIB_TX_LCOLS];
1291 	stats->tx_deferrals += mib[MIB_TX_DEFERED];
1292 	stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1293 	stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1294 	/* Rx stat. */
1295 	stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1296 	stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1297 	stats->rx_octets += mib[MIB_RX_O];
1298 	stats->rx_frames += mib[MIB_RX_P];
1299 	stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1300 	stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1301 	stats->rx_pkts_64 += mib[MIB_RX_64];
1302 	stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1303 	stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1304 	stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1305 	stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1306 	stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1307 	stats->rx_jabbers += mib[MIB_RX_JABBER];
1308 	stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1309 	stats->rx_frag_frames += mib[MIB_RX_FRAG];
1310 	stats->rx_missed_frames += mib[MIB_RX_MISS];
1311 	stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1312 	stats->rx_runts += mib[MIB_RX_USIZE];
1313 	stats->rx_crc_errs += mib[MIB_RX_CRC];
1314 	stats->rx_align_errs += mib[MIB_RX_ALIGN];
1315 	stats->rx_symbol_errs += mib[MIB_RX_SYM];
1316 	stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1317 	stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1318 
1319 	/* Update counters in ifnet. */
1320 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1321 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1322 	if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1323 	    (u_long)mib[MIB_TX_ECOLS] +
1324 	    (u_long)mib[MIB_TX_DEFERED] +
1325 	    (u_long)mib[MIB_TX_CLOST]);
1326 
1327 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1328 
1329 	if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1330 	    mib[MIB_RX_MISS] +
1331 	    mib[MIB_RX_CRCA] +
1332 	    mib[MIB_RX_USIZE] +
1333 	    mib[MIB_RX_CRC] +
1334 	    mib[MIB_RX_ALIGN] +
1335 	    mib[MIB_RX_SYM]);
1336 }
1337 
1338 static void
1339 bfe_txeof(struct bfe_softc *sc)
1340 {
1341 	struct bfe_tx_data *r;
1342 	struct ifnet *ifp;
1343 	int i, chipidx;
1344 
1345 	BFE_LOCK_ASSERT(sc);
1346 
1347 	ifp = sc->bfe_ifp;
1348 
1349 	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1350 	chipidx /= sizeof(struct bfe_desc);
1351 
1352 	i = sc->bfe_tx_cons;
1353 	if (i == chipidx)
1354 		return;
1355 	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1356 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1357 	/* Go through the mbufs and free those that have been transmitted */
1358 	for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1359 		r = &sc->bfe_tx_ring[i];
1360 		sc->bfe_tx_cnt--;
1361 		if (r->bfe_mbuf == NULL)
1362 			continue;
1363 		bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1364 		    BUS_DMASYNC_POSTWRITE);
1365 		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1366 
1367 		m_freem(r->bfe_mbuf);
1368 		r->bfe_mbuf = NULL;
1369 	}
1370 
1371 	if (i != sc->bfe_tx_cons) {
1372 		/* we freed up some mbufs */
1373 		sc->bfe_tx_cons = i;
1374 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1375 	}
1376 
1377 	if (sc->bfe_tx_cnt == 0)
1378 		sc->bfe_watchdog_timer = 0;
1379 }
1380 
1381 /* Pass a received packet up the stack */
1382 static void
1383 bfe_rxeof(struct bfe_softc *sc)
1384 {
1385 	struct mbuf *m;
1386 	struct ifnet *ifp;
1387 	struct bfe_rxheader *rxheader;
1388 	struct bfe_rx_data *r;
1389 	int cons, prog;
1390 	u_int32_t status, current, len, flags;
1391 
1392 	BFE_LOCK_ASSERT(sc);
1393 	cons = sc->bfe_rx_cons;
1394 	status = CSR_READ_4(sc, BFE_DMARX_STAT);
1395 	current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1396 
1397 	ifp = sc->bfe_ifp;
1398 
1399 	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1400 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1401 
1402 	for (prog = 0; current != cons; prog++,
1403 	    BFE_INC(cons, BFE_RX_LIST_CNT)) {
1404 		r = &sc->bfe_rx_ring[cons];
1405 		m = r->bfe_mbuf;
1406 		/*
1407 		 * Rx status should be read from mbuf such that we can't
1408 		 * delay bus_dmamap_sync(9). This hardware limiation
1409 		 * results in inefficent mbuf usage as bfe(4) couldn't
1410 		 * reuse mapped buffer from errored frame.
1411 		 */
1412 		if (bfe_list_newbuf(sc, cons) != 0) {
1413 			if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1414 			bfe_discard_buf(sc, cons);
1415 			continue;
1416 		}
1417 		rxheader = mtod(m, struct bfe_rxheader*);
1418 		len = le16toh(rxheader->len);
1419 		flags = le16toh(rxheader->flags);
1420 
1421 		/* Remove CRC bytes. */
1422 		len -= ETHER_CRC_LEN;
1423 
1424 		/* flag an error and try again */
1425 		if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1426 			m_freem(m);
1427 			continue;
1428 		}
1429 
1430 		/* Make sure to skip header bytes written by hardware. */
1431 		m_adj(m, BFE_RX_OFFSET);
1432 		m->m_len = m->m_pkthdr.len = len;
1433 
1434 		m->m_pkthdr.rcvif = ifp;
1435 		BFE_UNLOCK(sc);
1436 		(*ifp->if_input)(ifp, m);
1437 		BFE_LOCK(sc);
1438 	}
1439 
1440 	if (prog > 0) {
1441 		sc->bfe_rx_cons = cons;
1442 		bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1443 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1444 	}
1445 }
1446 
1447 static void
1448 bfe_intr(void *xsc)
1449 {
1450 	struct bfe_softc *sc = xsc;
1451 	struct ifnet *ifp;
1452 	u_int32_t istat;
1453 
1454 	ifp = sc->bfe_ifp;
1455 
1456 	BFE_LOCK(sc);
1457 
1458 	istat = CSR_READ_4(sc, BFE_ISTAT);
1459 
1460 	/*
1461 	 * Defer unsolicited interrupts - This is necessary because setting the
1462 	 * chips interrupt mask register to 0 doesn't actually stop the
1463 	 * interrupts
1464 	 */
1465 	istat &= BFE_IMASK_DEF;
1466 	CSR_WRITE_4(sc, BFE_ISTAT, istat);
1467 	CSR_READ_4(sc, BFE_ISTAT);
1468 
1469 	/* not expecting this interrupt, disregard it */
1470 	if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1471 		BFE_UNLOCK(sc);
1472 		return;
1473 	}
1474 
1475 	/* A packet was received */
1476 	if (istat & BFE_ISTAT_RX)
1477 		bfe_rxeof(sc);
1478 
1479 	/* A packet was sent */
1480 	if (istat & BFE_ISTAT_TX)
1481 		bfe_txeof(sc);
1482 
1483 	if (istat & BFE_ISTAT_ERRORS) {
1484 		if (istat & BFE_ISTAT_DSCE) {
1485 			device_printf(sc->bfe_dev, "Descriptor Error\n");
1486 			bfe_stop(sc);
1487 			BFE_UNLOCK(sc);
1488 			return;
1489 		}
1490 
1491 		if (istat & BFE_ISTAT_DPE) {
1492 			device_printf(sc->bfe_dev,
1493 			    "Descriptor Protocol Error\n");
1494 			bfe_stop(sc);
1495 			BFE_UNLOCK(sc);
1496 			return;
1497 		}
1498 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1499 		bfe_init_locked(sc);
1500 	}
1501 
1502 	/* We have packets pending, fire them out */
1503 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1504 		bfe_start_locked(ifp);
1505 
1506 	BFE_UNLOCK(sc);
1507 }
1508 
1509 static int
1510 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1511 {
1512 	struct bfe_desc *d;
1513 	struct bfe_tx_data *r, *r1;
1514 	struct mbuf *m;
1515 	bus_dmamap_t map;
1516 	bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1517 	uint32_t cur, si;
1518 	int error, i, nsegs;
1519 
1520 	BFE_LOCK_ASSERT(sc);
1521 
1522 	M_ASSERTPKTHDR((*m_head));
1523 
1524 	si = cur = sc->bfe_tx_prod;
1525 	r = &sc->bfe_tx_ring[cur];
1526 	error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1527 	    txsegs, &nsegs, 0);
1528 	if (error == EFBIG) {
1529 		m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1530 		if (m == NULL) {
1531 			m_freem(*m_head);
1532 			*m_head = NULL;
1533 			return (ENOMEM);
1534 		}
1535 		*m_head = m;
1536 		error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1537 		    *m_head, txsegs, &nsegs, 0);
1538 		if (error != 0) {
1539 			m_freem(*m_head);
1540 			*m_head = NULL;
1541 			return (error);
1542 		}
1543 	} else if (error != 0)
1544 		return (error);
1545 	if (nsegs == 0) {
1546 		m_freem(*m_head);
1547 		*m_head = NULL;
1548 		return (EIO);
1549 	}
1550 
1551 	if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1552 		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1553 		return (ENOBUFS);
1554 	}
1555 
1556 	for (i = 0; i < nsegs; i++) {
1557 		d = &sc->bfe_tx_list[cur];
1558 		d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1559 		d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1560 		if (cur == BFE_TX_LIST_CNT - 1)
1561 			/*
1562 			 * Tell the chip to wrap to the start of
1563 			 * the descriptor list.
1564 			 */
1565 			d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1566 		/* The chip needs all addresses to be added to BFE_PCI_DMA. */
1567 		d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1568 		    BFE_PCI_DMA);
1569 		BFE_INC(cur, BFE_TX_LIST_CNT);
1570 	}
1571 
1572 	/* Update producer index. */
1573 	sc->bfe_tx_prod = cur;
1574 
1575 	/* Set EOF on the last descriptor. */
1576 	cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1577 	d = &sc->bfe_tx_list[cur];
1578 	d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1579 
1580 	/* Lastly set SOF on the first descriptor to avoid races. */
1581 	d = &sc->bfe_tx_list[si];
1582 	d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1583 
1584 	r1 = &sc->bfe_tx_ring[cur];
1585 	map = r->bfe_map;
1586 	r->bfe_map = r1->bfe_map;
1587 	r1->bfe_map = map;
1588 	r1->bfe_mbuf = *m_head;
1589 	sc->bfe_tx_cnt += nsegs;
1590 
1591 	bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1592 
1593 	return (0);
1594 }
1595 
1596 /*
1597  * Set up to transmit a packet.
1598  */
1599 static void
1600 bfe_start(struct ifnet *ifp)
1601 {
1602 	BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1603 	bfe_start_locked(ifp);
1604 	BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1605 }
1606 
1607 /*
1608  * Set up to transmit a packet. The softc is already locked.
1609  */
1610 static void
1611 bfe_start_locked(struct ifnet *ifp)
1612 {
1613 	struct bfe_softc *sc;
1614 	struct mbuf *m_head;
1615 	int queued;
1616 
1617 	sc = ifp->if_softc;
1618 
1619 	BFE_LOCK_ASSERT(sc);
1620 
1621 	/*
1622 	 * Not much point trying to send if the link is down
1623 	 * or we have nothing to send.
1624 	 */
1625 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1626 	    IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1627 		return;
1628 
1629 	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1630 	    sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1631 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1632 		if (m_head == NULL)
1633 			break;
1634 
1635 		/*
1636 		 * Pack the data into the tx ring.  If we dont have
1637 		 * enough room, let the chip drain the ring.
1638 		 */
1639 		if (bfe_encap(sc, &m_head)) {
1640 			if (m_head == NULL)
1641 				break;
1642 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1643 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1644 			break;
1645 		}
1646 
1647 		queued++;
1648 
1649 		/*
1650 		 * If there's a BPF listener, bounce a copy of this frame
1651 		 * to him.
1652 		 */
1653 		BPF_MTAP(ifp, m_head);
1654 	}
1655 
1656 	if (queued) {
1657 		bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1658 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1659 		/* Transmit - twice due to apparent hardware bug */
1660 		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1661 		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1662 		/*
1663 		 * XXX It seems the following write is not necessary
1664 		 * to kick Tx command. What might be required would be
1665 		 * a way flushing PCI posted write. Reading the register
1666 		 * back ensures the flush operation. In addition,
1667 		 * hardware will execute PCI posted write in the long
1668 		 * run and watchdog timer for the kick command was set
1669 		 * to 5 seconds. Therefore I think the second write
1670 		 * access is not necessary or could be replaced with
1671 		 * read operation.
1672 		 */
1673 		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1674 		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1675 
1676 		/*
1677 		 * Set a timeout in case the chip goes out to lunch.
1678 		 */
1679 		sc->bfe_watchdog_timer = 5;
1680 	}
1681 }
1682 
1683 static void
1684 bfe_init(void *xsc)
1685 {
1686 	BFE_LOCK((struct bfe_softc *)xsc);
1687 	bfe_init_locked(xsc);
1688 	BFE_UNLOCK((struct bfe_softc *)xsc);
1689 }
1690 
1691 static void
1692 bfe_init_locked(void *xsc)
1693 {
1694 	struct bfe_softc *sc = (struct bfe_softc*)xsc;
1695 	struct ifnet *ifp = sc->bfe_ifp;
1696 	struct mii_data *mii;
1697 
1698 	BFE_LOCK_ASSERT(sc);
1699 
1700 	mii = device_get_softc(sc->bfe_miibus);
1701 
1702 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1703 		return;
1704 
1705 	bfe_stop(sc);
1706 	bfe_chip_reset(sc);
1707 
1708 	if (bfe_list_rx_init(sc) == ENOBUFS) {
1709 		device_printf(sc->bfe_dev,
1710 		    "%s: Not enough memory for list buffers\n", __func__);
1711 		bfe_stop(sc);
1712 		return;
1713 	}
1714 	bfe_list_tx_init(sc);
1715 
1716 	bfe_set_rx_mode(sc);
1717 
1718 	/* Enable the chip and core */
1719 	BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1720 	/* Enable interrupts */
1721 	CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1722 
1723 	/* Clear link state and change media. */
1724 	sc->bfe_flags &= ~BFE_FLAG_LINK;
1725 	mii_mediachg(mii);
1726 
1727 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1728 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1729 
1730 	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1731 }
1732 
1733 /*
1734  * Set media options.
1735  */
1736 static int
1737 bfe_ifmedia_upd(struct ifnet *ifp)
1738 {
1739 	struct bfe_softc *sc;
1740 	struct mii_data *mii;
1741 	struct mii_softc *miisc;
1742 	int error;
1743 
1744 	sc = ifp->if_softc;
1745 	BFE_LOCK(sc);
1746 
1747 	mii = device_get_softc(sc->bfe_miibus);
1748 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1749 		PHY_RESET(miisc);
1750 	error = mii_mediachg(mii);
1751 	BFE_UNLOCK(sc);
1752 
1753 	return (error);
1754 }
1755 
1756 /*
1757  * Report current media status.
1758  */
1759 static void
1760 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1761 {
1762 	struct bfe_softc *sc = ifp->if_softc;
1763 	struct mii_data *mii;
1764 
1765 	BFE_LOCK(sc);
1766 	mii = device_get_softc(sc->bfe_miibus);
1767 	mii_pollstat(mii);
1768 	ifmr->ifm_active = mii->mii_media_active;
1769 	ifmr->ifm_status = mii->mii_media_status;
1770 	BFE_UNLOCK(sc);
1771 }
1772 
1773 static int
1774 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1775 {
1776 	struct bfe_softc *sc = ifp->if_softc;
1777 	struct ifreq *ifr = (struct ifreq *) data;
1778 	struct mii_data *mii;
1779 	int error = 0;
1780 
1781 	switch (command) {
1782 	case SIOCSIFFLAGS:
1783 		BFE_LOCK(sc);
1784 		if (ifp->if_flags & IFF_UP) {
1785 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1786 				bfe_set_rx_mode(sc);
1787 			else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1788 				bfe_init_locked(sc);
1789 		} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1790 			bfe_stop(sc);
1791 		BFE_UNLOCK(sc);
1792 		break;
1793 	case SIOCADDMULTI:
1794 	case SIOCDELMULTI:
1795 		BFE_LOCK(sc);
1796 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1797 			bfe_set_rx_mode(sc);
1798 		BFE_UNLOCK(sc);
1799 		break;
1800 	case SIOCGIFMEDIA:
1801 	case SIOCSIFMEDIA:
1802 		mii = device_get_softc(sc->bfe_miibus);
1803 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1804 		break;
1805 	default:
1806 		error = ether_ioctl(ifp, command, data);
1807 		break;
1808 	}
1809 
1810 	return (error);
1811 }
1812 
1813 static void
1814 bfe_watchdog(struct bfe_softc *sc)
1815 {
1816 	struct ifnet *ifp;
1817 
1818 	BFE_LOCK_ASSERT(sc);
1819 
1820 	if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1821 		return;
1822 
1823 	ifp = sc->bfe_ifp;
1824 
1825 	device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1826 
1827 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1828 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1829 	bfe_init_locked(sc);
1830 
1831 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1832 		bfe_start_locked(ifp);
1833 }
1834 
1835 static void
1836 bfe_tick(void *xsc)
1837 {
1838 	struct bfe_softc *sc = xsc;
1839 	struct mii_data *mii;
1840 
1841 	BFE_LOCK_ASSERT(sc);
1842 
1843 	mii = device_get_softc(sc->bfe_miibus);
1844 	mii_tick(mii);
1845 	bfe_stats_update(sc);
1846 	bfe_watchdog(sc);
1847 	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1848 }
1849 
1850 /*
1851  * Stop the adapter and free any mbufs allocated to the
1852  * RX and TX lists.
1853  */
1854 static void
1855 bfe_stop(struct bfe_softc *sc)
1856 {
1857 	struct ifnet *ifp;
1858 
1859 	BFE_LOCK_ASSERT(sc);
1860 
1861 	ifp = sc->bfe_ifp;
1862 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1863 	sc->bfe_flags &= ~BFE_FLAG_LINK;
1864 	callout_stop(&sc->bfe_stat_co);
1865 	sc->bfe_watchdog_timer = 0;
1866 
1867 	bfe_chip_halt(sc);
1868 	bfe_tx_ring_free(sc);
1869 	bfe_rx_ring_free(sc);
1870 }
1871 
1872 static int
1873 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1874 {
1875 	struct bfe_softc *sc;
1876 	struct bfe_hw_stats *stats;
1877 	int error, result;
1878 
1879 	result = -1;
1880 	error = sysctl_handle_int(oidp, &result, 0, req);
1881 
1882 	if (error != 0 || req->newptr == NULL)
1883 		return (error);
1884 
1885 	if (result != 1)
1886 		return (error);
1887 
1888 	sc = (struct bfe_softc *)arg1;
1889 	stats = &sc->bfe_stats;
1890 
1891 	printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1892 	printf("Transmit good octets : %ju\n",
1893 	    (uintmax_t)stats->tx_good_octets);
1894 	printf("Transmit good frames : %ju\n",
1895 	    (uintmax_t)stats->tx_good_frames);
1896 	printf("Transmit octets : %ju\n",
1897 	    (uintmax_t)stats->tx_octets);
1898 	printf("Transmit frames : %ju\n",
1899 	    (uintmax_t)stats->tx_frames);
1900 	printf("Transmit broadcast frames : %ju\n",
1901 	    (uintmax_t)stats->tx_bcast_frames);
1902 	printf("Transmit multicast frames : %ju\n",
1903 	    (uintmax_t)stats->tx_mcast_frames);
1904 	printf("Transmit frames 64 bytes : %ju\n",
1905 	    (uint64_t)stats->tx_pkts_64);
1906 	printf("Transmit frames 65 to 127 bytes : %ju\n",
1907 	    (uint64_t)stats->tx_pkts_65_127);
1908 	printf("Transmit frames 128 to 255 bytes : %ju\n",
1909 	    (uint64_t)stats->tx_pkts_128_255);
1910 	printf("Transmit frames 256 to 511 bytes : %ju\n",
1911 	    (uint64_t)stats->tx_pkts_256_511);
1912 	printf("Transmit frames 512 to 1023 bytes : %ju\n",
1913 	    (uint64_t)stats->tx_pkts_512_1023);
1914 	printf("Transmit frames 1024 to max bytes : %ju\n",
1915 	    (uint64_t)stats->tx_pkts_1024_max);
1916 	printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1917 	printf("Transmit oversized frames : %ju\n",
1918 	    (uint64_t)stats->tx_oversize_frames);
1919 	printf("Transmit fragmented frames : %ju\n",
1920 	    (uint64_t)stats->tx_frag_frames);
1921 	printf("Transmit underruns : %u\n", stats->tx_colls);
1922 	printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1923 	printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1924 	printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1925 	printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1926 	printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1927 	printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1928 	printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1929 	printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1930 
1931 	printf("Receive good octets : %ju\n",
1932 	    (uintmax_t)stats->rx_good_octets);
1933 	printf("Receive good frames : %ju\n",
1934 	    (uintmax_t)stats->rx_good_frames);
1935 	printf("Receive octets : %ju\n",
1936 	    (uintmax_t)stats->rx_octets);
1937 	printf("Receive frames : %ju\n",
1938 	    (uintmax_t)stats->rx_frames);
1939 	printf("Receive broadcast frames : %ju\n",
1940 	    (uintmax_t)stats->rx_bcast_frames);
1941 	printf("Receive multicast frames : %ju\n",
1942 	    (uintmax_t)stats->rx_mcast_frames);
1943 	printf("Receive frames 64 bytes : %ju\n",
1944 	    (uint64_t)stats->rx_pkts_64);
1945 	printf("Receive frames 65 to 127 bytes : %ju\n",
1946 	    (uint64_t)stats->rx_pkts_65_127);
1947 	printf("Receive frames 128 to 255 bytes : %ju\n",
1948 	    (uint64_t)stats->rx_pkts_128_255);
1949 	printf("Receive frames 256 to 511 bytes : %ju\n",
1950 	    (uint64_t)stats->rx_pkts_256_511);
1951 	printf("Receive frames 512 to 1023 bytes : %ju\n",
1952 	    (uint64_t)stats->rx_pkts_512_1023);
1953 	printf("Receive frames 1024 to max bytes : %ju\n",
1954 	    (uint64_t)stats->rx_pkts_1024_max);
1955 	printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1956 	printf("Receive oversized frames : %ju\n",
1957 	    (uint64_t)stats->rx_oversize_frames);
1958 	printf("Receive fragmented frames : %ju\n",
1959 	    (uint64_t)stats->rx_frag_frames);
1960 	printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1961 	printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1962 	printf("Receive undersized frames : %u\n", stats->rx_runts);
1963 	printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1964 	printf("Receive align errors : %u\n", stats->rx_align_errs);
1965 	printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1966 	printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1967 	printf("Receive control frames : %u\n", stats->rx_control_frames);
1968 
1969 	return (error);
1970 }
1971