1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6 /* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/queue.h> 42 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <net/bpf.h> 50 51 #include <net/if_types.h> 52 #include <net/if_vlan_var.h> 53 54 #include <netinet/in_systm.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include "miidevs.h" 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <dev/bfe/if_bfereg.h> 73 74 MODULE_DEPEND(bfe, pci, 1, 1, 1); 75 MODULE_DEPEND(bfe, ether, 1, 1, 1); 76 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78 /* "controller miibus0" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83 static struct bfe_type bfe_devs[] = { 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 87 "Broadcom BCM4401-B0 Fast Ethernet" }, 88 { 0, 0, NULL } 89 }; 90 91 static int bfe_probe (device_t); 92 static int bfe_attach (device_t); 93 static int bfe_detach (device_t); 94 static void bfe_release_resources (struct bfe_softc *); 95 static void bfe_intr (void *); 96 static void bfe_start (struct ifnet *); 97 static void bfe_start_locked (struct ifnet *); 98 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 99 static void bfe_init (void *); 100 static void bfe_init_locked (void *); 101 static void bfe_stop (struct bfe_softc *); 102 static void bfe_watchdog (struct ifnet *); 103 static void bfe_shutdown (device_t); 104 static void bfe_tick (void *); 105 static void bfe_txeof (struct bfe_softc *); 106 static void bfe_rxeof (struct bfe_softc *); 107 static void bfe_set_rx_mode (struct bfe_softc *); 108 static int bfe_list_rx_init (struct bfe_softc *); 109 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 110 static void bfe_rx_ring_free (struct bfe_softc *); 111 112 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 113 static int bfe_ifmedia_upd (struct ifnet *); 114 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 115 static int bfe_miibus_readreg (device_t, int, int); 116 static int bfe_miibus_writereg (device_t, int, int, int); 117 static void bfe_miibus_statchg (device_t); 118 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 119 u_long, const int); 120 static void bfe_get_config (struct bfe_softc *sc); 121 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 122 static void bfe_stats_update (struct bfe_softc *); 123 static void bfe_clear_stats (struct bfe_softc *); 124 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 125 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 126 static int bfe_resetphy (struct bfe_softc *); 127 static int bfe_setupphy (struct bfe_softc *); 128 static void bfe_chip_reset (struct bfe_softc *); 129 static void bfe_chip_halt (struct bfe_softc *); 130 static void bfe_core_reset (struct bfe_softc *); 131 static void bfe_core_disable (struct bfe_softc *); 132 static int bfe_dma_alloc (device_t); 133 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 134 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 135 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 136 137 static device_method_t bfe_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, bfe_probe), 140 DEVMETHOD(device_attach, bfe_attach), 141 DEVMETHOD(device_detach, bfe_detach), 142 DEVMETHOD(device_shutdown, bfe_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160 }; 161 162 static devclass_t bfe_devclass; 163 164 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167 /* 168 * Probe for a Broadcom 4401 chip. 169 */ 170 static int 171 bfe_probe(device_t dev) 172 { 173 struct bfe_type *t; 174 struct bfe_softc *sc; 175 176 t = bfe_devs; 177 178 sc = device_get_softc(dev); 179 bzero(sc, sizeof(struct bfe_softc)); 180 sc->bfe_unit = device_get_unit(dev); 181 sc->bfe_dev = dev; 182 183 while(t->bfe_name != NULL) { 184 if ((pci_get_vendor(dev) == t->bfe_vid) && 185 (pci_get_device(dev) == t->bfe_did)) { 186 device_set_desc_copy(dev, t->bfe_name); 187 return (0); 188 } 189 t++; 190 } 191 192 return (ENXIO); 193 } 194 195 static int 196 bfe_dma_alloc(device_t dev) 197 { 198 struct bfe_softc *sc; 199 int error, i; 200 201 sc = device_get_softc(dev); 202 203 /* parent tag */ 204 error = bus_dma_tag_create(NULL, /* parent */ 205 PAGE_SIZE, 0, /* alignment, boundary */ 206 BUS_SPACE_MAXADDR, /* lowaddr */ 207 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 208 NULL, NULL, /* filter, filterarg */ 209 MAXBSIZE, /* maxsize */ 210 BUS_SPACE_UNRESTRICTED, /* num of segments */ 211 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 212 BUS_DMA_ALLOCNOW, /* flags */ 213 NULL, NULL, /* lockfunc, lockarg */ 214 &sc->bfe_parent_tag); 215 216 /* tag for TX ring */ 217 error = bus_dma_tag_create(sc->bfe_parent_tag, 218 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 219 BUS_SPACE_MAXADDR, 220 BUS_SPACE_MAXADDR, 221 NULL, NULL, 222 BFE_TX_LIST_SIZE, 223 1, 224 BUS_SPACE_MAXSIZE_32BIT, 225 0, 226 NULL, NULL, 227 &sc->bfe_tx_tag); 228 229 if (error) { 230 device_printf(dev, "could not allocate dma tag\n"); 231 return (ENOMEM); 232 } 233 234 /* tag for RX ring */ 235 error = bus_dma_tag_create(sc->bfe_parent_tag, 236 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 237 BUS_SPACE_MAXADDR, 238 BUS_SPACE_MAXADDR, 239 NULL, NULL, 240 BFE_RX_LIST_SIZE, 241 1, 242 BUS_SPACE_MAXSIZE_32BIT, 243 0, 244 NULL, NULL, 245 &sc->bfe_rx_tag); 246 247 if (error) { 248 device_printf(dev, "could not allocate dma tag\n"); 249 return (ENOMEM); 250 } 251 252 /* tag for mbufs */ 253 error = bus_dma_tag_create(sc->bfe_parent_tag, 254 ETHER_ALIGN, 0, 255 BUS_SPACE_MAXADDR, 256 BUS_SPACE_MAXADDR, 257 NULL, NULL, 258 MCLBYTES, 259 1, 260 BUS_SPACE_MAXSIZE_32BIT, 261 0, 262 NULL, NULL, 263 &sc->bfe_tag); 264 265 if (error) { 266 device_printf(dev, "could not allocate dma tag\n"); 267 return (ENOMEM); 268 } 269 270 /* pre allocate dmamaps for RX list */ 271 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 272 error = bus_dmamap_create(sc->bfe_tag, 0, 273 &sc->bfe_rx_ring[i].bfe_map); 274 if (error) { 275 device_printf(dev, "cannot create DMA map for RX\n"); 276 return (ENOMEM); 277 } 278 } 279 280 /* pre allocate dmamaps for TX list */ 281 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 282 error = bus_dmamap_create(sc->bfe_tag, 0, 283 &sc->bfe_tx_ring[i].bfe_map); 284 if (error) { 285 device_printf(dev, "cannot create DMA map for TX\n"); 286 return (ENOMEM); 287 } 288 } 289 290 /* Alloc dma for rx ring */ 291 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 292 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 293 294 if(error) 295 return (ENOMEM); 296 297 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 298 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 299 sc->bfe_rx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_rx_dma, 0); 301 302 if(error) 303 return (ENOMEM); 304 305 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 306 307 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 308 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 309 if (error) 310 return (ENOMEM); 311 312 313 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 314 sc->bfe_tx_list, sizeof(struct bfe_desc), 315 bfe_dma_map, &sc->bfe_tx_dma, 0); 316 if(error) 317 return (ENOMEM); 318 319 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 320 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 321 322 return (0); 323 } 324 325 static int 326 bfe_attach(device_t dev) 327 { 328 struct ifnet *ifp; 329 struct bfe_softc *sc; 330 int unit, error = 0, rid; 331 332 sc = device_get_softc(dev); 333 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 334 MTX_DEF); 335 336 unit = device_get_unit(dev); 337 sc->bfe_dev = dev; 338 sc->bfe_unit = unit; 339 340 /* 341 * Handle power management nonsense. 342 */ 343 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 344 u_int32_t membase, irq; 345 346 /* Save important PCI config data. */ 347 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 348 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 349 350 /* Reset the power state. */ 351 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 352 sc->bfe_unit, pci_get_powerstate(dev)); 353 354 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 355 356 /* Restore PCI config data. */ 357 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 358 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 359 } 360 361 /* 362 * Map control/status registers. 363 */ 364 pci_enable_busmaster(dev); 365 366 rid = BFE_PCI_MEMLO; 367 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 368 RF_ACTIVE); 369 if (sc->bfe_res == NULL) { 370 printf ("bfe%d: couldn't map memory\n", unit); 371 error = ENXIO; 372 goto fail; 373 } 374 375 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 376 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 377 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 378 379 /* Allocate interrupt */ 380 rid = 0; 381 382 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 383 RF_SHAREABLE | RF_ACTIVE); 384 if (sc->bfe_irq == NULL) { 385 printf("bfe%d: couldn't map interrupt\n", unit); 386 error = ENXIO; 387 goto fail; 388 } 389 390 if (bfe_dma_alloc(dev)) { 391 printf("bfe%d: failed to allocate DMA resources\n", 392 sc->bfe_unit); 393 bfe_release_resources(sc); 394 error = ENXIO; 395 goto fail; 396 } 397 398 /* Set up ifnet structure */ 399 ifp = &sc->arpcom.ac_if; 400 ifp->if_softc = sc; 401 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 402 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 403 ifp->if_ioctl = bfe_ioctl; 404 ifp->if_start = bfe_start; 405 ifp->if_watchdog = bfe_watchdog; 406 ifp->if_init = bfe_init; 407 ifp->if_mtu = ETHERMTU; 408 ifp->if_baudrate = 100000000; 409 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 410 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 411 IFQ_SET_READY(&ifp->if_snd); 412 413 bfe_get_config(sc); 414 415 /* Reset the chip and turn on the PHY */ 416 BFE_LOCK(sc); 417 bfe_chip_reset(sc); 418 BFE_UNLOCK(sc); 419 420 if (mii_phy_probe(dev, &sc->bfe_miibus, 421 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 422 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 423 error = ENXIO; 424 goto fail; 425 } 426 427 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 428 callout_handle_init(&sc->bfe_stat_ch); 429 430 /* 431 * Tell the upper layer(s) we support long frames. 432 */ 433 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 434 ifp->if_capabilities |= IFCAP_VLAN_MTU; 435 ifp->if_capenable |= IFCAP_VLAN_MTU; 436 437 /* 438 * Hook interrupt last to avoid having to lock softc 439 */ 440 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 441 bfe_intr, sc, &sc->bfe_intrhand); 442 443 if (error) { 444 bfe_release_resources(sc); 445 printf("bfe%d: couldn't set up irq\n", unit); 446 goto fail; 447 } 448 fail: 449 if(error) 450 bfe_release_resources(sc); 451 return (error); 452 } 453 454 static int 455 bfe_detach(device_t dev) 456 { 457 struct bfe_softc *sc; 458 struct ifnet *ifp; 459 460 sc = device_get_softc(dev); 461 462 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 463 BFE_LOCK(sc); 464 465 ifp = &sc->arpcom.ac_if; 466 467 if (device_is_attached(dev)) { 468 bfe_stop(sc); 469 ether_ifdetach(ifp); 470 } 471 472 bfe_chip_reset(sc); 473 474 bus_generic_detach(dev); 475 if(sc->bfe_miibus != NULL) 476 device_delete_child(dev, sc->bfe_miibus); 477 478 bfe_release_resources(sc); 479 BFE_UNLOCK(sc); 480 mtx_destroy(&sc->bfe_mtx); 481 482 return (0); 483 } 484 485 /* 486 * Stop all chip I/O so that the kernel's probe routines don't 487 * get confused by errant DMAs when rebooting. 488 */ 489 static void 490 bfe_shutdown(device_t dev) 491 { 492 struct bfe_softc *sc; 493 494 sc = device_get_softc(dev); 495 BFE_LOCK(sc); 496 bfe_stop(sc); 497 498 BFE_UNLOCK(sc); 499 return; 500 } 501 502 static int 503 bfe_miibus_readreg(device_t dev, int phy, int reg) 504 { 505 struct bfe_softc *sc; 506 u_int32_t ret; 507 508 sc = device_get_softc(dev); 509 if(phy != sc->bfe_phyaddr) 510 return (0); 511 bfe_readphy(sc, reg, &ret); 512 513 return (ret); 514 } 515 516 static int 517 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 518 { 519 struct bfe_softc *sc; 520 521 sc = device_get_softc(dev); 522 if(phy != sc->bfe_phyaddr) 523 return (0); 524 bfe_writephy(sc, reg, val); 525 526 return (0); 527 } 528 529 static void 530 bfe_miibus_statchg(device_t dev) 531 { 532 return; 533 } 534 535 static void 536 bfe_tx_ring_free(struct bfe_softc *sc) 537 { 538 int i; 539 540 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 541 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 542 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 543 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 544 bus_dmamap_unload(sc->bfe_tag, 545 sc->bfe_tx_ring[i].bfe_map); 546 bus_dmamap_destroy(sc->bfe_tag, 547 sc->bfe_tx_ring[i].bfe_map); 548 } 549 } 550 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 551 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 552 } 553 554 static void 555 bfe_rx_ring_free(struct bfe_softc *sc) 556 { 557 int i; 558 559 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 560 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 561 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 562 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 563 bus_dmamap_unload(sc->bfe_tag, 564 sc->bfe_rx_ring[i].bfe_map); 565 bus_dmamap_destroy(sc->bfe_tag, 566 sc->bfe_rx_ring[i].bfe_map); 567 } 568 } 569 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 570 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 571 } 572 573 574 static int 575 bfe_list_rx_init(struct bfe_softc *sc) 576 { 577 int i; 578 579 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 580 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 581 return (ENOBUFS); 582 } 583 584 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 585 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 586 587 sc->bfe_rx_cons = 0; 588 589 return (0); 590 } 591 592 static int 593 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 594 { 595 struct bfe_rxheader *rx_header; 596 struct bfe_desc *d; 597 struct bfe_data *r; 598 u_int32_t ctrl; 599 600 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 601 return (EINVAL); 602 603 if(m == NULL) { 604 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 605 if(m == NULL) 606 return (ENOBUFS); 607 m->m_len = m->m_pkthdr.len = MCLBYTES; 608 } 609 else 610 m->m_data = m->m_ext.ext_buf; 611 612 rx_header = mtod(m, struct bfe_rxheader *); 613 rx_header->len = 0; 614 rx_header->flags = 0; 615 616 /* Map the mbuf into DMA */ 617 sc->bfe_rx_cnt = c; 618 d = &sc->bfe_rx_list[c]; 619 r = &sc->bfe_rx_ring[c]; 620 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 621 MCLBYTES, bfe_dma_map_desc, d, 0); 622 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 623 624 ctrl = ETHER_MAX_LEN + 32; 625 626 if(c == BFE_RX_LIST_CNT - 1) 627 ctrl |= BFE_DESC_EOT; 628 629 d->bfe_ctrl = ctrl; 630 r->bfe_mbuf = m; 631 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 632 return (0); 633 } 634 635 static void 636 bfe_get_config(struct bfe_softc *sc) 637 { 638 u_int8_t eeprom[128]; 639 640 bfe_read_eeprom(sc, eeprom); 641 642 sc->arpcom.ac_enaddr[0] = eeprom[79]; 643 sc->arpcom.ac_enaddr[1] = eeprom[78]; 644 sc->arpcom.ac_enaddr[2] = eeprom[81]; 645 sc->arpcom.ac_enaddr[3] = eeprom[80]; 646 sc->arpcom.ac_enaddr[4] = eeprom[83]; 647 sc->arpcom.ac_enaddr[5] = eeprom[82]; 648 649 sc->bfe_phyaddr = eeprom[90] & 0x1f; 650 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 651 652 sc->bfe_core_unit = 0; 653 sc->bfe_dma_offset = BFE_PCI_DMA; 654 } 655 656 static void 657 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 658 { 659 u_int32_t bar_orig, pci_rev, val; 660 661 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 662 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 663 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 664 665 val = CSR_READ_4(sc, BFE_SBINTVEC); 666 val |= cores; 667 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 668 669 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 670 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 671 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 672 673 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 674 } 675 676 static void 677 bfe_clear_stats(struct bfe_softc *sc) 678 { 679 u_long reg; 680 681 BFE_LOCK_ASSERT(sc); 682 683 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 684 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 685 CSR_READ_4(sc, reg); 686 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 687 CSR_READ_4(sc, reg); 688 } 689 690 static int 691 bfe_resetphy(struct bfe_softc *sc) 692 { 693 u_int32_t val; 694 695 bfe_writephy(sc, 0, BMCR_RESET); 696 DELAY(100); 697 bfe_readphy(sc, 0, &val); 698 if (val & BMCR_RESET) { 699 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 700 return (ENXIO); 701 } 702 return (0); 703 } 704 705 static void 706 bfe_chip_halt(struct bfe_softc *sc) 707 { 708 BFE_LOCK_ASSERT(sc); 709 /* disable interrupts - not that it actually does..*/ 710 CSR_WRITE_4(sc, BFE_IMASK, 0); 711 CSR_READ_4(sc, BFE_IMASK); 712 713 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 714 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 715 716 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 717 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 718 DELAY(10); 719 } 720 721 static void 722 bfe_chip_reset(struct bfe_softc *sc) 723 { 724 u_int32_t val; 725 726 BFE_LOCK_ASSERT(sc); 727 728 /* Set the interrupt vector for the enet core */ 729 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 730 731 /* is core up? */ 732 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 733 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 734 if (val == BFE_CLOCK) { 735 /* It is, so shut it down */ 736 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 737 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 738 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 739 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 740 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 741 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 742 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 743 100, 0); 744 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 745 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 746 } 747 748 bfe_core_reset(sc); 749 bfe_clear_stats(sc); 750 751 /* 752 * We want the phy registers to be accessible even when 753 * the driver is "downed" so initialize MDC preamble, frequency, 754 * and whether internal or external phy here. 755 */ 756 757 /* 4402 has 62.5Mhz SB clock and internal phy */ 758 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 759 760 /* Internal or external PHY? */ 761 val = CSR_READ_4(sc, BFE_DEVCTRL); 762 if(!(val & BFE_IPP)) 763 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 764 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 765 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 766 DELAY(100); 767 } 768 769 /* Enable CRC32 generation and set proper LED modes */ 770 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 771 772 /* Reset or clear powerdown control bit */ 773 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 774 775 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 776 BFE_LAZY_FC_MASK)); 777 778 /* 779 * We don't want lazy interrupts, so just send them at 780 * the end of a frame, please 781 */ 782 BFE_OR(sc, BFE_RCV_LAZY, 0); 783 784 /* Set max lengths, accounting for VLAN tags */ 785 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 786 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 787 788 /* Set watermark XXX - magic */ 789 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 790 791 /* 792 * Initialise DMA channels 793 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 794 */ 795 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 796 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 797 798 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 799 BFE_RX_CTRL_ENABLE); 800 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 801 802 bfe_resetphy(sc); 803 bfe_setupphy(sc); 804 } 805 806 static void 807 bfe_core_disable(struct bfe_softc *sc) 808 { 809 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 810 return; 811 812 /* 813 * Set reject, wait for it set, then wait for the core to stop 814 * being busy, then set reset and reject and enable the clocks. 815 */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 817 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 818 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 820 BFE_RESET)); 821 CSR_READ_4(sc, BFE_SBTMSLOW); 822 DELAY(10); 823 /* Leave reset and reject set */ 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 825 DELAY(10); 826 } 827 828 static void 829 bfe_core_reset(struct bfe_softc *sc) 830 { 831 u_int32_t val; 832 833 /* Disable the core */ 834 bfe_core_disable(sc); 835 836 /* and bring it back up */ 837 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 841 /* Chip bug, clear SERR, IB and TO if they are set. */ 842 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 843 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 844 val = CSR_READ_4(sc, BFE_SBIMSTATE); 845 if (val & (BFE_IBE | BFE_TO)) 846 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 847 848 /* Clear reset and allow it to move through the core */ 849 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 850 CSR_READ_4(sc, BFE_SBTMSLOW); 851 DELAY(10); 852 853 /* Leave the clock set */ 854 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 855 CSR_READ_4(sc, BFE_SBTMSLOW); 856 DELAY(10); 857 } 858 859 static void 860 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 861 { 862 u_int32_t val; 863 864 val = ((u_int32_t) data[2]) << 24; 865 val |= ((u_int32_t) data[3]) << 16; 866 val |= ((u_int32_t) data[4]) << 8; 867 val |= ((u_int32_t) data[5]); 868 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 869 val = (BFE_CAM_HI_VALID | 870 (((u_int32_t) data[0]) << 8) | 871 (((u_int32_t) data[1]))); 872 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 873 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 874 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 875 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 876 } 877 878 static void 879 bfe_set_rx_mode(struct bfe_softc *sc) 880 { 881 struct ifnet *ifp = &sc->arpcom.ac_if; 882 struct ifmultiaddr *ifma; 883 u_int32_t val; 884 int i = 0; 885 886 val = CSR_READ_4(sc, BFE_RXCONF); 887 888 if (ifp->if_flags & IFF_PROMISC) 889 val |= BFE_RXCONF_PROMISC; 890 else 891 val &= ~BFE_RXCONF_PROMISC; 892 893 if (ifp->if_flags & IFF_BROADCAST) 894 val &= ~BFE_RXCONF_DBCAST; 895 else 896 val |= BFE_RXCONF_DBCAST; 897 898 899 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 900 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 901 902 if (ifp->if_flags & IFF_ALLMULTI) 903 val |= BFE_RXCONF_ALLMULTI; 904 else { 905 val &= ~BFE_RXCONF_ALLMULTI; 906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 907 if (ifma->ifma_addr->sa_family != AF_LINK) 908 continue; 909 bfe_cam_write(sc, 910 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 911 } 912 } 913 914 CSR_WRITE_4(sc, BFE_RXCONF, val); 915 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 916 } 917 918 static void 919 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 920 { 921 u_int32_t *ptr; 922 923 ptr = arg; 924 *ptr = segs->ds_addr; 925 } 926 927 static void 928 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 929 { 930 struct bfe_desc *d; 931 932 d = arg; 933 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 934 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 935 } 936 937 static void 938 bfe_release_resources(struct bfe_softc *sc) 939 { 940 device_t dev; 941 int i; 942 943 dev = sc->bfe_dev; 944 945 if (sc->bfe_vpd_prodname != NULL) 946 free(sc->bfe_vpd_prodname, M_DEVBUF); 947 948 if (sc->bfe_vpd_readonly != NULL) 949 free(sc->bfe_vpd_readonly, M_DEVBUF); 950 951 if (sc->bfe_intrhand != NULL) 952 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 953 954 if (sc->bfe_irq != NULL) 955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 956 957 if (sc->bfe_res != NULL) 958 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 959 960 if(sc->bfe_tx_tag != NULL) { 961 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 962 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 963 sc->bfe_tx_map); 964 bus_dma_tag_destroy(sc->bfe_tx_tag); 965 sc->bfe_tx_tag = NULL; 966 } 967 968 if(sc->bfe_rx_tag != NULL) { 969 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 970 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 971 sc->bfe_rx_map); 972 bus_dma_tag_destroy(sc->bfe_rx_tag); 973 sc->bfe_rx_tag = NULL; 974 } 975 976 if(sc->bfe_tag != NULL) { 977 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 978 bus_dmamap_destroy(sc->bfe_tag, 979 sc->bfe_tx_ring[i].bfe_map); 980 } 981 bus_dma_tag_destroy(sc->bfe_tag); 982 sc->bfe_tag = NULL; 983 } 984 985 if(sc->bfe_parent_tag != NULL) 986 bus_dma_tag_destroy(sc->bfe_parent_tag); 987 988 return; 989 } 990 991 static void 992 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 993 { 994 long i; 995 u_int16_t *ptr = (u_int16_t *)data; 996 997 for(i = 0; i < 128; i += 2) 998 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 999 } 1000 1001 static int 1002 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1003 u_long timeout, const int clear) 1004 { 1005 u_long i; 1006 1007 for (i = 0; i < timeout; i++) { 1008 u_int32_t val = CSR_READ_4(sc, reg); 1009 1010 if (clear && !(val & bit)) 1011 break; 1012 if (!clear && (val & bit)) 1013 break; 1014 DELAY(10); 1015 } 1016 if (i == timeout) { 1017 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1018 "%x to %s.\n", sc->bfe_unit, bit, reg, 1019 (clear ? "clear" : "set")); 1020 return (-1); 1021 } 1022 return (0); 1023 } 1024 1025 static int 1026 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1027 { 1028 int err; 1029 1030 /* Clear MII ISR */ 1031 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1032 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1033 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1034 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1035 (reg << BFE_MDIO_RA_SHIFT) | 1036 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1037 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1038 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1039 1040 return (err); 1041 } 1042 1043 static int 1044 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1045 { 1046 int status; 1047 1048 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1049 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1050 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1051 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1052 (reg << BFE_MDIO_RA_SHIFT) | 1053 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1054 (val & BFE_MDIO_DATA_DATA))); 1055 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1056 1057 return (status); 1058 } 1059 1060 /* 1061 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1062 * twice 1063 */ 1064 static int 1065 bfe_setupphy(struct bfe_softc *sc) 1066 { 1067 u_int32_t val; 1068 1069 /* Enable activity LED */ 1070 bfe_readphy(sc, 26, &val); 1071 bfe_writephy(sc, 26, val & 0x7fff); 1072 bfe_readphy(sc, 26, &val); 1073 1074 /* Enable traffic meter LED mode */ 1075 bfe_readphy(sc, 27, &val); 1076 bfe_writephy(sc, 27, val | (1 << 6)); 1077 1078 return (0); 1079 } 1080 1081 static void 1082 bfe_stats_update(struct bfe_softc *sc) 1083 { 1084 u_long reg; 1085 u_int32_t *val; 1086 1087 val = &sc->bfe_hwstats.tx_good_octets; 1088 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1089 *val++ += CSR_READ_4(sc, reg); 1090 } 1091 val = &sc->bfe_hwstats.rx_good_octets; 1092 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1093 *val++ += CSR_READ_4(sc, reg); 1094 } 1095 } 1096 1097 static void 1098 bfe_txeof(struct bfe_softc *sc) 1099 { 1100 struct ifnet *ifp; 1101 int i, chipidx; 1102 1103 BFE_LOCK_ASSERT(sc); 1104 1105 ifp = &sc->arpcom.ac_if; 1106 1107 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1108 chipidx /= sizeof(struct bfe_desc); 1109 1110 i = sc->bfe_tx_cons; 1111 /* Go through the mbufs and free those that have been transmitted */ 1112 while(i != chipidx) { 1113 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1114 if(r->bfe_mbuf != NULL) { 1115 ifp->if_opackets++; 1116 m_freem(r->bfe_mbuf); 1117 r->bfe_mbuf = NULL; 1118 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1119 } 1120 sc->bfe_tx_cnt--; 1121 BFE_INC(i, BFE_TX_LIST_CNT); 1122 } 1123 1124 if(i != sc->bfe_tx_cons) { 1125 /* we freed up some mbufs */ 1126 sc->bfe_tx_cons = i; 1127 ifp->if_flags &= ~IFF_OACTIVE; 1128 } 1129 if(sc->bfe_tx_cnt == 0) 1130 ifp->if_timer = 0; 1131 else 1132 ifp->if_timer = 5; 1133 } 1134 1135 /* Pass a received packet up the stack */ 1136 static void 1137 bfe_rxeof(struct bfe_softc *sc) 1138 { 1139 struct mbuf *m; 1140 struct ifnet *ifp; 1141 struct bfe_rxheader *rxheader; 1142 struct bfe_data *r; 1143 int cons; 1144 u_int32_t status, current, len, flags; 1145 1146 BFE_LOCK_ASSERT(sc); 1147 cons = sc->bfe_rx_cons; 1148 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1149 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1150 1151 ifp = &sc->arpcom.ac_if; 1152 1153 while(current != cons) { 1154 r = &sc->bfe_rx_ring[cons]; 1155 m = r->bfe_mbuf; 1156 rxheader = mtod(m, struct bfe_rxheader*); 1157 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1158 len = rxheader->len; 1159 r->bfe_mbuf = NULL; 1160 1161 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1162 flags = rxheader->flags; 1163 1164 len -= ETHER_CRC_LEN; 1165 1166 /* flag an error and try again */ 1167 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1168 ifp->if_ierrors++; 1169 if (flags & BFE_RX_FLAG_SERR) 1170 ifp->if_collisions++; 1171 bfe_list_newbuf(sc, cons, m); 1172 BFE_INC(cons, BFE_RX_LIST_CNT); 1173 continue; 1174 } 1175 1176 /* Go past the rx header */ 1177 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1178 m_adj(m, BFE_RX_OFFSET); 1179 m->m_len = m->m_pkthdr.len = len; 1180 } else { 1181 bfe_list_newbuf(sc, cons, m); 1182 ifp->if_ierrors++; 1183 BFE_INC(cons, BFE_RX_LIST_CNT); 1184 continue; 1185 } 1186 1187 ifp->if_ipackets++; 1188 m->m_pkthdr.rcvif = ifp; 1189 BFE_UNLOCK(sc); 1190 (*ifp->if_input)(ifp, m); 1191 BFE_LOCK(sc); 1192 1193 BFE_INC(cons, BFE_RX_LIST_CNT); 1194 } 1195 sc->bfe_rx_cons = cons; 1196 } 1197 1198 static void 1199 bfe_intr(void *xsc) 1200 { 1201 struct bfe_softc *sc = xsc; 1202 struct ifnet *ifp; 1203 u_int32_t istat, imask, flag; 1204 1205 ifp = &sc->arpcom.ac_if; 1206 1207 BFE_LOCK(sc); 1208 1209 istat = CSR_READ_4(sc, BFE_ISTAT); 1210 imask = CSR_READ_4(sc, BFE_IMASK); 1211 1212 /* 1213 * Defer unsolicited interrupts - This is necessary because setting the 1214 * chips interrupt mask register to 0 doesn't actually stop the 1215 * interrupts 1216 */ 1217 istat &= imask; 1218 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1219 CSR_READ_4(sc, BFE_ISTAT); 1220 1221 /* not expecting this interrupt, disregard it */ 1222 if(istat == 0) { 1223 BFE_UNLOCK(sc); 1224 return; 1225 } 1226 1227 if(istat & BFE_ISTAT_ERRORS) { 1228 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1229 if(flag & BFE_STAT_EMASK) 1230 ifp->if_oerrors++; 1231 1232 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1233 if(flag & BFE_RX_FLAG_ERRORS) 1234 ifp->if_ierrors++; 1235 1236 ifp->if_flags &= ~IFF_RUNNING; 1237 bfe_init_locked(sc); 1238 } 1239 1240 /* A packet was received */ 1241 if(istat & BFE_ISTAT_RX) 1242 bfe_rxeof(sc); 1243 1244 /* A packet was sent */ 1245 if(istat & BFE_ISTAT_TX) 1246 bfe_txeof(sc); 1247 1248 /* We have packets pending, fire them out */ 1249 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1250 bfe_start_locked(ifp); 1251 1252 BFE_UNLOCK(sc); 1253 } 1254 1255 static int 1256 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1257 { 1258 struct bfe_desc *d = NULL; 1259 struct bfe_data *r = NULL; 1260 struct mbuf *m; 1261 u_int32_t frag, cur, cnt = 0; 1262 int chainlen = 0; 1263 1264 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1265 return (ENOBUFS); 1266 1267 /* 1268 * Count the number of frags in this chain to see if 1269 * we need to m_defrag. Since the descriptor list is shared 1270 * by all packets, we'll m_defrag long chains so that they 1271 * do not use up the entire list, even if they would fit. 1272 */ 1273 for(m = m_head; m != NULL; m = m->m_next) 1274 chainlen++; 1275 1276 1277 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1278 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1279 m = m_defrag(m_head, M_DONTWAIT); 1280 if (m == NULL) 1281 return (ENOBUFS); 1282 m_head = m; 1283 } 1284 1285 /* 1286 * Start packing the mbufs in this chain into 1287 * the fragment pointers. Stop when we run out 1288 * of fragments or hit the end of the mbuf chain. 1289 */ 1290 m = m_head; 1291 cur = frag = *txidx; 1292 cnt = 0; 1293 1294 for(m = m_head; m != NULL; m = m->m_next) { 1295 if(m->m_len != 0) { 1296 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1297 return (ENOBUFS); 1298 1299 d = &sc->bfe_tx_list[cur]; 1300 r = &sc->bfe_tx_ring[cur]; 1301 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1302 /* always intterupt on completion */ 1303 d->bfe_ctrl |= BFE_DESC_IOC; 1304 if(cnt == 0) 1305 /* Set start of frame */ 1306 d->bfe_ctrl |= BFE_DESC_SOF; 1307 if(cur == BFE_TX_LIST_CNT - 1) 1308 /* 1309 * Tell the chip to wrap to the start of 1310 * the descriptor list 1311 */ 1312 d->bfe_ctrl |= BFE_DESC_EOT; 1313 1314 bus_dmamap_load(sc->bfe_tag, 1315 r->bfe_map, mtod(m, void*), m->m_len, 1316 bfe_dma_map_desc, d, 0); 1317 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1318 BUS_DMASYNC_PREREAD); 1319 1320 frag = cur; 1321 BFE_INC(cur, BFE_TX_LIST_CNT); 1322 cnt++; 1323 } 1324 } 1325 1326 if (m != NULL) 1327 return (ENOBUFS); 1328 1329 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1330 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1331 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1332 1333 *txidx = cur; 1334 sc->bfe_tx_cnt += cnt; 1335 return (0); 1336 } 1337 1338 /* 1339 * Set up to transmit a packet. 1340 */ 1341 static void 1342 bfe_start(struct ifnet *ifp) 1343 { 1344 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1345 bfe_start_locked(ifp); 1346 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1347 } 1348 1349 /* 1350 * Set up to transmit a packet. The softc is already locked. 1351 */ 1352 static void 1353 bfe_start_locked(struct ifnet *ifp) 1354 { 1355 struct bfe_softc *sc; 1356 struct mbuf *m_head = NULL; 1357 int idx, queued = 0; 1358 1359 sc = ifp->if_softc; 1360 idx = sc->bfe_tx_prod; 1361 1362 BFE_LOCK_ASSERT(sc); 1363 1364 /* 1365 * Not much point trying to send if the link is down 1366 * or we have nothing to send. 1367 */ 1368 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1369 return; 1370 1371 if (ifp->if_flags & IFF_OACTIVE) 1372 return; 1373 1374 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1375 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1376 if(m_head == NULL) 1377 break; 1378 1379 /* 1380 * Pack the data into the tx ring. If we dont have 1381 * enough room, let the chip drain the ring. 1382 */ 1383 if(bfe_encap(sc, m_head, &idx)) { 1384 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1385 ifp->if_flags |= IFF_OACTIVE; 1386 break; 1387 } 1388 1389 queued++; 1390 1391 /* 1392 * If there's a BPF listener, bounce a copy of this frame 1393 * to him. 1394 */ 1395 BPF_MTAP(ifp, m_head); 1396 } 1397 1398 if (queued) { 1399 sc->bfe_tx_prod = idx; 1400 /* Transmit - twice due to apparent hardware bug */ 1401 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1402 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1403 1404 /* 1405 * Set a timeout in case the chip goes out to lunch. 1406 */ 1407 ifp->if_timer = 5; 1408 } 1409 } 1410 1411 static void 1412 bfe_init(void *xsc) 1413 { 1414 BFE_LOCK((struct bfe_softc *)xsc); 1415 bfe_init_locked(xsc); 1416 BFE_UNLOCK((struct bfe_softc *)xsc); 1417 } 1418 1419 static void 1420 bfe_init_locked(void *xsc) 1421 { 1422 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1423 struct ifnet *ifp = &sc->arpcom.ac_if; 1424 1425 BFE_LOCK_ASSERT(sc); 1426 1427 if (ifp->if_flags & IFF_RUNNING) 1428 return; 1429 1430 bfe_stop(sc); 1431 bfe_chip_reset(sc); 1432 1433 if (bfe_list_rx_init(sc) == ENOBUFS) { 1434 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1435 sc->bfe_unit); 1436 bfe_stop(sc); 1437 return; 1438 } 1439 1440 bfe_set_rx_mode(sc); 1441 1442 /* Enable the chip and core */ 1443 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1444 /* Enable interrupts */ 1445 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1446 1447 bfe_ifmedia_upd(ifp); 1448 ifp->if_flags |= IFF_RUNNING; 1449 ifp->if_flags &= ~IFF_OACTIVE; 1450 1451 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1452 } 1453 1454 /* 1455 * Set media options. 1456 */ 1457 static int 1458 bfe_ifmedia_upd(struct ifnet *ifp) 1459 { 1460 struct bfe_softc *sc; 1461 struct mii_data *mii; 1462 1463 sc = ifp->if_softc; 1464 1465 mii = device_get_softc(sc->bfe_miibus); 1466 sc->bfe_link = 0; 1467 if (mii->mii_instance) { 1468 struct mii_softc *miisc; 1469 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1470 miisc = LIST_NEXT(miisc, mii_list)) 1471 mii_phy_reset(miisc); 1472 } 1473 mii_mediachg(mii); 1474 1475 return (0); 1476 } 1477 1478 /* 1479 * Report current media status. 1480 */ 1481 static void 1482 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1483 { 1484 struct bfe_softc *sc = ifp->if_softc; 1485 struct mii_data *mii; 1486 1487 mii = device_get_softc(sc->bfe_miibus); 1488 mii_pollstat(mii); 1489 ifmr->ifm_active = mii->mii_media_active; 1490 ifmr->ifm_status = mii->mii_media_status; 1491 } 1492 1493 static int 1494 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1495 { 1496 struct bfe_softc *sc = ifp->if_softc; 1497 struct ifreq *ifr = (struct ifreq *) data; 1498 struct mii_data *mii; 1499 int error = 0; 1500 1501 switch(command) { 1502 case SIOCSIFFLAGS: 1503 BFE_LOCK(sc); 1504 if(ifp->if_flags & IFF_UP) 1505 if(ifp->if_flags & IFF_RUNNING) 1506 bfe_set_rx_mode(sc); 1507 else 1508 bfe_init_locked(sc); 1509 else if(ifp->if_flags & IFF_RUNNING) 1510 bfe_stop(sc); 1511 BFE_UNLOCK(sc); 1512 break; 1513 case SIOCADDMULTI: 1514 case SIOCDELMULTI: 1515 BFE_LOCK(sc); 1516 if(ifp->if_flags & IFF_RUNNING) 1517 bfe_set_rx_mode(sc); 1518 BFE_UNLOCK(sc); 1519 break; 1520 case SIOCGIFMEDIA: 1521 case SIOCSIFMEDIA: 1522 mii = device_get_softc(sc->bfe_miibus); 1523 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1524 command); 1525 break; 1526 default: 1527 error = ether_ioctl(ifp, command, data); 1528 break; 1529 } 1530 1531 return (error); 1532 } 1533 1534 static void 1535 bfe_watchdog(struct ifnet *ifp) 1536 { 1537 struct bfe_softc *sc; 1538 1539 sc = ifp->if_softc; 1540 1541 BFE_LOCK(sc); 1542 1543 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1544 1545 ifp->if_flags &= ~IFF_RUNNING; 1546 bfe_init_locked(sc); 1547 1548 ifp->if_oerrors++; 1549 1550 BFE_UNLOCK(sc); 1551 } 1552 1553 static void 1554 bfe_tick(void *xsc) 1555 { 1556 struct bfe_softc *sc = xsc; 1557 struct mii_data *mii; 1558 1559 if (sc == NULL) 1560 return; 1561 1562 BFE_LOCK(sc); 1563 1564 mii = device_get_softc(sc->bfe_miibus); 1565 1566 bfe_stats_update(sc); 1567 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1568 1569 if(sc->bfe_link) { 1570 BFE_UNLOCK(sc); 1571 return; 1572 } 1573 1574 mii_tick(mii); 1575 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1576 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1577 sc->bfe_link++; 1578 1579 BFE_UNLOCK(sc); 1580 } 1581 1582 /* 1583 * Stop the adapter and free any mbufs allocated to the 1584 * RX and TX lists. 1585 */ 1586 static void 1587 bfe_stop(struct bfe_softc *sc) 1588 { 1589 struct ifnet *ifp; 1590 1591 BFE_LOCK_ASSERT(sc); 1592 1593 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1594 1595 ifp = &sc->arpcom.ac_if; 1596 1597 bfe_chip_halt(sc); 1598 bfe_tx_ring_free(sc); 1599 bfe_rx_ring_free(sc); 1600 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 } 1603