1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/if_vlan_var.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/bfe/if_bfereg.h> 62 63 MODULE_DEPEND(bfe, pci, 1, 1, 1); 64 MODULE_DEPEND(bfe, ether, 1, 1, 1); 65 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 66 67 /* "device miibus" required. See GENERIC if you get errors here. */ 68 #include "miibus_if.h" 69 70 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 71 72 static struct bfe_type bfe_devs[] = { 73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 74 "Broadcom BCM4401 Fast Ethernet" }, 75 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 76 "Broadcom BCM4401-B0 Fast Ethernet" }, 77 { 0, 0, NULL } 78 }; 79 80 static int bfe_probe (device_t); 81 static int bfe_attach (device_t); 82 static int bfe_detach (device_t); 83 static int bfe_suspend (device_t); 84 static int bfe_resume (device_t); 85 static void bfe_release_resources (struct bfe_softc *); 86 static void bfe_intr (void *); 87 static int bfe_encap (struct bfe_softc *, struct mbuf **); 88 static void bfe_start (struct ifnet *); 89 static void bfe_start_locked (struct ifnet *); 90 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 91 static void bfe_init (void *); 92 static void bfe_init_locked (void *); 93 static void bfe_stop (struct bfe_softc *); 94 static void bfe_watchdog (struct bfe_softc *); 95 static int bfe_shutdown (device_t); 96 static void bfe_tick (void *); 97 static void bfe_txeof (struct bfe_softc *); 98 static void bfe_rxeof (struct bfe_softc *); 99 static void bfe_set_rx_mode (struct bfe_softc *); 100 static int bfe_list_rx_init (struct bfe_softc *); 101 static void bfe_list_tx_init (struct bfe_softc *); 102 static void bfe_discard_buf (struct bfe_softc *, int); 103 static int bfe_list_newbuf (struct bfe_softc *, int); 104 static void bfe_rx_ring_free (struct bfe_softc *); 105 106 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 107 static int bfe_ifmedia_upd (struct ifnet *); 108 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 static int bfe_miibus_readreg (device_t, int, int); 110 static int bfe_miibus_writereg (device_t, int, int, int); 111 static void bfe_miibus_statchg (device_t); 112 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 113 u_long, const int); 114 static void bfe_get_config (struct bfe_softc *sc); 115 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 116 static void bfe_stats_update (struct bfe_softc *); 117 static void bfe_clear_stats (struct bfe_softc *); 118 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 119 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 120 static int bfe_resetphy (struct bfe_softc *); 121 static int bfe_setupphy (struct bfe_softc *); 122 static void bfe_chip_reset (struct bfe_softc *); 123 static void bfe_chip_halt (struct bfe_softc *); 124 static void bfe_core_reset (struct bfe_softc *); 125 static void bfe_core_disable (struct bfe_softc *); 126 static int bfe_dma_alloc (struct bfe_softc *); 127 static void bfe_dma_free (struct bfe_softc *sc); 128 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 129 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 130 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 DEVMETHOD(device_suspend, bfe_suspend), 139 DEVMETHOD(device_resume, bfe_resume), 140 141 /* MII interface */ 142 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 143 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 144 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 145 146 DEVMETHOD_END 147 }; 148 149 static driver_t bfe_driver = { 150 "bfe", 151 bfe_methods, 152 sizeof(struct bfe_softc) 153 }; 154 155 static devclass_t bfe_devclass; 156 157 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 158 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 159 160 /* 161 * Probe for a Broadcom 4401 chip. 162 */ 163 static int 164 bfe_probe(device_t dev) 165 { 166 struct bfe_type *t; 167 168 t = bfe_devs; 169 170 while (t->bfe_name != NULL) { 171 if (pci_get_vendor(dev) == t->bfe_vid && 172 pci_get_device(dev) == t->bfe_did) { 173 device_set_desc(dev, t->bfe_name); 174 return (BUS_PROBE_DEFAULT); 175 } 176 t++; 177 } 178 179 return (ENXIO); 180 } 181 182 struct bfe_dmamap_arg { 183 bus_addr_t bfe_busaddr; 184 }; 185 186 static int 187 bfe_dma_alloc(struct bfe_softc *sc) 188 { 189 struct bfe_dmamap_arg ctx; 190 struct bfe_rx_data *rd; 191 struct bfe_tx_data *td; 192 int error, i; 193 194 /* 195 * parent tag. Apparently the chip cannot handle any DMA address 196 * greater than 1GB. 197 */ 198 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 199 1, 0, /* alignment, boundary */ 200 BFE_DMA_MAXADDR, /* lowaddr */ 201 BUS_SPACE_MAXADDR, /* highaddr */ 202 NULL, NULL, /* filter, filterarg */ 203 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 204 0, /* nsegments */ 205 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 206 0, /* flags */ 207 NULL, NULL, /* lockfunc, lockarg */ 208 &sc->bfe_parent_tag); 209 if (error != 0) { 210 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 211 goto fail; 212 } 213 214 /* Create tag for Tx ring. */ 215 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 216 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 217 BUS_SPACE_MAXADDR, /* lowaddr */ 218 BUS_SPACE_MAXADDR, /* highaddr */ 219 NULL, NULL, /* filter, filterarg */ 220 BFE_TX_LIST_SIZE, /* maxsize */ 221 1, /* nsegments */ 222 BFE_TX_LIST_SIZE, /* maxsegsize */ 223 0, /* flags */ 224 NULL, NULL, /* lockfunc, lockarg */ 225 &sc->bfe_tx_tag); 226 if (error != 0) { 227 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 228 goto fail; 229 } 230 231 /* Create tag for Rx ring. */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 233 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 234 BUS_SPACE_MAXADDR, /* lowaddr */ 235 BUS_SPACE_MAXADDR, /* highaddr */ 236 NULL, NULL, /* filter, filterarg */ 237 BFE_RX_LIST_SIZE, /* maxsize */ 238 1, /* nsegments */ 239 BFE_RX_LIST_SIZE, /* maxsegsize */ 240 0, /* flags */ 241 NULL, NULL, /* lockfunc, lockarg */ 242 &sc->bfe_rx_tag); 243 if (error != 0) { 244 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 245 goto fail; 246 } 247 248 /* Create tag for Tx buffers. */ 249 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 250 1, 0, /* alignment, boundary */ 251 BUS_SPACE_MAXADDR, /* lowaddr */ 252 BUS_SPACE_MAXADDR, /* highaddr */ 253 NULL, NULL, /* filter, filterarg */ 254 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 255 BFE_MAXTXSEGS, /* nsegments */ 256 MCLBYTES, /* maxsegsize */ 257 0, /* flags */ 258 NULL, NULL, /* lockfunc, lockarg */ 259 &sc->bfe_txmbuf_tag); 260 if (error != 0) { 261 device_printf(sc->bfe_dev, 262 "cannot create Tx buffer DMA tag.\n"); 263 goto fail; 264 } 265 266 /* Create tag for Rx buffers. */ 267 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 268 1, 0, /* alignment, boundary */ 269 BUS_SPACE_MAXADDR, /* lowaddr */ 270 BUS_SPACE_MAXADDR, /* highaddr */ 271 NULL, NULL, /* filter, filterarg */ 272 MCLBYTES, /* maxsize */ 273 1, /* nsegments */ 274 MCLBYTES, /* maxsegsize */ 275 0, /* flags */ 276 NULL, NULL, /* lockfunc, lockarg */ 277 &sc->bfe_rxmbuf_tag); 278 if (error != 0) { 279 device_printf(sc->bfe_dev, 280 "cannot create Rx buffer DMA tag.\n"); 281 goto fail; 282 } 283 284 /* Allocate DMA'able memory and load DMA map. */ 285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 286 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 287 if (error != 0) { 288 device_printf(sc->bfe_dev, 289 "cannot allocate DMA'able memory for Tx ring.\n"); 290 goto fail; 291 } 292 ctx.bfe_busaddr = 0; 293 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 294 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 295 BUS_DMA_NOWAIT); 296 if (error != 0 || ctx.bfe_busaddr == 0) { 297 device_printf(sc->bfe_dev, 298 "cannot load DMA'able memory for Tx ring.\n"); 299 goto fail; 300 } 301 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 302 303 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 304 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 305 if (error != 0) { 306 device_printf(sc->bfe_dev, 307 "cannot allocate DMA'able memory for Rx ring.\n"); 308 goto fail; 309 } 310 ctx.bfe_busaddr = 0; 311 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 312 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 313 BUS_DMA_NOWAIT); 314 if (error != 0 || ctx.bfe_busaddr == 0) { 315 device_printf(sc->bfe_dev, 316 "cannot load DMA'able memory for Rx ring.\n"); 317 goto fail; 318 } 319 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 320 321 /* Create DMA maps for Tx buffers. */ 322 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 323 td = &sc->bfe_tx_ring[i]; 324 td->bfe_mbuf = NULL; 325 td->bfe_map = NULL; 326 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 327 if (error != 0) { 328 device_printf(sc->bfe_dev, 329 "cannot create DMA map for Tx.\n"); 330 goto fail; 331 } 332 } 333 334 /* Create spare DMA map for Rx buffers. */ 335 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 336 if (error != 0) { 337 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 338 goto fail; 339 } 340 /* Create DMA maps for Rx buffers. */ 341 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 342 rd = &sc->bfe_rx_ring[i]; 343 rd->bfe_mbuf = NULL; 344 rd->bfe_map = NULL; 345 rd->bfe_ctrl = 0; 346 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 347 if (error != 0) { 348 device_printf(sc->bfe_dev, 349 "cannot create DMA map for Rx.\n"); 350 goto fail; 351 } 352 } 353 354 fail: 355 return (error); 356 } 357 358 static void 359 bfe_dma_free(struct bfe_softc *sc) 360 { 361 struct bfe_tx_data *td; 362 struct bfe_rx_data *rd; 363 int i; 364 365 /* Tx ring. */ 366 if (sc->bfe_tx_tag != NULL) { 367 if (sc->bfe_tx_dma != 0) 368 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 369 if (sc->bfe_tx_list != NULL) 370 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 371 sc->bfe_tx_map); 372 sc->bfe_tx_dma = 0; 373 sc->bfe_tx_list = NULL; 374 bus_dma_tag_destroy(sc->bfe_tx_tag); 375 sc->bfe_tx_tag = NULL; 376 } 377 378 /* Rx ring. */ 379 if (sc->bfe_rx_tag != NULL) { 380 if (sc->bfe_rx_dma != 0) 381 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 382 if (sc->bfe_rx_list != NULL) 383 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 384 sc->bfe_rx_map); 385 sc->bfe_rx_dma = 0; 386 sc->bfe_rx_list = NULL; 387 bus_dma_tag_destroy(sc->bfe_rx_tag); 388 sc->bfe_rx_tag = NULL; 389 } 390 391 /* Tx buffers. */ 392 if (sc->bfe_txmbuf_tag != NULL) { 393 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 394 td = &sc->bfe_tx_ring[i]; 395 if (td->bfe_map != NULL) { 396 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 397 td->bfe_map); 398 td->bfe_map = NULL; 399 } 400 } 401 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 402 sc->bfe_txmbuf_tag = NULL; 403 } 404 405 /* Rx buffers. */ 406 if (sc->bfe_rxmbuf_tag != NULL) { 407 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 408 rd = &sc->bfe_rx_ring[i]; 409 if (rd->bfe_map != NULL) { 410 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 411 rd->bfe_map); 412 rd->bfe_map = NULL; 413 } 414 } 415 if (sc->bfe_rx_sparemap != NULL) { 416 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 417 sc->bfe_rx_sparemap); 418 sc->bfe_rx_sparemap = NULL; 419 } 420 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 421 sc->bfe_rxmbuf_tag = NULL; 422 } 423 424 if (sc->bfe_parent_tag != NULL) { 425 bus_dma_tag_destroy(sc->bfe_parent_tag); 426 sc->bfe_parent_tag = NULL; 427 } 428 } 429 430 static int 431 bfe_attach(device_t dev) 432 { 433 struct ifnet *ifp = NULL; 434 struct bfe_softc *sc; 435 int error = 0, rid; 436 437 sc = device_get_softc(dev); 438 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 439 MTX_DEF); 440 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 441 442 sc->bfe_dev = dev; 443 444 /* 445 * Map control/status registers. 446 */ 447 pci_enable_busmaster(dev); 448 449 rid = PCIR_BAR(0); 450 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 451 RF_ACTIVE); 452 if (sc->bfe_res == NULL) { 453 device_printf(dev, "couldn't map memory\n"); 454 error = ENXIO; 455 goto fail; 456 } 457 458 /* Allocate interrupt */ 459 rid = 0; 460 461 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 462 RF_SHAREABLE | RF_ACTIVE); 463 if (sc->bfe_irq == NULL) { 464 device_printf(dev, "couldn't map interrupt\n"); 465 error = ENXIO; 466 goto fail; 467 } 468 469 if (bfe_dma_alloc(sc) != 0) { 470 device_printf(dev, "failed to allocate DMA resources\n"); 471 error = ENXIO; 472 goto fail; 473 } 474 475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 476 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 477 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats, 478 "I", "Statistics"); 479 480 /* Set up ifnet structure */ 481 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 482 if (ifp == NULL) { 483 device_printf(dev, "failed to if_alloc()\n"); 484 error = ENOSPC; 485 goto fail; 486 } 487 ifp->if_softc = sc; 488 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 490 ifp->if_ioctl = bfe_ioctl; 491 ifp->if_start = bfe_start; 492 ifp->if_init = bfe_init; 493 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 494 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 495 IFQ_SET_READY(&ifp->if_snd); 496 497 bfe_get_config(sc); 498 499 /* Reset the chip and turn on the PHY */ 500 BFE_LOCK(sc); 501 bfe_chip_reset(sc); 502 BFE_UNLOCK(sc); 503 504 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 505 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 506 0); 507 if (error != 0) { 508 device_printf(dev, "attaching PHYs failed\n"); 509 goto fail; 510 } 511 512 ether_ifattach(ifp, sc->bfe_enaddr); 513 514 /* 515 * Tell the upper layer(s) we support long frames. 516 */ 517 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 518 ifp->if_capabilities |= IFCAP_VLAN_MTU; 519 ifp->if_capenable |= IFCAP_VLAN_MTU; 520 521 /* 522 * Hook interrupt last to avoid having to lock softc 523 */ 524 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 525 NULL, bfe_intr, sc, &sc->bfe_intrhand); 526 527 if (error) { 528 device_printf(dev, "couldn't set up irq\n"); 529 goto fail; 530 } 531 fail: 532 if (error != 0) 533 bfe_detach(dev); 534 return (error); 535 } 536 537 static int 538 bfe_detach(device_t dev) 539 { 540 struct bfe_softc *sc; 541 struct ifnet *ifp; 542 543 sc = device_get_softc(dev); 544 545 ifp = sc->bfe_ifp; 546 547 if (device_is_attached(dev)) { 548 BFE_LOCK(sc); 549 sc->bfe_flags |= BFE_FLAG_DETACH; 550 bfe_stop(sc); 551 BFE_UNLOCK(sc); 552 callout_drain(&sc->bfe_stat_co); 553 if (ifp != NULL) 554 ether_ifdetach(ifp); 555 } 556 557 BFE_LOCK(sc); 558 bfe_chip_reset(sc); 559 BFE_UNLOCK(sc); 560 561 bus_generic_detach(dev); 562 if (sc->bfe_miibus != NULL) 563 device_delete_child(dev, sc->bfe_miibus); 564 565 bfe_release_resources(sc); 566 bfe_dma_free(sc); 567 mtx_destroy(&sc->bfe_mtx); 568 569 return (0); 570 } 571 572 /* 573 * Stop all chip I/O so that the kernel's probe routines don't 574 * get confused by errant DMAs when rebooting. 575 */ 576 static int 577 bfe_shutdown(device_t dev) 578 { 579 struct bfe_softc *sc; 580 581 sc = device_get_softc(dev); 582 BFE_LOCK(sc); 583 bfe_stop(sc); 584 585 BFE_UNLOCK(sc); 586 587 return (0); 588 } 589 590 static int 591 bfe_suspend(device_t dev) 592 { 593 struct bfe_softc *sc; 594 595 sc = device_get_softc(dev); 596 BFE_LOCK(sc); 597 bfe_stop(sc); 598 BFE_UNLOCK(sc); 599 600 return (0); 601 } 602 603 static int 604 bfe_resume(device_t dev) 605 { 606 struct bfe_softc *sc; 607 struct ifnet *ifp; 608 609 sc = device_get_softc(dev); 610 ifp = sc->bfe_ifp; 611 BFE_LOCK(sc); 612 bfe_chip_reset(sc); 613 if (ifp->if_flags & IFF_UP) { 614 bfe_init_locked(sc); 615 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 616 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 617 bfe_start_locked(ifp); 618 } 619 BFE_UNLOCK(sc); 620 621 return (0); 622 } 623 624 static int 625 bfe_miibus_readreg(device_t dev, int phy, int reg) 626 { 627 struct bfe_softc *sc; 628 u_int32_t ret; 629 630 sc = device_get_softc(dev); 631 bfe_readphy(sc, reg, &ret); 632 633 return (ret); 634 } 635 636 static int 637 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 638 { 639 struct bfe_softc *sc; 640 641 sc = device_get_softc(dev); 642 bfe_writephy(sc, reg, val); 643 644 return (0); 645 } 646 647 static void 648 bfe_miibus_statchg(device_t dev) 649 { 650 struct bfe_softc *sc; 651 struct mii_data *mii; 652 u_int32_t val, flow; 653 654 sc = device_get_softc(dev); 655 mii = device_get_softc(sc->bfe_miibus); 656 657 sc->bfe_flags &= ~BFE_FLAG_LINK; 658 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 659 (IFM_ACTIVE | IFM_AVALID)) { 660 switch (IFM_SUBTYPE(mii->mii_media_active)) { 661 case IFM_10_T: 662 case IFM_100_TX: 663 sc->bfe_flags |= BFE_FLAG_LINK; 664 break; 665 default: 666 break; 667 } 668 } 669 670 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 671 val = CSR_READ_4(sc, BFE_TX_CTRL); 672 val &= ~BFE_TX_DUPLEX; 673 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 674 val |= BFE_TX_DUPLEX; 675 flow = 0; 676 #ifdef notyet 677 flow = CSR_READ_4(sc, BFE_RXCONF); 678 flow &= ~BFE_RXCONF_FLOW; 679 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 680 IFM_ETH_RXPAUSE) != 0) 681 flow |= BFE_RXCONF_FLOW; 682 CSR_WRITE_4(sc, BFE_RXCONF, flow); 683 /* 684 * It seems that the hardware has Tx pause issues 685 * so enable only Rx pause. 686 */ 687 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 688 flow &= ~BFE_FLOW_PAUSE_ENAB; 689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 690 #endif 691 } 692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 693 } 694 695 static void 696 bfe_tx_ring_free(struct bfe_softc *sc) 697 { 698 int i; 699 700 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 701 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 702 bus_dmamap_sync(sc->bfe_txmbuf_tag, 703 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 704 bus_dmamap_unload(sc->bfe_txmbuf_tag, 705 sc->bfe_tx_ring[i].bfe_map); 706 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 707 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 708 } 709 } 710 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 711 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 } 714 715 static void 716 bfe_rx_ring_free(struct bfe_softc *sc) 717 { 718 int i; 719 720 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 721 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 722 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 723 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 725 sc->bfe_rx_ring[i].bfe_map); 726 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 727 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 728 } 729 } 730 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 731 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 } 734 735 static int 736 bfe_list_rx_init(struct bfe_softc *sc) 737 { 738 struct bfe_rx_data *rd; 739 int i; 740 741 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 742 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 743 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 744 rd = &sc->bfe_rx_ring[i]; 745 rd->bfe_mbuf = NULL; 746 rd->bfe_ctrl = 0; 747 if (bfe_list_newbuf(sc, i) != 0) 748 return (ENOBUFS); 749 } 750 751 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 754 755 return (0); 756 } 757 758 static void 759 bfe_list_tx_init(struct bfe_softc *sc) 760 { 761 int i; 762 763 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 764 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 765 for (i = 0; i < BFE_TX_LIST_CNT; i++) 766 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 767 768 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 } 771 772 static void 773 bfe_discard_buf(struct bfe_softc *sc, int c) 774 { 775 struct bfe_rx_data *r; 776 struct bfe_desc *d; 777 778 r = &sc->bfe_rx_ring[c]; 779 d = &sc->bfe_rx_list[c]; 780 d->bfe_ctrl = htole32(r->bfe_ctrl); 781 } 782 783 static int 784 bfe_list_newbuf(struct bfe_softc *sc, int c) 785 { 786 struct bfe_rxheader *rx_header; 787 struct bfe_desc *d; 788 struct bfe_rx_data *r; 789 struct mbuf *m; 790 bus_dma_segment_t segs[1]; 791 bus_dmamap_t map; 792 u_int32_t ctrl; 793 int nsegs; 794 795 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 796 if (m == NULL) 797 return (ENOBUFS); 798 m->m_len = m->m_pkthdr.len = MCLBYTES; 799 800 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 801 m, segs, &nsegs, 0) != 0) { 802 m_freem(m); 803 return (ENOBUFS); 804 } 805 806 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 807 r = &sc->bfe_rx_ring[c]; 808 if (r->bfe_mbuf != NULL) { 809 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 810 BUS_DMASYNC_POSTREAD); 811 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 812 } 813 map = r->bfe_map; 814 r->bfe_map = sc->bfe_rx_sparemap; 815 sc->bfe_rx_sparemap = map; 816 r->bfe_mbuf = m; 817 818 rx_header = mtod(m, struct bfe_rxheader *); 819 rx_header->len = 0; 820 rx_header->flags = 0; 821 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 822 823 ctrl = segs[0].ds_len & BFE_DESC_LEN; 824 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 825 __func__, ctrl)); 826 if (c == BFE_RX_LIST_CNT - 1) 827 ctrl |= BFE_DESC_EOT; 828 r->bfe_ctrl = ctrl; 829 830 d = &sc->bfe_rx_list[c]; 831 d->bfe_ctrl = htole32(ctrl); 832 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 833 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 834 835 return (0); 836 } 837 838 static void 839 bfe_get_config(struct bfe_softc *sc) 840 { 841 u_int8_t eeprom[128]; 842 843 bfe_read_eeprom(sc, eeprom); 844 845 sc->bfe_enaddr[0] = eeprom[79]; 846 sc->bfe_enaddr[1] = eeprom[78]; 847 sc->bfe_enaddr[2] = eeprom[81]; 848 sc->bfe_enaddr[3] = eeprom[80]; 849 sc->bfe_enaddr[4] = eeprom[83]; 850 sc->bfe_enaddr[5] = eeprom[82]; 851 852 sc->bfe_phyaddr = eeprom[90] & 0x1f; 853 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 854 855 sc->bfe_core_unit = 0; 856 sc->bfe_dma_offset = BFE_PCI_DMA; 857 } 858 859 static void 860 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 861 { 862 u_int32_t bar_orig, pci_rev, val; 863 864 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 865 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 866 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 867 868 val = CSR_READ_4(sc, BFE_SBINTVEC); 869 val |= cores; 870 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 871 872 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 873 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 874 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 875 876 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 877 } 878 879 static void 880 bfe_clear_stats(struct bfe_softc *sc) 881 { 882 uint32_t reg; 883 884 BFE_LOCK_ASSERT(sc); 885 886 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 887 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 888 CSR_READ_4(sc, reg); 889 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 890 CSR_READ_4(sc, reg); 891 } 892 893 static int 894 bfe_resetphy(struct bfe_softc *sc) 895 { 896 u_int32_t val; 897 898 bfe_writephy(sc, 0, BMCR_RESET); 899 DELAY(100); 900 bfe_readphy(sc, 0, &val); 901 if (val & BMCR_RESET) { 902 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 903 return (ENXIO); 904 } 905 return (0); 906 } 907 908 static void 909 bfe_chip_halt(struct bfe_softc *sc) 910 { 911 BFE_LOCK_ASSERT(sc); 912 /* disable interrupts - not that it actually does..*/ 913 CSR_WRITE_4(sc, BFE_IMASK, 0); 914 CSR_READ_4(sc, BFE_IMASK); 915 916 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 917 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 918 919 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 920 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 921 DELAY(10); 922 } 923 924 static void 925 bfe_chip_reset(struct bfe_softc *sc) 926 { 927 u_int32_t val; 928 929 BFE_LOCK_ASSERT(sc); 930 931 /* Set the interrupt vector for the enet core */ 932 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 933 934 /* is core up? */ 935 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 936 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 937 if (val == BFE_CLOCK) { 938 /* It is, so shut it down */ 939 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 940 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 941 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 942 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 943 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 944 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 945 100, 0); 946 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 947 } 948 949 bfe_core_reset(sc); 950 bfe_clear_stats(sc); 951 952 /* 953 * We want the phy registers to be accessible even when 954 * the driver is "downed" so initialize MDC preamble, frequency, 955 * and whether internal or external phy here. 956 */ 957 958 /* 4402 has 62.5Mhz SB clock and internal phy */ 959 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 960 961 /* Internal or external PHY? */ 962 val = CSR_READ_4(sc, BFE_DEVCTRL); 963 if (!(val & BFE_IPP)) 964 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 965 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 966 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 967 DELAY(100); 968 } 969 970 /* Enable CRC32 generation and set proper LED modes */ 971 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 972 973 /* Reset or clear powerdown control bit */ 974 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 975 976 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 977 BFE_LAZY_FC_MASK)); 978 979 /* 980 * We don't want lazy interrupts, so just send them at 981 * the end of a frame, please 982 */ 983 BFE_OR(sc, BFE_RCV_LAZY, 0); 984 985 /* Set max lengths, accounting for VLAN tags */ 986 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 987 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 988 989 /* Set watermark XXX - magic */ 990 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 991 992 /* 993 * Initialise DMA channels 994 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 995 */ 996 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 997 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 998 999 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 1000 BFE_RX_CTRL_ENABLE); 1001 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1002 1003 bfe_resetphy(sc); 1004 bfe_setupphy(sc); 1005 } 1006 1007 static void 1008 bfe_core_disable(struct bfe_softc *sc) 1009 { 1010 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1011 return; 1012 1013 /* 1014 * Set reject, wait for it set, then wait for the core to stop 1015 * being busy, then set reset and reject and enable the clocks. 1016 */ 1017 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1018 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1019 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1020 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1021 BFE_RESET)); 1022 CSR_READ_4(sc, BFE_SBTMSLOW); 1023 DELAY(10); 1024 /* Leave reset and reject set */ 1025 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1026 DELAY(10); 1027 } 1028 1029 static void 1030 bfe_core_reset(struct bfe_softc *sc) 1031 { 1032 u_int32_t val; 1033 1034 /* Disable the core */ 1035 bfe_core_disable(sc); 1036 1037 /* and bring it back up */ 1038 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1039 CSR_READ_4(sc, BFE_SBTMSLOW); 1040 DELAY(10); 1041 1042 /* Chip bug, clear SERR, IB and TO if they are set. */ 1043 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1044 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1045 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1046 if (val & (BFE_IBE | BFE_TO)) 1047 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1048 1049 /* Clear reset and allow it to move through the core */ 1050 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1051 CSR_READ_4(sc, BFE_SBTMSLOW); 1052 DELAY(10); 1053 1054 /* Leave the clock set */ 1055 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1056 CSR_READ_4(sc, BFE_SBTMSLOW); 1057 DELAY(10); 1058 } 1059 1060 static void 1061 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1062 { 1063 u_int32_t val; 1064 1065 val = ((u_int32_t) data[2]) << 24; 1066 val |= ((u_int32_t) data[3]) << 16; 1067 val |= ((u_int32_t) data[4]) << 8; 1068 val |= ((u_int32_t) data[5]); 1069 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1070 val = (BFE_CAM_HI_VALID | 1071 (((u_int32_t) data[0]) << 8) | 1072 (((u_int32_t) data[1]))); 1073 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1074 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1075 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1076 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1077 } 1078 1079 static void 1080 bfe_set_rx_mode(struct bfe_softc *sc) 1081 { 1082 struct ifnet *ifp = sc->bfe_ifp; 1083 struct ifmultiaddr *ifma; 1084 u_int32_t val; 1085 int i = 0; 1086 1087 BFE_LOCK_ASSERT(sc); 1088 1089 val = CSR_READ_4(sc, BFE_RXCONF); 1090 1091 if (ifp->if_flags & IFF_PROMISC) 1092 val |= BFE_RXCONF_PROMISC; 1093 else 1094 val &= ~BFE_RXCONF_PROMISC; 1095 1096 if (ifp->if_flags & IFF_BROADCAST) 1097 val &= ~BFE_RXCONF_DBCAST; 1098 else 1099 val |= BFE_RXCONF_DBCAST; 1100 1101 1102 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1103 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1104 1105 if (ifp->if_flags & IFF_ALLMULTI) 1106 val |= BFE_RXCONF_ALLMULTI; 1107 else { 1108 val &= ~BFE_RXCONF_ALLMULTI; 1109 if_maddr_rlock(ifp); 1110 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1111 if (ifma->ifma_addr->sa_family != AF_LINK) 1112 continue; 1113 bfe_cam_write(sc, 1114 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1115 } 1116 if_maddr_runlock(ifp); 1117 } 1118 1119 CSR_WRITE_4(sc, BFE_RXCONF, val); 1120 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1121 } 1122 1123 static void 1124 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1125 { 1126 struct bfe_dmamap_arg *ctx; 1127 1128 if (error != 0) 1129 return; 1130 1131 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1132 1133 ctx = (struct bfe_dmamap_arg *)arg; 1134 ctx->bfe_busaddr = segs[0].ds_addr; 1135 } 1136 1137 static void 1138 bfe_release_resources(struct bfe_softc *sc) 1139 { 1140 1141 if (sc->bfe_intrhand != NULL) 1142 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1143 1144 if (sc->bfe_irq != NULL) 1145 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1146 1147 if (sc->bfe_res != NULL) 1148 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1149 sc->bfe_res); 1150 1151 if (sc->bfe_ifp != NULL) 1152 if_free(sc->bfe_ifp); 1153 } 1154 1155 static void 1156 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1157 { 1158 long i; 1159 u_int16_t *ptr = (u_int16_t *)data; 1160 1161 for(i = 0; i < 128; i += 2) 1162 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1163 } 1164 1165 static int 1166 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1167 u_long timeout, const int clear) 1168 { 1169 u_long i; 1170 1171 for (i = 0; i < timeout; i++) { 1172 u_int32_t val = CSR_READ_4(sc, reg); 1173 1174 if (clear && !(val & bit)) 1175 break; 1176 if (!clear && (val & bit)) 1177 break; 1178 DELAY(10); 1179 } 1180 if (i == timeout) { 1181 device_printf(sc->bfe_dev, 1182 "BUG! Timeout waiting for bit %08x of register " 1183 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1184 return (-1); 1185 } 1186 return (0); 1187 } 1188 1189 static int 1190 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1191 { 1192 int err; 1193 1194 /* Clear MII ISR */ 1195 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1196 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1197 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1198 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1199 (reg << BFE_MDIO_RA_SHIFT) | 1200 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1201 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1202 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1203 1204 return (err); 1205 } 1206 1207 static int 1208 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1209 { 1210 int status; 1211 1212 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1213 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1214 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1215 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1216 (reg << BFE_MDIO_RA_SHIFT) | 1217 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1218 (val & BFE_MDIO_DATA_DATA))); 1219 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1220 1221 return (status); 1222 } 1223 1224 /* 1225 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1226 * twice 1227 */ 1228 static int 1229 bfe_setupphy(struct bfe_softc *sc) 1230 { 1231 u_int32_t val; 1232 1233 /* Enable activity LED */ 1234 bfe_readphy(sc, 26, &val); 1235 bfe_writephy(sc, 26, val & 0x7fff); 1236 bfe_readphy(sc, 26, &val); 1237 1238 /* Enable traffic meter LED mode */ 1239 bfe_readphy(sc, 27, &val); 1240 bfe_writephy(sc, 27, val | (1 << 6)); 1241 1242 return (0); 1243 } 1244 1245 static void 1246 bfe_stats_update(struct bfe_softc *sc) 1247 { 1248 struct bfe_hw_stats *stats; 1249 struct ifnet *ifp; 1250 uint32_t mib[BFE_MIB_CNT]; 1251 uint32_t reg, *val; 1252 1253 BFE_LOCK_ASSERT(sc); 1254 1255 val = mib; 1256 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 1257 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1258 *val++ = CSR_READ_4(sc, reg); 1259 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1260 *val++ = CSR_READ_4(sc, reg); 1261 1262 ifp = sc->bfe_ifp; 1263 stats = &sc->bfe_stats; 1264 /* Tx stat. */ 1265 stats->tx_good_octets += mib[MIB_TX_GOOD_O]; 1266 stats->tx_good_frames += mib[MIB_TX_GOOD_P]; 1267 stats->tx_octets += mib[MIB_TX_O]; 1268 stats->tx_frames += mib[MIB_TX_P]; 1269 stats->tx_bcast_frames += mib[MIB_TX_BCAST]; 1270 stats->tx_mcast_frames += mib[MIB_TX_MCAST]; 1271 stats->tx_pkts_64 += mib[MIB_TX_64]; 1272 stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; 1273 stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; 1274 stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; 1275 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; 1276 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; 1277 stats->tx_jabbers += mib[MIB_TX_JABBER]; 1278 stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; 1279 stats->tx_frag_frames += mib[MIB_TX_FRAG]; 1280 stats->tx_underruns += mib[MIB_TX_URUNS]; 1281 stats->tx_colls += mib[MIB_TX_TCOLS]; 1282 stats->tx_single_colls += mib[MIB_TX_SCOLS]; 1283 stats->tx_multi_colls += mib[MIB_TX_MCOLS]; 1284 stats->tx_excess_colls += mib[MIB_TX_ECOLS]; 1285 stats->tx_late_colls += mib[MIB_TX_LCOLS]; 1286 stats->tx_deferrals += mib[MIB_TX_DEFERED]; 1287 stats->tx_carrier_losts += mib[MIB_TX_CLOST]; 1288 stats->tx_pause_frames += mib[MIB_TX_PAUSE]; 1289 /* Rx stat. */ 1290 stats->rx_good_octets += mib[MIB_RX_GOOD_O]; 1291 stats->rx_good_frames += mib[MIB_RX_GOOD_P]; 1292 stats->rx_octets += mib[MIB_RX_O]; 1293 stats->rx_frames += mib[MIB_RX_P]; 1294 stats->rx_bcast_frames += mib[MIB_RX_BCAST]; 1295 stats->rx_mcast_frames += mib[MIB_RX_MCAST]; 1296 stats->rx_pkts_64 += mib[MIB_RX_64]; 1297 stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; 1298 stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; 1299 stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; 1300 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; 1301 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; 1302 stats->rx_jabbers += mib[MIB_RX_JABBER]; 1303 stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; 1304 stats->rx_frag_frames += mib[MIB_RX_FRAG]; 1305 stats->rx_missed_frames += mib[MIB_RX_MISS]; 1306 stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; 1307 stats->rx_runts += mib[MIB_RX_USIZE]; 1308 stats->rx_crc_errs += mib[MIB_RX_CRC]; 1309 stats->rx_align_errs += mib[MIB_RX_ALIGN]; 1310 stats->rx_symbol_errs += mib[MIB_RX_SYM]; 1311 stats->rx_pause_frames += mib[MIB_RX_PAUSE]; 1312 stats->rx_control_frames += mib[MIB_RX_NPAUSE]; 1313 1314 /* Update counters in ifnet. */ 1315 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]); 1316 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]); 1317 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] + 1318 (u_long)mib[MIB_TX_ECOLS] + 1319 (u_long)mib[MIB_TX_DEFERED] + 1320 (u_long)mib[MIB_TX_CLOST]); 1321 1322 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]); 1323 1324 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] + 1325 mib[MIB_RX_MISS] + 1326 mib[MIB_RX_CRCA] + 1327 mib[MIB_RX_USIZE] + 1328 mib[MIB_RX_CRC] + 1329 mib[MIB_RX_ALIGN] + 1330 mib[MIB_RX_SYM]); 1331 } 1332 1333 static void 1334 bfe_txeof(struct bfe_softc *sc) 1335 { 1336 struct bfe_tx_data *r; 1337 struct ifnet *ifp; 1338 int i, chipidx; 1339 1340 BFE_LOCK_ASSERT(sc); 1341 1342 ifp = sc->bfe_ifp; 1343 1344 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1345 chipidx /= sizeof(struct bfe_desc); 1346 1347 i = sc->bfe_tx_cons; 1348 if (i == chipidx) 1349 return; 1350 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1352 /* Go through the mbufs and free those that have been transmitted */ 1353 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1354 r = &sc->bfe_tx_ring[i]; 1355 sc->bfe_tx_cnt--; 1356 if (r->bfe_mbuf == NULL) 1357 continue; 1358 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1359 BUS_DMASYNC_POSTWRITE); 1360 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1361 1362 m_freem(r->bfe_mbuf); 1363 r->bfe_mbuf = NULL; 1364 } 1365 1366 if (i != sc->bfe_tx_cons) { 1367 /* we freed up some mbufs */ 1368 sc->bfe_tx_cons = i; 1369 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1370 } 1371 1372 if (sc->bfe_tx_cnt == 0) 1373 sc->bfe_watchdog_timer = 0; 1374 } 1375 1376 /* Pass a received packet up the stack */ 1377 static void 1378 bfe_rxeof(struct bfe_softc *sc) 1379 { 1380 struct mbuf *m; 1381 struct ifnet *ifp; 1382 struct bfe_rxheader *rxheader; 1383 struct bfe_rx_data *r; 1384 int cons, prog; 1385 u_int32_t status, current, len, flags; 1386 1387 BFE_LOCK_ASSERT(sc); 1388 cons = sc->bfe_rx_cons; 1389 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1390 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1391 1392 ifp = sc->bfe_ifp; 1393 1394 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1395 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1396 1397 for (prog = 0; current != cons; prog++, 1398 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1399 r = &sc->bfe_rx_ring[cons]; 1400 m = r->bfe_mbuf; 1401 /* 1402 * Rx status should be read from mbuf such that we can't 1403 * delay bus_dmamap_sync(9). This hardware limiation 1404 * results in inefficent mbuf usage as bfe(4) couldn't 1405 * reuse mapped buffer from errored frame. 1406 */ 1407 if (bfe_list_newbuf(sc, cons) != 0) { 1408 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1409 bfe_discard_buf(sc, cons); 1410 continue; 1411 } 1412 rxheader = mtod(m, struct bfe_rxheader*); 1413 len = le16toh(rxheader->len); 1414 flags = le16toh(rxheader->flags); 1415 1416 /* Remove CRC bytes. */ 1417 len -= ETHER_CRC_LEN; 1418 1419 /* flag an error and try again */ 1420 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1421 m_freem(m); 1422 continue; 1423 } 1424 1425 /* Make sure to skip header bytes written by hardware. */ 1426 m_adj(m, BFE_RX_OFFSET); 1427 m->m_len = m->m_pkthdr.len = len; 1428 1429 m->m_pkthdr.rcvif = ifp; 1430 BFE_UNLOCK(sc); 1431 (*ifp->if_input)(ifp, m); 1432 BFE_LOCK(sc); 1433 } 1434 1435 if (prog > 0) { 1436 sc->bfe_rx_cons = cons; 1437 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1438 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1439 } 1440 } 1441 1442 static void 1443 bfe_intr(void *xsc) 1444 { 1445 struct bfe_softc *sc = xsc; 1446 struct ifnet *ifp; 1447 u_int32_t istat; 1448 1449 ifp = sc->bfe_ifp; 1450 1451 BFE_LOCK(sc); 1452 1453 istat = CSR_READ_4(sc, BFE_ISTAT); 1454 1455 /* 1456 * Defer unsolicited interrupts - This is necessary because setting the 1457 * chips interrupt mask register to 0 doesn't actually stop the 1458 * interrupts 1459 */ 1460 istat &= BFE_IMASK_DEF; 1461 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1462 CSR_READ_4(sc, BFE_ISTAT); 1463 1464 /* not expecting this interrupt, disregard it */ 1465 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1466 BFE_UNLOCK(sc); 1467 return; 1468 } 1469 1470 /* A packet was received */ 1471 if (istat & BFE_ISTAT_RX) 1472 bfe_rxeof(sc); 1473 1474 /* A packet was sent */ 1475 if (istat & BFE_ISTAT_TX) 1476 bfe_txeof(sc); 1477 1478 if (istat & BFE_ISTAT_ERRORS) { 1479 1480 if (istat & BFE_ISTAT_DSCE) { 1481 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1482 bfe_stop(sc); 1483 BFE_UNLOCK(sc); 1484 return; 1485 } 1486 1487 if (istat & BFE_ISTAT_DPE) { 1488 device_printf(sc->bfe_dev, 1489 "Descriptor Protocol Error\n"); 1490 bfe_stop(sc); 1491 BFE_UNLOCK(sc); 1492 return; 1493 } 1494 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1495 bfe_init_locked(sc); 1496 } 1497 1498 /* We have packets pending, fire them out */ 1499 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1500 bfe_start_locked(ifp); 1501 1502 BFE_UNLOCK(sc); 1503 } 1504 1505 static int 1506 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1507 { 1508 struct bfe_desc *d; 1509 struct bfe_tx_data *r, *r1; 1510 struct mbuf *m; 1511 bus_dmamap_t map; 1512 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1513 uint32_t cur, si; 1514 int error, i, nsegs; 1515 1516 BFE_LOCK_ASSERT(sc); 1517 1518 M_ASSERTPKTHDR((*m_head)); 1519 1520 si = cur = sc->bfe_tx_prod; 1521 r = &sc->bfe_tx_ring[cur]; 1522 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1523 txsegs, &nsegs, 0); 1524 if (error == EFBIG) { 1525 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); 1526 if (m == NULL) { 1527 m_freem(*m_head); 1528 *m_head = NULL; 1529 return (ENOMEM); 1530 } 1531 *m_head = m; 1532 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1533 *m_head, txsegs, &nsegs, 0); 1534 if (error != 0) { 1535 m_freem(*m_head); 1536 *m_head = NULL; 1537 return (error); 1538 } 1539 } else if (error != 0) 1540 return (error); 1541 if (nsegs == 0) { 1542 m_freem(*m_head); 1543 *m_head = NULL; 1544 return (EIO); 1545 } 1546 1547 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1548 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1549 return (ENOBUFS); 1550 } 1551 1552 for (i = 0; i < nsegs; i++) { 1553 d = &sc->bfe_tx_list[cur]; 1554 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1555 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1556 if (cur == BFE_TX_LIST_CNT - 1) 1557 /* 1558 * Tell the chip to wrap to the start of 1559 * the descriptor list. 1560 */ 1561 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1562 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1563 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1564 BFE_PCI_DMA); 1565 BFE_INC(cur, BFE_TX_LIST_CNT); 1566 } 1567 1568 /* Update producer index. */ 1569 sc->bfe_tx_prod = cur; 1570 1571 /* Set EOF on the last descriptor. */ 1572 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1573 d = &sc->bfe_tx_list[cur]; 1574 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1575 1576 /* Lastly set SOF on the first descriptor to avoid races. */ 1577 d = &sc->bfe_tx_list[si]; 1578 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1579 1580 r1 = &sc->bfe_tx_ring[cur]; 1581 map = r->bfe_map; 1582 r->bfe_map = r1->bfe_map; 1583 r1->bfe_map = map; 1584 r1->bfe_mbuf = *m_head; 1585 sc->bfe_tx_cnt += nsegs; 1586 1587 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1588 1589 return (0); 1590 } 1591 1592 /* 1593 * Set up to transmit a packet. 1594 */ 1595 static void 1596 bfe_start(struct ifnet *ifp) 1597 { 1598 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1599 bfe_start_locked(ifp); 1600 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1601 } 1602 1603 /* 1604 * Set up to transmit a packet. The softc is already locked. 1605 */ 1606 static void 1607 bfe_start_locked(struct ifnet *ifp) 1608 { 1609 struct bfe_softc *sc; 1610 struct mbuf *m_head; 1611 int queued; 1612 1613 sc = ifp->if_softc; 1614 1615 BFE_LOCK_ASSERT(sc); 1616 1617 /* 1618 * Not much point trying to send if the link is down 1619 * or we have nothing to send. 1620 */ 1621 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1622 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1623 return; 1624 1625 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1626 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1627 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1628 if (m_head == NULL) 1629 break; 1630 1631 /* 1632 * Pack the data into the tx ring. If we dont have 1633 * enough room, let the chip drain the ring. 1634 */ 1635 if (bfe_encap(sc, &m_head)) { 1636 if (m_head == NULL) 1637 break; 1638 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1639 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1640 break; 1641 } 1642 1643 queued++; 1644 1645 /* 1646 * If there's a BPF listener, bounce a copy of this frame 1647 * to him. 1648 */ 1649 BPF_MTAP(ifp, m_head); 1650 } 1651 1652 if (queued) { 1653 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1654 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1655 /* Transmit - twice due to apparent hardware bug */ 1656 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1657 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1658 /* 1659 * XXX It seems the following write is not necessary 1660 * to kick Tx command. What might be required would be 1661 * a way flushing PCI posted write. Reading the register 1662 * back ensures the flush operation. In addition, 1663 * hardware will execute PCI posted write in the long 1664 * run and watchdog timer for the kick command was set 1665 * to 5 seconds. Therefore I think the second write 1666 * access is not necessary or could be replaced with 1667 * read operation. 1668 */ 1669 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1670 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1671 1672 /* 1673 * Set a timeout in case the chip goes out to lunch. 1674 */ 1675 sc->bfe_watchdog_timer = 5; 1676 } 1677 } 1678 1679 static void 1680 bfe_init(void *xsc) 1681 { 1682 BFE_LOCK((struct bfe_softc *)xsc); 1683 bfe_init_locked(xsc); 1684 BFE_UNLOCK((struct bfe_softc *)xsc); 1685 } 1686 1687 static void 1688 bfe_init_locked(void *xsc) 1689 { 1690 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1691 struct ifnet *ifp = sc->bfe_ifp; 1692 struct mii_data *mii; 1693 1694 BFE_LOCK_ASSERT(sc); 1695 1696 mii = device_get_softc(sc->bfe_miibus); 1697 1698 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1699 return; 1700 1701 bfe_stop(sc); 1702 bfe_chip_reset(sc); 1703 1704 if (bfe_list_rx_init(sc) == ENOBUFS) { 1705 device_printf(sc->bfe_dev, 1706 "%s: Not enough memory for list buffers\n", __func__); 1707 bfe_stop(sc); 1708 return; 1709 } 1710 bfe_list_tx_init(sc); 1711 1712 bfe_set_rx_mode(sc); 1713 1714 /* Enable the chip and core */ 1715 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1716 /* Enable interrupts */ 1717 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1718 1719 /* Clear link state and change media. */ 1720 sc->bfe_flags &= ~BFE_FLAG_LINK; 1721 mii_mediachg(mii); 1722 1723 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1724 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1725 1726 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1727 } 1728 1729 /* 1730 * Set media options. 1731 */ 1732 static int 1733 bfe_ifmedia_upd(struct ifnet *ifp) 1734 { 1735 struct bfe_softc *sc; 1736 struct mii_data *mii; 1737 struct mii_softc *miisc; 1738 int error; 1739 1740 sc = ifp->if_softc; 1741 BFE_LOCK(sc); 1742 1743 mii = device_get_softc(sc->bfe_miibus); 1744 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1745 PHY_RESET(miisc); 1746 error = mii_mediachg(mii); 1747 BFE_UNLOCK(sc); 1748 1749 return (error); 1750 } 1751 1752 /* 1753 * Report current media status. 1754 */ 1755 static void 1756 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1757 { 1758 struct bfe_softc *sc = ifp->if_softc; 1759 struct mii_data *mii; 1760 1761 BFE_LOCK(sc); 1762 mii = device_get_softc(sc->bfe_miibus); 1763 mii_pollstat(mii); 1764 ifmr->ifm_active = mii->mii_media_active; 1765 ifmr->ifm_status = mii->mii_media_status; 1766 BFE_UNLOCK(sc); 1767 } 1768 1769 static int 1770 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1771 { 1772 struct bfe_softc *sc = ifp->if_softc; 1773 struct ifreq *ifr = (struct ifreq *) data; 1774 struct mii_data *mii; 1775 int error = 0; 1776 1777 switch (command) { 1778 case SIOCSIFFLAGS: 1779 BFE_LOCK(sc); 1780 if (ifp->if_flags & IFF_UP) { 1781 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1782 bfe_set_rx_mode(sc); 1783 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1784 bfe_init_locked(sc); 1785 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1786 bfe_stop(sc); 1787 BFE_UNLOCK(sc); 1788 break; 1789 case SIOCADDMULTI: 1790 case SIOCDELMULTI: 1791 BFE_LOCK(sc); 1792 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1793 bfe_set_rx_mode(sc); 1794 BFE_UNLOCK(sc); 1795 break; 1796 case SIOCGIFMEDIA: 1797 case SIOCSIFMEDIA: 1798 mii = device_get_softc(sc->bfe_miibus); 1799 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1800 break; 1801 default: 1802 error = ether_ioctl(ifp, command, data); 1803 break; 1804 } 1805 1806 return (error); 1807 } 1808 1809 static void 1810 bfe_watchdog(struct bfe_softc *sc) 1811 { 1812 struct ifnet *ifp; 1813 1814 BFE_LOCK_ASSERT(sc); 1815 1816 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1817 return; 1818 1819 ifp = sc->bfe_ifp; 1820 1821 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1822 1823 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1825 bfe_init_locked(sc); 1826 1827 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1828 bfe_start_locked(ifp); 1829 } 1830 1831 static void 1832 bfe_tick(void *xsc) 1833 { 1834 struct bfe_softc *sc = xsc; 1835 struct mii_data *mii; 1836 1837 BFE_LOCK_ASSERT(sc); 1838 1839 mii = device_get_softc(sc->bfe_miibus); 1840 mii_tick(mii); 1841 bfe_stats_update(sc); 1842 bfe_watchdog(sc); 1843 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1844 } 1845 1846 /* 1847 * Stop the adapter and free any mbufs allocated to the 1848 * RX and TX lists. 1849 */ 1850 static void 1851 bfe_stop(struct bfe_softc *sc) 1852 { 1853 struct ifnet *ifp; 1854 1855 BFE_LOCK_ASSERT(sc); 1856 1857 ifp = sc->bfe_ifp; 1858 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1859 sc->bfe_flags &= ~BFE_FLAG_LINK; 1860 callout_stop(&sc->bfe_stat_co); 1861 sc->bfe_watchdog_timer = 0; 1862 1863 bfe_chip_halt(sc); 1864 bfe_tx_ring_free(sc); 1865 bfe_rx_ring_free(sc); 1866 } 1867 1868 static int 1869 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS) 1870 { 1871 struct bfe_softc *sc; 1872 struct bfe_hw_stats *stats; 1873 int error, result; 1874 1875 result = -1; 1876 error = sysctl_handle_int(oidp, &result, 0, req); 1877 1878 if (error != 0 || req->newptr == NULL) 1879 return (error); 1880 1881 if (result != 1) 1882 return (error); 1883 1884 sc = (struct bfe_softc *)arg1; 1885 stats = &sc->bfe_stats; 1886 1887 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); 1888 printf("Transmit good octets : %ju\n", 1889 (uintmax_t)stats->tx_good_octets); 1890 printf("Transmit good frames : %ju\n", 1891 (uintmax_t)stats->tx_good_frames); 1892 printf("Transmit octets : %ju\n", 1893 (uintmax_t)stats->tx_octets); 1894 printf("Transmit frames : %ju\n", 1895 (uintmax_t)stats->tx_frames); 1896 printf("Transmit broadcast frames : %ju\n", 1897 (uintmax_t)stats->tx_bcast_frames); 1898 printf("Transmit multicast frames : %ju\n", 1899 (uintmax_t)stats->tx_mcast_frames); 1900 printf("Transmit frames 64 bytes : %ju\n", 1901 (uint64_t)stats->tx_pkts_64); 1902 printf("Transmit frames 65 to 127 bytes : %ju\n", 1903 (uint64_t)stats->tx_pkts_65_127); 1904 printf("Transmit frames 128 to 255 bytes : %ju\n", 1905 (uint64_t)stats->tx_pkts_128_255); 1906 printf("Transmit frames 256 to 511 bytes : %ju\n", 1907 (uint64_t)stats->tx_pkts_256_511); 1908 printf("Transmit frames 512 to 1023 bytes : %ju\n", 1909 (uint64_t)stats->tx_pkts_512_1023); 1910 printf("Transmit frames 1024 to max bytes : %ju\n", 1911 (uint64_t)stats->tx_pkts_1024_max); 1912 printf("Transmit jabber errors : %u\n", stats->tx_jabbers); 1913 printf("Transmit oversized frames : %ju\n", 1914 (uint64_t)stats->tx_oversize_frames); 1915 printf("Transmit fragmented frames : %ju\n", 1916 (uint64_t)stats->tx_frag_frames); 1917 printf("Transmit underruns : %u\n", stats->tx_colls); 1918 printf("Transmit total collisions : %u\n", stats->tx_single_colls); 1919 printf("Transmit single collisions : %u\n", stats->tx_single_colls); 1920 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); 1921 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); 1922 printf("Transmit late collisions : %u\n", stats->tx_late_colls); 1923 printf("Transmit deferrals : %u\n", stats->tx_deferrals); 1924 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); 1925 printf("Transmit pause frames : %u\n", stats->tx_pause_frames); 1926 1927 printf("Receive good octets : %ju\n", 1928 (uintmax_t)stats->rx_good_octets); 1929 printf("Receive good frames : %ju\n", 1930 (uintmax_t)stats->rx_good_frames); 1931 printf("Receive octets : %ju\n", 1932 (uintmax_t)stats->rx_octets); 1933 printf("Receive frames : %ju\n", 1934 (uintmax_t)stats->rx_frames); 1935 printf("Receive broadcast frames : %ju\n", 1936 (uintmax_t)stats->rx_bcast_frames); 1937 printf("Receive multicast frames : %ju\n", 1938 (uintmax_t)stats->rx_mcast_frames); 1939 printf("Receive frames 64 bytes : %ju\n", 1940 (uint64_t)stats->rx_pkts_64); 1941 printf("Receive frames 65 to 127 bytes : %ju\n", 1942 (uint64_t)stats->rx_pkts_65_127); 1943 printf("Receive frames 128 to 255 bytes : %ju\n", 1944 (uint64_t)stats->rx_pkts_128_255); 1945 printf("Receive frames 256 to 511 bytes : %ju\n", 1946 (uint64_t)stats->rx_pkts_256_511); 1947 printf("Receive frames 512 to 1023 bytes : %ju\n", 1948 (uint64_t)stats->rx_pkts_512_1023); 1949 printf("Receive frames 1024 to max bytes : %ju\n", 1950 (uint64_t)stats->rx_pkts_1024_max); 1951 printf("Receive jabber errors : %u\n", stats->rx_jabbers); 1952 printf("Receive oversized frames : %ju\n", 1953 (uint64_t)stats->rx_oversize_frames); 1954 printf("Receive fragmented frames : %ju\n", 1955 (uint64_t)stats->rx_frag_frames); 1956 printf("Receive missed frames : %u\n", stats->rx_missed_frames); 1957 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); 1958 printf("Receive undersized frames : %u\n", stats->rx_runts); 1959 printf("Receive CRC errors : %u\n", stats->rx_crc_errs); 1960 printf("Receive align errors : %u\n", stats->rx_align_errs); 1961 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); 1962 printf("Receive pause frames : %u\n", stats->rx_pause_frames); 1963 printf("Receive control frames : %u\n", stats->rx_control_frames); 1964 1965 return (error); 1966 } 1967