1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp = NULL; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 354 355 /* Allocate interrupt */ 356 rid = 0; 357 358 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 359 RF_SHAREABLE | RF_ACTIVE); 360 if (sc->bfe_irq == NULL) { 361 printf("bfe%d: couldn't map interrupt\n", unit); 362 error = ENXIO; 363 goto fail; 364 } 365 366 if (bfe_dma_alloc(dev)) { 367 printf("bfe%d: failed to allocate DMA resources\n", 368 sc->bfe_unit); 369 bfe_release_resources(sc); 370 error = ENXIO; 371 goto fail; 372 } 373 374 /* Set up ifnet structure */ 375 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 376 if (ifp == NULL) { 377 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 378 error = ENOSPC; 379 goto fail; 380 } 381 ifp->if_softc = sc; 382 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_ioctl = bfe_ioctl; 385 ifp->if_start = bfe_start; 386 ifp->if_watchdog = bfe_watchdog; 387 ifp->if_init = bfe_init; 388 ifp->if_mtu = ETHERMTU; 389 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 390 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 bfe_get_config(sc); 394 395 /* Reset the chip and turn on the PHY */ 396 BFE_LOCK(sc); 397 bfe_chip_reset(sc); 398 BFE_UNLOCK(sc); 399 400 if (mii_phy_probe(dev, &sc->bfe_miibus, 401 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 402 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 403 error = ENXIO; 404 goto fail; 405 } 406 407 ether_ifattach(ifp, sc->bfe_enaddr); 408 callout_handle_init(&sc->bfe_stat_ch); 409 410 /* 411 * Tell the upper layer(s) we support long frames. 412 */ 413 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 414 ifp->if_capabilities |= IFCAP_VLAN_MTU; 415 ifp->if_capenable |= IFCAP_VLAN_MTU; 416 417 /* 418 * Hook interrupt last to avoid having to lock softc 419 */ 420 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 421 bfe_intr, sc, &sc->bfe_intrhand); 422 423 if (error) { 424 bfe_release_resources(sc); 425 printf("bfe%d: couldn't set up irq\n", unit); 426 goto fail; 427 } 428 fail: 429 if (error) 430 bfe_release_resources(sc); 431 return (error); 432 } 433 434 static int 435 bfe_detach(device_t dev) 436 { 437 struct bfe_softc *sc; 438 struct ifnet *ifp; 439 440 sc = device_get_softc(dev); 441 442 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 443 BFE_LOCK(sc); 444 445 ifp = sc->bfe_ifp; 446 447 if (device_is_attached(dev)) { 448 bfe_stop(sc); 449 ether_ifdetach(ifp); 450 } 451 452 bfe_chip_reset(sc); 453 454 bus_generic_detach(dev); 455 if(sc->bfe_miibus != NULL) 456 device_delete_child(dev, sc->bfe_miibus); 457 458 bfe_release_resources(sc); 459 BFE_UNLOCK(sc); 460 mtx_destroy(&sc->bfe_mtx); 461 462 return (0); 463 } 464 465 /* 466 * Stop all chip I/O so that the kernel's probe routines don't 467 * get confused by errant DMAs when rebooting. 468 */ 469 static void 470 bfe_shutdown(device_t dev) 471 { 472 struct bfe_softc *sc; 473 474 sc = device_get_softc(dev); 475 BFE_LOCK(sc); 476 bfe_stop(sc); 477 478 BFE_UNLOCK(sc); 479 return; 480 } 481 482 static int 483 bfe_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct bfe_softc *sc; 486 u_int32_t ret; 487 488 sc = device_get_softc(dev); 489 if(phy != sc->bfe_phyaddr) 490 return (0); 491 bfe_readphy(sc, reg, &ret); 492 493 return (ret); 494 } 495 496 static int 497 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 498 { 499 struct bfe_softc *sc; 500 501 sc = device_get_softc(dev); 502 if(phy != sc->bfe_phyaddr) 503 return (0); 504 bfe_writephy(sc, reg, val); 505 506 return (0); 507 } 508 509 static void 510 bfe_miibus_statchg(device_t dev) 511 { 512 return; 513 } 514 515 static void 516 bfe_tx_ring_free(struct bfe_softc *sc) 517 { 518 int i; 519 520 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 521 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 522 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 523 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 524 bus_dmamap_unload(sc->bfe_tag, 525 sc->bfe_tx_ring[i].bfe_map); 526 } 527 } 528 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 529 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 530 } 531 532 static void 533 bfe_rx_ring_free(struct bfe_softc *sc) 534 { 535 int i; 536 537 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 538 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 539 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 540 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 541 bus_dmamap_unload(sc->bfe_tag, 542 sc->bfe_rx_ring[i].bfe_map); 543 } 544 } 545 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 546 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 547 } 548 549 static int 550 bfe_list_rx_init(struct bfe_softc *sc) 551 { 552 int i; 553 554 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 555 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 556 return (ENOBUFS); 557 } 558 559 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 560 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 561 562 sc->bfe_rx_cons = 0; 563 564 return (0); 565 } 566 567 static int 568 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 569 { 570 struct bfe_rxheader *rx_header; 571 struct bfe_desc *d; 572 struct bfe_data *r; 573 u_int32_t ctrl; 574 575 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 576 return (EINVAL); 577 578 if(m == NULL) { 579 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 580 if(m == NULL) 581 return (ENOBUFS); 582 m->m_len = m->m_pkthdr.len = MCLBYTES; 583 } 584 else 585 m->m_data = m->m_ext.ext_buf; 586 587 rx_header = mtod(m, struct bfe_rxheader *); 588 rx_header->len = 0; 589 rx_header->flags = 0; 590 591 /* Map the mbuf into DMA */ 592 sc->bfe_rx_cnt = c; 593 d = &sc->bfe_rx_list[c]; 594 r = &sc->bfe_rx_ring[c]; 595 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 596 MCLBYTES, bfe_dma_map_desc, d, 0); 597 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 598 599 ctrl = ETHER_MAX_LEN + 32; 600 601 if(c == BFE_RX_LIST_CNT - 1) 602 ctrl |= BFE_DESC_EOT; 603 604 d->bfe_ctrl = ctrl; 605 r->bfe_mbuf = m; 606 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 607 return (0); 608 } 609 610 static void 611 bfe_get_config(struct bfe_softc *sc) 612 { 613 u_int8_t eeprom[128]; 614 615 bfe_read_eeprom(sc, eeprom); 616 617 sc->bfe_enaddr[0] = eeprom[79]; 618 sc->bfe_enaddr[1] = eeprom[78]; 619 sc->bfe_enaddr[2] = eeprom[81]; 620 sc->bfe_enaddr[3] = eeprom[80]; 621 sc->bfe_enaddr[4] = eeprom[83]; 622 sc->bfe_enaddr[5] = eeprom[82]; 623 624 sc->bfe_phyaddr = eeprom[90] & 0x1f; 625 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 626 627 sc->bfe_core_unit = 0; 628 sc->bfe_dma_offset = BFE_PCI_DMA; 629 } 630 631 static void 632 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 633 { 634 u_int32_t bar_orig, pci_rev, val; 635 636 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 637 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 638 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 639 640 val = CSR_READ_4(sc, BFE_SBINTVEC); 641 val |= cores; 642 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 643 644 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 645 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 646 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 647 648 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 649 } 650 651 static void 652 bfe_clear_stats(struct bfe_softc *sc) 653 { 654 u_long reg; 655 656 BFE_LOCK_ASSERT(sc); 657 658 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 659 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 660 CSR_READ_4(sc, reg); 661 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 662 CSR_READ_4(sc, reg); 663 } 664 665 static int 666 bfe_resetphy(struct bfe_softc *sc) 667 { 668 u_int32_t val; 669 670 bfe_writephy(sc, 0, BMCR_RESET); 671 DELAY(100); 672 bfe_readphy(sc, 0, &val); 673 if (val & BMCR_RESET) { 674 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 675 return (ENXIO); 676 } 677 return (0); 678 } 679 680 static void 681 bfe_chip_halt(struct bfe_softc *sc) 682 { 683 BFE_LOCK_ASSERT(sc); 684 /* disable interrupts - not that it actually does..*/ 685 CSR_WRITE_4(sc, BFE_IMASK, 0); 686 CSR_READ_4(sc, BFE_IMASK); 687 688 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 689 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 690 691 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 692 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 693 DELAY(10); 694 } 695 696 static void 697 bfe_chip_reset(struct bfe_softc *sc) 698 { 699 u_int32_t val; 700 701 BFE_LOCK_ASSERT(sc); 702 703 /* Set the interrupt vector for the enet core */ 704 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 705 706 /* is core up? */ 707 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 708 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 709 if (val == BFE_CLOCK) { 710 /* It is, so shut it down */ 711 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 712 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 713 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 714 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 715 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 716 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 717 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 718 100, 0); 719 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 720 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 721 } 722 723 bfe_core_reset(sc); 724 bfe_clear_stats(sc); 725 726 /* 727 * We want the phy registers to be accessible even when 728 * the driver is "downed" so initialize MDC preamble, frequency, 729 * and whether internal or external phy here. 730 */ 731 732 /* 4402 has 62.5Mhz SB clock and internal phy */ 733 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 734 735 /* Internal or external PHY? */ 736 val = CSR_READ_4(sc, BFE_DEVCTRL); 737 if(!(val & BFE_IPP)) 738 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 739 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 740 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 741 DELAY(100); 742 } 743 744 /* Enable CRC32 generation and set proper LED modes */ 745 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 746 747 /* Reset or clear powerdown control bit */ 748 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 749 750 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 751 BFE_LAZY_FC_MASK)); 752 753 /* 754 * We don't want lazy interrupts, so just send them at 755 * the end of a frame, please 756 */ 757 BFE_OR(sc, BFE_RCV_LAZY, 0); 758 759 /* Set max lengths, accounting for VLAN tags */ 760 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 761 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 762 763 /* Set watermark XXX - magic */ 764 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 765 766 /* 767 * Initialise DMA channels 768 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 769 */ 770 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 771 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 772 773 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 774 BFE_RX_CTRL_ENABLE); 775 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 776 777 bfe_resetphy(sc); 778 bfe_setupphy(sc); 779 } 780 781 static void 782 bfe_core_disable(struct bfe_softc *sc) 783 { 784 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 785 return; 786 787 /* 788 * Set reject, wait for it set, then wait for the core to stop 789 * being busy, then set reset and reject and enable the clocks. 790 */ 791 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 792 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 793 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 795 BFE_RESET)); 796 CSR_READ_4(sc, BFE_SBTMSLOW); 797 DELAY(10); 798 /* Leave reset and reject set */ 799 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 800 DELAY(10); 801 } 802 803 static void 804 bfe_core_reset(struct bfe_softc *sc) 805 { 806 u_int32_t val; 807 808 /* Disable the core */ 809 bfe_core_disable(sc); 810 811 /* and bring it back up */ 812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 813 CSR_READ_4(sc, BFE_SBTMSLOW); 814 DELAY(10); 815 816 /* Chip bug, clear SERR, IB and TO if they are set. */ 817 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 818 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 819 val = CSR_READ_4(sc, BFE_SBIMSTATE); 820 if (val & (BFE_IBE | BFE_TO)) 821 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 822 823 /* Clear reset and allow it to move through the core */ 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 825 CSR_READ_4(sc, BFE_SBTMSLOW); 826 DELAY(10); 827 828 /* Leave the clock set */ 829 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 830 CSR_READ_4(sc, BFE_SBTMSLOW); 831 DELAY(10); 832 } 833 834 static void 835 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 836 { 837 u_int32_t val; 838 839 val = ((u_int32_t) data[2]) << 24; 840 val |= ((u_int32_t) data[3]) << 16; 841 val |= ((u_int32_t) data[4]) << 8; 842 val |= ((u_int32_t) data[5]); 843 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 844 val = (BFE_CAM_HI_VALID | 845 (((u_int32_t) data[0]) << 8) | 846 (((u_int32_t) data[1]))); 847 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 848 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 849 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 850 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 851 } 852 853 static void 854 bfe_set_rx_mode(struct bfe_softc *sc) 855 { 856 struct ifnet *ifp = sc->bfe_ifp; 857 struct ifmultiaddr *ifma; 858 u_int32_t val; 859 int i = 0; 860 861 val = CSR_READ_4(sc, BFE_RXCONF); 862 863 if (ifp->if_flags & IFF_PROMISC) 864 val |= BFE_RXCONF_PROMISC; 865 else 866 val &= ~BFE_RXCONF_PROMISC; 867 868 if (ifp->if_flags & IFF_BROADCAST) 869 val &= ~BFE_RXCONF_DBCAST; 870 else 871 val |= BFE_RXCONF_DBCAST; 872 873 874 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 875 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 876 877 if (ifp->if_flags & IFF_ALLMULTI) 878 val |= BFE_RXCONF_ALLMULTI; 879 else { 880 val &= ~BFE_RXCONF_ALLMULTI; 881 IF_ADDR_LOCK(ifp); 882 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 883 if (ifma->ifma_addr->sa_family != AF_LINK) 884 continue; 885 bfe_cam_write(sc, 886 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 887 } 888 IF_ADDR_UNLOCK(ifp); 889 } 890 891 CSR_WRITE_4(sc, BFE_RXCONF, val); 892 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 893 } 894 895 static void 896 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 897 { 898 u_int32_t *ptr; 899 900 ptr = arg; 901 *ptr = segs->ds_addr; 902 } 903 904 static void 905 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 906 { 907 struct bfe_desc *d; 908 909 d = arg; 910 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 911 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 912 } 913 914 static void 915 bfe_release_resources(struct bfe_softc *sc) 916 { 917 device_t dev; 918 int i; 919 920 dev = sc->bfe_dev; 921 922 if (sc->bfe_vpd_prodname != NULL) 923 free(sc->bfe_vpd_prodname, M_DEVBUF); 924 925 if (sc->bfe_vpd_readonly != NULL) 926 free(sc->bfe_vpd_readonly, M_DEVBUF); 927 928 if (sc->bfe_intrhand != NULL) 929 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 930 931 if (sc->bfe_irq != NULL) 932 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 933 934 if (sc->bfe_res != NULL) 935 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 936 937 if (sc->bfe_ifp != NULL) 938 if_free(sc->bfe_ifp); 939 940 if(sc->bfe_tx_tag != NULL) { 941 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 942 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 943 sc->bfe_tx_map); 944 bus_dma_tag_destroy(sc->bfe_tx_tag); 945 sc->bfe_tx_tag = NULL; 946 } 947 948 if(sc->bfe_rx_tag != NULL) { 949 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 950 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 951 sc->bfe_rx_map); 952 bus_dma_tag_destroy(sc->bfe_rx_tag); 953 sc->bfe_rx_tag = NULL; 954 } 955 956 if(sc->bfe_tag != NULL) { 957 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 958 bus_dmamap_destroy(sc->bfe_tag, 959 sc->bfe_tx_ring[i].bfe_map); 960 } 961 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 962 bus_dmamap_destroy(sc->bfe_tag, 963 sc->bfe_rx_ring[i].bfe_map); 964 } 965 bus_dma_tag_destroy(sc->bfe_tag); 966 sc->bfe_tag = NULL; 967 } 968 969 if(sc->bfe_parent_tag != NULL) 970 bus_dma_tag_destroy(sc->bfe_parent_tag); 971 972 return; 973 } 974 975 static void 976 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 977 { 978 long i; 979 u_int16_t *ptr = (u_int16_t *)data; 980 981 for(i = 0; i < 128; i += 2) 982 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 983 } 984 985 static int 986 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 987 u_long timeout, const int clear) 988 { 989 u_long i; 990 991 for (i = 0; i < timeout; i++) { 992 u_int32_t val = CSR_READ_4(sc, reg); 993 994 if (clear && !(val & bit)) 995 break; 996 if (!clear && (val & bit)) 997 break; 998 DELAY(10); 999 } 1000 if (i == timeout) { 1001 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1002 "%x to %s.\n", sc->bfe_unit, bit, reg, 1003 (clear ? "clear" : "set")); 1004 return (-1); 1005 } 1006 return (0); 1007 } 1008 1009 static int 1010 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1011 { 1012 int err; 1013 1014 /* Clear MII ISR */ 1015 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1016 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1017 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1018 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1019 (reg << BFE_MDIO_RA_SHIFT) | 1020 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1021 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1022 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1023 1024 return (err); 1025 } 1026 1027 static int 1028 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1029 { 1030 int status; 1031 1032 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1033 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1034 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1035 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1036 (reg << BFE_MDIO_RA_SHIFT) | 1037 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1038 (val & BFE_MDIO_DATA_DATA))); 1039 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1040 1041 return (status); 1042 } 1043 1044 /* 1045 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1046 * twice 1047 */ 1048 static int 1049 bfe_setupphy(struct bfe_softc *sc) 1050 { 1051 u_int32_t val; 1052 1053 /* Enable activity LED */ 1054 bfe_readphy(sc, 26, &val); 1055 bfe_writephy(sc, 26, val & 0x7fff); 1056 bfe_readphy(sc, 26, &val); 1057 1058 /* Enable traffic meter LED mode */ 1059 bfe_readphy(sc, 27, &val); 1060 bfe_writephy(sc, 27, val | (1 << 6)); 1061 1062 return (0); 1063 } 1064 1065 static void 1066 bfe_stats_update(struct bfe_softc *sc) 1067 { 1068 u_long reg; 1069 u_int32_t *val; 1070 1071 val = &sc->bfe_hwstats.tx_good_octets; 1072 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1073 *val++ += CSR_READ_4(sc, reg); 1074 } 1075 val = &sc->bfe_hwstats.rx_good_octets; 1076 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1077 *val++ += CSR_READ_4(sc, reg); 1078 } 1079 } 1080 1081 static void 1082 bfe_txeof(struct bfe_softc *sc) 1083 { 1084 struct ifnet *ifp; 1085 int i, chipidx; 1086 1087 BFE_LOCK_ASSERT(sc); 1088 1089 ifp = sc->bfe_ifp; 1090 1091 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1092 chipidx /= sizeof(struct bfe_desc); 1093 1094 i = sc->bfe_tx_cons; 1095 /* Go through the mbufs and free those that have been transmitted */ 1096 while(i != chipidx) { 1097 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1098 if(r->bfe_mbuf != NULL) { 1099 ifp->if_opackets++; 1100 m_freem(r->bfe_mbuf); 1101 r->bfe_mbuf = NULL; 1102 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1103 } 1104 sc->bfe_tx_cnt--; 1105 BFE_INC(i, BFE_TX_LIST_CNT); 1106 } 1107 1108 if(i != sc->bfe_tx_cons) { 1109 /* we freed up some mbufs */ 1110 sc->bfe_tx_cons = i; 1111 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1112 } 1113 if(sc->bfe_tx_cnt == 0) 1114 ifp->if_timer = 0; 1115 else 1116 ifp->if_timer = 5; 1117 } 1118 1119 /* Pass a received packet up the stack */ 1120 static void 1121 bfe_rxeof(struct bfe_softc *sc) 1122 { 1123 struct mbuf *m; 1124 struct ifnet *ifp; 1125 struct bfe_rxheader *rxheader; 1126 struct bfe_data *r; 1127 int cons; 1128 u_int32_t status, current, len, flags; 1129 1130 BFE_LOCK_ASSERT(sc); 1131 cons = sc->bfe_rx_cons; 1132 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1133 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1134 1135 ifp = sc->bfe_ifp; 1136 1137 while(current != cons) { 1138 r = &sc->bfe_rx_ring[cons]; 1139 m = r->bfe_mbuf; 1140 rxheader = mtod(m, struct bfe_rxheader*); 1141 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1142 len = rxheader->len; 1143 r->bfe_mbuf = NULL; 1144 1145 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1146 flags = rxheader->flags; 1147 1148 len -= ETHER_CRC_LEN; 1149 1150 /* flag an error and try again */ 1151 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1152 ifp->if_ierrors++; 1153 if (flags & BFE_RX_FLAG_SERR) 1154 ifp->if_collisions++; 1155 bfe_list_newbuf(sc, cons, m); 1156 BFE_INC(cons, BFE_RX_LIST_CNT); 1157 continue; 1158 } 1159 1160 /* Go past the rx header */ 1161 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1162 m_adj(m, BFE_RX_OFFSET); 1163 m->m_len = m->m_pkthdr.len = len; 1164 } else { 1165 bfe_list_newbuf(sc, cons, m); 1166 ifp->if_ierrors++; 1167 BFE_INC(cons, BFE_RX_LIST_CNT); 1168 continue; 1169 } 1170 1171 ifp->if_ipackets++; 1172 m->m_pkthdr.rcvif = ifp; 1173 BFE_UNLOCK(sc); 1174 (*ifp->if_input)(ifp, m); 1175 BFE_LOCK(sc); 1176 1177 BFE_INC(cons, BFE_RX_LIST_CNT); 1178 } 1179 sc->bfe_rx_cons = cons; 1180 } 1181 1182 static void 1183 bfe_intr(void *xsc) 1184 { 1185 struct bfe_softc *sc = xsc; 1186 struct ifnet *ifp; 1187 u_int32_t istat, imask, flag; 1188 1189 ifp = sc->bfe_ifp; 1190 1191 BFE_LOCK(sc); 1192 1193 istat = CSR_READ_4(sc, BFE_ISTAT); 1194 imask = CSR_READ_4(sc, BFE_IMASK); 1195 1196 /* 1197 * Defer unsolicited interrupts - This is necessary because setting the 1198 * chips interrupt mask register to 0 doesn't actually stop the 1199 * interrupts 1200 */ 1201 istat &= imask; 1202 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1203 CSR_READ_4(sc, BFE_ISTAT); 1204 1205 /* not expecting this interrupt, disregard it */ 1206 if(istat == 0) { 1207 BFE_UNLOCK(sc); 1208 return; 1209 } 1210 1211 if(istat & BFE_ISTAT_ERRORS) { 1212 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1213 if(flag & BFE_STAT_EMASK) 1214 ifp->if_oerrors++; 1215 1216 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1217 if(flag & BFE_RX_FLAG_ERRORS) 1218 ifp->if_ierrors++; 1219 1220 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1221 bfe_init_locked(sc); 1222 } 1223 1224 /* A packet was received */ 1225 if(istat & BFE_ISTAT_RX) 1226 bfe_rxeof(sc); 1227 1228 /* A packet was sent */ 1229 if(istat & BFE_ISTAT_TX) 1230 bfe_txeof(sc); 1231 1232 /* We have packets pending, fire them out */ 1233 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1234 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1235 bfe_start_locked(ifp); 1236 1237 BFE_UNLOCK(sc); 1238 } 1239 1240 static int 1241 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1242 { 1243 struct bfe_desc *d = NULL; 1244 struct bfe_data *r = NULL; 1245 struct mbuf *m; 1246 u_int32_t frag, cur, cnt = 0; 1247 int chainlen = 0; 1248 1249 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1250 return (ENOBUFS); 1251 1252 /* 1253 * Count the number of frags in this chain to see if 1254 * we need to m_defrag. Since the descriptor list is shared 1255 * by all packets, we'll m_defrag long chains so that they 1256 * do not use up the entire list, even if they would fit. 1257 */ 1258 for(m = m_head; m != NULL; m = m->m_next) 1259 chainlen++; 1260 1261 1262 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1263 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1264 m = m_defrag(m_head, M_DONTWAIT); 1265 if (m == NULL) 1266 return (ENOBUFS); 1267 m_head = m; 1268 } 1269 1270 /* 1271 * Start packing the mbufs in this chain into 1272 * the fragment pointers. Stop when we run out 1273 * of fragments or hit the end of the mbuf chain. 1274 */ 1275 m = m_head; 1276 cur = frag = *txidx; 1277 cnt = 0; 1278 1279 for(m = m_head; m != NULL; m = m->m_next) { 1280 if(m->m_len != 0) { 1281 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1282 return (ENOBUFS); 1283 1284 d = &sc->bfe_tx_list[cur]; 1285 r = &sc->bfe_tx_ring[cur]; 1286 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1287 /* always intterupt on completion */ 1288 d->bfe_ctrl |= BFE_DESC_IOC; 1289 if(cnt == 0) 1290 /* Set start of frame */ 1291 d->bfe_ctrl |= BFE_DESC_SOF; 1292 if(cur == BFE_TX_LIST_CNT - 1) 1293 /* 1294 * Tell the chip to wrap to the start of 1295 * the descriptor list 1296 */ 1297 d->bfe_ctrl |= BFE_DESC_EOT; 1298 1299 bus_dmamap_load(sc->bfe_tag, 1300 r->bfe_map, mtod(m, void*), m->m_len, 1301 bfe_dma_map_desc, d, 0); 1302 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1303 BUS_DMASYNC_PREREAD); 1304 1305 frag = cur; 1306 BFE_INC(cur, BFE_TX_LIST_CNT); 1307 cnt++; 1308 } 1309 } 1310 1311 if (m != NULL) 1312 return (ENOBUFS); 1313 1314 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1315 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1316 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1317 1318 *txidx = cur; 1319 sc->bfe_tx_cnt += cnt; 1320 return (0); 1321 } 1322 1323 /* 1324 * Set up to transmit a packet. 1325 */ 1326 static void 1327 bfe_start(struct ifnet *ifp) 1328 { 1329 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1330 bfe_start_locked(ifp); 1331 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1332 } 1333 1334 /* 1335 * Set up to transmit a packet. The softc is already locked. 1336 */ 1337 static void 1338 bfe_start_locked(struct ifnet *ifp) 1339 { 1340 struct bfe_softc *sc; 1341 struct mbuf *m_head = NULL; 1342 int idx, queued = 0; 1343 1344 sc = ifp->if_softc; 1345 idx = sc->bfe_tx_prod; 1346 1347 BFE_LOCK_ASSERT(sc); 1348 1349 /* 1350 * Not much point trying to send if the link is down 1351 * or we have nothing to send. 1352 */ 1353 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1354 return; 1355 1356 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1357 return; 1358 1359 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1360 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1361 if(m_head == NULL) 1362 break; 1363 1364 /* 1365 * Pack the data into the tx ring. If we dont have 1366 * enough room, let the chip drain the ring. 1367 */ 1368 if(bfe_encap(sc, m_head, &idx)) { 1369 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1370 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1371 break; 1372 } 1373 1374 queued++; 1375 1376 /* 1377 * If there's a BPF listener, bounce a copy of this frame 1378 * to him. 1379 */ 1380 BPF_MTAP(ifp, m_head); 1381 } 1382 1383 if (queued) { 1384 sc->bfe_tx_prod = idx; 1385 /* Transmit - twice due to apparent hardware bug */ 1386 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1387 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1388 1389 /* 1390 * Set a timeout in case the chip goes out to lunch. 1391 */ 1392 ifp->if_timer = 5; 1393 } 1394 } 1395 1396 static void 1397 bfe_init(void *xsc) 1398 { 1399 BFE_LOCK((struct bfe_softc *)xsc); 1400 bfe_init_locked(xsc); 1401 BFE_UNLOCK((struct bfe_softc *)xsc); 1402 } 1403 1404 static void 1405 bfe_init_locked(void *xsc) 1406 { 1407 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1408 struct ifnet *ifp = sc->bfe_ifp; 1409 1410 BFE_LOCK_ASSERT(sc); 1411 1412 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1413 return; 1414 1415 bfe_stop(sc); 1416 bfe_chip_reset(sc); 1417 1418 if (bfe_list_rx_init(sc) == ENOBUFS) { 1419 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1420 sc->bfe_unit); 1421 bfe_stop(sc); 1422 return; 1423 } 1424 1425 bfe_set_rx_mode(sc); 1426 1427 /* Enable the chip and core */ 1428 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1429 /* Enable interrupts */ 1430 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1431 1432 bfe_ifmedia_upd(ifp); 1433 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1434 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1435 1436 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1437 } 1438 1439 /* 1440 * Set media options. 1441 */ 1442 static int 1443 bfe_ifmedia_upd(struct ifnet *ifp) 1444 { 1445 struct bfe_softc *sc; 1446 struct mii_data *mii; 1447 1448 sc = ifp->if_softc; 1449 1450 mii = device_get_softc(sc->bfe_miibus); 1451 sc->bfe_link = 0; 1452 if (mii->mii_instance) { 1453 struct mii_softc *miisc; 1454 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1455 miisc = LIST_NEXT(miisc, mii_list)) 1456 mii_phy_reset(miisc); 1457 } 1458 mii_mediachg(mii); 1459 1460 return (0); 1461 } 1462 1463 /* 1464 * Report current media status. 1465 */ 1466 static void 1467 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1468 { 1469 struct bfe_softc *sc = ifp->if_softc; 1470 struct mii_data *mii; 1471 1472 mii = device_get_softc(sc->bfe_miibus); 1473 mii_pollstat(mii); 1474 ifmr->ifm_active = mii->mii_media_active; 1475 ifmr->ifm_status = mii->mii_media_status; 1476 } 1477 1478 static int 1479 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1480 { 1481 struct bfe_softc *sc = ifp->if_softc; 1482 struct ifreq *ifr = (struct ifreq *) data; 1483 struct mii_data *mii; 1484 int error = 0; 1485 1486 switch(command) { 1487 case SIOCSIFFLAGS: 1488 BFE_LOCK(sc); 1489 if(ifp->if_flags & IFF_UP) 1490 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1491 bfe_set_rx_mode(sc); 1492 else 1493 bfe_init_locked(sc); 1494 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1495 bfe_stop(sc); 1496 BFE_UNLOCK(sc); 1497 break; 1498 case SIOCADDMULTI: 1499 case SIOCDELMULTI: 1500 BFE_LOCK(sc); 1501 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1502 bfe_set_rx_mode(sc); 1503 BFE_UNLOCK(sc); 1504 break; 1505 case SIOCGIFMEDIA: 1506 case SIOCSIFMEDIA: 1507 mii = device_get_softc(sc->bfe_miibus); 1508 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1509 command); 1510 break; 1511 default: 1512 error = ether_ioctl(ifp, command, data); 1513 break; 1514 } 1515 1516 return (error); 1517 } 1518 1519 static void 1520 bfe_watchdog(struct ifnet *ifp) 1521 { 1522 struct bfe_softc *sc; 1523 1524 sc = ifp->if_softc; 1525 1526 BFE_LOCK(sc); 1527 1528 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1529 1530 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1531 bfe_init_locked(sc); 1532 1533 ifp->if_oerrors++; 1534 1535 BFE_UNLOCK(sc); 1536 } 1537 1538 static void 1539 bfe_tick(void *xsc) 1540 { 1541 struct bfe_softc *sc = xsc; 1542 struct mii_data *mii; 1543 1544 if (sc == NULL) 1545 return; 1546 1547 BFE_LOCK(sc); 1548 1549 mii = device_get_softc(sc->bfe_miibus); 1550 1551 bfe_stats_update(sc); 1552 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1553 1554 if(sc->bfe_link) { 1555 BFE_UNLOCK(sc); 1556 return; 1557 } 1558 1559 mii_tick(mii); 1560 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1561 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1562 sc->bfe_link++; 1563 1564 BFE_UNLOCK(sc); 1565 } 1566 1567 /* 1568 * Stop the adapter and free any mbufs allocated to the 1569 * RX and TX lists. 1570 */ 1571 static void 1572 bfe_stop(struct bfe_softc *sc) 1573 { 1574 struct ifnet *ifp; 1575 1576 BFE_LOCK_ASSERT(sc); 1577 1578 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1579 1580 ifp = sc->bfe_ifp; 1581 1582 bfe_chip_halt(sc); 1583 bfe_tx_ring_free(sc); 1584 bfe_rx_ring_free(sc); 1585 1586 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1587 } 1588