1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp = NULL; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 354 355 /* Allocate interrupt */ 356 rid = 0; 357 358 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 359 RF_SHAREABLE | RF_ACTIVE); 360 if (sc->bfe_irq == NULL) { 361 printf("bfe%d: couldn't map interrupt\n", unit); 362 error = ENXIO; 363 goto fail; 364 } 365 366 if (bfe_dma_alloc(dev)) { 367 printf("bfe%d: failed to allocate DMA resources\n", 368 sc->bfe_unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 /* Set up ifnet structure */ 374 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 375 if (ifp == NULL) { 376 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 377 error = ENOSPC; 378 goto fail; 379 } 380 ifp->if_softc = sc; 381 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 383 ifp->if_ioctl = bfe_ioctl; 384 ifp->if_start = bfe_start; 385 ifp->if_watchdog = bfe_watchdog; 386 ifp->if_init = bfe_init; 387 ifp->if_mtu = ETHERMTU; 388 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 389 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 390 IFQ_SET_READY(&ifp->if_snd); 391 392 bfe_get_config(sc); 393 394 /* Reset the chip and turn on the PHY */ 395 BFE_LOCK(sc); 396 bfe_chip_reset(sc); 397 BFE_UNLOCK(sc); 398 399 if (mii_phy_probe(dev, &sc->bfe_miibus, 400 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 401 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 402 error = ENXIO; 403 goto fail; 404 } 405 406 ether_ifattach(ifp, sc->bfe_enaddr); 407 callout_handle_init(&sc->bfe_stat_ch); 408 409 /* 410 * Tell the upper layer(s) we support long frames. 411 */ 412 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 413 ifp->if_capabilities |= IFCAP_VLAN_MTU; 414 ifp->if_capenable |= IFCAP_VLAN_MTU; 415 416 /* 417 * Hook interrupt last to avoid having to lock softc 418 */ 419 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 420 bfe_intr, sc, &sc->bfe_intrhand); 421 422 if (error) { 423 printf("bfe%d: couldn't set up irq\n", unit); 424 goto fail; 425 } 426 fail: 427 if (error) 428 bfe_release_resources(sc); 429 return (error); 430 } 431 432 static int 433 bfe_detach(device_t dev) 434 { 435 struct bfe_softc *sc; 436 struct ifnet *ifp; 437 438 sc = device_get_softc(dev); 439 440 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 441 BFE_LOCK(sc); 442 443 ifp = sc->bfe_ifp; 444 445 if (device_is_attached(dev)) { 446 bfe_stop(sc); 447 ether_ifdetach(ifp); 448 } 449 450 bfe_chip_reset(sc); 451 452 bus_generic_detach(dev); 453 if(sc->bfe_miibus != NULL) 454 device_delete_child(dev, sc->bfe_miibus); 455 456 bfe_release_resources(sc); 457 BFE_UNLOCK(sc); 458 mtx_destroy(&sc->bfe_mtx); 459 460 return (0); 461 } 462 463 /* 464 * Stop all chip I/O so that the kernel's probe routines don't 465 * get confused by errant DMAs when rebooting. 466 */ 467 static void 468 bfe_shutdown(device_t dev) 469 { 470 struct bfe_softc *sc; 471 472 sc = device_get_softc(dev); 473 BFE_LOCK(sc); 474 bfe_stop(sc); 475 476 BFE_UNLOCK(sc); 477 return; 478 } 479 480 static int 481 bfe_miibus_readreg(device_t dev, int phy, int reg) 482 { 483 struct bfe_softc *sc; 484 u_int32_t ret; 485 486 sc = device_get_softc(dev); 487 if(phy != sc->bfe_phyaddr) 488 return (0); 489 bfe_readphy(sc, reg, &ret); 490 491 return (ret); 492 } 493 494 static int 495 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 496 { 497 struct bfe_softc *sc; 498 499 sc = device_get_softc(dev); 500 if(phy != sc->bfe_phyaddr) 501 return (0); 502 bfe_writephy(sc, reg, val); 503 504 return (0); 505 } 506 507 static void 508 bfe_miibus_statchg(device_t dev) 509 { 510 return; 511 } 512 513 static void 514 bfe_tx_ring_free(struct bfe_softc *sc) 515 { 516 int i; 517 518 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 519 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 520 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 521 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 522 bus_dmamap_unload(sc->bfe_tag, 523 sc->bfe_tx_ring[i].bfe_map); 524 } 525 } 526 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 527 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 528 } 529 530 static void 531 bfe_rx_ring_free(struct bfe_softc *sc) 532 { 533 int i; 534 535 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 536 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 537 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 538 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 539 bus_dmamap_unload(sc->bfe_tag, 540 sc->bfe_rx_ring[i].bfe_map); 541 } 542 } 543 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 544 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 545 } 546 547 static int 548 bfe_list_rx_init(struct bfe_softc *sc) 549 { 550 int i; 551 552 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 553 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 554 return (ENOBUFS); 555 } 556 557 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 558 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 559 560 sc->bfe_rx_cons = 0; 561 562 return (0); 563 } 564 565 static int 566 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 567 { 568 struct bfe_rxheader *rx_header; 569 struct bfe_desc *d; 570 struct bfe_data *r; 571 u_int32_t ctrl; 572 573 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 574 return (EINVAL); 575 576 if(m == NULL) { 577 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 578 if(m == NULL) 579 return (ENOBUFS); 580 m->m_len = m->m_pkthdr.len = MCLBYTES; 581 } 582 else 583 m->m_data = m->m_ext.ext_buf; 584 585 rx_header = mtod(m, struct bfe_rxheader *); 586 rx_header->len = 0; 587 rx_header->flags = 0; 588 589 /* Map the mbuf into DMA */ 590 sc->bfe_rx_cnt = c; 591 d = &sc->bfe_rx_list[c]; 592 r = &sc->bfe_rx_ring[c]; 593 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 594 MCLBYTES, bfe_dma_map_desc, d, 0); 595 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 596 597 ctrl = ETHER_MAX_LEN + 32; 598 599 if(c == BFE_RX_LIST_CNT - 1) 600 ctrl |= BFE_DESC_EOT; 601 602 d->bfe_ctrl = ctrl; 603 r->bfe_mbuf = m; 604 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 605 return (0); 606 } 607 608 static void 609 bfe_get_config(struct bfe_softc *sc) 610 { 611 u_int8_t eeprom[128]; 612 613 bfe_read_eeprom(sc, eeprom); 614 615 sc->bfe_enaddr[0] = eeprom[79]; 616 sc->bfe_enaddr[1] = eeprom[78]; 617 sc->bfe_enaddr[2] = eeprom[81]; 618 sc->bfe_enaddr[3] = eeprom[80]; 619 sc->bfe_enaddr[4] = eeprom[83]; 620 sc->bfe_enaddr[5] = eeprom[82]; 621 622 sc->bfe_phyaddr = eeprom[90] & 0x1f; 623 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 624 625 sc->bfe_core_unit = 0; 626 sc->bfe_dma_offset = BFE_PCI_DMA; 627 } 628 629 static void 630 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 631 { 632 u_int32_t bar_orig, pci_rev, val; 633 634 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 635 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 636 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 637 638 val = CSR_READ_4(sc, BFE_SBINTVEC); 639 val |= cores; 640 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 641 642 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 643 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 644 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 645 646 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 647 } 648 649 static void 650 bfe_clear_stats(struct bfe_softc *sc) 651 { 652 u_long reg; 653 654 BFE_LOCK_ASSERT(sc); 655 656 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 657 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 658 CSR_READ_4(sc, reg); 659 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 660 CSR_READ_4(sc, reg); 661 } 662 663 static int 664 bfe_resetphy(struct bfe_softc *sc) 665 { 666 u_int32_t val; 667 668 bfe_writephy(sc, 0, BMCR_RESET); 669 DELAY(100); 670 bfe_readphy(sc, 0, &val); 671 if (val & BMCR_RESET) { 672 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 673 return (ENXIO); 674 } 675 return (0); 676 } 677 678 static void 679 bfe_chip_halt(struct bfe_softc *sc) 680 { 681 BFE_LOCK_ASSERT(sc); 682 /* disable interrupts - not that it actually does..*/ 683 CSR_WRITE_4(sc, BFE_IMASK, 0); 684 CSR_READ_4(sc, BFE_IMASK); 685 686 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 687 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 688 689 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 690 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 691 DELAY(10); 692 } 693 694 static void 695 bfe_chip_reset(struct bfe_softc *sc) 696 { 697 u_int32_t val; 698 699 BFE_LOCK_ASSERT(sc); 700 701 /* Set the interrupt vector for the enet core */ 702 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 703 704 /* is core up? */ 705 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 706 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 707 if (val == BFE_CLOCK) { 708 /* It is, so shut it down */ 709 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 710 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 711 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 712 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 713 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 714 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 715 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 716 100, 0); 717 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 718 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 719 } 720 721 bfe_core_reset(sc); 722 bfe_clear_stats(sc); 723 724 /* 725 * We want the phy registers to be accessible even when 726 * the driver is "downed" so initialize MDC preamble, frequency, 727 * and whether internal or external phy here. 728 */ 729 730 /* 4402 has 62.5Mhz SB clock and internal phy */ 731 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 732 733 /* Internal or external PHY? */ 734 val = CSR_READ_4(sc, BFE_DEVCTRL); 735 if(!(val & BFE_IPP)) 736 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 737 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 738 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 739 DELAY(100); 740 } 741 742 /* Enable CRC32 generation and set proper LED modes */ 743 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 744 745 /* Reset or clear powerdown control bit */ 746 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 747 748 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 749 BFE_LAZY_FC_MASK)); 750 751 /* 752 * We don't want lazy interrupts, so just send them at 753 * the end of a frame, please 754 */ 755 BFE_OR(sc, BFE_RCV_LAZY, 0); 756 757 /* Set max lengths, accounting for VLAN tags */ 758 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 759 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 760 761 /* Set watermark XXX - magic */ 762 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 763 764 /* 765 * Initialise DMA channels 766 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 767 */ 768 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 769 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 770 771 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 772 BFE_RX_CTRL_ENABLE); 773 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 774 775 bfe_resetphy(sc); 776 bfe_setupphy(sc); 777 } 778 779 static void 780 bfe_core_disable(struct bfe_softc *sc) 781 { 782 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 783 return; 784 785 /* 786 * Set reject, wait for it set, then wait for the core to stop 787 * being busy, then set reset and reject and enable the clocks. 788 */ 789 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 790 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 791 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 793 BFE_RESET)); 794 CSR_READ_4(sc, BFE_SBTMSLOW); 795 DELAY(10); 796 /* Leave reset and reject set */ 797 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 798 DELAY(10); 799 } 800 801 static void 802 bfe_core_reset(struct bfe_softc *sc) 803 { 804 u_int32_t val; 805 806 /* Disable the core */ 807 bfe_core_disable(sc); 808 809 /* and bring it back up */ 810 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 811 CSR_READ_4(sc, BFE_SBTMSLOW); 812 DELAY(10); 813 814 /* Chip bug, clear SERR, IB and TO if they are set. */ 815 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 816 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 817 val = CSR_READ_4(sc, BFE_SBIMSTATE); 818 if (val & (BFE_IBE | BFE_TO)) 819 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 820 821 /* Clear reset and allow it to move through the core */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 823 CSR_READ_4(sc, BFE_SBTMSLOW); 824 DELAY(10); 825 826 /* Leave the clock set */ 827 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 828 CSR_READ_4(sc, BFE_SBTMSLOW); 829 DELAY(10); 830 } 831 832 static void 833 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 834 { 835 u_int32_t val; 836 837 val = ((u_int32_t) data[2]) << 24; 838 val |= ((u_int32_t) data[3]) << 16; 839 val |= ((u_int32_t) data[4]) << 8; 840 val |= ((u_int32_t) data[5]); 841 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 842 val = (BFE_CAM_HI_VALID | 843 (((u_int32_t) data[0]) << 8) | 844 (((u_int32_t) data[1]))); 845 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 846 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 847 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 848 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 849 } 850 851 static void 852 bfe_set_rx_mode(struct bfe_softc *sc) 853 { 854 struct ifnet *ifp = sc->bfe_ifp; 855 struct ifmultiaddr *ifma; 856 u_int32_t val; 857 int i = 0; 858 859 val = CSR_READ_4(sc, BFE_RXCONF); 860 861 if (ifp->if_flags & IFF_PROMISC) 862 val |= BFE_RXCONF_PROMISC; 863 else 864 val &= ~BFE_RXCONF_PROMISC; 865 866 if (ifp->if_flags & IFF_BROADCAST) 867 val &= ~BFE_RXCONF_DBCAST; 868 else 869 val |= BFE_RXCONF_DBCAST; 870 871 872 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 873 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 874 875 if (ifp->if_flags & IFF_ALLMULTI) 876 val |= BFE_RXCONF_ALLMULTI; 877 else { 878 val &= ~BFE_RXCONF_ALLMULTI; 879 IF_ADDR_LOCK(ifp); 880 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 881 if (ifma->ifma_addr->sa_family != AF_LINK) 882 continue; 883 bfe_cam_write(sc, 884 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 885 } 886 IF_ADDR_UNLOCK(ifp); 887 } 888 889 CSR_WRITE_4(sc, BFE_RXCONF, val); 890 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 891 } 892 893 static void 894 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 895 { 896 u_int32_t *ptr; 897 898 ptr = arg; 899 *ptr = segs->ds_addr; 900 } 901 902 static void 903 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 904 { 905 struct bfe_desc *d; 906 907 d = arg; 908 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 909 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 910 } 911 912 static void 913 bfe_release_resources(struct bfe_softc *sc) 914 { 915 device_t dev; 916 int i; 917 918 dev = sc->bfe_dev; 919 920 if (sc->bfe_vpd_prodname != NULL) 921 free(sc->bfe_vpd_prodname, M_DEVBUF); 922 923 if (sc->bfe_vpd_readonly != NULL) 924 free(sc->bfe_vpd_readonly, M_DEVBUF); 925 926 if (sc->bfe_intrhand != NULL) 927 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 928 929 if (sc->bfe_irq != NULL) 930 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 931 932 if (sc->bfe_res != NULL) 933 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 934 935 if (sc->bfe_ifp != NULL) 936 if_free(sc->bfe_ifp); 937 938 if(sc->bfe_tx_tag != NULL) { 939 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 940 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 941 sc->bfe_tx_map); 942 bus_dma_tag_destroy(sc->bfe_tx_tag); 943 sc->bfe_tx_tag = NULL; 944 } 945 946 if(sc->bfe_rx_tag != NULL) { 947 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 948 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 949 sc->bfe_rx_map); 950 bus_dma_tag_destroy(sc->bfe_rx_tag); 951 sc->bfe_rx_tag = NULL; 952 } 953 954 if(sc->bfe_tag != NULL) { 955 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 956 bus_dmamap_destroy(sc->bfe_tag, 957 sc->bfe_tx_ring[i].bfe_map); 958 } 959 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 960 bus_dmamap_destroy(sc->bfe_tag, 961 sc->bfe_rx_ring[i].bfe_map); 962 } 963 bus_dma_tag_destroy(sc->bfe_tag); 964 sc->bfe_tag = NULL; 965 } 966 967 if(sc->bfe_parent_tag != NULL) 968 bus_dma_tag_destroy(sc->bfe_parent_tag); 969 970 return; 971 } 972 973 static void 974 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 975 { 976 long i; 977 u_int16_t *ptr = (u_int16_t *)data; 978 979 for(i = 0; i < 128; i += 2) 980 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 981 } 982 983 static int 984 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 985 u_long timeout, const int clear) 986 { 987 u_long i; 988 989 for (i = 0; i < timeout; i++) { 990 u_int32_t val = CSR_READ_4(sc, reg); 991 992 if (clear && !(val & bit)) 993 break; 994 if (!clear && (val & bit)) 995 break; 996 DELAY(10); 997 } 998 if (i == timeout) { 999 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1000 "%x to %s.\n", sc->bfe_unit, bit, reg, 1001 (clear ? "clear" : "set")); 1002 return (-1); 1003 } 1004 return (0); 1005 } 1006 1007 static int 1008 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1009 { 1010 int err; 1011 1012 /* Clear MII ISR */ 1013 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1014 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1015 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1016 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1017 (reg << BFE_MDIO_RA_SHIFT) | 1018 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1019 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1020 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1021 1022 return (err); 1023 } 1024 1025 static int 1026 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1027 { 1028 int status; 1029 1030 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1031 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1032 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1033 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1034 (reg << BFE_MDIO_RA_SHIFT) | 1035 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1036 (val & BFE_MDIO_DATA_DATA))); 1037 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1038 1039 return (status); 1040 } 1041 1042 /* 1043 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1044 * twice 1045 */ 1046 static int 1047 bfe_setupphy(struct bfe_softc *sc) 1048 { 1049 u_int32_t val; 1050 1051 /* Enable activity LED */ 1052 bfe_readphy(sc, 26, &val); 1053 bfe_writephy(sc, 26, val & 0x7fff); 1054 bfe_readphy(sc, 26, &val); 1055 1056 /* Enable traffic meter LED mode */ 1057 bfe_readphy(sc, 27, &val); 1058 bfe_writephy(sc, 27, val | (1 << 6)); 1059 1060 return (0); 1061 } 1062 1063 static void 1064 bfe_stats_update(struct bfe_softc *sc) 1065 { 1066 u_long reg; 1067 u_int32_t *val; 1068 1069 val = &sc->bfe_hwstats.tx_good_octets; 1070 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1071 *val++ += CSR_READ_4(sc, reg); 1072 } 1073 val = &sc->bfe_hwstats.rx_good_octets; 1074 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1075 *val++ += CSR_READ_4(sc, reg); 1076 } 1077 } 1078 1079 static void 1080 bfe_txeof(struct bfe_softc *sc) 1081 { 1082 struct ifnet *ifp; 1083 int i, chipidx; 1084 1085 BFE_LOCK_ASSERT(sc); 1086 1087 ifp = sc->bfe_ifp; 1088 1089 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1090 chipidx /= sizeof(struct bfe_desc); 1091 1092 i = sc->bfe_tx_cons; 1093 /* Go through the mbufs and free those that have been transmitted */ 1094 while(i != chipidx) { 1095 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1096 if(r->bfe_mbuf != NULL) { 1097 ifp->if_opackets++; 1098 m_freem(r->bfe_mbuf); 1099 r->bfe_mbuf = NULL; 1100 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1101 } 1102 sc->bfe_tx_cnt--; 1103 BFE_INC(i, BFE_TX_LIST_CNT); 1104 } 1105 1106 if(i != sc->bfe_tx_cons) { 1107 /* we freed up some mbufs */ 1108 sc->bfe_tx_cons = i; 1109 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1110 } 1111 if(sc->bfe_tx_cnt == 0) 1112 ifp->if_timer = 0; 1113 else 1114 ifp->if_timer = 5; 1115 } 1116 1117 /* Pass a received packet up the stack */ 1118 static void 1119 bfe_rxeof(struct bfe_softc *sc) 1120 { 1121 struct mbuf *m; 1122 struct ifnet *ifp; 1123 struct bfe_rxheader *rxheader; 1124 struct bfe_data *r; 1125 int cons; 1126 u_int32_t status, current, len, flags; 1127 1128 BFE_LOCK_ASSERT(sc); 1129 cons = sc->bfe_rx_cons; 1130 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1131 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1132 1133 ifp = sc->bfe_ifp; 1134 1135 while(current != cons) { 1136 r = &sc->bfe_rx_ring[cons]; 1137 m = r->bfe_mbuf; 1138 rxheader = mtod(m, struct bfe_rxheader*); 1139 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1140 len = rxheader->len; 1141 r->bfe_mbuf = NULL; 1142 1143 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1144 flags = rxheader->flags; 1145 1146 len -= ETHER_CRC_LEN; 1147 1148 /* flag an error and try again */ 1149 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1150 ifp->if_ierrors++; 1151 if (flags & BFE_RX_FLAG_SERR) 1152 ifp->if_collisions++; 1153 bfe_list_newbuf(sc, cons, m); 1154 BFE_INC(cons, BFE_RX_LIST_CNT); 1155 continue; 1156 } 1157 1158 /* Go past the rx header */ 1159 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1160 m_adj(m, BFE_RX_OFFSET); 1161 m->m_len = m->m_pkthdr.len = len; 1162 } else { 1163 bfe_list_newbuf(sc, cons, m); 1164 ifp->if_ierrors++; 1165 BFE_INC(cons, BFE_RX_LIST_CNT); 1166 continue; 1167 } 1168 1169 ifp->if_ipackets++; 1170 m->m_pkthdr.rcvif = ifp; 1171 BFE_UNLOCK(sc); 1172 (*ifp->if_input)(ifp, m); 1173 BFE_LOCK(sc); 1174 1175 BFE_INC(cons, BFE_RX_LIST_CNT); 1176 } 1177 sc->bfe_rx_cons = cons; 1178 } 1179 1180 static void 1181 bfe_intr(void *xsc) 1182 { 1183 struct bfe_softc *sc = xsc; 1184 struct ifnet *ifp; 1185 u_int32_t istat, imask, flag; 1186 1187 ifp = sc->bfe_ifp; 1188 1189 BFE_LOCK(sc); 1190 1191 istat = CSR_READ_4(sc, BFE_ISTAT); 1192 imask = CSR_READ_4(sc, BFE_IMASK); 1193 1194 /* 1195 * Defer unsolicited interrupts - This is necessary because setting the 1196 * chips interrupt mask register to 0 doesn't actually stop the 1197 * interrupts 1198 */ 1199 istat &= imask; 1200 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1201 CSR_READ_4(sc, BFE_ISTAT); 1202 1203 /* not expecting this interrupt, disregard it */ 1204 if(istat == 0) { 1205 BFE_UNLOCK(sc); 1206 return; 1207 } 1208 1209 if(istat & BFE_ISTAT_ERRORS) { 1210 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1211 if(flag & BFE_STAT_EMASK) 1212 ifp->if_oerrors++; 1213 1214 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1215 if(flag & BFE_RX_FLAG_ERRORS) 1216 ifp->if_ierrors++; 1217 1218 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1219 bfe_init_locked(sc); 1220 } 1221 1222 /* A packet was received */ 1223 if(istat & BFE_ISTAT_RX) 1224 bfe_rxeof(sc); 1225 1226 /* A packet was sent */ 1227 if(istat & BFE_ISTAT_TX) 1228 bfe_txeof(sc); 1229 1230 /* We have packets pending, fire them out */ 1231 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1232 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1233 bfe_start_locked(ifp); 1234 1235 BFE_UNLOCK(sc); 1236 } 1237 1238 static int 1239 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1240 { 1241 struct bfe_desc *d = NULL; 1242 struct bfe_data *r = NULL; 1243 struct mbuf *m; 1244 u_int32_t frag, cur, cnt = 0; 1245 int chainlen = 0; 1246 1247 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1248 return (ENOBUFS); 1249 1250 /* 1251 * Count the number of frags in this chain to see if 1252 * we need to m_defrag. Since the descriptor list is shared 1253 * by all packets, we'll m_defrag long chains so that they 1254 * do not use up the entire list, even if they would fit. 1255 */ 1256 for(m = m_head; m != NULL; m = m->m_next) 1257 chainlen++; 1258 1259 1260 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1261 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1262 m = m_defrag(m_head, M_DONTWAIT); 1263 if (m == NULL) 1264 return (ENOBUFS); 1265 m_head = m; 1266 } 1267 1268 /* 1269 * Start packing the mbufs in this chain into 1270 * the fragment pointers. Stop when we run out 1271 * of fragments or hit the end of the mbuf chain. 1272 */ 1273 m = m_head; 1274 cur = frag = *txidx; 1275 cnt = 0; 1276 1277 for(m = m_head; m != NULL; m = m->m_next) { 1278 if(m->m_len != 0) { 1279 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1280 return (ENOBUFS); 1281 1282 d = &sc->bfe_tx_list[cur]; 1283 r = &sc->bfe_tx_ring[cur]; 1284 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1285 /* always intterupt on completion */ 1286 d->bfe_ctrl |= BFE_DESC_IOC; 1287 if(cnt == 0) 1288 /* Set start of frame */ 1289 d->bfe_ctrl |= BFE_DESC_SOF; 1290 if(cur == BFE_TX_LIST_CNT - 1) 1291 /* 1292 * Tell the chip to wrap to the start of 1293 * the descriptor list 1294 */ 1295 d->bfe_ctrl |= BFE_DESC_EOT; 1296 1297 bus_dmamap_load(sc->bfe_tag, 1298 r->bfe_map, mtod(m, void*), m->m_len, 1299 bfe_dma_map_desc, d, 0); 1300 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1301 BUS_DMASYNC_PREREAD); 1302 1303 frag = cur; 1304 BFE_INC(cur, BFE_TX_LIST_CNT); 1305 cnt++; 1306 } 1307 } 1308 1309 if (m != NULL) 1310 return (ENOBUFS); 1311 1312 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1313 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1314 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1315 1316 *txidx = cur; 1317 sc->bfe_tx_cnt += cnt; 1318 return (0); 1319 } 1320 1321 /* 1322 * Set up to transmit a packet. 1323 */ 1324 static void 1325 bfe_start(struct ifnet *ifp) 1326 { 1327 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1328 bfe_start_locked(ifp); 1329 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1330 } 1331 1332 /* 1333 * Set up to transmit a packet. The softc is already locked. 1334 */ 1335 static void 1336 bfe_start_locked(struct ifnet *ifp) 1337 { 1338 struct bfe_softc *sc; 1339 struct mbuf *m_head = NULL; 1340 int idx, queued = 0; 1341 1342 sc = ifp->if_softc; 1343 idx = sc->bfe_tx_prod; 1344 1345 BFE_LOCK_ASSERT(sc); 1346 1347 /* 1348 * Not much point trying to send if the link is down 1349 * or we have nothing to send. 1350 */ 1351 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1352 return; 1353 1354 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1355 return; 1356 1357 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1358 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1359 if(m_head == NULL) 1360 break; 1361 1362 /* 1363 * Pack the data into the tx ring. If we dont have 1364 * enough room, let the chip drain the ring. 1365 */ 1366 if(bfe_encap(sc, m_head, &idx)) { 1367 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1368 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1369 break; 1370 } 1371 1372 queued++; 1373 1374 /* 1375 * If there's a BPF listener, bounce a copy of this frame 1376 * to him. 1377 */ 1378 BPF_MTAP(ifp, m_head); 1379 } 1380 1381 if (queued) { 1382 sc->bfe_tx_prod = idx; 1383 /* Transmit - twice due to apparent hardware bug */ 1384 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1385 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1386 1387 /* 1388 * Set a timeout in case the chip goes out to lunch. 1389 */ 1390 ifp->if_timer = 5; 1391 } 1392 } 1393 1394 static void 1395 bfe_init(void *xsc) 1396 { 1397 BFE_LOCK((struct bfe_softc *)xsc); 1398 bfe_init_locked(xsc); 1399 BFE_UNLOCK((struct bfe_softc *)xsc); 1400 } 1401 1402 static void 1403 bfe_init_locked(void *xsc) 1404 { 1405 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1406 struct ifnet *ifp = sc->bfe_ifp; 1407 1408 BFE_LOCK_ASSERT(sc); 1409 1410 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1411 return; 1412 1413 bfe_stop(sc); 1414 bfe_chip_reset(sc); 1415 1416 if (bfe_list_rx_init(sc) == ENOBUFS) { 1417 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1418 sc->bfe_unit); 1419 bfe_stop(sc); 1420 return; 1421 } 1422 1423 bfe_set_rx_mode(sc); 1424 1425 /* Enable the chip and core */ 1426 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1427 /* Enable interrupts */ 1428 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1429 1430 bfe_ifmedia_upd(ifp); 1431 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1432 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1433 1434 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1435 } 1436 1437 /* 1438 * Set media options. 1439 */ 1440 static int 1441 bfe_ifmedia_upd(struct ifnet *ifp) 1442 { 1443 struct bfe_softc *sc; 1444 struct mii_data *mii; 1445 1446 sc = ifp->if_softc; 1447 1448 mii = device_get_softc(sc->bfe_miibus); 1449 sc->bfe_link = 0; 1450 if (mii->mii_instance) { 1451 struct mii_softc *miisc; 1452 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1453 miisc = LIST_NEXT(miisc, mii_list)) 1454 mii_phy_reset(miisc); 1455 } 1456 mii_mediachg(mii); 1457 1458 return (0); 1459 } 1460 1461 /* 1462 * Report current media status. 1463 */ 1464 static void 1465 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1466 { 1467 struct bfe_softc *sc = ifp->if_softc; 1468 struct mii_data *mii; 1469 1470 mii = device_get_softc(sc->bfe_miibus); 1471 mii_pollstat(mii); 1472 ifmr->ifm_active = mii->mii_media_active; 1473 ifmr->ifm_status = mii->mii_media_status; 1474 } 1475 1476 static int 1477 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1478 { 1479 struct bfe_softc *sc = ifp->if_softc; 1480 struct ifreq *ifr = (struct ifreq *) data; 1481 struct mii_data *mii; 1482 int error = 0; 1483 1484 switch(command) { 1485 case SIOCSIFFLAGS: 1486 BFE_LOCK(sc); 1487 if(ifp->if_flags & IFF_UP) 1488 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1489 bfe_set_rx_mode(sc); 1490 else 1491 bfe_init_locked(sc); 1492 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1493 bfe_stop(sc); 1494 BFE_UNLOCK(sc); 1495 break; 1496 case SIOCADDMULTI: 1497 case SIOCDELMULTI: 1498 BFE_LOCK(sc); 1499 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1500 bfe_set_rx_mode(sc); 1501 BFE_UNLOCK(sc); 1502 break; 1503 case SIOCGIFMEDIA: 1504 case SIOCSIFMEDIA: 1505 mii = device_get_softc(sc->bfe_miibus); 1506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1507 command); 1508 break; 1509 default: 1510 error = ether_ioctl(ifp, command, data); 1511 break; 1512 } 1513 1514 return (error); 1515 } 1516 1517 static void 1518 bfe_watchdog(struct ifnet *ifp) 1519 { 1520 struct bfe_softc *sc; 1521 1522 sc = ifp->if_softc; 1523 1524 BFE_LOCK(sc); 1525 1526 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1527 1528 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1529 bfe_init_locked(sc); 1530 1531 ifp->if_oerrors++; 1532 1533 BFE_UNLOCK(sc); 1534 } 1535 1536 static void 1537 bfe_tick(void *xsc) 1538 { 1539 struct bfe_softc *sc = xsc; 1540 struct mii_data *mii; 1541 1542 if (sc == NULL) 1543 return; 1544 1545 BFE_LOCK(sc); 1546 1547 mii = device_get_softc(sc->bfe_miibus); 1548 1549 bfe_stats_update(sc); 1550 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1551 1552 if(sc->bfe_link) { 1553 BFE_UNLOCK(sc); 1554 return; 1555 } 1556 1557 mii_tick(mii); 1558 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1559 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1560 sc->bfe_link++; 1561 1562 BFE_UNLOCK(sc); 1563 } 1564 1565 /* 1566 * Stop the adapter and free any mbufs allocated to the 1567 * RX and TX lists. 1568 */ 1569 static void 1570 bfe_stop(struct bfe_softc *sc) 1571 { 1572 struct ifnet *ifp; 1573 1574 BFE_LOCK_ASSERT(sc); 1575 1576 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1577 1578 ifp = sc->bfe_ifp; 1579 1580 bfe_chip_halt(sc); 1581 bfe_tx_ring_free(sc); 1582 bfe_rx_ring_free(sc); 1583 1584 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1585 } 1586