1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 5 * and Duncan Barclay<dmlb@dmlb.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/mbuf.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/socket.h> 40 #include <sys/sockio.h> 41 #include <sys/sysctl.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_var.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <machine/bus.h> 59 60 #include <dev/bfe/if_bfereg.h> 61 62 MODULE_DEPEND(bfe, pci, 1, 1, 1); 63 MODULE_DEPEND(bfe, ether, 1, 1, 1); 64 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 65 66 /* "device miibus" required. See GENERIC if you get errors here. */ 67 #include "miibus_if.h" 68 69 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 70 71 static struct bfe_type bfe_devs[] = { 72 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 73 "Broadcom BCM4401 Fast Ethernet" }, 74 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 75 "Broadcom BCM4401-B0 Fast Ethernet" }, 76 { 0, 0, NULL } 77 }; 78 79 static int bfe_probe (device_t); 80 static int bfe_attach (device_t); 81 static int bfe_detach (device_t); 82 static int bfe_suspend (device_t); 83 static int bfe_resume (device_t); 84 static void bfe_release_resources (struct bfe_softc *); 85 static void bfe_intr (void *); 86 static int bfe_encap (struct bfe_softc *, struct mbuf **); 87 static void bfe_start (if_t); 88 static void bfe_start_locked (if_t); 89 static int bfe_ioctl (if_t, u_long, caddr_t); 90 static void bfe_init (void *); 91 static void bfe_init_locked (void *); 92 static void bfe_stop (struct bfe_softc *); 93 static void bfe_watchdog (struct bfe_softc *); 94 static int bfe_shutdown (device_t); 95 static void bfe_tick (void *); 96 static void bfe_txeof (struct bfe_softc *); 97 static void bfe_rxeof (struct bfe_softc *); 98 static void bfe_set_rx_mode (struct bfe_softc *); 99 static int bfe_list_rx_init (struct bfe_softc *); 100 static void bfe_list_tx_init (struct bfe_softc *); 101 static void bfe_discard_buf (struct bfe_softc *, int); 102 static int bfe_list_newbuf (struct bfe_softc *, int); 103 static void bfe_rx_ring_free (struct bfe_softc *); 104 105 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 106 static int bfe_ifmedia_upd (if_t); 107 static void bfe_ifmedia_sts (if_t, struct ifmediareq *); 108 static int bfe_miibus_readreg (device_t, int, int); 109 static int bfe_miibus_writereg (device_t, int, int, int); 110 static void bfe_miibus_statchg (device_t); 111 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 112 u_long, const int); 113 static void bfe_get_config (struct bfe_softc *sc); 114 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 115 static void bfe_stats_update (struct bfe_softc *); 116 static void bfe_clear_stats (struct bfe_softc *); 117 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 118 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 119 static int bfe_resetphy (struct bfe_softc *); 120 static int bfe_setupphy (struct bfe_softc *); 121 static void bfe_chip_reset (struct bfe_softc *); 122 static void bfe_chip_halt (struct bfe_softc *); 123 static void bfe_core_reset (struct bfe_softc *); 124 static void bfe_core_disable (struct bfe_softc *); 125 static int bfe_dma_alloc (struct bfe_softc *); 126 static void bfe_dma_free (struct bfe_softc *sc); 127 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 128 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 129 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); 130 131 static device_method_t bfe_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, bfe_probe), 134 DEVMETHOD(device_attach, bfe_attach), 135 DEVMETHOD(device_detach, bfe_detach), 136 DEVMETHOD(device_shutdown, bfe_shutdown), 137 DEVMETHOD(device_suspend, bfe_suspend), 138 DEVMETHOD(device_resume, bfe_resume), 139 140 /* MII interface */ 141 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 142 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 143 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 144 145 DEVMETHOD_END 146 }; 147 148 static driver_t bfe_driver = { 149 "bfe", 150 bfe_methods, 151 sizeof(struct bfe_softc) 152 }; 153 154 DRIVER_MODULE(bfe, pci, bfe_driver, 0, 0); 155 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs, 156 nitems(bfe_devs) - 1); 157 DRIVER_MODULE(miibus, bfe, miibus_driver, 0, 0); 158 159 /* 160 * Probe for a Broadcom 4401 chip. 161 */ 162 static int 163 bfe_probe(device_t dev) 164 { 165 struct bfe_type *t; 166 167 t = bfe_devs; 168 169 while (t->bfe_name != NULL) { 170 if (pci_get_vendor(dev) == t->bfe_vid && 171 pci_get_device(dev) == t->bfe_did) { 172 device_set_desc(dev, t->bfe_name); 173 return (BUS_PROBE_DEFAULT); 174 } 175 t++; 176 } 177 178 return (ENXIO); 179 } 180 181 struct bfe_dmamap_arg { 182 bus_addr_t bfe_busaddr; 183 }; 184 185 static int 186 bfe_dma_alloc(struct bfe_softc *sc) 187 { 188 struct bfe_dmamap_arg ctx; 189 struct bfe_rx_data *rd; 190 struct bfe_tx_data *td; 191 int error, i; 192 193 /* 194 * parent tag. Apparently the chip cannot handle any DMA address 195 * greater than 1GB. 196 */ 197 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 198 1, 0, /* alignment, boundary */ 199 BFE_DMA_MAXADDR, /* lowaddr */ 200 BUS_SPACE_MAXADDR, /* highaddr */ 201 NULL, NULL, /* filter, filterarg */ 202 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 203 0, /* nsegments */ 204 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 205 0, /* flags */ 206 NULL, NULL, /* lockfunc, lockarg */ 207 &sc->bfe_parent_tag); 208 if (error != 0) { 209 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 210 goto fail; 211 } 212 213 /* Create tag for Tx ring. */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 215 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 216 BUS_SPACE_MAXADDR, /* lowaddr */ 217 BUS_SPACE_MAXADDR, /* highaddr */ 218 NULL, NULL, /* filter, filterarg */ 219 BFE_TX_LIST_SIZE, /* maxsize */ 220 1, /* nsegments */ 221 BFE_TX_LIST_SIZE, /* maxsegsize */ 222 0, /* flags */ 223 NULL, NULL, /* lockfunc, lockarg */ 224 &sc->bfe_tx_tag); 225 if (error != 0) { 226 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 227 goto fail; 228 } 229 230 /* Create tag for Rx ring. */ 231 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 232 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 233 BUS_SPACE_MAXADDR, /* lowaddr */ 234 BUS_SPACE_MAXADDR, /* highaddr */ 235 NULL, NULL, /* filter, filterarg */ 236 BFE_RX_LIST_SIZE, /* maxsize */ 237 1, /* nsegments */ 238 BFE_RX_LIST_SIZE, /* maxsegsize */ 239 0, /* flags */ 240 NULL, NULL, /* lockfunc, lockarg */ 241 &sc->bfe_rx_tag); 242 if (error != 0) { 243 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 244 goto fail; 245 } 246 247 /* Create tag for Tx buffers. */ 248 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 249 1, 0, /* alignment, boundary */ 250 BUS_SPACE_MAXADDR, /* lowaddr */ 251 BUS_SPACE_MAXADDR, /* highaddr */ 252 NULL, NULL, /* filter, filterarg */ 253 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 254 BFE_MAXTXSEGS, /* nsegments */ 255 MCLBYTES, /* maxsegsize */ 256 0, /* flags */ 257 NULL, NULL, /* lockfunc, lockarg */ 258 &sc->bfe_txmbuf_tag); 259 if (error != 0) { 260 device_printf(sc->bfe_dev, 261 "cannot create Tx buffer DMA tag.\n"); 262 goto fail; 263 } 264 265 /* Create tag for Rx buffers. */ 266 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 267 1, 0, /* alignment, boundary */ 268 BUS_SPACE_MAXADDR, /* lowaddr */ 269 BUS_SPACE_MAXADDR, /* highaddr */ 270 NULL, NULL, /* filter, filterarg */ 271 MCLBYTES, /* maxsize */ 272 1, /* nsegments */ 273 MCLBYTES, /* maxsegsize */ 274 0, /* flags */ 275 NULL, NULL, /* lockfunc, lockarg */ 276 &sc->bfe_rxmbuf_tag); 277 if (error != 0) { 278 device_printf(sc->bfe_dev, 279 "cannot create Rx buffer DMA tag.\n"); 280 goto fail; 281 } 282 283 /* Allocate DMA'able memory and load DMA map. */ 284 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 285 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 286 if (error != 0) { 287 device_printf(sc->bfe_dev, 288 "cannot allocate DMA'able memory for Tx ring.\n"); 289 goto fail; 290 } 291 ctx.bfe_busaddr = 0; 292 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 293 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 294 BUS_DMA_NOWAIT); 295 if (error != 0 || ctx.bfe_busaddr == 0) { 296 device_printf(sc->bfe_dev, 297 "cannot load DMA'able memory for Tx ring.\n"); 298 goto fail; 299 } 300 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 301 302 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 303 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 304 if (error != 0) { 305 device_printf(sc->bfe_dev, 306 "cannot allocate DMA'able memory for Rx ring.\n"); 307 goto fail; 308 } 309 ctx.bfe_busaddr = 0; 310 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 311 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 312 BUS_DMA_NOWAIT); 313 if (error != 0 || ctx.bfe_busaddr == 0) { 314 device_printf(sc->bfe_dev, 315 "cannot load DMA'able memory for Rx ring.\n"); 316 goto fail; 317 } 318 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 319 320 /* Create DMA maps for Tx buffers. */ 321 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 322 td = &sc->bfe_tx_ring[i]; 323 td->bfe_mbuf = NULL; 324 td->bfe_map = NULL; 325 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 326 if (error != 0) { 327 device_printf(sc->bfe_dev, 328 "cannot create DMA map for Tx.\n"); 329 goto fail; 330 } 331 } 332 333 /* Create spare DMA map for Rx buffers. */ 334 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 335 if (error != 0) { 336 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 337 goto fail; 338 } 339 /* Create DMA maps for Rx buffers. */ 340 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 341 rd = &sc->bfe_rx_ring[i]; 342 rd->bfe_mbuf = NULL; 343 rd->bfe_map = NULL; 344 rd->bfe_ctrl = 0; 345 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 346 if (error != 0) { 347 device_printf(sc->bfe_dev, 348 "cannot create DMA map for Rx.\n"); 349 goto fail; 350 } 351 } 352 353 fail: 354 return (error); 355 } 356 357 static void 358 bfe_dma_free(struct bfe_softc *sc) 359 { 360 struct bfe_tx_data *td; 361 struct bfe_rx_data *rd; 362 int i; 363 364 /* Tx ring. */ 365 if (sc->bfe_tx_tag != NULL) { 366 if (sc->bfe_tx_dma != 0) 367 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 368 if (sc->bfe_tx_list != NULL) 369 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 370 sc->bfe_tx_map); 371 sc->bfe_tx_dma = 0; 372 sc->bfe_tx_list = NULL; 373 bus_dma_tag_destroy(sc->bfe_tx_tag); 374 sc->bfe_tx_tag = NULL; 375 } 376 377 /* Rx ring. */ 378 if (sc->bfe_rx_tag != NULL) { 379 if (sc->bfe_rx_dma != 0) 380 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 381 if (sc->bfe_rx_list != NULL) 382 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 383 sc->bfe_rx_map); 384 sc->bfe_rx_dma = 0; 385 sc->bfe_rx_list = NULL; 386 bus_dma_tag_destroy(sc->bfe_rx_tag); 387 sc->bfe_rx_tag = NULL; 388 } 389 390 /* Tx buffers. */ 391 if (sc->bfe_txmbuf_tag != NULL) { 392 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 393 td = &sc->bfe_tx_ring[i]; 394 if (td->bfe_map != NULL) { 395 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 396 td->bfe_map); 397 td->bfe_map = NULL; 398 } 399 } 400 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 401 sc->bfe_txmbuf_tag = NULL; 402 } 403 404 /* Rx buffers. */ 405 if (sc->bfe_rxmbuf_tag != NULL) { 406 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 407 rd = &sc->bfe_rx_ring[i]; 408 if (rd->bfe_map != NULL) { 409 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 410 rd->bfe_map); 411 rd->bfe_map = NULL; 412 } 413 } 414 if (sc->bfe_rx_sparemap != NULL) { 415 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 416 sc->bfe_rx_sparemap); 417 sc->bfe_rx_sparemap = NULL; 418 } 419 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 420 sc->bfe_rxmbuf_tag = NULL; 421 } 422 423 if (sc->bfe_parent_tag != NULL) { 424 bus_dma_tag_destroy(sc->bfe_parent_tag); 425 sc->bfe_parent_tag = NULL; 426 } 427 } 428 429 static int 430 bfe_attach(device_t dev) 431 { 432 if_t ifp = NULL; 433 struct bfe_softc *sc; 434 int error = 0, rid; 435 436 sc = device_get_softc(dev); 437 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 438 MTX_DEF); 439 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 440 441 sc->bfe_dev = dev; 442 443 /* 444 * Map control/status registers. 445 */ 446 pci_enable_busmaster(dev); 447 448 rid = PCIR_BAR(0); 449 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 450 RF_ACTIVE); 451 if (sc->bfe_res == NULL) { 452 device_printf(dev, "couldn't map memory\n"); 453 error = ENXIO; 454 goto fail; 455 } 456 457 /* Allocate interrupt */ 458 rid = 0; 459 460 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 461 RF_SHAREABLE | RF_ACTIVE); 462 if (sc->bfe_irq == NULL) { 463 device_printf(dev, "couldn't map interrupt\n"); 464 error = ENXIO; 465 goto fail; 466 } 467 468 if (bfe_dma_alloc(sc) != 0) { 469 device_printf(dev, "failed to allocate DMA resources\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 476 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 477 sysctl_bfe_stats, "I", "Statistics"); 478 479 /* Set up ifnet structure */ 480 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 481 if (ifp == NULL) { 482 device_printf(dev, "failed to if_alloc()\n"); 483 error = ENOSPC; 484 goto fail; 485 } 486 if_setsoftc(ifp, sc); 487 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 488 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 489 if_setioctlfn(ifp, bfe_ioctl); 490 if_setstartfn(ifp, bfe_start); 491 if_setinitfn(ifp, bfe_init); 492 if_setsendqlen(ifp, BFE_TX_QLEN); 493 if_setsendqready(ifp); 494 495 bfe_get_config(sc); 496 497 /* Reset the chip and turn on the PHY */ 498 BFE_LOCK(sc); 499 bfe_chip_reset(sc); 500 BFE_UNLOCK(sc); 501 502 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 503 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 504 0); 505 if (error != 0) { 506 device_printf(dev, "attaching PHYs failed\n"); 507 goto fail; 508 } 509 510 ether_ifattach(ifp, sc->bfe_enaddr); 511 512 /* 513 * Tell the upper layer(s) we support long frames. 514 */ 515 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 516 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 517 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 518 519 /* 520 * Hook interrupt last to avoid having to lock softc 521 */ 522 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 523 NULL, bfe_intr, sc, &sc->bfe_intrhand); 524 525 if (error) { 526 device_printf(dev, "couldn't set up irq\n"); 527 goto fail; 528 } 529 fail: 530 if (error != 0) 531 bfe_detach(dev); 532 return (error); 533 } 534 535 static int 536 bfe_detach(device_t dev) 537 { 538 struct bfe_softc *sc; 539 if_t ifp; 540 541 sc = device_get_softc(dev); 542 543 ifp = sc->bfe_ifp; 544 545 if (device_is_attached(dev)) { 546 BFE_LOCK(sc); 547 sc->bfe_flags |= BFE_FLAG_DETACH; 548 bfe_stop(sc); 549 BFE_UNLOCK(sc); 550 callout_drain(&sc->bfe_stat_co); 551 if (ifp != NULL) 552 ether_ifdetach(ifp); 553 } 554 555 BFE_LOCK(sc); 556 bfe_chip_reset(sc); 557 BFE_UNLOCK(sc); 558 559 bus_generic_detach(dev); 560 if (sc->bfe_miibus != NULL) 561 device_delete_child(dev, sc->bfe_miibus); 562 563 bfe_release_resources(sc); 564 bfe_dma_free(sc); 565 mtx_destroy(&sc->bfe_mtx); 566 567 return (0); 568 } 569 570 /* 571 * Stop all chip I/O so that the kernel's probe routines don't 572 * get confused by errant DMAs when rebooting. 573 */ 574 static int 575 bfe_shutdown(device_t dev) 576 { 577 struct bfe_softc *sc; 578 579 sc = device_get_softc(dev); 580 BFE_LOCK(sc); 581 bfe_stop(sc); 582 583 BFE_UNLOCK(sc); 584 585 return (0); 586 } 587 588 static int 589 bfe_suspend(device_t dev) 590 { 591 struct bfe_softc *sc; 592 593 sc = device_get_softc(dev); 594 BFE_LOCK(sc); 595 bfe_stop(sc); 596 BFE_UNLOCK(sc); 597 598 return (0); 599 } 600 601 static int 602 bfe_resume(device_t dev) 603 { 604 struct bfe_softc *sc; 605 if_t ifp; 606 607 sc = device_get_softc(dev); 608 ifp = sc->bfe_ifp; 609 BFE_LOCK(sc); 610 bfe_chip_reset(sc); 611 if (if_getflags(ifp) & IFF_UP) { 612 bfe_init_locked(sc); 613 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 614 !if_sendq_empty(ifp)) 615 bfe_start_locked(ifp); 616 } 617 BFE_UNLOCK(sc); 618 619 return (0); 620 } 621 622 static int 623 bfe_miibus_readreg(device_t dev, int phy, int reg) 624 { 625 struct bfe_softc *sc; 626 u_int32_t ret; 627 628 sc = device_get_softc(dev); 629 bfe_readphy(sc, reg, &ret); 630 631 return (ret); 632 } 633 634 static int 635 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 636 { 637 struct bfe_softc *sc; 638 639 sc = device_get_softc(dev); 640 bfe_writephy(sc, reg, val); 641 642 return (0); 643 } 644 645 static void 646 bfe_miibus_statchg(device_t dev) 647 { 648 struct bfe_softc *sc; 649 struct mii_data *mii; 650 u_int32_t val; 651 #ifdef notyet 652 u_int32_t flow; 653 #endif 654 655 sc = device_get_softc(dev); 656 mii = device_get_softc(sc->bfe_miibus); 657 658 sc->bfe_flags &= ~BFE_FLAG_LINK; 659 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 660 (IFM_ACTIVE | IFM_AVALID)) { 661 switch (IFM_SUBTYPE(mii->mii_media_active)) { 662 case IFM_10_T: 663 case IFM_100_TX: 664 sc->bfe_flags |= BFE_FLAG_LINK; 665 break; 666 default: 667 break; 668 } 669 } 670 671 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 672 val = CSR_READ_4(sc, BFE_TX_CTRL); 673 val &= ~BFE_TX_DUPLEX; 674 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 675 val |= BFE_TX_DUPLEX; 676 #ifdef notyet 677 flow = CSR_READ_4(sc, BFE_RXCONF); 678 flow &= ~BFE_RXCONF_FLOW; 679 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 680 IFM_ETH_RXPAUSE) != 0) 681 flow |= BFE_RXCONF_FLOW; 682 CSR_WRITE_4(sc, BFE_RXCONF, flow); 683 /* 684 * It seems that the hardware has Tx pause issues 685 * so enable only Rx pause. 686 */ 687 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 688 flow &= ~BFE_FLOW_PAUSE_ENAB; 689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 690 #endif 691 } 692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 693 } 694 695 static void 696 bfe_tx_ring_free(struct bfe_softc *sc) 697 { 698 int i; 699 700 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 701 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 702 bus_dmamap_sync(sc->bfe_txmbuf_tag, 703 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 704 bus_dmamap_unload(sc->bfe_txmbuf_tag, 705 sc->bfe_tx_ring[i].bfe_map); 706 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 707 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 708 } 709 } 710 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 711 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 } 714 715 static void 716 bfe_rx_ring_free(struct bfe_softc *sc) 717 { 718 int i; 719 720 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 721 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 722 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 723 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 725 sc->bfe_rx_ring[i].bfe_map); 726 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 727 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 728 } 729 } 730 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 731 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 } 734 735 static int 736 bfe_list_rx_init(struct bfe_softc *sc) 737 { 738 struct bfe_rx_data *rd; 739 int i; 740 741 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 742 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 743 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 744 rd = &sc->bfe_rx_ring[i]; 745 rd->bfe_mbuf = NULL; 746 rd->bfe_ctrl = 0; 747 if (bfe_list_newbuf(sc, i) != 0) 748 return (ENOBUFS); 749 } 750 751 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 754 755 return (0); 756 } 757 758 static void 759 bfe_list_tx_init(struct bfe_softc *sc) 760 { 761 int i; 762 763 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 764 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 765 for (i = 0; i < BFE_TX_LIST_CNT; i++) 766 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 767 768 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 } 771 772 static void 773 bfe_discard_buf(struct bfe_softc *sc, int c) 774 { 775 struct bfe_rx_data *r; 776 struct bfe_desc *d; 777 778 r = &sc->bfe_rx_ring[c]; 779 d = &sc->bfe_rx_list[c]; 780 d->bfe_ctrl = htole32(r->bfe_ctrl); 781 } 782 783 static int 784 bfe_list_newbuf(struct bfe_softc *sc, int c) 785 { 786 struct bfe_rxheader *rx_header; 787 struct bfe_desc *d; 788 struct bfe_rx_data *r; 789 struct mbuf *m; 790 bus_dma_segment_t segs[1]; 791 bus_dmamap_t map; 792 u_int32_t ctrl; 793 int nsegs; 794 795 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 796 if (m == NULL) 797 return (ENOBUFS); 798 m->m_len = m->m_pkthdr.len = MCLBYTES; 799 800 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 801 m, segs, &nsegs, 0) != 0) { 802 m_freem(m); 803 return (ENOBUFS); 804 } 805 806 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 807 r = &sc->bfe_rx_ring[c]; 808 if (r->bfe_mbuf != NULL) { 809 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 810 BUS_DMASYNC_POSTREAD); 811 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 812 } 813 map = r->bfe_map; 814 r->bfe_map = sc->bfe_rx_sparemap; 815 sc->bfe_rx_sparemap = map; 816 r->bfe_mbuf = m; 817 818 rx_header = mtod(m, struct bfe_rxheader *); 819 rx_header->len = 0; 820 rx_header->flags = 0; 821 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 822 823 ctrl = segs[0].ds_len & BFE_DESC_LEN; 824 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 825 __func__, ctrl)); 826 if (c == BFE_RX_LIST_CNT - 1) 827 ctrl |= BFE_DESC_EOT; 828 r->bfe_ctrl = ctrl; 829 830 d = &sc->bfe_rx_list[c]; 831 d->bfe_ctrl = htole32(ctrl); 832 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 833 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 834 835 return (0); 836 } 837 838 static void 839 bfe_get_config(struct bfe_softc *sc) 840 { 841 u_int8_t eeprom[128]; 842 843 bfe_read_eeprom(sc, eeprom); 844 845 sc->bfe_enaddr[0] = eeprom[79]; 846 sc->bfe_enaddr[1] = eeprom[78]; 847 sc->bfe_enaddr[2] = eeprom[81]; 848 sc->bfe_enaddr[3] = eeprom[80]; 849 sc->bfe_enaddr[4] = eeprom[83]; 850 sc->bfe_enaddr[5] = eeprom[82]; 851 852 sc->bfe_phyaddr = eeprom[90] & 0x1f; 853 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 854 855 sc->bfe_core_unit = 0; 856 sc->bfe_dma_offset = BFE_PCI_DMA; 857 } 858 859 static void 860 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 861 { 862 u_int32_t bar_orig, val; 863 864 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 865 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 866 867 val = CSR_READ_4(sc, BFE_SBINTVEC); 868 val |= cores; 869 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 870 871 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 872 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 873 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 874 875 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 876 } 877 878 static void 879 bfe_clear_stats(struct bfe_softc *sc) 880 { 881 uint32_t reg; 882 883 BFE_LOCK_ASSERT(sc); 884 885 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 886 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 887 CSR_READ_4(sc, reg); 888 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 889 CSR_READ_4(sc, reg); 890 } 891 892 static int 893 bfe_resetphy(struct bfe_softc *sc) 894 { 895 u_int32_t val; 896 897 bfe_writephy(sc, 0, BMCR_RESET); 898 DELAY(100); 899 bfe_readphy(sc, 0, &val); 900 if (val & BMCR_RESET) { 901 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 902 return (ENXIO); 903 } 904 return (0); 905 } 906 907 static void 908 bfe_chip_halt(struct bfe_softc *sc) 909 { 910 BFE_LOCK_ASSERT(sc); 911 /* disable interrupts - not that it actually does..*/ 912 CSR_WRITE_4(sc, BFE_IMASK, 0); 913 CSR_READ_4(sc, BFE_IMASK); 914 915 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 916 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 917 918 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 919 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 920 DELAY(10); 921 } 922 923 static void 924 bfe_chip_reset(struct bfe_softc *sc) 925 { 926 u_int32_t val; 927 928 BFE_LOCK_ASSERT(sc); 929 930 /* Set the interrupt vector for the enet core */ 931 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 932 933 /* is core up? */ 934 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 935 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 936 if (val == BFE_CLOCK) { 937 /* It is, so shut it down */ 938 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 939 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 940 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 941 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 942 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 943 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 944 100, 0); 945 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 946 } 947 948 bfe_core_reset(sc); 949 bfe_clear_stats(sc); 950 951 /* 952 * We want the phy registers to be accessible even when 953 * the driver is "downed" so initialize MDC preamble, frequency, 954 * and whether internal or external phy here. 955 */ 956 957 /* 4402 has 62.5Mhz SB clock and internal phy */ 958 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 959 960 /* Internal or external PHY? */ 961 val = CSR_READ_4(sc, BFE_DEVCTRL); 962 if (!(val & BFE_IPP)) 963 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 964 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 965 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 966 DELAY(100); 967 } 968 969 /* Enable CRC32 generation and set proper LED modes */ 970 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 971 972 /* Reset or clear powerdown control bit */ 973 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 974 975 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 976 BFE_LAZY_FC_MASK)); 977 978 /* 979 * We don't want lazy interrupts, so just send them at 980 * the end of a frame, please 981 */ 982 BFE_OR(sc, BFE_RCV_LAZY, 0); 983 984 /* Set max lengths, accounting for VLAN tags */ 985 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 986 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 987 988 /* Set watermark XXX - magic */ 989 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 990 991 /* 992 * Initialise DMA channels 993 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 994 */ 995 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 996 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 997 998 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 999 BFE_RX_CTRL_ENABLE); 1000 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1001 1002 bfe_resetphy(sc); 1003 bfe_setupphy(sc); 1004 } 1005 1006 static void 1007 bfe_core_disable(struct bfe_softc *sc) 1008 { 1009 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1010 return; 1011 1012 /* 1013 * Set reject, wait for it set, then wait for the core to stop 1014 * being busy, then set reset and reject and enable the clocks. 1015 */ 1016 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1017 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1018 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1019 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1020 BFE_RESET)); 1021 CSR_READ_4(sc, BFE_SBTMSLOW); 1022 DELAY(10); 1023 /* Leave reset and reject set */ 1024 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1025 DELAY(10); 1026 } 1027 1028 static void 1029 bfe_core_reset(struct bfe_softc *sc) 1030 { 1031 u_int32_t val; 1032 1033 /* Disable the core */ 1034 bfe_core_disable(sc); 1035 1036 /* and bring it back up */ 1037 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1038 CSR_READ_4(sc, BFE_SBTMSLOW); 1039 DELAY(10); 1040 1041 /* Chip bug, clear SERR, IB and TO if they are set. */ 1042 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1043 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1044 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1045 if (val & (BFE_IBE | BFE_TO)) 1046 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1047 1048 /* Clear reset and allow it to move through the core */ 1049 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1050 CSR_READ_4(sc, BFE_SBTMSLOW); 1051 DELAY(10); 1052 1053 /* Leave the clock set */ 1054 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1055 CSR_READ_4(sc, BFE_SBTMSLOW); 1056 DELAY(10); 1057 } 1058 1059 static void 1060 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1061 { 1062 u_int32_t val; 1063 1064 val = ((u_int32_t) data[2]) << 24; 1065 val |= ((u_int32_t) data[3]) << 16; 1066 val |= ((u_int32_t) data[4]) << 8; 1067 val |= ((u_int32_t) data[5]); 1068 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1069 val = (BFE_CAM_HI_VALID | 1070 (((u_int32_t) data[0]) << 8) | 1071 (((u_int32_t) data[1]))); 1072 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1073 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1074 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1075 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1076 } 1077 1078 static u_int 1079 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1080 { 1081 struct bfe_softc *sc = arg; 1082 1083 bfe_cam_write(sc, LLADDR(sdl), cnt + 1); 1084 1085 return (1); 1086 } 1087 1088 static void 1089 bfe_set_rx_mode(struct bfe_softc *sc) 1090 { 1091 if_t ifp = sc->bfe_ifp; 1092 u_int32_t val; 1093 1094 BFE_LOCK_ASSERT(sc); 1095 1096 val = CSR_READ_4(sc, BFE_RXCONF); 1097 1098 if (if_getflags(ifp) & IFF_PROMISC) 1099 val |= BFE_RXCONF_PROMISC; 1100 else 1101 val &= ~BFE_RXCONF_PROMISC; 1102 1103 if (if_getflags(ifp) & IFF_BROADCAST) 1104 val &= ~BFE_RXCONF_DBCAST; 1105 else 1106 val |= BFE_RXCONF_DBCAST; 1107 1108 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1109 bfe_cam_write(sc, if_getlladdr(sc->bfe_ifp), 0); 1110 1111 if (if_getflags(ifp) & IFF_ALLMULTI) 1112 val |= BFE_RXCONF_ALLMULTI; 1113 else { 1114 val &= ~BFE_RXCONF_ALLMULTI; 1115 if_foreach_llmaddr(ifp, bfe_write_maddr, sc); 1116 } 1117 1118 CSR_WRITE_4(sc, BFE_RXCONF, val); 1119 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1120 } 1121 1122 static void 1123 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1124 { 1125 struct bfe_dmamap_arg *ctx; 1126 1127 if (error != 0) 1128 return; 1129 1130 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1131 1132 ctx = (struct bfe_dmamap_arg *)arg; 1133 ctx->bfe_busaddr = segs[0].ds_addr; 1134 } 1135 1136 static void 1137 bfe_release_resources(struct bfe_softc *sc) 1138 { 1139 1140 if (sc->bfe_intrhand != NULL) 1141 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1142 1143 if (sc->bfe_irq != NULL) 1144 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1145 1146 if (sc->bfe_res != NULL) 1147 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1148 sc->bfe_res); 1149 1150 if (sc->bfe_ifp != NULL) 1151 if_free(sc->bfe_ifp); 1152 } 1153 1154 static void 1155 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1156 { 1157 long i; 1158 u_int16_t *ptr = (u_int16_t *)data; 1159 1160 for(i = 0; i < 128; i += 2) 1161 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1162 } 1163 1164 static int 1165 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1166 u_long timeout, const int clear) 1167 { 1168 u_long i; 1169 1170 for (i = 0; i < timeout; i++) { 1171 u_int32_t val = CSR_READ_4(sc, reg); 1172 1173 if (clear && !(val & bit)) 1174 break; 1175 if (!clear && (val & bit)) 1176 break; 1177 DELAY(10); 1178 } 1179 if (i == timeout) { 1180 device_printf(sc->bfe_dev, 1181 "BUG! Timeout waiting for bit %08x of register " 1182 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1183 return (-1); 1184 } 1185 return (0); 1186 } 1187 1188 static int 1189 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1190 { 1191 int err; 1192 1193 /* Clear MII ISR */ 1194 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1195 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1196 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1197 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1198 (reg << BFE_MDIO_RA_SHIFT) | 1199 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1200 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1201 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1202 1203 return (err); 1204 } 1205 1206 static int 1207 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1208 { 1209 int status; 1210 1211 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1212 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1213 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1214 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1215 (reg << BFE_MDIO_RA_SHIFT) | 1216 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1217 (val & BFE_MDIO_DATA_DATA))); 1218 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1219 1220 return (status); 1221 } 1222 1223 /* 1224 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1225 * twice 1226 */ 1227 static int 1228 bfe_setupphy(struct bfe_softc *sc) 1229 { 1230 u_int32_t val; 1231 1232 /* Enable activity LED */ 1233 bfe_readphy(sc, 26, &val); 1234 bfe_writephy(sc, 26, val & 0x7fff); 1235 bfe_readphy(sc, 26, &val); 1236 1237 /* Enable traffic meter LED mode */ 1238 bfe_readphy(sc, 27, &val); 1239 bfe_writephy(sc, 27, val | (1 << 6)); 1240 1241 return (0); 1242 } 1243 1244 static void 1245 bfe_stats_update(struct bfe_softc *sc) 1246 { 1247 struct bfe_hw_stats *stats; 1248 if_t ifp; 1249 uint32_t mib[BFE_MIB_CNT]; 1250 uint32_t reg, *val; 1251 1252 BFE_LOCK_ASSERT(sc); 1253 1254 val = mib; 1255 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 1256 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1257 *val++ = CSR_READ_4(sc, reg); 1258 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1259 *val++ = CSR_READ_4(sc, reg); 1260 1261 ifp = sc->bfe_ifp; 1262 stats = &sc->bfe_stats; 1263 /* Tx stat. */ 1264 stats->tx_good_octets += mib[MIB_TX_GOOD_O]; 1265 stats->tx_good_frames += mib[MIB_TX_GOOD_P]; 1266 stats->tx_octets += mib[MIB_TX_O]; 1267 stats->tx_frames += mib[MIB_TX_P]; 1268 stats->tx_bcast_frames += mib[MIB_TX_BCAST]; 1269 stats->tx_mcast_frames += mib[MIB_TX_MCAST]; 1270 stats->tx_pkts_64 += mib[MIB_TX_64]; 1271 stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; 1272 stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; 1273 stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; 1274 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; 1275 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; 1276 stats->tx_jabbers += mib[MIB_TX_JABBER]; 1277 stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; 1278 stats->tx_frag_frames += mib[MIB_TX_FRAG]; 1279 stats->tx_underruns += mib[MIB_TX_URUNS]; 1280 stats->tx_colls += mib[MIB_TX_TCOLS]; 1281 stats->tx_single_colls += mib[MIB_TX_SCOLS]; 1282 stats->tx_multi_colls += mib[MIB_TX_MCOLS]; 1283 stats->tx_excess_colls += mib[MIB_TX_ECOLS]; 1284 stats->tx_late_colls += mib[MIB_TX_LCOLS]; 1285 stats->tx_deferrals += mib[MIB_TX_DEFERED]; 1286 stats->tx_carrier_losts += mib[MIB_TX_CLOST]; 1287 stats->tx_pause_frames += mib[MIB_TX_PAUSE]; 1288 /* Rx stat. */ 1289 stats->rx_good_octets += mib[MIB_RX_GOOD_O]; 1290 stats->rx_good_frames += mib[MIB_RX_GOOD_P]; 1291 stats->rx_octets += mib[MIB_RX_O]; 1292 stats->rx_frames += mib[MIB_RX_P]; 1293 stats->rx_bcast_frames += mib[MIB_RX_BCAST]; 1294 stats->rx_mcast_frames += mib[MIB_RX_MCAST]; 1295 stats->rx_pkts_64 += mib[MIB_RX_64]; 1296 stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; 1297 stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; 1298 stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; 1299 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; 1300 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; 1301 stats->rx_jabbers += mib[MIB_RX_JABBER]; 1302 stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; 1303 stats->rx_frag_frames += mib[MIB_RX_FRAG]; 1304 stats->rx_missed_frames += mib[MIB_RX_MISS]; 1305 stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; 1306 stats->rx_runts += mib[MIB_RX_USIZE]; 1307 stats->rx_crc_errs += mib[MIB_RX_CRC]; 1308 stats->rx_align_errs += mib[MIB_RX_ALIGN]; 1309 stats->rx_symbol_errs += mib[MIB_RX_SYM]; 1310 stats->rx_pause_frames += mib[MIB_RX_PAUSE]; 1311 stats->rx_control_frames += mib[MIB_RX_NPAUSE]; 1312 1313 /* Update counters in ifnet. */ 1314 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]); 1315 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]); 1316 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] + 1317 (u_long)mib[MIB_TX_ECOLS] + 1318 (u_long)mib[MIB_TX_DEFERED] + 1319 (u_long)mib[MIB_TX_CLOST]); 1320 1321 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]); 1322 1323 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] + 1324 mib[MIB_RX_MISS] + 1325 mib[MIB_RX_CRCA] + 1326 mib[MIB_RX_USIZE] + 1327 mib[MIB_RX_CRC] + 1328 mib[MIB_RX_ALIGN] + 1329 mib[MIB_RX_SYM]); 1330 } 1331 1332 static void 1333 bfe_txeof(struct bfe_softc *sc) 1334 { 1335 struct bfe_tx_data *r; 1336 if_t ifp; 1337 int i, chipidx; 1338 1339 BFE_LOCK_ASSERT(sc); 1340 1341 ifp = sc->bfe_ifp; 1342 1343 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1344 chipidx /= sizeof(struct bfe_desc); 1345 1346 i = sc->bfe_tx_cons; 1347 if (i == chipidx) 1348 return; 1349 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1350 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1351 /* Go through the mbufs and free those that have been transmitted */ 1352 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1353 r = &sc->bfe_tx_ring[i]; 1354 sc->bfe_tx_cnt--; 1355 if (r->bfe_mbuf == NULL) 1356 continue; 1357 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1358 BUS_DMASYNC_POSTWRITE); 1359 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1360 1361 m_freem(r->bfe_mbuf); 1362 r->bfe_mbuf = NULL; 1363 } 1364 1365 if (i != sc->bfe_tx_cons) { 1366 /* we freed up some mbufs */ 1367 sc->bfe_tx_cons = i; 1368 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1369 } 1370 1371 if (sc->bfe_tx_cnt == 0) 1372 sc->bfe_watchdog_timer = 0; 1373 } 1374 1375 /* Pass a received packet up the stack */ 1376 static void 1377 bfe_rxeof(struct bfe_softc *sc) 1378 { 1379 struct mbuf *m; 1380 if_t ifp; 1381 struct bfe_rxheader *rxheader; 1382 struct bfe_rx_data *r; 1383 int cons, prog; 1384 u_int32_t status, current, len, flags; 1385 1386 BFE_LOCK_ASSERT(sc); 1387 cons = sc->bfe_rx_cons; 1388 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1389 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1390 1391 ifp = sc->bfe_ifp; 1392 1393 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1394 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1395 1396 for (prog = 0; current != cons; prog++, 1397 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1398 r = &sc->bfe_rx_ring[cons]; 1399 m = r->bfe_mbuf; 1400 /* 1401 * Rx status should be read from mbuf such that we can't 1402 * delay bus_dmamap_sync(9). This hardware limiation 1403 * results in inefficient mbuf usage as bfe(4) couldn't 1404 * reuse mapped buffer from errored frame. 1405 */ 1406 if (bfe_list_newbuf(sc, cons) != 0) { 1407 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1408 bfe_discard_buf(sc, cons); 1409 continue; 1410 } 1411 rxheader = mtod(m, struct bfe_rxheader*); 1412 len = le16toh(rxheader->len); 1413 flags = le16toh(rxheader->flags); 1414 1415 /* Remove CRC bytes. */ 1416 len -= ETHER_CRC_LEN; 1417 1418 /* flag an error and try again */ 1419 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1420 m_freem(m); 1421 continue; 1422 } 1423 1424 /* Make sure to skip header bytes written by hardware. */ 1425 m_adj(m, BFE_RX_OFFSET); 1426 m->m_len = m->m_pkthdr.len = len; 1427 1428 m->m_pkthdr.rcvif = ifp; 1429 BFE_UNLOCK(sc); 1430 if_input(ifp, m); 1431 BFE_LOCK(sc); 1432 } 1433 1434 if (prog > 0) { 1435 sc->bfe_rx_cons = cons; 1436 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1437 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1438 } 1439 } 1440 1441 static void 1442 bfe_intr(void *xsc) 1443 { 1444 struct bfe_softc *sc = xsc; 1445 if_t ifp; 1446 u_int32_t istat; 1447 1448 ifp = sc->bfe_ifp; 1449 1450 BFE_LOCK(sc); 1451 1452 istat = CSR_READ_4(sc, BFE_ISTAT); 1453 1454 /* 1455 * Defer unsolicited interrupts - This is necessary because setting the 1456 * chips interrupt mask register to 0 doesn't actually stop the 1457 * interrupts 1458 */ 1459 istat &= BFE_IMASK_DEF; 1460 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1461 CSR_READ_4(sc, BFE_ISTAT); 1462 1463 /* not expecting this interrupt, disregard it */ 1464 if (istat == 0 || (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1465 BFE_UNLOCK(sc); 1466 return; 1467 } 1468 1469 /* A packet was received */ 1470 if (istat & BFE_ISTAT_RX) 1471 bfe_rxeof(sc); 1472 1473 /* A packet was sent */ 1474 if (istat & BFE_ISTAT_TX) 1475 bfe_txeof(sc); 1476 1477 if (istat & BFE_ISTAT_ERRORS) { 1478 if (istat & BFE_ISTAT_DSCE) { 1479 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1480 bfe_stop(sc); 1481 BFE_UNLOCK(sc); 1482 return; 1483 } 1484 1485 if (istat & BFE_ISTAT_DPE) { 1486 device_printf(sc->bfe_dev, 1487 "Descriptor Protocol Error\n"); 1488 bfe_stop(sc); 1489 BFE_UNLOCK(sc); 1490 return; 1491 } 1492 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1493 bfe_init_locked(sc); 1494 } 1495 1496 /* We have packets pending, fire them out */ 1497 if (!if_sendq_empty(ifp)) 1498 bfe_start_locked(ifp); 1499 1500 BFE_UNLOCK(sc); 1501 } 1502 1503 static int 1504 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1505 { 1506 struct bfe_desc *d; 1507 struct bfe_tx_data *r, *r1; 1508 struct mbuf *m; 1509 bus_dmamap_t map; 1510 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1511 uint32_t cur, si; 1512 int error, i, nsegs; 1513 1514 BFE_LOCK_ASSERT(sc); 1515 1516 M_ASSERTPKTHDR((*m_head)); 1517 1518 si = cur = sc->bfe_tx_prod; 1519 r = &sc->bfe_tx_ring[cur]; 1520 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1521 txsegs, &nsegs, 0); 1522 if (error == EFBIG) { 1523 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); 1524 if (m == NULL) { 1525 m_freem(*m_head); 1526 *m_head = NULL; 1527 return (ENOMEM); 1528 } 1529 *m_head = m; 1530 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1531 *m_head, txsegs, &nsegs, 0); 1532 if (error != 0) { 1533 m_freem(*m_head); 1534 *m_head = NULL; 1535 return (error); 1536 } 1537 } else if (error != 0) 1538 return (error); 1539 if (nsegs == 0) { 1540 m_freem(*m_head); 1541 *m_head = NULL; 1542 return (EIO); 1543 } 1544 1545 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1546 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1547 return (ENOBUFS); 1548 } 1549 1550 for (i = 0; i < nsegs; i++) { 1551 d = &sc->bfe_tx_list[cur]; 1552 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1553 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1554 if (cur == BFE_TX_LIST_CNT - 1) 1555 /* 1556 * Tell the chip to wrap to the start of 1557 * the descriptor list. 1558 */ 1559 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1560 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1561 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1562 BFE_PCI_DMA); 1563 BFE_INC(cur, BFE_TX_LIST_CNT); 1564 } 1565 1566 /* Update producer index. */ 1567 sc->bfe_tx_prod = cur; 1568 1569 /* Set EOF on the last descriptor. */ 1570 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1571 d = &sc->bfe_tx_list[cur]; 1572 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1573 1574 /* Lastly set SOF on the first descriptor to avoid races. */ 1575 d = &sc->bfe_tx_list[si]; 1576 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1577 1578 r1 = &sc->bfe_tx_ring[cur]; 1579 map = r->bfe_map; 1580 r->bfe_map = r1->bfe_map; 1581 r1->bfe_map = map; 1582 r1->bfe_mbuf = *m_head; 1583 sc->bfe_tx_cnt += nsegs; 1584 1585 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1586 1587 return (0); 1588 } 1589 1590 /* 1591 * Set up to transmit a packet. 1592 */ 1593 static void 1594 bfe_start(if_t ifp) 1595 { 1596 BFE_LOCK((struct bfe_softc *)if_getsoftc(ifp)); 1597 bfe_start_locked(ifp); 1598 BFE_UNLOCK((struct bfe_softc *)if_getsoftc(ifp)); 1599 } 1600 1601 /* 1602 * Set up to transmit a packet. The softc is already locked. 1603 */ 1604 static void 1605 bfe_start_locked(if_t ifp) 1606 { 1607 struct bfe_softc *sc; 1608 struct mbuf *m_head; 1609 int queued; 1610 1611 sc = if_getsoftc(ifp); 1612 1613 BFE_LOCK_ASSERT(sc); 1614 1615 /* 1616 * Not much point trying to send if the link is down 1617 * or we have nothing to send. 1618 */ 1619 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1620 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1621 return; 1622 1623 for (queued = 0; !if_sendq_empty(ifp) && 1624 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1625 m_head = if_dequeue(ifp); 1626 if (m_head == NULL) 1627 break; 1628 1629 /* 1630 * Pack the data into the tx ring. If we dont have 1631 * enough room, let the chip drain the ring. 1632 */ 1633 if (bfe_encap(sc, &m_head)) { 1634 if (m_head == NULL) 1635 break; 1636 if_sendq_prepend(ifp, m_head); 1637 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1638 break; 1639 } 1640 1641 queued++; 1642 1643 /* 1644 * If there's a BPF listener, bounce a copy of this frame 1645 * to him. 1646 */ 1647 BPF_MTAP(ifp, m_head); 1648 } 1649 1650 if (queued) { 1651 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1653 /* Transmit - twice due to apparent hardware bug */ 1654 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1655 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1656 /* 1657 * XXX It seems the following write is not necessary 1658 * to kick Tx command. What might be required would be 1659 * a way flushing PCI posted write. Reading the register 1660 * back ensures the flush operation. In addition, 1661 * hardware will execute PCI posted write in the long 1662 * run and watchdog timer for the kick command was set 1663 * to 5 seconds. Therefore I think the second write 1664 * access is not necessary or could be replaced with 1665 * read operation. 1666 */ 1667 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1668 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1669 1670 /* 1671 * Set a timeout in case the chip goes out to lunch. 1672 */ 1673 sc->bfe_watchdog_timer = 5; 1674 } 1675 } 1676 1677 static void 1678 bfe_init(void *xsc) 1679 { 1680 BFE_LOCK((struct bfe_softc *)xsc); 1681 bfe_init_locked(xsc); 1682 BFE_UNLOCK((struct bfe_softc *)xsc); 1683 } 1684 1685 static void 1686 bfe_init_locked(void *xsc) 1687 { 1688 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1689 if_t ifp = sc->bfe_ifp; 1690 struct mii_data *mii; 1691 1692 BFE_LOCK_ASSERT(sc); 1693 1694 mii = device_get_softc(sc->bfe_miibus); 1695 1696 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1697 return; 1698 1699 bfe_stop(sc); 1700 bfe_chip_reset(sc); 1701 1702 if (bfe_list_rx_init(sc) == ENOBUFS) { 1703 device_printf(sc->bfe_dev, 1704 "%s: Not enough memory for list buffers\n", __func__); 1705 bfe_stop(sc); 1706 return; 1707 } 1708 bfe_list_tx_init(sc); 1709 1710 bfe_set_rx_mode(sc); 1711 1712 /* Enable the chip and core */ 1713 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1714 /* Enable interrupts */ 1715 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1716 1717 /* Clear link state and change media. */ 1718 sc->bfe_flags &= ~BFE_FLAG_LINK; 1719 mii_mediachg(mii); 1720 1721 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1722 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1723 1724 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1725 } 1726 1727 /* 1728 * Set media options. 1729 */ 1730 static int 1731 bfe_ifmedia_upd(if_t ifp) 1732 { 1733 struct bfe_softc *sc; 1734 struct mii_data *mii; 1735 struct mii_softc *miisc; 1736 int error; 1737 1738 sc = if_getsoftc(ifp); 1739 BFE_LOCK(sc); 1740 1741 mii = device_get_softc(sc->bfe_miibus); 1742 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1743 PHY_RESET(miisc); 1744 error = mii_mediachg(mii); 1745 BFE_UNLOCK(sc); 1746 1747 return (error); 1748 } 1749 1750 /* 1751 * Report current media status. 1752 */ 1753 static void 1754 bfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1755 { 1756 struct bfe_softc *sc = if_getsoftc(ifp); 1757 struct mii_data *mii; 1758 1759 BFE_LOCK(sc); 1760 mii = device_get_softc(sc->bfe_miibus); 1761 mii_pollstat(mii); 1762 ifmr->ifm_active = mii->mii_media_active; 1763 ifmr->ifm_status = mii->mii_media_status; 1764 BFE_UNLOCK(sc); 1765 } 1766 1767 static int 1768 bfe_ioctl(if_t ifp, u_long command, caddr_t data) 1769 { 1770 struct bfe_softc *sc = if_getsoftc(ifp); 1771 struct ifreq *ifr = (struct ifreq *) data; 1772 struct mii_data *mii; 1773 int error = 0; 1774 1775 switch (command) { 1776 case SIOCSIFFLAGS: 1777 BFE_LOCK(sc); 1778 if (if_getflags(ifp) & IFF_UP) { 1779 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1780 bfe_set_rx_mode(sc); 1781 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1782 bfe_init_locked(sc); 1783 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1784 bfe_stop(sc); 1785 BFE_UNLOCK(sc); 1786 break; 1787 case SIOCADDMULTI: 1788 case SIOCDELMULTI: 1789 BFE_LOCK(sc); 1790 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1791 bfe_set_rx_mode(sc); 1792 BFE_UNLOCK(sc); 1793 break; 1794 case SIOCGIFMEDIA: 1795 case SIOCSIFMEDIA: 1796 mii = device_get_softc(sc->bfe_miibus); 1797 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1798 break; 1799 default: 1800 error = ether_ioctl(ifp, command, data); 1801 break; 1802 } 1803 1804 return (error); 1805 } 1806 1807 static void 1808 bfe_watchdog(struct bfe_softc *sc) 1809 { 1810 if_t ifp; 1811 1812 BFE_LOCK_ASSERT(sc); 1813 1814 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1815 return; 1816 1817 ifp = sc->bfe_ifp; 1818 1819 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1820 1821 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1822 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1823 bfe_init_locked(sc); 1824 1825 if (!if_sendq_empty(ifp)) 1826 bfe_start_locked(ifp); 1827 } 1828 1829 static void 1830 bfe_tick(void *xsc) 1831 { 1832 struct bfe_softc *sc = xsc; 1833 struct mii_data *mii; 1834 1835 BFE_LOCK_ASSERT(sc); 1836 1837 mii = device_get_softc(sc->bfe_miibus); 1838 mii_tick(mii); 1839 bfe_stats_update(sc); 1840 bfe_watchdog(sc); 1841 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1842 } 1843 1844 /* 1845 * Stop the adapter and free any mbufs allocated to the 1846 * RX and TX lists. 1847 */ 1848 static void 1849 bfe_stop(struct bfe_softc *sc) 1850 { 1851 if_t ifp; 1852 1853 BFE_LOCK_ASSERT(sc); 1854 1855 ifp = sc->bfe_ifp; 1856 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1857 sc->bfe_flags &= ~BFE_FLAG_LINK; 1858 callout_stop(&sc->bfe_stat_co); 1859 sc->bfe_watchdog_timer = 0; 1860 1861 bfe_chip_halt(sc); 1862 bfe_tx_ring_free(sc); 1863 bfe_rx_ring_free(sc); 1864 } 1865 1866 static int 1867 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS) 1868 { 1869 struct bfe_softc *sc; 1870 struct bfe_hw_stats *stats; 1871 int error, result; 1872 1873 result = -1; 1874 error = sysctl_handle_int(oidp, &result, 0, req); 1875 1876 if (error != 0 || req->newptr == NULL) 1877 return (error); 1878 1879 if (result != 1) 1880 return (error); 1881 1882 sc = (struct bfe_softc *)arg1; 1883 stats = &sc->bfe_stats; 1884 1885 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); 1886 printf("Transmit good octets : %ju\n", 1887 (uintmax_t)stats->tx_good_octets); 1888 printf("Transmit good frames : %ju\n", 1889 (uintmax_t)stats->tx_good_frames); 1890 printf("Transmit octets : %ju\n", 1891 (uintmax_t)stats->tx_octets); 1892 printf("Transmit frames : %ju\n", 1893 (uintmax_t)stats->tx_frames); 1894 printf("Transmit broadcast frames : %ju\n", 1895 (uintmax_t)stats->tx_bcast_frames); 1896 printf("Transmit multicast frames : %ju\n", 1897 (uintmax_t)stats->tx_mcast_frames); 1898 printf("Transmit frames 64 bytes : %ju\n", 1899 (uint64_t)stats->tx_pkts_64); 1900 printf("Transmit frames 65 to 127 bytes : %ju\n", 1901 (uint64_t)stats->tx_pkts_65_127); 1902 printf("Transmit frames 128 to 255 bytes : %ju\n", 1903 (uint64_t)stats->tx_pkts_128_255); 1904 printf("Transmit frames 256 to 511 bytes : %ju\n", 1905 (uint64_t)stats->tx_pkts_256_511); 1906 printf("Transmit frames 512 to 1023 bytes : %ju\n", 1907 (uint64_t)stats->tx_pkts_512_1023); 1908 printf("Transmit frames 1024 to max bytes : %ju\n", 1909 (uint64_t)stats->tx_pkts_1024_max); 1910 printf("Transmit jabber errors : %u\n", stats->tx_jabbers); 1911 printf("Transmit oversized frames : %ju\n", 1912 (uint64_t)stats->tx_oversize_frames); 1913 printf("Transmit fragmented frames : %ju\n", 1914 (uint64_t)stats->tx_frag_frames); 1915 printf("Transmit underruns : %u\n", stats->tx_colls); 1916 printf("Transmit total collisions : %u\n", stats->tx_single_colls); 1917 printf("Transmit single collisions : %u\n", stats->tx_single_colls); 1918 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); 1919 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); 1920 printf("Transmit late collisions : %u\n", stats->tx_late_colls); 1921 printf("Transmit deferrals : %u\n", stats->tx_deferrals); 1922 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); 1923 printf("Transmit pause frames : %u\n", stats->tx_pause_frames); 1924 1925 printf("Receive good octets : %ju\n", 1926 (uintmax_t)stats->rx_good_octets); 1927 printf("Receive good frames : %ju\n", 1928 (uintmax_t)stats->rx_good_frames); 1929 printf("Receive octets : %ju\n", 1930 (uintmax_t)stats->rx_octets); 1931 printf("Receive frames : %ju\n", 1932 (uintmax_t)stats->rx_frames); 1933 printf("Receive broadcast frames : %ju\n", 1934 (uintmax_t)stats->rx_bcast_frames); 1935 printf("Receive multicast frames : %ju\n", 1936 (uintmax_t)stats->rx_mcast_frames); 1937 printf("Receive frames 64 bytes : %ju\n", 1938 (uint64_t)stats->rx_pkts_64); 1939 printf("Receive frames 65 to 127 bytes : %ju\n", 1940 (uint64_t)stats->rx_pkts_65_127); 1941 printf("Receive frames 128 to 255 bytes : %ju\n", 1942 (uint64_t)stats->rx_pkts_128_255); 1943 printf("Receive frames 256 to 511 bytes : %ju\n", 1944 (uint64_t)stats->rx_pkts_256_511); 1945 printf("Receive frames 512 to 1023 bytes : %ju\n", 1946 (uint64_t)stats->rx_pkts_512_1023); 1947 printf("Receive frames 1024 to max bytes : %ju\n", 1948 (uint64_t)stats->rx_pkts_1024_max); 1949 printf("Receive jabber errors : %u\n", stats->rx_jabbers); 1950 printf("Receive oversized frames : %ju\n", 1951 (uint64_t)stats->rx_oversize_frames); 1952 printf("Receive fragmented frames : %ju\n", 1953 (uint64_t)stats->rx_frag_frames); 1954 printf("Receive missed frames : %u\n", stats->rx_missed_frames); 1955 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); 1956 printf("Receive undersized frames : %u\n", stats->rx_runts); 1957 printf("Receive CRC errors : %u\n", stats->rx_crc_errs); 1958 printf("Receive align errors : %u\n", stats->rx_align_errs); 1959 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); 1960 printf("Receive pause frames : %u\n", stats->rx_pause_frames); 1961 printf("Receive control frames : %u\n", stats->rx_control_frames); 1962 1963 return (error); 1964 } 1965