1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 #include <sys/bus.h> 59 #include <sys/rman.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 #include "miidevs.h" 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <dev/bfe/if_bfereg.h> 69 70 MODULE_DEPEND(bfe, pci, 1, 1, 1); 71 MODULE_DEPEND(bfe, ether, 1, 1, 1); 72 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79 static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85 }; 86 87 static int bfe_probe (device_t); 88 static int bfe_attach (device_t); 89 static int bfe_detach (device_t); 90 static int bfe_suspend (device_t); 91 static int bfe_resume (device_t); 92 static void bfe_release_resources (struct bfe_softc *); 93 static void bfe_intr (void *); 94 static void bfe_start (struct ifnet *); 95 static void bfe_start_locked (struct ifnet *); 96 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97 static void bfe_init (void *); 98 static void bfe_init_locked (void *); 99 static void bfe_stop (struct bfe_softc *); 100 static void bfe_watchdog (struct ifnet *); 101 static int bfe_shutdown (device_t); 102 static void bfe_tick (void *); 103 static void bfe_txeof (struct bfe_softc *); 104 static void bfe_rxeof (struct bfe_softc *); 105 static void bfe_set_rx_mode (struct bfe_softc *); 106 static int bfe_list_rx_init (struct bfe_softc *); 107 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free (struct bfe_softc *); 109 110 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111 static int bfe_ifmedia_upd (struct ifnet *); 112 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg (device_t, int, int); 114 static int bfe_miibus_writereg (device_t, int, int, int); 115 static void bfe_miibus_statchg (device_t); 116 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118 static void bfe_get_config (struct bfe_softc *sc); 119 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120 static void bfe_stats_update (struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124 static int bfe_resetphy (struct bfe_softc *); 125 static int bfe_setupphy (struct bfe_softc *); 126 static void bfe_chip_reset (struct bfe_softc *); 127 static void bfe_chip_halt (struct bfe_softc *); 128 static void bfe_core_reset (struct bfe_softc *); 129 static void bfe_core_disable (struct bfe_softc *); 130 static int bfe_dma_alloc (device_t); 131 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 DEVMETHOD(device_suspend, bfe_suspend), 142 DEVMETHOD(device_resume, bfe_resume), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160 }; 161 162 static devclass_t bfe_devclass; 163 164 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167 /* 168 * Probe for a Broadcom 4401 chip. 169 */ 170 static int 171 bfe_probe(device_t dev) 172 { 173 struct bfe_type *t; 174 struct bfe_softc *sc; 175 176 t = bfe_devs; 177 178 sc = device_get_softc(dev); 179 bzero(sc, sizeof(struct bfe_softc)); 180 sc->bfe_unit = device_get_unit(dev); 181 sc->bfe_dev = dev; 182 183 while(t->bfe_name != NULL) { 184 if ((pci_get_vendor(dev) == t->bfe_vid) && 185 (pci_get_device(dev) == t->bfe_did)) { 186 device_set_desc_copy(dev, t->bfe_name); 187 return (BUS_PROBE_DEFAULT); 188 } 189 t++; 190 } 191 192 return (ENXIO); 193 } 194 195 static int 196 bfe_dma_alloc(device_t dev) 197 { 198 struct bfe_softc *sc; 199 int error, i; 200 201 sc = device_get_softc(dev); 202 203 /* 204 * parent tag. Apparently the chip cannot handle any DMA address 205 * greater than 1GB. 206 */ 207 error = bus_dma_tag_create(NULL, /* parent */ 208 4096, 0, /* alignment, boundary */ 209 0x3FFFFFFF, /* lowaddr */ 210 BUS_SPACE_MAXADDR, /* highaddr */ 211 NULL, NULL, /* filter, filterarg */ 212 MAXBSIZE, /* maxsize */ 213 BUS_SPACE_UNRESTRICTED, /* num of segments */ 214 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 215 0, /* flags */ 216 NULL, NULL, /* lockfunc, lockarg */ 217 &sc->bfe_parent_tag); 218 219 /* tag for TX ring */ 220 error = bus_dma_tag_create(sc->bfe_parent_tag, 221 4096, 0, 222 BUS_SPACE_MAXADDR, 223 BUS_SPACE_MAXADDR, 224 NULL, NULL, 225 BFE_TX_LIST_SIZE, 226 1, 227 BUS_SPACE_MAXSIZE_32BIT, 228 0, 229 NULL, NULL, 230 &sc->bfe_tx_tag); 231 232 if (error) { 233 device_printf(dev, "could not allocate dma tag\n"); 234 return (ENOMEM); 235 } 236 237 /* tag for RX ring */ 238 error = bus_dma_tag_create(sc->bfe_parent_tag, 239 4096, 0, 240 BUS_SPACE_MAXADDR, 241 BUS_SPACE_MAXADDR, 242 NULL, NULL, 243 BFE_RX_LIST_SIZE, 244 1, 245 BUS_SPACE_MAXSIZE_32BIT, 246 0, 247 NULL, NULL, 248 &sc->bfe_rx_tag); 249 250 if (error) { 251 device_printf(dev, "could not allocate dma tag\n"); 252 return (ENOMEM); 253 } 254 255 /* tag for mbufs */ 256 error = bus_dma_tag_create(sc->bfe_parent_tag, 257 ETHER_ALIGN, 0, 258 BUS_SPACE_MAXADDR, 259 BUS_SPACE_MAXADDR, 260 NULL, NULL, 261 MCLBYTES, 262 1, 263 BUS_SPACE_MAXSIZE_32BIT, 264 BUS_DMA_ALLOCNOW, 265 NULL, NULL, 266 &sc->bfe_tag); 267 268 if (error) { 269 device_printf(dev, "could not allocate dma tag\n"); 270 return (ENOMEM); 271 } 272 273 /* pre allocate dmamaps for RX list */ 274 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 275 error = bus_dmamap_create(sc->bfe_tag, 0, 276 &sc->bfe_rx_ring[i].bfe_map); 277 if (error) { 278 device_printf(dev, "cannot create DMA map for RX\n"); 279 return (ENOMEM); 280 } 281 } 282 283 /* pre allocate dmamaps for TX list */ 284 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 285 error = bus_dmamap_create(sc->bfe_tag, 0, 286 &sc->bfe_tx_ring[i].bfe_map); 287 if (error) { 288 device_printf(dev, "cannot create DMA map for TX\n"); 289 return (ENOMEM); 290 } 291 } 292 293 /* Alloc dma for rx ring */ 294 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 295 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 296 297 if(error) 298 return (ENOMEM); 299 300 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 301 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 302 sc->bfe_rx_list, sizeof(struct bfe_desc), 303 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 304 305 if(error) 306 return (ENOMEM); 307 308 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 309 310 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 311 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 312 if (error) 313 return (ENOMEM); 314 315 316 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 317 sc->bfe_tx_list, sizeof(struct bfe_desc), 318 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 319 if(error) 320 return (ENOMEM); 321 322 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 323 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 324 325 return (0); 326 } 327 328 static int 329 bfe_attach(device_t dev) 330 { 331 struct ifnet *ifp = NULL; 332 struct bfe_softc *sc; 333 int unit, error = 0, rid; 334 335 sc = device_get_softc(dev); 336 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 337 MTX_DEF); 338 339 unit = device_get_unit(dev); 340 sc->bfe_dev = dev; 341 sc->bfe_unit = unit; 342 343 /* 344 * Map control/status registers. 345 */ 346 pci_enable_busmaster(dev); 347 348 rid = BFE_PCI_MEMLO; 349 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 350 RF_ACTIVE); 351 if (sc->bfe_res == NULL) { 352 printf ("bfe%d: couldn't map memory\n", unit); 353 error = ENXIO; 354 goto fail; 355 } 356 357 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 358 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 359 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 360 361 /* Allocate interrupt */ 362 rid = 0; 363 364 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 365 RF_SHAREABLE | RF_ACTIVE); 366 if (sc->bfe_irq == NULL) { 367 printf("bfe%d: couldn't map interrupt\n", unit); 368 error = ENXIO; 369 goto fail; 370 } 371 372 if (bfe_dma_alloc(dev)) { 373 printf("bfe%d: failed to allocate DMA resources\n", 374 sc->bfe_unit); 375 error = ENXIO; 376 goto fail; 377 } 378 379 /* Set up ifnet structure */ 380 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 381 if (ifp == NULL) { 382 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 383 error = ENOSPC; 384 goto fail; 385 } 386 ifp->if_softc = sc; 387 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 389 ifp->if_ioctl = bfe_ioctl; 390 ifp->if_start = bfe_start; 391 ifp->if_watchdog = bfe_watchdog; 392 ifp->if_init = bfe_init; 393 ifp->if_mtu = ETHERMTU; 394 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 395 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 396 IFQ_SET_READY(&ifp->if_snd); 397 398 bfe_get_config(sc); 399 400 /* Reset the chip and turn on the PHY */ 401 BFE_LOCK(sc); 402 bfe_chip_reset(sc); 403 BFE_UNLOCK(sc); 404 405 if (mii_phy_probe(dev, &sc->bfe_miibus, 406 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 407 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 408 error = ENXIO; 409 goto fail; 410 } 411 412 ether_ifattach(ifp, sc->bfe_enaddr); 413 callout_handle_init(&sc->bfe_stat_ch); 414 415 /* 416 * Tell the upper layer(s) we support long frames. 417 */ 418 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 419 ifp->if_capabilities |= IFCAP_VLAN_MTU; 420 ifp->if_capenable |= IFCAP_VLAN_MTU; 421 422 /* 423 * Hook interrupt last to avoid having to lock softc 424 */ 425 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 426 NULL, bfe_intr, sc, &sc->bfe_intrhand); 427 428 if (error) { 429 printf("bfe%d: couldn't set up irq\n", unit); 430 goto fail; 431 } 432 fail: 433 if (error) 434 bfe_release_resources(sc); 435 return (error); 436 } 437 438 static int 439 bfe_detach(device_t dev) 440 { 441 struct bfe_softc *sc; 442 struct ifnet *ifp; 443 444 sc = device_get_softc(dev); 445 446 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 447 BFE_LOCK(sc); 448 449 ifp = sc->bfe_ifp; 450 451 if (device_is_attached(dev)) { 452 bfe_stop(sc); 453 ether_ifdetach(ifp); 454 } 455 456 bfe_chip_reset(sc); 457 458 bus_generic_detach(dev); 459 if(sc->bfe_miibus != NULL) 460 device_delete_child(dev, sc->bfe_miibus); 461 462 bfe_release_resources(sc); 463 BFE_UNLOCK(sc); 464 mtx_destroy(&sc->bfe_mtx); 465 466 return (0); 467 } 468 469 /* 470 * Stop all chip I/O so that the kernel's probe routines don't 471 * get confused by errant DMAs when rebooting. 472 */ 473 static int 474 bfe_shutdown(device_t dev) 475 { 476 struct bfe_softc *sc; 477 478 sc = device_get_softc(dev); 479 BFE_LOCK(sc); 480 bfe_stop(sc); 481 482 BFE_UNLOCK(sc); 483 484 return (0); 485 } 486 487 static int 488 bfe_suspend(device_t dev) 489 { 490 struct bfe_softc *sc; 491 492 sc = device_get_softc(dev); 493 BFE_LOCK(sc); 494 bfe_stop(sc); 495 BFE_UNLOCK(sc); 496 497 return (0); 498 } 499 500 static int 501 bfe_resume(device_t dev) 502 { 503 struct bfe_softc *sc; 504 struct ifnet *ifp; 505 506 sc = device_get_softc(dev); 507 ifp = sc->bfe_ifp; 508 BFE_LOCK(sc); 509 bfe_chip_reset(sc); 510 if (ifp->if_flags & IFF_UP) { 511 bfe_init_locked(sc); 512 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 513 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 514 bfe_start_locked(ifp); 515 } 516 BFE_UNLOCK(sc); 517 518 return (0); 519 } 520 521 static int 522 bfe_miibus_readreg(device_t dev, int phy, int reg) 523 { 524 struct bfe_softc *sc; 525 u_int32_t ret; 526 527 sc = device_get_softc(dev); 528 if(phy != sc->bfe_phyaddr) 529 return (0); 530 bfe_readphy(sc, reg, &ret); 531 532 return (ret); 533 } 534 535 static int 536 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 537 { 538 struct bfe_softc *sc; 539 540 sc = device_get_softc(dev); 541 if(phy != sc->bfe_phyaddr) 542 return (0); 543 bfe_writephy(sc, reg, val); 544 545 return (0); 546 } 547 548 static void 549 bfe_miibus_statchg(device_t dev) 550 { 551 return; 552 } 553 554 static void 555 bfe_tx_ring_free(struct bfe_softc *sc) 556 { 557 int i; 558 559 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 560 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 561 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 562 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 563 bus_dmamap_unload(sc->bfe_tag, 564 sc->bfe_tx_ring[i].bfe_map); 565 } 566 } 567 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 568 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 569 } 570 571 static void 572 bfe_rx_ring_free(struct bfe_softc *sc) 573 { 574 int i; 575 576 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 577 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 578 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 579 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 580 bus_dmamap_unload(sc->bfe_tag, 581 sc->bfe_rx_ring[i].bfe_map); 582 } 583 } 584 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 585 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 586 } 587 588 static int 589 bfe_list_rx_init(struct bfe_softc *sc) 590 { 591 int i; 592 593 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 594 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 595 return (ENOBUFS); 596 } 597 598 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 599 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 600 601 sc->bfe_rx_cons = 0; 602 603 return (0); 604 } 605 606 static int 607 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 608 { 609 struct bfe_rxheader *rx_header; 610 struct bfe_desc *d; 611 struct bfe_data *r; 612 u_int32_t ctrl; 613 int error; 614 615 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 616 return (EINVAL); 617 618 if(m == NULL) { 619 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 620 if(m == NULL) 621 return (ENOBUFS); 622 m->m_len = m->m_pkthdr.len = MCLBYTES; 623 } 624 else 625 m->m_data = m->m_ext.ext_buf; 626 627 rx_header = mtod(m, struct bfe_rxheader *); 628 rx_header->len = 0; 629 rx_header->flags = 0; 630 631 /* Map the mbuf into DMA */ 632 sc->bfe_rx_cnt = c; 633 d = &sc->bfe_rx_list[c]; 634 r = &sc->bfe_rx_ring[c]; 635 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 636 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 637 if (error) 638 printf("Serious error: bfe failed to map RX buffer\n"); 639 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 640 641 ctrl = ETHER_MAX_LEN + 32; 642 643 if(c == BFE_RX_LIST_CNT - 1) 644 ctrl |= BFE_DESC_EOT; 645 646 d->bfe_ctrl = ctrl; 647 r->bfe_mbuf = m; 648 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 649 return (0); 650 } 651 652 static void 653 bfe_get_config(struct bfe_softc *sc) 654 { 655 u_int8_t eeprom[128]; 656 657 bfe_read_eeprom(sc, eeprom); 658 659 sc->bfe_enaddr[0] = eeprom[79]; 660 sc->bfe_enaddr[1] = eeprom[78]; 661 sc->bfe_enaddr[2] = eeprom[81]; 662 sc->bfe_enaddr[3] = eeprom[80]; 663 sc->bfe_enaddr[4] = eeprom[83]; 664 sc->bfe_enaddr[5] = eeprom[82]; 665 666 sc->bfe_phyaddr = eeprom[90] & 0x1f; 667 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 668 669 sc->bfe_core_unit = 0; 670 sc->bfe_dma_offset = BFE_PCI_DMA; 671 } 672 673 static void 674 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 675 { 676 u_int32_t bar_orig, pci_rev, val; 677 678 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 679 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 680 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 681 682 val = CSR_READ_4(sc, BFE_SBINTVEC); 683 val |= cores; 684 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 685 686 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 687 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 688 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 689 690 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 691 } 692 693 static void 694 bfe_clear_stats(struct bfe_softc *sc) 695 { 696 u_long reg; 697 698 BFE_LOCK_ASSERT(sc); 699 700 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 701 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 702 CSR_READ_4(sc, reg); 703 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 704 CSR_READ_4(sc, reg); 705 } 706 707 static int 708 bfe_resetphy(struct bfe_softc *sc) 709 { 710 u_int32_t val; 711 712 bfe_writephy(sc, 0, BMCR_RESET); 713 DELAY(100); 714 bfe_readphy(sc, 0, &val); 715 if (val & BMCR_RESET) { 716 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 717 return (ENXIO); 718 } 719 return (0); 720 } 721 722 static void 723 bfe_chip_halt(struct bfe_softc *sc) 724 { 725 BFE_LOCK_ASSERT(sc); 726 /* disable interrupts - not that it actually does..*/ 727 CSR_WRITE_4(sc, BFE_IMASK, 0); 728 CSR_READ_4(sc, BFE_IMASK); 729 730 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 731 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 732 733 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 734 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 735 DELAY(10); 736 } 737 738 static void 739 bfe_chip_reset(struct bfe_softc *sc) 740 { 741 u_int32_t val; 742 743 BFE_LOCK_ASSERT(sc); 744 745 /* Set the interrupt vector for the enet core */ 746 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 747 748 /* is core up? */ 749 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 750 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 751 if (val == BFE_CLOCK) { 752 /* It is, so shut it down */ 753 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 754 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 755 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 756 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 757 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 758 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 759 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 760 100, 0); 761 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 762 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 763 } 764 765 bfe_core_reset(sc); 766 bfe_clear_stats(sc); 767 768 /* 769 * We want the phy registers to be accessible even when 770 * the driver is "downed" so initialize MDC preamble, frequency, 771 * and whether internal or external phy here. 772 */ 773 774 /* 4402 has 62.5Mhz SB clock and internal phy */ 775 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 776 777 /* Internal or external PHY? */ 778 val = CSR_READ_4(sc, BFE_DEVCTRL); 779 if(!(val & BFE_IPP)) 780 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 781 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 782 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 783 DELAY(100); 784 } 785 786 /* Enable CRC32 generation and set proper LED modes */ 787 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 788 789 /* Reset or clear powerdown control bit */ 790 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 791 792 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 793 BFE_LAZY_FC_MASK)); 794 795 /* 796 * We don't want lazy interrupts, so just send them at 797 * the end of a frame, please 798 */ 799 BFE_OR(sc, BFE_RCV_LAZY, 0); 800 801 /* Set max lengths, accounting for VLAN tags */ 802 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 803 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 804 805 /* Set watermark XXX - magic */ 806 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 807 808 /* 809 * Initialise DMA channels 810 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 811 */ 812 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 813 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 814 815 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 816 BFE_RX_CTRL_ENABLE); 817 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 818 819 bfe_resetphy(sc); 820 bfe_setupphy(sc); 821 } 822 823 static void 824 bfe_core_disable(struct bfe_softc *sc) 825 { 826 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 827 return; 828 829 /* 830 * Set reject, wait for it set, then wait for the core to stop 831 * being busy, then set reset and reject and enable the clocks. 832 */ 833 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 834 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 835 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 836 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 837 BFE_RESET)); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 /* Leave reset and reject set */ 841 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 842 DELAY(10); 843 } 844 845 static void 846 bfe_core_reset(struct bfe_softc *sc) 847 { 848 u_int32_t val; 849 850 /* Disable the core */ 851 bfe_core_disable(sc); 852 853 /* and bring it back up */ 854 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 855 CSR_READ_4(sc, BFE_SBTMSLOW); 856 DELAY(10); 857 858 /* Chip bug, clear SERR, IB and TO if they are set. */ 859 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 860 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 861 val = CSR_READ_4(sc, BFE_SBIMSTATE); 862 if (val & (BFE_IBE | BFE_TO)) 863 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 864 865 /* Clear reset and allow it to move through the core */ 866 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 867 CSR_READ_4(sc, BFE_SBTMSLOW); 868 DELAY(10); 869 870 /* Leave the clock set */ 871 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 872 CSR_READ_4(sc, BFE_SBTMSLOW); 873 DELAY(10); 874 } 875 876 static void 877 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 878 { 879 u_int32_t val; 880 881 val = ((u_int32_t) data[2]) << 24; 882 val |= ((u_int32_t) data[3]) << 16; 883 val |= ((u_int32_t) data[4]) << 8; 884 val |= ((u_int32_t) data[5]); 885 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 886 val = (BFE_CAM_HI_VALID | 887 (((u_int32_t) data[0]) << 8) | 888 (((u_int32_t) data[1]))); 889 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 890 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 891 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 892 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 893 } 894 895 static void 896 bfe_set_rx_mode(struct bfe_softc *sc) 897 { 898 struct ifnet *ifp = sc->bfe_ifp; 899 struct ifmultiaddr *ifma; 900 u_int32_t val; 901 int i = 0; 902 903 val = CSR_READ_4(sc, BFE_RXCONF); 904 905 if (ifp->if_flags & IFF_PROMISC) 906 val |= BFE_RXCONF_PROMISC; 907 else 908 val &= ~BFE_RXCONF_PROMISC; 909 910 if (ifp->if_flags & IFF_BROADCAST) 911 val &= ~BFE_RXCONF_DBCAST; 912 else 913 val |= BFE_RXCONF_DBCAST; 914 915 916 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 917 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 918 919 if (ifp->if_flags & IFF_ALLMULTI) 920 val |= BFE_RXCONF_ALLMULTI; 921 else { 922 val &= ~BFE_RXCONF_ALLMULTI; 923 IF_ADDR_LOCK(ifp); 924 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 925 if (ifma->ifma_addr->sa_family != AF_LINK) 926 continue; 927 bfe_cam_write(sc, 928 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 929 } 930 IF_ADDR_UNLOCK(ifp); 931 } 932 933 CSR_WRITE_4(sc, BFE_RXCONF, val); 934 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 935 } 936 937 static void 938 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 939 { 940 u_int32_t *ptr; 941 942 ptr = arg; 943 *ptr = segs->ds_addr; 944 } 945 946 static void 947 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 948 { 949 struct bfe_desc *d; 950 951 d = arg; 952 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 953 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 954 } 955 956 static void 957 bfe_release_resources(struct bfe_softc *sc) 958 { 959 device_t dev; 960 int i; 961 962 dev = sc->bfe_dev; 963 964 if (sc->bfe_vpd_prodname != NULL) 965 free(sc->bfe_vpd_prodname, M_DEVBUF); 966 967 if (sc->bfe_vpd_readonly != NULL) 968 free(sc->bfe_vpd_readonly, M_DEVBUF); 969 970 if (sc->bfe_intrhand != NULL) 971 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 972 973 if (sc->bfe_irq != NULL) 974 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 975 976 if (sc->bfe_res != NULL) 977 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 978 979 if (sc->bfe_ifp != NULL) 980 if_free(sc->bfe_ifp); 981 982 if(sc->bfe_tx_tag != NULL) { 983 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 984 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 985 sc->bfe_tx_map); 986 bus_dma_tag_destroy(sc->bfe_tx_tag); 987 sc->bfe_tx_tag = NULL; 988 } 989 990 if(sc->bfe_rx_tag != NULL) { 991 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 992 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 993 sc->bfe_rx_map); 994 bus_dma_tag_destroy(sc->bfe_rx_tag); 995 sc->bfe_rx_tag = NULL; 996 } 997 998 if(sc->bfe_tag != NULL) { 999 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1000 bus_dmamap_destroy(sc->bfe_tag, 1001 sc->bfe_tx_ring[i].bfe_map); 1002 } 1003 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1004 bus_dmamap_destroy(sc->bfe_tag, 1005 sc->bfe_rx_ring[i].bfe_map); 1006 } 1007 bus_dma_tag_destroy(sc->bfe_tag); 1008 sc->bfe_tag = NULL; 1009 } 1010 1011 if(sc->bfe_parent_tag != NULL) 1012 bus_dma_tag_destroy(sc->bfe_parent_tag); 1013 1014 return; 1015 } 1016 1017 static void 1018 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1019 { 1020 long i; 1021 u_int16_t *ptr = (u_int16_t *)data; 1022 1023 for(i = 0; i < 128; i += 2) 1024 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1025 } 1026 1027 static int 1028 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1029 u_long timeout, const int clear) 1030 { 1031 u_long i; 1032 1033 for (i = 0; i < timeout; i++) { 1034 u_int32_t val = CSR_READ_4(sc, reg); 1035 1036 if (clear && !(val & bit)) 1037 break; 1038 if (!clear && (val & bit)) 1039 break; 1040 DELAY(10); 1041 } 1042 if (i == timeout) { 1043 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1044 "%x to %s.\n", sc->bfe_unit, bit, reg, 1045 (clear ? "clear" : "set")); 1046 return (-1); 1047 } 1048 return (0); 1049 } 1050 1051 static int 1052 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1053 { 1054 int err; 1055 1056 /* Clear MII ISR */ 1057 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1058 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1059 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1060 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1061 (reg << BFE_MDIO_RA_SHIFT) | 1062 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1063 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1064 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1065 1066 return (err); 1067 } 1068 1069 static int 1070 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1071 { 1072 int status; 1073 1074 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1075 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1076 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1077 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1078 (reg << BFE_MDIO_RA_SHIFT) | 1079 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1080 (val & BFE_MDIO_DATA_DATA))); 1081 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1082 1083 return (status); 1084 } 1085 1086 /* 1087 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1088 * twice 1089 */ 1090 static int 1091 bfe_setupphy(struct bfe_softc *sc) 1092 { 1093 u_int32_t val; 1094 1095 /* Enable activity LED */ 1096 bfe_readphy(sc, 26, &val); 1097 bfe_writephy(sc, 26, val & 0x7fff); 1098 bfe_readphy(sc, 26, &val); 1099 1100 /* Enable traffic meter LED mode */ 1101 bfe_readphy(sc, 27, &val); 1102 bfe_writephy(sc, 27, val | (1 << 6)); 1103 1104 return (0); 1105 } 1106 1107 static void 1108 bfe_stats_update(struct bfe_softc *sc) 1109 { 1110 u_long reg; 1111 u_int32_t *val; 1112 1113 val = &sc->bfe_hwstats.tx_good_octets; 1114 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1115 *val++ += CSR_READ_4(sc, reg); 1116 } 1117 val = &sc->bfe_hwstats.rx_good_octets; 1118 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1119 *val++ += CSR_READ_4(sc, reg); 1120 } 1121 } 1122 1123 static void 1124 bfe_txeof(struct bfe_softc *sc) 1125 { 1126 struct ifnet *ifp; 1127 int i, chipidx; 1128 1129 BFE_LOCK_ASSERT(sc); 1130 1131 ifp = sc->bfe_ifp; 1132 1133 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1134 chipidx /= sizeof(struct bfe_desc); 1135 1136 i = sc->bfe_tx_cons; 1137 /* Go through the mbufs and free those that have been transmitted */ 1138 while(i != chipidx) { 1139 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1140 if(r->bfe_mbuf != NULL) { 1141 ifp->if_opackets++; 1142 m_freem(r->bfe_mbuf); 1143 r->bfe_mbuf = NULL; 1144 } 1145 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1146 sc->bfe_tx_cnt--; 1147 BFE_INC(i, BFE_TX_LIST_CNT); 1148 } 1149 1150 if(i != sc->bfe_tx_cons) { 1151 /* we freed up some mbufs */ 1152 sc->bfe_tx_cons = i; 1153 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1154 } 1155 if(sc->bfe_tx_cnt == 0) 1156 ifp->if_timer = 0; 1157 else 1158 ifp->if_timer = 5; 1159 } 1160 1161 /* Pass a received packet up the stack */ 1162 static void 1163 bfe_rxeof(struct bfe_softc *sc) 1164 { 1165 struct mbuf *m; 1166 struct ifnet *ifp; 1167 struct bfe_rxheader *rxheader; 1168 struct bfe_data *r; 1169 int cons; 1170 u_int32_t status, current, len, flags; 1171 1172 BFE_LOCK_ASSERT(sc); 1173 cons = sc->bfe_rx_cons; 1174 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1175 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1176 1177 ifp = sc->bfe_ifp; 1178 1179 while(current != cons) { 1180 r = &sc->bfe_rx_ring[cons]; 1181 m = r->bfe_mbuf; 1182 rxheader = mtod(m, struct bfe_rxheader*); 1183 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1184 len = rxheader->len; 1185 r->bfe_mbuf = NULL; 1186 1187 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1188 flags = rxheader->flags; 1189 1190 len -= ETHER_CRC_LEN; 1191 1192 /* flag an error and try again */ 1193 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1194 ifp->if_ierrors++; 1195 if (flags & BFE_RX_FLAG_SERR) 1196 ifp->if_collisions++; 1197 bfe_list_newbuf(sc, cons, m); 1198 BFE_INC(cons, BFE_RX_LIST_CNT); 1199 continue; 1200 } 1201 1202 /* Go past the rx header */ 1203 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1204 m_adj(m, BFE_RX_OFFSET); 1205 m->m_len = m->m_pkthdr.len = len; 1206 } else { 1207 bfe_list_newbuf(sc, cons, m); 1208 ifp->if_ierrors++; 1209 BFE_INC(cons, BFE_RX_LIST_CNT); 1210 continue; 1211 } 1212 1213 ifp->if_ipackets++; 1214 m->m_pkthdr.rcvif = ifp; 1215 BFE_UNLOCK(sc); 1216 (*ifp->if_input)(ifp, m); 1217 BFE_LOCK(sc); 1218 1219 BFE_INC(cons, BFE_RX_LIST_CNT); 1220 } 1221 sc->bfe_rx_cons = cons; 1222 } 1223 1224 static void 1225 bfe_intr(void *xsc) 1226 { 1227 struct bfe_softc *sc = xsc; 1228 struct ifnet *ifp; 1229 u_int32_t istat, imask, flag; 1230 1231 ifp = sc->bfe_ifp; 1232 1233 BFE_LOCK(sc); 1234 1235 istat = CSR_READ_4(sc, BFE_ISTAT); 1236 imask = CSR_READ_4(sc, BFE_IMASK); 1237 1238 /* 1239 * Defer unsolicited interrupts - This is necessary because setting the 1240 * chips interrupt mask register to 0 doesn't actually stop the 1241 * interrupts 1242 */ 1243 istat &= imask; 1244 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1245 CSR_READ_4(sc, BFE_ISTAT); 1246 1247 /* not expecting this interrupt, disregard it */ 1248 if(istat == 0) { 1249 BFE_UNLOCK(sc); 1250 return; 1251 } 1252 1253 if(istat & BFE_ISTAT_ERRORS) { 1254 1255 if (istat & BFE_ISTAT_DSCE) { 1256 printf("if_bfe Descriptor Error\n"); 1257 bfe_stop(sc); 1258 BFE_UNLOCK(sc); 1259 return; 1260 } 1261 1262 if (istat & BFE_ISTAT_DPE) { 1263 printf("if_bfe Descriptor Protocol Error\n"); 1264 bfe_stop(sc); 1265 BFE_UNLOCK(sc); 1266 return; 1267 } 1268 1269 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1270 if(flag & BFE_STAT_EMASK) 1271 ifp->if_oerrors++; 1272 1273 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1274 if(flag & BFE_RX_FLAG_ERRORS) 1275 ifp->if_ierrors++; 1276 1277 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1278 bfe_init_locked(sc); 1279 } 1280 1281 /* A packet was received */ 1282 if(istat & BFE_ISTAT_RX) 1283 bfe_rxeof(sc); 1284 1285 /* A packet was sent */ 1286 if(istat & BFE_ISTAT_TX) 1287 bfe_txeof(sc); 1288 1289 /* We have packets pending, fire them out */ 1290 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1291 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1292 bfe_start_locked(ifp); 1293 1294 BFE_UNLOCK(sc); 1295 } 1296 1297 static int 1298 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1299 { 1300 struct bfe_desc *d = NULL; 1301 struct bfe_data *r = NULL; 1302 struct mbuf *m; 1303 u_int32_t frag, cur, cnt = 0; 1304 int chainlen = 0; 1305 int error; 1306 1307 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1308 return (ENOBUFS); 1309 1310 /* 1311 * Count the number of frags in this chain to see if 1312 * we need to m_defrag. Since the descriptor list is shared 1313 * by all packets, we'll m_defrag long chains so that they 1314 * do not use up the entire list, even if they would fit. 1315 */ 1316 for(m = *m_head; m != NULL; m = m->m_next) 1317 chainlen++; 1318 1319 1320 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1321 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1322 m = m_defrag(*m_head, M_DONTWAIT); 1323 if (m == NULL) 1324 return (ENOBUFS); 1325 *m_head = m; 1326 } 1327 1328 /* 1329 * Start packing the mbufs in this chain into 1330 * the fragment pointers. Stop when we run out 1331 * of fragments or hit the end of the mbuf chain. 1332 */ 1333 cur = frag = *txidx; 1334 cnt = 0; 1335 1336 for(m = *m_head; m != NULL; m = m->m_next) { 1337 if(m->m_len != 0) { 1338 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1339 return (ENOBUFS); 1340 1341 d = &sc->bfe_tx_list[cur]; 1342 r = &sc->bfe_tx_ring[cur]; 1343 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1344 /* always intterupt on completion */ 1345 d->bfe_ctrl |= BFE_DESC_IOC; 1346 if(cnt == 0) 1347 /* Set start of frame */ 1348 d->bfe_ctrl |= BFE_DESC_SOF; 1349 if(cur == BFE_TX_LIST_CNT - 1) 1350 /* 1351 * Tell the chip to wrap to the start of 1352 * the descriptor list 1353 */ 1354 d->bfe_ctrl |= BFE_DESC_EOT; 1355 1356 error = bus_dmamap_load(sc->bfe_tag, 1357 r->bfe_map, mtod(m, void*), m->m_len, 1358 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1359 if (error) 1360 return (ENOBUFS); 1361 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1362 BUS_DMASYNC_PREWRITE); 1363 1364 frag = cur; 1365 BFE_INC(cur, BFE_TX_LIST_CNT); 1366 cnt++; 1367 } 1368 } 1369 1370 if (m != NULL) 1371 return (ENOBUFS); 1372 1373 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1374 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1375 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1376 1377 *txidx = cur; 1378 sc->bfe_tx_cnt += cnt; 1379 return (0); 1380 } 1381 1382 /* 1383 * Set up to transmit a packet. 1384 */ 1385 static void 1386 bfe_start(struct ifnet *ifp) 1387 { 1388 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1389 bfe_start_locked(ifp); 1390 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1391 } 1392 1393 /* 1394 * Set up to transmit a packet. The softc is already locked. 1395 */ 1396 static void 1397 bfe_start_locked(struct ifnet *ifp) 1398 { 1399 struct bfe_softc *sc; 1400 struct mbuf *m_head = NULL; 1401 int idx, queued = 0; 1402 1403 sc = ifp->if_softc; 1404 idx = sc->bfe_tx_prod; 1405 1406 BFE_LOCK_ASSERT(sc); 1407 1408 /* 1409 * Not much point trying to send if the link is down 1410 * or we have nothing to send. 1411 */ 1412 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1413 return; 1414 1415 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1416 return; 1417 1418 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1419 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1420 if(m_head == NULL) 1421 break; 1422 1423 /* 1424 * Pack the data into the tx ring. If we dont have 1425 * enough room, let the chip drain the ring. 1426 */ 1427 if(bfe_encap(sc, &m_head, &idx)) { 1428 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1429 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1430 break; 1431 } 1432 1433 queued++; 1434 1435 /* 1436 * If there's a BPF listener, bounce a copy of this frame 1437 * to him. 1438 */ 1439 BPF_MTAP(ifp, m_head); 1440 } 1441 1442 if (queued) { 1443 sc->bfe_tx_prod = idx; 1444 /* Transmit - twice due to apparent hardware bug */ 1445 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1446 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1447 1448 /* 1449 * Set a timeout in case the chip goes out to lunch. 1450 */ 1451 ifp->if_timer = 5; 1452 } 1453 } 1454 1455 static void 1456 bfe_init(void *xsc) 1457 { 1458 BFE_LOCK((struct bfe_softc *)xsc); 1459 bfe_init_locked(xsc); 1460 BFE_UNLOCK((struct bfe_softc *)xsc); 1461 } 1462 1463 static void 1464 bfe_init_locked(void *xsc) 1465 { 1466 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1467 struct ifnet *ifp = sc->bfe_ifp; 1468 1469 BFE_LOCK_ASSERT(sc); 1470 1471 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1472 return; 1473 1474 bfe_stop(sc); 1475 bfe_chip_reset(sc); 1476 1477 if (bfe_list_rx_init(sc) == ENOBUFS) { 1478 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1479 sc->bfe_unit); 1480 bfe_stop(sc); 1481 return; 1482 } 1483 1484 bfe_set_rx_mode(sc); 1485 1486 /* Enable the chip and core */ 1487 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1488 /* Enable interrupts */ 1489 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1490 1491 bfe_ifmedia_upd(ifp); 1492 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1493 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1494 1495 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1496 } 1497 1498 /* 1499 * Set media options. 1500 */ 1501 static int 1502 bfe_ifmedia_upd(struct ifnet *ifp) 1503 { 1504 struct bfe_softc *sc; 1505 struct mii_data *mii; 1506 1507 sc = ifp->if_softc; 1508 1509 mii = device_get_softc(sc->bfe_miibus); 1510 sc->bfe_link = 0; 1511 if (mii->mii_instance) { 1512 struct mii_softc *miisc; 1513 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1514 miisc = LIST_NEXT(miisc, mii_list)) 1515 mii_phy_reset(miisc); 1516 } 1517 mii_mediachg(mii); 1518 1519 return (0); 1520 } 1521 1522 /* 1523 * Report current media status. 1524 */ 1525 static void 1526 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1527 { 1528 struct bfe_softc *sc = ifp->if_softc; 1529 struct mii_data *mii; 1530 1531 mii = device_get_softc(sc->bfe_miibus); 1532 mii_pollstat(mii); 1533 ifmr->ifm_active = mii->mii_media_active; 1534 ifmr->ifm_status = mii->mii_media_status; 1535 } 1536 1537 static int 1538 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1539 { 1540 struct bfe_softc *sc = ifp->if_softc; 1541 struct ifreq *ifr = (struct ifreq *) data; 1542 struct mii_data *mii; 1543 int error = 0; 1544 1545 switch(command) { 1546 case SIOCSIFFLAGS: 1547 BFE_LOCK(sc); 1548 if(ifp->if_flags & IFF_UP) 1549 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1550 bfe_set_rx_mode(sc); 1551 else 1552 bfe_init_locked(sc); 1553 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1554 bfe_stop(sc); 1555 BFE_UNLOCK(sc); 1556 break; 1557 case SIOCADDMULTI: 1558 case SIOCDELMULTI: 1559 BFE_LOCK(sc); 1560 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1561 bfe_set_rx_mode(sc); 1562 BFE_UNLOCK(sc); 1563 break; 1564 case SIOCGIFMEDIA: 1565 case SIOCSIFMEDIA: 1566 mii = device_get_softc(sc->bfe_miibus); 1567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1568 command); 1569 break; 1570 default: 1571 error = ether_ioctl(ifp, command, data); 1572 break; 1573 } 1574 1575 return (error); 1576 } 1577 1578 static void 1579 bfe_watchdog(struct ifnet *ifp) 1580 { 1581 struct bfe_softc *sc; 1582 1583 sc = ifp->if_softc; 1584 1585 BFE_LOCK(sc); 1586 1587 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1588 1589 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1590 bfe_init_locked(sc); 1591 1592 ifp->if_oerrors++; 1593 1594 BFE_UNLOCK(sc); 1595 } 1596 1597 static void 1598 bfe_tick(void *xsc) 1599 { 1600 struct bfe_softc *sc = xsc; 1601 struct mii_data *mii; 1602 1603 if (sc == NULL) 1604 return; 1605 1606 BFE_LOCK(sc); 1607 1608 mii = device_get_softc(sc->bfe_miibus); 1609 1610 bfe_stats_update(sc); 1611 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1612 1613 if(sc->bfe_link) { 1614 BFE_UNLOCK(sc); 1615 return; 1616 } 1617 1618 mii_tick(mii); 1619 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1620 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1621 sc->bfe_link++; 1622 1623 BFE_UNLOCK(sc); 1624 } 1625 1626 /* 1627 * Stop the adapter and free any mbufs allocated to the 1628 * RX and TX lists. 1629 */ 1630 static void 1631 bfe_stop(struct bfe_softc *sc) 1632 { 1633 struct ifnet *ifp; 1634 1635 BFE_LOCK_ASSERT(sc); 1636 1637 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1638 1639 ifp = sc->bfe_ifp; 1640 1641 bfe_chip_halt(sc); 1642 bfe_tx_ring_free(sc); 1643 bfe_rx_ring_free(sc); 1644 1645 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1646 } 1647