1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6 /* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #include <net/bpf.h> 49 50 #include <net/if_types.h> 51 #include <net/if_vlan_var.h> 52 53 #include <netinet/in_systm.h> 54 #include <netinet/in.h> 55 #include <netinet/ip.h> 56 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include "miidevs.h" 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <dev/bfe/if_bfereg.h> 72 73 MODULE_DEPEND(bfe, pci, 1, 1, 1); 74 MODULE_DEPEND(bfe, ether, 1, 1, 1); 75 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77 /* "controller miibus0" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82 static struct bfe_type bfe_devs[] = { 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95 static void bfe_init (void *); 96 static void bfe_stop (struct bfe_softc *); 97 static void bfe_watchdog (struct ifnet *); 98 static void bfe_shutdown (device_t); 99 static void bfe_tick (void *); 100 static void bfe_txeof (struct bfe_softc *); 101 static void bfe_rxeof (struct bfe_softc *); 102 static void bfe_set_rx_mode (struct bfe_softc *); 103 static int bfe_list_rx_init (struct bfe_softc *); 104 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105 static void bfe_rx_ring_free (struct bfe_softc *); 106 107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108 static int bfe_ifmedia_upd (struct ifnet *); 109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 static int bfe_miibus_readreg (device_t, int, int); 111 static int bfe_miibus_writereg (device_t, int, int, int); 112 static void bfe_miibus_statchg (device_t); 113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115 static void bfe_get_config (struct bfe_softc *sc); 116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117 static void bfe_stats_update (struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121 static int bfe_resetphy (struct bfe_softc *); 122 static int bfe_setupphy (struct bfe_softc *); 123 static void bfe_chip_reset (struct bfe_softc *); 124 static void bfe_chip_halt (struct bfe_softc *); 125 static void bfe_core_reset (struct bfe_softc *); 126 static void bfe_core_disable (struct bfe_softc *); 127 static int bfe_dma_alloc (device_t); 128 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149 }; 150 151 static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155 }; 156 157 static devclass_t bfe_devclass; 158 159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162 /* 163 * Probe for a Broadcom 4401 chip. 164 */ 165 static int 166 bfe_probe(device_t dev) 167 { 168 struct bfe_type *t; 169 struct bfe_softc *sc; 170 171 t = bfe_devs; 172 173 sc = device_get_softc(dev); 174 bzero(sc, sizeof(struct bfe_softc)); 175 sc->bfe_unit = device_get_unit(dev); 176 sc->bfe_dev = dev; 177 178 while(t->bfe_name != NULL) { 179 if ((pci_get_vendor(dev) == t->bfe_vid) && 180 (pci_get_device(dev) == t->bfe_did)) { 181 device_set_desc_copy(dev, t->bfe_name); 182 return(0); 183 } 184 t++; 185 } 186 187 return(ENXIO); 188 } 189 190 static int 191 bfe_dma_alloc(device_t dev) 192 { 193 struct bfe_softc *sc; 194 int error, i; 195 196 sc = device_get_softc(dev); 197 198 /* parent tag */ 199 error = bus_dma_tag_create(NULL, /* parent */ 200 PAGE_SIZE, 0, /* alignment, boundary */ 201 BUS_SPACE_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 MAXBSIZE, /* maxsize */ 205 BUS_SPACE_UNRESTRICTED, /* num of segments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207 BUS_DMA_ALLOCNOW, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 213 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 214 BUS_SPACE_MAXADDR, 215 BUS_SPACE_MAXADDR, 216 NULL, NULL, 217 BFE_TX_LIST_SIZE, 218 1, 219 BUS_SPACE_MAXSIZE_32BIT, 220 0, 221 NULL, NULL, 222 &sc->bfe_tx_tag); 223 224 if (error) { 225 device_printf(dev, "could not allocate dma tag\n"); 226 return(ENOMEM); 227 } 228 229 /* tag for RX ring */ 230 error = bus_dma_tag_create(sc->bfe_parent_tag, 231 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 232 BUS_SPACE_MAXADDR, 233 BUS_SPACE_MAXADDR, 234 NULL, NULL, 235 BFE_RX_LIST_SIZE, 236 1, 237 BUS_SPACE_MAXSIZE_32BIT, 238 0, 239 NULL, NULL, 240 &sc->bfe_rx_tag); 241 242 if (error) { 243 device_printf(dev, "could not allocate dma tag\n"); 244 return(ENOMEM); 245 } 246 247 /* tag for mbufs */ 248 error = bus_dma_tag_create(sc->bfe_parent_tag, 249 ETHER_ALIGN, 0, 250 BUS_SPACE_MAXADDR, 251 BUS_SPACE_MAXADDR, 252 NULL, NULL, 253 MCLBYTES, 254 1, 255 BUS_SPACE_MAXSIZE_32BIT, 256 0, 257 NULL, NULL, 258 &sc->bfe_tag); 259 260 if (error) { 261 device_printf(dev, "could not allocate dma tag\n"); 262 return(ENOMEM); 263 } 264 265 /* pre allocate dmamaps for RX list */ 266 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 267 error = bus_dmamap_create(sc->bfe_tag, 0, 268 &sc->bfe_rx_ring[i].bfe_map); 269 if (error) { 270 device_printf(dev, "cannot create DMA map for RX\n"); 271 return(ENOMEM); 272 } 273 } 274 275 /* pre allocate dmamaps for TX list */ 276 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 277 error = bus_dmamap_create(sc->bfe_tag, 0, 278 &sc->bfe_tx_ring[i].bfe_map); 279 if (error) { 280 device_printf(dev, "cannot create DMA map for TX\n"); 281 return(ENOMEM); 282 } 283 } 284 285 /* Alloc dma for rx ring */ 286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 287 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 288 289 if(error) 290 return(ENOMEM); 291 292 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 293 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 294 sc->bfe_rx_list, sizeof(struct bfe_desc), 295 bfe_dma_map, &sc->bfe_rx_dma, 0); 296 297 if(error) 298 return(ENOMEM); 299 300 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 301 302 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 303 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 304 if (error) 305 return(ENOMEM); 306 307 308 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 309 sc->bfe_tx_list, sizeof(struct bfe_desc), 310 bfe_dma_map, &sc->bfe_tx_dma, 0); 311 if(error) 312 return(ENOMEM); 313 314 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 316 317 return(0); 318 } 319 320 static int 321 bfe_attach(device_t dev) 322 { 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int unit, error = 0, rid; 326 327 sc = device_get_softc(dev); 328 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 329 MTX_DEF | MTX_RECURSE); 330 331 unit = device_get_unit(dev); 332 sc->bfe_dev = dev; 333 sc->bfe_unit = unit; 334 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 u_int32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 347 sc->bfe_unit, pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 printf ("bfe%d: couldn't map memory\n", unit); 366 error = ENXIO; 367 goto fail; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 373 374 /* Allocate interrupt */ 375 rid = 0; 376 377 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 378 RF_SHAREABLE | RF_ACTIVE); 379 if (sc->bfe_irq == NULL) { 380 printf("bfe%d: couldn't map interrupt\n", unit); 381 error = ENXIO; 382 goto fail; 383 } 384 385 if (bfe_dma_alloc(dev)) { 386 printf("bfe%d: failed to allocate DMA resources\n", 387 sc->bfe_unit); 388 bfe_release_resources(sc); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* Set up ifnet structure */ 394 ifp = &sc->arpcom.ac_if; 395 ifp->if_softc = sc; 396 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 398 ifp->if_ioctl = bfe_ioctl; 399 ifp->if_output = ether_output; 400 ifp->if_start = bfe_start; 401 ifp->if_watchdog = bfe_watchdog; 402 ifp->if_init = bfe_init; 403 ifp->if_mtu = ETHERMTU; 404 ifp->if_baudrate = 10000000; 405 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 406 407 bfe_get_config(sc); 408 409 printf("bfe%d: Ethernet address: %6D\n", unit, 410 sc->arpcom.ac_enaddr, ":"); 411 412 /* Reset the chip and turn on the PHY */ 413 bfe_chip_reset(sc); 414 415 if (mii_phy_probe(dev, &sc->bfe_miibus, 416 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 417 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 418 error = ENXIO; 419 goto fail; 420 } 421 422 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 423 callout_handle_init(&sc->bfe_stat_ch); 424 425 /* 426 * Hook interrupt last to avoid having to lock softc 427 */ 428 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 429 bfe_intr, sc, &sc->bfe_intrhand); 430 431 if (error) { 432 bfe_release_resources(sc); 433 printf("bfe%d: couldn't set up irq\n", unit); 434 goto fail; 435 } 436 fail: 437 if(error) 438 bfe_release_resources(sc); 439 return(error); 440 } 441 442 static int 443 bfe_detach(device_t dev) 444 { 445 struct bfe_softc *sc; 446 struct ifnet *ifp; 447 448 sc = device_get_softc(dev); 449 450 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 451 BFE_LOCK(scp); 452 453 ifp = &sc->arpcom.ac_if; 454 455 if (device_is_attached(dev)) { 456 bfe_stop(sc); 457 ether_ifdetach(ifp); 458 } 459 460 bfe_chip_reset(sc); 461 462 bus_generic_detach(dev); 463 if(sc->bfe_miibus != NULL) 464 device_delete_child(dev, sc->bfe_miibus); 465 466 bfe_release_resources(sc); 467 BFE_UNLOCK(sc); 468 mtx_destroy(&sc->bfe_mtx); 469 470 return(0); 471 } 472 473 /* 474 * Stop all chip I/O so that the kernel's probe routines don't 475 * get confused by errant DMAs when rebooting. 476 */ 477 static void 478 bfe_shutdown(device_t dev) 479 { 480 struct bfe_softc *sc; 481 482 sc = device_get_softc(dev); 483 BFE_LOCK(sc); 484 bfe_stop(sc); 485 486 BFE_UNLOCK(sc); 487 return; 488 } 489 490 static int 491 bfe_miibus_readreg(device_t dev, int phy, int reg) 492 { 493 struct bfe_softc *sc; 494 u_int32_t ret; 495 496 sc = device_get_softc(dev); 497 if(phy != sc->bfe_phyaddr) 498 return(0); 499 bfe_readphy(sc, reg, &ret); 500 501 return(ret); 502 } 503 504 static int 505 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 506 { 507 struct bfe_softc *sc; 508 509 sc = device_get_softc(dev); 510 if(phy != sc->bfe_phyaddr) 511 return(0); 512 bfe_writephy(sc, reg, val); 513 514 return(0); 515 } 516 517 static void 518 bfe_miibus_statchg(device_t dev) 519 { 520 return; 521 } 522 523 static void 524 bfe_tx_ring_free(struct bfe_softc *sc) 525 { 526 int i; 527 528 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 529 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 530 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 531 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 532 bus_dmamap_unload(sc->bfe_tag, 533 sc->bfe_tx_ring[i].bfe_map); 534 bus_dmamap_destroy(sc->bfe_tag, 535 sc->bfe_tx_ring[i].bfe_map); 536 } 537 } 538 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 539 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 540 } 541 542 static void 543 bfe_rx_ring_free(struct bfe_softc *sc) 544 { 545 int i; 546 547 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 548 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 549 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 550 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 551 bus_dmamap_unload(sc->bfe_tag, 552 sc->bfe_rx_ring[i].bfe_map); 553 bus_dmamap_destroy(sc->bfe_tag, 554 sc->bfe_rx_ring[i].bfe_map); 555 } 556 } 557 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 558 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 559 } 560 561 562 static int 563 bfe_list_rx_init(struct bfe_softc *sc) 564 { 565 int i; 566 567 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 568 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 569 return ENOBUFS; 570 } 571 572 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 573 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 574 575 sc->bfe_rx_cons = 0; 576 577 return(0); 578 } 579 580 static int 581 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 582 { 583 struct bfe_rxheader *rx_header; 584 struct bfe_desc *d; 585 struct bfe_data *r; 586 u_int32_t ctrl; 587 588 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 589 return(EINVAL); 590 591 if(m == NULL) { 592 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 593 if(m == NULL) 594 return(ENOBUFS); 595 m->m_len = m->m_pkthdr.len = MCLBYTES; 596 } 597 else 598 m->m_data = m->m_ext.ext_buf; 599 600 rx_header = mtod(m, struct bfe_rxheader *); 601 rx_header->len = 0; 602 rx_header->flags = 0; 603 604 /* Map the mbuf into DMA */ 605 sc->bfe_rx_cnt = c; 606 d = &sc->bfe_rx_list[c]; 607 r = &sc->bfe_rx_ring[c]; 608 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 609 MCLBYTES, bfe_dma_map_desc, d, 0); 610 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 611 612 ctrl = ETHER_MAX_LEN + 32; 613 614 if(c == BFE_RX_LIST_CNT - 1) 615 ctrl |= BFE_DESC_EOT; 616 617 d->bfe_ctrl = ctrl; 618 r->bfe_mbuf = m; 619 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 620 return(0); 621 } 622 623 static void 624 bfe_get_config(struct bfe_softc *sc) 625 { 626 u_int8_t eeprom[128]; 627 628 bfe_read_eeprom(sc, eeprom); 629 630 sc->arpcom.ac_enaddr[0] = eeprom[79]; 631 sc->arpcom.ac_enaddr[1] = eeprom[78]; 632 sc->arpcom.ac_enaddr[2] = eeprom[81]; 633 sc->arpcom.ac_enaddr[3] = eeprom[80]; 634 sc->arpcom.ac_enaddr[4] = eeprom[83]; 635 sc->arpcom.ac_enaddr[5] = eeprom[82]; 636 637 sc->bfe_phyaddr = eeprom[90] & 0x1f; 638 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 639 640 sc->bfe_core_unit = 0; 641 sc->bfe_dma_offset = BFE_PCI_DMA; 642 } 643 644 static void 645 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 646 { 647 u_int32_t bar_orig, pci_rev, val; 648 649 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 650 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 651 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 652 653 val = CSR_READ_4(sc, BFE_SBINTVEC); 654 val |= cores; 655 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 656 657 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 658 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 659 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 660 661 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 662 } 663 664 static void 665 bfe_clear_stats(struct bfe_softc *sc) 666 { 667 u_long reg; 668 669 BFE_LOCK(sc); 670 671 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 672 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 673 CSR_READ_4(sc, reg); 674 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 675 CSR_READ_4(sc, reg); 676 677 BFE_UNLOCK(sc); 678 } 679 680 static int 681 bfe_resetphy(struct bfe_softc *sc) 682 { 683 u_int32_t val; 684 685 BFE_LOCK(sc); 686 bfe_writephy(sc, 0, BMCR_RESET); 687 DELAY(100); 688 bfe_readphy(sc, 0, &val); 689 if (val & BMCR_RESET) { 690 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 691 BFE_UNLOCK(sc); 692 return ENXIO; 693 } 694 BFE_UNLOCK(sc); 695 return 0; 696 } 697 698 static void 699 bfe_chip_halt(struct bfe_softc *sc) 700 { 701 BFE_LOCK(sc); 702 /* disable interrupts - not that it actually does..*/ 703 CSR_WRITE_4(sc, BFE_IMASK, 0); 704 CSR_READ_4(sc, BFE_IMASK); 705 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 708 709 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 711 DELAY(10); 712 713 BFE_UNLOCK(sc); 714 } 715 716 static void 717 bfe_chip_reset(struct bfe_softc *sc) 718 { 719 u_int32_t val; 720 721 BFE_LOCK(sc); 722 723 /* Set the interrupt vector for the enet core */ 724 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 725 726 /* is core up? */ 727 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 728 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 729 if (val == BFE_CLOCK) { 730 /* It is, so shut it down */ 731 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 733 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 734 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 735 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 736 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 737 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 738 100, 0); 739 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 740 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 741 } 742 743 bfe_core_reset(sc); 744 bfe_clear_stats(sc); 745 746 /* 747 * We want the phy registers to be accessible even when 748 * the driver is "downed" so initialize MDC preamble, frequency, 749 * and whether internal or external phy here. 750 */ 751 752 /* 4402 has 62.5Mhz SB clock and internal phy */ 753 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 754 755 /* Internal or external PHY? */ 756 val = CSR_READ_4(sc, BFE_DEVCTRL); 757 if(!(val & BFE_IPP)) 758 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 759 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 760 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 761 DELAY(100); 762 } 763 764 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 765 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 766 BFE_LAZY_FC_MASK)); 767 768 /* 769 * We don't want lazy interrupts, so just send them at 770 * the end of a frame, please 771 */ 772 BFE_OR(sc, BFE_RCV_LAZY, 0); 773 774 /* Set max lengths, accounting for VLAN tags */ 775 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 776 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 777 778 /* Set watermark XXX - magic */ 779 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 780 781 /* 782 * Initialise DMA channels 783 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 784 */ 785 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 786 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 787 788 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 789 BFE_RX_CTRL_ENABLE); 790 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 791 792 bfe_resetphy(sc); 793 bfe_setupphy(sc); 794 795 BFE_UNLOCK(sc); 796 } 797 798 static void 799 bfe_core_disable(struct bfe_softc *sc) 800 { 801 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 802 return; 803 804 /* 805 * Set reject, wait for it set, then wait for the core to stop 806 * being busy, then set reset and reject and enable the clocks. 807 */ 808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 809 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 810 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 811 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 812 BFE_RESET)); 813 CSR_READ_4(sc, BFE_SBTMSLOW); 814 DELAY(10); 815 /* Leave reset and reject set */ 816 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 817 DELAY(10); 818 } 819 820 static void 821 bfe_core_reset(struct bfe_softc *sc) 822 { 823 u_int32_t val; 824 825 /* Disable the core */ 826 bfe_core_disable(sc); 827 828 /* and bring it back up */ 829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 830 CSR_READ_4(sc, BFE_SBTMSLOW); 831 DELAY(10); 832 833 /* Chip bug, clear SERR, IB and TO if they are set. */ 834 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 835 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 836 val = CSR_READ_4(sc, BFE_SBIMSTATE); 837 if (val & (BFE_IBE | BFE_TO)) 838 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 839 840 /* Clear reset and allow it to move through the core */ 841 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 842 CSR_READ_4(sc, BFE_SBTMSLOW); 843 DELAY(10); 844 845 /* Leave the clock set */ 846 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 847 CSR_READ_4(sc, BFE_SBTMSLOW); 848 DELAY(10); 849 } 850 851 static void 852 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 853 { 854 u_int32_t val; 855 856 val = ((u_int32_t) data[2]) << 24; 857 val |= ((u_int32_t) data[3]) << 16; 858 val |= ((u_int32_t) data[4]) << 8; 859 val |= ((u_int32_t) data[5]); 860 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 861 val = (BFE_CAM_HI_VALID | 862 (((u_int32_t) data[0]) << 8) | 863 (((u_int32_t) data[1]))); 864 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 865 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 866 (index << BFE_CAM_INDEX_SHIFT))); 867 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 868 } 869 870 static void 871 bfe_set_rx_mode(struct bfe_softc *sc) 872 { 873 struct ifnet *ifp = &sc->arpcom.ac_if; 874 struct ifmultiaddr *ifma; 875 u_int32_t val; 876 int i = 0; 877 878 val = CSR_READ_4(sc, BFE_RXCONF); 879 880 if (ifp->if_flags & IFF_PROMISC) 881 val |= BFE_RXCONF_PROMISC; 882 else 883 val &= ~BFE_RXCONF_PROMISC; 884 885 if (ifp->if_flags & IFF_BROADCAST) 886 val &= ~BFE_RXCONF_DBCAST; 887 else 888 val |= BFE_RXCONF_DBCAST; 889 890 891 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 892 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 893 894 if (ifp->if_flags & IFF_ALLMULTI) 895 val |= BFE_RXCONF_ALLMULTI; 896 else { 897 val &= ~BFE_RXCONF_ALLMULTI; 898 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 899 if (ifma->ifma_addr->sa_family != AF_LINK) 900 continue; 901 bfe_cam_write(sc, 902 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 903 } 904 } 905 906 CSR_WRITE_4(sc, BFE_RXCONF, val); 907 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 908 } 909 910 static void 911 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 912 { 913 u_int32_t *ptr; 914 915 ptr = arg; 916 *ptr = segs->ds_addr; 917 } 918 919 static void 920 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 921 { 922 struct bfe_desc *d; 923 924 d = arg; 925 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 926 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 927 } 928 929 static void 930 bfe_release_resources(struct bfe_softc *sc) 931 { 932 device_t dev; 933 int i; 934 935 dev = sc->bfe_dev; 936 937 if (sc->bfe_vpd_prodname != NULL) 938 free(sc->bfe_vpd_prodname, M_DEVBUF); 939 940 if (sc->bfe_vpd_readonly != NULL) 941 free(sc->bfe_vpd_readonly, M_DEVBUF); 942 943 if (sc->bfe_intrhand != NULL) 944 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 945 946 if (sc->bfe_irq != NULL) 947 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 948 949 if (sc->bfe_res != NULL) 950 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 951 952 if(sc->bfe_tx_tag != NULL) { 953 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 954 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 955 sc->bfe_tx_map); 956 bus_dma_tag_destroy(sc->bfe_tx_tag); 957 sc->bfe_tx_tag = NULL; 958 } 959 960 if(sc->bfe_rx_tag != NULL) { 961 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 962 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 963 sc->bfe_rx_map); 964 bus_dma_tag_destroy(sc->bfe_rx_tag); 965 sc->bfe_rx_tag = NULL; 966 } 967 968 if(sc->bfe_tag != NULL) { 969 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 970 bus_dmamap_destroy(sc->bfe_tag, 971 sc->bfe_tx_ring[i].bfe_map); 972 } 973 bus_dma_tag_destroy(sc->bfe_tag); 974 sc->bfe_tag = NULL; 975 } 976 977 if(sc->bfe_parent_tag != NULL) 978 bus_dma_tag_destroy(sc->bfe_parent_tag); 979 980 return; 981 } 982 983 static void 984 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 985 { 986 long i; 987 u_int16_t *ptr = (u_int16_t *)data; 988 989 for(i = 0; i < 128; i += 2) 990 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 991 } 992 993 static int 994 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 995 u_long timeout, const int clear) 996 { 997 u_long i; 998 999 for (i = 0; i < timeout; i++) { 1000 u_int32_t val = CSR_READ_4(sc, reg); 1001 1002 if (clear && !(val & bit)) 1003 break; 1004 if (!clear && (val & bit)) 1005 break; 1006 DELAY(10); 1007 } 1008 if (i == timeout) { 1009 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1010 "%x to %s.\n", sc->bfe_unit, bit, reg, 1011 (clear ? "clear" : "set")); 1012 return -1; 1013 } 1014 return 0; 1015 } 1016 1017 static int 1018 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1019 { 1020 int err; 1021 1022 BFE_LOCK(sc); 1023 /* Clear MII ISR */ 1024 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1025 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1026 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1027 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1028 (reg << BFE_MDIO_RA_SHIFT) | 1029 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1030 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1031 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1032 1033 BFE_UNLOCK(sc); 1034 return err; 1035 } 1036 1037 static int 1038 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1039 { 1040 int status; 1041 1042 BFE_LOCK(sc); 1043 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1044 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1045 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1046 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1047 (reg << BFE_MDIO_RA_SHIFT) | 1048 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1049 (val & BFE_MDIO_DATA_DATA))); 1050 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1051 BFE_UNLOCK(sc); 1052 1053 return status; 1054 } 1055 1056 /* 1057 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1058 * twice 1059 */ 1060 static int 1061 bfe_setupphy(struct bfe_softc *sc) 1062 { 1063 u_int32_t val; 1064 BFE_LOCK(sc); 1065 1066 /* Enable activity LED */ 1067 bfe_readphy(sc, 26, &val); 1068 bfe_writephy(sc, 26, val & 0x7fff); 1069 bfe_readphy(sc, 26, &val); 1070 1071 /* Enable traffic meter LED mode */ 1072 bfe_readphy(sc, 27, &val); 1073 bfe_writephy(sc, 27, val | (1 << 6)); 1074 1075 BFE_UNLOCK(sc); 1076 return 0; 1077 } 1078 1079 static void 1080 bfe_stats_update(struct bfe_softc *sc) 1081 { 1082 u_long reg; 1083 u_int32_t *val; 1084 1085 val = &sc->bfe_hwstats.tx_good_octets; 1086 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1087 *val++ += CSR_READ_4(sc, reg); 1088 } 1089 val = &sc->bfe_hwstats.rx_good_octets; 1090 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1091 *val++ += CSR_READ_4(sc, reg); 1092 } 1093 } 1094 1095 static void 1096 bfe_txeof(struct bfe_softc *sc) 1097 { 1098 struct ifnet *ifp; 1099 int i, chipidx; 1100 1101 BFE_LOCK(sc); 1102 1103 ifp = &sc->arpcom.ac_if; 1104 1105 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1106 chipidx /= sizeof(struct bfe_desc); 1107 1108 i = sc->bfe_tx_cons; 1109 /* Go through the mbufs and free those that have been transmitted */ 1110 while(i != chipidx) { 1111 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1112 if(r->bfe_mbuf != NULL) { 1113 ifp->if_opackets++; 1114 m_freem(r->bfe_mbuf); 1115 r->bfe_mbuf = NULL; 1116 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1117 } 1118 sc->bfe_tx_cnt--; 1119 BFE_INC(i, BFE_TX_LIST_CNT); 1120 } 1121 1122 if(i != sc->bfe_tx_cons) { 1123 /* we freed up some mbufs */ 1124 sc->bfe_tx_cons = i; 1125 ifp->if_flags &= ~IFF_OACTIVE; 1126 } 1127 if(sc->bfe_tx_cnt == 0) 1128 ifp->if_timer = 0; 1129 else 1130 ifp->if_timer = 5; 1131 1132 BFE_UNLOCK(sc); 1133 } 1134 1135 /* Pass a received packet up the stack */ 1136 static void 1137 bfe_rxeof(struct bfe_softc *sc) 1138 { 1139 struct mbuf *m; 1140 struct ifnet *ifp; 1141 struct bfe_rxheader *rxheader; 1142 struct bfe_data *r; 1143 int cons; 1144 u_int32_t status, current, len, flags; 1145 1146 BFE_LOCK(sc); 1147 cons = sc->bfe_rx_cons; 1148 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1149 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1150 1151 ifp = &sc->arpcom.ac_if; 1152 1153 while(current != cons) { 1154 r = &sc->bfe_rx_ring[cons]; 1155 m = r->bfe_mbuf; 1156 rxheader = mtod(m, struct bfe_rxheader*); 1157 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1158 len = rxheader->len; 1159 r->bfe_mbuf = NULL; 1160 1161 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1162 flags = rxheader->flags; 1163 1164 len -= ETHER_CRC_LEN; 1165 1166 /* flag an error and try again */ 1167 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1168 ifp->if_ierrors++; 1169 if (flags & BFE_RX_FLAG_SERR) 1170 ifp->if_collisions++; 1171 bfe_list_newbuf(sc, cons, m); 1172 BFE_INC(cons, BFE_RX_LIST_CNT); 1173 continue; 1174 } 1175 1176 /* Go past the rx header */ 1177 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1178 m_adj(m, BFE_RX_OFFSET); 1179 m->m_len = m->m_pkthdr.len = len; 1180 } else { 1181 bfe_list_newbuf(sc, cons, m); 1182 ifp->if_ierrors++; 1183 BFE_INC(cons, BFE_RX_LIST_CNT); 1184 continue; 1185 } 1186 1187 ifp->if_ipackets++; 1188 m->m_pkthdr.rcvif = ifp; 1189 BFE_UNLOCK(sc); 1190 (*ifp->if_input)(ifp, m); 1191 BFE_LOCK(sc); 1192 1193 BFE_INC(cons, BFE_RX_LIST_CNT); 1194 } 1195 sc->bfe_rx_cons = cons; 1196 BFE_UNLOCK(sc); 1197 } 1198 1199 static void 1200 bfe_intr(void *xsc) 1201 { 1202 struct bfe_softc *sc = xsc; 1203 struct ifnet *ifp; 1204 u_int32_t istat, imask, flag; 1205 1206 ifp = &sc->arpcom.ac_if; 1207 1208 BFE_LOCK(sc); 1209 1210 istat = CSR_READ_4(sc, BFE_ISTAT); 1211 imask = CSR_READ_4(sc, BFE_IMASK); 1212 1213 /* 1214 * Defer unsolicited interrupts - This is necessary because setting the 1215 * chips interrupt mask register to 0 doesn't actually stop the 1216 * interrupts 1217 */ 1218 istat &= imask; 1219 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1220 CSR_READ_4(sc, BFE_ISTAT); 1221 1222 /* not expecting this interrupt, disregard it */ 1223 if(istat == 0) { 1224 BFE_UNLOCK(sc); 1225 return; 1226 } 1227 1228 if(istat & BFE_ISTAT_ERRORS) { 1229 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1230 if(flag & BFE_STAT_EMASK) 1231 ifp->if_oerrors++; 1232 1233 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1234 if(flag & BFE_RX_FLAG_ERRORS) 1235 ifp->if_ierrors++; 1236 1237 ifp->if_flags &= ~IFF_RUNNING; 1238 bfe_init(sc); 1239 } 1240 1241 /* A packet was received */ 1242 if(istat & BFE_ISTAT_RX) 1243 bfe_rxeof(sc); 1244 1245 /* A packet was sent */ 1246 if(istat & BFE_ISTAT_TX) 1247 bfe_txeof(sc); 1248 1249 /* We have packets pending, fire them out */ 1250 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1251 bfe_start(ifp); 1252 1253 BFE_UNLOCK(sc); 1254 } 1255 1256 static int 1257 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1258 { 1259 struct bfe_desc *d = NULL; 1260 struct bfe_data *r = NULL; 1261 struct mbuf *m; 1262 u_int32_t frag, cur, cnt = 0; 1263 int chainlen = 0; 1264 1265 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1266 return(ENOBUFS); 1267 1268 /* 1269 * Count the number of frags in this chain to see if 1270 * we need to m_defrag. Since the descriptor list is shared 1271 * by all packets, we'll m_defrag long chains so that they 1272 * do not use up the entire list, even if they would fit. 1273 */ 1274 for(m = m_head; m != NULL; m = m->m_next) 1275 chainlen++; 1276 1277 1278 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1279 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1280 m = m_defrag(m_head, M_DONTWAIT); 1281 if (m == NULL) 1282 return(ENOBUFS); 1283 m_head = m; 1284 } 1285 1286 /* 1287 * Start packing the mbufs in this chain into 1288 * the fragment pointers. Stop when we run out 1289 * of fragments or hit the end of the mbuf chain. 1290 */ 1291 m = m_head; 1292 cur = frag = *txidx; 1293 cnt = 0; 1294 1295 for(m = m_head; m != NULL; m = m->m_next) { 1296 if(m->m_len != 0) { 1297 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1298 return(ENOBUFS); 1299 1300 d = &sc->bfe_tx_list[cur]; 1301 r = &sc->bfe_tx_ring[cur]; 1302 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1303 /* always intterupt on completion */ 1304 d->bfe_ctrl |= BFE_DESC_IOC; 1305 if(cnt == 0) 1306 /* Set start of frame */ 1307 d->bfe_ctrl |= BFE_DESC_SOF; 1308 if(cur == BFE_TX_LIST_CNT - 1) 1309 /* 1310 * Tell the chip to wrap to the start of 1311 * the descriptor list 1312 */ 1313 d->bfe_ctrl |= BFE_DESC_EOT; 1314 1315 bus_dmamap_load(sc->bfe_tag, 1316 r->bfe_map, mtod(m, void*), m->m_len, 1317 bfe_dma_map_desc, d, 0); 1318 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1319 BUS_DMASYNC_PREREAD); 1320 1321 frag = cur; 1322 BFE_INC(cur, BFE_TX_LIST_CNT); 1323 cnt++; 1324 } 1325 } 1326 1327 if (m != NULL) 1328 return(ENOBUFS); 1329 1330 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1331 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1332 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1333 1334 *txidx = cur; 1335 sc->bfe_tx_cnt += cnt; 1336 return (0); 1337 } 1338 1339 /* 1340 * Set up to transmit a packet 1341 */ 1342 static void 1343 bfe_start(struct ifnet *ifp) 1344 { 1345 struct bfe_softc *sc; 1346 struct mbuf *m_head = NULL; 1347 int idx; 1348 1349 sc = ifp->if_softc; 1350 idx = sc->bfe_tx_prod; 1351 1352 BFE_LOCK(sc); 1353 1354 /* 1355 * Not much point trying to send if the link is down 1356 * or we have nothing to send. 1357 */ 1358 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1359 BFE_UNLOCK(sc); 1360 return; 1361 } 1362 1363 if (ifp->if_flags & IFF_OACTIVE) { 1364 BFE_UNLOCK(sc); 1365 return; 1366 } 1367 1368 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1369 IF_DEQUEUE(&ifp->if_snd, m_head); 1370 if(m_head == NULL) 1371 break; 1372 1373 /* 1374 * Pack the data into the tx ring. If we dont have 1375 * enough room, let the chip drain the ring. 1376 */ 1377 if(bfe_encap(sc, m_head, &idx)) { 1378 IF_PREPEND(&ifp->if_snd, m_head); 1379 ifp->if_flags |= IFF_OACTIVE; 1380 break; 1381 } 1382 1383 /* 1384 * If there's a BPF listener, bounce a copy of this frame 1385 * to him. 1386 */ 1387 BPF_MTAP(ifp, m_head); 1388 } 1389 1390 sc->bfe_tx_prod = idx; 1391 /* Transmit - twice due to apparent hardware bug */ 1392 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1393 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1394 1395 /* 1396 * Set a timeout in case the chip goes out to lunch. 1397 */ 1398 ifp->if_timer = 5; 1399 BFE_UNLOCK(sc); 1400 } 1401 1402 static void 1403 bfe_init(void *xsc) 1404 { 1405 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1406 struct ifnet *ifp = &sc->arpcom.ac_if; 1407 1408 BFE_LOCK(sc); 1409 1410 if (ifp->if_flags & IFF_RUNNING) { 1411 BFE_UNLOCK(sc); 1412 return; 1413 } 1414 1415 bfe_stop(sc); 1416 bfe_chip_reset(sc); 1417 1418 if (bfe_list_rx_init(sc) == ENOBUFS) { 1419 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1420 sc->bfe_unit); 1421 bfe_stop(sc); 1422 return; 1423 } 1424 1425 bfe_set_rx_mode(sc); 1426 1427 /* Enable the chip and core */ 1428 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1429 /* Enable interrupts */ 1430 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1431 1432 bfe_ifmedia_upd(ifp); 1433 ifp->if_flags |= IFF_RUNNING; 1434 ifp->if_flags &= ~IFF_OACTIVE; 1435 1436 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1437 BFE_UNLOCK(sc); 1438 } 1439 1440 /* 1441 * Set media options. 1442 */ 1443 static int 1444 bfe_ifmedia_upd(struct ifnet *ifp) 1445 { 1446 struct bfe_softc *sc; 1447 struct mii_data *mii; 1448 1449 sc = ifp->if_softc; 1450 1451 BFE_LOCK(sc); 1452 1453 mii = device_get_softc(sc->bfe_miibus); 1454 sc->bfe_link = 0; 1455 if (mii->mii_instance) { 1456 struct mii_softc *miisc; 1457 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1458 miisc = LIST_NEXT(miisc, mii_list)) 1459 mii_phy_reset(miisc); 1460 } 1461 mii_mediachg(mii); 1462 1463 BFE_UNLOCK(sc); 1464 return(0); 1465 } 1466 1467 /* 1468 * Report current media status. 1469 */ 1470 static void 1471 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1472 { 1473 struct bfe_softc *sc = ifp->if_softc; 1474 struct mii_data *mii; 1475 1476 BFE_LOCK(sc); 1477 1478 mii = device_get_softc(sc->bfe_miibus); 1479 mii_pollstat(mii); 1480 ifmr->ifm_active = mii->mii_media_active; 1481 ifmr->ifm_status = mii->mii_media_status; 1482 1483 BFE_UNLOCK(sc); 1484 } 1485 1486 static int 1487 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1488 { 1489 struct bfe_softc *sc = ifp->if_softc; 1490 struct ifreq *ifr = (struct ifreq *) data; 1491 struct mii_data *mii; 1492 int error = 0; 1493 1494 BFE_LOCK(sc); 1495 1496 switch(command) { 1497 case SIOCSIFFLAGS: 1498 if(ifp->if_flags & IFF_UP) 1499 if(ifp->if_flags & IFF_RUNNING) 1500 bfe_set_rx_mode(sc); 1501 else 1502 bfe_init(sc); 1503 else if(ifp->if_flags & IFF_RUNNING) 1504 bfe_stop(sc); 1505 break; 1506 case SIOCADDMULTI: 1507 case SIOCDELMULTI: 1508 if(ifp->if_flags & IFF_RUNNING) 1509 bfe_set_rx_mode(sc); 1510 break; 1511 case SIOCGIFMEDIA: 1512 case SIOCSIFMEDIA: 1513 mii = device_get_softc(sc->bfe_miibus); 1514 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1515 command); 1516 break; 1517 default: 1518 error = ether_ioctl(ifp, command, data); 1519 break; 1520 } 1521 1522 BFE_UNLOCK(sc); 1523 return error; 1524 } 1525 1526 static void 1527 bfe_watchdog(struct ifnet *ifp) 1528 { 1529 struct bfe_softc *sc; 1530 1531 sc = ifp->if_softc; 1532 1533 BFE_LOCK(sc); 1534 1535 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1536 1537 ifp->if_flags &= ~IFF_RUNNING; 1538 bfe_init(sc); 1539 1540 ifp->if_oerrors++; 1541 1542 BFE_UNLOCK(sc); 1543 } 1544 1545 static void 1546 bfe_tick(void *xsc) 1547 { 1548 struct bfe_softc *sc = xsc; 1549 struct mii_data *mii; 1550 1551 if (sc == NULL) 1552 return; 1553 1554 BFE_LOCK(sc); 1555 1556 mii = device_get_softc(sc->bfe_miibus); 1557 1558 bfe_stats_update(sc); 1559 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1560 1561 if(sc->bfe_link) { 1562 BFE_UNLOCK(sc); 1563 return; 1564 } 1565 1566 mii_tick(mii); 1567 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1568 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1569 sc->bfe_link++; 1570 1571 BFE_UNLOCK(sc); 1572 } 1573 1574 /* 1575 * Stop the adapter and free any mbufs allocated to the 1576 * RX and TX lists. 1577 */ 1578 static void 1579 bfe_stop(struct bfe_softc *sc) 1580 { 1581 struct ifnet *ifp; 1582 1583 BFE_LOCK(sc); 1584 1585 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1586 1587 ifp = &sc->arpcom.ac_if; 1588 1589 bfe_chip_halt(sc); 1590 bfe_tx_ring_free(sc); 1591 bfe_rx_ring_free(sc); 1592 1593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1594 1595 BFE_UNLOCK(sc); 1596 } 1597