1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/if_vlan_var.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/bfe/if_bfereg.h> 62 63 MODULE_DEPEND(bfe, pci, 1, 1, 1); 64 MODULE_DEPEND(bfe, ether, 1, 1, 1); 65 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 66 67 /* "device miibus" required. See GENERIC if you get errors here. */ 68 #include "miibus_if.h" 69 70 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 71 72 static struct bfe_type bfe_devs[] = { 73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 74 "Broadcom BCM4401 Fast Ethernet" }, 75 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 76 "Broadcom BCM4401-B0 Fast Ethernet" }, 77 { 0, 0, NULL } 78 }; 79 80 static int bfe_probe (device_t); 81 static int bfe_attach (device_t); 82 static int bfe_detach (device_t); 83 static int bfe_suspend (device_t); 84 static int bfe_resume (device_t); 85 static void bfe_release_resources (struct bfe_softc *); 86 static void bfe_intr (void *); 87 static int bfe_encap (struct bfe_softc *, struct mbuf **); 88 static void bfe_start (struct ifnet *); 89 static void bfe_start_locked (struct ifnet *); 90 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 91 static void bfe_init (void *); 92 static void bfe_init_locked (void *); 93 static void bfe_stop (struct bfe_softc *); 94 static void bfe_watchdog (struct bfe_softc *); 95 static int bfe_shutdown (device_t); 96 static void bfe_tick (void *); 97 static void bfe_txeof (struct bfe_softc *); 98 static void bfe_rxeof (struct bfe_softc *); 99 static void bfe_set_rx_mode (struct bfe_softc *); 100 static int bfe_list_rx_init (struct bfe_softc *); 101 static void bfe_list_tx_init (struct bfe_softc *); 102 static void bfe_discard_buf (struct bfe_softc *, int); 103 static int bfe_list_newbuf (struct bfe_softc *, int); 104 static void bfe_rx_ring_free (struct bfe_softc *); 105 106 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 107 static int bfe_ifmedia_upd (struct ifnet *); 108 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 static int bfe_miibus_readreg (device_t, int, int); 110 static int bfe_miibus_writereg (device_t, int, int, int); 111 static void bfe_miibus_statchg (device_t); 112 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 113 u_long, const int); 114 static void bfe_get_config (struct bfe_softc *sc); 115 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 116 static void bfe_stats_update (struct bfe_softc *); 117 static void bfe_clear_stats (struct bfe_softc *); 118 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 119 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 120 static int bfe_resetphy (struct bfe_softc *); 121 static int bfe_setupphy (struct bfe_softc *); 122 static void bfe_chip_reset (struct bfe_softc *); 123 static void bfe_chip_halt (struct bfe_softc *); 124 static void bfe_core_reset (struct bfe_softc *); 125 static void bfe_core_disable (struct bfe_softc *); 126 static int bfe_dma_alloc (struct bfe_softc *); 127 static void bfe_dma_free (struct bfe_softc *sc); 128 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 129 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 130 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 DEVMETHOD(device_suspend, bfe_suspend), 139 DEVMETHOD(device_resume, bfe_resume), 140 141 /* MII interface */ 142 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 143 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 144 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 145 146 DEVMETHOD_END 147 }; 148 149 static driver_t bfe_driver = { 150 "bfe", 151 bfe_methods, 152 sizeof(struct bfe_softc) 153 }; 154 155 static devclass_t bfe_devclass; 156 157 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 158 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 159 160 /* 161 * Probe for a Broadcom 4401 chip. 162 */ 163 static int 164 bfe_probe(device_t dev) 165 { 166 struct bfe_type *t; 167 168 t = bfe_devs; 169 170 while (t->bfe_name != NULL) { 171 if (pci_get_vendor(dev) == t->bfe_vid && 172 pci_get_device(dev) == t->bfe_did) { 173 device_set_desc(dev, t->bfe_name); 174 return (BUS_PROBE_DEFAULT); 175 } 176 t++; 177 } 178 179 return (ENXIO); 180 } 181 182 struct bfe_dmamap_arg { 183 bus_addr_t bfe_busaddr; 184 }; 185 186 static int 187 bfe_dma_alloc(struct bfe_softc *sc) 188 { 189 struct bfe_dmamap_arg ctx; 190 struct bfe_rx_data *rd; 191 struct bfe_tx_data *td; 192 int error, i; 193 194 /* 195 * parent tag. Apparently the chip cannot handle any DMA address 196 * greater than 1GB. 197 */ 198 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 199 1, 0, /* alignment, boundary */ 200 BFE_DMA_MAXADDR, /* lowaddr */ 201 BUS_SPACE_MAXADDR, /* highaddr */ 202 NULL, NULL, /* filter, filterarg */ 203 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 204 0, /* nsegments */ 205 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 206 0, /* flags */ 207 NULL, NULL, /* lockfunc, lockarg */ 208 &sc->bfe_parent_tag); 209 if (error != 0) { 210 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 211 goto fail; 212 } 213 214 /* Create tag for Tx ring. */ 215 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 216 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 217 BUS_SPACE_MAXADDR, /* lowaddr */ 218 BUS_SPACE_MAXADDR, /* highaddr */ 219 NULL, NULL, /* filter, filterarg */ 220 BFE_TX_LIST_SIZE, /* maxsize */ 221 1, /* nsegments */ 222 BFE_TX_LIST_SIZE, /* maxsegsize */ 223 0, /* flags */ 224 NULL, NULL, /* lockfunc, lockarg */ 225 &sc->bfe_tx_tag); 226 if (error != 0) { 227 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 228 goto fail; 229 } 230 231 /* Create tag for Rx ring. */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 233 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 234 BUS_SPACE_MAXADDR, /* lowaddr */ 235 BUS_SPACE_MAXADDR, /* highaddr */ 236 NULL, NULL, /* filter, filterarg */ 237 BFE_RX_LIST_SIZE, /* maxsize */ 238 1, /* nsegments */ 239 BFE_RX_LIST_SIZE, /* maxsegsize */ 240 0, /* flags */ 241 NULL, NULL, /* lockfunc, lockarg */ 242 &sc->bfe_rx_tag); 243 if (error != 0) { 244 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 245 goto fail; 246 } 247 248 /* Create tag for Tx buffers. */ 249 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 250 1, 0, /* alignment, boundary */ 251 BUS_SPACE_MAXADDR, /* lowaddr */ 252 BUS_SPACE_MAXADDR, /* highaddr */ 253 NULL, NULL, /* filter, filterarg */ 254 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 255 BFE_MAXTXSEGS, /* nsegments */ 256 MCLBYTES, /* maxsegsize */ 257 0, /* flags */ 258 NULL, NULL, /* lockfunc, lockarg */ 259 &sc->bfe_txmbuf_tag); 260 if (error != 0) { 261 device_printf(sc->bfe_dev, 262 "cannot create Tx buffer DMA tag.\n"); 263 goto fail; 264 } 265 266 /* Create tag for Rx buffers. */ 267 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 268 1, 0, /* alignment, boundary */ 269 BUS_SPACE_MAXADDR, /* lowaddr */ 270 BUS_SPACE_MAXADDR, /* highaddr */ 271 NULL, NULL, /* filter, filterarg */ 272 MCLBYTES, /* maxsize */ 273 1, /* nsegments */ 274 MCLBYTES, /* maxsegsize */ 275 0, /* flags */ 276 NULL, NULL, /* lockfunc, lockarg */ 277 &sc->bfe_rxmbuf_tag); 278 if (error != 0) { 279 device_printf(sc->bfe_dev, 280 "cannot create Rx buffer DMA tag.\n"); 281 goto fail; 282 } 283 284 /* Allocate DMA'able memory and load DMA map. */ 285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 286 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 287 if (error != 0) { 288 device_printf(sc->bfe_dev, 289 "cannot allocate DMA'able memory for Tx ring.\n"); 290 goto fail; 291 } 292 ctx.bfe_busaddr = 0; 293 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 294 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 295 BUS_DMA_NOWAIT); 296 if (error != 0 || ctx.bfe_busaddr == 0) { 297 device_printf(sc->bfe_dev, 298 "cannot load DMA'able memory for Tx ring.\n"); 299 goto fail; 300 } 301 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 302 303 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 304 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 305 if (error != 0) { 306 device_printf(sc->bfe_dev, 307 "cannot allocate DMA'able memory for Rx ring.\n"); 308 goto fail; 309 } 310 ctx.bfe_busaddr = 0; 311 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 312 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 313 BUS_DMA_NOWAIT); 314 if (error != 0 || ctx.bfe_busaddr == 0) { 315 device_printf(sc->bfe_dev, 316 "cannot load DMA'able memory for Rx ring.\n"); 317 goto fail; 318 } 319 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 320 321 /* Create DMA maps for Tx buffers. */ 322 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 323 td = &sc->bfe_tx_ring[i]; 324 td->bfe_mbuf = NULL; 325 td->bfe_map = NULL; 326 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 327 if (error != 0) { 328 device_printf(sc->bfe_dev, 329 "cannot create DMA map for Tx.\n"); 330 goto fail; 331 } 332 } 333 334 /* Create spare DMA map for Rx buffers. */ 335 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 336 if (error != 0) { 337 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 338 goto fail; 339 } 340 /* Create DMA maps for Rx buffers. */ 341 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 342 rd = &sc->bfe_rx_ring[i]; 343 rd->bfe_mbuf = NULL; 344 rd->bfe_map = NULL; 345 rd->bfe_ctrl = 0; 346 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 347 if (error != 0) { 348 device_printf(sc->bfe_dev, 349 "cannot create DMA map for Rx.\n"); 350 goto fail; 351 } 352 } 353 354 fail: 355 return (error); 356 } 357 358 static void 359 bfe_dma_free(struct bfe_softc *sc) 360 { 361 struct bfe_tx_data *td; 362 struct bfe_rx_data *rd; 363 int i; 364 365 /* Tx ring. */ 366 if (sc->bfe_tx_tag != NULL) { 367 if (sc->bfe_tx_map != NULL) 368 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 369 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 370 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 371 sc->bfe_tx_map); 372 sc->bfe_tx_map = NULL; 373 sc->bfe_tx_list = NULL; 374 bus_dma_tag_destroy(sc->bfe_tx_tag); 375 sc->bfe_tx_tag = NULL; 376 } 377 378 /* Rx ring. */ 379 if (sc->bfe_rx_tag != NULL) { 380 if (sc->bfe_rx_map != NULL) 381 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 382 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 383 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 384 sc->bfe_rx_map); 385 sc->bfe_rx_map = NULL; 386 sc->bfe_rx_list = NULL; 387 bus_dma_tag_destroy(sc->bfe_rx_tag); 388 sc->bfe_rx_tag = NULL; 389 } 390 391 /* Tx buffers. */ 392 if (sc->bfe_txmbuf_tag != NULL) { 393 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 394 td = &sc->bfe_tx_ring[i]; 395 if (td->bfe_map != NULL) { 396 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 397 td->bfe_map); 398 td->bfe_map = NULL; 399 } 400 } 401 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 402 sc->bfe_txmbuf_tag = NULL; 403 } 404 405 /* Rx buffers. */ 406 if (sc->bfe_rxmbuf_tag != NULL) { 407 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 408 rd = &sc->bfe_rx_ring[i]; 409 if (rd->bfe_map != NULL) { 410 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 411 rd->bfe_map); 412 rd->bfe_map = NULL; 413 } 414 } 415 if (sc->bfe_rx_sparemap != NULL) { 416 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 417 sc->bfe_rx_sparemap); 418 sc->bfe_rx_sparemap = NULL; 419 } 420 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 421 sc->bfe_rxmbuf_tag = NULL; 422 } 423 424 if (sc->bfe_parent_tag != NULL) { 425 bus_dma_tag_destroy(sc->bfe_parent_tag); 426 sc->bfe_parent_tag = NULL; 427 } 428 } 429 430 static int 431 bfe_attach(device_t dev) 432 { 433 struct ifnet *ifp = NULL; 434 struct bfe_softc *sc; 435 int error = 0, rid; 436 437 sc = device_get_softc(dev); 438 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 439 MTX_DEF); 440 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 441 442 sc->bfe_dev = dev; 443 444 /* 445 * Map control/status registers. 446 */ 447 pci_enable_busmaster(dev); 448 449 rid = PCIR_BAR(0); 450 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 451 RF_ACTIVE); 452 if (sc->bfe_res == NULL) { 453 device_printf(dev, "couldn't map memory\n"); 454 error = ENXIO; 455 goto fail; 456 } 457 458 /* Allocate interrupt */ 459 rid = 0; 460 461 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 462 RF_SHAREABLE | RF_ACTIVE); 463 if (sc->bfe_irq == NULL) { 464 device_printf(dev, "couldn't map interrupt\n"); 465 error = ENXIO; 466 goto fail; 467 } 468 469 if (bfe_dma_alloc(sc) != 0) { 470 device_printf(dev, "failed to allocate DMA resources\n"); 471 error = ENXIO; 472 goto fail; 473 } 474 475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 476 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 477 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats, 478 "I", "Statistics"); 479 480 /* Set up ifnet structure */ 481 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 482 if (ifp == NULL) { 483 device_printf(dev, "failed to if_alloc()\n"); 484 error = ENOSPC; 485 goto fail; 486 } 487 ifp->if_softc = sc; 488 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 490 ifp->if_ioctl = bfe_ioctl; 491 ifp->if_start = bfe_start; 492 ifp->if_init = bfe_init; 493 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 494 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 495 IFQ_SET_READY(&ifp->if_snd); 496 497 bfe_get_config(sc); 498 499 /* Reset the chip and turn on the PHY */ 500 BFE_LOCK(sc); 501 bfe_chip_reset(sc); 502 BFE_UNLOCK(sc); 503 504 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 505 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 506 0); 507 if (error != 0) { 508 device_printf(dev, "attaching PHYs failed\n"); 509 goto fail; 510 } 511 512 ether_ifattach(ifp, sc->bfe_enaddr); 513 514 /* 515 * Tell the upper layer(s) we support long frames. 516 */ 517 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 518 ifp->if_capabilities |= IFCAP_VLAN_MTU; 519 ifp->if_capenable |= IFCAP_VLAN_MTU; 520 521 /* 522 * Hook interrupt last to avoid having to lock softc 523 */ 524 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 525 NULL, bfe_intr, sc, &sc->bfe_intrhand); 526 527 if (error) { 528 device_printf(dev, "couldn't set up irq\n"); 529 goto fail; 530 } 531 fail: 532 if (error != 0) 533 bfe_detach(dev); 534 return (error); 535 } 536 537 static int 538 bfe_detach(device_t dev) 539 { 540 struct bfe_softc *sc; 541 struct ifnet *ifp; 542 543 sc = device_get_softc(dev); 544 545 ifp = sc->bfe_ifp; 546 547 if (device_is_attached(dev)) { 548 BFE_LOCK(sc); 549 sc->bfe_flags |= BFE_FLAG_DETACH; 550 bfe_stop(sc); 551 BFE_UNLOCK(sc); 552 callout_drain(&sc->bfe_stat_co); 553 if (ifp != NULL) 554 ether_ifdetach(ifp); 555 } 556 557 BFE_LOCK(sc); 558 bfe_chip_reset(sc); 559 BFE_UNLOCK(sc); 560 561 bus_generic_detach(dev); 562 if (sc->bfe_miibus != NULL) 563 device_delete_child(dev, sc->bfe_miibus); 564 565 bfe_release_resources(sc); 566 bfe_dma_free(sc); 567 mtx_destroy(&sc->bfe_mtx); 568 569 return (0); 570 } 571 572 /* 573 * Stop all chip I/O so that the kernel's probe routines don't 574 * get confused by errant DMAs when rebooting. 575 */ 576 static int 577 bfe_shutdown(device_t dev) 578 { 579 struct bfe_softc *sc; 580 581 sc = device_get_softc(dev); 582 BFE_LOCK(sc); 583 bfe_stop(sc); 584 585 BFE_UNLOCK(sc); 586 587 return (0); 588 } 589 590 static int 591 bfe_suspend(device_t dev) 592 { 593 struct bfe_softc *sc; 594 595 sc = device_get_softc(dev); 596 BFE_LOCK(sc); 597 bfe_stop(sc); 598 BFE_UNLOCK(sc); 599 600 return (0); 601 } 602 603 static int 604 bfe_resume(device_t dev) 605 { 606 struct bfe_softc *sc; 607 struct ifnet *ifp; 608 609 sc = device_get_softc(dev); 610 ifp = sc->bfe_ifp; 611 BFE_LOCK(sc); 612 bfe_chip_reset(sc); 613 if (ifp->if_flags & IFF_UP) { 614 bfe_init_locked(sc); 615 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 616 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 617 bfe_start_locked(ifp); 618 } 619 BFE_UNLOCK(sc); 620 621 return (0); 622 } 623 624 static int 625 bfe_miibus_readreg(device_t dev, int phy, int reg) 626 { 627 struct bfe_softc *sc; 628 u_int32_t ret; 629 630 sc = device_get_softc(dev); 631 bfe_readphy(sc, reg, &ret); 632 633 return (ret); 634 } 635 636 static int 637 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 638 { 639 struct bfe_softc *sc; 640 641 sc = device_get_softc(dev); 642 bfe_writephy(sc, reg, val); 643 644 return (0); 645 } 646 647 static void 648 bfe_miibus_statchg(device_t dev) 649 { 650 struct bfe_softc *sc; 651 struct mii_data *mii; 652 u_int32_t val, flow; 653 654 sc = device_get_softc(dev); 655 mii = device_get_softc(sc->bfe_miibus); 656 657 sc->bfe_flags &= ~BFE_FLAG_LINK; 658 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 659 (IFM_ACTIVE | IFM_AVALID)) { 660 switch (IFM_SUBTYPE(mii->mii_media_active)) { 661 case IFM_10_T: 662 case IFM_100_TX: 663 sc->bfe_flags |= BFE_FLAG_LINK; 664 break; 665 default: 666 break; 667 } 668 } 669 670 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 671 val = CSR_READ_4(sc, BFE_TX_CTRL); 672 val &= ~BFE_TX_DUPLEX; 673 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 674 val |= BFE_TX_DUPLEX; 675 flow = 0; 676 #ifdef notyet 677 flow = CSR_READ_4(sc, BFE_RXCONF); 678 flow &= ~BFE_RXCONF_FLOW; 679 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 680 IFM_ETH_RXPAUSE) != 0) 681 flow |= BFE_RXCONF_FLOW; 682 CSR_WRITE_4(sc, BFE_RXCONF, flow); 683 /* 684 * It seems that the hardware has Tx pause issues 685 * so enable only Rx pause. 686 */ 687 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 688 flow &= ~BFE_FLOW_PAUSE_ENAB; 689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 690 #endif 691 } 692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 693 } 694 695 static void 696 bfe_tx_ring_free(struct bfe_softc *sc) 697 { 698 int i; 699 700 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 701 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 702 bus_dmamap_sync(sc->bfe_txmbuf_tag, 703 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 704 bus_dmamap_unload(sc->bfe_txmbuf_tag, 705 sc->bfe_tx_ring[i].bfe_map); 706 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 707 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 708 } 709 } 710 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 711 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 } 714 715 static void 716 bfe_rx_ring_free(struct bfe_softc *sc) 717 { 718 int i; 719 720 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 721 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 722 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 723 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 725 sc->bfe_rx_ring[i].bfe_map); 726 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 727 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 728 } 729 } 730 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 731 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 } 734 735 static int 736 bfe_list_rx_init(struct bfe_softc *sc) 737 { 738 struct bfe_rx_data *rd; 739 int i; 740 741 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 742 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 743 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 744 rd = &sc->bfe_rx_ring[i]; 745 rd->bfe_mbuf = NULL; 746 rd->bfe_ctrl = 0; 747 if (bfe_list_newbuf(sc, i) != 0) 748 return (ENOBUFS); 749 } 750 751 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 754 755 return (0); 756 } 757 758 static void 759 bfe_list_tx_init(struct bfe_softc *sc) 760 { 761 int i; 762 763 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 764 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 765 for (i = 0; i < BFE_TX_LIST_CNT; i++) 766 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 767 768 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 } 771 772 static void 773 bfe_discard_buf(struct bfe_softc *sc, int c) 774 { 775 struct bfe_rx_data *r; 776 struct bfe_desc *d; 777 778 r = &sc->bfe_rx_ring[c]; 779 d = &sc->bfe_rx_list[c]; 780 d->bfe_ctrl = htole32(r->bfe_ctrl); 781 } 782 783 static int 784 bfe_list_newbuf(struct bfe_softc *sc, int c) 785 { 786 struct bfe_rxheader *rx_header; 787 struct bfe_desc *d; 788 struct bfe_rx_data *r; 789 struct mbuf *m; 790 bus_dma_segment_t segs[1]; 791 bus_dmamap_t map; 792 u_int32_t ctrl; 793 int nsegs; 794 795 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 796 m->m_len = m->m_pkthdr.len = MCLBYTES; 797 798 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 799 m, segs, &nsegs, 0) != 0) { 800 m_freem(m); 801 return (ENOBUFS); 802 } 803 804 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 805 r = &sc->bfe_rx_ring[c]; 806 if (r->bfe_mbuf != NULL) { 807 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 808 BUS_DMASYNC_POSTREAD); 809 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 810 } 811 map = r->bfe_map; 812 r->bfe_map = sc->bfe_rx_sparemap; 813 sc->bfe_rx_sparemap = map; 814 r->bfe_mbuf = m; 815 816 rx_header = mtod(m, struct bfe_rxheader *); 817 rx_header->len = 0; 818 rx_header->flags = 0; 819 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 820 821 ctrl = segs[0].ds_len & BFE_DESC_LEN; 822 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 823 __func__, ctrl)); 824 if (c == BFE_RX_LIST_CNT - 1) 825 ctrl |= BFE_DESC_EOT; 826 r->bfe_ctrl = ctrl; 827 828 d = &sc->bfe_rx_list[c]; 829 d->bfe_ctrl = htole32(ctrl); 830 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 831 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 832 833 return (0); 834 } 835 836 static void 837 bfe_get_config(struct bfe_softc *sc) 838 { 839 u_int8_t eeprom[128]; 840 841 bfe_read_eeprom(sc, eeprom); 842 843 sc->bfe_enaddr[0] = eeprom[79]; 844 sc->bfe_enaddr[1] = eeprom[78]; 845 sc->bfe_enaddr[2] = eeprom[81]; 846 sc->bfe_enaddr[3] = eeprom[80]; 847 sc->bfe_enaddr[4] = eeprom[83]; 848 sc->bfe_enaddr[5] = eeprom[82]; 849 850 sc->bfe_phyaddr = eeprom[90] & 0x1f; 851 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 852 853 sc->bfe_core_unit = 0; 854 sc->bfe_dma_offset = BFE_PCI_DMA; 855 } 856 857 static void 858 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 859 { 860 u_int32_t bar_orig, pci_rev, val; 861 862 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 863 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 864 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 865 866 val = CSR_READ_4(sc, BFE_SBINTVEC); 867 val |= cores; 868 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 869 870 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 871 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 872 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 873 874 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 875 } 876 877 static void 878 bfe_clear_stats(struct bfe_softc *sc) 879 { 880 uint32_t reg; 881 882 BFE_LOCK_ASSERT(sc); 883 884 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 885 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 886 CSR_READ_4(sc, reg); 887 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 888 CSR_READ_4(sc, reg); 889 } 890 891 static int 892 bfe_resetphy(struct bfe_softc *sc) 893 { 894 u_int32_t val; 895 896 bfe_writephy(sc, 0, BMCR_RESET); 897 DELAY(100); 898 bfe_readphy(sc, 0, &val); 899 if (val & BMCR_RESET) { 900 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 901 return (ENXIO); 902 } 903 return (0); 904 } 905 906 static void 907 bfe_chip_halt(struct bfe_softc *sc) 908 { 909 BFE_LOCK_ASSERT(sc); 910 /* disable interrupts - not that it actually does..*/ 911 CSR_WRITE_4(sc, BFE_IMASK, 0); 912 CSR_READ_4(sc, BFE_IMASK); 913 914 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 915 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 916 917 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 918 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 919 DELAY(10); 920 } 921 922 static void 923 bfe_chip_reset(struct bfe_softc *sc) 924 { 925 u_int32_t val; 926 927 BFE_LOCK_ASSERT(sc); 928 929 /* Set the interrupt vector for the enet core */ 930 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 931 932 /* is core up? */ 933 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 934 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 935 if (val == BFE_CLOCK) { 936 /* It is, so shut it down */ 937 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 938 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 939 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 940 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 941 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 942 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 943 100, 0); 944 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 945 } 946 947 bfe_core_reset(sc); 948 bfe_clear_stats(sc); 949 950 /* 951 * We want the phy registers to be accessible even when 952 * the driver is "downed" so initialize MDC preamble, frequency, 953 * and whether internal or external phy here. 954 */ 955 956 /* 4402 has 62.5Mhz SB clock and internal phy */ 957 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 958 959 /* Internal or external PHY? */ 960 val = CSR_READ_4(sc, BFE_DEVCTRL); 961 if (!(val & BFE_IPP)) 962 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 963 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 964 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 965 DELAY(100); 966 } 967 968 /* Enable CRC32 generation and set proper LED modes */ 969 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 970 971 /* Reset or clear powerdown control bit */ 972 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 973 974 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 975 BFE_LAZY_FC_MASK)); 976 977 /* 978 * We don't want lazy interrupts, so just send them at 979 * the end of a frame, please 980 */ 981 BFE_OR(sc, BFE_RCV_LAZY, 0); 982 983 /* Set max lengths, accounting for VLAN tags */ 984 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 985 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 986 987 /* Set watermark XXX - magic */ 988 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 989 990 /* 991 * Initialise DMA channels 992 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 993 */ 994 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 995 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 996 997 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 998 BFE_RX_CTRL_ENABLE); 999 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1000 1001 bfe_resetphy(sc); 1002 bfe_setupphy(sc); 1003 } 1004 1005 static void 1006 bfe_core_disable(struct bfe_softc *sc) 1007 { 1008 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1009 return; 1010 1011 /* 1012 * Set reject, wait for it set, then wait for the core to stop 1013 * being busy, then set reset and reject and enable the clocks. 1014 */ 1015 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1016 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1017 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1018 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1019 BFE_RESET)); 1020 CSR_READ_4(sc, BFE_SBTMSLOW); 1021 DELAY(10); 1022 /* Leave reset and reject set */ 1023 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1024 DELAY(10); 1025 } 1026 1027 static void 1028 bfe_core_reset(struct bfe_softc *sc) 1029 { 1030 u_int32_t val; 1031 1032 /* Disable the core */ 1033 bfe_core_disable(sc); 1034 1035 /* and bring it back up */ 1036 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1037 CSR_READ_4(sc, BFE_SBTMSLOW); 1038 DELAY(10); 1039 1040 /* Chip bug, clear SERR, IB and TO if they are set. */ 1041 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1042 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1043 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1044 if (val & (BFE_IBE | BFE_TO)) 1045 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1046 1047 /* Clear reset and allow it to move through the core */ 1048 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1049 CSR_READ_4(sc, BFE_SBTMSLOW); 1050 DELAY(10); 1051 1052 /* Leave the clock set */ 1053 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1054 CSR_READ_4(sc, BFE_SBTMSLOW); 1055 DELAY(10); 1056 } 1057 1058 static void 1059 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1060 { 1061 u_int32_t val; 1062 1063 val = ((u_int32_t) data[2]) << 24; 1064 val |= ((u_int32_t) data[3]) << 16; 1065 val |= ((u_int32_t) data[4]) << 8; 1066 val |= ((u_int32_t) data[5]); 1067 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1068 val = (BFE_CAM_HI_VALID | 1069 (((u_int32_t) data[0]) << 8) | 1070 (((u_int32_t) data[1]))); 1071 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1072 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1073 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1074 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1075 } 1076 1077 static void 1078 bfe_set_rx_mode(struct bfe_softc *sc) 1079 { 1080 struct ifnet *ifp = sc->bfe_ifp; 1081 struct ifmultiaddr *ifma; 1082 u_int32_t val; 1083 int i = 0; 1084 1085 BFE_LOCK_ASSERT(sc); 1086 1087 val = CSR_READ_4(sc, BFE_RXCONF); 1088 1089 if (ifp->if_flags & IFF_PROMISC) 1090 val |= BFE_RXCONF_PROMISC; 1091 else 1092 val &= ~BFE_RXCONF_PROMISC; 1093 1094 if (ifp->if_flags & IFF_BROADCAST) 1095 val &= ~BFE_RXCONF_DBCAST; 1096 else 1097 val |= BFE_RXCONF_DBCAST; 1098 1099 1100 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1101 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1102 1103 if (ifp->if_flags & IFF_ALLMULTI) 1104 val |= BFE_RXCONF_ALLMULTI; 1105 else { 1106 val &= ~BFE_RXCONF_ALLMULTI; 1107 if_maddr_rlock(ifp); 1108 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1109 if (ifma->ifma_addr->sa_family != AF_LINK) 1110 continue; 1111 bfe_cam_write(sc, 1112 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1113 } 1114 if_maddr_runlock(ifp); 1115 } 1116 1117 CSR_WRITE_4(sc, BFE_RXCONF, val); 1118 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1119 } 1120 1121 static void 1122 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1123 { 1124 struct bfe_dmamap_arg *ctx; 1125 1126 if (error != 0) 1127 return; 1128 1129 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1130 1131 ctx = (struct bfe_dmamap_arg *)arg; 1132 ctx->bfe_busaddr = segs[0].ds_addr; 1133 } 1134 1135 static void 1136 bfe_release_resources(struct bfe_softc *sc) 1137 { 1138 1139 if (sc->bfe_intrhand != NULL) 1140 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1141 1142 if (sc->bfe_irq != NULL) 1143 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1144 1145 if (sc->bfe_res != NULL) 1146 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1147 sc->bfe_res); 1148 1149 if (sc->bfe_ifp != NULL) 1150 if_free(sc->bfe_ifp); 1151 } 1152 1153 static void 1154 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1155 { 1156 long i; 1157 u_int16_t *ptr = (u_int16_t *)data; 1158 1159 for(i = 0; i < 128; i += 2) 1160 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1161 } 1162 1163 static int 1164 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1165 u_long timeout, const int clear) 1166 { 1167 u_long i; 1168 1169 for (i = 0; i < timeout; i++) { 1170 u_int32_t val = CSR_READ_4(sc, reg); 1171 1172 if (clear && !(val & bit)) 1173 break; 1174 if (!clear && (val & bit)) 1175 break; 1176 DELAY(10); 1177 } 1178 if (i == timeout) { 1179 device_printf(sc->bfe_dev, 1180 "BUG! Timeout waiting for bit %08x of register " 1181 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1182 return (-1); 1183 } 1184 return (0); 1185 } 1186 1187 static int 1188 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1189 { 1190 int err; 1191 1192 /* Clear MII ISR */ 1193 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1194 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1195 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1196 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1197 (reg << BFE_MDIO_RA_SHIFT) | 1198 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1199 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1200 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1201 1202 return (err); 1203 } 1204 1205 static int 1206 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1207 { 1208 int status; 1209 1210 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1211 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1212 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1213 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1214 (reg << BFE_MDIO_RA_SHIFT) | 1215 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1216 (val & BFE_MDIO_DATA_DATA))); 1217 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1218 1219 return (status); 1220 } 1221 1222 /* 1223 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1224 * twice 1225 */ 1226 static int 1227 bfe_setupphy(struct bfe_softc *sc) 1228 { 1229 u_int32_t val; 1230 1231 /* Enable activity LED */ 1232 bfe_readphy(sc, 26, &val); 1233 bfe_writephy(sc, 26, val & 0x7fff); 1234 bfe_readphy(sc, 26, &val); 1235 1236 /* Enable traffic meter LED mode */ 1237 bfe_readphy(sc, 27, &val); 1238 bfe_writephy(sc, 27, val | (1 << 6)); 1239 1240 return (0); 1241 } 1242 1243 static void 1244 bfe_stats_update(struct bfe_softc *sc) 1245 { 1246 struct bfe_hw_stats *stats; 1247 struct ifnet *ifp; 1248 uint32_t mib[BFE_MIB_CNT]; 1249 uint32_t reg, *val; 1250 1251 BFE_LOCK_ASSERT(sc); 1252 1253 val = mib; 1254 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 1255 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1256 *val++ = CSR_READ_4(sc, reg); 1257 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1258 *val++ = CSR_READ_4(sc, reg); 1259 1260 ifp = sc->bfe_ifp; 1261 stats = &sc->bfe_stats; 1262 /* Tx stat. */ 1263 stats->tx_good_octets += mib[MIB_TX_GOOD_O]; 1264 stats->tx_good_frames += mib[MIB_TX_GOOD_P]; 1265 stats->tx_octets += mib[MIB_TX_O]; 1266 stats->tx_frames += mib[MIB_TX_P]; 1267 stats->tx_bcast_frames += mib[MIB_TX_BCAST]; 1268 stats->tx_mcast_frames += mib[MIB_TX_MCAST]; 1269 stats->tx_pkts_64 += mib[MIB_TX_64]; 1270 stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; 1271 stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; 1272 stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; 1273 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; 1274 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; 1275 stats->tx_jabbers += mib[MIB_TX_JABBER]; 1276 stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; 1277 stats->tx_frag_frames += mib[MIB_TX_FRAG]; 1278 stats->tx_underruns += mib[MIB_TX_URUNS]; 1279 stats->tx_colls += mib[MIB_TX_TCOLS]; 1280 stats->tx_single_colls += mib[MIB_TX_SCOLS]; 1281 stats->tx_multi_colls += mib[MIB_TX_MCOLS]; 1282 stats->tx_excess_colls += mib[MIB_TX_ECOLS]; 1283 stats->tx_late_colls += mib[MIB_TX_LCOLS]; 1284 stats->tx_deferrals += mib[MIB_TX_DEFERED]; 1285 stats->tx_carrier_losts += mib[MIB_TX_CLOST]; 1286 stats->tx_pause_frames += mib[MIB_TX_PAUSE]; 1287 /* Rx stat. */ 1288 stats->rx_good_octets += mib[MIB_RX_GOOD_O]; 1289 stats->rx_good_frames += mib[MIB_RX_GOOD_P]; 1290 stats->rx_octets += mib[MIB_RX_O]; 1291 stats->rx_frames += mib[MIB_RX_P]; 1292 stats->rx_bcast_frames += mib[MIB_RX_BCAST]; 1293 stats->rx_mcast_frames += mib[MIB_RX_MCAST]; 1294 stats->rx_pkts_64 += mib[MIB_RX_64]; 1295 stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; 1296 stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; 1297 stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; 1298 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; 1299 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; 1300 stats->rx_jabbers += mib[MIB_RX_JABBER]; 1301 stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; 1302 stats->rx_frag_frames += mib[MIB_RX_FRAG]; 1303 stats->rx_missed_frames += mib[MIB_RX_MISS]; 1304 stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; 1305 stats->rx_runts += mib[MIB_RX_USIZE]; 1306 stats->rx_crc_errs += mib[MIB_RX_CRC]; 1307 stats->rx_align_errs += mib[MIB_RX_ALIGN]; 1308 stats->rx_symbol_errs += mib[MIB_RX_SYM]; 1309 stats->rx_pause_frames += mib[MIB_RX_PAUSE]; 1310 stats->rx_control_frames += mib[MIB_RX_NPAUSE]; 1311 1312 /* Update counters in ifnet. */ 1313 ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P]; 1314 ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS]; 1315 ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] + 1316 (u_long)mib[MIB_TX_ECOLS] + 1317 (u_long)mib[MIB_TX_DEFERED] + 1318 (u_long)mib[MIB_TX_CLOST]; 1319 1320 ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P]; 1321 1322 ifp->if_ierrors += mib[MIB_RX_JABBER] + 1323 mib[MIB_RX_MISS] + 1324 mib[MIB_RX_CRCA] + 1325 mib[MIB_RX_USIZE] + 1326 mib[MIB_RX_CRC] + 1327 mib[MIB_RX_ALIGN] + 1328 mib[MIB_RX_SYM]; 1329 } 1330 1331 static void 1332 bfe_txeof(struct bfe_softc *sc) 1333 { 1334 struct bfe_tx_data *r; 1335 struct ifnet *ifp; 1336 int i, chipidx; 1337 1338 BFE_LOCK_ASSERT(sc); 1339 1340 ifp = sc->bfe_ifp; 1341 1342 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1343 chipidx /= sizeof(struct bfe_desc); 1344 1345 i = sc->bfe_tx_cons; 1346 if (i == chipidx) 1347 return; 1348 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1350 /* Go through the mbufs and free those that have been transmitted */ 1351 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1352 r = &sc->bfe_tx_ring[i]; 1353 sc->bfe_tx_cnt--; 1354 if (r->bfe_mbuf == NULL) 1355 continue; 1356 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1357 BUS_DMASYNC_POSTWRITE); 1358 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1359 1360 m_freem(r->bfe_mbuf); 1361 r->bfe_mbuf = NULL; 1362 } 1363 1364 if (i != sc->bfe_tx_cons) { 1365 /* we freed up some mbufs */ 1366 sc->bfe_tx_cons = i; 1367 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1368 } 1369 1370 if (sc->bfe_tx_cnt == 0) 1371 sc->bfe_watchdog_timer = 0; 1372 } 1373 1374 /* Pass a received packet up the stack */ 1375 static void 1376 bfe_rxeof(struct bfe_softc *sc) 1377 { 1378 struct mbuf *m; 1379 struct ifnet *ifp; 1380 struct bfe_rxheader *rxheader; 1381 struct bfe_rx_data *r; 1382 int cons, prog; 1383 u_int32_t status, current, len, flags; 1384 1385 BFE_LOCK_ASSERT(sc); 1386 cons = sc->bfe_rx_cons; 1387 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1388 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1389 1390 ifp = sc->bfe_ifp; 1391 1392 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1393 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1394 1395 for (prog = 0; current != cons; prog++, 1396 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1397 r = &sc->bfe_rx_ring[cons]; 1398 m = r->bfe_mbuf; 1399 /* 1400 * Rx status should be read from mbuf such that we can't 1401 * delay bus_dmamap_sync(9). This hardware limiation 1402 * results in inefficent mbuf usage as bfe(4) couldn't 1403 * reuse mapped buffer from errored frame. 1404 */ 1405 if (bfe_list_newbuf(sc, cons) != 0) { 1406 ifp->if_iqdrops++; 1407 bfe_discard_buf(sc, cons); 1408 continue; 1409 } 1410 rxheader = mtod(m, struct bfe_rxheader*); 1411 len = le16toh(rxheader->len); 1412 flags = le16toh(rxheader->flags); 1413 1414 /* Remove CRC bytes. */ 1415 len -= ETHER_CRC_LEN; 1416 1417 /* flag an error and try again */ 1418 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1419 m_freem(m); 1420 continue; 1421 } 1422 1423 /* Make sure to skip header bytes written by hardware. */ 1424 m_adj(m, BFE_RX_OFFSET); 1425 m->m_len = m->m_pkthdr.len = len; 1426 1427 m->m_pkthdr.rcvif = ifp; 1428 BFE_UNLOCK(sc); 1429 (*ifp->if_input)(ifp, m); 1430 BFE_LOCK(sc); 1431 } 1432 1433 if (prog > 0) { 1434 sc->bfe_rx_cons = cons; 1435 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1437 } 1438 } 1439 1440 static void 1441 bfe_intr(void *xsc) 1442 { 1443 struct bfe_softc *sc = xsc; 1444 struct ifnet *ifp; 1445 u_int32_t istat; 1446 1447 ifp = sc->bfe_ifp; 1448 1449 BFE_LOCK(sc); 1450 1451 istat = CSR_READ_4(sc, BFE_ISTAT); 1452 1453 /* 1454 * Defer unsolicited interrupts - This is necessary because setting the 1455 * chips interrupt mask register to 0 doesn't actually stop the 1456 * interrupts 1457 */ 1458 istat &= BFE_IMASK_DEF; 1459 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1460 CSR_READ_4(sc, BFE_ISTAT); 1461 1462 /* not expecting this interrupt, disregard it */ 1463 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1464 BFE_UNLOCK(sc); 1465 return; 1466 } 1467 1468 /* A packet was received */ 1469 if (istat & BFE_ISTAT_RX) 1470 bfe_rxeof(sc); 1471 1472 /* A packet was sent */ 1473 if (istat & BFE_ISTAT_TX) 1474 bfe_txeof(sc); 1475 1476 if (istat & BFE_ISTAT_ERRORS) { 1477 1478 if (istat & BFE_ISTAT_DSCE) { 1479 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1480 bfe_stop(sc); 1481 BFE_UNLOCK(sc); 1482 return; 1483 } 1484 1485 if (istat & BFE_ISTAT_DPE) { 1486 device_printf(sc->bfe_dev, 1487 "Descriptor Protocol Error\n"); 1488 bfe_stop(sc); 1489 BFE_UNLOCK(sc); 1490 return; 1491 } 1492 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1493 bfe_init_locked(sc); 1494 } 1495 1496 /* We have packets pending, fire them out */ 1497 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1498 bfe_start_locked(ifp); 1499 1500 BFE_UNLOCK(sc); 1501 } 1502 1503 static int 1504 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1505 { 1506 struct bfe_desc *d; 1507 struct bfe_tx_data *r, *r1; 1508 struct mbuf *m; 1509 bus_dmamap_t map; 1510 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1511 uint32_t cur, si; 1512 int error, i, nsegs; 1513 1514 BFE_LOCK_ASSERT(sc); 1515 1516 M_ASSERTPKTHDR((*m_head)); 1517 1518 si = cur = sc->bfe_tx_prod; 1519 r = &sc->bfe_tx_ring[cur]; 1520 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1521 txsegs, &nsegs, 0); 1522 if (error == EFBIG) { 1523 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); 1524 if (m == NULL) { 1525 m_freem(*m_head); 1526 *m_head = NULL; 1527 return (ENOMEM); 1528 } 1529 *m_head = m; 1530 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1531 *m_head, txsegs, &nsegs, 0); 1532 if (error != 0) { 1533 m_freem(*m_head); 1534 *m_head = NULL; 1535 return (error); 1536 } 1537 } else if (error != 0) 1538 return (error); 1539 if (nsegs == 0) { 1540 m_freem(*m_head); 1541 *m_head = NULL; 1542 return (EIO); 1543 } 1544 1545 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1546 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1547 return (ENOBUFS); 1548 } 1549 1550 for (i = 0; i < nsegs; i++) { 1551 d = &sc->bfe_tx_list[cur]; 1552 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1553 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1554 if (cur == BFE_TX_LIST_CNT - 1) 1555 /* 1556 * Tell the chip to wrap to the start of 1557 * the descriptor list. 1558 */ 1559 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1560 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1561 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1562 BFE_PCI_DMA); 1563 BFE_INC(cur, BFE_TX_LIST_CNT); 1564 } 1565 1566 /* Update producer index. */ 1567 sc->bfe_tx_prod = cur; 1568 1569 /* Set EOF on the last descriptor. */ 1570 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1571 d = &sc->bfe_tx_list[cur]; 1572 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1573 1574 /* Lastly set SOF on the first descriptor to avoid races. */ 1575 d = &sc->bfe_tx_list[si]; 1576 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1577 1578 r1 = &sc->bfe_tx_ring[cur]; 1579 map = r->bfe_map; 1580 r->bfe_map = r1->bfe_map; 1581 r1->bfe_map = map; 1582 r1->bfe_mbuf = *m_head; 1583 sc->bfe_tx_cnt += nsegs; 1584 1585 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1586 1587 return (0); 1588 } 1589 1590 /* 1591 * Set up to transmit a packet. 1592 */ 1593 static void 1594 bfe_start(struct ifnet *ifp) 1595 { 1596 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1597 bfe_start_locked(ifp); 1598 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1599 } 1600 1601 /* 1602 * Set up to transmit a packet. The softc is already locked. 1603 */ 1604 static void 1605 bfe_start_locked(struct ifnet *ifp) 1606 { 1607 struct bfe_softc *sc; 1608 struct mbuf *m_head; 1609 int queued; 1610 1611 sc = ifp->if_softc; 1612 1613 BFE_LOCK_ASSERT(sc); 1614 1615 /* 1616 * Not much point trying to send if the link is down 1617 * or we have nothing to send. 1618 */ 1619 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1620 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1621 return; 1622 1623 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1624 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1626 if (m_head == NULL) 1627 break; 1628 1629 /* 1630 * Pack the data into the tx ring. If we dont have 1631 * enough room, let the chip drain the ring. 1632 */ 1633 if (bfe_encap(sc, &m_head)) { 1634 if (m_head == NULL) 1635 break; 1636 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1637 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1638 break; 1639 } 1640 1641 queued++; 1642 1643 /* 1644 * If there's a BPF listener, bounce a copy of this frame 1645 * to him. 1646 */ 1647 BPF_MTAP(ifp, m_head); 1648 } 1649 1650 if (queued) { 1651 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1653 /* Transmit - twice due to apparent hardware bug */ 1654 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1655 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1656 /* 1657 * XXX It seems the following write is not necessary 1658 * to kick Tx command. What might be required would be 1659 * a way flushing PCI posted write. Reading the register 1660 * back ensures the flush operation. In addition, 1661 * hardware will execute PCI posted write in the long 1662 * run and watchdog timer for the kick command was set 1663 * to 5 seconds. Therefore I think the second write 1664 * access is not necessary or could be replaced with 1665 * read operation. 1666 */ 1667 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1668 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1669 1670 /* 1671 * Set a timeout in case the chip goes out to lunch. 1672 */ 1673 sc->bfe_watchdog_timer = 5; 1674 } 1675 } 1676 1677 static void 1678 bfe_init(void *xsc) 1679 { 1680 BFE_LOCK((struct bfe_softc *)xsc); 1681 bfe_init_locked(xsc); 1682 BFE_UNLOCK((struct bfe_softc *)xsc); 1683 } 1684 1685 static void 1686 bfe_init_locked(void *xsc) 1687 { 1688 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1689 struct ifnet *ifp = sc->bfe_ifp; 1690 struct mii_data *mii; 1691 1692 BFE_LOCK_ASSERT(sc); 1693 1694 mii = device_get_softc(sc->bfe_miibus); 1695 1696 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1697 return; 1698 1699 bfe_stop(sc); 1700 bfe_chip_reset(sc); 1701 1702 if (bfe_list_rx_init(sc) == ENOBUFS) { 1703 device_printf(sc->bfe_dev, 1704 "%s: Not enough memory for list buffers\n", __func__); 1705 bfe_stop(sc); 1706 return; 1707 } 1708 bfe_list_tx_init(sc); 1709 1710 bfe_set_rx_mode(sc); 1711 1712 /* Enable the chip and core */ 1713 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1714 /* Enable interrupts */ 1715 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1716 1717 /* Clear link state and change media. */ 1718 sc->bfe_flags &= ~BFE_FLAG_LINK; 1719 mii_mediachg(mii); 1720 1721 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1722 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1723 1724 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1725 } 1726 1727 /* 1728 * Set media options. 1729 */ 1730 static int 1731 bfe_ifmedia_upd(struct ifnet *ifp) 1732 { 1733 struct bfe_softc *sc; 1734 struct mii_data *mii; 1735 struct mii_softc *miisc; 1736 int error; 1737 1738 sc = ifp->if_softc; 1739 BFE_LOCK(sc); 1740 1741 mii = device_get_softc(sc->bfe_miibus); 1742 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1743 PHY_RESET(miisc); 1744 error = mii_mediachg(mii); 1745 BFE_UNLOCK(sc); 1746 1747 return (error); 1748 } 1749 1750 /* 1751 * Report current media status. 1752 */ 1753 static void 1754 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1755 { 1756 struct bfe_softc *sc = ifp->if_softc; 1757 struct mii_data *mii; 1758 1759 BFE_LOCK(sc); 1760 mii = device_get_softc(sc->bfe_miibus); 1761 mii_pollstat(mii); 1762 ifmr->ifm_active = mii->mii_media_active; 1763 ifmr->ifm_status = mii->mii_media_status; 1764 BFE_UNLOCK(sc); 1765 } 1766 1767 static int 1768 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1769 { 1770 struct bfe_softc *sc = ifp->if_softc; 1771 struct ifreq *ifr = (struct ifreq *) data; 1772 struct mii_data *mii; 1773 int error = 0; 1774 1775 switch (command) { 1776 case SIOCSIFFLAGS: 1777 BFE_LOCK(sc); 1778 if (ifp->if_flags & IFF_UP) { 1779 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1780 bfe_set_rx_mode(sc); 1781 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1782 bfe_init_locked(sc); 1783 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1784 bfe_stop(sc); 1785 BFE_UNLOCK(sc); 1786 break; 1787 case SIOCADDMULTI: 1788 case SIOCDELMULTI: 1789 BFE_LOCK(sc); 1790 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1791 bfe_set_rx_mode(sc); 1792 BFE_UNLOCK(sc); 1793 break; 1794 case SIOCGIFMEDIA: 1795 case SIOCSIFMEDIA: 1796 mii = device_get_softc(sc->bfe_miibus); 1797 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1798 break; 1799 default: 1800 error = ether_ioctl(ifp, command, data); 1801 break; 1802 } 1803 1804 return (error); 1805 } 1806 1807 static void 1808 bfe_watchdog(struct bfe_softc *sc) 1809 { 1810 struct ifnet *ifp; 1811 1812 BFE_LOCK_ASSERT(sc); 1813 1814 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1815 return; 1816 1817 ifp = sc->bfe_ifp; 1818 1819 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1820 1821 ifp->if_oerrors++; 1822 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1823 bfe_init_locked(sc); 1824 1825 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1826 bfe_start_locked(ifp); 1827 } 1828 1829 static void 1830 bfe_tick(void *xsc) 1831 { 1832 struct bfe_softc *sc = xsc; 1833 struct mii_data *mii; 1834 1835 BFE_LOCK_ASSERT(sc); 1836 1837 mii = device_get_softc(sc->bfe_miibus); 1838 mii_tick(mii); 1839 bfe_stats_update(sc); 1840 bfe_watchdog(sc); 1841 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1842 } 1843 1844 /* 1845 * Stop the adapter and free any mbufs allocated to the 1846 * RX and TX lists. 1847 */ 1848 static void 1849 bfe_stop(struct bfe_softc *sc) 1850 { 1851 struct ifnet *ifp; 1852 1853 BFE_LOCK_ASSERT(sc); 1854 1855 ifp = sc->bfe_ifp; 1856 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1857 sc->bfe_flags &= ~BFE_FLAG_LINK; 1858 callout_stop(&sc->bfe_stat_co); 1859 sc->bfe_watchdog_timer = 0; 1860 1861 bfe_chip_halt(sc); 1862 bfe_tx_ring_free(sc); 1863 bfe_rx_ring_free(sc); 1864 } 1865 1866 static int 1867 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS) 1868 { 1869 struct bfe_softc *sc; 1870 struct bfe_hw_stats *stats; 1871 int error, result; 1872 1873 result = -1; 1874 error = sysctl_handle_int(oidp, &result, 0, req); 1875 1876 if (error != 0 || req->newptr == NULL) 1877 return (error); 1878 1879 if (result != 1) 1880 return (error); 1881 1882 sc = (struct bfe_softc *)arg1; 1883 stats = &sc->bfe_stats; 1884 1885 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); 1886 printf("Transmit good octets : %ju\n", 1887 (uintmax_t)stats->tx_good_octets); 1888 printf("Transmit good frames : %ju\n", 1889 (uintmax_t)stats->tx_good_frames); 1890 printf("Transmit octets : %ju\n", 1891 (uintmax_t)stats->tx_octets); 1892 printf("Transmit frames : %ju\n", 1893 (uintmax_t)stats->tx_frames); 1894 printf("Transmit broadcast frames : %ju\n", 1895 (uintmax_t)stats->tx_bcast_frames); 1896 printf("Transmit multicast frames : %ju\n", 1897 (uintmax_t)stats->tx_mcast_frames); 1898 printf("Transmit frames 64 bytes : %ju\n", 1899 (uint64_t)stats->tx_pkts_64); 1900 printf("Transmit frames 65 to 127 bytes : %ju\n", 1901 (uint64_t)stats->tx_pkts_65_127); 1902 printf("Transmit frames 128 to 255 bytes : %ju\n", 1903 (uint64_t)stats->tx_pkts_128_255); 1904 printf("Transmit frames 256 to 511 bytes : %ju\n", 1905 (uint64_t)stats->tx_pkts_256_511); 1906 printf("Transmit frames 512 to 1023 bytes : %ju\n", 1907 (uint64_t)stats->tx_pkts_512_1023); 1908 printf("Transmit frames 1024 to max bytes : %ju\n", 1909 (uint64_t)stats->tx_pkts_1024_max); 1910 printf("Transmit jabber errors : %u\n", stats->tx_jabbers); 1911 printf("Transmit oversized frames : %ju\n", 1912 (uint64_t)stats->tx_oversize_frames); 1913 printf("Transmit fragmented frames : %ju\n", 1914 (uint64_t)stats->tx_frag_frames); 1915 printf("Transmit underruns : %u\n", stats->tx_colls); 1916 printf("Transmit total collisions : %u\n", stats->tx_single_colls); 1917 printf("Transmit single collisions : %u\n", stats->tx_single_colls); 1918 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); 1919 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); 1920 printf("Transmit late collisions : %u\n", stats->tx_late_colls); 1921 printf("Transmit deferrals : %u\n", stats->tx_deferrals); 1922 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); 1923 printf("Transmit pause frames : %u\n", stats->tx_pause_frames); 1924 1925 printf("Receive good octets : %ju\n", 1926 (uintmax_t)stats->rx_good_octets); 1927 printf("Receive good frames : %ju\n", 1928 (uintmax_t)stats->rx_good_frames); 1929 printf("Receive octets : %ju\n", 1930 (uintmax_t)stats->rx_octets); 1931 printf("Receive frames : %ju\n", 1932 (uintmax_t)stats->rx_frames); 1933 printf("Receive broadcast frames : %ju\n", 1934 (uintmax_t)stats->rx_bcast_frames); 1935 printf("Receive multicast frames : %ju\n", 1936 (uintmax_t)stats->rx_mcast_frames); 1937 printf("Receive frames 64 bytes : %ju\n", 1938 (uint64_t)stats->rx_pkts_64); 1939 printf("Receive frames 65 to 127 bytes : %ju\n", 1940 (uint64_t)stats->rx_pkts_65_127); 1941 printf("Receive frames 128 to 255 bytes : %ju\n", 1942 (uint64_t)stats->rx_pkts_128_255); 1943 printf("Receive frames 256 to 511 bytes : %ju\n", 1944 (uint64_t)stats->rx_pkts_256_511); 1945 printf("Receive frames 512 to 1023 bytes : %ju\n", 1946 (uint64_t)stats->rx_pkts_512_1023); 1947 printf("Receive frames 1024 to max bytes : %ju\n", 1948 (uint64_t)stats->rx_pkts_1024_max); 1949 printf("Receive jabber errors : %u\n", stats->rx_jabbers); 1950 printf("Receive oversized frames : %ju\n", 1951 (uint64_t)stats->rx_oversize_frames); 1952 printf("Receive fragmented frames : %ju\n", 1953 (uint64_t)stats->rx_frag_frames); 1954 printf("Receive missed frames : %u\n", stats->rx_missed_frames); 1955 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); 1956 printf("Receive undersized frames : %u\n", stats->rx_runts); 1957 printf("Receive CRC errors : %u\n", stats->rx_crc_errs); 1958 printf("Receive align errors : %u\n", stats->rx_align_errs); 1959 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); 1960 printf("Receive pause frames : %u\n", stats->rx_pause_frames); 1961 printf("Receive control frames : %u\n", stats->rx_control_frames); 1962 1963 return (error); 1964 } 1965