1 /*- 2 * Copyright (c) 2006 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written consent. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BCE_H_DEFINED 33 #define _BCE_H_DEFINED 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/endian.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <sys/queue.h> 50 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #include <net/bpf.h> 58 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in_systm.h> 63 #include <netinet/in.h> 64 #include <netinet/ip.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include "miidevs.h" 74 #include <dev/mii/brgphyreg.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include "miibus_if.h" 80 81 /****************************************************************************/ 82 /* Conversion to FreeBSD type definitions. */ 83 /****************************************************************************/ 84 #define u64 uint64_t 85 #define u32 uint32_t 86 #define u16 uint16_t 87 #define u8 uint8_t 88 89 #if BYTE_ORDER == BIG_ENDIAN 90 #define __BIG_ENDIAN 1 91 #undef __LITTLE_ENDIAN 92 #else 93 #undef __BIG_ENDIAN 94 #define __LITTLE_ENDIAN 1 95 #endif 96 97 /****************************************************************************/ 98 /* Debugging macros and definitions. */ 99 /****************************************************************************/ 100 #define BCE_CP_LOAD 0x00000001 101 #define BCE_CP_SEND 0x00000002 102 #define BCE_CP_RECV 0x00000004 103 #define BCE_CP_INTR 0x00000008 104 #define BCE_CP_UNLOAD 0x00000010 105 #define BCE_CP_RESET 0x00000020 106 #define BCE_CP_ALL 0x00FFFFFF 107 108 #define BCE_CP_MASK 0x00FFFFFF 109 110 #define BCE_LEVEL_FATAL 0x00000000 111 #define BCE_LEVEL_WARN 0x01000000 112 #define BCE_LEVEL_INFO 0x02000000 113 #define BCE_LEVEL_VERBOSE 0x03000000 114 #define BCE_LEVEL_EXCESSIVE 0x04000000 115 116 #define BCE_LEVEL_MASK 0xFF000000 117 118 #define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 119 #define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 120 #define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 121 #define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE) 122 123 #define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 124 #define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 125 #define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 126 #define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE) 127 128 #define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 129 #define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 130 #define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 131 #define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE) 132 133 #define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 134 #define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 135 #define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 136 #define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE) 137 138 #define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 139 #define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 140 #define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 141 #define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE) 142 143 #define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 144 #define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 145 #define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 146 #define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE) 147 148 #define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 149 #define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 150 #define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 151 #define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 152 #define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE) 153 154 #define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 155 #define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 156 #define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 157 158 #ifdef BCE_DEBUG 159 160 /* Print a message based on the logging level and code path. */ 161 #define DBPRINT(sc, level, format, args...) \ 162 if (BCE_LOG_MSG(level)) { \ 163 device_printf(sc->bce_dev, format, ## args); \ 164 } 165 166 /* Runs a particular command based on the logging level and code path. */ 167 #define DBRUN(m, args...) \ 168 if (BCE_LOG_MSG(m)) { \ 169 args; \ 170 } 171 172 /* Runs a particular command based on the logging level. */ 173 #define DBRUNLV(level, args...) \ 174 if (BCE_MSG_LEVEL(level)) { \ 175 args; \ 176 } 177 178 /* Runs a particular command based on the code path. */ 179 #define DBRUNCP(cp, args...) \ 180 if (BCE_CODE_PATH(cp)) { \ 181 args; \ 182 } 183 184 /* Runs a particular command based on a condition. */ 185 #define DBRUNIF(cond, args...) \ 186 if (cond) { \ 187 args; \ 188 } 189 190 /* Needed for random() function which is only used in debugging. */ 191 #include <sys/random.h> 192 193 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 194 #define DB_RANDOMFALSE(defects) (random() > defects) 195 #define DB_OR_RANDOMFALSE(defects) || (random() > defects) 196 #define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 197 198 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 199 #define DB_RANDOMTRUE(defects) (random() < defects) 200 #define DB_OR_RANDOMTRUE(defects) || (random() < defects) 201 #define DB_AND_RANDOMTRUE(defects) && (random() < defects) 202 203 #else 204 205 #define DBPRINT(level, format, args...) 206 #define DBRUN(m, args...) 207 #define DBRUNLV(level, args...) 208 #define DBRUNCP(cp, args...) 209 #define DBRUNIF(cond, args...) 210 #define DB_RANDOMFALSE(defects) 211 #define DB_OR_RANDOMFALSE(percent) 212 #define DB_AND_RANDOMFALSE(percent) 213 #define DB_RANDOMTRUE(defects) 214 #define DB_OR_RANDOMTRUE(percent) 215 #define DB_AND_RANDOMTRUE(percent) 216 217 #endif /* BCE_DEBUG */ 218 219 220 /****************************************************************************/ 221 /* Device identification definitions. */ 222 /****************************************************************************/ 223 #define BRCM_VENDORID 0x14E4 224 #define BRCM_DEVICEID_BCM5706 0x164A 225 #define BRCM_DEVICEID_BCM5706S 0x16AA 226 #define BRCM_DEVICEID_BCM5708 0x164C 227 #define BRCM_DEVICEID_BCM5708S 0x16AC 228 229 #define HP_VENDORID 0x103C 230 231 #define PCI_ANY_ID (u_int16_t) (~0U) 232 233 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 234 235 #define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 236 #define BCE_CHIP_NUM_5706 0x57060000 237 #define BCE_CHIP_NUM_5708 0x57080000 238 239 #define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 240 #define BCE_CHIP_REV_Ax 0x00000000 241 #define BCE_CHIP_REV_Bx 0x00001000 242 #define BCE_CHIP_REV_Cx 0x00002000 243 244 #define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 245 #define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 246 247 #define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 248 #define BCE_CHIP_ID_5706_A0 0x57060000 249 #define BCE_CHIP_ID_5706_A1 0x57060010 250 #define BCE_CHIP_ID_5706_A2 0x57060020 251 #define BCE_CHIP_ID_5708_A0 0x57080000 252 #define BCE_CHIP_ID_5708_B0 0x57081000 253 #define BCE_CHIP_ID_5708_B1 0x57081010 254 255 #define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 256 257 /* A serdes chip will have the first bit of the bond id set. */ 258 #define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 259 260 261 /* shorthand one */ 262 #define BCE_ASICREV(x) ((x) >> 28) 263 #define BCE_ASICREV_BCM5700 0x06 264 265 /* chip revisions */ 266 #define BCE_CHIPREV(x) ((x) >> 24) 267 #define BCE_CHIPREV_5700_AX 0x70 268 #define BCE_CHIPREV_5700_BX 0x71 269 #define BCE_CHIPREV_5700_CX 0x72 270 #define BCE_CHIPREV_5701_AX 0x00 271 272 struct bce_type { 273 u_int16_t bce_vid; 274 u_int16_t bce_did; 275 u_int16_t bce_svid; 276 u_int16_t bce_sdid; 277 char *bce_name; 278 }; 279 280 /****************************************************************************/ 281 /* Byte order conversions. */ 282 /****************************************************************************/ 283 #if __FreeBSD_version >= 500000 284 #define bce_htobe16(x) htobe16(x) 285 #define bce_htobe32(x) htobe32(x) 286 #define bce_htobe64(x) htobe64(x) 287 #define bce_htole16(x) htole16(x) 288 #define bce_htole32(x) htole32(x) 289 #define bce_htole64(x) htole64(x) 290 291 #define bce_be16toh(x) be16toh(x) 292 #define bce_be32toh(x) be32toh(x) 293 #define bce_be64toh(x) be64toh(x) 294 #define bce_le16toh(x) le16toh(x) 295 #define bce_le32toh(x) le32toh(x) 296 #define bce_le64toh(x) le64toh(x) 297 #else 298 #define bce_htobe16(x) (x) 299 #define bce_htobe32(x) (x) 300 #define bce_htobe64(x) (x) 301 #define bce_htole16(x) (x) 302 #define bce_htole32(x) (x) 303 #define bce_htole64(x) (x) 304 305 #define bce_be16toh(x) (x) 306 #define bce_be32toh(x) (x) 307 #define bce_be64toh(x) (x) 308 #define bce_le16toh(x) (x) 309 #define bce_le32toh(x) (x) 310 #define bce_le64toh(x) (x) 311 #endif 312 313 314 /****************************************************************************/ 315 /* NVRAM Access */ 316 /****************************************************************************/ 317 318 /* Buffered flash (Atmel: AT45DB011B) specific information */ 319 #define SEEPROM_PAGE_BITS 2 320 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 321 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 322 #define SEEPROM_PAGE_SIZE 4 323 #define SEEPROM_TOTAL_SIZE 65536 324 325 #define BUFFERED_FLASH_PAGE_BITS 9 326 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 327 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 328 #define BUFFERED_FLASH_PAGE_SIZE 264 329 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 330 331 #define SAIFUN_FLASH_PAGE_BITS 8 332 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 333 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 334 #define SAIFUN_FLASH_PAGE_SIZE 256 335 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 336 337 #define ST_MICRO_FLASH_PAGE_BITS 8 338 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 339 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 340 #define ST_MICRO_FLASH_PAGE_SIZE 256 341 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 342 343 #define NVRAM_TIMEOUT_COUNT 30000 344 #define BCE_FLASHDESC_MAX 64 345 346 #define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 347 BCE_NVM_CFG1_BUFFER_MODE | \ 348 BCE_NVM_CFG1_PROTECT_MODE | \ 349 BCE_NVM_CFG1_FLASH_SIZE) 350 351 #define FLASH_BACKUP_STRAP_MASK (0xf << 26) 352 353 struct flash_spec { 354 u32 strapping; 355 u32 config1; 356 u32 config2; 357 u32 config3; 358 u32 write1; 359 u32 buffered; 360 u32 page_bits; 361 u32 page_size; 362 u32 addr_mask; 363 u32 total_size; 364 u8 *name; 365 }; 366 367 368 /****************************************************************************/ 369 /* Shared Memory layout */ 370 /* The BCE bootcode will initialize this data area with port configurtion */ 371 /* information which can be accessed by the driver. */ 372 /****************************************************************************/ 373 374 /* 375 * This value (in milliseconds) determines the frequency of the driver 376 * issuing the PULSE message code. The firmware monitors this periodic 377 * pulse to determine when to switch to an OS-absent mode. 378 */ 379 #define DRV_PULSE_PERIOD_MS 250 380 381 /* 382 * This value (in milliseconds) determines how long the driver should 383 * wait for an acknowledgement from the firmware before timing out. Once 384 * the firmware has timed out, the driver will assume there is no firmware 385 * running and there won't be any firmware-driver synchronization during a 386 * driver reset. 387 */ 388 #define FW_ACK_TIME_OUT_MS 100 389 390 391 #define BCE_DRV_RESET_SIGNATURE 0x00000000 392 #define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 393 394 #define BCE_DRV_MB 0x00000004 395 #define BCE_DRV_MSG_CODE 0xff000000 396 #define BCE_DRV_MSG_CODE_RESET 0x01000000 397 #define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 398 #define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 399 #define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 400 #define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 401 #define BCE_DRV_MSG_CODE_PULSE 0x06000000 402 #define BCE_DRV_MSG_CODE_DIAG 0x07000000 403 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 404 405 #define BCE_DRV_MSG_DATA 0x00ff0000 406 #define BCE_DRV_MSG_DATA_WAIT0 0x00010000 407 #define BCE_DRV_MSG_DATA_WAIT1 0x00020000 408 #define BCE_DRV_MSG_DATA_WAIT2 0x00030000 409 #define BCE_DRV_MSG_DATA_WAIT3 0x00040000 410 411 #define BCE_DRV_MSG_SEQ 0x0000ffff 412 413 #define BCE_FW_MB 0x00000008 414 #define BCE_FW_MSG_ACK 0x0000ffff 415 #define BCE_FW_MSG_STATUS_MASK 0x00ff0000 416 #define BCE_FW_MSG_STATUS_OK 0x00000000 417 #define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 418 419 #define BCE_LINK_STATUS 0x0000000c 420 #define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 421 #define BCE_LINK_STATUS_LINK_UP 0x1 422 #define BCE_LINK_STATUS_LINK_DOWN 0x0 423 #define BCE_LINK_STATUS_SPEED_MASK 0x1e 424 #define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 425 #define BCE_LINK_STATUS_10HALF (1<<1) 426 #define BCE_LINK_STATUS_10FULL (2<<1) 427 #define BCE_LINK_STATUS_100HALF (3<<1) 428 #define BCE_LINK_STATUS_100BASE_T4 (4<<1) 429 #define BCE_LINK_STATUS_100FULL (5<<1) 430 #define BCE_LINK_STATUS_1000HALF (6<<1) 431 #define BCE_LINK_STATUS_1000FULL (7<<1) 432 #define BCE_LINK_STATUS_2500HALF (8<<1) 433 #define BCE_LINK_STATUS_2500FULL (9<<1) 434 #define BCE_LINK_STATUS_AN_ENABLED (1<<5) 435 #define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 436 #define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 437 #define BCE_LINK_STATUS_RESERVED (1<<8) 438 #define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 439 #define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 440 #define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 441 #define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 442 #define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 443 #define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 444 #define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 445 #define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 446 #define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 447 #define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 448 #define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 449 #define BCE_LINK_STATUS_SERDES_LINK (1<<20) 450 #define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 451 #define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 452 453 #define BCE_DRV_PULSE_MB 0x00000010 454 #define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 455 456 /* Indicate to the firmware not to go into the 457 * OS absent when it is not getting driver pulse. 458 * This is used for debugging. */ 459 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 460 461 #define BCE_DEV_INFO_SIGNATURE 0x00000020 462 #define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 463 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 464 #define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 465 #define BCE_DEV_INFO_SECONDARY_PORT 0x80 466 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 467 468 #define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 469 470 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 471 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 472 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 473 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 474 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 475 476 #define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 477 #define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 478 #define BCE_SHARED_HW_CFG_DESIGN_NIC 0 479 #define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 480 #define BCE_SHARED_HW_CFG_PHY_COPPER 0 481 #define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 482 #define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 483 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 484 #define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 485 #define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 486 #define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 487 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 488 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 489 490 #define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 491 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 492 493 #define BCE_DEV_INFO_BC_REV 0x0000004c 494 495 #define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 496 #define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 497 498 #define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 499 #define BCE_PORT_HW_CFG_CONFIG 0x00000058 500 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 501 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 502 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 503 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 504 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 505 506 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 507 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 508 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 509 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 510 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 511 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 512 513 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 514 515 #define BCE_DEV_INFO_FORMAT_REV 0x000000c4 516 #define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 517 #define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 518 519 #define BCE_SHARED_FEATURE 0x000000c8 520 #define BCE_SHARED_FEATURE_MASK 0xffffffff 521 522 #define BCE_PORT_FEATURE 0x000000d8 523 #define BCE_PORT2_FEATURE 0x00000014c 524 #define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 525 #define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 526 #define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 527 #define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 528 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 529 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 530 #define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 531 #define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 532 #define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 533 #define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 534 #define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 535 #define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 536 #define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 537 #define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 538 #define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 539 #define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 540 #define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 541 #define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 542 #define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 543 #define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 544 #define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 545 546 #define BCE_PORT_FEATURE_WOL 0xdc 547 #define BCE_PORT2_FEATURE_WOL 0x150 548 #define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 549 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 550 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 551 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 552 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 553 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 554 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 555 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 556 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 557 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 558 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 559 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 560 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 561 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 562 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 563 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 564 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 565 566 #define BCE_PORT_FEATURE_MBA 0xe0 567 #define BCE_PORT2_FEATURE_MBA 0x154 568 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 569 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 570 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 571 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 572 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 573 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 574 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 575 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 576 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 577 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 578 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 579 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 580 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 581 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 582 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 583 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 584 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 585 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 586 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 587 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 588 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 589 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 590 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 591 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 592 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 593 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 594 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 595 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 596 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 597 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 598 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 599 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 600 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 601 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 602 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 603 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 604 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 605 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 606 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 607 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 608 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 609 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 610 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 611 612 #define BCE_PORT_FEATURE_IMD 0xe4 613 #define BCE_PORT2_FEATURE_IMD 0x158 614 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 615 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 616 617 #define BCE_PORT_FEATURE_VLAN 0xe8 618 #define BCE_PORT2_FEATURE_VLAN 0x15c 619 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 620 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 621 622 #define BCE_BC_STATE_RESET_TYPE 0x000001c0 623 #define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 624 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 625 #define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ 626 0x00010000) 627 #define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ 628 0x00020000) 629 #define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ 630 0x00030000) 631 #define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 632 #define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ 633 DRV_MSG_CODE_RESET) 634 #define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ 635 DRV_MSG_CODE_UNLOAD) 636 #define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ 637 DRV_MSG_CODE_SHUTDOWN) 638 #define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ 639 DRV_MSG_CODE_WOL) 640 #define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ 641 DRV_MSG_CODE_DIAG) 642 #define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ 643 (msg)) 644 645 #define BCE_BC_STATE 0x000001c4 646 #define BCE_BC_STATE_ERR_MASK 0x0000ff00 647 #define BCE_BC_STATE_SIGN 0x42530000 648 #define BCE_BC_STATE_SIGN_MASK 0xffff0000 649 #define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 650 #define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 651 #define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 652 #define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 653 #define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 654 #define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 655 #define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 656 #define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 657 #define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 658 #define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 659 #define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 660 #define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 661 #define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 662 #define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 663 #define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 664 #define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 665 #define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 666 #define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 667 #define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 668 #define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 669 #define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 670 #define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 671 #define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 672 #define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 673 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 674 675 #define BCE_BC_STATE_DEBUG_CMD 0x1dc 676 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 677 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 678 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 679 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 680 681 #define HOST_VIEW_SHMEM_BASE 0x167c00 682 683 /* 684 * PCI registers defined in the PCI 2.2 spec. 685 */ 686 #define BCE_PCI_PCIX_CMD 0x42 687 688 689 /****************************************************************************/ 690 /* Convenience definitions. */ 691 /****************************************************************************/ 692 #define BCE_PRINTF(sc, fmt, args...) device_printf(sc->bce_dev, fmt, ##args) 693 694 #define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 695 #define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 696 #define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 697 #define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 698 #define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 699 700 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) 701 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) 702 #define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) 703 #define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 704 #define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 705 #define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val) 706 #define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 707 #define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 708 #define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 709 #define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 710 711 #define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 712 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 713 #define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 714 #define BCE_ADDR_HI(y) ((u64) (y) >> 32) 715 #else 716 #define BCE_ADDR_LO(y) ((u32)y) 717 #define BCE_ADDR_HI(y) (0) 718 #endif 719 720 721 /* 722 * The following data structures are generated from RTL code. 723 * Do not modify any values below this line. 724 */ 725 726 /****************************************************************************/ 727 /* Do not modify any of the following data structures, they are generated */ 728 /* from RTL code. */ 729 /* */ 730 /* Begin machine generated definitions. */ 731 /****************************************************************************/ 732 733 /* 734 * tx_bd definition 735 */ 736 struct tx_bd { 737 u32 tx_bd_haddr_hi; 738 u32 tx_bd_haddr_lo; 739 u32 tx_bd_mss_nbytes; 740 u32 tx_bd_vlan_tag_flags; 741 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 742 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 743 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 744 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 745 #define TX_BD_FLAGS_COAL_NOW (1<<4) 746 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 747 #define TX_BD_FLAGS_END (1<<6) 748 #define TX_BD_FLAGS_START (1<<7) 749 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 750 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 751 #define TX_BD_FLAGS_SW_SNAP (1<<14) 752 #define TX_BD_FLAGS_SW_LSO (1<<15) 753 754 }; 755 756 757 /* 758 * rx_bd definition 759 */ 760 struct rx_bd { 761 u32 rx_bd_haddr_hi; 762 u32 rx_bd_haddr_lo; 763 u32 rx_bd_len; 764 u32 rx_bd_flags; 765 #define RX_BD_FLAGS_NOPUSH (1<<0) 766 #define RX_BD_FLAGS_DUMMY (1<<1) 767 #define RX_BD_FLAGS_END (1<<2) 768 #define RX_BD_FLAGS_START (1<<3) 769 770 }; 771 772 773 /* 774 * status_block definition 775 */ 776 struct status_block { 777 u32 status_attn_bits; 778 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 779 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 780 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 781 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 782 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 783 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 784 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 785 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 786 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 787 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 788 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 789 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 790 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 791 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 792 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 793 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 794 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 795 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 796 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 797 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 798 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 799 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 800 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 801 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 802 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 803 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 804 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 805 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 806 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 807 808 u32 status_attn_bits_ack; 809 #if defined(__BIG_ENDIAN) 810 u16 status_tx_quick_consumer_index0; 811 u16 status_tx_quick_consumer_index1; 812 u16 status_tx_quick_consumer_index2; 813 u16 status_tx_quick_consumer_index3; 814 u16 status_rx_quick_consumer_index0; 815 u16 status_rx_quick_consumer_index1; 816 u16 status_rx_quick_consumer_index2; 817 u16 status_rx_quick_consumer_index3; 818 u16 status_rx_quick_consumer_index4; 819 u16 status_rx_quick_consumer_index5; 820 u16 status_rx_quick_consumer_index6; 821 u16 status_rx_quick_consumer_index7; 822 u16 status_rx_quick_consumer_index8; 823 u16 status_rx_quick_consumer_index9; 824 u16 status_rx_quick_consumer_index10; 825 u16 status_rx_quick_consumer_index11; 826 u16 status_rx_quick_consumer_index12; 827 u16 status_rx_quick_consumer_index13; 828 u16 status_rx_quick_consumer_index14; 829 u16 status_rx_quick_consumer_index15; 830 u16 status_completion_producer_index; 831 u16 status_cmd_consumer_index; 832 u16 status_idx; 833 u16 status_unused; 834 #elif defined(__LITTLE_ENDIAN) 835 u16 status_tx_quick_consumer_index1; 836 u16 status_tx_quick_consumer_index0; 837 u16 status_tx_quick_consumer_index3; 838 u16 status_tx_quick_consumer_index2; 839 u16 status_rx_quick_consumer_index1; 840 u16 status_rx_quick_consumer_index0; 841 u16 status_rx_quick_consumer_index3; 842 u16 status_rx_quick_consumer_index2; 843 u16 status_rx_quick_consumer_index5; 844 u16 status_rx_quick_consumer_index4; 845 u16 status_rx_quick_consumer_index7; 846 u16 status_rx_quick_consumer_index6; 847 u16 status_rx_quick_consumer_index9; 848 u16 status_rx_quick_consumer_index8; 849 u16 status_rx_quick_consumer_index11; 850 u16 status_rx_quick_consumer_index10; 851 u16 status_rx_quick_consumer_index13; 852 u16 status_rx_quick_consumer_index12; 853 u16 status_rx_quick_consumer_index15; 854 u16 status_rx_quick_consumer_index14; 855 u16 status_cmd_consumer_index; 856 u16 status_completion_producer_index; 857 u16 status_unused; 858 u16 status_idx; 859 #endif 860 }; 861 862 863 /* 864 * statistics_block definition 865 */ 866 struct statistics_block { 867 u32 stat_IfHCInOctets_hi; 868 u32 stat_IfHCInOctets_lo; 869 u32 stat_IfHCInBadOctets_hi; 870 u32 stat_IfHCInBadOctets_lo; 871 u32 stat_IfHCOutOctets_hi; 872 u32 stat_IfHCOutOctets_lo; 873 u32 stat_IfHCOutBadOctets_hi; 874 u32 stat_IfHCOutBadOctets_lo; 875 u32 stat_IfHCInUcastPkts_hi; 876 u32 stat_IfHCInUcastPkts_lo; 877 u32 stat_IfHCInMulticastPkts_hi; 878 u32 stat_IfHCInMulticastPkts_lo; 879 u32 stat_IfHCInBroadcastPkts_hi; 880 u32 stat_IfHCInBroadcastPkts_lo; 881 u32 stat_IfHCOutUcastPkts_hi; 882 u32 stat_IfHCOutUcastPkts_lo; 883 u32 stat_IfHCOutMulticastPkts_hi; 884 u32 stat_IfHCOutMulticastPkts_lo; 885 u32 stat_IfHCOutBroadcastPkts_hi; 886 u32 stat_IfHCOutBroadcastPkts_lo; 887 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 888 u32 stat_Dot3StatsCarrierSenseErrors; 889 u32 stat_Dot3StatsFCSErrors; 890 u32 stat_Dot3StatsAlignmentErrors; 891 u32 stat_Dot3StatsSingleCollisionFrames; 892 u32 stat_Dot3StatsMultipleCollisionFrames; 893 u32 stat_Dot3StatsDeferredTransmissions; 894 u32 stat_Dot3StatsExcessiveCollisions; 895 u32 stat_Dot3StatsLateCollisions; 896 u32 stat_EtherStatsCollisions; 897 u32 stat_EtherStatsFragments; 898 u32 stat_EtherStatsJabbers; 899 u32 stat_EtherStatsUndersizePkts; 900 u32 stat_EtherStatsOverrsizePkts; 901 u32 stat_EtherStatsPktsRx64Octets; 902 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 903 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 904 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 905 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 906 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 907 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 908 u32 stat_EtherStatsPktsTx64Octets; 909 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 910 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 911 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 912 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 913 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 914 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 915 u32 stat_XonPauseFramesReceived; 916 u32 stat_XoffPauseFramesReceived; 917 u32 stat_OutXonSent; 918 u32 stat_OutXoffSent; 919 u32 stat_FlowControlDone; 920 u32 stat_MacControlFramesReceived; 921 u32 stat_XoffStateEntered; 922 u32 stat_IfInFramesL2FilterDiscards; 923 u32 stat_IfInRuleCheckerDiscards; 924 u32 stat_IfInFTQDiscards; 925 u32 stat_IfInMBUFDiscards; 926 u32 stat_IfInRuleCheckerP4Hit; 927 u32 stat_CatchupInRuleCheckerDiscards; 928 u32 stat_CatchupInFTQDiscards; 929 u32 stat_CatchupInMBUFDiscards; 930 u32 stat_CatchupInRuleCheckerP4Hit; 931 u32 stat_GenStat00; 932 u32 stat_GenStat01; 933 u32 stat_GenStat02; 934 u32 stat_GenStat03; 935 u32 stat_GenStat04; 936 u32 stat_GenStat05; 937 u32 stat_GenStat06; 938 u32 stat_GenStat07; 939 u32 stat_GenStat08; 940 u32 stat_GenStat09; 941 u32 stat_GenStat10; 942 u32 stat_GenStat11; 943 u32 stat_GenStat12; 944 u32 stat_GenStat13; 945 u32 stat_GenStat14; 946 u32 stat_GenStat15; 947 }; 948 949 950 /* 951 * l2_fhdr definition 952 */ 953 struct l2_fhdr { 954 u32 l2_fhdr_status; 955 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 956 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 957 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 958 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 959 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 960 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 961 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 962 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 963 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 964 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 965 966 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 967 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 968 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 969 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 970 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 971 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 972 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 973 974 u32 l2_fhdr_hash; 975 #if defined(__BIG_ENDIAN) 976 u16 l2_fhdr_pkt_len; 977 u16 l2_fhdr_vlan_tag; 978 u16 l2_fhdr_ip_xsum; 979 u16 l2_fhdr_tcp_udp_xsum; 980 #elif defined(__LITTLE_ENDIAN) 981 u16 l2_fhdr_vlan_tag; 982 u16 l2_fhdr_pkt_len; 983 u16 l2_fhdr_tcp_udp_xsum; 984 u16 l2_fhdr_ip_xsum; 985 #endif 986 }; 987 988 989 /* 990 * l2_context definition 991 */ 992 #define BCE_L2CTX_TYPE 0x00000000 993 #define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 994 #define BCE_L2CTX_TYPE_TYPE (0xf<<28) 995 #define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28) 996 #define BCE_L2CTX_TYPE_TYPE_L2 (1<<28) 997 998 #define BCE_L2CTX_TX_HOST_BIDX 0x00000088 999 #define BCE_L2CTX_EST_NBD 0x00000088 1000 #define BCE_L2CTX_CMD_TYPE 0x00000088 1001 #define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24) 1002 #define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 1003 #define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 1004 1005 #define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1006 #define BCE_L2CTX_TSCH_BSEQ 0x00000094 1007 #define BCE_L2CTX_TBDR_BSEQ 0x00000098 1008 #define BCE_L2CTX_TBDR_BOFF 0x0000009c 1009 #define BCE_L2CTX_TBDR_BIDX 0x0000009c 1010 #define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0 1011 #define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4 1012 #define BCE_L2CTX_TXP_BOFF 0x000000a8 1013 #define BCE_L2CTX_TXP_BIDX 0x000000a8 1014 #define BCE_L2CTX_TXP_BSEQ 0x000000ac 1015 1016 1017 /* 1018 * l2_bd_chain_context definition 1019 */ 1020 #define BCE_L2CTX_BD_PRE_READ 0x00000000 1021 #define BCE_L2CTX_CTX_SIZE 0x00000000 1022 #define BCE_L2CTX_CTX_TYPE 0x00000000 1023 #define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1024 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1025 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1026 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1027 1028 #define BCE_L2CTX_HOST_BDIDX 0x00000004 1029 #define BCE_L2CTX_HOST_BSEQ 0x00000008 1030 #define BCE_L2CTX_NX_BSEQ 0x0000000c 1031 #define BCE_L2CTX_NX_BDHADDR_HI 0x00000010 1032 #define BCE_L2CTX_NX_BDHADDR_LO 0x00000014 1033 #define BCE_L2CTX_NX_BDIDX 0x00000018 1034 1035 1036 /* 1037 * pci_config_l definition 1038 * offset: 0000 1039 */ 1040 #define BCE_PCICFG_MISC_CONFIG 0x00000068 1041 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1042 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1043 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1044 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1045 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1046 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1047 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1048 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1049 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1050 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1051 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1052 1053 #define BCE_PCICFG_MISC_STATUS 0x0000006c 1054 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1055 #define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1056 #define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1057 #define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1058 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1059 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1060 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1061 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1062 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1063 1064 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1065 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1066 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1067 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1068 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1069 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1070 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1071 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1072 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1073 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1074 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1075 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1076 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1077 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1078 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1079 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1080 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1081 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1082 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1083 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1084 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1085 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1086 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1087 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1088 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1089 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1090 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1091 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1092 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1093 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1094 1095 #define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1096 #define BCE_PCICFG_REG_WINDOW 0x00000080 1097 #define BCE_PCICFG_INT_ACK_CMD 0x00000084 1098 #define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1099 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1100 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1101 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1102 1103 #define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1104 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1105 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1106 #define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1107 1108 1109 /* 1110 * pci_reg definition 1111 * offset: 0x400 1112 */ 1113 #define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1114 #define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1115 1116 #define BCE_PCI_CONFIG_1 0x00000404 1117 #define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1118 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1119 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1120 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1121 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1122 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1123 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1124 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1125 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1126 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1127 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1128 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1129 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1130 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1131 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1132 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1133 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1134 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1135 1136 #define BCE_PCI_CONFIG_2 0x00000408 1137 #define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1138 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1139 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1140 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1141 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1142 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1143 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1144 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1145 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1146 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1147 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1148 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1149 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1150 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1151 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1152 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1153 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1154 #define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1155 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1156 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1157 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1158 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1159 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1160 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1161 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1162 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1163 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1164 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1165 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1166 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1167 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1168 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1169 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1170 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1171 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1172 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1173 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1174 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1175 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1176 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1177 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1178 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1179 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1180 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1181 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1182 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1183 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1184 1185 #define BCE_PCI_CONFIG_3 0x0000040c 1186 #define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1187 #define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1188 #define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1189 #define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1190 #define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1191 #define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1192 #define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1193 1194 #define BCE_PCI_PM_DATA_A 0x00000410 1195 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1196 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1197 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1198 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1199 1200 #define BCE_PCI_PM_DATA_B 0x00000414 1201 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1202 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1203 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1204 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1205 1206 #define BCE_PCI_SWAP_DIAG0 0x00000418 1207 #define BCE_PCI_SWAP_DIAG1 0x0000041c 1208 #define BCE_PCI_EXP_ROM_ADDR 0x00000420 1209 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1210 #define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1211 1212 #define BCE_PCI_EXP_ROM_DATA 0x00000424 1213 #define BCE_PCI_VPD_INTF 0x00000428 1214 #define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1215 1216 #define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1217 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1218 #define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1219 1220 #define BCE_PCI_VPD_DATA 0x00000430 1221 #define BCE_PCI_ID_VAL1 0x00000434 1222 #define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1223 #define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1224 1225 #define BCE_PCI_ID_VAL2 0x00000438 1226 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1227 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1228 1229 #define BCE_PCI_ID_VAL3 0x0000043c 1230 #define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1231 #define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1232 1233 #define BCE_PCI_ID_VAL4 0x00000440 1234 #define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1235 #define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1236 #define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1237 #define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1238 #define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1239 #define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1240 #define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1241 #define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1242 #define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1243 #define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1244 #define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1245 #define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1246 #define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1247 #define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1248 #define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1249 #define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1250 #define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1251 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1252 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1253 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1254 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1255 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1256 #define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1257 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1258 #define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1259 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1260 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1261 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1262 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1263 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1264 1265 #define BCE_PCI_ID_VAL5 0x00000444 1266 #define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1267 #define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1268 #define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1269 #define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1270 #define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1271 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1272 1273 #define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1274 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1275 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1276 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1277 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1278 1279 #define BCE_PCI_ID_VAL6 0x0000044c 1280 #define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1281 #define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1282 #define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1283 1284 #define BCE_PCI_MSI_DATA 0x00000450 1285 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1286 1287 #define BCE_PCI_MSI_ADDR_H 0x00000454 1288 #define BCE_PCI_MSI_ADDR_L 0x00000458 1289 1290 1291 /* 1292 * misc_reg definition 1293 * offset: 0x800 1294 */ 1295 #define BCE_MISC_COMMAND 0x00000800 1296 #define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1297 #define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1298 #define BCE_MISC_COMMAND_CORE_RESET (1L<<4) 1299 #define BCE_MISC_COMMAND_HARD_RESET (1L<<5) 1300 #define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1301 #define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1302 1303 #define BCE_MISC_CFG 0x00000804 1304 #define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1305 #define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1306 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1307 #define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1308 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1309 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1310 #define BCE_MISC_CFG_BIST_EN (1L<<3) 1311 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1312 #define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5) 1313 #define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6) 1314 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1315 #define BCE_MISC_CFG_LEDMODE (0x3L<<8) 1316 #define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1317 #define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1318 #define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1319 1320 #define BCE_MISC_ID 0x00000808 1321 #define BCE_MISC_ID_BOND_ID (0xfL<<0) 1322 #define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1323 #define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1324 #define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1325 1326 #define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1327 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1328 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1329 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1330 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1331 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1332 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1333 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1334 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1335 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1336 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1337 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1338 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1339 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1340 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1341 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1342 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1343 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1344 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1345 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1346 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1347 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1348 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1349 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1350 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1351 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1352 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1353 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1354 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1355 1356 #define BCE_MISC_ENABLE_SET_BITS 0x00000810 1357 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1358 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1359 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1360 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1361 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1362 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1363 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1364 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1365 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1366 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1367 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1368 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1369 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1370 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1371 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1372 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1373 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1374 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1375 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1376 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1377 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1378 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1379 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1380 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1381 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1382 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1383 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1384 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1385 1386 #define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1387 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1388 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1389 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1390 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1391 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1392 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1393 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1394 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1395 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1396 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1397 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1398 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1399 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1400 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1401 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1402 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1403 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1404 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1405 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1406 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1407 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1408 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1409 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1410 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1411 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1412 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1413 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1414 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1415 1416 #define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1417 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1418 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1419 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1420 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1421 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1422 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1423 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1424 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1425 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1426 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1427 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1428 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1429 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1430 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1431 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1432 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1433 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1434 #define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1435 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1436 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1437 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1438 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1439 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1440 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1441 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1442 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1443 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1444 #define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1445 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1446 1447 #define BCE_MISC_GPIO 0x0000081c 1448 #define BCE_MISC_GPIO_VALUE (0xffL<<0) 1449 #define BCE_MISC_GPIO_SET (0xffL<<8) 1450 #define BCE_MISC_GPIO_CLR (0xffL<<16) 1451 #define BCE_MISC_GPIO_FLOAT (0xffL<<24) 1452 1453 #define BCE_MISC_GPIO_INT 0x00000820 1454 #define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1455 #define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1456 #define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1457 #define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1458 1459 #define BCE_MISC_CONFIG_LFSR 0x00000824 1460 #define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1461 1462 #define BCE_MISC_LFSR_MASK_BITS 0x00000828 1463 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1464 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1465 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1466 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1467 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1468 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1469 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1470 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1471 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1472 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1473 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1474 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1475 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1476 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1477 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1478 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1479 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1480 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1481 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1482 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1483 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1484 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1485 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1486 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1487 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1488 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1489 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1490 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1491 1492 #define BCE_MISC_ARB_REQ0 0x0000082c 1493 #define BCE_MISC_ARB_REQ1 0x00000830 1494 #define BCE_MISC_ARB_REQ2 0x00000834 1495 #define BCE_MISC_ARB_REQ3 0x00000838 1496 #define BCE_MISC_ARB_REQ4 0x0000083c 1497 #define BCE_MISC_ARB_FREE0 0x00000840 1498 #define BCE_MISC_ARB_FREE1 0x00000844 1499 #define BCE_MISC_ARB_FREE2 0x00000848 1500 #define BCE_MISC_ARB_FREE3 0x0000084c 1501 #define BCE_MISC_ARB_FREE4 0x00000850 1502 #define BCE_MISC_ARB_REQ_STATUS0 0x00000854 1503 #define BCE_MISC_ARB_REQ_STATUS1 0x00000858 1504 #define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 1505 #define BCE_MISC_ARB_REQ_STATUS3 0x00000860 1506 #define BCE_MISC_ARB_REQ_STATUS4 0x00000864 1507 #define BCE_MISC_ARB_GNT0 0x00000868 1508 #define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 1509 #define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 1510 #define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 1511 #define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 1512 #define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 1513 #define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 1514 #define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 1515 #define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 1516 1517 #define BCE_MISC_ARB_GNT1 0x0000086c 1518 #define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 1519 #define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 1520 #define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 1521 #define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 1522 #define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 1523 #define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 1524 #define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 1525 #define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 1526 1527 #define BCE_MISC_ARB_GNT2 0x00000870 1528 #define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 1529 #define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 1530 #define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 1531 #define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 1532 #define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 1533 #define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 1534 #define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 1535 #define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 1536 1537 #define BCE_MISC_ARB_GNT3 0x00000874 1538 #define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 1539 #define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 1540 #define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 1541 #define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 1542 #define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 1543 #define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 1544 #define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 1545 #define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 1546 1547 #define BCE_MISC_PRBS_CONTROL 0x00000878 1548 #define BCE_MISC_PRBS_CONTROL_EN (1L<<0) 1549 #define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1) 1550 #define BCE_MISC_PRBS_CONTROL_INV (1L<<2) 1551 #define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1552 #define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1553 #define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1554 #define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1555 #define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1556 #define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1557 1558 #define BCE_MISC_PRBS_STATUS 0x0000087c 1559 #define BCE_MISC_PRBS_STATUS_LOCK (1L<<0) 1560 #define BCE_MISC_PRBS_STATUS_STKY (1L<<1) 1561 #define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1562 #define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16) 1563 1564 #define BCE_MISC_SM_ASF_CONTROL 0x00000880 1565 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1566 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1567 #define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1568 #define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1569 #define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1570 #define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1571 #define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1572 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1573 #define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1574 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1575 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1576 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1577 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1578 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1579 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1580 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1581 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1582 1583 #define BCE_MISC_SMB_IN 0x00000884 1584 #define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 1585 #define BCE_MISC_SMB_IN_RDY (1L<<8) 1586 #define BCE_MISC_SMB_IN_DONE (1L<<9) 1587 #define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1588 #define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 1589 #define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1590 #define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1591 #define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1592 #define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1593 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1594 1595 #define BCE_MISC_SMB_OUT 0x00000888 1596 #define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1597 #define BCE_MISC_SMB_OUT_RDY (1L<<8) 1598 #define BCE_MISC_SMB_OUT_START (1L<<9) 1599 #define BCE_MISC_SMB_OUT_LAST (1L<<10) 1600 #define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1601 #define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 1602 #define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1603 #define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1604 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1605 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1606 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1607 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1608 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1609 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1610 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1611 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1612 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1613 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1614 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1615 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1616 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1617 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1618 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1619 1620 #define BCE_MISC_SMB_WATCHDOG 0x0000088c 1621 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1622 1623 #define BCE_MISC_SMB_HEARTBEAT 0x00000890 1624 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1625 1626 #define BCE_MISC_SMB_POLL_ASF 0x00000894 1627 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1628 1629 #define BCE_MISC_SMB_POLL_LEGACY 0x00000898 1630 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1631 1632 #define BCE_MISC_SMB_RETRAN 0x0000089c 1633 #define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1634 1635 #define BCE_MISC_SMB_TIMESTAMP 0x000008a0 1636 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1637 1638 #define BCE_MISC_PERR_ENA0 0x000008a4 1639 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1640 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1641 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1642 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1643 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1644 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1645 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1646 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1647 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1648 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1649 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1650 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1651 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1652 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1653 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1654 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1655 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1656 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1657 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1658 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1659 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1660 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1661 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1662 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1663 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1664 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1665 #define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1666 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1667 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1668 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1669 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1670 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1671 1672 #define BCE_MISC_PERR_ENA1 0x000008a8 1673 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1674 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1675 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1676 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1677 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1678 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1679 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1680 #define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1681 #define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1682 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1683 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1684 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1685 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1686 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1687 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1688 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1689 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1690 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1691 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1692 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1693 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1694 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1695 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1696 #define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1697 #define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1698 #define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1699 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1700 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1701 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1702 #define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1703 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1704 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1705 1706 #define BCE_MISC_PERR_ENA2 0x000008ac 1707 #define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1708 #define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1709 #define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1710 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1711 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1712 #define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1713 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1714 #define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1715 #define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1716 1717 #define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 1718 #define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1719 #define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1720 1721 #define BCE_MISC_VREG_CONTROL 0x000008b4 1722 #define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1723 #define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1724 1725 #define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1726 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1727 1728 #define BCE_MISC_UNUSED0 0x000008bc 1729 1730 1731 /* 1732 * nvm_reg definition 1733 * offset: 0x6400 1734 */ 1735 #define BCE_NVM_COMMAND 0x00006400 1736 #define BCE_NVM_COMMAND_RST (1L<<0) 1737 #define BCE_NVM_COMMAND_DONE (1L<<3) 1738 #define BCE_NVM_COMMAND_DOIT (1L<<4) 1739 #define BCE_NVM_COMMAND_WR (1L<<5) 1740 #define BCE_NVM_COMMAND_ERASE (1L<<6) 1741 #define BCE_NVM_COMMAND_FIRST (1L<<7) 1742 #define BCE_NVM_COMMAND_LAST (1L<<8) 1743 #define BCE_NVM_COMMAND_WREN (1L<<16) 1744 #define BCE_NVM_COMMAND_WRDI (1L<<17) 1745 #define BCE_NVM_COMMAND_EWSR (1L<<18) 1746 #define BCE_NVM_COMMAND_WRSR (1L<<19) 1747 1748 #define BCE_NVM_STATUS 0x00006404 1749 #define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1750 #define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1751 #define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1752 1753 #define BCE_NVM_WRITE 0x00006408 1754 #define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1755 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1756 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1757 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1758 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1759 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1760 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1761 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1762 1763 #define BCE_NVM_ADDR 0x0000640c 1764 #define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1765 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1766 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1767 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1768 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1769 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1770 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1771 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1772 1773 #define BCE_NVM_READ 0x00006410 1774 #define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1775 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1776 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1777 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1778 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1779 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1780 #define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1781 #define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1782 1783 #define BCE_NVM_CFG1 0x00006414 1784 #define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 1785 #define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 1786 #define BCE_NVM_CFG1_PASS_MODE (1L<<2) 1787 #define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 1788 #define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 1789 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1790 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1791 #define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1792 #define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1793 #define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 1794 #define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 1795 #define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1796 1797 #define BCE_NVM_CFG2 0x00006418 1798 #define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 1799 #define BCE_NVM_CFG2_DUMMY (0xffL<<8) 1800 #define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 1801 1802 #define BCE_NVM_CFG3 0x0000641c 1803 #define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1804 #define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 1805 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1806 #define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 1807 1808 #define BCE_NVM_SW_ARB 0x00006420 1809 #define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1810 #define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1811 #define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1812 #define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1813 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1814 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1815 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1816 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1817 #define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1818 #define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1819 #define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1820 #define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1821 #define BCE_NVM_SW_ARB_REQ0 (1L<<12) 1822 #define BCE_NVM_SW_ARB_REQ1 (1L<<13) 1823 #define BCE_NVM_SW_ARB_REQ2 (1L<<14) 1824 #define BCE_NVM_SW_ARB_REQ3 (1L<<15) 1825 1826 #define BCE_NVM_ACCESS_ENABLE 0x00006424 1827 #define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 1828 #define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1829 1830 #define BCE_NVM_WRITE1 0x00006428 1831 #define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 1832 #define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1833 #define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 1834 1835 1836 1837 /* 1838 * dma_reg definition 1839 * offset: 0xc00 1840 */ 1841 #define BCE_DMA_COMMAND 0x00000c00 1842 #define BCE_DMA_COMMAND_ENABLE (1L<<0) 1843 1844 #define BCE_DMA_STATUS 0x00000c04 1845 #define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1846 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1847 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1848 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1849 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1850 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1851 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1852 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1853 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1854 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1855 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1856 1857 #define BCE_DMA_CONFIG 0x00000c08 1858 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1859 #define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1860 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1861 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1862 #define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 1863 #define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1864 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1865 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1866 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1867 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1868 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1869 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1870 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1871 #define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1872 #define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1873 #define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1874 #define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1875 #define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1876 #define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1877 1878 #define BCE_DMA_BLACKOUT 0x00000c0c 1879 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1880 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1881 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1882 1883 #define BCE_DMA_RCHAN_STAT 0x00000c30 1884 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1885 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1886 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1887 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1888 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1889 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1890 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1891 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1892 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1893 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1894 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1895 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1896 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1897 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1898 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1899 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1900 1901 #define BCE_DMA_WCHAN_STAT 0x00000c34 1902 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1903 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1904 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1905 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1906 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1907 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1908 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1909 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1910 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1911 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1912 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1913 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1914 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1915 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1916 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1917 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1918 1919 #define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 1920 #define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1921 #define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1922 #define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1923 #define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1924 #define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1925 #define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1926 #define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1927 #define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1928 1929 #define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1930 #define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1931 #define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1932 #define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1933 #define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1934 #define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1935 #define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 1936 #define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 1937 #define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 1938 1939 #define BCE_DMA_RCHAN_STAT_00 0x00000c40 1940 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1941 1942 #define BCE_DMA_RCHAN_STAT_01 0x00000c44 1943 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1944 1945 #define BCE_DMA_RCHAN_STAT_02 0x00000c48 1946 #define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 1947 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 1948 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 1949 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1950 1951 #define BCE_DMA_RCHAN_STAT_10 0x00000c4c 1952 #define BCE_DMA_RCHAN_STAT_11 0x00000c50 1953 #define BCE_DMA_RCHAN_STAT_12 0x00000c54 1954 #define BCE_DMA_RCHAN_STAT_20 0x00000c58 1955 #define BCE_DMA_RCHAN_STAT_21 0x00000c5c 1956 #define BCE_DMA_RCHAN_STAT_22 0x00000c60 1957 #define BCE_DMA_RCHAN_STAT_30 0x00000c64 1958 #define BCE_DMA_RCHAN_STAT_31 0x00000c68 1959 #define BCE_DMA_RCHAN_STAT_32 0x00000c6c 1960 #define BCE_DMA_RCHAN_STAT_40 0x00000c70 1961 #define BCE_DMA_RCHAN_STAT_41 0x00000c74 1962 #define BCE_DMA_RCHAN_STAT_42 0x00000c78 1963 #define BCE_DMA_RCHAN_STAT_50 0x00000c7c 1964 #define BCE_DMA_RCHAN_STAT_51 0x00000c80 1965 #define BCE_DMA_RCHAN_STAT_52 0x00000c84 1966 #define BCE_DMA_RCHAN_STAT_60 0x00000c88 1967 #define BCE_DMA_RCHAN_STAT_61 0x00000c8c 1968 #define BCE_DMA_RCHAN_STAT_62 0x00000c90 1969 #define BCE_DMA_RCHAN_STAT_70 0x00000c94 1970 #define BCE_DMA_RCHAN_STAT_71 0x00000c98 1971 #define BCE_DMA_RCHAN_STAT_72 0x00000c9c 1972 #define BCE_DMA_WCHAN_STAT_00 0x00000ca0 1973 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1974 1975 #define BCE_DMA_WCHAN_STAT_01 0x00000ca4 1976 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1977 1978 #define BCE_DMA_WCHAN_STAT_02 0x00000ca8 1979 #define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 1980 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 1981 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 1982 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1983 1984 #define BCE_DMA_WCHAN_STAT_10 0x00000cac 1985 #define BCE_DMA_WCHAN_STAT_11 0x00000cb0 1986 #define BCE_DMA_WCHAN_STAT_12 0x00000cb4 1987 #define BCE_DMA_WCHAN_STAT_20 0x00000cb8 1988 #define BCE_DMA_WCHAN_STAT_21 0x00000cbc 1989 #define BCE_DMA_WCHAN_STAT_22 0x00000cc0 1990 #define BCE_DMA_WCHAN_STAT_30 0x00000cc4 1991 #define BCE_DMA_WCHAN_STAT_31 0x00000cc8 1992 #define BCE_DMA_WCHAN_STAT_32 0x00000ccc 1993 #define BCE_DMA_WCHAN_STAT_40 0x00000cd0 1994 #define BCE_DMA_WCHAN_STAT_41 0x00000cd4 1995 #define BCE_DMA_WCHAN_STAT_42 0x00000cd8 1996 #define BCE_DMA_WCHAN_STAT_50 0x00000cdc 1997 #define BCE_DMA_WCHAN_STAT_51 0x00000ce0 1998 #define BCE_DMA_WCHAN_STAT_52 0x00000ce4 1999 #define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2000 #define BCE_DMA_WCHAN_STAT_61 0x00000cec 2001 #define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2002 #define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2003 #define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2004 #define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2005 #define BCE_DMA_ARB_STAT_00 0x00000d00 2006 #define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2007 #define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2008 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2009 2010 #define BCE_DMA_ARB_STAT_01 0x00000d04 2011 #define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2012 #define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2013 #define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2014 #define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2015 #define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2016 #define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2017 #define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2018 #define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2019 2020 #define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2021 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2022 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2023 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2024 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2025 #define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2026 2027 #define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2028 #define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2029 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2030 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2031 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2032 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2033 #define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2034 2035 #define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2036 #define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2037 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2038 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2039 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2040 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2041 #define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2042 2043 #define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2044 2045 2046 /* 2047 * context_reg definition 2048 * offset: 0x1000 2049 */ 2050 #define BCE_CTX_COMMAND 0x00001000 2051 #define BCE_CTX_COMMAND_ENABLED (1L<<0) 2052 2053 #define BCE_CTX_STATUS 0x00001004 2054 #define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 2055 #define BCE_CTX_STATUS_READ_STAT (1L<<16) 2056 #define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 2057 #define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2058 #define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2059 2060 #define BCE_CTX_VIRT_ADDR 0x00001008 2061 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2062 2063 #define BCE_CTX_PAGE_TBL 0x0000100c 2064 #define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2065 2066 #define BCE_CTX_DATA_ADR 0x00001010 2067 #define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2068 2069 #define BCE_CTX_DATA 0x00001014 2070 #define BCE_CTX_LOCK 0x00001018 2071 #define BCE_CTX_LOCK_TYPE (0x7L<<0) 2072 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2073 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2074 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2075 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2076 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2077 #define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2078 #define BCE_CTX_LOCK_GRANTED (1L<<26) 2079 #define BCE_CTX_LOCK_MODE (0x7L<<27) 2080 #define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2081 #define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2082 #define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 2083 #define BCE_CTX_LOCK_STATUS (1L<<30) 2084 #define BCE_CTX_LOCK_REQ (1L<<31) 2085 2086 #define BCE_CTX_ACCESS_STATUS 0x00001040 2087 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2088 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2089 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2090 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2091 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2092 2093 #define BCE_CTX_DBG_LOCK_STATUS 0x00001044 2094 #define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2095 #define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2096 2097 #define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 2098 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2099 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2100 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2101 2102 #define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 2103 #define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 2104 #define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2105 #define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 2106 #define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 2107 #define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 2108 #define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2109 #define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2110 2111 2112 /* 2113 * emac_reg definition 2114 * offset: 0x1400 2115 */ 2116 #define BCE_EMAC_MODE 0x00001400 2117 #define BCE_EMAC_MODE_RESET (1L<<0) 2118 #define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 2119 #define BCE_EMAC_MODE_PORT (0x3L<<2) 2120 #define BCE_EMAC_MODE_PORT_NONE (0L<<2) 2121 #define BCE_EMAC_MODE_PORT_MII (1L<<2) 2122 #define BCE_EMAC_MODE_PORT_GMII (2L<<2) 2123 #define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 2124 #define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 2125 #define BCE_EMAC_MODE_25G (1L<<5) 2126 #define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2127 #define BCE_EMAC_MODE_TX_BURST (1L<<8) 2128 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2129 #define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 2130 #define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 2131 #define BCE_EMAC_MODE_MPKT (1L<<18) 2132 #define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 2133 #define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 2134 2135 #define BCE_EMAC_STATUS 0x00001404 2136 #define BCE_EMAC_STATUS_LINK (1L<<11) 2137 #define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 2138 #define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 2139 #define BCE_EMAC_STATUS_MI_INT (1L<<23) 2140 #define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 2141 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2142 2143 #define BCE_EMAC_ATTENTION_ENA 0x00001408 2144 #define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 2145 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2146 #define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2147 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2148 2149 #define BCE_EMAC_LED 0x0000140c 2150 #define BCE_EMAC_LED_OVERRIDE (1L<<0) 2151 #define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2152 #define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 2153 #define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 2154 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2155 #define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2156 #define BCE_EMAC_LED_TRAFFIC (1L<<6) 2157 #define BCE_EMAC_LED_1000MB (1L<<7) 2158 #define BCE_EMAC_LED_100MB (1L<<8) 2159 #define BCE_EMAC_LED_10MB (1L<<9) 2160 #define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 2161 #define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 2162 #define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2163 2164 #define BCE_EMAC_MAC_MATCH0 0x00001410 2165 #define BCE_EMAC_MAC_MATCH1 0x00001414 2166 #define BCE_EMAC_MAC_MATCH2 0x00001418 2167 #define BCE_EMAC_MAC_MATCH3 0x0000141c 2168 #define BCE_EMAC_MAC_MATCH4 0x00001420 2169 #define BCE_EMAC_MAC_MATCH5 0x00001424 2170 #define BCE_EMAC_MAC_MATCH6 0x00001428 2171 #define BCE_EMAC_MAC_MATCH7 0x0000142c 2172 #define BCE_EMAC_MAC_MATCH8 0x00001430 2173 #define BCE_EMAC_MAC_MATCH9 0x00001434 2174 #define BCE_EMAC_MAC_MATCH10 0x00001438 2175 #define BCE_EMAC_MAC_MATCH11 0x0000143c 2176 #define BCE_EMAC_MAC_MATCH12 0x00001440 2177 #define BCE_EMAC_MAC_MATCH13 0x00001444 2178 #define BCE_EMAC_MAC_MATCH14 0x00001448 2179 #define BCE_EMAC_MAC_MATCH15 0x0000144c 2180 #define BCE_EMAC_MAC_MATCH16 0x00001450 2181 #define BCE_EMAC_MAC_MATCH17 0x00001454 2182 #define BCE_EMAC_MAC_MATCH18 0x00001458 2183 #define BCE_EMAC_MAC_MATCH19 0x0000145c 2184 #define BCE_EMAC_MAC_MATCH20 0x00001460 2185 #define BCE_EMAC_MAC_MATCH21 0x00001464 2186 #define BCE_EMAC_MAC_MATCH22 0x00001468 2187 #define BCE_EMAC_MAC_MATCH23 0x0000146c 2188 #define BCE_EMAC_MAC_MATCH24 0x00001470 2189 #define BCE_EMAC_MAC_MATCH25 0x00001474 2190 #define BCE_EMAC_MAC_MATCH26 0x00001478 2191 #define BCE_EMAC_MAC_MATCH27 0x0000147c 2192 #define BCE_EMAC_MAC_MATCH28 0x00001480 2193 #define BCE_EMAC_MAC_MATCH29 0x00001484 2194 #define BCE_EMAC_MAC_MATCH30 0x00001488 2195 #define BCE_EMAC_MAC_MATCH31 0x0000148c 2196 #define BCE_EMAC_BACKOFF_SEED 0x00001498 2197 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2198 2199 #define BCE_EMAC_RX_MTU_SIZE 0x0000149c 2200 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2201 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2202 2203 #define BCE_EMAC_SERDES_CNTL 0x000014a4 2204 #define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2205 #define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2206 #define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2207 #define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2208 #define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2209 #define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2210 #define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2211 #define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2212 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2213 #define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2214 #define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2215 #define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2216 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2217 #define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2218 #define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2219 #define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2220 2221 #define BCE_EMAC_SERDES_STATUS 0x000014a8 2222 #define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2223 #define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2224 2225 #define BCE_EMAC_MDIO_COMM 0x000014ac 2226 #define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2227 #define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2228 #define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2229 #define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2230 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2231 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2232 #define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2233 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2234 #define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 2235 #define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2236 #define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 2237 2238 #define BCE_EMAC_MDIO_STATUS 0x000014b0 2239 #define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 2240 #define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 2241 2242 #define BCE_EMAC_MDIO_MODE 0x000014b4 2243 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2244 #define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2245 #define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2246 #define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 2247 #define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2248 #define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 2249 #define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 2250 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2251 2252 #define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 2253 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2254 2255 #define BCE_EMAC_TX_MODE 0x000014bc 2256 #define BCE_EMAC_TX_MODE_RESET (1L<<0) 2257 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2258 #define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 2259 #define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2260 #define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2261 #define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2262 2263 #define BCE_EMAC_TX_STATUS 0x000014c0 2264 #define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 2265 #define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2266 #define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 2267 #define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 2268 #define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2269 2270 #define BCE_EMAC_TX_LENGTHS 0x000014c4 2271 #define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2272 #define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2273 #define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2274 2275 #define BCE_EMAC_RX_MODE 0x000014c8 2276 #define BCE_EMAC_RX_MODE_RESET (1L<<0) 2277 #define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 2278 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2279 #define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2280 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2281 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2282 #define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 2283 #define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2284 #define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2285 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2286 #define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2287 #define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 2288 2289 #define BCE_EMAC_RX_STATUS 0x000014cc 2290 #define BCE_EMAC_RX_STATUS_FFED (1L<<0) 2291 #define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2292 #define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2293 2294 #define BCE_EMAC_MULTICAST_HASH0 0x000014d0 2295 #define BCE_EMAC_MULTICAST_HASH1 0x000014d4 2296 #define BCE_EMAC_MULTICAST_HASH2 0x000014d8 2297 #define BCE_EMAC_MULTICAST_HASH3 0x000014dc 2298 #define BCE_EMAC_MULTICAST_HASH4 0x000014e0 2299 #define BCE_EMAC_MULTICAST_HASH5 0x000014e4 2300 #define BCE_EMAC_MULTICAST_HASH6 0x000014e8 2301 #define BCE_EMAC_MULTICAST_HASH7 0x000014ec 2302 #define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2303 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2304 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2305 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2306 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2307 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2308 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2309 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2310 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2311 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2312 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2313 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2314 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2315 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2316 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2317 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2318 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2319 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2320 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2321 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2322 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2323 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2324 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2325 #define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 2326 #define BCE_EMAC_RXMAC_DEBUG1 0x00001560 2327 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2328 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2329 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2330 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2331 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2332 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2333 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2334 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2335 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2336 2337 #define BCE_EMAC_RXMAC_DEBUG2 0x00001564 2338 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2339 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2340 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2341 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2342 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2343 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2344 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2345 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2346 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2347 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2348 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2349 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2350 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2351 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2352 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2353 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2354 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2355 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2356 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2357 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2358 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2359 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2360 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2361 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2362 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2363 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2364 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2365 2366 #define BCE_EMAC_RXMAC_DEBUG3 0x00001568 2367 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2368 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2369 2370 #define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 2371 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2372 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2373 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2374 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2375 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2376 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2377 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2378 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2379 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2380 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2381 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2382 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2383 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2384 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2385 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2386 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2387 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2388 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2389 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2390 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2391 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2392 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2393 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2394 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2395 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2396 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2397 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2398 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2399 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2400 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2401 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2402 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2403 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2404 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2405 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2406 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2407 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2408 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2409 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2410 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2411 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2412 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2413 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2414 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2415 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2416 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2417 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2418 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2419 #define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 2420 2421 #define BCE_EMAC_RXMAC_DEBUG5 0x00001570 2422 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2423 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2424 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2425 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2426 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2427 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2428 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2429 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2430 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2431 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2432 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2433 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2434 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2435 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2436 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2437 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2438 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2439 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2440 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2441 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2442 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2443 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2444 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2445 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2446 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2447 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2448 2449 #define BCE_EMAC_RX_STAT_AC0 0x00001580 2450 #define BCE_EMAC_RX_STAT_AC1 0x00001584 2451 #define BCE_EMAC_RX_STAT_AC2 0x00001588 2452 #define BCE_EMAC_RX_STAT_AC3 0x0000158c 2453 #define BCE_EMAC_RX_STAT_AC4 0x00001590 2454 #define BCE_EMAC_RX_STAT_AC5 0x00001594 2455 #define BCE_EMAC_RX_STAT_AC6 0x00001598 2456 #define BCE_EMAC_RX_STAT_AC7 0x0000159c 2457 #define BCE_EMAC_RX_STAT_AC8 0x000015a0 2458 #define BCE_EMAC_RX_STAT_AC9 0x000015a4 2459 #define BCE_EMAC_RX_STAT_AC10 0x000015a8 2460 #define BCE_EMAC_RX_STAT_AC11 0x000015ac 2461 #define BCE_EMAC_RX_STAT_AC12 0x000015b0 2462 #define BCE_EMAC_RX_STAT_AC13 0x000015b4 2463 #define BCE_EMAC_RX_STAT_AC14 0x000015b8 2464 #define BCE_EMAC_RX_STAT_AC15 0x000015bc 2465 #define BCE_EMAC_RX_STAT_AC16 0x000015c0 2466 #define BCE_EMAC_RX_STAT_AC17 0x000015c4 2467 #define BCE_EMAC_RX_STAT_AC18 0x000015c8 2468 #define BCE_EMAC_RX_STAT_AC19 0x000015cc 2469 #define BCE_EMAC_RX_STAT_AC20 0x000015d0 2470 #define BCE_EMAC_RX_STAT_AC21 0x000015d4 2471 #define BCE_EMAC_RX_STAT_AC22 0x000015d8 2472 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2473 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2474 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2475 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2476 #define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2477 #define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2478 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2479 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2480 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2481 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2482 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2483 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2484 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2485 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2486 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2487 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2488 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2489 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2490 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2491 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2492 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2493 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2494 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2495 #define BCE_EMAC_TXMAC_DEBUG0 0x00001658 2496 #define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 2497 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2498 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2499 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2500 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2501 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2502 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2503 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2504 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2505 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2506 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2507 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2508 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2509 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2510 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2511 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2512 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2513 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2514 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2515 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2516 2517 #define BCE_EMAC_TXMAC_DEBUG2 0x00001660 2518 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2519 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2520 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2521 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2522 2523 #define BCE_EMAC_TXMAC_DEBUG3 0x00001664 2524 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2525 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2526 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2527 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2528 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2529 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2530 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2531 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2532 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2533 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2534 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2535 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2536 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2537 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2538 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2539 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2540 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2541 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2542 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2543 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2544 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2545 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2546 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2547 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2548 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2549 #define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2550 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2551 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2552 2553 #define BCE_EMAC_TXMAC_DEBUG4 0x00001668 2554 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2555 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2556 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2557 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2558 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2559 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2560 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2561 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2562 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2563 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2564 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2565 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2566 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2567 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2568 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2569 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2570 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2571 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2572 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2573 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2574 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2575 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2576 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2577 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2578 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2579 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2580 #define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2581 2582 #define BCE_EMAC_TX_STAT_AC0 0x00001680 2583 #define BCE_EMAC_TX_STAT_AC1 0x00001684 2584 #define BCE_EMAC_TX_STAT_AC2 0x00001688 2585 #define BCE_EMAC_TX_STAT_AC3 0x0000168c 2586 #define BCE_EMAC_TX_STAT_AC4 0x00001690 2587 #define BCE_EMAC_TX_STAT_AC5 0x00001694 2588 #define BCE_EMAC_TX_STAT_AC6 0x00001698 2589 #define BCE_EMAC_TX_STAT_AC7 0x0000169c 2590 #define BCE_EMAC_TX_STAT_AC8 0x000016a0 2591 #define BCE_EMAC_TX_STAT_AC9 0x000016a4 2592 #define BCE_EMAC_TX_STAT_AC10 0x000016a8 2593 #define BCE_EMAC_TX_STAT_AC11 0x000016ac 2594 #define BCE_EMAC_TX_STAT_AC12 0x000016b0 2595 #define BCE_EMAC_TX_STAT_AC13 0x000016b4 2596 #define BCE_EMAC_TX_STAT_AC14 0x000016b8 2597 #define BCE_EMAC_TX_STAT_AC15 0x000016bc 2598 #define BCE_EMAC_TX_STAT_AC16 0x000016c0 2599 #define BCE_EMAC_TX_STAT_AC17 0x000016c4 2600 #define BCE_EMAC_TX_STAT_AC18 0x000016c8 2601 #define BCE_EMAC_TX_STAT_AC19 0x000016cc 2602 #define BCE_EMAC_TX_STAT_AC20 0x000016d0 2603 #define BCE_EMAC_TX_STAT_AC21 0x000016d4 2604 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2605 2606 2607 /* 2608 * rpm_reg definition 2609 * offset: 0x1800 2610 */ 2611 #define BCE_RPM_COMMAND 0x00001800 2612 #define BCE_RPM_COMMAND_ENABLED (1L<<0) 2613 #define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2614 2615 #define BCE_RPM_STATUS 0x00001804 2616 #define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 2617 #define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 2618 2619 #define BCE_RPM_CONFIG 0x00001808 2620 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2621 #define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 2622 #define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 2623 #define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 2624 #define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2625 #define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2626 2627 #define BCE_RPM_VLAN_MATCH0 0x00001810 2628 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2629 2630 #define BCE_RPM_VLAN_MATCH1 0x00001814 2631 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2632 2633 #define BCE_RPM_VLAN_MATCH2 0x00001818 2634 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2635 2636 #define BCE_RPM_VLAN_MATCH3 0x0000181c 2637 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2638 2639 #define BCE_RPM_SORT_USER0 0x00001820 2640 #define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2641 #define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 2642 #define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 2643 #define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2644 #define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 2645 #define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2646 #define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2647 #define BCE_RPM_SORT_USER0_ENA (1L<<31) 2648 2649 #define BCE_RPM_SORT_USER1 0x00001824 2650 #define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2651 #define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 2652 #define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 2653 #define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2654 #define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 2655 #define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2656 #define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2657 #define BCE_RPM_SORT_USER1_ENA (1L<<31) 2658 2659 #define BCE_RPM_SORT_USER2 0x00001828 2660 #define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2661 #define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 2662 #define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 2663 #define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2664 #define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 2665 #define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2666 #define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2667 #define BCE_RPM_SORT_USER2_ENA (1L<<31) 2668 2669 #define BCE_RPM_SORT_USER3 0x0000182c 2670 #define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2671 #define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 2672 #define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 2673 #define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2674 #define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 2675 #define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2676 #define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2677 #define BCE_RPM_SORT_USER3_ENA (1L<<31) 2678 2679 #define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2680 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2681 #define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 2682 #define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2683 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2684 #define BCE_RPM_STAT_AC0 0x00001880 2685 #define BCE_RPM_STAT_AC1 0x00001884 2686 #define BCE_RPM_STAT_AC2 0x00001888 2687 #define BCE_RPM_STAT_AC3 0x0000188c 2688 #define BCE_RPM_STAT_AC4 0x00001890 2689 #define BCE_RPM_RC_CNTL_0 0x00001900 2690 #define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2691 #define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2692 #define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2693 #define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 2694 #define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2695 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2696 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2697 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2698 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2699 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2700 #define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 2701 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2702 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2703 #define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2704 #define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2705 #define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 2706 #define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2707 #define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 2708 #define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 2709 #define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 2710 #define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 2711 #define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 2712 #define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 2713 #define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 2714 2715 #define BCE_RPM_RC_VALUE_MASK_0 0x00001904 2716 #define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2717 #define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2718 2719 #define BCE_RPM_RC_CNTL_1 0x00001908 2720 #define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2721 #define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 2722 2723 #define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 2724 #define BCE_RPM_RC_CNTL_2 0x00001910 2725 #define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2726 #define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 2727 2728 #define BCE_RPM_RC_VALUE_MASK_2 0x00001914 2729 #define BCE_RPM_RC_CNTL_3 0x00001918 2730 #define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2731 #define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 2732 2733 #define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 2734 #define BCE_RPM_RC_CNTL_4 0x00001920 2735 #define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2736 #define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 2737 2738 #define BCE_RPM_RC_VALUE_MASK_4 0x00001924 2739 #define BCE_RPM_RC_CNTL_5 0x00001928 2740 #define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2741 #define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 2742 2743 #define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 2744 #define BCE_RPM_RC_CNTL_6 0x00001930 2745 #define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2746 #define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 2747 2748 #define BCE_RPM_RC_VALUE_MASK_6 0x00001934 2749 #define BCE_RPM_RC_CNTL_7 0x00001938 2750 #define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2751 #define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 2752 2753 #define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 2754 #define BCE_RPM_RC_CNTL_8 0x00001940 2755 #define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2756 #define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 2757 2758 #define BCE_RPM_RC_VALUE_MASK_8 0x00001944 2759 #define BCE_RPM_RC_CNTL_9 0x00001948 2760 #define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2761 #define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 2762 2763 #define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 2764 #define BCE_RPM_RC_CNTL_10 0x00001950 2765 #define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2766 #define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 2767 2768 #define BCE_RPM_RC_VALUE_MASK_10 0x00001954 2769 #define BCE_RPM_RC_CNTL_11 0x00001958 2770 #define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2771 #define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 2772 2773 #define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 2774 #define BCE_RPM_RC_CNTL_12 0x00001960 2775 #define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2776 #define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 2777 2778 #define BCE_RPM_RC_VALUE_MASK_12 0x00001964 2779 #define BCE_RPM_RC_CNTL_13 0x00001968 2780 #define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2781 #define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 2782 2783 #define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 2784 #define BCE_RPM_RC_CNTL_14 0x00001970 2785 #define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2786 #define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 2787 2788 #define BCE_RPM_RC_VALUE_MASK_14 0x00001974 2789 #define BCE_RPM_RC_CNTL_15 0x00001978 2790 #define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2791 #define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 2792 2793 #define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 2794 #define BCE_RPM_RC_CONFIG 0x00001980 2795 #define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2796 #define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2797 2798 #define BCE_RPM_DEBUG0 0x00001984 2799 #define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2800 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2801 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2802 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2803 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2804 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2805 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2806 #define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 2807 #define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 2808 #define BCE_RPM_DEBUG0_DONE (1L<<24) 2809 #define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2810 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2811 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2812 #define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2813 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2814 2815 #define BCE_RPM_DEBUG1 0x00001988 2816 #define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2817 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2818 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2819 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2820 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2821 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2822 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2823 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2824 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2825 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2826 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2827 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2828 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2829 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2830 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2831 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2832 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2833 #define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2834 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2835 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2836 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2837 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2838 2839 #define BCE_RPM_DEBUG2 0x0000198c 2840 #define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2841 #define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2842 #define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2843 #define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2844 #define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2845 #define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2846 #define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2847 #define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 2848 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2849 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2850 2851 #define BCE_RPM_DEBUG3 0x00001990 2852 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2853 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2854 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2855 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2856 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2857 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2858 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2859 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2860 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2861 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2862 #define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2863 #define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 2864 #define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2865 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2866 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2867 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2868 #define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2869 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2870 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2871 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2872 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2873 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2874 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2875 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2876 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2877 #define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2878 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2879 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2880 #define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2881 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2882 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2883 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2884 2885 #define BCE_RPM_DEBUG4 0x00001994 2886 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2887 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2888 #define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2889 #define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2890 2891 #define BCE_RPM_DEBUG5 0x00001998 2892 #define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 2893 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 2894 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 2895 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 2896 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 2897 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 2898 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 2899 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 2900 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 2901 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 2902 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 2903 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 2904 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 2905 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 2906 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 2907 #define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 2908 2909 #define BCE_RPM_DEBUG6 0x0000199c 2910 #define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 2911 #define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 2912 2913 #define BCE_RPM_DEBUG7 0x000019a0 2914 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 2915 2916 #define BCE_RPM_DEBUG8 0x000019a4 2917 #define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 2918 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 2919 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 2920 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 2921 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 2922 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 2923 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 2924 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 2925 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 2926 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 2927 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 2928 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 2929 #define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 2930 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 2931 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 2932 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 2933 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 2934 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 2935 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 2936 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 2937 #define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 2938 #define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 2939 #define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 2940 #define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 2941 #define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 2942 #define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 2943 2944 #define BCE_RPM_DEBUG9 0x000019a8 2945 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 2946 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 2947 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 2948 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 2949 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 2950 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 2951 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 2952 2953 #define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 2954 #define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 2955 #define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 2956 #define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 2957 #define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 2958 #define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 2959 #define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 2960 #define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 2961 #define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 2962 #define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 2963 #define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 2964 #define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 2965 #define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 2966 #define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 2967 #define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 2968 #define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 2969 2970 2971 /* 2972 * rbuf_reg definition 2973 * offset: 0x200000 2974 */ 2975 #define BCE_RBUF_COMMAND 0x00200000 2976 #define BCE_RBUF_COMMAND_ENABLED (1L<<0) 2977 #define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 2978 #define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 2979 #define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 2980 #define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 2981 2982 #define BCE_RBUF_STATUS1 0x00200004 2983 #define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 2984 2985 #define BCE_RBUF_STATUS2 0x00200008 2986 #define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 2987 #define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 2988 2989 #define BCE_RBUF_CONFIG 0x0020000c 2990 #define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 2991 #define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 2992 2993 #define BCE_RBUF_FW_BUF_ALLOC 0x00200010 2994 #define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 2995 2996 #define BCE_RBUF_FW_BUF_FREE 0x00200014 2997 #define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 2998 #define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 2999 #define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3000 3001 #define BCE_RBUF_FW_BUF_SEL 0x00200018 3002 #define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3003 #define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3004 #define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3005 3006 #define BCE_RBUF_CONFIG2 0x0020001c 3007 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3008 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3009 3010 #define BCE_RBUF_CONFIG3 0x00200020 3011 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3012 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3013 3014 #define BCE_RBUF_PKT_DATA 0x00208000 3015 #define BCE_RBUF_CLIST_DATA 0x00210000 3016 #define BCE_RBUF_BUF_DATA 0x00220000 3017 3018 3019 /* 3020 * rv2p_reg definition 3021 * offset: 0x2800 3022 */ 3023 #define BCE_RV2P_COMMAND 0x00002800 3024 #define BCE_RV2P_COMMAND_ENABLED (1L<<0) 3025 #define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3026 #define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3027 #define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 3028 #define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 3029 #define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 3030 #define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 3031 #define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 3032 #define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 3033 #define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 3034 #define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 3035 #define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3036 3037 #define BCE_RV2P_STATUS 0x00002804 3038 #define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 3039 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3040 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3041 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3042 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3043 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3044 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3045 3046 #define BCE_RV2P_CONFIG 0x00002808 3047 #define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3048 #define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3049 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3050 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3051 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3052 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3053 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3054 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3055 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3056 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3057 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3058 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3059 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3060 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3061 #define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3062 #define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3063 #define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3064 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3065 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3066 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3067 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3068 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3069 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3070 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3071 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3072 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3073 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3074 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3075 3076 #define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 3077 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3078 3079 #define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 3080 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3081 3082 #define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 3083 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3084 3085 #define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 3086 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3087 3088 #define BCE_RV2P_INSTR_HIGH 0x00002830 3089 #define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3090 3091 #define BCE_RV2P_INSTR_LOW 0x00002834 3092 #define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 3093 #define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3094 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3095 3096 #define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 3097 #define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3098 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3099 3100 #define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 3101 #define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 3102 #define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 3103 #define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 3104 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3105 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3106 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3107 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3108 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3109 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3110 3111 #define BCE_RV2P_PFTQ_DATA 0x00002b40 3112 #define BCE_RV2P_PFTQ_CMD 0x00002b78 3113 #define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3114 #define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3115 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3116 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3117 #define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3118 #define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3119 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3120 #define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3121 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3122 #define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 3123 #define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 3124 3125 #define BCE_RV2P_PFTQ_CTL 0x00002b7c 3126 #define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3127 #define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3128 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3129 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3130 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3131 3132 #define BCE_RV2P_TFTQ_DATA 0x00002b80 3133 #define BCE_RV2P_TFTQ_CMD 0x00002bb8 3134 #define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3135 #define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3136 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3137 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3138 #define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3139 #define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3140 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3141 #define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3142 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3143 #define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 3144 #define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 3145 3146 #define BCE_RV2P_TFTQ_CTL 0x00002bbc 3147 #define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3148 #define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3149 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3150 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3151 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3152 3153 #define BCE_RV2P_MFTQ_DATA 0x00002bc0 3154 #define BCE_RV2P_MFTQ_CMD 0x00002bf8 3155 #define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3156 #define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3157 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3158 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3159 #define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3160 #define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3161 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3162 #define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3163 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3164 #define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 3165 #define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 3166 3167 #define BCE_RV2P_MFTQ_CTL 0x00002bfc 3168 #define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3169 #define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3170 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3171 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3172 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3173 3174 3175 3176 /* 3177 * mq_reg definition 3178 * offset: 0x3c00 3179 */ 3180 #define BCE_MQ_COMMAND 0x00003c00 3181 #define BCE_MQ_COMMAND_ENABLED (1L<<0) 3182 #define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 3183 #define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 3184 #define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 3185 3186 #define BCE_MQ_STATUS 0x00003c04 3187 #define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3188 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3189 #define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3190 3191 #define BCE_MQ_CONFIG 0x00003c08 3192 #define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3193 #define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 3194 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3195 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3196 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3197 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3198 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3199 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3200 #define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3201 #define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3202 3203 #define BCE_MQ_ENQUEUE1 0x00003c0c 3204 #define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3205 #define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 3206 #define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3207 #define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3208 3209 #define BCE_MQ_ENQUEUE2 0x00003c10 3210 #define BCE_MQ_BAD_WR_ADDR 0x00003c14 3211 #define BCE_MQ_BAD_RD_ADDR 0x00003c18 3212 #define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 3213 #define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3214 3215 #define BCE_MQ_KNL_WIND_END 0x00003c20 3216 #define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3217 3218 #define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 3219 #define BCE_MQ_KNL_TX_MASK1 0x00003c28 3220 #define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 3221 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3222 #define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 3223 #define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 3224 #define BCE_MQ_KNL_TX_MASK2 0x00003c3c 3225 #define BCE_MQ_KNL_CMD_MASK2 0x00003c40 3226 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3227 #define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 3228 #define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3229 #define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 3230 #define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3231 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3232 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3233 #define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3234 #define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 3235 #define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3236 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3237 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3238 #define BCE_MQ_MEM_WR_ADDR 0x00003c74 3239 #define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3240 3241 #define BCE_MQ_MEM_WR_DATA0 0x00003c78 3242 #define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3243 3244 #define BCE_MQ_MEM_WR_DATA1 0x00003c7c 3245 #define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3246 3247 #define BCE_MQ_MEM_WR_DATA2 0x00003c80 3248 #define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3249 3250 #define BCE_MQ_MEM_RD_ADDR 0x00003c84 3251 #define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3252 3253 #define BCE_MQ_MEM_RD_DATA0 0x00003c88 3254 #define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3255 3256 #define BCE_MQ_MEM_RD_DATA1 0x00003c8c 3257 #define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3258 3259 #define BCE_MQ_MEM_RD_DATA2 0x00003c90 3260 #define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3261 3262 3263 3264 /* 3265 * tbdr_reg definition 3266 * offset: 0x5000 3267 */ 3268 #define BCE_TBDR_COMMAND 0x00005000 3269 #define BCE_TBDR_COMMAND_ENABLE (1L<<0) 3270 #define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 3271 #define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3272 3273 #define BCE_TBDR_STATUS 0x00005004 3274 #define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 3275 #define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 3276 #define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3277 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3278 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3279 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3280 #define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 3281 3282 #define BCE_TBDR_CONFIG 0x00005008 3283 #define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3284 #define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 3285 #define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 3286 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3287 #define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3288 #define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3289 #define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3290 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3291 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3292 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3293 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3294 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3295 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3296 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3297 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3298 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3299 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3300 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3301 3302 #define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 3303 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3304 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3305 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3306 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3307 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3308 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3309 3310 #define BCE_TBDR_FTQ_DATA 0x000053c0 3311 #define BCE_TBDR_FTQ_CMD 0x000053f8 3312 #define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3313 #define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3314 #define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3315 #define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3316 #define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3317 #define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3318 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3319 #define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3320 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3321 #define BCE_TBDR_FTQ_CMD_POP (1L<<30) 3322 #define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 3323 3324 #define BCE_TBDR_FTQ_CTL 0x000053fc 3325 #define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3326 #define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3327 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3328 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3329 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3330 3331 3332 3333 /* 3334 * tdma_reg definition 3335 * offset: 0x5c00 3336 */ 3337 #define BCE_TDMA_COMMAND 0x00005c00 3338 #define BCE_TDMA_COMMAND_ENABLED (1L<<0) 3339 #define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3340 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3341 3342 #define BCE_TDMA_STATUS 0x00005c04 3343 #define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 3344 #define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3345 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3346 #define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 3347 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3348 #define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 3349 3350 #define BCE_TDMA_CONFIG 0x00005c08 3351 #define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 3352 #define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 3353 #define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3354 #define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3355 #define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3356 #define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3357 #define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3358 #define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3359 #define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3360 #define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3361 #define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3362 #define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3363 #define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3364 #define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3365 #define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3366 3367 #define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 3368 #define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3369 3370 #define BCE_TDMA_DBG_WATCHDOG 0x00005c10 3371 #define BCE_TDMA_DBG_TRIGGER 0x00005c14 3372 #define BCE_TDMA_DMAD_FSM 0x00005c80 3373 #define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3374 #define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3375 #define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3376 #define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3377 #define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3378 #define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3379 #define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 3380 3381 #define BCE_TDMA_DMAD_STATUS 0x00005c84 3382 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3383 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3384 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3385 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3386 3387 #define BCE_TDMA_DR_INTF_FSM 0x00005c88 3388 #define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3389 #define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3390 #define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3391 #define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3392 #define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3393 3394 #define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 3395 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3396 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3397 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3398 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3399 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3400 3401 #define BCE_TDMA_FTQ_DATA 0x00005fc0 3402 #define BCE_TDMA_FTQ_CMD 0x00005ff8 3403 #define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3404 #define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3405 #define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3406 #define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3407 #define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3408 #define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3409 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3410 #define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3411 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3412 #define BCE_TDMA_FTQ_CMD_POP (1L<<30) 3413 #define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 3414 3415 #define BCE_TDMA_FTQ_CTL 0x00005ffc 3416 #define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3417 #define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3418 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3419 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3420 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3421 3422 3423 3424 /* 3425 * hc_reg definition 3426 * offset: 0x6800 3427 */ 3428 #define BCE_HC_COMMAND 0x00006800 3429 #define BCE_HC_COMMAND_ENABLE (1L<<0) 3430 #define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 3431 #define BCE_HC_COMMAND_COAL_NOW (1L<<16) 3432 #define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3433 #define BCE_HC_COMMAND_STATS_NOW (1L<<18) 3434 #define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 3435 #define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3436 #define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3437 #define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3438 #define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3439 #define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3440 3441 #define BCE_HC_STATUS 0x00006804 3442 #define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 3443 #define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3444 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3445 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3446 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3447 #define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3448 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3449 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3450 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3451 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3452 3453 #define BCE_HC_CONFIG 0x00006808 3454 #define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 3455 #define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 3456 #define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 3457 #define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 3458 #define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3459 #define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3460 #define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3461 #define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3462 3463 #define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 3464 #define BCE_HC_STATUS_ADDR_L 0x00006810 3465 #define BCE_HC_STATUS_ADDR_H 0x00006814 3466 #define BCE_HC_STATISTICS_ADDR_L 0x00006818 3467 #define BCE_HC_STATISTICS_ADDR_H 0x0000681c 3468 #define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 3469 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3470 #define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3471 3472 #define BCE_HC_COMP_PROD_TRIP 0x00006824 3473 #define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3474 #define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3475 3476 #define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 3477 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3478 #define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3479 3480 #define BCE_HC_RX_TICKS 0x0000682c 3481 #define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 3482 #define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 3483 3484 #define BCE_HC_TX_TICKS 0x00006830 3485 #define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 3486 #define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 3487 3488 #define BCE_HC_COM_TICKS 0x00006834 3489 #define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 3490 #define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 3491 3492 #define BCE_HC_CMD_TICKS 0x00006838 3493 #define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3494 #define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 3495 3496 #define BCE_HC_PERIODIC_TICKS 0x0000683c 3497 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3498 3499 #define BCE_HC_STAT_COLLECT_TICKS 0x00006840 3500 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3501 3502 #define BCE_HC_STATS_TICKS 0x00006844 3503 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3504 3505 #define BCE_HC_STAT_MEM_DATA 0x0000684c 3506 #define BCE_HC_STAT_GEN_SEL_0 0x00006850 3507 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3508 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3509 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3510 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3511 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3512 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3513 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3514 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3515 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3516 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3517 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3518 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3519 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3520 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3521 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3522 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3523 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3524 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3525 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3526 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3527 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3528 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3529 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3530 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3531 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3532 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3533 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3534 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3535 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3536 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3537 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3538 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3539 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3540 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3541 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3542 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3543 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3544 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3545 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3546 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3547 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3548 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3549 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3550 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3551 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3552 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3553 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3554 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3555 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3556 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3557 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3558 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3559 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3560 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3561 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3562 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3563 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3564 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3565 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3566 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3567 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3568 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3569 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3570 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3571 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3572 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3573 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3574 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3575 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3576 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3577 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3578 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3579 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3580 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3581 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3582 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3583 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3584 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3585 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3586 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3587 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3588 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3589 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3590 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3591 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3592 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3593 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3594 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3595 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3596 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3597 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3598 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3599 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3600 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3601 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3602 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3603 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3604 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3605 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3606 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3607 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3608 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3609 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3610 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3611 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3612 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3613 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3614 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3615 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3616 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3617 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3618 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3619 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3620 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3621 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3622 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3623 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3624 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3625 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3626 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3627 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3628 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3629 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3630 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3631 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3632 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3633 3634 #define BCE_HC_STAT_GEN_SEL_1 0x00006854 3635 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3636 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3637 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3638 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3639 3640 #define BCE_HC_STAT_GEN_SEL_2 0x00006858 3641 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3642 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3643 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3644 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3645 3646 #define BCE_HC_STAT_GEN_SEL_3 0x0000685c 3647 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3648 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3649 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3650 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3651 3652 #define BCE_HC_STAT_GEN_STAT0 0x00006888 3653 #define BCE_HC_STAT_GEN_STAT1 0x0000688c 3654 #define BCE_HC_STAT_GEN_STAT2 0x00006890 3655 #define BCE_HC_STAT_GEN_STAT3 0x00006894 3656 #define BCE_HC_STAT_GEN_STAT4 0x00006898 3657 #define BCE_HC_STAT_GEN_STAT5 0x0000689c 3658 #define BCE_HC_STAT_GEN_STAT6 0x000068a0 3659 #define BCE_HC_STAT_GEN_STAT7 0x000068a4 3660 #define BCE_HC_STAT_GEN_STAT8 0x000068a8 3661 #define BCE_HC_STAT_GEN_STAT9 0x000068ac 3662 #define BCE_HC_STAT_GEN_STAT10 0x000068b0 3663 #define BCE_HC_STAT_GEN_STAT11 0x000068b4 3664 #define BCE_HC_STAT_GEN_STAT12 0x000068b8 3665 #define BCE_HC_STAT_GEN_STAT13 0x000068bc 3666 #define BCE_HC_STAT_GEN_STAT14 0x000068c0 3667 #define BCE_HC_STAT_GEN_STAT15 0x000068c4 3668 #define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 3669 #define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 3670 #define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 3671 #define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 3672 #define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 3673 #define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 3674 #define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 3675 #define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 3676 #define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 3677 #define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 3678 #define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 3679 #define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 3680 #define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 3681 #define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 3682 #define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 3683 #define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 3684 #define BCE_HC_VIS 0x00006908 3685 #define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3686 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3687 #define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3688 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3689 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3690 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3691 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3692 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3693 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3694 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3695 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3696 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3697 #define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3698 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3699 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3700 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3701 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3702 #define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3703 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3704 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3705 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3706 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3707 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3708 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3709 #define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3710 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3711 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3712 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3713 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3714 3715 #define BCE_HC_VIS_1 0x0000690c 3716 #define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3717 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3718 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3719 #define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3720 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3721 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3722 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3723 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3724 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3725 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3726 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3727 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3728 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3729 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3730 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3731 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3732 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3733 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3734 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3735 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3736 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3737 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3738 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3739 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3740 #define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 3741 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3742 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3743 #define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3744 #define BCE_HC_VIS_1_INT_B (1L<<27) 3745 3746 #define BCE_HC_DEBUG_VECT_PEEK 0x00006910 3747 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3748 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3749 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3750 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3751 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3752 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3753 3754 3755 3756 /* 3757 * txp_reg definition 3758 * offset: 0x40000 3759 */ 3760 #define BCE_TXP_CPU_MODE 0x00045000 3761 #define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3762 #define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 3763 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3764 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3765 #define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3766 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3767 #define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3768 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3769 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3770 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3771 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3772 3773 #define BCE_TXP_CPU_STATE 0x00045004 3774 #define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3775 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3776 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3777 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3778 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3779 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3780 #define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3781 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3782 #define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3783 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3784 #define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3785 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3786 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3787 #define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3788 3789 #define BCE_TXP_CPU_EVENT_MASK 0x00045008 3790 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3791 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3792 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3793 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3794 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3795 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3796 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3797 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3798 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3799 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3800 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3801 3802 #define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3803 #define BCE_TXP_CPU_INSTRUCTION 0x00045020 3804 #define BCE_TXP_CPU_DATA_ACCESS 0x00045024 3805 #define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3806 #define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3807 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3808 #define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 3809 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3810 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3811 3812 #define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3813 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3814 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3815 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3816 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3817 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3818 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3819 3820 #define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3821 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3822 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3823 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3824 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3825 3826 #define BCE_TXP_CPU_REG_FILE 0x00045200 3827 #define BCE_TXP_FTQ_DATA 0x000453c0 3828 #define BCE_TXP_FTQ_CMD 0x000453f8 3829 #define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3830 #define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 3831 #define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3832 #define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3833 #define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3834 #define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 3835 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3836 #define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3837 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3838 #define BCE_TXP_FTQ_CMD_POP (1L<<30) 3839 #define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 3840 3841 #define BCE_TXP_FTQ_CTL 0x000453fc 3842 #define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 3843 #define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3844 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3845 #define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3846 #define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3847 3848 #define BCE_TXP_SCRATCH 0x00060000 3849 3850 3851 /* 3852 * tpat_reg definition 3853 * offset: 0x80000 3854 */ 3855 #define BCE_TPAT_CPU_MODE 0x00085000 3856 #define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3857 #define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3858 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3859 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3860 #define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3861 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3862 #define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3863 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3864 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3865 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3866 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3867 3868 #define BCE_TPAT_CPU_STATE 0x00085004 3869 #define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3870 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3871 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3872 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3873 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3874 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3875 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3876 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3877 #define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3878 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3879 #define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3880 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3881 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 3882 #define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 3883 3884 #define BCE_TPAT_CPU_EVENT_MASK 0x00085008 3885 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3886 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3887 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3888 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3889 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3890 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3891 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3892 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3893 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3894 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3895 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3896 3897 #define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 3898 #define BCE_TPAT_CPU_INSTRUCTION 0x00085020 3899 #define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 3900 #define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 3901 #define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 3902 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 3903 #define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 3904 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3905 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3906 3907 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 3908 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3909 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3910 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3911 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3912 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3913 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3914 3915 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 3916 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3917 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3918 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3919 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3920 3921 #define BCE_TPAT_CPU_REG_FILE 0x00085200 3922 #define BCE_TPAT_FTQ_DATA 0x000853c0 3923 #define BCE_TPAT_FTQ_CMD 0x000853f8 3924 #define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 3925 #define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 3926 #define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 3927 #define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 3928 #define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 3929 #define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 3930 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 3931 #define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 3932 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 3933 #define BCE_TPAT_FTQ_CMD_POP (1L<<30) 3934 #define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 3935 3936 #define BCE_TPAT_FTQ_CTL 0x000853fc 3937 #define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 3938 #define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 3939 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3940 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3941 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3942 3943 #define BCE_TPAT_SCRATCH 0x000a0000 3944 3945 3946 /* 3947 * rxp_reg definition 3948 * offset: 0xc0000 3949 */ 3950 #define BCE_RXP_CPU_MODE 0x000c5000 3951 #define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 3952 #define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 3953 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3954 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3955 #define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 3956 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3957 #define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 3958 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3959 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3960 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3961 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3962 3963 #define BCE_RXP_CPU_STATE 0x000c5004 3964 #define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 3965 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3966 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3967 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3968 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3969 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3970 #define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3971 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3972 #define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 3973 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3974 #define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 3975 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3976 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3977 #define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 3978 3979 #define BCE_RXP_CPU_EVENT_MASK 0x000c5008 3980 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3981 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3982 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3983 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3984 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3985 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3986 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3987 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3988 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3989 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3990 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3991 3992 #define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 3993 #define BCE_RXP_CPU_INSTRUCTION 0x000c5020 3994 #define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 3995 #define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 3996 #define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 3997 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 3998 #define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 3999 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4000 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4001 4002 #define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 4003 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4004 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4005 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4006 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4007 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4008 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4009 4010 #define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 4011 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4012 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4013 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4014 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4015 4016 #define BCE_RXP_CPU_REG_FILE 0x000c5200 4017 #define BCE_RXP_CFTQ_DATA 0x000c5380 4018 #define BCE_RXP_CFTQ_CMD 0x000c53b8 4019 #define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 4020 #define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 4021 #define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 4022 #define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4023 #define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4024 #define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4025 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4026 #define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4027 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4028 #define BCE_RXP_CFTQ_CMD_POP (1L<<30) 4029 #define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 4030 4031 #define BCE_RXP_CFTQ_CTL 0x000c53bc 4032 #define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4033 #define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4034 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4035 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4036 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4037 4038 #define BCE_RXP_FTQ_DATA 0x000c53c0 4039 #define BCE_RXP_FTQ_CMD 0x000c53f8 4040 #define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4041 #define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 4042 #define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4043 #define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4044 #define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4045 #define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 4046 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4047 #define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4048 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4049 #define BCE_RXP_FTQ_CMD_POP (1L<<30) 4050 #define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 4051 4052 #define BCE_RXP_FTQ_CTL 0x000c53fc 4053 #define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 4054 #define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4055 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4056 #define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4057 #define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4058 4059 #define BCE_RXP_SCRATCH 0x000e0000 4060 4061 4062 /* 4063 * com_reg definition 4064 * offset: 0x100000 4065 */ 4066 #define BCE_COM_CPU_MODE 0x00105000 4067 #define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 4068 #define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 4069 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4070 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4071 #define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4072 #define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4073 #define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 4074 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4075 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4076 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4077 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4078 4079 #define BCE_COM_CPU_STATE 0x00105004 4080 #define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 4081 #define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4082 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4083 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4084 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4085 #define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4086 #define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4087 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4088 #define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4089 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4090 #define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 4091 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4092 #define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4093 #define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4094 4095 #define BCE_COM_CPU_EVENT_MASK 0x00105008 4096 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4097 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4098 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4099 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4100 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4101 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4102 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4103 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4104 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4105 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4106 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4107 4108 #define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 4109 #define BCE_COM_CPU_INSTRUCTION 0x00105020 4110 #define BCE_COM_CPU_DATA_ACCESS 0x00105024 4111 #define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 4112 #define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4113 #define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4114 #define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 4115 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4116 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4117 4118 #define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4119 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4120 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4121 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4122 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4123 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4124 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4125 4126 #define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4127 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4128 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4129 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4130 #define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4131 4132 #define BCE_COM_CPU_REG_FILE 0x00105200 4133 #define BCE_COM_COMXQ_FTQ_DATA 0x00105340 4134 #define BCE_COM_COMXQ_FTQ_CMD 0x00105378 4135 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4136 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4137 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4138 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4139 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4140 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4141 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4142 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4143 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4144 #define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4145 #define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4146 4147 #define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 4148 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4149 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4150 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4151 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4152 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4153 4154 #define BCE_COM_COMTQ_FTQ_DATA 0x00105380 4155 #define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 4156 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4157 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4158 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4159 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4160 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4161 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4162 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4163 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4164 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4165 #define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4166 #define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4167 4168 #define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 4169 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4170 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4171 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4172 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4173 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4174 4175 #define BCE_COM_COMQ_FTQ_DATA 0x001053c0 4176 #define BCE_COM_COMQ_FTQ_CMD 0x001053f8 4177 #define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4178 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4179 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4180 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4181 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4182 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4183 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4184 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4185 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4186 #define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 4187 #define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4188 4189 #define BCE_COM_COMQ_FTQ_CTL 0x001053fc 4190 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4191 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4192 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4193 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4194 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4195 4196 #define BCE_COM_SCRATCH 0x00120000 4197 4198 4199 /* 4200 * cp_reg definition 4201 * offset: 0x180000 4202 */ 4203 #define BCE_CP_CPU_MODE 0x00185000 4204 #define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 4205 #define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 4206 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4207 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4208 #define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4209 #define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4210 #define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 4211 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4212 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4213 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4214 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4215 4216 #define BCE_CP_CPU_STATE 0x00185004 4217 #define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 4218 #define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4219 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4220 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4221 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4222 #define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4223 #define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4224 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4225 #define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4226 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4227 #define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 4228 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4229 #define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4230 #define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4231 4232 #define BCE_CP_CPU_EVENT_MASK 0x00185008 4233 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4234 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4235 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4236 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4237 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4238 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4239 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4240 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4241 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4242 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4243 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4244 4245 #define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 4246 #define BCE_CP_CPU_INSTRUCTION 0x00185020 4247 #define BCE_CP_CPU_DATA_ACCESS 0x00185024 4248 #define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 4249 #define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4250 #define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4251 #define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 4252 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4253 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4254 4255 #define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4256 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4257 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4258 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4259 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4260 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4261 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4262 4263 #define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4264 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4265 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4266 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4267 #define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4268 4269 #define BCE_CP_CPU_REG_FILE 0x00185200 4270 #define BCE_CP_CPQ_FTQ_DATA 0x001853c0 4271 #define BCE_CP_CPQ_FTQ_CMD 0x001853f8 4272 #define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4273 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4274 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4275 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4276 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4277 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4278 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4279 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4280 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4281 #define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 4282 #define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4283 4284 #define BCE_CP_CPQ_FTQ_CTL 0x001853fc 4285 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4286 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4287 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4288 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4289 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4290 4291 #define BCE_CP_SCRATCH 0x001a0000 4292 4293 4294 /* 4295 * mcp_reg definition 4296 * offset: 0x140000 4297 */ 4298 #define BCE_MCP_CPU_MODE 0x00145000 4299 #define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4300 #define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 4301 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4302 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4303 #define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4304 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4305 #define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4306 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4307 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4308 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4309 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4310 4311 #define BCE_MCP_CPU_STATE 0x00145004 4312 #define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4313 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4314 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4315 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4316 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4317 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4318 #define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4319 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4320 #define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4321 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4322 #define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4323 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4324 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4325 #define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4326 4327 #define BCE_MCP_CPU_EVENT_MASK 0x00145008 4328 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4329 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4330 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4331 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4332 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4333 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4334 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4335 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4336 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4337 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4338 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4339 4340 #define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4341 #define BCE_MCP_CPU_INSTRUCTION 0x00145020 4342 #define BCE_MCP_CPU_DATA_ACCESS 0x00145024 4343 #define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4344 #define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4345 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4346 #define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 4347 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4348 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4349 4350 #define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4351 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4352 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4353 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4354 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4355 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4356 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4357 4358 #define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4359 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4360 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4361 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4362 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4363 4364 #define BCE_MCP_CPU_REG_FILE 0x00145200 4365 #define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 4366 #define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 4367 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4368 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4369 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4370 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4371 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4372 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4373 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4374 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4375 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4376 #define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4377 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4378 4379 #define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 4380 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4381 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4382 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4383 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4384 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4385 4386 #define BCE_MCP_ROM 0x00150000 4387 #define BCE_MCP_SCRATCH 0x00160000 4388 4389 #define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 4390 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4391 #define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 4392 #define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4393 #define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4394 4395 #define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 4396 #define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 4397 4398 /****************************************************************************/ 4399 /* End machine generated definitions. */ 4400 /****************************************************************************/ 4401 4402 #define NUM_MC_HASH_REGISTERS 8 4403 4404 4405 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4406 #define PHY_BCM5706_PHY_ID 0x00206160 4407 4408 #define PHY_ID(id) ((id) & 0xfffffff0) 4409 #define PHY_REV_ID(id) ((id) & 0xf) 4410 4411 /* 5708 Serdes PHY registers */ 4412 4413 #define BCM5708S_UP1 0xb 4414 4415 #define BCM5708S_UP1_2G5 0x1 4416 4417 #define BCM5708S_BLK_ADDR 0x1f 4418 4419 #define BCM5708S_BLK_ADDR_DIG 0x0000 4420 #define BCM5708S_BLK_ADDR_DIG3 0x0002 4421 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4422 4423 /* Digital Block */ 4424 #define BCM5708S_1000X_CTL1 0x10 4425 4426 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4427 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4428 4429 #define BCM5708S_1000X_CTL2 0x11 4430 4431 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4432 4433 #define BCM5708S_1000X_STAT1 0x14 4434 4435 #define BCM5708S_1000X_STAT1_SGMII 0x0001 4436 #define BCM5708S_1000X_STAT1_LINK 0x0002 4437 #define BCM5708S_1000X_STAT1_FD 0x0004 4438 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4439 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4440 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4441 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4442 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4443 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4444 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4445 4446 /* Digital3 Block */ 4447 #define BCM5708S_DIG_3_0 0x10 4448 4449 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4450 4451 /* Tx/Misc Block */ 4452 #define BCM5708S_TX_ACTL1 0x15 4453 4454 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4455 4456 #define BCM5708S_TX_ACTL3 0x17 4457 4458 #define RX_COPY_THRESH 92 4459 4460 #define DMA_READ_CHANS 5 4461 #define DMA_WRITE_CHANS 3 4462 4463 /* Use the natural page size of the host CPU. */ 4464 /* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4465 #define BCM_PAGE_BITS PAGE_SHIFT 4466 #define BCM_PAGE_SIZE PAGE_SIZE 4467 4468 #define TX_PAGES 2 4469 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4470 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4471 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4472 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4473 #define MAX_TX_BD (TOTAL_TX_BD - 1) 4474 #define BCE_TX_SLACK_SPACE 16 4475 4476 #define RX_PAGES 2 4477 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4478 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4479 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4480 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4481 #define MAX_RX_BD (TOTAL_RX_BD - 1) 4482 #define BCE_RX_SLACK_SPACE (MAX_RX_BD - 8) 4483 4484 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4485 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4486 (x) + 2 : (x) + 1 4487 4488 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4489 4490 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) 4491 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4492 4493 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4494 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4495 (x) + 2 : (x) + 1 4496 4497 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4498 4499 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) 4500 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4501 4502 /* Context size. */ 4503 #define CTX_SHIFT 7 4504 #define CTX_SIZE (1 << CTX_SHIFT) 4505 #define CTX_MASK (CTX_SIZE - 1) 4506 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4507 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4508 4509 #define PHY_CTX_SHIFT 6 4510 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4511 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4512 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4513 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4514 4515 #define MB_KERNEL_CTX_SHIFT 8 4516 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4517 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4518 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4519 4520 #define MAX_CID_CNT 0x4000 4521 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4522 #define INVALID_CID_ADDR 0xffffffff 4523 4524 #define TX_CID 16 4525 #define RX_CID 0 4526 4527 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4528 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4529 4530 /****************************************************************************/ 4531 /* BCE Processor Firmwware Load Definitions */ 4532 /****************************************************************************/ 4533 4534 struct cpu_reg { 4535 u32 mode; 4536 u32 mode_value_halt; 4537 u32 mode_value_sstep; 4538 4539 u32 state; 4540 u32 state_value_clear; 4541 4542 u32 gpr0; 4543 u32 evmask; 4544 u32 pc; 4545 u32 inst; 4546 u32 bp; 4547 4548 u32 spad_base; 4549 4550 u32 mips_view_base; 4551 }; 4552 4553 struct fw_info { 4554 u32 ver_major; 4555 u32 ver_minor; 4556 u32 ver_fix; 4557 4558 u32 start_addr; 4559 4560 /* Text section. */ 4561 u32 text_addr; 4562 u32 text_len; 4563 u32 text_index; 4564 u32 *text; 4565 4566 /* Data section. */ 4567 u32 data_addr; 4568 u32 data_len; 4569 u32 data_index; 4570 u32 *data; 4571 4572 /* SBSS section. */ 4573 u32 sbss_addr; 4574 u32 sbss_len; 4575 u32 sbss_index; 4576 u32 *sbss; 4577 4578 /* BSS section. */ 4579 u32 bss_addr; 4580 u32 bss_len; 4581 u32 bss_index; 4582 u32 *bss; 4583 4584 /* Read-only section. */ 4585 u32 rodata_addr; 4586 u32 rodata_len; 4587 u32 rodata_index; 4588 u32 *rodata; 4589 }; 4590 4591 #define RV2P_PROC1 0 4592 #define RV2P_PROC2 1 4593 4594 #define BCE_MIREG(x) ((x & 0x1F) << 16) 4595 #define BCE_MIPHY(x) ((x & 0x1F) << 21) 4596 #define BCE_PHY_TIMEOUT 50 4597 4598 #define BCE_NVRAM_SIZE 0x200 4599 #define BCE_NVRAM_MAGIC 0x669955aa 4600 #define BCE_CRC32_RESIDUAL 0xdebb20e3 4601 4602 #define BCE_TX_TIMEOUT 5 4603 4604 #define BCE_MAX_SEGMENTS 8 4605 #define BCE_DMA_ALIGN 8 4606 #define BCE_DMA_BOUNDARY 0 4607 4608 /* The BCM5708 has a problem with addresses greater that 40bits. */ 4609 /* Handle the sizing issue in an architecture agnostic fashion. */ 4610 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 4611 #define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 4612 #else 4613 #define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 4614 #endif 4615 4616 /* 4617 * XXX Checksum offload involving IP fragments seems to cause problems on 4618 * transmit. Disable it for now, hopefully there will be a more elegant 4619 * solution later. 4620 */ 4621 #ifdef BCE_IP_CSUM 4622 #define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 4623 #else 4624 #define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) 4625 #endif 4626 4627 #if __FreeBSD_version < 700000 4628 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4629 IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 4630 #else 4631 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4632 IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) 4633 #endif 4634 4635 #define BCE_MIN_MTU 60 4636 #define BCE_MIN_ETHER_MTU 64 4637 4638 #define BCE_MAX_STD_MTU 1500 4639 #define BCE_MAX_STD_ETHER_MTU 1518 4640 #define BCE_MAX_STD_ETHER_MTU_VLAN 1522 4641 4642 #define BCE_MAX_JUMBO_MTU 9000 4643 #define BCE_MAX_JUMBO_ETHER_MTU 9018 4644 #define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 4645 4646 // #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ 4647 4648 /****************************************************************************/ 4649 /* BCE Device State Data Structure */ 4650 /****************************************************************************/ 4651 4652 #define BCE_STATUS_BLK_SZ sizeof(struct status_block) 4653 #define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 4654 #define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4655 #define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4656 4657 struct bce_softc 4658 { 4659 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */ 4660 struct ifnet *bce_ifp; /* Interface info */ 4661 device_t bce_dev; /* Parent device handle */ 4662 u_int8_t bce_unit; /* Interface number */ 4663 struct resource *bce_res; /* Device resource handle */ 4664 struct ifmedia bce_ifmedia; /* TBI media info */ 4665 bus_space_tag_t bce_btag; /* Device bus tag */ 4666 bus_space_handle_t bce_bhandle; /* Device bus handle */ 4667 vm_offset_t bce_vhandle; /* Device virtual memory handle */ 4668 struct resource *bce_irq; /* IRQ Resource Handle */ 4669 struct mtx bce_mtx; /* Mutex */ 4670 void *bce_intrhand; /* Interrupt handler */ 4671 4672 /* ASIC Chip ID. */ 4673 u32 bce_chipid; 4674 4675 /* General controller flags. */ 4676 u32 bce_flags; 4677 #define BCE_PCIX_FLAG 0x01 4678 #define BCE_PCI_32BIT_FLAG 0x02 4679 #define BCE_ONE_TDMA_FLAG 0x04 /* Deprecated */ 4680 #define BCE_NO_WOL_FLAG 0x08 4681 #define BCE_USING_DAC_FLAG 0x10 4682 #define BCE_USING_MSI_FLAG 0x20 4683 #define BCE_MFW_ENABLE_FLAG 0x40 4684 4685 /* PHY specific flags. */ 4686 u32 bce_phy_flags; 4687 #define BCE_PHY_SERDES_FLAG 1 4688 #define BCE_PHY_CRC_FIX_FLAG 2 4689 #define BCE_PHY_PARALLEL_DETECT_FLAG 4 4690 #define BCE_PHY_2_5G_CAPABLE_FLAG 8 4691 #define BCE_PHY_INT_MODE_MASK_FLAG 0x300 4692 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 4693 #define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x200 4694 4695 bus_addr_t max_bus_addr; 4696 u16 bus_speed_mhz; /* PCI bus speed */ 4697 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */ 4698 u32 bce_flash_size; /* Flash NVRAM size */ 4699 u32 bce_shmem_base; /* Shared Memory base address */ 4700 char * bce_name; /* Name string */ 4701 4702 /* Tracks the version of bootcode firmware. */ 4703 u32 bce_fw_ver; 4704 4705 /* Tracks the state of the firmware. 0 = Running while any */ 4706 /* other value indicates that the firmware is not responding. */ 4707 u16 bce_fw_timed_out; 4708 4709 /* An incrementing sequence used to coordinate messages passed */ 4710 /* from the driver to the firmware. */ 4711 u16 bce_fw_wr_seq; 4712 4713 /* An incrementing sequence used to let the firmware know that */ 4714 /* the driver is still operating. Without the pulse, management */ 4715 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4716 u16 bce_fw_drv_pulse_wr_seq; 4717 4718 /* Ethernet MAC address. */ 4719 u_char eaddr[6]; 4720 4721 /* These setting are used by the host coalescing (HC) block to */ 4722 /* to control how often the status block, statistics block and */ 4723 /* interrupts are generated. */ 4724 u16 bce_tx_quick_cons_trip_int; 4725 u16 bce_tx_quick_cons_trip; 4726 u16 bce_rx_quick_cons_trip_int; 4727 u16 bce_rx_quick_cons_trip; 4728 u16 bce_comp_prod_trip_int; 4729 u16 bce_comp_prod_trip; 4730 u16 bce_tx_ticks_int; 4731 u16 bce_tx_ticks; 4732 u16 bce_rx_ticks_int; 4733 u16 bce_rx_ticks; 4734 u16 bce_com_ticks_int; 4735 u16 bce_com_ticks; 4736 u16 bce_cmd_ticks_int; 4737 u16 bce_cmd_ticks; 4738 u32 bce_stats_ticks; 4739 4740 /* The address of the integrated PHY on the MII bus. */ 4741 int bce_phy_addr; 4742 4743 /* The device handle for the MII bus child device. */ 4744 device_t bce_miibus; 4745 4746 /* Driver maintained TX chain pointers and byte counter. */ 4747 u16 rx_prod; 4748 u16 rx_cons; 4749 u32 rx_prod_bseq; /* Counts the bytes used. */ 4750 u16 tx_prod; 4751 u16 tx_cons; 4752 u32 tx_prod_bseq; /* Counts the bytes used. */ 4753 4754 int bce_link; 4755 struct callout bce_stat_ch; 4756 4757 /* Frame size and mbuf allocation size for RX frames. */ 4758 u32 max_frame_size; 4759 int mbuf_alloc_size; 4760 4761 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4762 u32 rx_mode; 4763 4764 #ifdef DEVICE_POLLING 4765 int bce_rxcycles; /* Counter for receive polling cycles */ 4766 #endif 4767 4768 /* Bus tag for the bce controller. */ 4769 bus_dma_tag_t parent_tag; 4770 4771 /* H/W maintained TX buffer descriptor chain structure. */ 4772 bus_dma_tag_t tx_bd_chain_tag; 4773 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4774 struct tx_bd *tx_bd_chain[TX_PAGES]; 4775 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4776 4777 /* H/W maintained RX buffer descriptor chain structure. */ 4778 bus_dma_tag_t rx_bd_chain_tag; 4779 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4780 struct rx_bd *rx_bd_chain[RX_PAGES]; 4781 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4782 4783 /* H/W maintained status block. */ 4784 bus_dma_tag_t status_tag; 4785 bus_dmamap_t status_map; 4786 struct status_block *status_block; /* virtual address */ 4787 bus_addr_t status_block_paddr; /* Physical address */ 4788 4789 /* Driver maintained status block values. */ 4790 u16 last_status_idx; 4791 u16 hw_rx_cons; 4792 u16 hw_tx_cons; 4793 4794 /* H/W maintained statistics block. */ 4795 bus_dma_tag_t stats_tag; 4796 bus_dmamap_t stats_map; 4797 struct statistics_block *stats_block; /* Virtual address */ 4798 bus_addr_t stats_block_paddr; /* Physical address */ 4799 4800 /* Bus tag for RX/TX mbufs. */ 4801 bus_dma_tag_t rx_mbuf_tag; 4802 bus_dma_tag_t tx_mbuf_tag; 4803 4804 /* S/W maintained mbuf TX chain structure. */ 4805 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4806 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4807 4808 /* S/W maintained mbuf RX chain structure. */ 4809 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4810 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4811 4812 /* Track the number of rx_bd and tx_bd's in use. */ 4813 u16 free_rx_bd; 4814 u16 used_tx_bd; 4815 4816 /* Provides access to hardware statistics through sysctl. */ 4817 u64 stat_IfHCInOctets; 4818 u64 stat_IfHCInBadOctets; 4819 u64 stat_IfHCOutOctets; 4820 u64 stat_IfHCOutBadOctets; 4821 u64 stat_IfHCInUcastPkts; 4822 u64 stat_IfHCInMulticastPkts; 4823 u64 stat_IfHCInBroadcastPkts; 4824 u64 stat_IfHCOutUcastPkts; 4825 u64 stat_IfHCOutMulticastPkts; 4826 u64 stat_IfHCOutBroadcastPkts; 4827 4828 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4829 u32 stat_Dot3StatsCarrierSenseErrors; 4830 u32 stat_Dot3StatsFCSErrors; 4831 u32 stat_Dot3StatsAlignmentErrors; 4832 u32 stat_Dot3StatsSingleCollisionFrames; 4833 u32 stat_Dot3StatsMultipleCollisionFrames; 4834 u32 stat_Dot3StatsDeferredTransmissions; 4835 u32 stat_Dot3StatsExcessiveCollisions; 4836 u32 stat_Dot3StatsLateCollisions; 4837 u32 stat_EtherStatsCollisions; 4838 u32 stat_EtherStatsFragments; 4839 u32 stat_EtherStatsJabbers; 4840 u32 stat_EtherStatsUndersizePkts; 4841 u32 stat_EtherStatsOverrsizePkts; 4842 u32 stat_EtherStatsPktsRx64Octets; 4843 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 4844 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 4845 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 4846 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 4847 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 4848 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 4849 u32 stat_EtherStatsPktsTx64Octets; 4850 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 4851 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 4852 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 4853 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 4854 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 4855 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 4856 u32 stat_XonPauseFramesReceived; 4857 u32 stat_XoffPauseFramesReceived; 4858 u32 stat_OutXonSent; 4859 u32 stat_OutXoffSent; 4860 u32 stat_FlowControlDone; 4861 u32 stat_MacControlFramesReceived; 4862 u32 stat_XoffStateEntered; 4863 u32 stat_IfInFramesL2FilterDiscards; 4864 u32 stat_IfInRuleCheckerDiscards; 4865 u32 stat_IfInFTQDiscards; 4866 u32 stat_IfInMBUFDiscards; 4867 u32 stat_IfInRuleCheckerP4Hit; 4868 u32 stat_CatchupInRuleCheckerDiscards; 4869 u32 stat_CatchupInFTQDiscards; 4870 u32 stat_CatchupInMBUFDiscards; 4871 u32 stat_CatchupInRuleCheckerP4Hit; 4872 4873 #ifdef BCE_DEBUG 4874 /* Track the number of enqueued mbufs. */ 4875 int tx_mbuf_alloc; 4876 int rx_mbuf_alloc; 4877 4878 /* Track how many and what type of interrupts are generated. */ 4879 u32 interrupts_generated; 4880 u32 interrupts_handled; 4881 u32 rx_interrupts; 4882 u32 tx_interrupts; 4883 4884 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */ 4885 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */ 4886 u32 mbuf_alloc_failed; /* Mbuf allocation failure counter. */ 4887 u32 l2fhdr_status_errors; 4888 u32 unexpected_attentions; 4889 u32 lost_status_block_updates; 4890 #endif 4891 }; 4892 4893 #endif /* #ifndef _BCE_H_DEFINED */ 4894