1 /*- 2 * Copyright (c) 2006-2008 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written consent. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BCE_H_DEFINED 33 #define _BCE_H_DEFINED 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/queue.h> 46 47 #include <net/bpf.h> 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 #include <netinet/ip.h> 61 #include <netinet/ip6.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 65 #include <machine/bus.h> 66 #include <machine/resource.h> 67 #include <sys/bus.h> 68 #include <sys/rman.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include "miidevs.h" 73 #include <dev/mii/brgphyreg.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 78 #include "miibus_if.h" 79 80 /****************************************************************************/ 81 /* Conversion to FreeBSD type definitions. */ 82 /****************************************************************************/ 83 #define u64 uint64_t 84 #define u32 uint32_t 85 #define u16 uint16_t 86 #define u8 uint8_t 87 88 #if BYTE_ORDER == BIG_ENDIAN 89 #define __BIG_ENDIAN 1 90 #undef __LITTLE_ENDIAN 91 #else 92 #undef __BIG_ENDIAN 93 #define __LITTLE_ENDIAN 1 94 #endif 95 96 #define BCE_DWORD_PRINTFB \ 97 "\020" \ 98 "\40b31" \ 99 "\37b30" \ 100 "\36b29" \ 101 "\35b28" \ 102 "\34b27" \ 103 "\33b26" \ 104 "\32b25" \ 105 "\31b24" \ 106 "\30b23" \ 107 "\27b22" \ 108 "\26b21" \ 109 "\25b20" \ 110 "\24b19" \ 111 "\23b18" \ 112 "\22b17" \ 113 "\21b16" \ 114 "\20b15" \ 115 "\17b14" \ 116 "\16b13" \ 117 "\15b12" \ 118 "\14b11" \ 119 "\13b10" \ 120 "\12b9" \ 121 "\11b8" \ 122 "\10b7" \ 123 "\07b6" \ 124 "\06b5" \ 125 "\05b4" \ 126 "\04b3" \ 127 "\03b2" \ 128 "\02b1" \ 129 "\01b0" 130 131 132 /****************************************************************************/ 133 /* Debugging macros and definitions. */ 134 /****************************************************************************/ 135 #define BCE_CP_LOAD 0x00000001 136 #define BCE_CP_SEND 0x00000002 137 #define BCE_CP_RECV 0x00000004 138 #define BCE_CP_INTR 0x00000008 139 #define BCE_CP_UNLOAD 0x00000010 140 #define BCE_CP_RESET 0x00000020 141 #define BCE_CP_PHY 0x00000040 142 #define BCE_CP_NVRAM 0x00000080 143 #define BCE_CP_FIRMWARE 0x00000100 144 #define BCE_CP_MISC 0x00400000 145 #define BCE_CP_SPECIAL 0x00800000 146 #define BCE_CP_ALL 0x00FFFFFF 147 148 #define BCE_CP_MASK 0x00FFFFFF 149 150 #define BCE_LEVEL_FATAL 0x00000000 151 #define BCE_LEVEL_WARN 0x01000000 152 #define BCE_LEVEL_INFO 0x02000000 153 #define BCE_LEVEL_VERBOSE 0x03000000 154 #define BCE_LEVEL_EXCESSIVE 0x04000000 155 156 #define BCE_LEVEL_MASK 0xFF000000 157 158 #define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 159 #define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 160 #define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 161 #define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE) 162 163 #define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 164 #define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 165 #define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 166 #define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE) 167 168 #define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 169 #define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 170 #define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 171 #define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE) 172 173 #define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 174 #define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 175 #define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 176 #define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE) 177 178 #define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 179 #define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 180 #define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 181 #define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE) 182 183 #define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 184 #define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 185 #define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 186 #define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE) 187 188 #define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN) 189 #define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO) 190 #define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE) 191 #define BCE_EXCESSIVE_PHY (BCE_CP_PHY | BCE_LEVEL_EXCESSIVE) 192 193 #define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN) 194 #define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO) 195 #define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE) 196 #define BCE_EXCESSIVE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXCESSIVE) 197 198 #define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN) 199 #define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO) 200 #define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE) 201 #define BCE_EXCESSIVE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXCESSIVE) 202 203 #define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN) 204 #define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO) 205 #define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE) 206 #define BCE_EXCESSIVE_MISC (BCE_CP_MISC | BCE_LEVEL_EXCESSIVE) 207 208 #define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN) 209 #define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO) 210 #define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE) 211 #define BCE_EXCESSIVE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXCESSIVE) 212 213 #define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 214 #define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 215 #define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 216 #define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 217 #define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE) 218 219 #define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 220 #define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 221 #define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 222 223 #ifdef BCE_DEBUG 224 225 /* 226 * Calculate the time delta between two reads 227 * of the 25MHz free running clock. 228 */ 229 #define BCE_TIME_DELTA(start, end) (start > end ? (start - end) : \ 230 (~start + end + 1)) 231 232 /* Print a message based on the logging level and code path. */ 233 #define DBPRINT(sc, level, format, args...) \ 234 if (BCE_LOG_MSG(level)) { \ 235 device_printf(sc->bce_dev, format, ## args); \ 236 } 237 238 /* Runs a particular command when debugging is enabled. */ 239 #define DBRUN(args...) \ 240 do { \ 241 args; \ 242 } while (0) 243 244 /* Runs a particular command based on the logging level and code path. */ 245 #define DBRUNMSG(msg, args...) \ 246 if (BCE_LOG_MSG(msg)) { \ 247 args; \ 248 } 249 250 /* Runs a particular command based on the logging level. */ 251 #define DBRUNLV(level, args...) \ 252 if (BCE_MSG_LEVEL(level)) { \ 253 args; \ 254 } 255 256 /* Runs a particular command based on the code path. */ 257 #define DBRUNCP(cp, args...) \ 258 if (BCE_CODE_PATH(cp)) { \ 259 args; \ 260 } 261 262 /* Runs a particular command based on a condition. */ 263 #define DBRUNIF(cond, args...) \ 264 if (cond) { \ 265 args; \ 266 } 267 268 /* Needed for random() function which is only used in debugging. */ 269 #include <sys/random.h> 270 271 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 272 #define DB_RANDOMFALSE(defects) (random() > defects) 273 #define DB_OR_RANDOMFALSE(defects) || (random() > defects) 274 #define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 275 276 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 277 #define DB_RANDOMTRUE(defects) (random() < defects) 278 #define DB_OR_RANDOMTRUE(defects) || (random() < defects) 279 #define DB_AND_RANDOMTRUE(defects) && (random() < defects) 280 281 #else 282 283 #define DBPRINT(level, format, args...) 284 #define DBRUN(args...) 285 #define DBRUNMSG(msg, args...) 286 #define DBRUNLV(level, args...) 287 #define DBRUNCP(cp, args...) 288 #define DBRUNIF(cond, args...) 289 #define DB_RANDOMFALSE(defects) 290 #define DB_OR_RANDOMFALSE(percent) 291 #define DB_AND_RANDOMFALSE(percent) 292 #define DB_RANDOMTRUE(defects) 293 #define DB_OR_RANDOMTRUE(percent) 294 #define DB_AND_RANDOMTRUE(percent) 295 296 #endif /* BCE_DEBUG */ 297 298 299 /****************************************************************************/ 300 /* Device identification definitions. */ 301 /****************************************************************************/ 302 #define BRCM_VENDORID 0x14E4 303 #define BRCM_DEVICEID_BCM5706 0x164A 304 #define BRCM_DEVICEID_BCM5706S 0x16AA 305 #define BRCM_DEVICEID_BCM5708 0x164C 306 #define BRCM_DEVICEID_BCM5708S 0x16AC 307 308 #define HP_VENDORID 0x103C 309 310 #define PCI_ANY_ID (u_int16_t) (~0U) 311 312 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 313 314 #define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 315 #define BCE_CHIP_NUM_5706 0x57060000 316 #define BCE_CHIP_NUM_5708 0x57080000 317 318 #define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 319 #define BCE_CHIP_REV_Ax 0x00000000 320 #define BCE_CHIP_REV_Bx 0x00001000 321 #define BCE_CHIP_REV_Cx 0x00002000 322 323 #define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 324 #define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 325 326 #define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 327 #define BCE_CHIP_ID_5706_A0 0x57060000 328 #define BCE_CHIP_ID_5706_A1 0x57060010 329 #define BCE_CHIP_ID_5706_A2 0x57060020 330 #define BCE_CHIP_ID_5706_A3 0x57060030 331 #define BCE_CHIP_ID_5708_A0 0x57080000 332 #define BCE_CHIP_ID_5708_B0 0x57081000 333 #define BCE_CHIP_ID_5708_B1 0x57081010 334 #define BCE_CHIP_ID_5708_B2 0x57081020 335 336 #define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 337 338 /* A serdes chip will have the first bit of the bond id set. */ 339 #define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 340 341 342 /* shorthand one */ 343 #define BCE_ASICREV(x) ((x) >> 28) 344 #define BCE_ASICREV_BCM5700 0x06 345 346 /* chip revisions */ 347 #define BCE_CHIPREV(x) ((x) >> 24) 348 #define BCE_CHIPREV_5700_AX 0x70 349 #define BCE_CHIPREV_5700_BX 0x71 350 #define BCE_CHIPREV_5700_CX 0x72 351 #define BCE_CHIPREV_5701_AX 0x00 352 353 struct bce_type { 354 u_int16_t bce_vid; 355 u_int16_t bce_did; 356 u_int16_t bce_svid; 357 u_int16_t bce_sdid; 358 char *bce_name; 359 }; 360 361 /****************************************************************************/ 362 /* Byte order conversions. */ 363 /****************************************************************************/ 364 #if __FreeBSD_version >= 500000 365 #define bce_htobe16(x) htobe16(x) 366 #define bce_htobe32(x) htobe32(x) 367 #define bce_htobe64(x) htobe64(x) 368 #define bce_htole16(x) htole16(x) 369 #define bce_htole32(x) htole32(x) 370 #define bce_htole64(x) htole64(x) 371 372 #define bce_be16toh(x) be16toh(x) 373 #define bce_be32toh(x) be32toh(x) 374 #define bce_be64toh(x) be64toh(x) 375 #define bce_le16toh(x) le16toh(x) 376 #define bce_le32toh(x) le32toh(x) 377 #define bce_le64toh(x) le64toh(x) 378 #else 379 #define bce_htobe16(x) (x) 380 #define bce_htobe32(x) (x) 381 #define bce_htobe64(x) (x) 382 #define bce_htole16(x) (x) 383 #define bce_htole32(x) (x) 384 #define bce_htole64(x) (x) 385 386 #define bce_be16toh(x) (x) 387 #define bce_be32toh(x) (x) 388 #define bce_be64toh(x) (x) 389 #define bce_le16toh(x) (x) 390 #define bce_le32toh(x) (x) 391 #define bce_le64toh(x) (x) 392 #endif 393 394 395 /****************************************************************************/ 396 /* NVRAM Access */ 397 /****************************************************************************/ 398 399 /* Buffered flash (Atmel: AT45DB011B) specific information */ 400 #define SEEPROM_PAGE_BITS 2 401 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 402 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 403 #define SEEPROM_PAGE_SIZE 4 404 #define SEEPROM_TOTAL_SIZE 65536 405 406 #define BUFFERED_FLASH_PAGE_BITS 9 407 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 408 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 409 #define BUFFERED_FLASH_PAGE_SIZE 264 410 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 411 412 #define SAIFUN_FLASH_PAGE_BITS 8 413 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 414 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 415 #define SAIFUN_FLASH_PAGE_SIZE 256 416 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 417 418 #define ST_MICRO_FLASH_PAGE_BITS 8 419 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 420 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 421 #define ST_MICRO_FLASH_PAGE_SIZE 256 422 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 423 424 #define NVRAM_TIMEOUT_COUNT 30000 425 #define BCE_FLASHDESC_MAX 64 426 427 #define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 428 BCE_NVM_CFG1_BUFFER_MODE | \ 429 BCE_NVM_CFG1_PROTECT_MODE | \ 430 BCE_NVM_CFG1_FLASH_SIZE) 431 432 #define FLASH_BACKUP_STRAP_MASK (0xf << 26) 433 434 struct flash_spec { 435 u32 strapping; 436 u32 config1; 437 u32 config2; 438 u32 config3; 439 u32 write1; 440 u32 buffered; 441 u32 page_bits; 442 u32 page_size; 443 u32 addr_mask; 444 u32 total_size; 445 u8 *name; 446 }; 447 448 449 /****************************************************************************/ 450 /* Shared Memory layout */ 451 /* The BCE bootcode will initialize this data area with port configurtion */ 452 /* information which can be accessed by the driver. */ 453 /****************************************************************************/ 454 455 /* 456 * This value (in milliseconds) determines the frequency of the driver 457 * issuing the PULSE message code. The firmware monitors this periodic 458 * pulse to determine when to switch to an OS-absent mode. 459 */ 460 #define DRV_PULSE_PERIOD_MS 250 461 462 /* 463 * This value (in milliseconds) determines how long the driver should 464 * wait for an acknowledgement from the firmware before timing out. Once 465 * the firmware has timed out, the driver will assume there is no firmware 466 * running and there won't be any firmware-driver synchronization during a 467 * driver reset. 468 */ 469 #define FW_ACK_TIME_OUT_MS 100 470 471 472 #define BCE_DRV_RESET_SIGNATURE 0x00000000 473 #define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 474 475 #define BCE_DRV_MB 0x00000004 476 #define BCE_DRV_MSG_CODE 0xff000000 477 #define BCE_DRV_MSG_CODE_RESET 0x01000000 478 #define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 479 #define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 480 #define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 481 #define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 482 #define BCE_DRV_MSG_CODE_PULSE 0x06000000 483 #define BCE_DRV_MSG_CODE_DIAG 0x07000000 484 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 485 #define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 486 #define BCE_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 487 488 #define BCE_DRV_MSG_DATA 0x00ff0000 489 #define BCE_DRV_MSG_DATA_WAIT0 0x00010000 490 #define BCE_DRV_MSG_DATA_WAIT1 0x00020000 491 #define BCE_DRV_MSG_DATA_WAIT2 0x00030000 492 #define BCE_DRV_MSG_DATA_WAIT3 0x00040000 493 494 #define BCE_DRV_MSG_SEQ 0x0000ffff 495 496 #define BCE_FW_MB 0x00000008 497 #define BCE_FW_MSG_ACK 0x0000ffff 498 #define BCE_FW_MSG_STATUS_MASK 0x00ff0000 499 #define BCE_FW_MSG_STATUS_OK 0x00000000 500 #define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 501 502 #define BCE_LINK_STATUS 0x0000000c 503 #define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 504 #define BCE_LINK_STATUS_LINK_UP 0x1 505 #define BCE_LINK_STATUS_LINK_DOWN 0x0 506 #define BCE_LINK_STATUS_SPEED_MASK 0x1e 507 #define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 508 #define BCE_LINK_STATUS_10HALF (1<<1) 509 #define BCE_LINK_STATUS_10FULL (2<<1) 510 #define BCE_LINK_STATUS_100HALF (3<<1) 511 #define BCE_LINK_STATUS_100BASE_T4 (4<<1) 512 #define BCE_LINK_STATUS_100FULL (5<<1) 513 #define BCE_LINK_STATUS_1000HALF (6<<1) 514 #define BCE_LINK_STATUS_1000FULL (7<<1) 515 #define BCE_LINK_STATUS_2500HALF (8<<1) 516 #define BCE_LINK_STATUS_2500FULL (9<<1) 517 #define BCE_LINK_STATUS_AN_ENABLED (1<<5) 518 #define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 519 #define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 520 #define BCE_LINK_STATUS_RESERVED (1<<8) 521 #define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 522 #define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 523 #define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 524 #define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 525 #define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 526 #define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 527 #define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 528 #define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 529 #define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 530 #define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 531 #define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 532 #define BCE_LINK_STATUS_SERDES_LINK (1<<20) 533 #define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 534 #define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 535 536 #define BCE_DRV_PULSE_MB 0x00000010 537 #define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 538 539 #define BCE_MB_ARGS_0 0x00000014 540 #define BCE_MB_ARGS_1 0x00000018 541 542 /* Indicate to the firmware not to go into the 543 * OS absent when it is not getting driver pulse. 544 * This is used for debugging. */ 545 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 546 547 #define BCE_DEV_INFO_SIGNATURE 0x00000020 548 #define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 549 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 550 #define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 551 #define BCE_DEV_INFO_SECONDARY_PORT 0x80 552 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 553 554 #define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 555 556 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 557 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 558 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 559 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 560 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 561 562 #define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 563 #define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 564 #define BCE_SHARED_HW_CFG_DESIGN_NIC 0 565 #define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 566 #define BCE_SHARED_HW_CFG_PHY_COPPER 0 567 #define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 568 #define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 569 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 570 #define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 571 #define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 572 #define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 573 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 574 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 575 576 #define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 577 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 578 579 #define BCE_DEV_INFO_BC_REV 0x0000004c 580 581 #define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 582 #define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 583 584 #define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 585 #define BCE_PORT_HW_CFG_CONFIG 0x00000058 586 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 587 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 588 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 589 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 590 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 591 592 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 593 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 594 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 595 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 596 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 597 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 598 599 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 600 601 #define BCE_DEV_INFO_FORMAT_REV 0x000000c4 602 #define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 603 #define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 604 605 #define BCE_SHARED_FEATURE 0x000000c8 606 #define BCE_SHARED_FEATURE_MASK 0xffffffff 607 608 #define BCE_PORT_FEATURE 0x000000d8 609 #define BCE_PORT2_FEATURE 0x00000014c 610 #define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 611 #define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 612 #define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 613 #define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 614 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 615 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 616 #define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 617 #define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 618 #define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 619 #define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 620 #define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 621 #define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 622 #define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 623 #define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 624 #define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 625 #define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 626 #define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 627 #define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 628 #define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 629 #define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 630 #define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 631 632 #define BCE_PORT_FEATURE_WOL 0xdc 633 #define BCE_PORT2_FEATURE_WOL 0x150 634 #define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 635 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 636 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 637 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 638 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 639 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 640 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 641 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 642 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 643 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 644 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 645 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 646 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 647 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 648 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 649 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 650 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 651 652 #define BCE_PORT_FEATURE_MBA 0xe0 653 #define BCE_PORT2_FEATURE_MBA 0x154 654 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 655 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 656 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 657 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 658 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 659 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 660 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 661 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 662 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 663 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 664 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 665 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 666 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 667 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 668 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 669 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 670 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 671 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 672 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 673 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 674 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 675 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 676 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 677 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 678 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 679 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 680 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 681 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 682 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 683 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 684 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 685 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 686 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 687 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 688 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 689 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 690 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 691 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 692 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 693 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 694 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 695 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 696 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 697 698 #define BCE_PORT_FEATURE_IMD 0xe4 699 #define BCE_PORT2_FEATURE_IMD 0x158 700 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 701 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 702 703 #define BCE_PORT_FEATURE_VLAN 0xe8 704 #define BCE_PORT2_FEATURE_VLAN 0x15c 705 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 706 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 707 708 #define BCE_BC_STATE_RESET_TYPE 0x000001c0 709 #define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 710 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 711 #define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ 712 0x00010000) 713 #define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ 714 0x00020000) 715 #define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ 716 0x00030000) 717 #define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 718 #define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ 719 DRV_MSG_CODE_RESET) 720 #define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ 721 DRV_MSG_CODE_UNLOAD) 722 #define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ 723 DRV_MSG_CODE_SHUTDOWN) 724 #define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ 725 DRV_MSG_CODE_WOL) 726 #define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ 727 DRV_MSG_CODE_DIAG) 728 #define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ 729 (msg)) 730 731 #define BCE_BC_RESET_TYPE 0x000001c0 732 733 #define BCE_BC_STATE 0x000001c4 734 #define BCE_BC_STATE_ERR_MASK 0x0000ff00 735 #define BCE_BC_STATE_SIGN 0x42530000 736 #define BCE_BC_STATE_SIGN_MASK 0xffff0000 737 #define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 738 #define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 739 #define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 740 #define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 741 #define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 742 #define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 743 #define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 744 #define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 745 #define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 746 #define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 747 #define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 748 #define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 749 #define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 750 #define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 751 #define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 752 #define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 753 #define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 754 #define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 755 #define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 756 #define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 757 #define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 758 #define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 759 #define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 760 #define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 761 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 762 763 #define BCE_BC_CONDITION 0x000001c8 764 765 #define BCE_BC_STATE_DEBUG_CMD 0x1dc 766 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 767 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 768 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 769 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 770 771 #define HOST_VIEW_SHMEM_BASE 0x167c00 772 773 /* 774 * PCI registers defined in the PCI 2.2 spec. 775 */ 776 #define BCE_PCI_PCIX_CMD 0x42 777 778 779 /****************************************************************************/ 780 /* Convenience definitions. */ 781 /****************************************************************************/ 782 #define BCE_PRINTF(fmt, args...) device_printf(sc->bce_dev, fmt, ##args) 783 784 #define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 785 #define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 786 #define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 787 #define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 788 #define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 789 790 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) 791 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) 792 #define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) 793 #define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 794 #define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 795 #define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val) 796 #define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset) 797 #define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 798 #define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 799 #define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 800 #define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 801 802 #define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 803 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 804 #define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 805 #define BCE_ADDR_HI(y) ((u64) (y) >> 32) 806 #else 807 #define BCE_ADDR_LO(y) ((u32)y) 808 #define BCE_ADDR_HI(y) (0) 809 #endif 810 811 812 /* 813 * The following data structures are generated from RTL code. 814 * Do not modify any values below this line. 815 */ 816 817 /****************************************************************************/ 818 /* Do not modify any of the following data structures, they are generated */ 819 /* from RTL code. */ 820 /* */ 821 /* Begin machine generated definitions. */ 822 /****************************************************************************/ 823 824 /* 825 * tx_bd definition 826 */ 827 struct tx_bd { 828 u32 tx_bd_haddr_hi; 829 u32 tx_bd_haddr_lo; 830 u32 tx_bd_mss_nbytes; 831 u16 tx_bd_flags; 832 u16 tx_bd_vlan_tag; 833 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 834 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 835 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 836 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 837 #define TX_BD_FLAGS_COAL_NOW (1<<4) 838 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 839 #define TX_BD_FLAGS_END (1<<6) 840 #define TX_BD_FLAGS_START (1<<7) 841 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 842 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 843 #define TX_BD_FLAGS_SW_SNAP (1<<14) 844 #define TX_BD_FLAGS_SW_LSO (1<<15) 845 846 }; 847 848 849 /* 850 * rx_bd definition 851 */ 852 struct rx_bd { 853 u32 rx_bd_haddr_hi; 854 u32 rx_bd_haddr_lo; 855 u32 rx_bd_len; 856 u32 rx_bd_flags; 857 #define RX_BD_FLAGS_NOPUSH (1<<0) 858 #define RX_BD_FLAGS_DUMMY (1<<1) 859 #define RX_BD_FLAGS_END (1<<2) 860 #define RX_BD_FLAGS_START (1<<3) 861 862 }; 863 864 865 /* 866 * status_block definition 867 */ 868 struct status_block { 869 u32 status_attn_bits; 870 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 871 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 872 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 873 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 874 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 875 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 876 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 877 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 878 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 879 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 880 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 881 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 882 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 883 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 884 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 885 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 886 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 887 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 888 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 889 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 890 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 891 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 892 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 893 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 894 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 895 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 896 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 897 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 898 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 899 900 u32 status_attn_bits_ack; 901 #if defined(__BIG_ENDIAN) 902 u16 status_tx_quick_consumer_index0; 903 u16 status_tx_quick_consumer_index1; 904 u16 status_tx_quick_consumer_index2; 905 u16 status_tx_quick_consumer_index3; 906 u16 status_rx_quick_consumer_index0; 907 u16 status_rx_quick_consumer_index1; 908 u16 status_rx_quick_consumer_index2; 909 u16 status_rx_quick_consumer_index3; 910 u16 status_rx_quick_consumer_index4; 911 u16 status_rx_quick_consumer_index5; 912 u16 status_rx_quick_consumer_index6; 913 u16 status_rx_quick_consumer_index7; 914 u16 status_rx_quick_consumer_index8; 915 u16 status_rx_quick_consumer_index9; 916 u16 status_rx_quick_consumer_index10; 917 u16 status_rx_quick_consumer_index11; 918 u16 status_rx_quick_consumer_index12; 919 u16 status_rx_quick_consumer_index13; 920 u16 status_rx_quick_consumer_index14; 921 u16 status_rx_quick_consumer_index15; 922 u16 status_completion_producer_index; 923 u16 status_cmd_consumer_index; 924 u16 status_idx; 925 u16 status_unused; 926 #elif defined(__LITTLE_ENDIAN) 927 u16 status_tx_quick_consumer_index1; 928 u16 status_tx_quick_consumer_index0; 929 u16 status_tx_quick_consumer_index3; 930 u16 status_tx_quick_consumer_index2; 931 u16 status_rx_quick_consumer_index1; 932 u16 status_rx_quick_consumer_index0; 933 u16 status_rx_quick_consumer_index3; 934 u16 status_rx_quick_consumer_index2; 935 u16 status_rx_quick_consumer_index5; 936 u16 status_rx_quick_consumer_index4; 937 u16 status_rx_quick_consumer_index7; 938 u16 status_rx_quick_consumer_index6; 939 u16 status_rx_quick_consumer_index9; 940 u16 status_rx_quick_consumer_index8; 941 u16 status_rx_quick_consumer_index11; 942 u16 status_rx_quick_consumer_index10; 943 u16 status_rx_quick_consumer_index13; 944 u16 status_rx_quick_consumer_index12; 945 u16 status_rx_quick_consumer_index15; 946 u16 status_rx_quick_consumer_index14; 947 u16 status_cmd_consumer_index; 948 u16 status_completion_producer_index; 949 u16 status_unused; 950 u16 status_idx; 951 #endif 952 }; 953 954 955 /* 956 * statistics_block definition 957 */ 958 struct statistics_block { 959 u32 stat_IfHCInOctets_hi; 960 u32 stat_IfHCInOctets_lo; 961 u32 stat_IfHCInBadOctets_hi; 962 u32 stat_IfHCInBadOctets_lo; 963 u32 stat_IfHCOutOctets_hi; 964 u32 stat_IfHCOutOctets_lo; 965 u32 stat_IfHCOutBadOctets_hi; 966 u32 stat_IfHCOutBadOctets_lo; 967 u32 stat_IfHCInUcastPkts_hi; 968 u32 stat_IfHCInUcastPkts_lo; 969 u32 stat_IfHCInMulticastPkts_hi; 970 u32 stat_IfHCInMulticastPkts_lo; 971 u32 stat_IfHCInBroadcastPkts_hi; 972 u32 stat_IfHCInBroadcastPkts_lo; 973 u32 stat_IfHCOutUcastPkts_hi; 974 u32 stat_IfHCOutUcastPkts_lo; 975 u32 stat_IfHCOutMulticastPkts_hi; 976 u32 stat_IfHCOutMulticastPkts_lo; 977 u32 stat_IfHCOutBroadcastPkts_hi; 978 u32 stat_IfHCOutBroadcastPkts_lo; 979 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 980 u32 stat_Dot3StatsCarrierSenseErrors; 981 u32 stat_Dot3StatsFCSErrors; 982 u32 stat_Dot3StatsAlignmentErrors; 983 u32 stat_Dot3StatsSingleCollisionFrames; 984 u32 stat_Dot3StatsMultipleCollisionFrames; 985 u32 stat_Dot3StatsDeferredTransmissions; 986 u32 stat_Dot3StatsExcessiveCollisions; 987 u32 stat_Dot3StatsLateCollisions; 988 u32 stat_EtherStatsCollisions; 989 u32 stat_EtherStatsFragments; 990 u32 stat_EtherStatsJabbers; 991 u32 stat_EtherStatsUndersizePkts; 992 u32 stat_EtherStatsOverrsizePkts; 993 u32 stat_EtherStatsPktsRx64Octets; 994 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 995 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 996 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 997 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 998 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 999 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 1000 u32 stat_EtherStatsPktsTx64Octets; 1001 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 1002 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 1003 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 1004 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 1005 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 1006 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 1007 u32 stat_XonPauseFramesReceived; 1008 u32 stat_XoffPauseFramesReceived; 1009 u32 stat_OutXonSent; 1010 u32 stat_OutXoffSent; 1011 u32 stat_FlowControlDone; 1012 u32 stat_MacControlFramesReceived; 1013 u32 stat_XoffStateEntered; 1014 u32 stat_IfInFramesL2FilterDiscards; 1015 u32 stat_IfInRuleCheckerDiscards; 1016 u32 stat_IfInFTQDiscards; 1017 u32 stat_IfInMBUFDiscards; 1018 u32 stat_IfInRuleCheckerP4Hit; 1019 u32 stat_CatchupInRuleCheckerDiscards; 1020 u32 stat_CatchupInFTQDiscards; 1021 u32 stat_CatchupInMBUFDiscards; 1022 u32 stat_CatchupInRuleCheckerP4Hit; 1023 u32 stat_GenStat00; 1024 u32 stat_GenStat01; 1025 u32 stat_GenStat02; 1026 u32 stat_GenStat03; 1027 u32 stat_GenStat04; 1028 u32 stat_GenStat05; 1029 u32 stat_GenStat06; 1030 u32 stat_GenStat07; 1031 u32 stat_GenStat08; 1032 u32 stat_GenStat09; 1033 u32 stat_GenStat10; 1034 u32 stat_GenStat11; 1035 u32 stat_GenStat12; 1036 u32 stat_GenStat13; 1037 u32 stat_GenStat14; 1038 u32 stat_GenStat15; 1039 }; 1040 1041 1042 /* 1043 * l2_fhdr definition 1044 */ 1045 struct l2_fhdr { 1046 u32 l2_fhdr_status; 1047 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 1048 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 1049 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 1050 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 1051 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 1052 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 1053 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 1054 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 1055 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 1056 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 1057 1058 #define L2_FHDR_STATUS_SPLIT (1<<16) 1059 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 1060 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 1061 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 1062 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 1063 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 1064 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 1065 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 1066 1067 u32 l2_fhdr_hash; 1068 #if defined(__BIG_ENDIAN) 1069 u16 l2_fhdr_pkt_len; 1070 u16 l2_fhdr_vlan_tag; 1071 u16 l2_fhdr_ip_xsum; 1072 u16 l2_fhdr_tcp_udp_xsum; 1073 #elif defined(__LITTLE_ENDIAN) 1074 u16 l2_fhdr_vlan_tag; 1075 u16 l2_fhdr_pkt_len; 1076 u16 l2_fhdr_tcp_udp_xsum; 1077 u16 l2_fhdr_ip_xsum; 1078 #endif 1079 }; 1080 1081 #define BCE_L2FHDR_PRINTFB \ 1082 "\20" \ 1083 "\40UDP_XSUM_ERR" \ 1084 "\37b30" \ 1085 "\36b29" \ 1086 "\35TCP_XSUM_ERR" \ 1087 "\34b27" \ 1088 "\33b26" \ 1089 "\32b25" \ 1090 "\31b24" \ 1091 "\30b23" \ 1092 "\27b22" \ 1093 "\26GIANT_ERR" \ 1094 "\25SHORT_ERR" \ 1095 "\24ALIGN_ERR" \ 1096 "\23PHY_ERR" \ 1097 "\22CRC_ERR" \ 1098 "\21SPLIT" \ 1099 "\20UDP" \ 1100 "\17TCP" \ 1101 "\16IP" \ 1102 "\15b12" \ 1103 "\14b11" \ 1104 "\13b10" \ 1105 "\12b09" \ 1106 "\11RSS" \ 1107 "\10SNAP" \ 1108 "\07VLAN" \ 1109 "\06P4" \ 1110 "\05P3" \ 1111 "\04P2" 1112 1113 1114 /* 1115 * l2_context definition 1116 */ 1117 #define BCE_L2CTX_TYPE 0x00000000 1118 #define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 1119 #define BCE_L2CTX_TYPE_TYPE (0xf<<28) 1120 #define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28) 1121 #define BCE_L2CTX_TYPE_TYPE_L2 (1<<28) 1122 1123 #define BCE_L2CTX_TX_HOST_BIDX 0x00000088 1124 #define BCE_L2CTX_EST_NBD 0x00000088 1125 #define BCE_L2CTX_CMD_TYPE 0x00000088 1126 #define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24) 1127 #define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 1128 #define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 1129 1130 #define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1131 #define BCE_L2CTX_TSCH_BSEQ 0x00000094 1132 #define BCE_L2CTX_TBDR_BSEQ 0x00000098 1133 #define BCE_L2CTX_TBDR_BOFF 0x0000009c 1134 #define BCE_L2CTX_TBDR_BIDX 0x0000009c 1135 #define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0 1136 #define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4 1137 #define BCE_L2CTX_TXP_BOFF 0x000000a8 1138 #define BCE_L2CTX_TXP_BIDX 0x000000a8 1139 #define BCE_L2CTX_TXP_BSEQ 0x000000ac 1140 1141 1142 /* 1143 * l2_bd_chain_context definition 1144 */ 1145 #define BCE_L2CTX_BD_PRE_READ 0x00000000 1146 #define BCE_L2CTX_CTX_SIZE 0x00000000 1147 #define BCE_L2CTX_CTX_TYPE 0x00000000 1148 #define BCE_L2CTX_LO_WATER_MARK_DEFAULT 32 1149 #define BCE_L2CTX_LO_WATER_MARK_SCALE 4 1150 #define BCE_L2CTX_LO_WATER_MARK_DIS 0 1151 #define BCE_L2CTX_HI_WATER_MARK_SHIFT 4 1152 #define BCE_L2CTX_HI_WATER_MARK_SCALE 16 1153 #define BCE_L2CTX_WATER_MARKS_MSK 0x000000ff 1154 1155 #define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1156 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1157 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1158 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1159 1160 #define BCE_L2CTX_HOST_BDIDX 0x00000004 1161 #define BCE_L2CTX_HOST_BSEQ 0x00000008 1162 #define BCE_L2CTX_NX_BSEQ 0x0000000c 1163 #define BCE_L2CTX_NX_BDHADDR_HI 0x00000010 1164 #define BCE_L2CTX_NX_BDHADDR_LO 0x00000014 1165 #define BCE_L2CTX_NX_BDIDX 0x00000018 1166 1167 /* Page Buffer Descriptor Index */ 1168 #define BCE_L2CTX_HOST_PG_BDIDX 0x00000044 1169 /* SKB and Page Buffer Size */ 1170 #define BCE_L2CTX_PG_BUF_SIZE 0x00000048 1171 /* Page Chain BD Context */ 1172 #define BCE_L2CTX_RBDC_KEY 0x0000004c 1173 #define BCE_L2CTX_RBDC_JUMBO_KEY 0x3ffe 1174 /* Page Chain Next BD Host Address */ 1175 #define BCE_L2CTX_NX_PG_BDHADDR_HI 0x00000050 1176 #define BCE_L2CTX_NX_PG_BDHADDR_LO 0x00000054 1177 #define BCE_L2CTX_NX_PG_BDIDX 0x00000058 1178 1179 1180 /* 1181 * pci_config_l definition 1182 * offset: 0000 1183 */ 1184 #define BCE_PCICFG_MISC_CONFIG 0x00000068 1185 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1186 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1187 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1188 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1189 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1190 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1191 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1192 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1193 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1194 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1195 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1196 1197 #define BCE_PCICFG_MISC_STATUS 0x0000006c 1198 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1199 #define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1200 #define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1201 #define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1202 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1203 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1204 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1205 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1206 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1207 1208 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1209 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1210 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1211 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1212 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1213 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1214 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1215 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1216 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1217 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1218 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1219 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1220 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1221 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1222 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1223 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1224 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1225 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1226 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1227 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1228 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1229 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1230 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1231 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1232 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1233 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1234 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1235 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1236 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1237 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1238 1239 #define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1240 #define BCE_PCICFG_REG_WINDOW 0x00000080 1241 #define BCE_PCICFG_INT_ACK_CMD 0x00000084 1242 #define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1243 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1244 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1245 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1246 1247 #define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1248 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1249 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1250 #define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1251 1252 1253 /* 1254 * pci_reg definition 1255 * offset: 0x400 1256 */ 1257 #define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1258 #define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1259 1260 #define BCE_PCI_CONFIG_1 0x00000404 1261 #define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1262 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1263 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1264 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1265 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1266 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1267 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1268 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1269 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1270 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1271 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1272 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1273 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1274 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1275 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1276 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1277 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1278 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1279 1280 #define BCE_PCI_CONFIG_2 0x00000408 1281 #define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1282 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1283 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1284 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1285 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1286 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1287 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1288 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1289 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1290 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1291 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1292 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1293 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1294 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1295 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1296 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1297 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1298 #define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1299 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1300 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1301 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1302 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1303 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1304 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1305 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1306 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1307 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1308 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1309 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1310 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1311 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1312 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1313 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1314 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1315 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1316 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1317 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1318 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1319 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1320 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1321 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1322 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1323 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1324 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1325 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1326 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1327 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1328 1329 #define BCE_PCI_CONFIG_3 0x0000040c 1330 #define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1331 #define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1332 #define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1333 #define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1334 #define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1335 #define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1336 #define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1337 1338 #define BCE_PCI_PM_DATA_A 0x00000410 1339 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1340 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1341 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1342 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1343 1344 #define BCE_PCI_PM_DATA_B 0x00000414 1345 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1346 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1347 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1348 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1349 1350 #define BCE_PCI_SWAP_DIAG0 0x00000418 1351 #define BCE_PCI_SWAP_DIAG1 0x0000041c 1352 #define BCE_PCI_EXP_ROM_ADDR 0x00000420 1353 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1354 #define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1355 1356 #define BCE_PCI_EXP_ROM_DATA 0x00000424 1357 #define BCE_PCI_VPD_INTF 0x00000428 1358 #define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1359 1360 #define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1361 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1362 #define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1363 1364 #define BCE_PCI_VPD_DATA 0x00000430 1365 #define BCE_PCI_ID_VAL1 0x00000434 1366 #define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1367 #define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1368 1369 #define BCE_PCI_ID_VAL2 0x00000438 1370 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1371 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1372 1373 #define BCE_PCI_ID_VAL3 0x0000043c 1374 #define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1375 #define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1376 1377 #define BCE_PCI_ID_VAL4 0x00000440 1378 #define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1379 #define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1380 #define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1381 #define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1382 #define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1383 #define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1384 #define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1385 #define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1386 #define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1387 #define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1388 #define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1389 #define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1390 #define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1391 #define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1392 #define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1393 #define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1394 #define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1395 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1396 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1397 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1398 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1399 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1400 #define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1401 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1402 #define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1403 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1404 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1405 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1406 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1407 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1408 1409 #define BCE_PCI_ID_VAL5 0x00000444 1410 #define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1411 #define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1412 #define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1413 #define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1414 #define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1415 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1416 1417 #define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1418 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1419 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1420 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1421 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1422 1423 #define BCE_PCI_ID_VAL6 0x0000044c 1424 #define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1425 #define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1426 #define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1427 1428 #define BCE_PCI_MSI_DATA 0x00000450 1429 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1430 1431 #define BCE_PCI_MSI_ADDR_H 0x00000454 1432 #define BCE_PCI_MSI_ADDR_L 0x00000458 1433 1434 1435 /* 1436 * misc_reg definition 1437 * offset: 0x800 1438 */ 1439 #define BCE_MISC_COMMAND 0x00000800 1440 #define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1441 #define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1442 #define BCE_MISC_COMMAND_CORE_RESET (1L<<4) 1443 #define BCE_MISC_COMMAND_HARD_RESET (1L<<5) 1444 #define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1445 #define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1446 1447 #define BCE_MISC_CFG 0x00000804 1448 #define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1449 #define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1450 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1451 #define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1452 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1453 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1454 #define BCE_MISC_CFG_BIST_EN (1L<<3) 1455 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1456 #define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5) 1457 #define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6) 1458 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1459 #define BCE_MISC_CFG_LEDMODE (0x3L<<8) 1460 #define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1461 #define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1462 #define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1463 1464 #define BCE_MISC_ID 0x00000808 1465 #define BCE_MISC_ID_BOND_ID (0xfL<<0) 1466 #define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1467 #define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1468 #define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1469 1470 #define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1471 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1472 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1473 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1474 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1475 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1476 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1477 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1478 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1479 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1480 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1481 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1482 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1483 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1484 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1485 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1486 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1487 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1488 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1489 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1490 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1491 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1492 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1493 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1494 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1495 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1496 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1497 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1498 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1499 1500 #define BCE_MISC_ENABLE_SET_BITS 0x00000810 1501 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1502 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1503 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1504 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1505 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1506 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1507 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1508 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1509 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1510 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1511 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1512 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1513 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1514 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1515 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1516 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1517 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1518 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1519 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1520 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1521 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1522 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1523 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1524 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1525 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1526 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1527 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1528 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1529 1530 #define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1531 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1532 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1533 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1534 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1535 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1536 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1537 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1538 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1539 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1540 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1541 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1542 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1543 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1544 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1545 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1546 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1547 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1548 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1549 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1550 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1551 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1552 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1553 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1554 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1555 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1556 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1557 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1558 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1559 1560 #define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1561 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1562 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1563 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1564 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1565 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1566 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1567 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1568 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1569 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1570 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1571 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1572 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1573 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1574 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1575 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1576 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1577 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1578 #define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1579 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1580 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1581 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1582 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1583 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1584 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1585 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1586 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1587 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1588 #define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1589 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1590 1591 #define BCE_MISC_GPIO 0x0000081c 1592 #define BCE_MISC_GPIO_VALUE (0xffL<<0) 1593 #define BCE_MISC_GPIO_SET (0xffL<<8) 1594 #define BCE_MISC_GPIO_CLR (0xffL<<16) 1595 #define BCE_MISC_GPIO_FLOAT (0xffL<<24) 1596 1597 #define BCE_MISC_GPIO_INT 0x00000820 1598 #define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1599 #define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1600 #define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1601 #define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1602 1603 #define BCE_MISC_CONFIG_LFSR 0x00000824 1604 #define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1605 1606 #define BCE_MISC_LFSR_MASK_BITS 0x00000828 1607 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1608 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1609 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1610 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1611 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1612 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1613 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1614 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1615 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1616 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1617 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1618 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1619 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1620 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1621 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1622 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1623 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1624 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1625 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1626 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1627 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1628 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1629 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1630 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1631 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1632 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1633 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1634 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1635 1636 #define BCE_MISC_ARB_REQ0 0x0000082c 1637 #define BCE_MISC_ARB_REQ1 0x00000830 1638 #define BCE_MISC_ARB_REQ2 0x00000834 1639 #define BCE_MISC_ARB_REQ3 0x00000838 1640 #define BCE_MISC_ARB_REQ4 0x0000083c 1641 #define BCE_MISC_ARB_FREE0 0x00000840 1642 #define BCE_MISC_ARB_FREE1 0x00000844 1643 #define BCE_MISC_ARB_FREE2 0x00000848 1644 #define BCE_MISC_ARB_FREE3 0x0000084c 1645 #define BCE_MISC_ARB_FREE4 0x00000850 1646 #define BCE_MISC_ARB_REQ_STATUS0 0x00000854 1647 #define BCE_MISC_ARB_REQ_STATUS1 0x00000858 1648 #define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 1649 #define BCE_MISC_ARB_REQ_STATUS3 0x00000860 1650 #define BCE_MISC_ARB_REQ_STATUS4 0x00000864 1651 #define BCE_MISC_ARB_GNT0 0x00000868 1652 #define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 1653 #define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 1654 #define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 1655 #define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 1656 #define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 1657 #define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 1658 #define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 1659 #define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 1660 1661 #define BCE_MISC_ARB_GNT1 0x0000086c 1662 #define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 1663 #define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 1664 #define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 1665 #define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 1666 #define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 1667 #define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 1668 #define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 1669 #define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 1670 1671 #define BCE_MISC_ARB_GNT2 0x00000870 1672 #define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 1673 #define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 1674 #define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 1675 #define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 1676 #define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 1677 #define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 1678 #define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 1679 #define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 1680 1681 #define BCE_MISC_ARB_GNT3 0x00000874 1682 #define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 1683 #define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 1684 #define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 1685 #define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 1686 #define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 1687 #define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 1688 #define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 1689 #define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 1690 1691 #define BCE_MISC_PRBS_CONTROL 0x00000878 1692 #define BCE_MISC_PRBS_CONTROL_EN (1L<<0) 1693 #define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1) 1694 #define BCE_MISC_PRBS_CONTROL_INV (1L<<2) 1695 #define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1696 #define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1697 #define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1698 #define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1699 #define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1700 #define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1701 1702 #define BCE_MISC_PRBS_STATUS 0x0000087c 1703 #define BCE_MISC_PRBS_STATUS_LOCK (1L<<0) 1704 #define BCE_MISC_PRBS_STATUS_STKY (1L<<1) 1705 #define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1706 #define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16) 1707 1708 #define BCE_MISC_SM_ASF_CONTROL 0x00000880 1709 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1710 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1711 #define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1712 #define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1713 #define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1714 #define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1715 #define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1716 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1717 #define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1718 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1719 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1720 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1721 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1722 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1723 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1724 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1725 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1726 1727 #define BCE_MISC_SMB_IN 0x00000884 1728 #define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 1729 #define BCE_MISC_SMB_IN_RDY (1L<<8) 1730 #define BCE_MISC_SMB_IN_DONE (1L<<9) 1731 #define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1732 #define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 1733 #define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1734 #define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1735 #define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1736 #define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1737 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1738 1739 #define BCE_MISC_SMB_OUT 0x00000888 1740 #define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1741 #define BCE_MISC_SMB_OUT_RDY (1L<<8) 1742 #define BCE_MISC_SMB_OUT_START (1L<<9) 1743 #define BCE_MISC_SMB_OUT_LAST (1L<<10) 1744 #define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1745 #define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 1746 #define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1747 #define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1748 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1749 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1750 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1751 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1752 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1753 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1754 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1755 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1756 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1757 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1758 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1759 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1760 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1761 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1762 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1763 1764 #define BCE_MISC_SMB_WATCHDOG 0x0000088c 1765 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1766 1767 #define BCE_MISC_SMB_HEARTBEAT 0x00000890 1768 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1769 1770 #define BCE_MISC_SMB_POLL_ASF 0x00000894 1771 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1772 1773 #define BCE_MISC_SMB_POLL_LEGACY 0x00000898 1774 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1775 1776 #define BCE_MISC_SMB_RETRAN 0x0000089c 1777 #define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1778 1779 #define BCE_MISC_SMB_TIMESTAMP 0x000008a0 1780 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1781 1782 #define BCE_MISC_PERR_ENA0 0x000008a4 1783 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1784 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1785 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1786 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1787 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1788 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1789 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1790 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1791 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1792 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1793 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1794 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1795 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1796 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1797 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1798 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1799 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1800 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1801 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1802 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1803 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1804 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1805 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1806 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1807 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1808 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1809 #define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1810 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1811 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1812 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1813 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1814 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1815 1816 #define BCE_MISC_PERR_ENA1 0x000008a8 1817 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1818 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1819 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1820 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1821 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1822 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1823 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1824 #define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1825 #define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1826 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1827 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1828 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1829 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1830 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1831 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1832 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1833 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1834 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1835 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1836 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1837 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1838 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1839 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1840 #define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1841 #define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1842 #define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1843 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1844 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1845 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1846 #define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1847 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1848 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1849 1850 #define BCE_MISC_PERR_ENA2 0x000008ac 1851 #define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1852 #define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1853 #define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1854 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1855 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1856 #define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1857 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1858 #define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1859 #define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1860 1861 #define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 1862 #define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1863 #define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1864 1865 #define BCE_MISC_VREG_CONTROL 0x000008b4 1866 #define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1867 #define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1868 1869 #define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1870 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1871 1872 #define BCE_MISC_UNUSED0 0x000008bc 1873 1874 1875 /* 1876 * nvm_reg definition 1877 * offset: 0x6400 1878 */ 1879 #define BCE_NVM_COMMAND 0x00006400 1880 #define BCE_NVM_COMMAND_RST (1L<<0) 1881 #define BCE_NVM_COMMAND_DONE (1L<<3) 1882 #define BCE_NVM_COMMAND_DOIT (1L<<4) 1883 #define BCE_NVM_COMMAND_WR (1L<<5) 1884 #define BCE_NVM_COMMAND_ERASE (1L<<6) 1885 #define BCE_NVM_COMMAND_FIRST (1L<<7) 1886 #define BCE_NVM_COMMAND_LAST (1L<<8) 1887 #define BCE_NVM_COMMAND_WREN (1L<<16) 1888 #define BCE_NVM_COMMAND_WRDI (1L<<17) 1889 #define BCE_NVM_COMMAND_EWSR (1L<<18) 1890 #define BCE_NVM_COMMAND_WRSR (1L<<19) 1891 1892 #define BCE_NVM_STATUS 0x00006404 1893 #define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1894 #define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1895 #define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1896 1897 #define BCE_NVM_WRITE 0x00006408 1898 #define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1899 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1900 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1901 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1902 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1903 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1904 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1905 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1906 1907 #define BCE_NVM_ADDR 0x0000640c 1908 #define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1909 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1910 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1911 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1912 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1913 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1914 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1915 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1916 1917 #define BCE_NVM_READ 0x00006410 1918 #define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1919 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1920 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1921 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1922 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1923 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1924 #define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1925 #define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1926 1927 #define BCE_NVM_CFG1 0x00006414 1928 #define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 1929 #define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 1930 #define BCE_NVM_CFG1_PASS_MODE (1L<<2) 1931 #define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 1932 #define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 1933 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1934 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1935 #define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1936 #define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1937 #define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 1938 #define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 1939 #define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1940 1941 #define BCE_NVM_CFG2 0x00006418 1942 #define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 1943 #define BCE_NVM_CFG2_DUMMY (0xffL<<8) 1944 #define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 1945 1946 #define BCE_NVM_CFG3 0x0000641c 1947 #define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1948 #define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 1949 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1950 #define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 1951 1952 #define BCE_NVM_SW_ARB 0x00006420 1953 #define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1954 #define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1955 #define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1956 #define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1957 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1958 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1959 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1960 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1961 #define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1962 #define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1963 #define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1964 #define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1965 #define BCE_NVM_SW_ARB_REQ0 (1L<<12) 1966 #define BCE_NVM_SW_ARB_REQ1 (1L<<13) 1967 #define BCE_NVM_SW_ARB_REQ2 (1L<<14) 1968 #define BCE_NVM_SW_ARB_REQ3 (1L<<15) 1969 1970 #define BCE_NVM_ACCESS_ENABLE 0x00006424 1971 #define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 1972 #define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1973 1974 #define BCE_NVM_WRITE1 0x00006428 1975 #define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 1976 #define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1977 #define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 1978 1979 1980 1981 /* 1982 * dma_reg definition 1983 * offset: 0xc00 1984 */ 1985 #define BCE_DMA_COMMAND 0x00000c00 1986 #define BCE_DMA_COMMAND_ENABLE (1L<<0) 1987 1988 #define BCE_DMA_STATUS 0x00000c04 1989 #define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1990 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1991 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1992 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1993 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1994 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1995 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1996 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1997 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1998 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1999 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 2000 2001 #define BCE_DMA_CONFIG 0x00000c08 2002 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 2003 #define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 2004 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 2005 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 2006 #define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 2007 #define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 2008 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 2009 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 2010 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 2011 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 2012 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 2013 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 2014 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 2015 #define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 2016 #define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 2017 #define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 2018 #define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 2019 #define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 2020 #define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 2021 2022 #define BCE_DMA_BLACKOUT 0x00000c0c 2023 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 2024 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 2025 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 2026 2027 #define BCE_DMA_RCHAN_STAT 0x00000c30 2028 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2029 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 2030 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2031 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 2032 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2033 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 2034 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2035 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 2036 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2037 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 2038 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2039 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 2040 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2041 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 2042 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2043 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 2044 2045 #define BCE_DMA_WCHAN_STAT 0x00000c34 2046 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2047 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 2048 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2049 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 2050 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2051 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 2052 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2053 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 2054 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2055 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 2056 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2057 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 2058 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2059 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 2060 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2061 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 2062 2063 #define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 2064 #define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 2065 #define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 2066 #define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 2067 #define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 2068 #define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 2069 #define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 2070 #define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 2071 #define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 2072 2073 #define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 2074 #define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 2075 #define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 2076 #define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 2077 #define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 2078 #define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 2079 #define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2080 #define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2081 #define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2082 2083 #define BCE_DMA_RCHAN_STAT_00 0x00000c40 2084 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2085 2086 #define BCE_DMA_RCHAN_STAT_01 0x00000c44 2087 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2088 2089 #define BCE_DMA_RCHAN_STAT_02 0x00000c48 2090 #define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2091 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2092 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2093 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2094 2095 #define BCE_DMA_RCHAN_STAT_10 0x00000c4c 2096 #define BCE_DMA_RCHAN_STAT_11 0x00000c50 2097 #define BCE_DMA_RCHAN_STAT_12 0x00000c54 2098 #define BCE_DMA_RCHAN_STAT_20 0x00000c58 2099 #define BCE_DMA_RCHAN_STAT_21 0x00000c5c 2100 #define BCE_DMA_RCHAN_STAT_22 0x00000c60 2101 #define BCE_DMA_RCHAN_STAT_30 0x00000c64 2102 #define BCE_DMA_RCHAN_STAT_31 0x00000c68 2103 #define BCE_DMA_RCHAN_STAT_32 0x00000c6c 2104 #define BCE_DMA_RCHAN_STAT_40 0x00000c70 2105 #define BCE_DMA_RCHAN_STAT_41 0x00000c74 2106 #define BCE_DMA_RCHAN_STAT_42 0x00000c78 2107 #define BCE_DMA_RCHAN_STAT_50 0x00000c7c 2108 #define BCE_DMA_RCHAN_STAT_51 0x00000c80 2109 #define BCE_DMA_RCHAN_STAT_52 0x00000c84 2110 #define BCE_DMA_RCHAN_STAT_60 0x00000c88 2111 #define BCE_DMA_RCHAN_STAT_61 0x00000c8c 2112 #define BCE_DMA_RCHAN_STAT_62 0x00000c90 2113 #define BCE_DMA_RCHAN_STAT_70 0x00000c94 2114 #define BCE_DMA_RCHAN_STAT_71 0x00000c98 2115 #define BCE_DMA_RCHAN_STAT_72 0x00000c9c 2116 #define BCE_DMA_WCHAN_STAT_00 0x00000ca0 2117 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2118 2119 #define BCE_DMA_WCHAN_STAT_01 0x00000ca4 2120 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2121 2122 #define BCE_DMA_WCHAN_STAT_02 0x00000ca8 2123 #define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2124 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2125 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2126 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2127 2128 #define BCE_DMA_WCHAN_STAT_10 0x00000cac 2129 #define BCE_DMA_WCHAN_STAT_11 0x00000cb0 2130 #define BCE_DMA_WCHAN_STAT_12 0x00000cb4 2131 #define BCE_DMA_WCHAN_STAT_20 0x00000cb8 2132 #define BCE_DMA_WCHAN_STAT_21 0x00000cbc 2133 #define BCE_DMA_WCHAN_STAT_22 0x00000cc0 2134 #define BCE_DMA_WCHAN_STAT_30 0x00000cc4 2135 #define BCE_DMA_WCHAN_STAT_31 0x00000cc8 2136 #define BCE_DMA_WCHAN_STAT_32 0x00000ccc 2137 #define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2138 #define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2139 #define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2140 #define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2141 #define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2142 #define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2143 #define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2144 #define BCE_DMA_WCHAN_STAT_61 0x00000cec 2145 #define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2146 #define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2147 #define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2148 #define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2149 #define BCE_DMA_ARB_STAT_00 0x00000d00 2150 #define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2151 #define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2152 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2153 2154 #define BCE_DMA_ARB_STAT_01 0x00000d04 2155 #define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2156 #define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2157 #define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2158 #define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2159 #define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2160 #define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2161 #define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2162 #define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2163 2164 #define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2165 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2166 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2167 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2168 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2169 #define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2170 2171 #define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2172 #define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2173 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2174 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2175 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2176 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2177 #define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2178 2179 #define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2180 #define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2181 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2182 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2183 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2184 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2185 #define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2186 2187 #define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2188 2189 2190 /* 2191 * context_reg definition 2192 * offset: 0x1000 2193 */ 2194 #define BCE_CTX_COMMAND 0x00001000 2195 #define BCE_CTX_COMMAND_ENABLED (1L<<0) 2196 2197 #define BCE_CTX_STATUS 0x00001004 2198 #define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 2199 #define BCE_CTX_STATUS_READ_STAT (1L<<16) 2200 #define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 2201 #define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2202 #define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2203 2204 #define BCE_CTX_VIRT_ADDR 0x00001008 2205 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2206 2207 #define BCE_CTX_PAGE_TBL 0x0000100c 2208 #define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2209 2210 #define BCE_CTX_DATA_ADR 0x00001010 2211 #define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2212 2213 #define BCE_CTX_DATA 0x00001014 2214 #define BCE_CTX_LOCK 0x00001018 2215 #define BCE_CTX_LOCK_TYPE (0x7L<<0) 2216 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2217 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2218 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2219 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2220 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2221 #define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2222 #define BCE_CTX_LOCK_GRANTED (1L<<26) 2223 #define BCE_CTX_LOCK_MODE (0x7L<<27) 2224 #define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2225 #define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2226 #define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 2227 #define BCE_CTX_LOCK_STATUS (1L<<30) 2228 #define BCE_CTX_LOCK_REQ (1L<<31) 2229 2230 #define BCE_CTX_ACCESS_STATUS 0x00001040 2231 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2232 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2233 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2234 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2235 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2236 2237 #define BCE_CTX_DBG_LOCK_STATUS 0x00001044 2238 #define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2239 #define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2240 2241 #define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 2242 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2243 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2244 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2245 2246 #define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 2247 #define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 2248 #define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2249 #define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 2250 #define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 2251 #define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 2252 #define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2253 #define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2254 2255 2256 /* 2257 * emac_reg definition 2258 * offset: 0x1400 2259 */ 2260 #define BCE_EMAC_MODE 0x00001400 2261 #define BCE_EMAC_MODE_RESET (1L<<0) 2262 #define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 2263 #define BCE_EMAC_MODE_PORT (0x3L<<2) 2264 #define BCE_EMAC_MODE_PORT_NONE (0L<<2) 2265 #define BCE_EMAC_MODE_PORT_MII (1L<<2) 2266 #define BCE_EMAC_MODE_PORT_GMII (2L<<2) 2267 #define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 2268 #define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 2269 #define BCE_EMAC_MODE_25G (1L<<5) 2270 #define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2271 #define BCE_EMAC_MODE_TX_BURST (1L<<8) 2272 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2273 #define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 2274 #define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 2275 #define BCE_EMAC_MODE_MPKT (1L<<18) 2276 #define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 2277 #define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 2278 2279 #define BCE_EMAC_STATUS 0x00001404 2280 #define BCE_EMAC_STATUS_LINK (1L<<11) 2281 #define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 2282 #define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 2283 #define BCE_EMAC_STATUS_MI_INT (1L<<23) 2284 #define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 2285 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2286 2287 #define BCE_EMAC_ATTENTION_ENA 0x00001408 2288 #define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 2289 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2290 #define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2291 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2292 2293 #define BCE_EMAC_LED 0x0000140c 2294 #define BCE_EMAC_LED_OVERRIDE (1L<<0) 2295 #define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2296 #define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 2297 #define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 2298 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2299 #define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2300 #define BCE_EMAC_LED_TRAFFIC (1L<<6) 2301 #define BCE_EMAC_LED_1000MB (1L<<7) 2302 #define BCE_EMAC_LED_100MB (1L<<8) 2303 #define BCE_EMAC_LED_10MB (1L<<9) 2304 #define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 2305 #define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 2306 #define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2307 2308 #define BCE_EMAC_MAC_MATCH0 0x00001410 2309 #define BCE_EMAC_MAC_MATCH1 0x00001414 2310 #define BCE_EMAC_MAC_MATCH2 0x00001418 2311 #define BCE_EMAC_MAC_MATCH3 0x0000141c 2312 #define BCE_EMAC_MAC_MATCH4 0x00001420 2313 #define BCE_EMAC_MAC_MATCH5 0x00001424 2314 #define BCE_EMAC_MAC_MATCH6 0x00001428 2315 #define BCE_EMAC_MAC_MATCH7 0x0000142c 2316 #define BCE_EMAC_MAC_MATCH8 0x00001430 2317 #define BCE_EMAC_MAC_MATCH9 0x00001434 2318 #define BCE_EMAC_MAC_MATCH10 0x00001438 2319 #define BCE_EMAC_MAC_MATCH11 0x0000143c 2320 #define BCE_EMAC_MAC_MATCH12 0x00001440 2321 #define BCE_EMAC_MAC_MATCH13 0x00001444 2322 #define BCE_EMAC_MAC_MATCH14 0x00001448 2323 #define BCE_EMAC_MAC_MATCH15 0x0000144c 2324 #define BCE_EMAC_MAC_MATCH16 0x00001450 2325 #define BCE_EMAC_MAC_MATCH17 0x00001454 2326 #define BCE_EMAC_MAC_MATCH18 0x00001458 2327 #define BCE_EMAC_MAC_MATCH19 0x0000145c 2328 #define BCE_EMAC_MAC_MATCH20 0x00001460 2329 #define BCE_EMAC_MAC_MATCH21 0x00001464 2330 #define BCE_EMAC_MAC_MATCH22 0x00001468 2331 #define BCE_EMAC_MAC_MATCH23 0x0000146c 2332 #define BCE_EMAC_MAC_MATCH24 0x00001470 2333 #define BCE_EMAC_MAC_MATCH25 0x00001474 2334 #define BCE_EMAC_MAC_MATCH26 0x00001478 2335 #define BCE_EMAC_MAC_MATCH27 0x0000147c 2336 #define BCE_EMAC_MAC_MATCH28 0x00001480 2337 #define BCE_EMAC_MAC_MATCH29 0x00001484 2338 #define BCE_EMAC_MAC_MATCH30 0x00001488 2339 #define BCE_EMAC_MAC_MATCH31 0x0000148c 2340 #define BCE_EMAC_BACKOFF_SEED 0x00001498 2341 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2342 2343 #define BCE_EMAC_RX_MTU_SIZE 0x0000149c 2344 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2345 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2346 2347 #define BCE_EMAC_SERDES_CNTL 0x000014a4 2348 #define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2349 #define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2350 #define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2351 #define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2352 #define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2353 #define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2354 #define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2355 #define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2356 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2357 #define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2358 #define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2359 #define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2360 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2361 #define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2362 #define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2363 #define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2364 2365 #define BCE_EMAC_SERDES_STATUS 0x000014a8 2366 #define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2367 #define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2368 2369 #define BCE_EMAC_MDIO_COMM 0x000014ac 2370 #define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2371 #define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2372 #define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2373 #define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2374 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2375 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2376 #define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2377 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2378 #define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 2379 #define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2380 #define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 2381 2382 #define BCE_EMAC_MDIO_STATUS 0x000014b0 2383 #define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 2384 #define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 2385 2386 #define BCE_EMAC_MDIO_MODE 0x000014b4 2387 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2388 #define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2389 #define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2390 #define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 2391 #define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2392 #define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 2393 #define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 2394 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2395 2396 #define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 2397 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2398 2399 #define BCE_EMAC_TX_MODE 0x000014bc 2400 #define BCE_EMAC_TX_MODE_RESET (1L<<0) 2401 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2402 #define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 2403 #define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2404 #define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2405 #define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2406 2407 #define BCE_EMAC_TX_STATUS 0x000014c0 2408 #define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 2409 #define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2410 #define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 2411 #define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 2412 #define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2413 2414 #define BCE_EMAC_TX_LENGTHS 0x000014c4 2415 #define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2416 #define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2417 #define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2418 2419 #define BCE_EMAC_RX_MODE 0x000014c8 2420 #define BCE_EMAC_RX_MODE_RESET (1L<<0) 2421 #define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 2422 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2423 #define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2424 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2425 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2426 #define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 2427 #define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2428 #define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2429 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2430 #define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2431 #define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 2432 2433 #define BCE_EMAC_RX_STATUS 0x000014cc 2434 #define BCE_EMAC_RX_STATUS_FFED (1L<<0) 2435 #define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2436 #define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2437 2438 #define BCE_EMAC_MULTICAST_HASH0 0x000014d0 2439 #define BCE_EMAC_MULTICAST_HASH1 0x000014d4 2440 #define BCE_EMAC_MULTICAST_HASH2 0x000014d8 2441 #define BCE_EMAC_MULTICAST_HASH3 0x000014dc 2442 #define BCE_EMAC_MULTICAST_HASH4 0x000014e0 2443 #define BCE_EMAC_MULTICAST_HASH5 0x000014e4 2444 #define BCE_EMAC_MULTICAST_HASH6 0x000014e8 2445 #define BCE_EMAC_MULTICAST_HASH7 0x000014ec 2446 #define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2447 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2448 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2449 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2450 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2451 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2452 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2453 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2454 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2455 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2456 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2457 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2458 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2459 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2460 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2461 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2462 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2463 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2464 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2465 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2466 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2467 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2468 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2469 #define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 2470 #define BCE_EMAC_RXMAC_DEBUG1 0x00001560 2471 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2472 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2473 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2474 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2475 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2476 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2477 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2478 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2479 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2480 2481 #define BCE_EMAC_RXMAC_DEBUG2 0x00001564 2482 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2483 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2484 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2485 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2486 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2487 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2488 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2489 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2490 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2491 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2492 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2493 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2494 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2495 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2496 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2497 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2498 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2499 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2500 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2501 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2502 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2503 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2504 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2505 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2506 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2507 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2508 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2509 2510 #define BCE_EMAC_RXMAC_DEBUG3 0x00001568 2511 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2512 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2513 2514 #define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 2515 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2516 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2517 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2518 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2519 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2520 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2521 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2522 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2523 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2524 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2525 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2526 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2527 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2528 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2529 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2530 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2531 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2532 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2533 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2534 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2535 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2536 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2537 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2538 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2539 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2540 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2541 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2542 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2543 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2544 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2545 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2546 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2547 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2548 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2549 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2550 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2551 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2552 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2553 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2554 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2555 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2556 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2557 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2558 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2559 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2560 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2561 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2562 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2563 #define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 2564 2565 #define BCE_EMAC_RXMAC_DEBUG5 0x00001570 2566 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2567 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2568 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2569 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2570 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2571 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2572 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2573 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2574 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2575 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2576 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2577 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2578 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2579 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2580 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2581 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2582 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2583 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2584 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2585 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2586 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2587 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2588 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2589 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2590 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2591 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2592 2593 #define BCE_EMAC_RX_STAT_AC0 0x00001580 2594 #define BCE_EMAC_RX_STAT_AC1 0x00001584 2595 #define BCE_EMAC_RX_STAT_AC2 0x00001588 2596 #define BCE_EMAC_RX_STAT_AC3 0x0000158c 2597 #define BCE_EMAC_RX_STAT_AC4 0x00001590 2598 #define BCE_EMAC_RX_STAT_AC5 0x00001594 2599 #define BCE_EMAC_RX_STAT_AC6 0x00001598 2600 #define BCE_EMAC_RX_STAT_AC7 0x0000159c 2601 #define BCE_EMAC_RX_STAT_AC8 0x000015a0 2602 #define BCE_EMAC_RX_STAT_AC9 0x000015a4 2603 #define BCE_EMAC_RX_STAT_AC10 0x000015a8 2604 #define BCE_EMAC_RX_STAT_AC11 0x000015ac 2605 #define BCE_EMAC_RX_STAT_AC12 0x000015b0 2606 #define BCE_EMAC_RX_STAT_AC13 0x000015b4 2607 #define BCE_EMAC_RX_STAT_AC14 0x000015b8 2608 #define BCE_EMAC_RX_STAT_AC15 0x000015bc 2609 #define BCE_EMAC_RX_STAT_AC16 0x000015c0 2610 #define BCE_EMAC_RX_STAT_AC17 0x000015c4 2611 #define BCE_EMAC_RX_STAT_AC18 0x000015c8 2612 #define BCE_EMAC_RX_STAT_AC19 0x000015cc 2613 #define BCE_EMAC_RX_STAT_AC20 0x000015d0 2614 #define BCE_EMAC_RX_STAT_AC21 0x000015d4 2615 #define BCE_EMAC_RX_STAT_AC22 0x000015d8 2616 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2617 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2618 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2619 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2620 #define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2621 #define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2622 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2623 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2624 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2625 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2626 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2627 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2628 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2629 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2630 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2631 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2632 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2633 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2634 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2635 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2636 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2637 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2638 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2639 #define BCE_EMAC_TXMAC_DEBUG0 0x00001658 2640 #define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 2641 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2642 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2643 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2644 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2645 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2646 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2647 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2648 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2649 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2650 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2651 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2652 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2653 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2654 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2655 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2656 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2657 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2658 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2659 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2660 2661 #define BCE_EMAC_TXMAC_DEBUG2 0x00001660 2662 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2663 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2664 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2665 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2666 2667 #define BCE_EMAC_TXMAC_DEBUG3 0x00001664 2668 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2669 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2670 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2671 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2672 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2673 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2674 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2675 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2676 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2677 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2678 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2679 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2680 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2681 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2682 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2683 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2684 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2685 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2686 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2687 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2688 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2689 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2690 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2691 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2692 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2693 #define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2694 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2695 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2696 2697 #define BCE_EMAC_TXMAC_DEBUG4 0x00001668 2698 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2699 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2700 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2701 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2702 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2703 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2704 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2705 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2706 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2707 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2708 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2709 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2710 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2711 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2712 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2713 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2714 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2715 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2716 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2717 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2718 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2719 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2720 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2721 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2722 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2723 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2724 #define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2725 2726 #define BCE_EMAC_TX_STAT_AC0 0x00001680 2727 #define BCE_EMAC_TX_STAT_AC1 0x00001684 2728 #define BCE_EMAC_TX_STAT_AC2 0x00001688 2729 #define BCE_EMAC_TX_STAT_AC3 0x0000168c 2730 #define BCE_EMAC_TX_STAT_AC4 0x00001690 2731 #define BCE_EMAC_TX_STAT_AC5 0x00001694 2732 #define BCE_EMAC_TX_STAT_AC6 0x00001698 2733 #define BCE_EMAC_TX_STAT_AC7 0x0000169c 2734 #define BCE_EMAC_TX_STAT_AC8 0x000016a0 2735 #define BCE_EMAC_TX_STAT_AC9 0x000016a4 2736 #define BCE_EMAC_TX_STAT_AC10 0x000016a8 2737 #define BCE_EMAC_TX_STAT_AC11 0x000016ac 2738 #define BCE_EMAC_TX_STAT_AC12 0x000016b0 2739 #define BCE_EMAC_TX_STAT_AC13 0x000016b4 2740 #define BCE_EMAC_TX_STAT_AC14 0x000016b8 2741 #define BCE_EMAC_TX_STAT_AC15 0x000016bc 2742 #define BCE_EMAC_TX_STAT_AC16 0x000016c0 2743 #define BCE_EMAC_TX_STAT_AC17 0x000016c4 2744 #define BCE_EMAC_TX_STAT_AC18 0x000016c8 2745 #define BCE_EMAC_TX_STAT_AC19 0x000016cc 2746 #define BCE_EMAC_TX_STAT_AC20 0x000016d0 2747 #define BCE_EMAC_TX_STAT_AC21 0x000016d4 2748 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2749 2750 2751 /* 2752 * rpm_reg definition 2753 * offset: 0x1800 2754 */ 2755 #define BCE_RPM_COMMAND 0x00001800 2756 #define BCE_RPM_COMMAND_ENABLED (1L<<0) 2757 #define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2758 2759 #define BCE_RPM_STATUS 0x00001804 2760 #define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 2761 #define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 2762 2763 #define BCE_RPM_CONFIG 0x00001808 2764 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2765 #define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 2766 #define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 2767 #define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 2768 #define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2769 #define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2770 2771 #define BCE_RPM_VLAN_MATCH0 0x00001810 2772 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2773 2774 #define BCE_RPM_VLAN_MATCH1 0x00001814 2775 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2776 2777 #define BCE_RPM_VLAN_MATCH2 0x00001818 2778 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2779 2780 #define BCE_RPM_VLAN_MATCH3 0x0000181c 2781 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2782 2783 #define BCE_RPM_SORT_USER0 0x00001820 2784 #define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2785 #define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 2786 #define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 2787 #define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2788 #define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 2789 #define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2790 #define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2791 #define BCE_RPM_SORT_USER0_ENA (1L<<31) 2792 2793 #define BCE_RPM_SORT_USER1 0x00001824 2794 #define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2795 #define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 2796 #define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 2797 #define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2798 #define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 2799 #define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2800 #define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2801 #define BCE_RPM_SORT_USER1_ENA (1L<<31) 2802 2803 #define BCE_RPM_SORT_USER2 0x00001828 2804 #define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2805 #define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 2806 #define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 2807 #define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2808 #define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 2809 #define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2810 #define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2811 #define BCE_RPM_SORT_USER2_ENA (1L<<31) 2812 2813 #define BCE_RPM_SORT_USER3 0x0000182c 2814 #define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2815 #define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 2816 #define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 2817 #define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2818 #define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 2819 #define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2820 #define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2821 #define BCE_RPM_SORT_USER3_ENA (1L<<31) 2822 2823 #define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2824 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2825 #define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 2826 #define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2827 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2828 #define BCE_RPM_STAT_AC0 0x00001880 2829 #define BCE_RPM_STAT_AC1 0x00001884 2830 #define BCE_RPM_STAT_AC2 0x00001888 2831 #define BCE_RPM_STAT_AC3 0x0000188c 2832 #define BCE_RPM_STAT_AC4 0x00001890 2833 #define BCE_RPM_RC_CNTL_0 0x00001900 2834 #define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2835 #define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2836 #define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2837 #define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 2838 #define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2839 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2840 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2841 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2842 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2843 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2844 #define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 2845 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2846 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2847 #define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2848 #define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2849 #define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 2850 #define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2851 #define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 2852 #define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 2853 #define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 2854 #define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 2855 #define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 2856 #define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 2857 #define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 2858 2859 #define BCE_RPM_RC_VALUE_MASK_0 0x00001904 2860 #define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2861 #define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2862 2863 #define BCE_RPM_RC_CNTL_1 0x00001908 2864 #define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2865 #define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 2866 2867 #define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 2868 #define BCE_RPM_RC_CNTL_2 0x00001910 2869 #define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2870 #define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 2871 2872 #define BCE_RPM_RC_VALUE_MASK_2 0x00001914 2873 #define BCE_RPM_RC_CNTL_3 0x00001918 2874 #define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2875 #define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 2876 2877 #define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 2878 #define BCE_RPM_RC_CNTL_4 0x00001920 2879 #define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2880 #define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 2881 2882 #define BCE_RPM_RC_VALUE_MASK_4 0x00001924 2883 #define BCE_RPM_RC_CNTL_5 0x00001928 2884 #define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2885 #define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 2886 2887 #define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 2888 #define BCE_RPM_RC_CNTL_6 0x00001930 2889 #define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2890 #define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 2891 2892 #define BCE_RPM_RC_VALUE_MASK_6 0x00001934 2893 #define BCE_RPM_RC_CNTL_7 0x00001938 2894 #define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2895 #define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 2896 2897 #define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 2898 #define BCE_RPM_RC_CNTL_8 0x00001940 2899 #define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2900 #define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 2901 2902 #define BCE_RPM_RC_VALUE_MASK_8 0x00001944 2903 #define BCE_RPM_RC_CNTL_9 0x00001948 2904 #define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2905 #define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 2906 2907 #define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 2908 #define BCE_RPM_RC_CNTL_10 0x00001950 2909 #define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2910 #define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 2911 2912 #define BCE_RPM_RC_VALUE_MASK_10 0x00001954 2913 #define BCE_RPM_RC_CNTL_11 0x00001958 2914 #define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2915 #define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 2916 2917 #define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 2918 #define BCE_RPM_RC_CNTL_12 0x00001960 2919 #define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2920 #define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 2921 2922 #define BCE_RPM_RC_VALUE_MASK_12 0x00001964 2923 #define BCE_RPM_RC_CNTL_13 0x00001968 2924 #define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2925 #define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 2926 2927 #define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 2928 #define BCE_RPM_RC_CNTL_14 0x00001970 2929 #define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2930 #define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 2931 2932 #define BCE_RPM_RC_VALUE_MASK_14 0x00001974 2933 #define BCE_RPM_RC_CNTL_15 0x00001978 2934 #define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2935 #define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 2936 2937 #define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 2938 #define BCE_RPM_RC_CONFIG 0x00001980 2939 #define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2940 #define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2941 2942 #define BCE_RPM_DEBUG0 0x00001984 2943 #define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2944 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2945 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2946 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2947 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2948 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2949 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2950 #define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 2951 #define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 2952 #define BCE_RPM_DEBUG0_DONE (1L<<24) 2953 #define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2954 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2955 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2956 #define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2957 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2958 2959 #define BCE_RPM_DEBUG1 0x00001988 2960 #define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2961 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2962 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2963 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2964 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2965 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2966 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2967 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2968 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2969 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2970 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2971 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2972 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2973 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2974 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2975 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2976 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2977 #define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2978 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2979 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2980 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2981 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2982 2983 #define BCE_RPM_DEBUG2 0x0000198c 2984 #define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2985 #define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2986 #define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2987 #define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2988 #define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2989 #define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2990 #define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2991 #define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 2992 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2993 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2994 2995 #define BCE_RPM_DEBUG3 0x00001990 2996 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2997 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2998 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2999 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 3000 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 3001 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 3002 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 3003 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 3004 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 3005 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 3006 #define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 3007 #define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 3008 #define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 3009 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 3010 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 3011 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 3012 #define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 3013 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 3014 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 3015 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 3016 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 3017 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 3018 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 3019 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 3020 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 3021 #define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 3022 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 3023 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 3024 #define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 3025 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 3026 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 3027 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 3028 3029 #define BCE_RPM_DEBUG4 0x00001994 3030 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 3031 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 3032 #define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 3033 #define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 3034 3035 #define BCE_RPM_DEBUG5 0x00001998 3036 #define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 3037 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 3038 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 3039 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 3040 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 3041 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 3042 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 3043 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 3044 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 3045 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 3046 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 3047 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 3048 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 3049 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 3050 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 3051 #define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 3052 3053 #define BCE_RPM_DEBUG6 0x0000199c 3054 #define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 3055 #define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 3056 3057 #define BCE_RPM_DEBUG7 0x000019a0 3058 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 3059 3060 #define BCE_RPM_DEBUG8 0x000019a4 3061 #define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 3062 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 3063 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 3064 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 3065 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 3066 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 3067 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 3068 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 3069 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 3070 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 3071 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 3072 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 3073 #define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 3074 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 3075 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 3076 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 3077 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 3078 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 3079 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 3080 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 3081 #define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 3082 #define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 3083 #define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 3084 #define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 3085 #define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 3086 #define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 3087 3088 #define BCE_RPM_DEBUG9 0x000019a8 3089 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 3090 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 3091 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 3092 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 3093 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 3094 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 3095 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 3096 3097 #define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 3098 #define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 3099 #define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 3100 #define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 3101 #define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 3102 #define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 3103 #define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 3104 #define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 3105 #define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 3106 #define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 3107 #define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 3108 #define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 3109 #define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 3110 #define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 3111 #define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 3112 #define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 3113 3114 3115 /* 3116 * rlup_reg definition 3117 * offset: 0x2000 3118 */ 3119 #define BCE_RLUP_FTQ_CMD 0x000023f8 3120 #define BCE_RLUP_FTQ_CTL 0x000023fc 3121 #define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3122 #define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3123 3124 3125 3126 /* 3127 * rdma_reg definition 3128 * offset: 0x2c00 3129 */ 3130 #define BCE_RDMA_FTQ_CMD 0x00002ff8 3131 #define BCE_RDMA_FTQ_CTL 0x00002ffc 3132 #define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3133 #define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3134 3135 3136 3137 /* 3138 * timer_reg definition 3139 * offset: 0x4400 3140 */ 3141 3142 #define BCE_TIMER_COMMAND 0x00004400 3143 #define BCE_TIMER_COMMAND_ENABLED (1L<<0) 3144 3145 #define BCE_TIMER_STATUS 0x00004404 3146 #define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0) 3147 #define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8) 3148 #define BCE_TIMER_STATUS_TMR1_CNT (1L<<9) 3149 #define BCE_TIMER_STATUS_TMR2_CNT (1L<<10) 3150 #define BCE_TIMER_STATUS_TMR3_CNT (1L<<11) 3151 #define BCE_TIMER_STATUS_TMR4_CNT (1L<<12) 3152 #define BCE_TIMER_STATUS_TMR5_CNT (1L<<13) 3153 3154 #define BCE_TIMER_25MHZ_FREE_RUN 0x00004448 3155 3156 3157 /* 3158 * tsch_reg definition 3159 * offset: 0x4c00 3160 */ 3161 3162 #define BCE_TSCH_FTQ_CMD 0x00004ff8 3163 #define BCE_TSCH_FTQ_CTL 0x00004ffc 3164 #define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3165 #define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3166 3167 3168 3169 /* 3170 * rbuf_reg definition 3171 * offset: 0x200000 3172 */ 3173 #define BCE_RBUF_COMMAND 0x00200000 3174 #define BCE_RBUF_COMMAND_ENABLED (1L<<0) 3175 #define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 3176 #define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 3177 #define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 3178 #define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 3179 3180 #define BCE_RBUF_STATUS1 0x00200004 3181 #define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 3182 3183 #define BCE_RBUF_STATUS2 0x00200008 3184 #define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 3185 #define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 3186 3187 #define BCE_RBUF_CONFIG 0x0020000c 3188 #define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 3189 #define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 3190 3191 #define BCE_RBUF_FW_BUF_ALLOC 0x00200010 3192 #define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 3193 3194 #define BCE_RBUF_FW_BUF_FREE 0x00200014 3195 #define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 3196 #define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 3197 #define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3198 3199 #define BCE_RBUF_FW_BUF_SEL 0x00200018 3200 #define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3201 #define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3202 #define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3203 3204 #define BCE_RBUF_CONFIG2 0x0020001c 3205 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3206 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3207 3208 #define BCE_RBUF_CONFIG3 0x00200020 3209 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3210 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3211 3212 #define BCE_RBUF_PKT_DATA 0x00208000 3213 #define BCE_RBUF_CLIST_DATA 0x00210000 3214 #define BCE_RBUF_BUF_DATA 0x00220000 3215 3216 3217 /* 3218 * rv2p_reg definition 3219 * offset: 0x2800 3220 */ 3221 #define BCE_RV2P_COMMAND 0x00002800 3222 #define BCE_RV2P_COMMAND_ENABLED (1L<<0) 3223 #define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3224 #define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3225 #define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 3226 #define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 3227 #define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 3228 #define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 3229 #define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 3230 #define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 3231 #define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 3232 #define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 3233 #define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3234 3235 #define BCE_RV2P_STATUS 0x00002804 3236 #define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 3237 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3238 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3239 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3240 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3241 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3242 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3243 3244 #define BCE_RV2P_CONFIG 0x00002808 3245 #define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3246 #define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3247 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3248 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3249 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3250 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3251 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3252 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3253 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3254 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3255 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3256 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3257 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3258 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3259 #define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3260 #define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3261 #define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3262 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3263 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3264 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3265 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3266 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3267 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3268 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3269 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3270 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3271 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3272 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3273 3274 #define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 3275 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3276 3277 #define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 3278 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3279 3280 #define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 3281 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3282 3283 #define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 3284 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3285 3286 #define BCE_RV2P_INSTR_HIGH 0x00002830 3287 #define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3288 3289 #define BCE_RV2P_INSTR_LOW 0x00002834 3290 #define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 3291 #define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3292 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3293 3294 #define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 3295 #define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3296 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3297 3298 #define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 3299 #define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 3300 #define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 3301 #define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 3302 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3303 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3304 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3305 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3306 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3307 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3308 3309 #define BCE_RV2P_PFTQ_DATA 0x00002b40 3310 #define BCE_RV2P_PFTQ_CMD 0x00002b78 3311 #define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3312 #define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3313 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3314 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3315 #define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3316 #define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3317 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3318 #define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3319 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3320 #define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 3321 #define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 3322 3323 #define BCE_RV2P_PFTQ_CTL 0x00002b7c 3324 #define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3325 #define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3326 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3327 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3328 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3329 3330 #define BCE_RV2P_TFTQ_DATA 0x00002b80 3331 #define BCE_RV2P_TFTQ_CMD 0x00002bb8 3332 #define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3333 #define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3334 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3335 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3336 #define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3337 #define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3338 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3339 #define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3340 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3341 #define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 3342 #define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 3343 3344 #define BCE_RV2P_TFTQ_CTL 0x00002bbc 3345 #define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3346 #define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3347 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3348 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3349 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3350 3351 #define BCE_RV2P_MFTQ_DATA 0x00002bc0 3352 #define BCE_RV2P_MFTQ_CMD 0x00002bf8 3353 #define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3354 #define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3355 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3356 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3357 #define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3358 #define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3359 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3360 #define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3361 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3362 #define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 3363 #define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 3364 3365 #define BCE_RV2P_MFTQ_CTL 0x00002bfc 3366 #define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3367 #define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3368 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3369 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3370 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3371 3372 3373 3374 /* 3375 * mq_reg definition 3376 * offset: 0x3c00 3377 */ 3378 #define BCE_MQ_COMMAND 0x00003c00 3379 #define BCE_MQ_COMMAND_ENABLED (1L<<0) 3380 #define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 3381 #define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 3382 #define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 3383 3384 #define BCE_MQ_STATUS 0x00003c04 3385 #define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3386 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3387 #define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3388 3389 #define BCE_MQ_CONFIG 0x00003c08 3390 #define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3391 #define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 3392 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3393 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3394 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3395 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3396 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3397 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3398 #define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3399 #define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3400 3401 #define BCE_MQ_ENQUEUE1 0x00003c0c 3402 #define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3403 #define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 3404 #define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3405 #define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3406 3407 #define BCE_MQ_ENQUEUE2 0x00003c10 3408 #define BCE_MQ_BAD_WR_ADDR 0x00003c14 3409 #define BCE_MQ_BAD_RD_ADDR 0x00003c18 3410 #define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 3411 #define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3412 3413 #define BCE_MQ_KNL_WIND_END 0x00003c20 3414 #define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3415 3416 #define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 3417 #define BCE_MQ_KNL_TX_MASK1 0x00003c28 3418 #define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 3419 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3420 #define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 3421 #define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 3422 #define BCE_MQ_KNL_TX_MASK2 0x00003c3c 3423 #define BCE_MQ_KNL_CMD_MASK2 0x00003c40 3424 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3425 #define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 3426 #define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3427 #define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 3428 #define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3429 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3430 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3431 #define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3432 #define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 3433 #define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3434 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3435 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3436 #define BCE_MQ_MEM_WR_ADDR 0x00003c74 3437 #define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3438 3439 #define BCE_MQ_MEM_WR_DATA0 0x00003c78 3440 #define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3441 3442 #define BCE_MQ_MEM_WR_DATA1 0x00003c7c 3443 #define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3444 3445 #define BCE_MQ_MEM_WR_DATA2 0x00003c80 3446 #define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3447 3448 #define BCE_MQ_MEM_RD_ADDR 0x00003c84 3449 #define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3450 3451 #define BCE_MQ_MEM_RD_DATA0 0x00003c88 3452 #define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3453 3454 #define BCE_MQ_MEM_RD_DATA1 0x00003c8c 3455 #define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3456 3457 #define BCE_MQ_MEM_RD_DATA2 0x00003c90 3458 #define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3459 3460 3461 /* 3462 * csch_reg definition 3463 * offset: 0x4000 3464 */ 3465 #define BCE_CSCH_COMMAND 0x00004000 3466 #define BCE_CSCH_CH_FTQ_CMD 0x000043f8 3467 #define BCE_CSCH_CH_FTQ_CTL 0x000043fc 3468 #define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3469 #define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3470 3471 3472 /* 3473 * tbdr_reg definition 3474 * offset: 0x5000 3475 */ 3476 #define BCE_TBDR_COMMAND 0x00005000 3477 #define BCE_TBDR_COMMAND_ENABLE (1L<<0) 3478 #define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 3479 #define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3480 3481 #define BCE_TBDR_STATUS 0x00005004 3482 #define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 3483 #define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 3484 #define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3485 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3486 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3487 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3488 #define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 3489 3490 #define BCE_TBDR_CONFIG 0x00005008 3491 #define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3492 #define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 3493 #define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 3494 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3495 #define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3496 #define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3497 #define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3498 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3499 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3500 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3501 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3502 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3503 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3504 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3505 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3506 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3507 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3508 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3509 3510 #define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 3511 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3512 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3513 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3514 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3515 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3516 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3517 3518 #define BCE_TBDR_FTQ_DATA 0x000053c0 3519 #define BCE_TBDR_FTQ_CMD 0x000053f8 3520 #define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3521 #define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3522 #define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3523 #define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3524 #define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3525 #define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3526 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3527 #define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3528 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3529 #define BCE_TBDR_FTQ_CMD_POP (1L<<30) 3530 #define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 3531 3532 #define BCE_TBDR_FTQ_CTL 0x000053fc 3533 #define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3534 #define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3535 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3536 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3537 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3538 3539 3540 3541 /* 3542 * tdma_reg definition 3543 * offset: 0x5c00 3544 */ 3545 #define BCE_TDMA_COMMAND 0x00005c00 3546 #define BCE_TDMA_COMMAND_ENABLED (1L<<0) 3547 #define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3548 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3549 3550 #define BCE_TDMA_STATUS 0x00005c04 3551 #define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 3552 #define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3553 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3554 #define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 3555 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3556 #define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 3557 3558 #define BCE_TDMA_CONFIG 0x00005c08 3559 #define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 3560 #define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 3561 #define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3562 #define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3563 #define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3564 #define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3565 #define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3566 #define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3567 #define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3568 #define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3569 #define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3570 #define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3571 #define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3572 #define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3573 #define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3574 3575 #define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 3576 #define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3577 3578 #define BCE_TDMA_DBG_WATCHDOG 0x00005c10 3579 #define BCE_TDMA_DBG_TRIGGER 0x00005c14 3580 #define BCE_TDMA_DMAD_FSM 0x00005c80 3581 #define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3582 #define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3583 #define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3584 #define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3585 #define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3586 #define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3587 #define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 3588 3589 #define BCE_TDMA_DMAD_STATUS 0x00005c84 3590 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3591 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3592 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3593 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3594 3595 #define BCE_TDMA_DR_INTF_FSM 0x00005c88 3596 #define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3597 #define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3598 #define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3599 #define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3600 #define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3601 3602 #define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 3603 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3604 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3605 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3606 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3607 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3608 3609 #define BCE_TDMA_FTQ_DATA 0x00005fc0 3610 #define BCE_TDMA_FTQ_CMD 0x00005ff8 3611 #define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3612 #define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3613 #define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3614 #define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3615 #define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3616 #define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3617 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3618 #define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3619 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3620 #define BCE_TDMA_FTQ_CMD_POP (1L<<30) 3621 #define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 3622 3623 #define BCE_TDMA_FTQ_CTL 0x00005ffc 3624 #define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3625 #define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3626 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3627 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3628 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3629 3630 3631 3632 /* 3633 * hc_reg definition 3634 * offset: 0x6800 3635 */ 3636 #define BCE_HC_COMMAND 0x00006800 3637 #define BCE_HC_COMMAND_ENABLE (1L<<0) 3638 #define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 3639 #define BCE_HC_COMMAND_COAL_NOW (1L<<16) 3640 #define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3641 #define BCE_HC_COMMAND_STATS_NOW (1L<<18) 3642 #define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 3643 #define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3644 #define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3645 #define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3646 #define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3647 #define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3648 3649 #define BCE_HC_STATUS 0x00006804 3650 #define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 3651 #define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3652 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3653 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3654 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3655 #define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3656 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3657 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3658 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3659 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3660 3661 #define BCE_HC_CONFIG 0x00006808 3662 #define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 3663 #define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 3664 #define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 3665 #define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 3666 #define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3667 #define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3668 #define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3669 #define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3670 3671 #define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 3672 #define BCE_HC_STATUS_ADDR_L 0x00006810 3673 #define BCE_HC_STATUS_ADDR_H 0x00006814 3674 #define BCE_HC_STATISTICS_ADDR_L 0x00006818 3675 #define BCE_HC_STATISTICS_ADDR_H 0x0000681c 3676 #define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 3677 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3678 #define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3679 3680 #define BCE_HC_COMP_PROD_TRIP 0x00006824 3681 #define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3682 #define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3683 3684 #define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 3685 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3686 #define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3687 3688 #define BCE_HC_RX_TICKS 0x0000682c 3689 #define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 3690 #define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 3691 3692 #define BCE_HC_TX_TICKS 0x00006830 3693 #define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 3694 #define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 3695 3696 #define BCE_HC_COM_TICKS 0x00006834 3697 #define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 3698 #define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 3699 3700 #define BCE_HC_CMD_TICKS 0x00006838 3701 #define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3702 #define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 3703 3704 #define BCE_HC_PERIODIC_TICKS 0x0000683c 3705 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3706 3707 #define BCE_HC_STAT_COLLECT_TICKS 0x00006840 3708 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3709 3710 #define BCE_HC_STATS_TICKS 0x00006844 3711 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3712 3713 #define BCE_HC_STAT_MEM_DATA 0x0000684c 3714 #define BCE_HC_STAT_GEN_SEL_0 0x00006850 3715 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3716 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3717 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3718 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3719 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3720 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3721 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3722 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3723 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3724 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3725 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3726 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3727 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3728 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3729 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3730 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3731 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3732 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3733 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3734 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3735 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3736 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3737 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3738 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3739 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3740 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3741 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3742 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3743 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3744 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3745 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3746 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3747 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3748 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3749 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3750 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3751 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3752 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3753 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3754 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3755 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3756 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3757 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3758 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3759 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3760 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3761 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3762 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3763 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3764 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3765 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3766 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3767 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3768 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3769 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3770 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3771 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3772 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3773 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3774 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3775 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3776 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3777 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3778 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3779 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3780 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3781 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3782 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3783 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3784 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3785 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3786 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3787 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3788 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3789 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3790 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3791 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3792 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3793 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3794 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3795 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3796 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3797 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3798 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3799 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3800 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3801 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3802 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3803 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3804 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3805 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3806 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3807 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3808 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3809 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3810 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3811 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3812 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3813 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3814 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3815 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3816 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3817 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3818 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3819 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3820 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3821 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3822 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3823 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3824 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3825 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3826 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3827 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3828 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3829 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3830 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3831 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3832 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3833 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3834 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3835 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3836 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3837 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3838 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3839 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3840 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3841 3842 #define BCE_HC_STAT_GEN_SEL_1 0x00006854 3843 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3844 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3845 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3846 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3847 3848 #define BCE_HC_STAT_GEN_SEL_2 0x00006858 3849 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3850 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3851 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3852 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3853 3854 #define BCE_HC_STAT_GEN_SEL_3 0x0000685c 3855 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3856 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3857 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3858 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3859 3860 #define BCE_HC_STAT_GEN_STAT0 0x00006888 3861 #define BCE_HC_STAT_GEN_STAT1 0x0000688c 3862 #define BCE_HC_STAT_GEN_STAT2 0x00006890 3863 #define BCE_HC_STAT_GEN_STAT3 0x00006894 3864 #define BCE_HC_STAT_GEN_STAT4 0x00006898 3865 #define BCE_HC_STAT_GEN_STAT5 0x0000689c 3866 #define BCE_HC_STAT_GEN_STAT6 0x000068a0 3867 #define BCE_HC_STAT_GEN_STAT7 0x000068a4 3868 #define BCE_HC_STAT_GEN_STAT8 0x000068a8 3869 #define BCE_HC_STAT_GEN_STAT9 0x000068ac 3870 #define BCE_HC_STAT_GEN_STAT10 0x000068b0 3871 #define BCE_HC_STAT_GEN_STAT11 0x000068b4 3872 #define BCE_HC_STAT_GEN_STAT12 0x000068b8 3873 #define BCE_HC_STAT_GEN_STAT13 0x000068bc 3874 #define BCE_HC_STAT_GEN_STAT14 0x000068c0 3875 #define BCE_HC_STAT_GEN_STAT15 0x000068c4 3876 #define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 3877 #define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 3878 #define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 3879 #define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 3880 #define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 3881 #define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 3882 #define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 3883 #define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 3884 #define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 3885 #define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 3886 #define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 3887 #define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 3888 #define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 3889 #define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 3890 #define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 3891 #define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 3892 #define BCE_HC_VIS 0x00006908 3893 #define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3894 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3895 #define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3896 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3897 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3898 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3899 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3900 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3901 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3902 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3903 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3904 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3905 #define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3906 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3907 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3908 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3909 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3910 #define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3911 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3912 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3913 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3914 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3915 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3916 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3917 #define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3918 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3919 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3920 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3921 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3922 3923 #define BCE_HC_VIS_1 0x0000690c 3924 #define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3925 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3926 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3927 #define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3928 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3929 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3930 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3931 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3932 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3933 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3934 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3935 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3936 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3937 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3938 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3939 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3940 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3941 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3942 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3943 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3944 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3945 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3946 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3947 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3948 #define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 3949 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3950 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3951 #define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3952 #define BCE_HC_VIS_1_INT_B (1L<<27) 3953 3954 #define BCE_HC_DEBUG_VECT_PEEK 0x00006910 3955 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3956 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3957 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3958 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3959 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3960 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3961 3962 3963 3964 /* 3965 * txp_reg definition 3966 * offset: 0x40000 3967 */ 3968 #define BCE_TXP_CPU_MODE 0x00045000 3969 #define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3970 #define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 3971 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3972 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3973 #define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3974 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3975 #define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3976 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3977 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3978 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3979 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3980 3981 #define BCE_TXP_CPU_STATE 0x00045004 3982 #define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3983 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3984 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3985 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3986 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3987 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3988 #define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3989 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3990 #define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3991 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3992 #define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3993 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3994 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3995 #define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3996 3997 #define BCE_TXP_CPU_EVENT_MASK 0x00045008 3998 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3999 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4000 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4001 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4002 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4003 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4004 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4005 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4006 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4007 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4008 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4009 4010 #define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 4011 #define BCE_TXP_CPU_INSTRUCTION 0x00045020 4012 #define BCE_TXP_CPU_DATA_ACCESS 0x00045024 4013 #define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 4014 #define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 4015 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 4016 #define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 4017 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4018 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4019 4020 #define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 4021 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4022 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4023 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4024 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4025 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4026 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4027 4028 #define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 4029 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4030 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4031 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4032 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4033 4034 #define BCE_TXP_CPU_REG_FILE 0x00045200 4035 #define BCE_TXP_FTQ_DATA 0x000453c0 4036 #define BCE_TXP_FTQ_CMD 0x000453f8 4037 #define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4038 #define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 4039 #define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4040 #define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4041 #define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 4042 #define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 4043 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4044 #define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 4045 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4046 #define BCE_TXP_FTQ_CMD_POP (1L<<30) 4047 #define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 4048 4049 #define BCE_TXP_FTQ_CTL 0x000453fc 4050 #define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 4051 #define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 4052 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4053 #define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4054 #define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4055 4056 #define BCE_TXP_SCRATCH 0x00060000 4057 4058 4059 /* 4060 * tpat_reg definition 4061 * offset: 0x80000 4062 */ 4063 #define BCE_TPAT_CPU_MODE 0x00085000 4064 #define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 4065 #define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 4066 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4067 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4068 #define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 4069 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 4070 #define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 4071 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4072 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4073 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4074 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4075 4076 #define BCE_TPAT_CPU_STATE 0x00085004 4077 #define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 4078 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 4079 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4080 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4081 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4082 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 4083 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 4084 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4085 #define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 4086 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4087 #define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 4088 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4089 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 4090 #define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 4091 4092 #define BCE_TPAT_CPU_EVENT_MASK 0x00085008 4093 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4094 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4095 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4096 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4097 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4098 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4099 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4100 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4101 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4102 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4103 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4104 4105 #define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 4106 #define BCE_TPAT_CPU_INSTRUCTION 0x00085020 4107 #define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 4108 #define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 4109 #define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 4110 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 4111 #define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 4112 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4113 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4114 4115 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 4116 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4117 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4118 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4119 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4120 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4121 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4122 4123 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 4124 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4125 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4126 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4127 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4128 4129 #define BCE_TPAT_CPU_REG_FILE 0x00085200 4130 #define BCE_TPAT_FTQ_DATA 0x000853c0 4131 #define BCE_TPAT_FTQ_CMD 0x000853f8 4132 #define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 4133 #define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 4134 #define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 4135 #define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 4136 #define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 4137 #define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 4138 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 4139 #define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 4140 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 4141 #define BCE_TPAT_FTQ_CMD_POP (1L<<30) 4142 #define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 4143 4144 #define BCE_TPAT_FTQ_CTL 0x000853fc 4145 #define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 4146 #define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 4147 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4148 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4149 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4150 4151 #define BCE_TPAT_SCRATCH 0x000a0000 4152 4153 4154 /* 4155 * rxp_reg definition 4156 * offset: 0xc0000 4157 */ 4158 #define BCE_RXP_CPU_MODE 0x000c5000 4159 #define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 4160 #define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 4161 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4162 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4163 #define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 4164 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4165 #define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 4166 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4167 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4168 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4169 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4170 4171 #define BCE_RXP_CPU_STATE 0x000c5004 4172 #define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 4173 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4174 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4175 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4176 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4177 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4178 #define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 4179 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4180 #define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 4181 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4182 #define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 4183 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4184 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4185 #define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 4186 4187 #define BCE_RXP_CPU_EVENT_MASK 0x000c5008 4188 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4189 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4190 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4191 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4192 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4193 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4194 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4195 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4196 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4197 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4198 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4199 4200 #define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 4201 #define BCE_RXP_CPU_INSTRUCTION 0x000c5020 4202 #define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 4203 #define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 4204 #define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 4205 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 4206 #define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 4207 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4208 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4209 4210 #define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 4211 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4212 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4213 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4214 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4215 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4216 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4217 4218 #define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 4219 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4220 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4221 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4222 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4223 4224 #define BCE_RXP_CPU_REG_FILE 0x000c5200 4225 #define BCE_RXP_CFTQ_DATA 0x000c5380 4226 #define BCE_RXP_CFTQ_CMD 0x000c53b8 4227 #define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 4228 #define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 4229 #define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 4230 #define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4231 #define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4232 #define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4233 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4234 #define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4235 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4236 #define BCE_RXP_CFTQ_CMD_POP (1L<<30) 4237 #define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 4238 4239 #define BCE_RXP_CFTQ_CTL 0x000c53bc 4240 #define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4241 #define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4242 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4243 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4244 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4245 4246 #define BCE_RXP_FTQ_DATA 0x000c53c0 4247 #define BCE_RXP_FTQ_CMD 0x000c53f8 4248 #define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4249 #define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 4250 #define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4251 #define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4252 #define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4253 #define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 4254 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4255 #define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4256 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4257 #define BCE_RXP_FTQ_CMD_POP (1L<<30) 4258 #define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 4259 4260 #define BCE_RXP_FTQ_CTL 0x000c53fc 4261 #define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 4262 #define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4263 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4264 #define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4265 #define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4266 4267 #define BCE_RXP_SCRATCH 0x000e0000 4268 4269 4270 /* 4271 * com_reg definition 4272 * offset: 0x100000 4273 */ 4274 #define BCE_COM_CPU_MODE 0x00105000 4275 #define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 4276 #define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 4277 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4278 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4279 #define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4280 #define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4281 #define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 4282 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4283 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4284 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4285 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4286 4287 #define BCE_COM_CPU_STATE 0x00105004 4288 #define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 4289 #define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4290 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4291 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4292 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4293 #define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4294 #define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4295 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4296 #define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4297 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4298 #define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 4299 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4300 #define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4301 #define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4302 4303 #define BCE_COM_CPU_EVENT_MASK 0x00105008 4304 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4305 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4306 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4307 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4308 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4309 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4310 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4311 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4312 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4313 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4314 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4315 4316 #define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 4317 #define BCE_COM_CPU_INSTRUCTION 0x00105020 4318 #define BCE_COM_CPU_DATA_ACCESS 0x00105024 4319 #define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 4320 #define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4321 #define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4322 #define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 4323 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4324 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4325 4326 #define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4327 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4328 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4329 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4330 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4331 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4332 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4333 4334 #define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4335 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4336 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4337 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4338 #define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4339 4340 #define BCE_COM_CPU_REG_FILE 0x00105200 4341 #define BCE_COM_COMXQ_FTQ_DATA 0x00105340 4342 #define BCE_COM_COMXQ_FTQ_CMD 0x00105378 4343 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4344 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4345 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4346 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4347 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4348 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4349 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4350 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4351 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4352 #define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4353 #define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4354 4355 #define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 4356 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4357 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4358 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4359 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4360 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4361 4362 #define BCE_COM_COMTQ_FTQ_DATA 0x00105380 4363 #define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 4364 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4365 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4366 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4367 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4368 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4369 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4370 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4371 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4372 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4373 #define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4374 #define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4375 4376 #define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 4377 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4378 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4379 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4380 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4381 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4382 4383 #define BCE_COM_COMQ_FTQ_DATA 0x001053c0 4384 #define BCE_COM_COMQ_FTQ_CMD 0x001053f8 4385 #define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4386 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4387 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4388 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4389 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4390 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4391 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4392 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4393 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4394 #define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 4395 #define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4396 4397 #define BCE_COM_COMQ_FTQ_CTL 0x001053fc 4398 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4399 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4400 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4401 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4402 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4403 4404 #define BCE_COM_SCRATCH 0x00120000 4405 4406 4407 /* 4408 * cp_reg definition 4409 * offset: 0x180000 4410 */ 4411 #define BCE_CP_CPU_MODE 0x00185000 4412 #define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 4413 #define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 4414 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4415 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4416 #define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4417 #define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4418 #define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 4419 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4420 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4421 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4422 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4423 4424 #define BCE_CP_CPU_STATE 0x00185004 4425 #define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 4426 #define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4427 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4428 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4429 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4430 #define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4431 #define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4432 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4433 #define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4434 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4435 #define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 4436 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4437 #define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4438 #define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4439 4440 #define BCE_CP_CPU_EVENT_MASK 0x00185008 4441 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4442 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4443 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4444 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4445 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4446 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4447 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4448 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4449 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4450 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4451 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4452 4453 #define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 4454 #define BCE_CP_CPU_INSTRUCTION 0x00185020 4455 #define BCE_CP_CPU_DATA_ACCESS 0x00185024 4456 #define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 4457 #define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4458 #define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4459 #define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 4460 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4461 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4462 4463 #define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4464 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4465 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4466 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4467 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4468 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4469 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4470 4471 #define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4472 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4473 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4474 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4475 #define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4476 4477 #define BCE_CP_CPU_REG_FILE 0x00185200 4478 #define BCE_CP_CPQ_FTQ_DATA 0x001853c0 4479 #define BCE_CP_CPQ_FTQ_CMD 0x001853f8 4480 #define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4481 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4482 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4483 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4484 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4485 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4486 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4487 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4488 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4489 #define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 4490 #define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4491 4492 #define BCE_CP_CPQ_FTQ_CTL 0x001853fc 4493 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4494 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4495 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4496 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4497 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4498 4499 #define BCE_CP_SCRATCH 0x001a0000 4500 4501 4502 /* 4503 * tas_reg definition 4504 * offset: 0x1c0000 4505 */ 4506 #define BCE_TAS_FTQ_CMD 0x001c03f8 4507 #define BCE_TAS_FTQ_CTL 0x001c03fc 4508 #define BCE_TAS_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4509 #define BCE_TAS_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4510 4511 4512 /* 4513 * mcp_reg definition 4514 * offset: 0x140000 4515 */ 4516 #define BCE_MCP_CPU_MODE 0x00145000 4517 #define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4518 #define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 4519 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4520 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4521 #define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4522 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4523 #define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4524 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4525 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4526 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4527 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4528 4529 #define BCE_MCP_CPU_STATE 0x00145004 4530 #define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4531 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4532 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4533 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4534 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4535 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4536 #define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4537 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4538 #define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4539 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4540 #define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4541 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4542 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4543 #define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4544 4545 #define BCE_MCP_CPU_EVENT_MASK 0x00145008 4546 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4547 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4548 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4549 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4550 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4551 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4552 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4553 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4554 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4555 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4556 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4557 4558 #define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4559 #define BCE_MCP_CPU_INSTRUCTION 0x00145020 4560 #define BCE_MCP_CPU_DATA_ACCESS 0x00145024 4561 #define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4562 #define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4563 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4564 #define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 4565 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4566 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4567 4568 #define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4569 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4570 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4571 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4572 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4573 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4574 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4575 4576 #define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4577 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4578 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4579 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4580 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4581 4582 #define BCE_MCP_CPU_REG_FILE 0x00145200 4583 #define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 4584 #define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 4585 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4586 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4587 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4588 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4589 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4590 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4591 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4592 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4593 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4594 #define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4595 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4596 4597 #define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 4598 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4599 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4600 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4601 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4602 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4603 4604 #define BCE_MCP_ROM 0x00150000 4605 #define BCE_MCP_SCRATCH 0x00160000 4606 4607 #define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 4608 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4609 #define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 4610 #define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4611 #define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4612 4613 #define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 4614 #define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 4615 4616 /****************************************************************************/ 4617 /* End machine generated definitions. */ 4618 /****************************************************************************/ 4619 4620 /****************************************************************************/ 4621 /* Begin firmware definitions. */ 4622 /****************************************************************************/ 4623 /* The following definitions refer to pre-defined locations in processor */ 4624 /* memory space which allows the driver to enable particular functionality */ 4625 /* within the firmware or read specfic information about the running */ 4626 /* firmware. */ 4627 /****************************************************************************/ 4628 4629 /* 4630 * Perfect match control register. 4631 * 0 = Default. All received unicst packets matching MAC address 4632 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue 4633 * 0, all other perfect match registers are reserved. 4634 * 1 = All received unicast packets matching MAC address 4635 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0, 4636 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc. 4637 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register 4638 * are sent to receive queue 0. 4639 */ 4640 #define BCE_RXP_PM_CTRL 0x0e00d0 4641 4642 /* 4643 * This firmware statistic records the number of frames that 4644 * were dropped because there were no buffers available in the 4645 * receive chain. 4646 */ 4647 #define BCE_COM_NO_BUFFERS 0x120084 4648 /****************************************************************************/ 4649 /* End firmware definitions. */ 4650 /****************************************************************************/ 4651 4652 #define NUM_MC_HASH_REGISTERS 8 4653 4654 4655 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4656 #define PHY_BCM5706_PHY_ID 0x00206160 4657 4658 #define PHY_ID(id) ((id) & 0xfffffff0) 4659 #define PHY_REV_ID(id) ((id) & 0xf) 4660 4661 /* 5708 Serdes PHY registers */ 4662 4663 #define BCM5708S_UP1 0xb 4664 4665 #define BCM5708S_UP1_2G5 0x1 4666 4667 #define BCM5708S_BLK_ADDR 0x1f 4668 4669 #define BCM5708S_BLK_ADDR_DIG 0x0000 4670 #define BCM5708S_BLK_ADDR_DIG3 0x0002 4671 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4672 4673 /* Digital Block */ 4674 #define BCM5708S_1000X_CTL1 0x10 4675 4676 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4677 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4678 4679 #define BCM5708S_1000X_CTL2 0x11 4680 4681 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4682 4683 #define BCM5708S_1000X_STAT1 0x14 4684 4685 #define BCM5708S_1000X_STAT1_SGMII 0x0001 4686 #define BCM5708S_1000X_STAT1_LINK 0x0002 4687 #define BCM5708S_1000X_STAT1_FD 0x0004 4688 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4689 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4690 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4691 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4692 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4693 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4694 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4695 4696 /* Digital3 Block */ 4697 #define BCM5708S_DIG_3_0 0x10 4698 4699 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4700 4701 /* Tx/Misc Block */ 4702 #define BCM5708S_TX_ACTL1 0x15 4703 4704 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4705 4706 #define BCM5708S_TX_ACTL3 0x17 4707 4708 #define RX_COPY_THRESH 92 4709 4710 #define DMA_READ_CHANS 5 4711 #define DMA_WRITE_CHANS 3 4712 4713 /* Use the natural page size of the host CPU. */ 4714 /* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4715 #define BCM_PAGE_BITS PAGE_SHIFT 4716 #define BCM_PAGE_SIZE PAGE_SIZE 4717 #define BCM_PAGE_MASK (BCM_PAGE_SIZE - 1) 4718 #define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) >> BCM_PAGE_BITS) 4719 4720 /* 4721 * Page count must remain a power of 2 for all 4722 * of the math to work correctly. 4723 */ 4724 #define TX_PAGES 2 4725 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4726 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4727 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4728 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4729 #define MAX_TX_BD (TOTAL_TX_BD - 1) 4730 4731 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4732 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4733 (x) + 2 : (x) + 1 4734 4735 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4736 4737 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 4738 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4739 4740 /* 4741 * Page count must remain a power of 2 for all 4742 * of the math to work correctly. 4743 */ 4744 #define RX_PAGES 2 4745 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4746 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4747 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4748 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4749 #define MAX_RX_BD (TOTAL_RX_BD - 1) 4750 4751 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4752 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4753 (x) + 2 : (x) + 1 4754 4755 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4756 4757 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 4758 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4759 4760 /* 4761 * To accomodate jumbo frames, the page chain should 4762 * be 4 times larger than the receive chain. 4763 */ 4764 #define PG_PAGES (RX_PAGES * 4) 4765 #define TOTAL_PG_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4766 #define USABLE_PG_BD_PER_PAGE (TOTAL_PG_BD_PER_PAGE - 1) 4767 #define TOTAL_PG_BD (TOTAL_PG_BD_PER_PAGE * PG_PAGES) 4768 #define USABLE_PG_BD (USABLE_PG_BD_PER_PAGE * PG_PAGES) 4769 #define MAX_PG_BD (TOTAL_PG_BD - 1) 4770 4771 #define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) == \ 4772 (USABLE_PG_BD_PER_PAGE - 1)) ? \ 4773 (x) + 2 : (x) + 1 4774 4775 #define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD) 4776 4777 #define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 4778 #define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE) 4779 4780 /* Context size. */ 4781 #define CTX_SHIFT 7 4782 #define CTX_SIZE (1 << CTX_SHIFT) 4783 #define CTX_MASK (CTX_SIZE - 1) 4784 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4785 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4786 4787 #define PHY_CTX_SHIFT 6 4788 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4789 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4790 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4791 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4792 4793 #define MB_KERNEL_CTX_SHIFT 8 4794 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4795 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4796 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4797 4798 #define MAX_CID_CNT 0x4000 4799 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4800 #define INVALID_CID_ADDR 0xffffffff 4801 4802 #define TX_CID 16 4803 #define RX_CID 0 4804 4805 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4806 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4807 4808 /****************************************************************************/ 4809 /* BCE Processor Firmwware Load Definitions */ 4810 /****************************************************************************/ 4811 4812 struct cpu_reg { 4813 u32 mode; 4814 u32 mode_value_halt; 4815 u32 mode_value_sstep; 4816 4817 u32 state; 4818 u32 state_value_clear; 4819 4820 u32 gpr0; 4821 u32 evmask; 4822 u32 pc; 4823 u32 inst; 4824 u32 bp; 4825 4826 u32 spad_base; 4827 4828 u32 mips_view_base; 4829 }; 4830 4831 struct fw_info { 4832 u32 ver_major; 4833 u32 ver_minor; 4834 u32 ver_fix; 4835 4836 u32 start_addr; 4837 4838 /* Text section. */ 4839 u32 text_addr; 4840 u32 text_len; 4841 u32 text_index; 4842 u32 *text; 4843 4844 /* Data section. */ 4845 u32 data_addr; 4846 u32 data_len; 4847 u32 data_index; 4848 u32 *data; 4849 4850 /* SBSS section. */ 4851 u32 sbss_addr; 4852 u32 sbss_len; 4853 u32 sbss_index; 4854 u32 *sbss; 4855 4856 /* BSS section. */ 4857 u32 bss_addr; 4858 u32 bss_len; 4859 u32 bss_index; 4860 u32 *bss; 4861 4862 /* Read-only section. */ 4863 u32 rodata_addr; 4864 u32 rodata_len; 4865 u32 rodata_index; 4866 u32 *rodata; 4867 }; 4868 4869 #define RV2P_PROC1 0 4870 #define RV2P_PROC2 1 4871 4872 #define BCE_MIREG(x) ((x & 0x1F) << 16) 4873 #define BCE_MIPHY(x) ((x & 0x1F) << 21) 4874 #define BCE_PHY_TIMEOUT 50 4875 4876 #define BCE_NVRAM_SIZE 0x200 4877 #define BCE_NVRAM_MAGIC 0x669955aa 4878 #define BCE_CRC32_RESIDUAL 0xdebb20e3 4879 4880 #define BCE_TX_TIMEOUT 5 4881 4882 #define BCE_MAX_SEGMENTS 32 4883 #define BCE_TSO_MAX_SIZE 65536 4884 #define BCE_TSO_MAX_SEG_SIZE 4096 4885 4886 #define BCE_DMA_ALIGN 8 4887 #define BCE_DMA_BOUNDARY 0 4888 4889 /* The BCM5708 has a problem with addresses greater that 40bits. */ 4890 /* Handle the sizing issue in an architecture agnostic fashion. */ 4891 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 4892 #define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 4893 #else 4894 #define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 4895 #endif 4896 4897 /* 4898 * XXX Checksum offload involving IP fragments seems to cause problems on 4899 * transmit. Disable it for now, hopefully there will be a more elegant 4900 * solution later. 4901 */ 4902 #ifdef BCE_IP_CSUM 4903 #define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 4904 #else 4905 #define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) 4906 #endif 4907 4908 #if __FreeBSD_version < 700000 4909 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4910 IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 4911 #else 4912 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4913 IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) 4914 #endif 4915 4916 #define BCE_MIN_MTU 60 4917 #define BCE_MIN_ETHER_MTU 64 4918 4919 #define BCE_MAX_STD_MTU 1500 4920 #define BCE_MAX_STD_ETHER_MTU 1518 4921 #define BCE_MAX_STD_ETHER_MTU_VLAN 1522 4922 4923 #define BCE_MAX_JUMBO_MTU 9000 4924 #define BCE_MAX_JUMBO_ETHER_MTU 9018 4925 #define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 4926 4927 // #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ 4928 4929 /****************************************************************************/ 4930 /* BCE Device State Data Structure */ 4931 /****************************************************************************/ 4932 4933 #define BCE_STATUS_BLK_SZ sizeof(struct status_block) 4934 #define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 4935 #define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4936 #define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4937 #define BCE_PG_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4938 4939 struct bce_softc 4940 { 4941 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */ 4942 struct ifnet *bce_ifp; /* Interface info */ 4943 device_t bce_dev; /* Parent device handle */ 4944 u_int8_t bce_unit; /* Interface number */ 4945 struct resource *bce_res_mem; /* Device resource handle */ 4946 struct ifmedia bce_ifmedia; /* TBI media info */ 4947 bus_space_tag_t bce_btag; /* Device bus tag */ 4948 bus_space_handle_t bce_bhandle; /* Device bus handle */ 4949 vm_offset_t bce_vhandle; /* Device virtual memory handle */ 4950 struct resource *bce_res_irq; /* IRQ Resource Handle */ 4951 struct mtx bce_mtx; /* Mutex */ 4952 void *bce_intrhand; /* Interrupt handler */ 4953 4954 /* ASIC Chip ID. */ 4955 u32 bce_chipid; 4956 4957 /* General controller flags. */ 4958 u32 bce_flags; 4959 #define BCE_PCIX_FLAG 0x00000001 4960 #define BCE_PCI_32BIT_FLAG 0x00000002 4961 #define BCE_ONE_TDMA_FLAG 0x00000004 /* Deprecated */ 4962 #define BCE_NO_WOL_FLAG 0x00000008 4963 #define BCE_USING_DAC_FLAG 0x00000010 4964 #define BCE_USING_MSI_FLAG 0x00000020 4965 #define BCE_MFW_ENABLE_FLAG 0x00000040 4966 4967 /* PHY specific flags. */ 4968 u32 bce_phy_flags; 4969 #define BCE_PHY_SERDES_FLAG 0x00000001 4970 #define BCE_PHY_CRC_FIX_FLAG 0x00000002 4971 #define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004 4972 #define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008 4973 #define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300 4974 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100 4975 #define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200 4976 4977 /* Values that need to be shared with the PHY driver. */ 4978 u32 bce_shared_hw_cfg; 4979 u32 bce_port_hw_cfg; 4980 4981 bus_addr_t max_bus_addr; 4982 u16 bus_speed_mhz; /* PCI bus speed */ 4983 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */ 4984 u32 bce_flash_size; /* Flash NVRAM size */ 4985 u32 bce_shmem_base; /* Shared Memory base address */ 4986 char * bce_name; /* Name string */ 4987 4988 /* Tracks the version of bootcode firmware. */ 4989 u32 bce_fw_ver; 4990 4991 /* Tracks the state of the firmware. 0 = Running while any */ 4992 /* other value indicates that the firmware is not responding. */ 4993 u16 bce_fw_timed_out; 4994 4995 /* An incrementing sequence used to coordinate messages passed */ 4996 /* from the driver to the firmware. */ 4997 u16 bce_fw_wr_seq; 4998 4999 /* An incrementing sequence used to let the firmware know that */ 5000 /* the driver is still operating. Without the pulse, management */ 5001 /* firmware such as IPMI or UMP will operate in OS absent state. */ 5002 u16 bce_fw_drv_pulse_wr_seq; 5003 5004 /* Ethernet MAC address. */ 5005 u_char eaddr[6]; 5006 5007 /* These setting are used by the host coalescing (HC) block to */ 5008 /* to control how often the status block, statistics block and */ 5009 /* interrupts are generated. */ 5010 u16 bce_tx_quick_cons_trip_int; 5011 u16 bce_tx_quick_cons_trip; 5012 u16 bce_rx_quick_cons_trip_int; 5013 u16 bce_rx_quick_cons_trip; 5014 u16 bce_comp_prod_trip_int; 5015 u16 bce_comp_prod_trip; 5016 u16 bce_tx_ticks_int; 5017 u16 bce_tx_ticks; 5018 u16 bce_rx_ticks_int; 5019 u16 bce_rx_ticks; 5020 u16 bce_com_ticks_int; 5021 u16 bce_com_ticks; 5022 u16 bce_cmd_ticks_int; 5023 u16 bce_cmd_ticks; 5024 u32 bce_stats_ticks; 5025 5026 /* The address of the integrated PHY on the MII bus. */ 5027 int bce_phy_addr; 5028 5029 /* The device handle for the MII bus child device. */ 5030 device_t bce_miibus; 5031 5032 /* Driver maintained TX chain pointers and byte counter. */ 5033 u16 rx_prod; 5034 u16 rx_cons; 5035 u32 rx_prod_bseq; /* Counts the bytes used. */ 5036 u16 tx_prod; 5037 u16 tx_cons; 5038 u32 tx_prod_bseq; /* Counts the bytes used. */ 5039 u16 pg_prod; 5040 u16 pg_cons; 5041 5042 int bce_link; 5043 struct callout bce_tick_callout; 5044 struct callout bce_pulse_callout; 5045 5046 int watchdog_timer; /* ticks until chip reset */ 5047 5048 /* Frame size and mbuf allocation size for RX frames. */ 5049 u32 max_frame_size; 5050 int rx_bd_mbuf_alloc_size; 5051 int pg_bd_mbuf_alloc_size; 5052 5053 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 5054 u32 rx_mode; 5055 5056 #ifdef DEVICE_POLLING 5057 int bce_rxcycles; /* Counter for receive polling cycles */ 5058 #endif 5059 5060 /* Bus tag for the bce controller. */ 5061 bus_dma_tag_t parent_tag; 5062 5063 /* H/W maintained TX buffer descriptor chain structure. */ 5064 bus_dma_tag_t tx_bd_chain_tag; 5065 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 5066 struct tx_bd *tx_bd_chain[TX_PAGES]; 5067 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 5068 5069 /* H/W maintained RX buffer descriptor chain structure. */ 5070 bus_dma_tag_t rx_bd_chain_tag; 5071 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 5072 struct rx_bd *rx_bd_chain[RX_PAGES]; 5073 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 5074 5075 /* H/W maintained page buffer descriptor chain structure. */ 5076 bus_dma_tag_t pg_bd_chain_tag; 5077 bus_dmamap_t pg_bd_chain_map[PG_PAGES]; 5078 struct rx_bd *pg_bd_chain[PG_PAGES]; 5079 bus_addr_t pg_bd_chain_paddr[PG_PAGES]; 5080 5081 /* H/W maintained status block. */ 5082 bus_dma_tag_t status_tag; 5083 bus_dmamap_t status_map; 5084 struct status_block *status_block; /* virtual address */ 5085 bus_addr_t status_block_paddr; /* Physical address */ 5086 5087 /* Driver maintained status block values. */ 5088 u16 last_status_idx; 5089 u16 hw_rx_cons; 5090 u16 hw_tx_cons; 5091 5092 /* H/W maintained statistics block. */ 5093 bus_dma_tag_t stats_tag; 5094 bus_dmamap_t stats_map; 5095 struct statistics_block *stats_block; /* Virtual address */ 5096 bus_addr_t stats_block_paddr; /* Physical address */ 5097 5098 /* Bus tag for RX/TX mbufs. */ 5099 bus_dma_tag_t rx_mbuf_tag; 5100 bus_dma_tag_t tx_mbuf_tag; 5101 bus_dma_tag_t pg_mbuf_tag; 5102 5103 /* S/W maintained mbuf TX chain structure. */ 5104 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 5105 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 5106 5107 /* S/W maintained mbuf RX chain structure. */ 5108 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 5109 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 5110 5111 /* S/W maintained mbuf page chain structure. */ 5112 bus_dmamap_t pg_mbuf_map[TOTAL_PG_BD]; 5113 struct mbuf *pg_mbuf_ptr[TOTAL_PG_BD]; 5114 5115 /* Track the number of buffer descriptors in use. */ 5116 u16 free_rx_bd; 5117 u16 max_rx_bd; 5118 u16 used_tx_bd; 5119 u16 max_tx_bd; 5120 u16 free_pg_bd; 5121 u16 max_pg_bd; 5122 5123 /* Provides access to hardware statistics through sysctl. */ 5124 u64 stat_IfHCInOctets; 5125 u64 stat_IfHCInBadOctets; 5126 u64 stat_IfHCOutOctets; 5127 u64 stat_IfHCOutBadOctets; 5128 u64 stat_IfHCInUcastPkts; 5129 u64 stat_IfHCInMulticastPkts; 5130 u64 stat_IfHCInBroadcastPkts; 5131 u64 stat_IfHCOutUcastPkts; 5132 u64 stat_IfHCOutMulticastPkts; 5133 u64 stat_IfHCOutBroadcastPkts; 5134 5135 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5136 u32 stat_Dot3StatsCarrierSenseErrors; 5137 u32 stat_Dot3StatsFCSErrors; 5138 u32 stat_Dot3StatsAlignmentErrors; 5139 u32 stat_Dot3StatsSingleCollisionFrames; 5140 u32 stat_Dot3StatsMultipleCollisionFrames; 5141 u32 stat_Dot3StatsDeferredTransmissions; 5142 u32 stat_Dot3StatsExcessiveCollisions; 5143 u32 stat_Dot3StatsLateCollisions; 5144 u32 stat_EtherStatsCollisions; 5145 u32 stat_EtherStatsFragments; 5146 u32 stat_EtherStatsJabbers; 5147 u32 stat_EtherStatsUndersizePkts; 5148 u32 stat_EtherStatsOverrsizePkts; 5149 u32 stat_EtherStatsPktsRx64Octets; 5150 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 5151 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 5152 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 5153 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 5154 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 5155 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 5156 u32 stat_EtherStatsPktsTx64Octets; 5157 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 5158 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 5159 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 5160 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 5161 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 5162 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 5163 u32 stat_XonPauseFramesReceived; 5164 u32 stat_XoffPauseFramesReceived; 5165 u32 stat_OutXonSent; 5166 u32 stat_OutXoffSent; 5167 u32 stat_FlowControlDone; 5168 u32 stat_MacControlFramesReceived; 5169 u32 stat_XoffStateEntered; 5170 u32 stat_IfInFramesL2FilterDiscards; 5171 u32 stat_IfInRuleCheckerDiscards; 5172 u32 stat_IfInFTQDiscards; 5173 u32 stat_IfInMBUFDiscards; 5174 u32 stat_IfInRuleCheckerP4Hit; 5175 u32 stat_CatchupInRuleCheckerDiscards; 5176 u32 stat_CatchupInFTQDiscards; 5177 u32 stat_CatchupInMBUFDiscards; 5178 u32 stat_CatchupInRuleCheckerP4Hit; 5179 5180 /* Provides access to certain firmware statistics. */ 5181 u32 com_no_buffers; 5182 5183 /* Mbuf allocation failure counter. */ 5184 u32 mbuf_alloc_failed; 5185 5186 /* TX DMA mapping failure counter. */ 5187 u32 tx_dma_map_failures; 5188 5189 u64 rx_intr_time; 5190 5191 #ifdef BCE_DEBUG 5192 /* Track the number of enqueued mbufs. */ 5193 int debug_tx_mbuf_alloc; 5194 int debug_rx_mbuf_alloc; 5195 int debug_pg_mbuf_alloc; 5196 5197 /* Track how many and what type of interrupts are generated. */ 5198 u32 interrupts_generated; 5199 u32 interrupts_handled; 5200 u32 rx_interrupts; 5201 u32 tx_interrupts; 5202 5203 /* Track interrupt time (25MHz clock). */ 5204 u64 tx_intr_time; 5205 5206 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */ 5207 u32 rx_empty_count; /* Number of times the RX chain was empty. */ 5208 5209 u32 pg_low_watermark; /* Lowest number of pages free. */ 5210 u32 pg_empty_count; /* Number of times the page chain was empty. */ 5211 5212 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */ 5213 u32 tx_full_count; /* Number of times the TX chain was full. */ 5214 5215 /* Simulated mbuf allocation failure counter. */ 5216 u32 debug_mbuf_sim_alloc_failed; 5217 5218 u32 l2fhdr_status_errors; 5219 u32 unexpected_attentions; 5220 u32 lost_status_block_updates; 5221 5222 u32 requested_tso_frames; /* Number of TSO frames enqueued. */ 5223 #endif 5224 }; 5225 5226 #endif /* #ifndef _BCE_H_DEFINED */ 5227 5228