1 /*- 2 * Copyright (c) 2006-2014 QLogic Corporation 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * The following controllers are supported by this driver: 32 * BCM5706C A2, A3 33 * BCM5706S A2, A3 34 * BCM5708C B1, B2 35 * BCM5708S B1, B2 36 * BCM5709C A1, C0 37 * BCM5709S A1, C0 38 * BCM5716C C0 39 * BCM5716S C0 40 * 41 * The following controllers are not supported by this driver: 42 * BCM5706C A0, A1 (pre-production) 43 * BCM5706S A0, A1 (pre-production) 44 * BCM5708C A0, B0 (pre-production) 45 * BCM5708S A0, B0 (pre-production) 46 * BCM5709C A0 B0, B1, B2 (pre-production) 47 * BCM5709S A0, B0, B1, B2 (pre-production) 48 */ 49 50 #include "opt_bce.h" 51 52 #include <sys/param.h> 53 #include <sys/endian.h> 54 #include <sys/systm.h> 55 #include <sys/sockio.h> 56 #include <sys/lock.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/kernel.h> 61 #include <sys/module.h> 62 #include <sys/socket.h> 63 #include <sys/sysctl.h> 64 #include <sys/queue.h> 65 66 #include <net/bpf.h> 67 #include <net/ethernet.h> 68 #include <net/if.h> 69 #include <net/if_var.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <netinet/in_systm.h> 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #include <netinet/ip.h> 81 #include <netinet/ip6.h> 82 #include <netinet/tcp.h> 83 #include <netinet/udp.h> 84 85 #include <machine/bus.h> 86 #include <machine/resource.h> 87 #include <sys/bus.h> 88 #include <sys/rman.h> 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 #include "miidevs.h" 93 #include <dev/mii/brgphyreg.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 98 #include "miibus_if.h" 99 100 #include <dev/bce/if_bcereg.h> 101 #include <dev/bce/if_bcefw.h> 102 103 /****************************************************************************/ 104 /* BCE Debug Options */ 105 /****************************************************************************/ 106 #ifdef BCE_DEBUG 107 u32 bce_debug = BCE_WARN; 108 109 /* 0 = Never */ 110 /* 1 = 1 in 2,147,483,648 */ 111 /* 256 = 1 in 8,388,608 */ 112 /* 2048 = 1 in 1,048,576 */ 113 /* 65536 = 1 in 32,768 */ 114 /* 1048576 = 1 in 2,048 */ 115 /* 268435456 = 1 in 8 */ 116 /* 536870912 = 1 in 4 */ 117 /* 1073741824 = 1 in 2 */ 118 119 /* Controls how often the l2_fhdr frame error check will fail. */ 120 int l2fhdr_error_sim_control = 0; 121 122 /* Controls how often the unexpected attention check will fail. */ 123 int unexpected_attention_sim_control = 0; 124 125 /* Controls how often to simulate an mbuf allocation failure. */ 126 int mbuf_alloc_failed_sim_control = 0; 127 128 /* Controls how often to simulate a DMA mapping failure. */ 129 int dma_map_addr_failed_sim_control = 0; 130 131 /* Controls how often to simulate a bootcode failure. */ 132 int bootcode_running_failure_sim_control = 0; 133 #endif 134 135 /****************************************************************************/ 136 /* PCI Device ID Table */ 137 /* */ 138 /* Used by bce_probe() to identify the devices supported by this driver. */ 139 /****************************************************************************/ 140 #define BCE_DEVDESC_MAX 64 141 142 static const struct bce_type bce_devs[] = { 143 /* BCM5706C Controllers and OEM boards. */ 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 145 "HP NC370T Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 147 "HP NC370i Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 151 "HP NC371i Multifunction Gigabit Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 153 "QLogic NetXtreme II BCM5706 1000Base-T" }, 154 155 /* BCM5706S controllers and OEM boards. */ 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 157 "HP NC370F Multifunction Gigabit Server Adapter" }, 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 159 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 160 161 /* BCM5708C controllers and OEM boards. */ 162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 163 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 165 "HP NC373i Multifunction Gigabit Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 167 "HP NC374m PCIe Multifunction Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 169 "QLogic NetXtreme II BCM5708 1000Base-T" }, 170 171 /* BCM5708S controllers and OEM boards. */ 172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 173 "HP NC373m Multifunction Gigabit Server Adapter" }, 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 175 "HP NC373i Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 177 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 179 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 180 181 /* BCM5709C controllers and OEM boards. */ 182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 183 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 187 "QLogic NetXtreme II BCM5709 1000Base-T" }, 188 189 /* BCM5709S controllers and OEM boards. */ 190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 193 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 195 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 196 197 /* BCM5716 controllers and OEM boards. */ 198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 199 "QLogic NetXtreme II BCM5716 1000Base-T" }, 200 201 { 0, 0, 0, 0, NULL } 202 }; 203 204 205 /****************************************************************************/ 206 /* Supported Flash NVRAM device data. */ 207 /****************************************************************************/ 208 static const struct flash_spec flash_table[] = 209 { 210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 211 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 212 213 /* Slow EEPROM */ 214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 217 "EEPROM - slow"}, 218 /* Expansion entry 0001 */ 219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 222 "Entry 0001"}, 223 /* Saifun SA25F010 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 228 "Non-buffered flash (128kB)"}, 229 /* Saifun SA25F020 (non-buffered flash) */ 230 /* strap, cfg1, & write1 need updates */ 231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 234 "Non-buffered flash (256kB)"}, 235 /* Expansion entry 0100 */ 236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 0100"}, 240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 250 /* Saifun SA25F005 (non-buffered flash) */ 251 /* strap, cfg1, & write1 need updates */ 252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 255 "Non-buffered flash (64kB)"}, 256 /* Fast EEPROM */ 257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 260 "EEPROM - fast"}, 261 /* Expansion entry 1001 */ 262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1001"}, 266 /* Expansion entry 1010 */ 267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 270 "Entry 1010"}, 271 /* ATMEL AT45DB011B (buffered flash) */ 272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 275 "Buffered flash (128kB)"}, 276 /* Expansion entry 1100 */ 277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 280 "Entry 1100"}, 281 /* Expansion entry 1101 */ 282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 285 "Entry 1101"}, 286 /* Ateml Expansion entry 1110 */ 287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 290 "Entry 1110 (Atmel)"}, 291 /* ATMEL AT45DB021B (buffered flash) */ 292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 295 "Buffered flash (256kB)"}, 296 }; 297 298 /* 299 * The BCM5709 controllers transparently handle the 300 * differences between Atmel 264 byte pages and all 301 * flash devices which use 256 byte pages, so no 302 * logical-to-physical mapping is required in the 303 * driver. 304 */ 305 static const struct flash_spec flash_5709 = { 306 .flags = BCE_NV_BUFFERED, 307 .page_bits = BCM5709_FLASH_PAGE_BITS, 308 .page_size = BCM5709_FLASH_PAGE_SIZE, 309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 311 .name = "5709/5716 buffered flash (256kB)", 312 }; 313 314 315 /****************************************************************************/ 316 /* FreeBSD device entry points. */ 317 /****************************************************************************/ 318 static int bce_probe (device_t); 319 static int bce_attach (device_t); 320 static int bce_detach (device_t); 321 static int bce_shutdown (device_t); 322 323 324 /****************************************************************************/ 325 /* BCE Debug Data Structure Dump Routines */ 326 /****************************************************************************/ 327 #ifdef BCE_DEBUG 328 static u32 bce_reg_rd (struct bce_softc *, u32); 329 static void bce_reg_wr (struct bce_softc *, u32, u32); 330 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 331 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 332 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 333 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 334 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 335 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 336 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 337 static void bce_dump_txbd (struct bce_softc *, 338 int, struct tx_bd *); 339 static void bce_dump_rxbd (struct bce_softc *, 340 int, struct rx_bd *); 341 static void bce_dump_pgbd (struct bce_softc *, 342 int, struct rx_bd *); 343 static void bce_dump_l2fhdr (struct bce_softc *, 344 int, struct l2_fhdr *); 345 static void bce_dump_ctx (struct bce_softc *, u16); 346 static void bce_dump_ftqs (struct bce_softc *); 347 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 348 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 349 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 350 static void bce_dump_status_block (struct bce_softc *); 351 static void bce_dump_stats_block (struct bce_softc *); 352 static void bce_dump_driver_state (struct bce_softc *); 353 static void bce_dump_hw_state (struct bce_softc *); 354 static void bce_dump_shmem_state (struct bce_softc *); 355 static void bce_dump_mq_regs (struct bce_softc *); 356 static void bce_dump_bc_state (struct bce_softc *); 357 static void bce_dump_txp_state (struct bce_softc *, int); 358 static void bce_dump_rxp_state (struct bce_softc *, int); 359 static void bce_dump_tpat_state (struct bce_softc *, int); 360 static void bce_dump_cp_state (struct bce_softc *, int); 361 static void bce_dump_com_state (struct bce_softc *, int); 362 static void bce_dump_rv2p_state (struct bce_softc *); 363 static void bce_breakpoint (struct bce_softc *); 364 #endif /*BCE_DEBUG */ 365 366 367 /****************************************************************************/ 368 /* BCE Register/Memory Access Routines */ 369 /****************************************************************************/ 370 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 371 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 372 static void bce_shmem_wr (struct bce_softc *, u32, u32); 373 static u32 bce_shmem_rd (struct bce_softc *, u32); 374 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 375 static int bce_miibus_read_reg (device_t, int, int); 376 static int bce_miibus_write_reg (device_t, int, int, int); 377 static void bce_miibus_statchg (device_t); 378 379 #ifdef BCE_DEBUG 380 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 381 #ifdef BCE_NVRAM_WRITE_SUPPORT 382 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 383 #endif 384 #endif 385 386 /****************************************************************************/ 387 /* BCE NVRAM Access Routines */ 388 /****************************************************************************/ 389 static int bce_acquire_nvram_lock (struct bce_softc *); 390 static int bce_release_nvram_lock (struct bce_softc *); 391 static void bce_enable_nvram_access(struct bce_softc *); 392 static void bce_disable_nvram_access(struct bce_softc *); 393 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 394 static int bce_init_nvram (struct bce_softc *); 395 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 396 static int bce_nvram_test (struct bce_softc *); 397 #ifdef BCE_NVRAM_WRITE_SUPPORT 398 static int bce_enable_nvram_write (struct bce_softc *); 399 static void bce_disable_nvram_write(struct bce_softc *); 400 static int bce_nvram_erase_page (struct bce_softc *, u32); 401 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 402 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 403 #endif 404 405 /****************************************************************************/ 406 /* */ 407 /****************************************************************************/ 408 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 409 static void bce_get_media (struct bce_softc *); 410 static void bce_init_media (struct bce_softc *); 411 static u32 bce_get_rphy_link (struct bce_softc *); 412 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 413 static int bce_dma_alloc (device_t); 414 static void bce_dma_free (struct bce_softc *); 415 static void bce_release_resources (struct bce_softc *); 416 417 /****************************************************************************/ 418 /* BCE Firmware Synchronization and Load */ 419 /****************************************************************************/ 420 static void bce_fw_cap_init (struct bce_softc *); 421 static int bce_fw_sync (struct bce_softc *, u32); 422 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 423 u32); 424 static void bce_load_cpu_fw (struct bce_softc *, 425 struct cpu_reg *, struct fw_info *); 426 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 427 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 428 static void bce_start_rxp_cpu (struct bce_softc *); 429 static void bce_init_rxp_cpu (struct bce_softc *); 430 static void bce_init_txp_cpu (struct bce_softc *); 431 static void bce_init_tpat_cpu (struct bce_softc *); 432 static void bce_init_cp_cpu (struct bce_softc *); 433 static void bce_init_com_cpu (struct bce_softc *); 434 static void bce_init_cpus (struct bce_softc *); 435 436 static void bce_print_adapter_info (struct bce_softc *); 437 static void bce_probe_pci_caps (device_t, struct bce_softc *); 438 static void bce_stop (struct bce_softc *); 439 static int bce_reset (struct bce_softc *, u32); 440 static int bce_chipinit (struct bce_softc *); 441 static int bce_blockinit (struct bce_softc *); 442 443 static int bce_init_tx_chain (struct bce_softc *); 444 static void bce_free_tx_chain (struct bce_softc *); 445 446 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 447 static int bce_init_rx_chain (struct bce_softc *); 448 static void bce_fill_rx_chain (struct bce_softc *); 449 static void bce_free_rx_chain (struct bce_softc *); 450 451 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 452 static int bce_init_pg_chain (struct bce_softc *); 453 static void bce_fill_pg_chain (struct bce_softc *); 454 static void bce_free_pg_chain (struct bce_softc *); 455 456 static struct mbuf *bce_tso_setup (struct bce_softc *, 457 struct mbuf **, u16 *); 458 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 459 static void bce_start_locked (struct ifnet *); 460 static void bce_start (struct ifnet *); 461 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 462 static void bce_watchdog (struct bce_softc *); 463 static int bce_ifmedia_upd (struct ifnet *); 464 static int bce_ifmedia_upd_locked (struct ifnet *); 465 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 466 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 467 static void bce_init_locked (struct bce_softc *); 468 static void bce_init (void *); 469 static void bce_mgmt_init_locked (struct bce_softc *sc); 470 471 static int bce_init_ctx (struct bce_softc *); 472 static void bce_get_mac_addr (struct bce_softc *); 473 static void bce_set_mac_addr (struct bce_softc *); 474 static void bce_phy_intr (struct bce_softc *); 475 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 476 static void bce_rx_intr (struct bce_softc *); 477 static void bce_tx_intr (struct bce_softc *); 478 static void bce_disable_intr (struct bce_softc *); 479 static void bce_enable_intr (struct bce_softc *, int); 480 481 static void bce_intr (void *); 482 static void bce_set_rx_mode (struct bce_softc *); 483 static void bce_stats_update (struct bce_softc *); 484 static void bce_tick (void *); 485 static void bce_pulse (void *); 486 static void bce_add_sysctls (struct bce_softc *); 487 488 489 /****************************************************************************/ 490 /* FreeBSD device dispatch table. */ 491 /****************************************************************************/ 492 static device_method_t bce_methods[] = { 493 /* Device interface (device_if.h) */ 494 DEVMETHOD(device_probe, bce_probe), 495 DEVMETHOD(device_attach, bce_attach), 496 DEVMETHOD(device_detach, bce_detach), 497 DEVMETHOD(device_shutdown, bce_shutdown), 498 /* Supported by device interface but not used here. */ 499 /* DEVMETHOD(device_identify, bce_identify), */ 500 /* DEVMETHOD(device_suspend, bce_suspend), */ 501 /* DEVMETHOD(device_resume, bce_resume), */ 502 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 503 504 /* MII interface (miibus_if.h) */ 505 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 506 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 507 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 508 /* Supported by MII interface but not used here. */ 509 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 510 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 511 512 DEVMETHOD_END 513 }; 514 515 static driver_t bce_driver = { 516 "bce", 517 bce_methods, 518 sizeof(struct bce_softc) 519 }; 520 521 static devclass_t bce_devclass; 522 523 MODULE_DEPEND(bce, pci, 1, 1, 1); 524 MODULE_DEPEND(bce, ether, 1, 1, 1); 525 MODULE_DEPEND(bce, miibus, 1, 1, 1); 526 527 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 528 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 529 530 531 /****************************************************************************/ 532 /* Tunable device values */ 533 /****************************************************************************/ 534 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 535 536 /* Allowable values are TRUE or FALSE */ 537 static int bce_verbose = TRUE; 538 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 539 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 540 "Verbose output enable/disable"); 541 542 /* Allowable values are TRUE or FALSE */ 543 static int bce_tso_enable = TRUE; 544 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 545 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 546 "TSO Enable/Disable"); 547 548 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 549 /* ToDo: Add MSI-X support. */ 550 static int bce_msi_enable = 1; 551 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 552 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 553 "MSI-X|MSI|INTx selector"); 554 555 /* Allowable values are 1, 2, 4, 8. */ 556 static int bce_rx_pages = DEFAULT_RX_PAGES; 557 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 558 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 559 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 560 561 /* Allowable values are 1, 2, 4, 8. */ 562 static int bce_tx_pages = DEFAULT_TX_PAGES; 563 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 564 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 565 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 566 567 /* Allowable values are TRUE or FALSE. */ 568 static int bce_hdr_split = TRUE; 569 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 570 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 571 "Frame header/payload splitting Enable/Disable"); 572 573 /* Allowable values are TRUE or FALSE. */ 574 static int bce_strict_rx_mtu = FALSE; 575 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 576 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 577 &bce_strict_rx_mtu, 0, 578 "Enable/Disable strict RX frame size checking"); 579 580 /* Allowable values are 0 ... 100 */ 581 #ifdef BCE_DEBUG 582 /* Generate 1 interrupt for every transmit completion. */ 583 static int bce_tx_quick_cons_trip_int = 1; 584 #else 585 /* Generate 1 interrupt for every 20 transmit completions. */ 586 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 587 #endif 588 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 589 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 590 &bce_tx_quick_cons_trip_int, 0, 591 "Transmit BD trip point during interrupts"); 592 593 /* Allowable values are 0 ... 100 */ 594 /* Generate 1 interrupt for every transmit completion. */ 595 #ifdef BCE_DEBUG 596 static int bce_tx_quick_cons_trip = 1; 597 #else 598 /* Generate 1 interrupt for every 20 transmit completions. */ 599 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 600 #endif 601 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 602 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 603 &bce_tx_quick_cons_trip, 0, 604 "Transmit BD trip point"); 605 606 /* Allowable values are 0 ... 100 */ 607 #ifdef BCE_DEBUG 608 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 609 static int bce_tx_ticks_int = 0; 610 #else 611 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 612 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 613 #endif 614 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 615 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 616 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 617 618 /* Allowable values are 0 ... 100 */ 619 #ifdef BCE_DEBUG 620 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 621 static int bce_tx_ticks = 0; 622 #else 623 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 624 static int bce_tx_ticks = DEFAULT_TX_TICKS; 625 #endif 626 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 627 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 628 &bce_tx_ticks, 0, "Transmit ticks count"); 629 630 /* Allowable values are 1 ... 100 */ 631 #ifdef BCE_DEBUG 632 /* Generate 1 interrupt for every received frame. */ 633 static int bce_rx_quick_cons_trip_int = 1; 634 #else 635 /* Generate 1 interrupt for every 6 received frames. */ 636 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 637 #endif 638 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 639 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 640 &bce_rx_quick_cons_trip_int, 0, 641 "Receive BD trip point duirng interrupts"); 642 643 /* Allowable values are 1 ... 100 */ 644 #ifdef BCE_DEBUG 645 /* Generate 1 interrupt for every received frame. */ 646 static int bce_rx_quick_cons_trip = 1; 647 #else 648 /* Generate 1 interrupt for every 6 received frames. */ 649 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 650 #endif 651 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 652 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 653 &bce_rx_quick_cons_trip, 0, 654 "Receive BD trip point"); 655 656 /* Allowable values are 0 ... 100 */ 657 #ifdef BCE_DEBUG 658 /* Generate an int. if 0us have elapsed since the last received frame. */ 659 static int bce_rx_ticks_int = 0; 660 #else 661 /* Generate an int. if 18us have elapsed since the last received frame. */ 662 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 663 #endif 664 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 665 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 666 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 667 668 /* Allowable values are 0 ... 100 */ 669 #ifdef BCE_DEBUG 670 /* Generate an int. if 0us have elapsed since the last received frame. */ 671 static int bce_rx_ticks = 0; 672 #else 673 /* Generate an int. if 18us have elapsed since the last received frame. */ 674 static int bce_rx_ticks = DEFAULT_RX_TICKS; 675 #endif 676 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 677 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 678 &bce_rx_ticks, 0, "Receive ticks count"); 679 680 681 /****************************************************************************/ 682 /* Device probe function. */ 683 /* */ 684 /* Compares the device to the driver's list of supported devices and */ 685 /* reports back to the OS whether this is the right driver for the device. */ 686 /* */ 687 /* Returns: */ 688 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 689 /****************************************************************************/ 690 static int 691 bce_probe(device_t dev) 692 { 693 const struct bce_type *t; 694 struct bce_softc *sc; 695 char *descbuf; 696 u16 vid = 0, did = 0, svid = 0, sdid = 0; 697 698 t = bce_devs; 699 700 sc = device_get_softc(dev); 701 sc->bce_unit = device_get_unit(dev); 702 sc->bce_dev = dev; 703 704 /* Get the data for the device to be probed. */ 705 vid = pci_get_vendor(dev); 706 did = pci_get_device(dev); 707 svid = pci_get_subvendor(dev); 708 sdid = pci_get_subdevice(dev); 709 710 DBPRINT(sc, BCE_EXTREME_LOAD, 711 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 712 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 713 714 /* Look through the list of known devices for a match. */ 715 while(t->bce_name != NULL) { 716 717 if ((vid == t->bce_vid) && (did == t->bce_did) && 718 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 719 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 720 721 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 722 723 if (descbuf == NULL) 724 return(ENOMEM); 725 726 /* Print out the device identity. */ 727 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 728 t->bce_name, (((pci_read_config(dev, 729 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 730 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 731 732 device_set_desc_copy(dev, descbuf); 733 free(descbuf, M_TEMP); 734 return(BUS_PROBE_DEFAULT); 735 } 736 t++; 737 } 738 739 return(ENXIO); 740 } 741 742 743 /****************************************************************************/ 744 /* PCI Capabilities Probe Function. */ 745 /* */ 746 /* Walks the PCI capabiites list for the device to find what features are */ 747 /* supported. */ 748 /* */ 749 /* Returns: */ 750 /* None. */ 751 /****************************************************************************/ 752 static void 753 bce_print_adapter_info(struct bce_softc *sc) 754 { 755 int i = 0; 756 757 DBENTER(BCE_VERBOSE_LOAD); 758 759 if (bce_verbose || bootverbose) { 760 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 761 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 762 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 763 764 765 /* Bus info. */ 766 if (sc->bce_flags & BCE_PCIE_FLAG) { 767 printf("Bus (PCIe x%d, ", sc->link_width); 768 switch (sc->link_speed) { 769 case 1: printf("2.5Gbps); "); break; 770 case 2: printf("5Gbps); "); break; 771 default: printf("Unknown link speed); "); 772 } 773 } else { 774 printf("Bus (PCI%s, %s, %dMHz); ", 775 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 776 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 777 "32-bit" : "64-bit"), sc->bus_speed_mhz); 778 } 779 780 /* Firmware version and device features. */ 781 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 782 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 783 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 784 785 if (bce_hdr_split == TRUE) { 786 printf("SPLT"); 787 i++; 788 } 789 790 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 791 if (i > 0) printf("|"); 792 printf("MSI"); i++; 793 } 794 795 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 796 if (i > 0) printf("|"); 797 printf("MSI-X"); i++; 798 } 799 800 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 801 if (i > 0) printf("|"); 802 printf("2.5G"); i++; 803 } 804 805 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 806 if (i > 0) printf("|"); 807 printf("Remote PHY(%s)", 808 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 809 "FIBER" : "TP"); i++; 810 } 811 812 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 813 if (i > 0) printf("|"); 814 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 815 } else { 816 printf(")\n"); 817 } 818 819 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 820 sc->bce_rx_quick_cons_trip_int, 821 sc->bce_rx_quick_cons_trip, 822 sc->bce_rx_ticks_int, 823 sc->bce_rx_ticks, 824 sc->bce_tx_quick_cons_trip_int, 825 sc->bce_tx_quick_cons_trip, 826 sc->bce_tx_ticks_int, 827 sc->bce_tx_ticks); 828 829 } 830 831 DBEXIT(BCE_VERBOSE_LOAD); 832 } 833 834 835 /****************************************************************************/ 836 /* PCI Capabilities Probe Function. */ 837 /* */ 838 /* Walks the PCI capabiites list for the device to find what features are */ 839 /* supported. */ 840 /* */ 841 /* Returns: */ 842 /* None. */ 843 /****************************************************************************/ 844 static void 845 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 846 { 847 u32 reg; 848 849 DBENTER(BCE_VERBOSE_LOAD); 850 851 /* Check if PCI-X capability is enabled. */ 852 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 853 if (reg != 0) 854 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 855 } 856 857 /* Check if PCIe capability is enabled. */ 858 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 859 if (reg != 0) { 860 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 861 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 862 "0x%08X\n", link_status); 863 sc->link_speed = link_status & 0xf; 864 sc->link_width = (link_status >> 4) & 0x3f; 865 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 866 sc->bce_flags |= BCE_PCIE_FLAG; 867 } 868 } 869 870 /* Check if MSI capability is enabled. */ 871 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 872 if (reg != 0) 873 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 874 } 875 876 /* Check if MSI-X capability is enabled. */ 877 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 878 if (reg != 0) 879 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 880 } 881 882 DBEXIT(BCE_VERBOSE_LOAD); 883 } 884 885 886 /****************************************************************************/ 887 /* Load and validate user tunable settings. */ 888 /* */ 889 /* Returns: */ 890 /* Nothing. */ 891 /****************************************************************************/ 892 static void 893 bce_set_tunables(struct bce_softc *sc) 894 { 895 /* Set sysctl values for RX page count. */ 896 switch (bce_rx_pages) { 897 case 1: 898 /* fall-through */ 899 case 2: 900 /* fall-through */ 901 case 4: 902 /* fall-through */ 903 case 8: 904 sc->rx_pages = bce_rx_pages; 905 break; 906 default: 907 sc->rx_pages = DEFAULT_RX_PAGES; 908 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 909 "hw.bce.rx_pages! Setting default of %d.\n", 910 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 911 } 912 913 /* ToDo: Consider allowing user setting for pg_pages. */ 914 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 915 916 /* Set sysctl values for TX page count. */ 917 switch (bce_tx_pages) { 918 case 1: 919 /* fall-through */ 920 case 2: 921 /* fall-through */ 922 case 4: 923 /* fall-through */ 924 case 8: 925 sc->tx_pages = bce_tx_pages; 926 break; 927 default: 928 sc->tx_pages = DEFAULT_TX_PAGES; 929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 930 "hw.bce.tx_pages! Setting default of %d.\n", 931 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 932 } 933 934 /* 935 * Validate the TX trip point (i.e. the number of 936 * TX completions before a status block update is 937 * generated and an interrupt is asserted. 938 */ 939 if (bce_tx_quick_cons_trip_int <= 100) { 940 sc->bce_tx_quick_cons_trip_int = 941 bce_tx_quick_cons_trip_int; 942 } else { 943 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 944 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 945 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 946 DEFAULT_TX_QUICK_CONS_TRIP_INT); 947 sc->bce_tx_quick_cons_trip_int = 948 DEFAULT_TX_QUICK_CONS_TRIP_INT; 949 } 950 951 if (bce_tx_quick_cons_trip <= 100) { 952 sc->bce_tx_quick_cons_trip = 953 bce_tx_quick_cons_trip; 954 } else { 955 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 956 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 957 __FILE__, __LINE__, bce_tx_quick_cons_trip, 958 DEFAULT_TX_QUICK_CONS_TRIP); 959 sc->bce_tx_quick_cons_trip = 960 DEFAULT_TX_QUICK_CONS_TRIP; 961 } 962 963 /* 964 * Validate the TX ticks count (i.e. the maximum amount 965 * of time to wait after the last TX completion has 966 * occurred before a status block update is generated 967 * and an interrupt is asserted. 968 */ 969 if (bce_tx_ticks_int <= 100) { 970 sc->bce_tx_ticks_int = 971 bce_tx_ticks_int; 972 } else { 973 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 974 "hw.bce.tx_ticks_int! Setting default of %d.\n", 975 __FILE__, __LINE__, bce_tx_ticks_int, 976 DEFAULT_TX_TICKS_INT); 977 sc->bce_tx_ticks_int = 978 DEFAULT_TX_TICKS_INT; 979 } 980 981 if (bce_tx_ticks <= 100) { 982 sc->bce_tx_ticks = 983 bce_tx_ticks; 984 } else { 985 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 986 "hw.bce.tx_ticks! Setting default of %d.\n", 987 __FILE__, __LINE__, bce_tx_ticks, 988 DEFAULT_TX_TICKS); 989 sc->bce_tx_ticks = 990 DEFAULT_TX_TICKS; 991 } 992 993 /* 994 * Validate the RX trip point (i.e. the number of 995 * RX frames received before a status block update is 996 * generated and an interrupt is asserted. 997 */ 998 if (bce_rx_quick_cons_trip_int <= 100) { 999 sc->bce_rx_quick_cons_trip_int = 1000 bce_rx_quick_cons_trip_int; 1001 } else { 1002 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1003 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 1004 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 1005 DEFAULT_RX_QUICK_CONS_TRIP_INT); 1006 sc->bce_rx_quick_cons_trip_int = 1007 DEFAULT_RX_QUICK_CONS_TRIP_INT; 1008 } 1009 1010 if (bce_rx_quick_cons_trip <= 100) { 1011 sc->bce_rx_quick_cons_trip = 1012 bce_rx_quick_cons_trip; 1013 } else { 1014 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1015 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 1016 __FILE__, __LINE__, bce_rx_quick_cons_trip, 1017 DEFAULT_RX_QUICK_CONS_TRIP); 1018 sc->bce_rx_quick_cons_trip = 1019 DEFAULT_RX_QUICK_CONS_TRIP; 1020 } 1021 1022 /* 1023 * Validate the RX ticks count (i.e. the maximum amount 1024 * of time to wait after the last RX frame has been 1025 * received before a status block update is generated 1026 * and an interrupt is asserted. 1027 */ 1028 if (bce_rx_ticks_int <= 100) { 1029 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1030 } else { 1031 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1032 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1033 __FILE__, __LINE__, bce_rx_ticks_int, 1034 DEFAULT_RX_TICKS_INT); 1035 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1036 } 1037 1038 if (bce_rx_ticks <= 100) { 1039 sc->bce_rx_ticks = bce_rx_ticks; 1040 } else { 1041 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1042 "hw.bce.rx_ticks! Setting default of %d.\n", 1043 __FILE__, __LINE__, bce_rx_ticks, 1044 DEFAULT_RX_TICKS); 1045 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1046 } 1047 1048 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1049 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1050 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1051 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1052 __FILE__, __LINE__); 1053 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1054 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1055 } 1056 1057 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1058 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1059 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1060 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1061 __FILE__, __LINE__); 1062 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1063 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1064 } 1065 } 1066 1067 1068 /****************************************************************************/ 1069 /* Device attach function. */ 1070 /* */ 1071 /* Allocates device resources, performs secondary chip identification, */ 1072 /* resets and initializes the hardware, and initializes driver instance */ 1073 /* variables. */ 1074 /* */ 1075 /* Returns: */ 1076 /* 0 on success, positive value on failure. */ 1077 /****************************************************************************/ 1078 static int 1079 bce_attach(device_t dev) 1080 { 1081 struct bce_softc *sc; 1082 struct ifnet *ifp; 1083 u32 val; 1084 int count, error, rc = 0, rid; 1085 1086 sc = device_get_softc(dev); 1087 sc->bce_dev = dev; 1088 1089 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1090 1091 sc->bce_unit = device_get_unit(dev); 1092 1093 /* Set initial device and PHY flags */ 1094 sc->bce_flags = 0; 1095 sc->bce_phy_flags = 0; 1096 1097 bce_set_tunables(sc); 1098 1099 pci_enable_busmaster(dev); 1100 1101 /* Allocate PCI memory resources. */ 1102 rid = PCIR_BAR(0); 1103 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1104 &rid, RF_ACTIVE); 1105 1106 if (sc->bce_res_mem == NULL) { 1107 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1108 __FILE__, __LINE__); 1109 rc = ENXIO; 1110 goto bce_attach_fail; 1111 } 1112 1113 /* Get various resource handles. */ 1114 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1115 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1116 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1117 1118 bce_probe_pci_caps(dev, sc); 1119 1120 rid = 1; 1121 count = 0; 1122 #if 0 1123 /* Try allocating MSI-X interrupts. */ 1124 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1125 (bce_msi_enable >= 2) && 1126 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1127 &rid, RF_ACTIVE)) != NULL)) { 1128 1129 msi_needed = count = 1; 1130 1131 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1132 (count != msi_needed)) { 1133 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1134 "Received = %d, error = %d\n", __FILE__, __LINE__, 1135 msi_needed, count, error); 1136 count = 0; 1137 pci_release_msi(dev); 1138 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1139 sc->bce_res_irq); 1140 sc->bce_res_irq = NULL; 1141 } else { 1142 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1143 __FUNCTION__); 1144 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1145 } 1146 } 1147 #endif 1148 1149 /* Try allocating a MSI interrupt. */ 1150 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1151 (bce_msi_enable >= 1) && (count == 0)) { 1152 count = 1; 1153 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1154 BCE_PRINTF("%s(%d): MSI allocation failed! " 1155 "error = %d\n", __FILE__, __LINE__, error); 1156 count = 0; 1157 pci_release_msi(dev); 1158 } else { 1159 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1160 "interrupt.\n", __FUNCTION__); 1161 sc->bce_flags |= BCE_USING_MSI_FLAG; 1162 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1163 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1164 rid = 1; 1165 } 1166 } 1167 1168 /* Try allocating a legacy interrupt. */ 1169 if (count == 0) { 1170 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1171 __FUNCTION__); 1172 rid = 0; 1173 } 1174 1175 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1176 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1177 1178 /* Report any IRQ allocation errors. */ 1179 if (sc->bce_res_irq == NULL) { 1180 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1181 __FILE__, __LINE__); 1182 rc = ENXIO; 1183 goto bce_attach_fail; 1184 } 1185 1186 /* Initialize mutex for the current device instance. */ 1187 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1188 1189 /* 1190 * Configure byte swap and enable indirect register access. 1191 * Rely on CPU to do target byte swapping on big endian systems. 1192 * Access to registers outside of PCI configurtion space are not 1193 * valid until this is done. 1194 */ 1195 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1196 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1197 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1198 1199 /* Save ASIC revsion info. */ 1200 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1201 1202 /* Weed out any non-production controller revisions. */ 1203 switch(BCE_CHIP_ID(sc)) { 1204 case BCE_CHIP_ID_5706_A0: 1205 case BCE_CHIP_ID_5706_A1: 1206 case BCE_CHIP_ID_5708_A0: 1207 case BCE_CHIP_ID_5708_B0: 1208 case BCE_CHIP_ID_5709_A0: 1209 case BCE_CHIP_ID_5709_B0: 1210 case BCE_CHIP_ID_5709_B1: 1211 case BCE_CHIP_ID_5709_B2: 1212 BCE_PRINTF("%s(%d): Unsupported controller " 1213 "revision (%c%d)!\n", __FILE__, __LINE__, 1214 (((pci_read_config(dev, PCIR_REVID, 4) & 1215 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1216 PCIR_REVID, 4) & 0xf)); 1217 rc = ENODEV; 1218 goto bce_attach_fail; 1219 } 1220 1221 /* 1222 * The embedded PCIe to PCI-X bridge (EPB) 1223 * in the 5708 cannot address memory above 1224 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1225 */ 1226 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1227 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1228 else 1229 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1230 1231 /* 1232 * Find the base address for shared memory access. 1233 * Newer versions of bootcode use a signature and offset 1234 * while older versions use a fixed address. 1235 */ 1236 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1237 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1238 /* Multi-port devices use different offsets in shared memory. */ 1239 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1240 (pci_get_function(sc->bce_dev) << 2)); 1241 else 1242 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1243 1244 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1245 __FUNCTION__, sc->bce_shmem_base); 1246 1247 /* Fetch the bootcode revision. */ 1248 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1249 for (int i = 0, j = 0; i < 3; i++) { 1250 u8 num; 1251 1252 num = (u8) (val >> (24 - (i * 8))); 1253 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1254 if (num >= k || !skip0 || k == 1) { 1255 sc->bce_bc_ver[j++] = (num / k) + '0'; 1256 skip0 = 0; 1257 } 1258 } 1259 1260 if (i != 2) 1261 sc->bce_bc_ver[j++] = '.'; 1262 } 1263 1264 /* Check if any management firwmare is enabled. */ 1265 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1266 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1267 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1268 1269 /* Allow time for firmware to enter the running state. */ 1270 for (int i = 0; i < 30; i++) { 1271 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1272 if (val & BCE_CONDITION_MFW_RUN_MASK) 1273 break; 1274 DELAY(10000); 1275 } 1276 1277 /* Check if management firmware is running. */ 1278 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1279 val &= BCE_CONDITION_MFW_RUN_MASK; 1280 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1281 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1282 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1283 int i = 0; 1284 1285 /* Read the management firmware version string. */ 1286 for (int j = 0; j < 3; j++) { 1287 val = bce_reg_rd_ind(sc, addr + j * 4); 1288 val = bswap32(val); 1289 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1290 i += 4; 1291 } 1292 } else { 1293 /* May cause firmware synchronization timeouts. */ 1294 BCE_PRINTF("%s(%d): Management firmware enabled " 1295 "but not running!\n", __FILE__, __LINE__); 1296 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1297 1298 /* ToDo: Any action the driver should take? */ 1299 } 1300 } 1301 1302 /* Get PCI bus information (speed and type). */ 1303 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1304 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1305 u32 clkreg; 1306 1307 sc->bce_flags |= BCE_PCIX_FLAG; 1308 1309 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1310 1311 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1312 switch (clkreg) { 1313 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1314 sc->bus_speed_mhz = 133; 1315 break; 1316 1317 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1318 sc->bus_speed_mhz = 100; 1319 break; 1320 1321 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1322 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1323 sc->bus_speed_mhz = 66; 1324 break; 1325 1326 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1327 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1328 sc->bus_speed_mhz = 50; 1329 break; 1330 1331 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1332 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1333 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1334 sc->bus_speed_mhz = 33; 1335 break; 1336 } 1337 } else { 1338 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1339 sc->bus_speed_mhz = 66; 1340 else 1341 sc->bus_speed_mhz = 33; 1342 } 1343 1344 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1345 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1346 1347 /* Find the media type for the adapter. */ 1348 bce_get_media(sc); 1349 1350 /* Reset controller and announce to bootcode that driver is present. */ 1351 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1352 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1353 __FILE__, __LINE__); 1354 rc = ENXIO; 1355 goto bce_attach_fail; 1356 } 1357 1358 /* Initialize the controller. */ 1359 if (bce_chipinit(sc)) { 1360 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1361 __FILE__, __LINE__); 1362 rc = ENXIO; 1363 goto bce_attach_fail; 1364 } 1365 1366 /* Perform NVRAM test. */ 1367 if (bce_nvram_test(sc)) { 1368 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1369 __FILE__, __LINE__); 1370 rc = ENXIO; 1371 goto bce_attach_fail; 1372 } 1373 1374 /* Fetch the permanent Ethernet MAC address. */ 1375 bce_get_mac_addr(sc); 1376 1377 /* Update statistics once every second. */ 1378 sc->bce_stats_ticks = 1000000 & 0xffff00; 1379 1380 /* Store data needed by PHY driver for backplane applications */ 1381 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1382 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1383 1384 /* Allocate DMA memory resources. */ 1385 if (bce_dma_alloc(dev)) { 1386 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1387 __FILE__, __LINE__); 1388 rc = ENXIO; 1389 goto bce_attach_fail; 1390 } 1391 1392 /* Allocate an ifnet structure. */ 1393 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1394 if (ifp == NULL) { 1395 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1396 __FILE__, __LINE__); 1397 rc = ENXIO; 1398 goto bce_attach_fail; 1399 } 1400 1401 /* Initialize the ifnet interface. */ 1402 ifp->if_softc = sc; 1403 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1405 ifp->if_ioctl = bce_ioctl; 1406 ifp->if_start = bce_start; 1407 ifp->if_init = bce_init; 1408 ifp->if_mtu = ETHERMTU; 1409 1410 if (bce_tso_enable) { 1411 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1412 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1413 IFCAP_VLAN_HWTSO; 1414 } else { 1415 ifp->if_hwassist = BCE_IF_HWASSIST; 1416 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1417 } 1418 1419 #if __FreeBSD_version >= 800505 1420 /* 1421 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1422 * so it's approximate value. 1423 */ 1424 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1425 ifp->if_capabilities |= IFCAP_LINKSTATE; 1426 #endif 1427 1428 ifp->if_capenable = ifp->if_capabilities; 1429 1430 /* 1431 * Assume standard mbuf sizes for buffer allocation. 1432 * This may change later if the MTU size is set to 1433 * something other than 1500. 1434 */ 1435 bce_get_rx_buffer_sizes(sc, 1436 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1437 1438 /* Recalculate our buffer allocation sizes. */ 1439 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1440 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1441 IFQ_SET_READY(&ifp->if_snd); 1442 1443 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1444 ifp->if_baudrate = IF_Mbps(2500ULL); 1445 else 1446 ifp->if_baudrate = IF_Mbps(1000); 1447 1448 /* Handle any special PHY initialization for SerDes PHYs. */ 1449 bce_init_media(sc); 1450 1451 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1452 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1453 bce_ifmedia_sts); 1454 /* 1455 * We can't manually override remote PHY's link and assume 1456 * PHY port configuration(Fiber or TP) is not changed after 1457 * device attach. This may not be correct though. 1458 */ 1459 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1460 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1461 ifmedia_add(&sc->bce_ifmedia, 1462 IFM_ETHER | IFM_2500_SX, 0, NULL); 1463 ifmedia_add(&sc->bce_ifmedia, 1464 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1465 } 1466 ifmedia_add(&sc->bce_ifmedia, 1467 IFM_ETHER | IFM_1000_SX, 0, NULL); 1468 ifmedia_add(&sc->bce_ifmedia, 1469 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1470 } else { 1471 ifmedia_add(&sc->bce_ifmedia, 1472 IFM_ETHER | IFM_10_T, 0, NULL); 1473 ifmedia_add(&sc->bce_ifmedia, 1474 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1475 ifmedia_add(&sc->bce_ifmedia, 1476 IFM_ETHER | IFM_100_TX, 0, NULL); 1477 ifmedia_add(&sc->bce_ifmedia, 1478 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1479 ifmedia_add(&sc->bce_ifmedia, 1480 IFM_ETHER | IFM_1000_T, 0, NULL); 1481 ifmedia_add(&sc->bce_ifmedia, 1482 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1483 } 1484 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1485 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1486 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1487 } else { 1488 /* MII child bus by attaching the PHY. */ 1489 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1490 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1491 MII_OFFSET_ANY, MIIF_DOPAUSE); 1492 if (rc != 0) { 1493 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1494 __LINE__); 1495 goto bce_attach_fail; 1496 } 1497 } 1498 1499 /* Attach to the Ethernet interface list. */ 1500 ether_ifattach(ifp, sc->eaddr); 1501 1502 #if __FreeBSD_version < 500000 1503 callout_init(&sc->bce_tick_callout); 1504 callout_init(&sc->bce_pulse_callout); 1505 #else 1506 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1507 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1508 #endif 1509 1510 /* Hookup IRQ last. */ 1511 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1512 NULL, bce_intr, sc, &sc->bce_intrhand); 1513 1514 if (rc) { 1515 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1516 __FILE__, __LINE__); 1517 bce_detach(dev); 1518 goto bce_attach_exit; 1519 } 1520 1521 /* 1522 * At this point we've acquired all the resources 1523 * we need to run so there's no turning back, we're 1524 * cleared for launch. 1525 */ 1526 1527 /* Print some important debugging info. */ 1528 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1529 1530 /* Add the supported sysctls to the kernel. */ 1531 bce_add_sysctls(sc); 1532 1533 BCE_LOCK(sc); 1534 1535 /* 1536 * The chip reset earlier notified the bootcode that 1537 * a driver is present. We now need to start our pulse 1538 * routine so that the bootcode is reminded that we're 1539 * still running. 1540 */ 1541 bce_pulse(sc); 1542 1543 bce_mgmt_init_locked(sc); 1544 BCE_UNLOCK(sc); 1545 1546 /* Finally, print some useful adapter info */ 1547 bce_print_adapter_info(sc); 1548 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1549 __FUNCTION__, sc); 1550 1551 goto bce_attach_exit; 1552 1553 bce_attach_fail: 1554 bce_release_resources(sc); 1555 1556 bce_attach_exit: 1557 1558 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1559 1560 return(rc); 1561 } 1562 1563 1564 /****************************************************************************/ 1565 /* Device detach function. */ 1566 /* */ 1567 /* Stops the controller, resets the controller, and releases resources. */ 1568 /* */ 1569 /* Returns: */ 1570 /* 0 on success, positive value on failure. */ 1571 /****************************************************************************/ 1572 static int 1573 bce_detach(device_t dev) 1574 { 1575 struct bce_softc *sc = device_get_softc(dev); 1576 struct ifnet *ifp; 1577 u32 msg; 1578 1579 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1580 1581 ifp = sc->bce_ifp; 1582 1583 /* Stop and reset the controller. */ 1584 BCE_LOCK(sc); 1585 1586 /* Stop the pulse so the bootcode can go to driver absent state. */ 1587 callout_stop(&sc->bce_pulse_callout); 1588 1589 bce_stop(sc); 1590 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1591 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1592 else 1593 msg = BCE_DRV_MSG_CODE_UNLOAD; 1594 bce_reset(sc, msg); 1595 1596 BCE_UNLOCK(sc); 1597 1598 ether_ifdetach(ifp); 1599 1600 /* If we have a child device on the MII bus remove it too. */ 1601 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1602 ifmedia_removeall(&sc->bce_ifmedia); 1603 else { 1604 bus_generic_detach(dev); 1605 device_delete_child(dev, sc->bce_miibus); 1606 } 1607 1608 /* Release all remaining resources. */ 1609 bce_release_resources(sc); 1610 1611 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1612 1613 return(0); 1614 } 1615 1616 1617 /****************************************************************************/ 1618 /* Device shutdown function. */ 1619 /* */ 1620 /* Stops and resets the controller. */ 1621 /* */ 1622 /* Returns: */ 1623 /* 0 on success, positive value on failure. */ 1624 /****************************************************************************/ 1625 static int 1626 bce_shutdown(device_t dev) 1627 { 1628 struct bce_softc *sc = device_get_softc(dev); 1629 u32 msg; 1630 1631 DBENTER(BCE_VERBOSE); 1632 1633 BCE_LOCK(sc); 1634 bce_stop(sc); 1635 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1636 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1637 else 1638 msg = BCE_DRV_MSG_CODE_UNLOAD; 1639 bce_reset(sc, msg); 1640 BCE_UNLOCK(sc); 1641 1642 DBEXIT(BCE_VERBOSE); 1643 1644 return (0); 1645 } 1646 1647 1648 #ifdef BCE_DEBUG 1649 /****************************************************************************/ 1650 /* Register read. */ 1651 /* */ 1652 /* Returns: */ 1653 /* The value of the register. */ 1654 /****************************************************************************/ 1655 static u32 1656 bce_reg_rd(struct bce_softc *sc, u32 offset) 1657 { 1658 u32 val = REG_RD(sc, offset); 1659 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1660 __FUNCTION__, offset, val); 1661 return val; 1662 } 1663 1664 1665 /****************************************************************************/ 1666 /* Register write (16 bit). */ 1667 /* */ 1668 /* Returns: */ 1669 /* Nothing. */ 1670 /****************************************************************************/ 1671 static void 1672 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1673 { 1674 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1675 __FUNCTION__, offset, val); 1676 REG_WR16(sc, offset, val); 1677 } 1678 1679 1680 /****************************************************************************/ 1681 /* Register write. */ 1682 /* */ 1683 /* Returns: */ 1684 /* Nothing. */ 1685 /****************************************************************************/ 1686 static void 1687 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1688 { 1689 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1690 __FUNCTION__, offset, val); 1691 REG_WR(sc, offset, val); 1692 } 1693 #endif 1694 1695 /****************************************************************************/ 1696 /* Indirect register read. */ 1697 /* */ 1698 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1699 /* configuration space. Using this mechanism avoids issues with posted */ 1700 /* reads but is much slower than memory-mapped I/O. */ 1701 /* */ 1702 /* Returns: */ 1703 /* The value of the register. */ 1704 /****************************************************************************/ 1705 static u32 1706 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1707 { 1708 device_t dev; 1709 dev = sc->bce_dev; 1710 1711 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1712 #ifdef BCE_DEBUG 1713 { 1714 u32 val; 1715 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1716 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1717 __FUNCTION__, offset, val); 1718 return val; 1719 } 1720 #else 1721 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1722 #endif 1723 } 1724 1725 1726 /****************************************************************************/ 1727 /* Indirect register write. */ 1728 /* */ 1729 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1730 /* configuration space. Using this mechanism avoids issues with posted */ 1731 /* writes but is muchh slower than memory-mapped I/O. */ 1732 /* */ 1733 /* Returns: */ 1734 /* Nothing. */ 1735 /****************************************************************************/ 1736 static void 1737 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1738 { 1739 device_t dev; 1740 dev = sc->bce_dev; 1741 1742 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1743 __FUNCTION__, offset, val); 1744 1745 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1746 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1747 } 1748 1749 1750 /****************************************************************************/ 1751 /* Shared memory write. */ 1752 /* */ 1753 /* Writes NetXtreme II shared memory region. */ 1754 /* */ 1755 /* Returns: */ 1756 /* Nothing. */ 1757 /****************************************************************************/ 1758 static void 1759 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1760 { 1761 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1762 "0x%08X\n", __FUNCTION__, val, offset); 1763 1764 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1765 } 1766 1767 1768 /****************************************************************************/ 1769 /* Shared memory read. */ 1770 /* */ 1771 /* Reads NetXtreme II shared memory region. */ 1772 /* */ 1773 /* Returns: */ 1774 /* The 32 bit value read. */ 1775 /****************************************************************************/ 1776 static u32 1777 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1778 { 1779 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1780 1781 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1782 "0x%08X\n", __FUNCTION__, val, offset); 1783 1784 return val; 1785 } 1786 1787 1788 #ifdef BCE_DEBUG 1789 /****************************************************************************/ 1790 /* Context memory read. */ 1791 /* */ 1792 /* The NetXtreme II controller uses context memory to track connection */ 1793 /* information for L2 and higher network protocols. */ 1794 /* */ 1795 /* Returns: */ 1796 /* The requested 32 bit value of context memory. */ 1797 /****************************************************************************/ 1798 static u32 1799 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1800 { 1801 u32 idx, offset, retry_cnt = 5, val; 1802 1803 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1804 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1805 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1806 1807 offset = ctx_offset + cid_addr; 1808 1809 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1810 1811 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1812 1813 for (idx = 0; idx < retry_cnt; idx++) { 1814 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1815 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1816 break; 1817 DELAY(5); 1818 } 1819 1820 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1821 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1822 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1823 __FILE__, __LINE__, cid_addr, ctx_offset); 1824 1825 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1826 } else { 1827 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1828 val = REG_RD(sc, BCE_CTX_DATA); 1829 } 1830 1831 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1832 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1833 1834 return(val); 1835 } 1836 #endif 1837 1838 1839 /****************************************************************************/ 1840 /* Context memory write. */ 1841 /* */ 1842 /* The NetXtreme II controller uses context memory to track connection */ 1843 /* information for L2 and higher network protocols. */ 1844 /* */ 1845 /* Returns: */ 1846 /* Nothing. */ 1847 /****************************************************************************/ 1848 static void 1849 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1850 { 1851 u32 idx, offset = ctx_offset + cid_addr; 1852 u32 val, retry_cnt = 5; 1853 1854 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1855 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1856 1857 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1858 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1859 __FUNCTION__, cid_addr)); 1860 1861 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1862 1863 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1864 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1865 1866 for (idx = 0; idx < retry_cnt; idx++) { 1867 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1868 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1869 break; 1870 DELAY(5); 1871 } 1872 1873 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1874 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1875 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1876 __FILE__, __LINE__, cid_addr, ctx_offset); 1877 1878 } else { 1879 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1880 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1881 } 1882 } 1883 1884 1885 /****************************************************************************/ 1886 /* PHY register read. */ 1887 /* */ 1888 /* Implements register reads on the MII bus. */ 1889 /* */ 1890 /* Returns: */ 1891 /* The value of the register. */ 1892 /****************************************************************************/ 1893 static int 1894 bce_miibus_read_reg(device_t dev, int phy, int reg) 1895 { 1896 struct bce_softc *sc; 1897 u32 val; 1898 int i; 1899 1900 sc = device_get_softc(dev); 1901 1902 /* 1903 * The 5709S PHY is an IEEE Clause 45 PHY 1904 * with special mappings to work with IEEE 1905 * Clause 22 register accesses. 1906 */ 1907 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1908 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1909 reg += 0x10; 1910 } 1911 1912 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1913 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1914 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1915 1916 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1917 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1918 1919 DELAY(40); 1920 } 1921 1922 1923 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1924 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1925 BCE_EMAC_MDIO_COMM_START_BUSY; 1926 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1927 1928 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1929 DELAY(10); 1930 1931 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1932 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1933 DELAY(5); 1934 1935 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1936 val &= BCE_EMAC_MDIO_COMM_DATA; 1937 1938 break; 1939 } 1940 } 1941 1942 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1943 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1944 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1945 val = 0x0; 1946 } else { 1947 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1948 } 1949 1950 1951 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1952 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1953 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1954 1955 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1956 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1957 1958 DELAY(40); 1959 } 1960 1961 DB_PRINT_PHY_REG(reg, val); 1962 return (val & 0xffff); 1963 } 1964 1965 1966 /****************************************************************************/ 1967 /* PHY register write. */ 1968 /* */ 1969 /* Implements register writes on the MII bus. */ 1970 /* */ 1971 /* Returns: */ 1972 /* The value of the register. */ 1973 /****************************************************************************/ 1974 static int 1975 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1976 { 1977 struct bce_softc *sc; 1978 u32 val1; 1979 int i; 1980 1981 sc = device_get_softc(dev); 1982 1983 DB_PRINT_PHY_REG(reg, val); 1984 1985 /* 1986 * The 5709S PHY is an IEEE Clause 45 PHY 1987 * with special mappings to work with IEEE 1988 * Clause 22 register accesses. 1989 */ 1990 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1991 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1992 reg += 0x10; 1993 } 1994 1995 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1996 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1997 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1998 1999 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2000 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2001 2002 DELAY(40); 2003 } 2004 2005 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 2006 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 2007 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 2008 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 2009 2010 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 2011 DELAY(10); 2012 2013 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 2014 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 2015 DELAY(5); 2016 break; 2017 } 2018 } 2019 2020 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 2021 BCE_PRINTF("%s(%d): PHY write timeout!\n", 2022 __FILE__, __LINE__); 2023 2024 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2025 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2026 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 2027 2028 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2029 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2030 2031 DELAY(40); 2032 } 2033 2034 return 0; 2035 } 2036 2037 2038 /****************************************************************************/ 2039 /* MII bus status change. */ 2040 /* */ 2041 /* Called by the MII bus driver when the PHY establishes link to set the */ 2042 /* MAC interface registers. */ 2043 /* */ 2044 /* Returns: */ 2045 /* Nothing. */ 2046 /****************************************************************************/ 2047 static void 2048 bce_miibus_statchg(device_t dev) 2049 { 2050 struct bce_softc *sc; 2051 struct mii_data *mii; 2052 struct ifmediareq ifmr; 2053 int media_active, media_status, val; 2054 2055 sc = device_get_softc(dev); 2056 2057 DBENTER(BCE_VERBOSE_PHY); 2058 2059 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2060 bzero(&ifmr, sizeof(ifmr)); 2061 bce_ifmedia_sts_rphy(sc, &ifmr); 2062 media_active = ifmr.ifm_active; 2063 media_status = ifmr.ifm_status; 2064 } else { 2065 mii = device_get_softc(sc->bce_miibus); 2066 media_active = mii->mii_media_active; 2067 media_status = mii->mii_media_status; 2068 } 2069 2070 /* Ignore invalid media status. */ 2071 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2072 (IFM_ACTIVE | IFM_AVALID)) 2073 goto bce_miibus_statchg_exit; 2074 2075 val = REG_RD(sc, BCE_EMAC_MODE); 2076 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2077 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2078 BCE_EMAC_MODE_25G); 2079 2080 /* Set MII or GMII interface based on the PHY speed. */ 2081 switch (IFM_SUBTYPE(media_active)) { 2082 case IFM_10_T: 2083 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2084 DBPRINT(sc, BCE_INFO_PHY, 2085 "Enabling 10Mb interface.\n"); 2086 val |= BCE_EMAC_MODE_PORT_MII_10; 2087 break; 2088 } 2089 /* fall-through */ 2090 case IFM_100_TX: 2091 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2092 val |= BCE_EMAC_MODE_PORT_MII; 2093 break; 2094 case IFM_2500_SX: 2095 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2096 val |= BCE_EMAC_MODE_25G; 2097 /* fall-through */ 2098 case IFM_1000_T: 2099 case IFM_1000_SX: 2100 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2101 val |= BCE_EMAC_MODE_PORT_GMII; 2102 break; 2103 default: 2104 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2105 "default GMII interface.\n"); 2106 val |= BCE_EMAC_MODE_PORT_GMII; 2107 } 2108 2109 /* Set half or full duplex based on PHY settings. */ 2110 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2111 DBPRINT(sc, BCE_INFO_PHY, 2112 "Setting Half-Duplex interface.\n"); 2113 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2114 } else 2115 DBPRINT(sc, BCE_INFO_PHY, 2116 "Setting Full-Duplex interface.\n"); 2117 2118 REG_WR(sc, BCE_EMAC_MODE, val); 2119 2120 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2121 DBPRINT(sc, BCE_INFO_PHY, 2122 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2123 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2124 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2125 } else { 2126 DBPRINT(sc, BCE_INFO_PHY, 2127 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2128 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2129 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2130 } 2131 2132 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2133 DBPRINT(sc, BCE_INFO_PHY, 2134 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2135 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2136 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2137 } else { 2138 DBPRINT(sc, BCE_INFO_PHY, 2139 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2140 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2141 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2142 } 2143 2144 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2145 2146 bce_miibus_statchg_exit: 2147 DBEXIT(BCE_VERBOSE_PHY); 2148 } 2149 2150 2151 /****************************************************************************/ 2152 /* Acquire NVRAM lock. */ 2153 /* */ 2154 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2155 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2156 /* for use by the driver. */ 2157 /* */ 2158 /* Returns: */ 2159 /* 0 on success, positive value on failure. */ 2160 /****************************************************************************/ 2161 static int 2162 bce_acquire_nvram_lock(struct bce_softc *sc) 2163 { 2164 u32 val; 2165 int j, rc = 0; 2166 2167 DBENTER(BCE_VERBOSE_NVRAM); 2168 2169 /* Request access to the flash interface. */ 2170 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2171 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2172 val = REG_RD(sc, BCE_NVM_SW_ARB); 2173 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2174 break; 2175 2176 DELAY(5); 2177 } 2178 2179 if (j >= NVRAM_TIMEOUT_COUNT) { 2180 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2181 rc = EBUSY; 2182 } 2183 2184 DBEXIT(BCE_VERBOSE_NVRAM); 2185 return (rc); 2186 } 2187 2188 2189 /****************************************************************************/ 2190 /* Release NVRAM lock. */ 2191 /* */ 2192 /* When the caller is finished accessing NVRAM the lock must be released. */ 2193 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2194 /* for use by the driver. */ 2195 /* */ 2196 /* Returns: */ 2197 /* 0 on success, positive value on failure. */ 2198 /****************************************************************************/ 2199 static int 2200 bce_release_nvram_lock(struct bce_softc *sc) 2201 { 2202 u32 val; 2203 int j, rc = 0; 2204 2205 DBENTER(BCE_VERBOSE_NVRAM); 2206 2207 /* 2208 * Relinquish nvram interface. 2209 */ 2210 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2211 2212 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2213 val = REG_RD(sc, BCE_NVM_SW_ARB); 2214 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2215 break; 2216 2217 DELAY(5); 2218 } 2219 2220 if (j >= NVRAM_TIMEOUT_COUNT) { 2221 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2222 rc = EBUSY; 2223 } 2224 2225 DBEXIT(BCE_VERBOSE_NVRAM); 2226 return (rc); 2227 } 2228 2229 2230 #ifdef BCE_NVRAM_WRITE_SUPPORT 2231 /****************************************************************************/ 2232 /* Enable NVRAM write access. */ 2233 /* */ 2234 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2235 /* */ 2236 /* Returns: */ 2237 /* 0 on success, positive value on failure. */ 2238 /****************************************************************************/ 2239 static int 2240 bce_enable_nvram_write(struct bce_softc *sc) 2241 { 2242 u32 val; 2243 int rc = 0; 2244 2245 DBENTER(BCE_VERBOSE_NVRAM); 2246 2247 val = REG_RD(sc, BCE_MISC_CFG); 2248 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2249 2250 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2251 int j; 2252 2253 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2254 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2255 2256 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2257 DELAY(5); 2258 2259 val = REG_RD(sc, BCE_NVM_COMMAND); 2260 if (val & BCE_NVM_COMMAND_DONE) 2261 break; 2262 } 2263 2264 if (j >= NVRAM_TIMEOUT_COUNT) { 2265 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2266 rc = EBUSY; 2267 } 2268 } 2269 2270 DBENTER(BCE_VERBOSE_NVRAM); 2271 return (rc); 2272 } 2273 2274 2275 /****************************************************************************/ 2276 /* Disable NVRAM write access. */ 2277 /* */ 2278 /* When the caller is finished writing to NVRAM write access must be */ 2279 /* disabled. */ 2280 /* */ 2281 /* Returns: */ 2282 /* Nothing. */ 2283 /****************************************************************************/ 2284 static void 2285 bce_disable_nvram_write(struct bce_softc *sc) 2286 { 2287 u32 val; 2288 2289 DBENTER(BCE_VERBOSE_NVRAM); 2290 2291 val = REG_RD(sc, BCE_MISC_CFG); 2292 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2293 2294 DBEXIT(BCE_VERBOSE_NVRAM); 2295 2296 } 2297 #endif 2298 2299 2300 /****************************************************************************/ 2301 /* Enable NVRAM access. */ 2302 /* */ 2303 /* Before accessing NVRAM for read or write operations the caller must */ 2304 /* enabled NVRAM access. */ 2305 /* */ 2306 /* Returns: */ 2307 /* Nothing. */ 2308 /****************************************************************************/ 2309 static void 2310 bce_enable_nvram_access(struct bce_softc *sc) 2311 { 2312 u32 val; 2313 2314 DBENTER(BCE_VERBOSE_NVRAM); 2315 2316 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2317 /* Enable both bits, even on read. */ 2318 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2319 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2320 2321 DBEXIT(BCE_VERBOSE_NVRAM); 2322 } 2323 2324 2325 /****************************************************************************/ 2326 /* Disable NVRAM access. */ 2327 /* */ 2328 /* When the caller is finished accessing NVRAM access must be disabled. */ 2329 /* */ 2330 /* Returns: */ 2331 /* Nothing. */ 2332 /****************************************************************************/ 2333 static void 2334 bce_disable_nvram_access(struct bce_softc *sc) 2335 { 2336 u32 val; 2337 2338 DBENTER(BCE_VERBOSE_NVRAM); 2339 2340 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2341 2342 /* Disable both bits, even after read. */ 2343 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2344 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2345 2346 DBEXIT(BCE_VERBOSE_NVRAM); 2347 } 2348 2349 2350 #ifdef BCE_NVRAM_WRITE_SUPPORT 2351 /****************************************************************************/ 2352 /* Erase NVRAM page before writing. */ 2353 /* */ 2354 /* Non-buffered flash parts require that a page be erased before it is */ 2355 /* written. */ 2356 /* */ 2357 /* Returns: */ 2358 /* 0 on success, positive value on failure. */ 2359 /****************************************************************************/ 2360 static int 2361 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2362 { 2363 u32 cmd; 2364 int j, rc = 0; 2365 2366 DBENTER(BCE_VERBOSE_NVRAM); 2367 2368 /* Buffered flash doesn't require an erase. */ 2369 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2370 goto bce_nvram_erase_page_exit; 2371 2372 /* Build an erase command. */ 2373 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2374 BCE_NVM_COMMAND_DOIT; 2375 2376 /* 2377 * Clear the DONE bit separately, set the NVRAM adress to erase, 2378 * and issue the erase command. 2379 */ 2380 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2381 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2382 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2383 2384 /* Wait for completion. */ 2385 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2386 u32 val; 2387 2388 DELAY(5); 2389 2390 val = REG_RD(sc, BCE_NVM_COMMAND); 2391 if (val & BCE_NVM_COMMAND_DONE) 2392 break; 2393 } 2394 2395 if (j >= NVRAM_TIMEOUT_COUNT) { 2396 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2397 rc = EBUSY; 2398 } 2399 2400 bce_nvram_erase_page_exit: 2401 DBEXIT(BCE_VERBOSE_NVRAM); 2402 return (rc); 2403 } 2404 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2405 2406 2407 /****************************************************************************/ 2408 /* Read a dword (32 bits) from NVRAM. */ 2409 /* */ 2410 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2411 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2412 /* */ 2413 /* Returns: */ 2414 /* 0 on success and the 32 bit value read, positive value on failure. */ 2415 /****************************************************************************/ 2416 static int 2417 bce_nvram_read_dword(struct bce_softc *sc, 2418 u32 offset, u8 *ret_val, u32 cmd_flags) 2419 { 2420 u32 cmd; 2421 int i, rc = 0; 2422 2423 DBENTER(BCE_EXTREME_NVRAM); 2424 2425 /* Build the command word. */ 2426 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2427 2428 /* Calculate the offset for buffered flash if translation is used. */ 2429 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2430 offset = ((offset / sc->bce_flash_info->page_size) << 2431 sc->bce_flash_info->page_bits) + 2432 (offset % sc->bce_flash_info->page_size); 2433 } 2434 2435 /* 2436 * Clear the DONE bit separately, set the address to read, 2437 * and issue the read. 2438 */ 2439 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2440 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2441 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2442 2443 /* Wait for completion. */ 2444 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2445 u32 val; 2446 2447 DELAY(5); 2448 2449 val = REG_RD(sc, BCE_NVM_COMMAND); 2450 if (val & BCE_NVM_COMMAND_DONE) { 2451 val = REG_RD(sc, BCE_NVM_READ); 2452 2453 val = bce_be32toh(val); 2454 memcpy(ret_val, &val, 4); 2455 break; 2456 } 2457 } 2458 2459 /* Check for errors. */ 2460 if (i >= NVRAM_TIMEOUT_COUNT) { 2461 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2462 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2463 rc = EBUSY; 2464 } 2465 2466 DBEXIT(BCE_EXTREME_NVRAM); 2467 return(rc); 2468 } 2469 2470 2471 #ifdef BCE_NVRAM_WRITE_SUPPORT 2472 /****************************************************************************/ 2473 /* Write a dword (32 bits) to NVRAM. */ 2474 /* */ 2475 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2476 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2477 /* enabled NVRAM write access. */ 2478 /* */ 2479 /* Returns: */ 2480 /* 0 on success, positive value on failure. */ 2481 /****************************************************************************/ 2482 static int 2483 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2484 u32 cmd_flags) 2485 { 2486 u32 cmd, val32; 2487 int j, rc = 0; 2488 2489 DBENTER(BCE_VERBOSE_NVRAM); 2490 2491 /* Build the command word. */ 2492 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2493 2494 /* Calculate the offset for buffered flash if translation is used. */ 2495 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2496 offset = ((offset / sc->bce_flash_info->page_size) << 2497 sc->bce_flash_info->page_bits) + 2498 (offset % sc->bce_flash_info->page_size); 2499 } 2500 2501 /* 2502 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2503 * set the NVRAM address to write, and issue the write command 2504 */ 2505 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2506 memcpy(&val32, val, 4); 2507 val32 = htobe32(val32); 2508 REG_WR(sc, BCE_NVM_WRITE, val32); 2509 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2510 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2511 2512 /* Wait for completion. */ 2513 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2514 DELAY(5); 2515 2516 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2517 break; 2518 } 2519 if (j >= NVRAM_TIMEOUT_COUNT) { 2520 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2521 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2522 rc = EBUSY; 2523 } 2524 2525 DBEXIT(BCE_VERBOSE_NVRAM); 2526 return (rc); 2527 } 2528 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2529 2530 2531 /****************************************************************************/ 2532 /* Initialize NVRAM access. */ 2533 /* */ 2534 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2535 /* access that device. */ 2536 /* */ 2537 /* Returns: */ 2538 /* 0 on success, positive value on failure. */ 2539 /****************************************************************************/ 2540 static int 2541 bce_init_nvram(struct bce_softc *sc) 2542 { 2543 u32 val; 2544 int j, entry_count, rc = 0; 2545 const struct flash_spec *flash; 2546 2547 DBENTER(BCE_VERBOSE_NVRAM); 2548 2549 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2550 sc->bce_flash_info = &flash_5709; 2551 goto bce_init_nvram_get_flash_size; 2552 } 2553 2554 /* Determine the selected interface. */ 2555 val = REG_RD(sc, BCE_NVM_CFG1); 2556 2557 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2558 2559 /* 2560 * Flash reconfiguration is required to support additional 2561 * NVRAM devices not directly supported in hardware. 2562 * Check if the flash interface was reconfigured 2563 * by the bootcode. 2564 */ 2565 2566 if (val & 0x40000000) { 2567 /* Flash interface reconfigured by bootcode. */ 2568 2569 DBPRINT(sc,BCE_INFO_LOAD, 2570 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2571 2572 for (j = 0, flash = &flash_table[0]; j < entry_count; 2573 j++, flash++) { 2574 if ((val & FLASH_BACKUP_STRAP_MASK) == 2575 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2576 sc->bce_flash_info = flash; 2577 break; 2578 } 2579 } 2580 } else { 2581 /* Flash interface not yet reconfigured. */ 2582 u32 mask; 2583 2584 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2585 __FUNCTION__); 2586 2587 if (val & (1 << 23)) 2588 mask = FLASH_BACKUP_STRAP_MASK; 2589 else 2590 mask = FLASH_STRAP_MASK; 2591 2592 /* Look for the matching NVRAM device configuration data. */ 2593 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2594 2595 /* Check if the device matches any of the known devices. */ 2596 if ((val & mask) == (flash->strapping & mask)) { 2597 /* Found a device match. */ 2598 sc->bce_flash_info = flash; 2599 2600 /* Request access to the flash interface. */ 2601 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2602 return rc; 2603 2604 /* Reconfigure the flash interface. */ 2605 bce_enable_nvram_access(sc); 2606 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2607 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2608 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2609 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2610 bce_disable_nvram_access(sc); 2611 bce_release_nvram_lock(sc); 2612 2613 break; 2614 } 2615 } 2616 } 2617 2618 /* Check if a matching device was found. */ 2619 if (j == entry_count) { 2620 sc->bce_flash_info = NULL; 2621 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2622 __FILE__, __LINE__); 2623 DBEXIT(BCE_VERBOSE_NVRAM); 2624 return (ENODEV); 2625 } 2626 2627 bce_init_nvram_get_flash_size: 2628 /* Write the flash config data to the shared memory interface. */ 2629 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2630 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2631 if (val) 2632 sc->bce_flash_size = val; 2633 else 2634 sc->bce_flash_size = sc->bce_flash_info->total_size; 2635 2636 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2637 __FUNCTION__, sc->bce_flash_info->name, 2638 sc->bce_flash_info->total_size); 2639 2640 DBEXIT(BCE_VERBOSE_NVRAM); 2641 return rc; 2642 } 2643 2644 2645 /****************************************************************************/ 2646 /* Read an arbitrary range of data from NVRAM. */ 2647 /* */ 2648 /* Prepares the NVRAM interface for access and reads the requested data */ 2649 /* into the supplied buffer. */ 2650 /* */ 2651 /* Returns: */ 2652 /* 0 on success and the data read, positive value on failure. */ 2653 /****************************************************************************/ 2654 static int 2655 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2656 int buf_size) 2657 { 2658 int rc = 0; 2659 u32 cmd_flags, offset32, len32, extra; 2660 2661 DBENTER(BCE_VERBOSE_NVRAM); 2662 2663 if (buf_size == 0) 2664 goto bce_nvram_read_exit; 2665 2666 /* Request access to the flash interface. */ 2667 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2668 goto bce_nvram_read_exit; 2669 2670 /* Enable access to flash interface */ 2671 bce_enable_nvram_access(sc); 2672 2673 len32 = buf_size; 2674 offset32 = offset; 2675 extra = 0; 2676 2677 cmd_flags = 0; 2678 2679 if (offset32 & 3) { 2680 u8 buf[4]; 2681 u32 pre_len; 2682 2683 offset32 &= ~3; 2684 pre_len = 4 - (offset & 3); 2685 2686 if (pre_len >= len32) { 2687 pre_len = len32; 2688 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2689 } 2690 else { 2691 cmd_flags = BCE_NVM_COMMAND_FIRST; 2692 } 2693 2694 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2695 2696 if (rc) 2697 return rc; 2698 2699 memcpy(ret_buf, buf + (offset & 3), pre_len); 2700 2701 offset32 += 4; 2702 ret_buf += pre_len; 2703 len32 -= pre_len; 2704 } 2705 2706 if (len32 & 3) { 2707 extra = 4 - (len32 & 3); 2708 len32 = (len32 + 4) & ~3; 2709 } 2710 2711 if (len32 == 4) { 2712 u8 buf[4]; 2713 2714 if (cmd_flags) 2715 cmd_flags = BCE_NVM_COMMAND_LAST; 2716 else 2717 cmd_flags = BCE_NVM_COMMAND_FIRST | 2718 BCE_NVM_COMMAND_LAST; 2719 2720 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2721 2722 memcpy(ret_buf, buf, 4 - extra); 2723 } 2724 else if (len32 > 0) { 2725 u8 buf[4]; 2726 2727 /* Read the first word. */ 2728 if (cmd_flags) 2729 cmd_flags = 0; 2730 else 2731 cmd_flags = BCE_NVM_COMMAND_FIRST; 2732 2733 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2734 2735 /* Advance to the next dword. */ 2736 offset32 += 4; 2737 ret_buf += 4; 2738 len32 -= 4; 2739 2740 while (len32 > 4 && rc == 0) { 2741 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2742 2743 /* Advance to the next dword. */ 2744 offset32 += 4; 2745 ret_buf += 4; 2746 len32 -= 4; 2747 } 2748 2749 if (rc) 2750 goto bce_nvram_read_locked_exit; 2751 2752 cmd_flags = BCE_NVM_COMMAND_LAST; 2753 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2754 2755 memcpy(ret_buf, buf, 4 - extra); 2756 } 2757 2758 bce_nvram_read_locked_exit: 2759 /* Disable access to flash interface and release the lock. */ 2760 bce_disable_nvram_access(sc); 2761 bce_release_nvram_lock(sc); 2762 2763 bce_nvram_read_exit: 2764 DBEXIT(BCE_VERBOSE_NVRAM); 2765 return rc; 2766 } 2767 2768 2769 #ifdef BCE_NVRAM_WRITE_SUPPORT 2770 /****************************************************************************/ 2771 /* Write an arbitrary range of data from NVRAM. */ 2772 /* */ 2773 /* Prepares the NVRAM interface for write access and writes the requested */ 2774 /* data from the supplied buffer. The caller is responsible for */ 2775 /* calculating any appropriate CRCs. */ 2776 /* */ 2777 /* Returns: */ 2778 /* 0 on success, positive value on failure. */ 2779 /****************************************************************************/ 2780 static int 2781 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2782 int buf_size) 2783 { 2784 u32 written, offset32, len32; 2785 u8 *buf, start[4], end[4]; 2786 int rc = 0; 2787 int align_start, align_end; 2788 2789 DBENTER(BCE_VERBOSE_NVRAM); 2790 2791 buf = data_buf; 2792 offset32 = offset; 2793 len32 = buf_size; 2794 align_start = align_end = 0; 2795 2796 if ((align_start = (offset32 & 3))) { 2797 offset32 &= ~3; 2798 len32 += align_start; 2799 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2800 goto bce_nvram_write_exit; 2801 } 2802 2803 if (len32 & 3) { 2804 if ((len32 > 4) || !align_start) { 2805 align_end = 4 - (len32 & 3); 2806 len32 += align_end; 2807 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2808 end, 4))) { 2809 goto bce_nvram_write_exit; 2810 } 2811 } 2812 } 2813 2814 if (align_start || align_end) { 2815 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2816 if (buf == 0) { 2817 rc = ENOMEM; 2818 goto bce_nvram_write_exit; 2819 } 2820 2821 if (align_start) { 2822 memcpy(buf, start, 4); 2823 } 2824 2825 if (align_end) { 2826 memcpy(buf + len32 - 4, end, 4); 2827 } 2828 memcpy(buf + align_start, data_buf, buf_size); 2829 } 2830 2831 written = 0; 2832 while ((written < len32) && (rc == 0)) { 2833 u32 page_start, page_end, data_start, data_end; 2834 u32 addr, cmd_flags; 2835 int i; 2836 u8 flash_buffer[264]; 2837 2838 /* Find the page_start addr */ 2839 page_start = offset32 + written; 2840 page_start -= (page_start % sc->bce_flash_info->page_size); 2841 /* Find the page_end addr */ 2842 page_end = page_start + sc->bce_flash_info->page_size; 2843 /* Find the data_start addr */ 2844 data_start = (written == 0) ? offset32 : page_start; 2845 /* Find the data_end addr */ 2846 data_end = (page_end > offset32 + len32) ? 2847 (offset32 + len32) : page_end; 2848 2849 /* Request access to the flash interface. */ 2850 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2851 goto bce_nvram_write_exit; 2852 2853 /* Enable access to flash interface */ 2854 bce_enable_nvram_access(sc); 2855 2856 cmd_flags = BCE_NVM_COMMAND_FIRST; 2857 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2858 int j; 2859 2860 /* Read the whole page into the buffer 2861 * (non-buffer flash only) */ 2862 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2863 if (j == (sc->bce_flash_info->page_size - 4)) { 2864 cmd_flags |= BCE_NVM_COMMAND_LAST; 2865 } 2866 rc = bce_nvram_read_dword(sc, 2867 page_start + j, 2868 &flash_buffer[j], 2869 cmd_flags); 2870 2871 if (rc) 2872 goto bce_nvram_write_locked_exit; 2873 2874 cmd_flags = 0; 2875 } 2876 } 2877 2878 /* Enable writes to flash interface (unlock write-protect) */ 2879 if ((rc = bce_enable_nvram_write(sc)) != 0) 2880 goto bce_nvram_write_locked_exit; 2881 2882 /* Erase the page */ 2883 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2884 goto bce_nvram_write_locked_exit; 2885 2886 /* Re-enable the write again for the actual write */ 2887 bce_enable_nvram_write(sc); 2888 2889 /* Loop to write back the buffer data from page_start to 2890 * data_start */ 2891 i = 0; 2892 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2893 for (addr = page_start; addr < data_start; 2894 addr += 4, i += 4) { 2895 2896 rc = bce_nvram_write_dword(sc, addr, 2897 &flash_buffer[i], cmd_flags); 2898 2899 if (rc != 0) 2900 goto bce_nvram_write_locked_exit; 2901 2902 cmd_flags = 0; 2903 } 2904 } 2905 2906 /* Loop to write the new data from data_start to data_end */ 2907 for (addr = data_start; addr < data_end; addr += 4, i++) { 2908 if ((addr == page_end - 4) || 2909 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2910 (addr == data_end - 4))) { 2911 2912 cmd_flags |= BCE_NVM_COMMAND_LAST; 2913 } 2914 rc = bce_nvram_write_dword(sc, addr, buf, 2915 cmd_flags); 2916 2917 if (rc != 0) 2918 goto bce_nvram_write_locked_exit; 2919 2920 cmd_flags = 0; 2921 buf += 4; 2922 } 2923 2924 /* Loop to write back the buffer data from data_end 2925 * to page_end */ 2926 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2927 for (addr = data_end; addr < page_end; 2928 addr += 4, i += 4) { 2929 2930 if (addr == page_end-4) { 2931 cmd_flags = BCE_NVM_COMMAND_LAST; 2932 } 2933 rc = bce_nvram_write_dword(sc, addr, 2934 &flash_buffer[i], cmd_flags); 2935 2936 if (rc != 0) 2937 goto bce_nvram_write_locked_exit; 2938 2939 cmd_flags = 0; 2940 } 2941 } 2942 2943 /* Disable writes to flash interface (lock write-protect) */ 2944 bce_disable_nvram_write(sc); 2945 2946 /* Disable access to flash interface */ 2947 bce_disable_nvram_access(sc); 2948 bce_release_nvram_lock(sc); 2949 2950 /* Increment written */ 2951 written += data_end - data_start; 2952 } 2953 2954 goto bce_nvram_write_exit; 2955 2956 bce_nvram_write_locked_exit: 2957 bce_disable_nvram_write(sc); 2958 bce_disable_nvram_access(sc); 2959 bce_release_nvram_lock(sc); 2960 2961 bce_nvram_write_exit: 2962 if (align_start || align_end) 2963 free(buf, M_DEVBUF); 2964 2965 DBEXIT(BCE_VERBOSE_NVRAM); 2966 return (rc); 2967 } 2968 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2969 2970 2971 /****************************************************************************/ 2972 /* Verifies that NVRAM is accessible and contains valid data. */ 2973 /* */ 2974 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2975 /* correct. */ 2976 /* */ 2977 /* Returns: */ 2978 /* 0 on success, positive value on failure. */ 2979 /****************************************************************************/ 2980 static int 2981 bce_nvram_test(struct bce_softc *sc) 2982 { 2983 u32 buf[BCE_NVRAM_SIZE / 4]; 2984 u8 *data = (u8 *) buf; 2985 int rc = 0; 2986 u32 magic, csum; 2987 2988 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2989 2990 /* 2991 * Check that the device NVRAM is valid by reading 2992 * the magic value at offset 0. 2993 */ 2994 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2995 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2996 __FILE__, __LINE__); 2997 goto bce_nvram_test_exit; 2998 } 2999 3000 /* 3001 * Verify that offset 0 of the NVRAM contains 3002 * a valid magic number. 3003 */ 3004 magic = bce_be32toh(buf[0]); 3005 if (magic != BCE_NVRAM_MAGIC) { 3006 rc = ENODEV; 3007 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 3008 "Expected: 0x%08X, Found: 0x%08X\n", 3009 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 3010 goto bce_nvram_test_exit; 3011 } 3012 3013 /* 3014 * Verify that the device NVRAM includes valid 3015 * configuration data. 3016 */ 3017 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 3018 BCE_PRINTF("%s(%d): Unable to read manufacturing " 3019 "Information from NVRAM!\n", __FILE__, __LINE__); 3020 goto bce_nvram_test_exit; 3021 } 3022 3023 csum = ether_crc32_le(data, 0x100); 3024 if (csum != BCE_CRC32_RESIDUAL) { 3025 rc = ENODEV; 3026 BCE_PRINTF("%s(%d): Invalid manufacturing information " 3027 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 3028 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 3029 goto bce_nvram_test_exit; 3030 } 3031 3032 csum = ether_crc32_le(data + 0x100, 0x100); 3033 if (csum != BCE_CRC32_RESIDUAL) { 3034 rc = ENODEV; 3035 BCE_PRINTF("%s(%d): Invalid feature configuration " 3036 "information NVRAM CRC! Expected: 0x%08X, " 3037 "Found: 08%08X\n", __FILE__, __LINE__, 3038 BCE_CRC32_RESIDUAL, csum); 3039 } 3040 3041 bce_nvram_test_exit: 3042 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 3043 return rc; 3044 } 3045 3046 3047 /****************************************************************************/ 3048 /* Calculates the size of the buffers to allocate based on the MTU. */ 3049 /* */ 3050 /* Returns: */ 3051 /* Nothing. */ 3052 /****************************************************************************/ 3053 static void 3054 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3055 { 3056 DBENTER(BCE_VERBOSE_LOAD); 3057 3058 /* Use a single allocation type when header splitting enabled. */ 3059 if (bce_hdr_split == TRUE) { 3060 sc->rx_bd_mbuf_alloc_size = MHLEN; 3061 /* Make sure offset is 16 byte aligned for hardware. */ 3062 sc->rx_bd_mbuf_align_pad = 3063 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 3064 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3065 sc->rx_bd_mbuf_align_pad; 3066 } else { 3067 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3068 ETHER_CRC_LEN) > MCLBYTES) { 3069 /* Setup for jumbo RX buffer allocations. */ 3070 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3071 sc->rx_bd_mbuf_align_pad = 3072 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3073 sc->rx_bd_mbuf_data_len = 3074 sc->rx_bd_mbuf_alloc_size - 3075 sc->rx_bd_mbuf_align_pad; 3076 } else { 3077 /* Setup for standard RX buffer allocations. */ 3078 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3079 sc->rx_bd_mbuf_align_pad = 3080 roundup2(MCLBYTES, 16) - MCLBYTES; 3081 sc->rx_bd_mbuf_data_len = 3082 sc->rx_bd_mbuf_alloc_size - 3083 sc->rx_bd_mbuf_align_pad; 3084 } 3085 } 3086 3087 // DBPRINT(sc, BCE_INFO_LOAD, 3088 DBPRINT(sc, BCE_WARN, 3089 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3090 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3091 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3092 sc->rx_bd_mbuf_align_pad); 3093 3094 DBEXIT(BCE_VERBOSE_LOAD); 3095 } 3096 3097 /****************************************************************************/ 3098 /* Identifies the current media type of the controller and sets the PHY */ 3099 /* address. */ 3100 /* */ 3101 /* Returns: */ 3102 /* Nothing. */ 3103 /****************************************************************************/ 3104 static void 3105 bce_get_media(struct bce_softc *sc) 3106 { 3107 u32 val; 3108 3109 DBENTER(BCE_VERBOSE_PHY); 3110 3111 /* Assume PHY address for copper controllers. */ 3112 sc->bce_phy_addr = 1; 3113 3114 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3115 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3116 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3117 u32 strap; 3118 3119 /* 3120 * The BCM5709S is software configurable 3121 * for Copper or SerDes operation. 3122 */ 3123 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3124 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3125 "for copper.\n"); 3126 goto bce_get_media_exit; 3127 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3128 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3129 "for dual media.\n"); 3130 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3131 goto bce_get_media_exit; 3132 } 3133 3134 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3135 strap = (val & 3136 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3137 else 3138 strap = (val & 3139 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3140 3141 if (pci_get_function(sc->bce_dev) == 0) { 3142 switch (strap) { 3143 case 0x4: 3144 case 0x5: 3145 case 0x6: 3146 DBPRINT(sc, BCE_INFO_LOAD, 3147 "BCM5709 s/w configured for SerDes.\n"); 3148 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3149 break; 3150 default: 3151 DBPRINT(sc, BCE_INFO_LOAD, 3152 "BCM5709 s/w configured for Copper.\n"); 3153 break; 3154 } 3155 } else { 3156 switch (strap) { 3157 case 0x1: 3158 case 0x2: 3159 case 0x4: 3160 DBPRINT(sc, BCE_INFO_LOAD, 3161 "BCM5709 s/w configured for SerDes.\n"); 3162 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3163 break; 3164 default: 3165 DBPRINT(sc, BCE_INFO_LOAD, 3166 "BCM5709 s/w configured for Copper.\n"); 3167 break; 3168 } 3169 } 3170 3171 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3172 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3173 3174 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3175 3176 sc->bce_flags |= BCE_NO_WOL_FLAG; 3177 3178 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3179 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3180 3181 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3182 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3183 sc->bce_phy_addr = 2; 3184 3185 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3186 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3187 sc->bce_phy_flags |= 3188 BCE_PHY_2_5G_CAPABLE_FLAG; 3189 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3190 "capable adapter\n"); 3191 } 3192 } 3193 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3194 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3195 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3196 3197 bce_get_media_exit: 3198 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3199 "Using PHY address %d.\n", sc->bce_phy_addr); 3200 3201 DBEXIT(BCE_VERBOSE_PHY); 3202 } 3203 3204 3205 /****************************************************************************/ 3206 /* Performs PHY initialization required before MII drivers access the */ 3207 /* device. */ 3208 /* */ 3209 /* Returns: */ 3210 /* Nothing. */ 3211 /****************************************************************************/ 3212 static void 3213 bce_init_media(struct bce_softc *sc) 3214 { 3215 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3216 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3217 /* 3218 * Configure 5709S/5716S PHYs to use traditional IEEE 3219 * Clause 22 method. Otherwise we have no way to attach 3220 * the PHY in mii(4) layer. PHY specific configuration 3221 * is done in mii layer. 3222 */ 3223 3224 /* Select auto-negotiation MMD of the PHY. */ 3225 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3226 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3227 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3228 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3229 3230 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3231 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3232 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3233 } 3234 } 3235 3236 3237 /****************************************************************************/ 3238 /* Free any DMA memory owned by the driver. */ 3239 /* */ 3240 /* Scans through each data structre that requires DMA memory and frees */ 3241 /* the memory if allocated. */ 3242 /* */ 3243 /* Returns: */ 3244 /* Nothing. */ 3245 /****************************************************************************/ 3246 static void 3247 bce_dma_free(struct bce_softc *sc) 3248 { 3249 int i; 3250 3251 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3252 3253 /* Free, unmap, and destroy the status block. */ 3254 if (sc->status_block_paddr != 0) { 3255 bus_dmamap_unload( 3256 sc->status_tag, 3257 sc->status_map); 3258 sc->status_block_paddr = 0; 3259 } 3260 3261 if (sc->status_block != NULL) { 3262 bus_dmamem_free( 3263 sc->status_tag, 3264 sc->status_block, 3265 sc->status_map); 3266 sc->status_block = NULL; 3267 } 3268 3269 if (sc->status_tag != NULL) { 3270 bus_dma_tag_destroy(sc->status_tag); 3271 sc->status_tag = NULL; 3272 } 3273 3274 3275 /* Free, unmap, and destroy the statistics block. */ 3276 if (sc->stats_block_paddr != 0) { 3277 bus_dmamap_unload( 3278 sc->stats_tag, 3279 sc->stats_map); 3280 sc->stats_block_paddr = 0; 3281 } 3282 3283 if (sc->stats_block != NULL) { 3284 bus_dmamem_free( 3285 sc->stats_tag, 3286 sc->stats_block, 3287 sc->stats_map); 3288 sc->stats_block = NULL; 3289 } 3290 3291 if (sc->stats_tag != NULL) { 3292 bus_dma_tag_destroy(sc->stats_tag); 3293 sc->stats_tag = NULL; 3294 } 3295 3296 3297 /* Free, unmap and destroy all context memory pages. */ 3298 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3299 for (i = 0; i < sc->ctx_pages; i++ ) { 3300 if (sc->ctx_paddr[i] != 0) { 3301 bus_dmamap_unload( 3302 sc->ctx_tag, 3303 sc->ctx_map[i]); 3304 sc->ctx_paddr[i] = 0; 3305 } 3306 3307 if (sc->ctx_block[i] != NULL) { 3308 bus_dmamem_free( 3309 sc->ctx_tag, 3310 sc->ctx_block[i], 3311 sc->ctx_map[i]); 3312 sc->ctx_block[i] = NULL; 3313 } 3314 } 3315 3316 /* Destroy the context memory tag. */ 3317 if (sc->ctx_tag != NULL) { 3318 bus_dma_tag_destroy(sc->ctx_tag); 3319 sc->ctx_tag = NULL; 3320 } 3321 } 3322 3323 3324 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3325 for (i = 0; i < sc->tx_pages; i++ ) { 3326 if (sc->tx_bd_chain_paddr[i] != 0) { 3327 bus_dmamap_unload( 3328 sc->tx_bd_chain_tag, 3329 sc->tx_bd_chain_map[i]); 3330 sc->tx_bd_chain_paddr[i] = 0; 3331 } 3332 3333 if (sc->tx_bd_chain[i] != NULL) { 3334 bus_dmamem_free( 3335 sc->tx_bd_chain_tag, 3336 sc->tx_bd_chain[i], 3337 sc->tx_bd_chain_map[i]); 3338 sc->tx_bd_chain[i] = NULL; 3339 } 3340 } 3341 3342 /* Destroy the TX buffer descriptor tag. */ 3343 if (sc->tx_bd_chain_tag != NULL) { 3344 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3345 sc->tx_bd_chain_tag = NULL; 3346 } 3347 3348 3349 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3350 for (i = 0; i < sc->rx_pages; i++ ) { 3351 if (sc->rx_bd_chain_paddr[i] != 0) { 3352 bus_dmamap_unload( 3353 sc->rx_bd_chain_tag, 3354 sc->rx_bd_chain_map[i]); 3355 sc->rx_bd_chain_paddr[i] = 0; 3356 } 3357 3358 if (sc->rx_bd_chain[i] != NULL) { 3359 bus_dmamem_free( 3360 sc->rx_bd_chain_tag, 3361 sc->rx_bd_chain[i], 3362 sc->rx_bd_chain_map[i]); 3363 sc->rx_bd_chain[i] = NULL; 3364 } 3365 } 3366 3367 /* Destroy the RX buffer descriptor tag. */ 3368 if (sc->rx_bd_chain_tag != NULL) { 3369 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3370 sc->rx_bd_chain_tag = NULL; 3371 } 3372 3373 3374 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3375 if (bce_hdr_split == TRUE) { 3376 for (i = 0; i < sc->pg_pages; i++ ) { 3377 if (sc->pg_bd_chain_paddr[i] != 0) { 3378 bus_dmamap_unload( 3379 sc->pg_bd_chain_tag, 3380 sc->pg_bd_chain_map[i]); 3381 sc->pg_bd_chain_paddr[i] = 0; 3382 } 3383 3384 if (sc->pg_bd_chain[i] != NULL) { 3385 bus_dmamem_free( 3386 sc->pg_bd_chain_tag, 3387 sc->pg_bd_chain[i], 3388 sc->pg_bd_chain_map[i]); 3389 sc->pg_bd_chain[i] = NULL; 3390 } 3391 } 3392 3393 /* Destroy the page buffer descriptor tag. */ 3394 if (sc->pg_bd_chain_tag != NULL) { 3395 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3396 sc->pg_bd_chain_tag = NULL; 3397 } 3398 } 3399 3400 3401 /* Unload and destroy the TX mbuf maps. */ 3402 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3403 if (sc->tx_mbuf_map[i] != NULL) { 3404 bus_dmamap_unload(sc->tx_mbuf_tag, 3405 sc->tx_mbuf_map[i]); 3406 bus_dmamap_destroy(sc->tx_mbuf_tag, 3407 sc->tx_mbuf_map[i]); 3408 sc->tx_mbuf_map[i] = NULL; 3409 } 3410 } 3411 3412 /* Destroy the TX mbuf tag. */ 3413 if (sc->tx_mbuf_tag != NULL) { 3414 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3415 sc->tx_mbuf_tag = NULL; 3416 } 3417 3418 /* Unload and destroy the RX mbuf maps. */ 3419 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3420 if (sc->rx_mbuf_map[i] != NULL) { 3421 bus_dmamap_unload(sc->rx_mbuf_tag, 3422 sc->rx_mbuf_map[i]); 3423 bus_dmamap_destroy(sc->rx_mbuf_tag, 3424 sc->rx_mbuf_map[i]); 3425 sc->rx_mbuf_map[i] = NULL; 3426 } 3427 } 3428 3429 /* Destroy the RX mbuf tag. */ 3430 if (sc->rx_mbuf_tag != NULL) { 3431 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3432 sc->rx_mbuf_tag = NULL; 3433 } 3434 3435 /* Unload and destroy the page mbuf maps. */ 3436 if (bce_hdr_split == TRUE) { 3437 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3438 if (sc->pg_mbuf_map[i] != NULL) { 3439 bus_dmamap_unload(sc->pg_mbuf_tag, 3440 sc->pg_mbuf_map[i]); 3441 bus_dmamap_destroy(sc->pg_mbuf_tag, 3442 sc->pg_mbuf_map[i]); 3443 sc->pg_mbuf_map[i] = NULL; 3444 } 3445 } 3446 3447 /* Destroy the page mbuf tag. */ 3448 if (sc->pg_mbuf_tag != NULL) { 3449 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3450 sc->pg_mbuf_tag = NULL; 3451 } 3452 } 3453 3454 /* Destroy the parent tag */ 3455 if (sc->parent_tag != NULL) { 3456 bus_dma_tag_destroy(sc->parent_tag); 3457 sc->parent_tag = NULL; 3458 } 3459 3460 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3461 } 3462 3463 3464 /****************************************************************************/ 3465 /* Get DMA memory from the OS. */ 3466 /* */ 3467 /* Validates that the OS has provided DMA buffers in response to a */ 3468 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3469 /* When the callback is used the OS will return 0 for the mapping function */ 3470 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3471 /* failures back to the caller. */ 3472 /* */ 3473 /* Returns: */ 3474 /* Nothing. */ 3475 /****************************************************************************/ 3476 static void 3477 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3478 { 3479 bus_addr_t *busaddr = arg; 3480 3481 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3482 __FUNCTION__, nseg)); 3483 /* Simulate a mapping failure. */ 3484 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3485 error = ENOMEM); 3486 3487 /* ToDo: How to increment debug sim_count variable here? */ 3488 3489 /* Check for an error and signal the caller that an error occurred. */ 3490 if (error) { 3491 *busaddr = 0; 3492 } else { 3493 *busaddr = segs->ds_addr; 3494 } 3495 } 3496 3497 3498 /****************************************************************************/ 3499 /* Allocate any DMA memory needed by the driver. */ 3500 /* */ 3501 /* Allocates DMA memory needed for the various global structures needed by */ 3502 /* hardware. */ 3503 /* */ 3504 /* Memory alignment requirements: */ 3505 /* +-----------------+----------+----------+----------+----------+ */ 3506 /* | | 5706 | 5708 | 5709 | 5716 | */ 3507 /* +-----------------+----------+----------+----------+----------+ */ 3508 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3509 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3510 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3511 /* |PG Buffers | none | none | none | none | */ 3512 /* |TX Buffers | none | none | none | none | */ 3513 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3514 /* |Context Memory | | | | | */ 3515 /* +-----------------+----------+----------+----------+----------+ */ 3516 /* */ 3517 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3518 /* */ 3519 /* Returns: */ 3520 /* 0 for success, positive value for failure. */ 3521 /****************************************************************************/ 3522 static int 3523 bce_dma_alloc(device_t dev) 3524 { 3525 struct bce_softc *sc; 3526 int i, error, rc = 0; 3527 bus_size_t max_size, max_seg_size; 3528 int max_segments; 3529 3530 sc = device_get_softc(dev); 3531 3532 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3533 3534 /* 3535 * Allocate the parent bus DMA tag appropriate for PCI. 3536 */ 3537 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3538 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3539 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3540 &sc->parent_tag)) { 3541 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3542 __FILE__, __LINE__); 3543 rc = ENOMEM; 3544 goto bce_dma_alloc_exit; 3545 } 3546 3547 /* 3548 * Create a DMA tag for the status block, allocate and clear the 3549 * memory, map the memory into DMA space, and fetch the physical 3550 * address of the block. 3551 */ 3552 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3553 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3554 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3555 0, NULL, NULL, &sc->status_tag)) { 3556 BCE_PRINTF("%s(%d): Could not allocate status block " 3557 "DMA tag!\n", __FILE__, __LINE__); 3558 rc = ENOMEM; 3559 goto bce_dma_alloc_exit; 3560 } 3561 3562 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3563 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3564 &sc->status_map)) { 3565 BCE_PRINTF("%s(%d): Could not allocate status block " 3566 "DMA memory!\n", __FILE__, __LINE__); 3567 rc = ENOMEM; 3568 goto bce_dma_alloc_exit; 3569 } 3570 3571 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3572 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3573 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3574 3575 if (error || sc->status_block_paddr == 0) { 3576 BCE_PRINTF("%s(%d): Could not map status block " 3577 "DMA memory!\n", __FILE__, __LINE__); 3578 rc = ENOMEM; 3579 goto bce_dma_alloc_exit; 3580 } 3581 3582 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3583 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3584 3585 /* 3586 * Create a DMA tag for the statistics block, allocate and clear the 3587 * memory, map the memory into DMA space, and fetch the physical 3588 * address of the block. 3589 */ 3590 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3591 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3592 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3593 0, NULL, NULL, &sc->stats_tag)) { 3594 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3595 "DMA tag!\n", __FILE__, __LINE__); 3596 rc = ENOMEM; 3597 goto bce_dma_alloc_exit; 3598 } 3599 3600 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3601 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3602 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3603 "DMA memory!\n", __FILE__, __LINE__); 3604 rc = ENOMEM; 3605 goto bce_dma_alloc_exit; 3606 } 3607 3608 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3609 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3610 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3611 3612 if (error || sc->stats_block_paddr == 0) { 3613 BCE_PRINTF("%s(%d): Could not map statistics block " 3614 "DMA memory!\n", __FILE__, __LINE__); 3615 rc = ENOMEM; 3616 goto bce_dma_alloc_exit; 3617 } 3618 3619 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3620 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3621 3622 /* BCM5709 uses host memory as cache for context memory. */ 3623 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3624 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3625 if (sc->ctx_pages == 0) 3626 sc->ctx_pages = 1; 3627 3628 DBRUNIF((sc->ctx_pages > 512), 3629 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3630 __FILE__, __LINE__, sc->ctx_pages)); 3631 3632 /* 3633 * Create a DMA tag for the context pages, 3634 * allocate and clear the memory, map the 3635 * memory into DMA space, and fetch the 3636 * physical address of the block. 3637 */ 3638 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3639 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3640 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3641 0, NULL, NULL, &sc->ctx_tag)) { 3642 BCE_PRINTF("%s(%d): Could not allocate CTX " 3643 "DMA tag!\n", __FILE__, __LINE__); 3644 rc = ENOMEM; 3645 goto bce_dma_alloc_exit; 3646 } 3647 3648 for (i = 0; i < sc->ctx_pages; i++) { 3649 3650 if(bus_dmamem_alloc(sc->ctx_tag, 3651 (void **)&sc->ctx_block[i], 3652 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3653 &sc->ctx_map[i])) { 3654 BCE_PRINTF("%s(%d): Could not allocate CTX " 3655 "DMA memory!\n", __FILE__, __LINE__); 3656 rc = ENOMEM; 3657 goto bce_dma_alloc_exit; 3658 } 3659 3660 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3661 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3662 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3663 3664 if (error || sc->ctx_paddr[i] == 0) { 3665 BCE_PRINTF("%s(%d): Could not map CTX " 3666 "DMA memory!\n", __FILE__, __LINE__); 3667 rc = ENOMEM; 3668 goto bce_dma_alloc_exit; 3669 } 3670 3671 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3672 "= 0x%jX\n", __FUNCTION__, i, 3673 (uintmax_t) sc->ctx_paddr[i]); 3674 } 3675 } 3676 3677 /* 3678 * Create a DMA tag for the TX buffer descriptor chain, 3679 * allocate and clear the memory, and fetch the 3680 * physical address of the block. 3681 */ 3682 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3683 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3684 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3685 NULL, NULL, &sc->tx_bd_chain_tag)) { 3686 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3687 "chain DMA tag!\n", __FILE__, __LINE__); 3688 rc = ENOMEM; 3689 goto bce_dma_alloc_exit; 3690 } 3691 3692 for (i = 0; i < sc->tx_pages; i++) { 3693 3694 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3695 (void **)&sc->tx_bd_chain[i], 3696 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3697 &sc->tx_bd_chain_map[i])) { 3698 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3699 "chain DMA memory!\n", __FILE__, __LINE__); 3700 rc = ENOMEM; 3701 goto bce_dma_alloc_exit; 3702 } 3703 3704 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3705 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3706 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3707 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3708 3709 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3710 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3711 "chain DMA memory!\n", __FILE__, __LINE__); 3712 rc = ENOMEM; 3713 goto bce_dma_alloc_exit; 3714 } 3715 3716 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3717 "0x%jX\n", __FUNCTION__, i, 3718 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3719 } 3720 3721 /* Check the required size before mapping to conserve resources. */ 3722 if (bce_tso_enable) { 3723 max_size = BCE_TSO_MAX_SIZE; 3724 max_segments = BCE_MAX_SEGMENTS; 3725 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3726 } else { 3727 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3728 max_segments = BCE_MAX_SEGMENTS; 3729 max_seg_size = MCLBYTES; 3730 } 3731 3732 /* Create a DMA tag for TX mbufs. */ 3733 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3734 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3735 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3736 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3737 __FILE__, __LINE__); 3738 rc = ENOMEM; 3739 goto bce_dma_alloc_exit; 3740 } 3741 3742 /* Create DMA maps for the TX mbufs clusters. */ 3743 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3744 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3745 &sc->tx_mbuf_map[i])) { 3746 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3747 "map!\n", __FILE__, __LINE__); 3748 rc = ENOMEM; 3749 goto bce_dma_alloc_exit; 3750 } 3751 } 3752 3753 /* 3754 * Create a DMA tag for the RX buffer descriptor chain, 3755 * allocate and clear the memory, and fetch the physical 3756 * address of the blocks. 3757 */ 3758 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3759 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3760 sc->max_bus_addr, NULL, NULL, 3761 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3762 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3763 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3764 "DMA tag!\n", __FILE__, __LINE__); 3765 rc = ENOMEM; 3766 goto bce_dma_alloc_exit; 3767 } 3768 3769 for (i = 0; i < sc->rx_pages; i++) { 3770 3771 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3772 (void **)&sc->rx_bd_chain[i], 3773 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3774 &sc->rx_bd_chain_map[i])) { 3775 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3776 "chain DMA memory!\n", __FILE__, __LINE__); 3777 rc = ENOMEM; 3778 goto bce_dma_alloc_exit; 3779 } 3780 3781 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3782 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3783 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3784 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3785 3786 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3787 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3788 "chain DMA memory!\n", __FILE__, __LINE__); 3789 rc = ENOMEM; 3790 goto bce_dma_alloc_exit; 3791 } 3792 3793 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3794 "0x%jX\n", __FUNCTION__, i, 3795 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3796 } 3797 3798 /* 3799 * Create a DMA tag for RX mbufs. 3800 */ 3801 if (bce_hdr_split == TRUE) 3802 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3803 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3804 else 3805 max_size = MJUM9BYTES; 3806 3807 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3808 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3809 3810 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3811 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3812 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3813 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3814 __FILE__, __LINE__); 3815 rc = ENOMEM; 3816 goto bce_dma_alloc_exit; 3817 } 3818 3819 /* Create DMA maps for the RX mbuf clusters. */ 3820 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3821 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3822 &sc->rx_mbuf_map[i])) { 3823 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3824 "DMA map!\n", __FILE__, __LINE__); 3825 rc = ENOMEM; 3826 goto bce_dma_alloc_exit; 3827 } 3828 } 3829 3830 if (bce_hdr_split == TRUE) { 3831 /* 3832 * Create a DMA tag for the page buffer descriptor chain, 3833 * allocate and clear the memory, and fetch the physical 3834 * address of the blocks. 3835 */ 3836 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3837 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3838 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3839 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3840 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3841 "chain DMA tag!\n", __FILE__, __LINE__); 3842 rc = ENOMEM; 3843 goto bce_dma_alloc_exit; 3844 } 3845 3846 for (i = 0; i < sc->pg_pages; i++) { 3847 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3848 (void **)&sc->pg_bd_chain[i], 3849 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3850 &sc->pg_bd_chain_map[i])) { 3851 BCE_PRINTF("%s(%d): Could not allocate page " 3852 "descriptor chain DMA memory!\n", 3853 __FILE__, __LINE__); 3854 rc = ENOMEM; 3855 goto bce_dma_alloc_exit; 3856 } 3857 3858 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3859 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3860 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3861 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3862 3863 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3864 BCE_PRINTF("%s(%d): Could not map page descriptor " 3865 "chain DMA memory!\n", __FILE__, __LINE__); 3866 rc = ENOMEM; 3867 goto bce_dma_alloc_exit; 3868 } 3869 3870 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3871 "0x%jX\n", __FUNCTION__, i, 3872 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3873 } 3874 3875 /* 3876 * Create a DMA tag for page mbufs. 3877 */ 3878 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3879 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3880 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3881 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3882 "DMA tag!\n", __FILE__, __LINE__); 3883 rc = ENOMEM; 3884 goto bce_dma_alloc_exit; 3885 } 3886 3887 /* Create DMA maps for the page mbuf clusters. */ 3888 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3889 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3890 &sc->pg_mbuf_map[i])) { 3891 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3892 "DMA map!\n", __FILE__, __LINE__); 3893 rc = ENOMEM; 3894 goto bce_dma_alloc_exit; 3895 } 3896 } 3897 } 3898 3899 bce_dma_alloc_exit: 3900 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3901 return(rc); 3902 } 3903 3904 3905 /****************************************************************************/ 3906 /* Release all resources used by the driver. */ 3907 /* */ 3908 /* Releases all resources acquired by the driver including interrupts, */ 3909 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3910 /* */ 3911 /* Returns: */ 3912 /* Nothing. */ 3913 /****************************************************************************/ 3914 static void 3915 bce_release_resources(struct bce_softc *sc) 3916 { 3917 device_t dev; 3918 3919 DBENTER(BCE_VERBOSE_RESET); 3920 3921 dev = sc->bce_dev; 3922 3923 bce_dma_free(sc); 3924 3925 if (sc->bce_intrhand != NULL) { 3926 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3927 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3928 } 3929 3930 if (sc->bce_res_irq != NULL) { 3931 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3932 bus_release_resource(dev, SYS_RES_IRQ, 3933 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3934 } 3935 3936 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3937 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3938 pci_release_msi(dev); 3939 } 3940 3941 if (sc->bce_res_mem != NULL) { 3942 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3943 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3944 sc->bce_res_mem); 3945 } 3946 3947 if (sc->bce_ifp != NULL) { 3948 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3949 if_free(sc->bce_ifp); 3950 } 3951 3952 if (mtx_initialized(&sc->bce_mtx)) 3953 BCE_LOCK_DESTROY(sc); 3954 3955 DBEXIT(BCE_VERBOSE_RESET); 3956 } 3957 3958 3959 /****************************************************************************/ 3960 /* Firmware synchronization. */ 3961 /* */ 3962 /* Before performing certain events such as a chip reset, synchronize with */ 3963 /* the firmware first. */ 3964 /* */ 3965 /* Returns: */ 3966 /* 0 for success, positive value for failure. */ 3967 /****************************************************************************/ 3968 static int 3969 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3970 { 3971 int i, rc = 0; 3972 u32 val; 3973 3974 DBENTER(BCE_VERBOSE_RESET); 3975 3976 /* Don't waste any time if we've timed out before. */ 3977 if (sc->bce_fw_timed_out == TRUE) { 3978 rc = EBUSY; 3979 goto bce_fw_sync_exit; 3980 } 3981 3982 /* Increment the message sequence number. */ 3983 sc->bce_fw_wr_seq++; 3984 msg_data |= sc->bce_fw_wr_seq; 3985 3986 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3987 "0x%08X\n", msg_data); 3988 3989 /* Send the message to the bootcode driver mailbox. */ 3990 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3991 3992 /* Wait for the bootcode to acknowledge the message. */ 3993 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3994 /* Check for a response in the bootcode firmware mailbox. */ 3995 val = bce_shmem_rd(sc, BCE_FW_MB); 3996 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3997 break; 3998 DELAY(1000); 3999 } 4000 4001 /* If we've timed out, tell bootcode that we've stopped waiting. */ 4002 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 4003 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 4004 4005 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 4006 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 4007 4008 msg_data &= ~BCE_DRV_MSG_CODE; 4009 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 4010 4011 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4012 4013 sc->bce_fw_timed_out = TRUE; 4014 rc = EBUSY; 4015 } 4016 4017 bce_fw_sync_exit: 4018 DBEXIT(BCE_VERBOSE_RESET); 4019 return (rc); 4020 } 4021 4022 4023 /****************************************************************************/ 4024 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 4025 /* */ 4026 /* Returns: */ 4027 /* Nothing. */ 4028 /****************************************************************************/ 4029 static void 4030 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4031 u32 rv2p_code_len, u32 rv2p_proc) 4032 { 4033 int i; 4034 u32 val; 4035 4036 DBENTER(BCE_VERBOSE_RESET); 4037 4038 /* Set the page size used by RV2P. */ 4039 if (rv2p_proc == RV2P_PROC2) { 4040 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4041 } 4042 4043 for (i = 0; i < rv2p_code_len; i += 8) { 4044 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4045 rv2p_code++; 4046 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4047 rv2p_code++; 4048 4049 if (rv2p_proc == RV2P_PROC1) { 4050 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4051 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4052 } 4053 else { 4054 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4055 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4056 } 4057 } 4058 4059 /* Reset the processor, un-stall is done later. */ 4060 if (rv2p_proc == RV2P_PROC1) { 4061 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4062 } 4063 else { 4064 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4065 } 4066 4067 DBEXIT(BCE_VERBOSE_RESET); 4068 } 4069 4070 4071 /****************************************************************************/ 4072 /* Load RISC processor firmware. */ 4073 /* */ 4074 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4075 /* associated with a particular processor. */ 4076 /* */ 4077 /* Returns: */ 4078 /* Nothing. */ 4079 /****************************************************************************/ 4080 static void 4081 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4082 struct fw_info *fw) 4083 { 4084 u32 offset; 4085 4086 DBENTER(BCE_VERBOSE_RESET); 4087 4088 bce_halt_cpu(sc, cpu_reg); 4089 4090 /* Load the Text area. */ 4091 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4092 if (fw->text) { 4093 int j; 4094 4095 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4096 REG_WR_IND(sc, offset, fw->text[j]); 4097 } 4098 } 4099 4100 /* Load the Data area. */ 4101 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4102 if (fw->data) { 4103 int j; 4104 4105 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4106 REG_WR_IND(sc, offset, fw->data[j]); 4107 } 4108 } 4109 4110 /* Load the SBSS area. */ 4111 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4112 if (fw->sbss) { 4113 int j; 4114 4115 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4116 REG_WR_IND(sc, offset, fw->sbss[j]); 4117 } 4118 } 4119 4120 /* Load the BSS area. */ 4121 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4122 if (fw->bss) { 4123 int j; 4124 4125 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4126 REG_WR_IND(sc, offset, fw->bss[j]); 4127 } 4128 } 4129 4130 /* Load the Read-Only area. */ 4131 offset = cpu_reg->spad_base + 4132 (fw->rodata_addr - cpu_reg->mips_view_base); 4133 if (fw->rodata) { 4134 int j; 4135 4136 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4137 REG_WR_IND(sc, offset, fw->rodata[j]); 4138 } 4139 } 4140 4141 /* Clear the pre-fetch instruction and set the FW start address. */ 4142 REG_WR_IND(sc, cpu_reg->inst, 0); 4143 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4144 4145 DBEXIT(BCE_VERBOSE_RESET); 4146 } 4147 4148 4149 /****************************************************************************/ 4150 /* Starts the RISC processor. */ 4151 /* */ 4152 /* Assumes the CPU starting address has already been set. */ 4153 /* */ 4154 /* Returns: */ 4155 /* Nothing. */ 4156 /****************************************************************************/ 4157 static void 4158 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4159 { 4160 u32 val; 4161 4162 DBENTER(BCE_VERBOSE_RESET); 4163 4164 /* Start the CPU. */ 4165 val = REG_RD_IND(sc, cpu_reg->mode); 4166 val &= ~cpu_reg->mode_value_halt; 4167 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4168 REG_WR_IND(sc, cpu_reg->mode, val); 4169 4170 DBEXIT(BCE_VERBOSE_RESET); 4171 } 4172 4173 4174 /****************************************************************************/ 4175 /* Halts the RISC processor. */ 4176 /* */ 4177 /* Returns: */ 4178 /* Nothing. */ 4179 /****************************************************************************/ 4180 static void 4181 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4182 { 4183 u32 val; 4184 4185 DBENTER(BCE_VERBOSE_RESET); 4186 4187 /* Halt the CPU. */ 4188 val = REG_RD_IND(sc, cpu_reg->mode); 4189 val |= cpu_reg->mode_value_halt; 4190 REG_WR_IND(sc, cpu_reg->mode, val); 4191 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4192 4193 DBEXIT(BCE_VERBOSE_RESET); 4194 } 4195 4196 4197 /****************************************************************************/ 4198 /* Initialize the RX CPU. */ 4199 /* */ 4200 /* Returns: */ 4201 /* Nothing. */ 4202 /****************************************************************************/ 4203 static void 4204 bce_start_rxp_cpu(struct bce_softc *sc) 4205 { 4206 struct cpu_reg cpu_reg; 4207 4208 DBENTER(BCE_VERBOSE_RESET); 4209 4210 cpu_reg.mode = BCE_RXP_CPU_MODE; 4211 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4212 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4213 cpu_reg.state = BCE_RXP_CPU_STATE; 4214 cpu_reg.state_value_clear = 0xffffff; 4215 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4216 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4217 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4218 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4219 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4220 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4221 cpu_reg.mips_view_base = 0x8000000; 4222 4223 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4224 bce_start_cpu(sc, &cpu_reg); 4225 4226 DBEXIT(BCE_VERBOSE_RESET); 4227 } 4228 4229 4230 /****************************************************************************/ 4231 /* Initialize the RX CPU. */ 4232 /* */ 4233 /* Returns: */ 4234 /* Nothing. */ 4235 /****************************************************************************/ 4236 static void 4237 bce_init_rxp_cpu(struct bce_softc *sc) 4238 { 4239 struct cpu_reg cpu_reg; 4240 struct fw_info fw; 4241 4242 DBENTER(BCE_VERBOSE_RESET); 4243 4244 cpu_reg.mode = BCE_RXP_CPU_MODE; 4245 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4246 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4247 cpu_reg.state = BCE_RXP_CPU_STATE; 4248 cpu_reg.state_value_clear = 0xffffff; 4249 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4250 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4251 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4252 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4253 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4254 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4255 cpu_reg.mips_view_base = 0x8000000; 4256 4257 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4258 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4259 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4260 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4261 fw.start_addr = bce_RXP_b09FwStartAddr; 4262 4263 fw.text_addr = bce_RXP_b09FwTextAddr; 4264 fw.text_len = bce_RXP_b09FwTextLen; 4265 fw.text_index = 0; 4266 fw.text = bce_RXP_b09FwText; 4267 4268 fw.data_addr = bce_RXP_b09FwDataAddr; 4269 fw.data_len = bce_RXP_b09FwDataLen; 4270 fw.data_index = 0; 4271 fw.data = bce_RXP_b09FwData; 4272 4273 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4274 fw.sbss_len = bce_RXP_b09FwSbssLen; 4275 fw.sbss_index = 0; 4276 fw.sbss = bce_RXP_b09FwSbss; 4277 4278 fw.bss_addr = bce_RXP_b09FwBssAddr; 4279 fw.bss_len = bce_RXP_b09FwBssLen; 4280 fw.bss_index = 0; 4281 fw.bss = bce_RXP_b09FwBss; 4282 4283 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4284 fw.rodata_len = bce_RXP_b09FwRodataLen; 4285 fw.rodata_index = 0; 4286 fw.rodata = bce_RXP_b09FwRodata; 4287 } else { 4288 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4289 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4290 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4291 fw.start_addr = bce_RXP_b06FwStartAddr; 4292 4293 fw.text_addr = bce_RXP_b06FwTextAddr; 4294 fw.text_len = bce_RXP_b06FwTextLen; 4295 fw.text_index = 0; 4296 fw.text = bce_RXP_b06FwText; 4297 4298 fw.data_addr = bce_RXP_b06FwDataAddr; 4299 fw.data_len = bce_RXP_b06FwDataLen; 4300 fw.data_index = 0; 4301 fw.data = bce_RXP_b06FwData; 4302 4303 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4304 fw.sbss_len = bce_RXP_b06FwSbssLen; 4305 fw.sbss_index = 0; 4306 fw.sbss = bce_RXP_b06FwSbss; 4307 4308 fw.bss_addr = bce_RXP_b06FwBssAddr; 4309 fw.bss_len = bce_RXP_b06FwBssLen; 4310 fw.bss_index = 0; 4311 fw.bss = bce_RXP_b06FwBss; 4312 4313 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4314 fw.rodata_len = bce_RXP_b06FwRodataLen; 4315 fw.rodata_index = 0; 4316 fw.rodata = bce_RXP_b06FwRodata; 4317 } 4318 4319 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4320 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4321 4322 /* Delay RXP start until initialization is complete. */ 4323 4324 DBEXIT(BCE_VERBOSE_RESET); 4325 } 4326 4327 4328 /****************************************************************************/ 4329 /* Initialize the TX CPU. */ 4330 /* */ 4331 /* Returns: */ 4332 /* Nothing. */ 4333 /****************************************************************************/ 4334 static void 4335 bce_init_txp_cpu(struct bce_softc *sc) 4336 { 4337 struct cpu_reg cpu_reg; 4338 struct fw_info fw; 4339 4340 DBENTER(BCE_VERBOSE_RESET); 4341 4342 cpu_reg.mode = BCE_TXP_CPU_MODE; 4343 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4344 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4345 cpu_reg.state = BCE_TXP_CPU_STATE; 4346 cpu_reg.state_value_clear = 0xffffff; 4347 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4348 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4349 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4350 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4351 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4352 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4353 cpu_reg.mips_view_base = 0x8000000; 4354 4355 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4356 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4357 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4358 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4359 fw.start_addr = bce_TXP_b09FwStartAddr; 4360 4361 fw.text_addr = bce_TXP_b09FwTextAddr; 4362 fw.text_len = bce_TXP_b09FwTextLen; 4363 fw.text_index = 0; 4364 fw.text = bce_TXP_b09FwText; 4365 4366 fw.data_addr = bce_TXP_b09FwDataAddr; 4367 fw.data_len = bce_TXP_b09FwDataLen; 4368 fw.data_index = 0; 4369 fw.data = bce_TXP_b09FwData; 4370 4371 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4372 fw.sbss_len = bce_TXP_b09FwSbssLen; 4373 fw.sbss_index = 0; 4374 fw.sbss = bce_TXP_b09FwSbss; 4375 4376 fw.bss_addr = bce_TXP_b09FwBssAddr; 4377 fw.bss_len = bce_TXP_b09FwBssLen; 4378 fw.bss_index = 0; 4379 fw.bss = bce_TXP_b09FwBss; 4380 4381 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4382 fw.rodata_len = bce_TXP_b09FwRodataLen; 4383 fw.rodata_index = 0; 4384 fw.rodata = bce_TXP_b09FwRodata; 4385 } else { 4386 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4387 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4388 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4389 fw.start_addr = bce_TXP_b06FwStartAddr; 4390 4391 fw.text_addr = bce_TXP_b06FwTextAddr; 4392 fw.text_len = bce_TXP_b06FwTextLen; 4393 fw.text_index = 0; 4394 fw.text = bce_TXP_b06FwText; 4395 4396 fw.data_addr = bce_TXP_b06FwDataAddr; 4397 fw.data_len = bce_TXP_b06FwDataLen; 4398 fw.data_index = 0; 4399 fw.data = bce_TXP_b06FwData; 4400 4401 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4402 fw.sbss_len = bce_TXP_b06FwSbssLen; 4403 fw.sbss_index = 0; 4404 fw.sbss = bce_TXP_b06FwSbss; 4405 4406 fw.bss_addr = bce_TXP_b06FwBssAddr; 4407 fw.bss_len = bce_TXP_b06FwBssLen; 4408 fw.bss_index = 0; 4409 fw.bss = bce_TXP_b06FwBss; 4410 4411 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4412 fw.rodata_len = bce_TXP_b06FwRodataLen; 4413 fw.rodata_index = 0; 4414 fw.rodata = bce_TXP_b06FwRodata; 4415 } 4416 4417 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4418 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4419 bce_start_cpu(sc, &cpu_reg); 4420 4421 DBEXIT(BCE_VERBOSE_RESET); 4422 } 4423 4424 4425 /****************************************************************************/ 4426 /* Initialize the TPAT CPU. */ 4427 /* */ 4428 /* Returns: */ 4429 /* Nothing. */ 4430 /****************************************************************************/ 4431 static void 4432 bce_init_tpat_cpu(struct bce_softc *sc) 4433 { 4434 struct cpu_reg cpu_reg; 4435 struct fw_info fw; 4436 4437 DBENTER(BCE_VERBOSE_RESET); 4438 4439 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4440 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4441 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4442 cpu_reg.state = BCE_TPAT_CPU_STATE; 4443 cpu_reg.state_value_clear = 0xffffff; 4444 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4445 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4446 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4447 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4448 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4449 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4450 cpu_reg.mips_view_base = 0x8000000; 4451 4452 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4453 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4454 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4455 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4456 fw.start_addr = bce_TPAT_b09FwStartAddr; 4457 4458 fw.text_addr = bce_TPAT_b09FwTextAddr; 4459 fw.text_len = bce_TPAT_b09FwTextLen; 4460 fw.text_index = 0; 4461 fw.text = bce_TPAT_b09FwText; 4462 4463 fw.data_addr = bce_TPAT_b09FwDataAddr; 4464 fw.data_len = bce_TPAT_b09FwDataLen; 4465 fw.data_index = 0; 4466 fw.data = bce_TPAT_b09FwData; 4467 4468 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4469 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4470 fw.sbss_index = 0; 4471 fw.sbss = bce_TPAT_b09FwSbss; 4472 4473 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4474 fw.bss_len = bce_TPAT_b09FwBssLen; 4475 fw.bss_index = 0; 4476 fw.bss = bce_TPAT_b09FwBss; 4477 4478 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4479 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4480 fw.rodata_index = 0; 4481 fw.rodata = bce_TPAT_b09FwRodata; 4482 } else { 4483 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4484 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4485 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4486 fw.start_addr = bce_TPAT_b06FwStartAddr; 4487 4488 fw.text_addr = bce_TPAT_b06FwTextAddr; 4489 fw.text_len = bce_TPAT_b06FwTextLen; 4490 fw.text_index = 0; 4491 fw.text = bce_TPAT_b06FwText; 4492 4493 fw.data_addr = bce_TPAT_b06FwDataAddr; 4494 fw.data_len = bce_TPAT_b06FwDataLen; 4495 fw.data_index = 0; 4496 fw.data = bce_TPAT_b06FwData; 4497 4498 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4499 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4500 fw.sbss_index = 0; 4501 fw.sbss = bce_TPAT_b06FwSbss; 4502 4503 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4504 fw.bss_len = bce_TPAT_b06FwBssLen; 4505 fw.bss_index = 0; 4506 fw.bss = bce_TPAT_b06FwBss; 4507 4508 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4509 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4510 fw.rodata_index = 0; 4511 fw.rodata = bce_TPAT_b06FwRodata; 4512 } 4513 4514 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4515 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4516 bce_start_cpu(sc, &cpu_reg); 4517 4518 DBEXIT(BCE_VERBOSE_RESET); 4519 } 4520 4521 4522 /****************************************************************************/ 4523 /* Initialize the CP CPU. */ 4524 /* */ 4525 /* Returns: */ 4526 /* Nothing. */ 4527 /****************************************************************************/ 4528 static void 4529 bce_init_cp_cpu(struct bce_softc *sc) 4530 { 4531 struct cpu_reg cpu_reg; 4532 struct fw_info fw; 4533 4534 DBENTER(BCE_VERBOSE_RESET); 4535 4536 cpu_reg.mode = BCE_CP_CPU_MODE; 4537 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4538 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4539 cpu_reg.state = BCE_CP_CPU_STATE; 4540 cpu_reg.state_value_clear = 0xffffff; 4541 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4542 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4543 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4544 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4545 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4546 cpu_reg.spad_base = BCE_CP_SCRATCH; 4547 cpu_reg.mips_view_base = 0x8000000; 4548 4549 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4550 fw.ver_major = bce_CP_b09FwReleaseMajor; 4551 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4552 fw.ver_fix = bce_CP_b09FwReleaseFix; 4553 fw.start_addr = bce_CP_b09FwStartAddr; 4554 4555 fw.text_addr = bce_CP_b09FwTextAddr; 4556 fw.text_len = bce_CP_b09FwTextLen; 4557 fw.text_index = 0; 4558 fw.text = bce_CP_b09FwText; 4559 4560 fw.data_addr = bce_CP_b09FwDataAddr; 4561 fw.data_len = bce_CP_b09FwDataLen; 4562 fw.data_index = 0; 4563 fw.data = bce_CP_b09FwData; 4564 4565 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4566 fw.sbss_len = bce_CP_b09FwSbssLen; 4567 fw.sbss_index = 0; 4568 fw.sbss = bce_CP_b09FwSbss; 4569 4570 fw.bss_addr = bce_CP_b09FwBssAddr; 4571 fw.bss_len = bce_CP_b09FwBssLen; 4572 fw.bss_index = 0; 4573 fw.bss = bce_CP_b09FwBss; 4574 4575 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4576 fw.rodata_len = bce_CP_b09FwRodataLen; 4577 fw.rodata_index = 0; 4578 fw.rodata = bce_CP_b09FwRodata; 4579 } else { 4580 fw.ver_major = bce_CP_b06FwReleaseMajor; 4581 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4582 fw.ver_fix = bce_CP_b06FwReleaseFix; 4583 fw.start_addr = bce_CP_b06FwStartAddr; 4584 4585 fw.text_addr = bce_CP_b06FwTextAddr; 4586 fw.text_len = bce_CP_b06FwTextLen; 4587 fw.text_index = 0; 4588 fw.text = bce_CP_b06FwText; 4589 4590 fw.data_addr = bce_CP_b06FwDataAddr; 4591 fw.data_len = bce_CP_b06FwDataLen; 4592 fw.data_index = 0; 4593 fw.data = bce_CP_b06FwData; 4594 4595 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4596 fw.sbss_len = bce_CP_b06FwSbssLen; 4597 fw.sbss_index = 0; 4598 fw.sbss = bce_CP_b06FwSbss; 4599 4600 fw.bss_addr = bce_CP_b06FwBssAddr; 4601 fw.bss_len = bce_CP_b06FwBssLen; 4602 fw.bss_index = 0; 4603 fw.bss = bce_CP_b06FwBss; 4604 4605 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4606 fw.rodata_len = bce_CP_b06FwRodataLen; 4607 fw.rodata_index = 0; 4608 fw.rodata = bce_CP_b06FwRodata; 4609 } 4610 4611 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4612 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4613 bce_start_cpu(sc, &cpu_reg); 4614 4615 DBEXIT(BCE_VERBOSE_RESET); 4616 } 4617 4618 4619 /****************************************************************************/ 4620 /* Initialize the COM CPU. */ 4621 /* */ 4622 /* Returns: */ 4623 /* Nothing. */ 4624 /****************************************************************************/ 4625 static void 4626 bce_init_com_cpu(struct bce_softc *sc) 4627 { 4628 struct cpu_reg cpu_reg; 4629 struct fw_info fw; 4630 4631 DBENTER(BCE_VERBOSE_RESET); 4632 4633 cpu_reg.mode = BCE_COM_CPU_MODE; 4634 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4635 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4636 cpu_reg.state = BCE_COM_CPU_STATE; 4637 cpu_reg.state_value_clear = 0xffffff; 4638 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4639 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4640 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4641 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4642 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4643 cpu_reg.spad_base = BCE_COM_SCRATCH; 4644 cpu_reg.mips_view_base = 0x8000000; 4645 4646 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4647 fw.ver_major = bce_COM_b09FwReleaseMajor; 4648 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4649 fw.ver_fix = bce_COM_b09FwReleaseFix; 4650 fw.start_addr = bce_COM_b09FwStartAddr; 4651 4652 fw.text_addr = bce_COM_b09FwTextAddr; 4653 fw.text_len = bce_COM_b09FwTextLen; 4654 fw.text_index = 0; 4655 fw.text = bce_COM_b09FwText; 4656 4657 fw.data_addr = bce_COM_b09FwDataAddr; 4658 fw.data_len = bce_COM_b09FwDataLen; 4659 fw.data_index = 0; 4660 fw.data = bce_COM_b09FwData; 4661 4662 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4663 fw.sbss_len = bce_COM_b09FwSbssLen; 4664 fw.sbss_index = 0; 4665 fw.sbss = bce_COM_b09FwSbss; 4666 4667 fw.bss_addr = bce_COM_b09FwBssAddr; 4668 fw.bss_len = bce_COM_b09FwBssLen; 4669 fw.bss_index = 0; 4670 fw.bss = bce_COM_b09FwBss; 4671 4672 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4673 fw.rodata_len = bce_COM_b09FwRodataLen; 4674 fw.rodata_index = 0; 4675 fw.rodata = bce_COM_b09FwRodata; 4676 } else { 4677 fw.ver_major = bce_COM_b06FwReleaseMajor; 4678 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4679 fw.ver_fix = bce_COM_b06FwReleaseFix; 4680 fw.start_addr = bce_COM_b06FwStartAddr; 4681 4682 fw.text_addr = bce_COM_b06FwTextAddr; 4683 fw.text_len = bce_COM_b06FwTextLen; 4684 fw.text_index = 0; 4685 fw.text = bce_COM_b06FwText; 4686 4687 fw.data_addr = bce_COM_b06FwDataAddr; 4688 fw.data_len = bce_COM_b06FwDataLen; 4689 fw.data_index = 0; 4690 fw.data = bce_COM_b06FwData; 4691 4692 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4693 fw.sbss_len = bce_COM_b06FwSbssLen; 4694 fw.sbss_index = 0; 4695 fw.sbss = bce_COM_b06FwSbss; 4696 4697 fw.bss_addr = bce_COM_b06FwBssAddr; 4698 fw.bss_len = bce_COM_b06FwBssLen; 4699 fw.bss_index = 0; 4700 fw.bss = bce_COM_b06FwBss; 4701 4702 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4703 fw.rodata_len = bce_COM_b06FwRodataLen; 4704 fw.rodata_index = 0; 4705 fw.rodata = bce_COM_b06FwRodata; 4706 } 4707 4708 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4709 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4710 bce_start_cpu(sc, &cpu_reg); 4711 4712 DBEXIT(BCE_VERBOSE_RESET); 4713 } 4714 4715 4716 /****************************************************************************/ 4717 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4718 /* */ 4719 /* Loads the firmware for each CPU and starts the CPU. */ 4720 /* */ 4721 /* Returns: */ 4722 /* Nothing. */ 4723 /****************************************************************************/ 4724 static void 4725 bce_init_cpus(struct bce_softc *sc) 4726 { 4727 DBENTER(BCE_VERBOSE_RESET); 4728 4729 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4730 4731 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4732 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4733 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4734 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4735 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4736 } else { 4737 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4738 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4739 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4740 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4741 } 4742 4743 } else { 4744 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4745 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4746 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4747 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4748 } 4749 4750 bce_init_rxp_cpu(sc); 4751 bce_init_txp_cpu(sc); 4752 bce_init_tpat_cpu(sc); 4753 bce_init_com_cpu(sc); 4754 bce_init_cp_cpu(sc); 4755 4756 DBEXIT(BCE_VERBOSE_RESET); 4757 } 4758 4759 4760 /****************************************************************************/ 4761 /* Initialize context memory. */ 4762 /* */ 4763 /* Clears the memory associated with each Context ID (CID). */ 4764 /* */ 4765 /* Returns: */ 4766 /* Nothing. */ 4767 /****************************************************************************/ 4768 static int 4769 bce_init_ctx(struct bce_softc *sc) 4770 { 4771 u32 offset, val, vcid_addr; 4772 int i, j, rc, retry_cnt; 4773 4774 rc = 0; 4775 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4776 4777 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4778 retry_cnt = CTX_INIT_RETRY_COUNT; 4779 4780 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4781 4782 /* 4783 * BCM5709 context memory may be cached 4784 * in host memory so prepare the host memory 4785 * for access. 4786 */ 4787 val = BCE_CTX_COMMAND_ENABLED | 4788 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4789 val |= (BCM_PAGE_BITS - 8) << 16; 4790 REG_WR(sc, BCE_CTX_COMMAND, val); 4791 4792 /* Wait for mem init command to complete. */ 4793 for (i = 0; i < retry_cnt; i++) { 4794 val = REG_RD(sc, BCE_CTX_COMMAND); 4795 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4796 break; 4797 DELAY(2); 4798 } 4799 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4800 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4801 __FUNCTION__); 4802 rc = EBUSY; 4803 goto init_ctx_fail; 4804 } 4805 4806 for (i = 0; i < sc->ctx_pages; i++) { 4807 /* Set the physical address of the context memory. */ 4808 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4809 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4810 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4811 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4812 BCE_ADDR_HI(sc->ctx_paddr[i])); 4813 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4814 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4815 4816 /* Verify the context memory write was successful. */ 4817 for (j = 0; j < retry_cnt; j++) { 4818 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4819 if ((val & 4820 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4821 break; 4822 DELAY(5); 4823 } 4824 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4825 BCE_PRINTF("%s(): Failed to initialize " 4826 "context page %d!\n", __FUNCTION__, i); 4827 rc = EBUSY; 4828 goto init_ctx_fail; 4829 } 4830 } 4831 } else { 4832 4833 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4834 4835 /* 4836 * For the 5706/5708, context memory is local to 4837 * the controller, so initialize the controller 4838 * context memory. 4839 */ 4840 4841 vcid_addr = GET_CID_ADDR(96); 4842 while (vcid_addr) { 4843 4844 vcid_addr -= PHY_CTX_SIZE; 4845 4846 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4847 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4848 4849 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4850 CTX_WR(sc, 0x00, offset, 0); 4851 } 4852 4853 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4854 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4855 } 4856 4857 } 4858 init_ctx_fail: 4859 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4860 return (rc); 4861 } 4862 4863 4864 /****************************************************************************/ 4865 /* Fetch the permanent MAC address of the controller. */ 4866 /* */ 4867 /* Returns: */ 4868 /* Nothing. */ 4869 /****************************************************************************/ 4870 static void 4871 bce_get_mac_addr(struct bce_softc *sc) 4872 { 4873 u32 mac_lo = 0, mac_hi = 0; 4874 4875 DBENTER(BCE_VERBOSE_RESET); 4876 4877 /* 4878 * The NetXtreme II bootcode populates various NIC 4879 * power-on and runtime configuration items in a 4880 * shared memory area. The factory configured MAC 4881 * address is available from both NVRAM and the 4882 * shared memory area so we'll read the value from 4883 * shared memory for speed. 4884 */ 4885 4886 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4887 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4888 4889 if ((mac_lo == 0) && (mac_hi == 0)) { 4890 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4891 __FILE__, __LINE__); 4892 } else { 4893 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4894 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4895 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4896 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4897 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4898 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4899 } 4900 4901 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4902 "address = %6D\n", sc->eaddr, ":"); 4903 DBEXIT(BCE_VERBOSE_RESET); 4904 } 4905 4906 4907 /****************************************************************************/ 4908 /* Program the MAC address. */ 4909 /* */ 4910 /* Returns: */ 4911 /* Nothing. */ 4912 /****************************************************************************/ 4913 static void 4914 bce_set_mac_addr(struct bce_softc *sc) 4915 { 4916 u32 val; 4917 u8 *mac_addr = sc->eaddr; 4918 4919 /* ToDo: Add support for setting multiple MAC addresses. */ 4920 4921 DBENTER(BCE_VERBOSE_RESET); 4922 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4923 "%6D\n", sc->eaddr, ":"); 4924 4925 val = (mac_addr[0] << 8) | mac_addr[1]; 4926 4927 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4928 4929 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4930 (mac_addr[4] << 8) | mac_addr[5]; 4931 4932 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4933 4934 DBEXIT(BCE_VERBOSE_RESET); 4935 } 4936 4937 4938 /****************************************************************************/ 4939 /* Stop the controller. */ 4940 /* */ 4941 /* Returns: */ 4942 /* Nothing. */ 4943 /****************************************************************************/ 4944 static void 4945 bce_stop(struct bce_softc *sc) 4946 { 4947 struct ifnet *ifp; 4948 4949 DBENTER(BCE_VERBOSE_RESET); 4950 4951 BCE_LOCK_ASSERT(sc); 4952 4953 ifp = sc->bce_ifp; 4954 4955 callout_stop(&sc->bce_tick_callout); 4956 4957 /* Disable the transmit/receive blocks. */ 4958 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4959 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4960 DELAY(20); 4961 4962 bce_disable_intr(sc); 4963 4964 /* Free RX buffers. */ 4965 if (bce_hdr_split == TRUE) { 4966 bce_free_pg_chain(sc); 4967 } 4968 bce_free_rx_chain(sc); 4969 4970 /* Free TX buffers. */ 4971 bce_free_tx_chain(sc); 4972 4973 sc->watchdog_timer = 0; 4974 4975 sc->bce_link_up = FALSE; 4976 4977 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4978 4979 DBEXIT(BCE_VERBOSE_RESET); 4980 } 4981 4982 4983 static int 4984 bce_reset(struct bce_softc *sc, u32 reset_code) 4985 { 4986 u32 emac_mode_save, val; 4987 int i, rc = 0; 4988 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4989 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4990 4991 DBENTER(BCE_VERBOSE_RESET); 4992 4993 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4994 __FUNCTION__, reset_code); 4995 4996 /* 4997 * If ASF/IPMI is operational, then the EMAC Mode register already 4998 * contains appropriate values for the link settings that have 4999 * been auto-negotiated. Resetting the chip will clobber those 5000 * values. Save the important bits so we can restore them after 5001 * the reset. 5002 */ 5003 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 5004 5005 /* Wait for pending PCI transactions to complete. */ 5006 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 5007 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 5008 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 5009 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 5010 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 5011 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 5012 DELAY(5); 5013 5014 /* Disable DMA */ 5015 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5016 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5017 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5018 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5019 } 5020 5021 /* Assume bootcode is running. */ 5022 sc->bce_fw_timed_out = FALSE; 5023 sc->bce_drv_cardiac_arrest = FALSE; 5024 5025 /* Give the firmware a chance to prepare for the reset. */ 5026 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 5027 if (rc) 5028 goto bce_reset_exit; 5029 5030 /* Set a firmware reminder that this is a soft reset. */ 5031 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5032 5033 /* Dummy read to force the chip to complete all current transactions. */ 5034 val = REG_RD(sc, BCE_MISC_ID); 5035 5036 /* Chip reset. */ 5037 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5038 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5039 REG_RD(sc, BCE_MISC_COMMAND); 5040 DELAY(5); 5041 5042 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5043 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5044 5045 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5046 } else { 5047 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5048 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5049 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5050 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5051 5052 /* Allow up to 30us for reset to complete. */ 5053 for (i = 0; i < 10; i++) { 5054 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5055 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5056 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5057 break; 5058 } 5059 DELAY(10); 5060 } 5061 5062 /* Check that reset completed successfully. */ 5063 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5064 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5065 BCE_PRINTF("%s(%d): Reset failed!\n", 5066 __FILE__, __LINE__); 5067 rc = EBUSY; 5068 goto bce_reset_exit; 5069 } 5070 } 5071 5072 /* Make sure byte swapping is properly configured. */ 5073 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5074 if (val != 0x01020304) { 5075 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5076 __FILE__, __LINE__); 5077 rc = ENODEV; 5078 goto bce_reset_exit; 5079 } 5080 5081 /* Just completed a reset, assume that firmware is running again. */ 5082 sc->bce_fw_timed_out = FALSE; 5083 sc->bce_drv_cardiac_arrest = FALSE; 5084 5085 /* Wait for the firmware to finish its initialization. */ 5086 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5087 if (rc) 5088 BCE_PRINTF("%s(%d): Firmware did not complete " 5089 "initialization!\n", __FILE__, __LINE__); 5090 /* Get firmware capabilities. */ 5091 bce_fw_cap_init(sc); 5092 5093 bce_reset_exit: 5094 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5095 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 5096 val = REG_RD(sc, BCE_EMAC_MODE); 5097 val = (val & ~emac_mode_mask) | emac_mode_save; 5098 REG_WR(sc, BCE_EMAC_MODE, val); 5099 } 5100 5101 DBEXIT(BCE_VERBOSE_RESET); 5102 return (rc); 5103 } 5104 5105 5106 static int 5107 bce_chipinit(struct bce_softc *sc) 5108 { 5109 u32 val; 5110 int rc = 0; 5111 5112 DBENTER(BCE_VERBOSE_RESET); 5113 5114 bce_disable_intr(sc); 5115 5116 /* 5117 * Initialize DMA byte/word swapping, configure the number of DMA 5118 * channels and PCI clock compensation delay. 5119 */ 5120 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5121 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5122 #if BYTE_ORDER == BIG_ENDIAN 5123 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5124 #endif 5125 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5126 DMA_READ_CHANS << 12 | 5127 DMA_WRITE_CHANS << 16; 5128 5129 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5130 5131 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5132 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5133 5134 /* 5135 * This setting resolves a problem observed on certain Intel PCI 5136 * chipsets that cannot handle multiple outstanding DMA operations. 5137 * See errata E9_5706A1_65. 5138 */ 5139 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5140 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5141 !(sc->bce_flags & BCE_PCIX_FLAG)) 5142 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5143 5144 REG_WR(sc, BCE_DMA_CONFIG, val); 5145 5146 /* Enable the RX_V2P and Context state machines before access. */ 5147 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5148 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5149 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5150 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5151 5152 /* Initialize context mapping and zero out the quick contexts. */ 5153 if ((rc = bce_init_ctx(sc)) != 0) 5154 goto bce_chipinit_exit; 5155 5156 /* Initialize the on-boards CPUs */ 5157 bce_init_cpus(sc); 5158 5159 /* Enable management frames (NC-SI) to flow to the MCP. */ 5160 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5161 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5162 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5163 } 5164 5165 /* Prepare NVRAM for access. */ 5166 if ((rc = bce_init_nvram(sc)) != 0) 5167 goto bce_chipinit_exit; 5168 5169 /* Set the kernel bypass block size */ 5170 val = REG_RD(sc, BCE_MQ_CONFIG); 5171 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5172 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5173 5174 /* Enable bins used on the 5709. */ 5175 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5176 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5177 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5178 val |= BCE_MQ_CONFIG_HALT_DIS; 5179 } 5180 5181 REG_WR(sc, BCE_MQ_CONFIG, val); 5182 5183 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5184 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5185 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5186 5187 /* Set the page size and clear the RV2P processor stall bits. */ 5188 val = (BCM_PAGE_BITS - 8) << 24; 5189 REG_WR(sc, BCE_RV2P_CONFIG, val); 5190 5191 /* Configure page size. */ 5192 val = REG_RD(sc, BCE_TBDR_CONFIG); 5193 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5194 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5195 REG_WR(sc, BCE_TBDR_CONFIG, val); 5196 5197 /* Set the perfect match control register to default. */ 5198 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5199 5200 bce_chipinit_exit: 5201 DBEXIT(BCE_VERBOSE_RESET); 5202 5203 return(rc); 5204 } 5205 5206 5207 /****************************************************************************/ 5208 /* Initialize the controller in preparation to send/receive traffic. */ 5209 /* */ 5210 /* Returns: */ 5211 /* 0 for success, positive value for failure. */ 5212 /****************************************************************************/ 5213 static int 5214 bce_blockinit(struct bce_softc *sc) 5215 { 5216 u32 reg, val; 5217 int rc = 0; 5218 5219 DBENTER(BCE_VERBOSE_RESET); 5220 5221 /* Load the hardware default MAC address. */ 5222 bce_set_mac_addr(sc); 5223 5224 /* Set the Ethernet backoff seed value */ 5225 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5226 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5227 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5228 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5229 5230 sc->last_status_idx = 0; 5231 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5232 5233 /* Set up link change interrupt generation. */ 5234 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5235 5236 /* Program the physical address of the status block. */ 5237 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5238 BCE_ADDR_LO(sc->status_block_paddr)); 5239 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5240 BCE_ADDR_HI(sc->status_block_paddr)); 5241 5242 /* Program the physical address of the statistics block. */ 5243 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5244 BCE_ADDR_LO(sc->stats_block_paddr)); 5245 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5246 BCE_ADDR_HI(sc->stats_block_paddr)); 5247 5248 /* 5249 * Program various host coalescing parameters. 5250 * Trip points control how many BDs should be ready before generating 5251 * an interrupt while ticks control how long a BD can sit in the chain 5252 * before generating an interrupt. 5253 */ 5254 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5255 (sc->bce_tx_quick_cons_trip_int << 16) | 5256 sc->bce_tx_quick_cons_trip); 5257 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5258 (sc->bce_rx_quick_cons_trip_int << 16) | 5259 sc->bce_rx_quick_cons_trip); 5260 REG_WR(sc, BCE_HC_TX_TICKS, 5261 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5262 REG_WR(sc, BCE_HC_RX_TICKS, 5263 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5264 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5265 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5266 /* Not used for L2. */ 5267 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5268 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5269 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5270 5271 /* Configure the Host Coalescing block. */ 5272 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5273 BCE_HC_CONFIG_COLLECT_STATS; 5274 5275 #if 0 5276 /* ToDo: Add MSI-X support. */ 5277 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5278 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5279 BCE_HC_SB_CONFIG_1; 5280 5281 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5282 5283 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5284 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5285 5286 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5287 (sc->tx_quick_cons_trip_int << 16) | 5288 sc->tx_quick_cons_trip); 5289 5290 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5291 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5292 5293 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5294 } 5295 5296 /* 5297 * Tell the HC block to automatically set the 5298 * INT_MASK bit after an MSI/MSI-X interrupt 5299 * is generated so the driver doesn't have to. 5300 */ 5301 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5302 val |= BCE_HC_CONFIG_ONE_SHOT; 5303 5304 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5305 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5306 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5307 #endif 5308 5309 REG_WR(sc, BCE_HC_CONFIG, val); 5310 5311 /* Clear the internal statistics counters. */ 5312 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5313 5314 /* Verify that bootcode is running. */ 5315 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5316 5317 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5318 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5319 __FILE__, __LINE__); 5320 reg = 0); 5321 5322 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5323 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5324 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5325 "Expected: 08%08X\n", __FILE__, __LINE__, 5326 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5327 BCE_DEV_INFO_SIGNATURE_MAGIC); 5328 rc = ENODEV; 5329 goto bce_blockinit_exit; 5330 } 5331 5332 /* Enable DMA */ 5333 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5334 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5335 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5336 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5337 } 5338 5339 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5340 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5341 BCE_DRV_MSG_CODE_RESET); 5342 5343 /* Enable link state change interrupt generation. */ 5344 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5345 5346 /* Enable the RXP. */ 5347 bce_start_rxp_cpu(sc); 5348 5349 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5350 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5351 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5352 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5353 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5354 } 5355 5356 /* Enable all remaining blocks in the MAC. */ 5357 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5358 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5359 BCE_MISC_ENABLE_DEFAULT_XI); 5360 else 5361 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5362 BCE_MISC_ENABLE_DEFAULT); 5363 5364 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5365 DELAY(20); 5366 5367 /* Save the current host coalescing block settings. */ 5368 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5369 5370 bce_blockinit_exit: 5371 DBEXIT(BCE_VERBOSE_RESET); 5372 5373 return (rc); 5374 } 5375 5376 5377 /****************************************************************************/ 5378 /* Encapsulate an mbuf into the rx_bd chain. */ 5379 /* */ 5380 /* Returns: */ 5381 /* 0 for success, positive value for failure. */ 5382 /****************************************************************************/ 5383 static int 5384 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5385 { 5386 bus_dma_segment_t segs[1]; 5387 struct mbuf *m_new = NULL; 5388 struct rx_bd *rxbd; 5389 int nsegs, error, rc = 0; 5390 #ifdef BCE_DEBUG 5391 u16 debug_chain_prod = chain_prod; 5392 #endif 5393 5394 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5395 5396 /* Make sure the inputs are valid. */ 5397 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5398 BCE_PRINTF("%s(%d): RX producer out of range: " 5399 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5400 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5401 5402 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5403 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5404 prod, chain_prod, *prod_bseq); 5405 5406 /* Update some debug statistic counters */ 5407 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5408 sc->rx_low_watermark = sc->free_rx_bd); 5409 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5410 sc->rx_empty_count++); 5411 5412 /* Simulate an mbuf allocation failure. */ 5413 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5414 sc->mbuf_alloc_failed_count++; 5415 sc->mbuf_alloc_failed_sim_count++; 5416 rc = ENOBUFS; 5417 goto bce_get_rx_buf_exit); 5418 5419 /* This is a new mbuf allocation. */ 5420 if (bce_hdr_split == TRUE) 5421 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5422 else 5423 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5424 sc->rx_bd_mbuf_alloc_size); 5425 5426 if (m_new == NULL) { 5427 sc->mbuf_alloc_failed_count++; 5428 rc = ENOBUFS; 5429 goto bce_get_rx_buf_exit; 5430 } 5431 5432 DBRUN(sc->debug_rx_mbuf_alloc++); 5433 5434 /* Make sure we have a valid packet header. */ 5435 M_ASSERTPKTHDR(m_new); 5436 5437 /* Initialize the mbuf size and pad if necessary for alignment. */ 5438 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5439 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5440 5441 /* ToDo: Consider calling m_fragment() to test error handling. */ 5442 5443 /* Map the mbuf cluster into device memory. */ 5444 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5445 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5446 5447 /* Handle any mapping errors. */ 5448 if (error) { 5449 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5450 "chain (%d)!\n", __FILE__, __LINE__, error); 5451 5452 sc->dma_map_addr_rx_failed_count++; 5453 m_freem(m_new); 5454 5455 DBRUN(sc->debug_rx_mbuf_alloc--); 5456 5457 rc = ENOBUFS; 5458 goto bce_get_rx_buf_exit; 5459 } 5460 5461 /* All mbufs must map to a single segment. */ 5462 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5463 __FUNCTION__, nsegs)); 5464 5465 /* Setup the rx_bd for the segment. */ 5466 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5467 5468 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5469 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5470 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5471 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5472 *prod_bseq += segs[0].ds_len; 5473 5474 /* Save the mbuf and update our counter. */ 5475 sc->rx_mbuf_ptr[chain_prod] = m_new; 5476 sc->free_rx_bd -= nsegs; 5477 5478 DBRUNMSG(BCE_INSANE_RECV, 5479 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5480 5481 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5482 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5483 chain_prod, *prod_bseq); 5484 5485 bce_get_rx_buf_exit: 5486 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5487 5488 return(rc); 5489 } 5490 5491 5492 /****************************************************************************/ 5493 /* Encapsulate an mbuf cluster into the page chain. */ 5494 /* */ 5495 /* Returns: */ 5496 /* 0 for success, positive value for failure. */ 5497 /****************************************************************************/ 5498 static int 5499 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5500 { 5501 bus_dma_segment_t segs[1]; 5502 struct mbuf *m_new = NULL; 5503 struct rx_bd *pgbd; 5504 int error, nsegs, rc = 0; 5505 #ifdef BCE_DEBUG 5506 u16 debug_prod_idx = prod_idx; 5507 #endif 5508 5509 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5510 5511 /* Make sure the inputs are valid. */ 5512 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5513 BCE_PRINTF("%s(%d): page producer out of range: " 5514 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5515 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5516 5517 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5518 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5519 5520 /* Update counters if we've hit a new low or run out of pages. */ 5521 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5522 sc->pg_low_watermark = sc->free_pg_bd); 5523 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5524 5525 /* Simulate an mbuf allocation failure. */ 5526 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5527 sc->mbuf_alloc_failed_count++; 5528 sc->mbuf_alloc_failed_sim_count++; 5529 rc = ENOBUFS; 5530 goto bce_get_pg_buf_exit); 5531 5532 /* This is a new mbuf allocation. */ 5533 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5534 if (m_new == NULL) { 5535 sc->mbuf_alloc_failed_count++; 5536 rc = ENOBUFS; 5537 goto bce_get_pg_buf_exit; 5538 } 5539 5540 DBRUN(sc->debug_pg_mbuf_alloc++); 5541 5542 m_new->m_len = MCLBYTES; 5543 5544 /* ToDo: Consider calling m_fragment() to test error handling. */ 5545 5546 /* Map the mbuf cluster into device memory. */ 5547 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5548 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5549 5550 /* Handle any mapping errors. */ 5551 if (error) { 5552 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5553 __FILE__, __LINE__); 5554 5555 m_freem(m_new); 5556 DBRUN(sc->debug_pg_mbuf_alloc--); 5557 5558 rc = ENOBUFS; 5559 goto bce_get_pg_buf_exit; 5560 } 5561 5562 /* All mbufs must map to a single segment. */ 5563 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5564 __FUNCTION__, nsegs)); 5565 5566 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5567 5568 /* 5569 * The page chain uses the same rx_bd data structure 5570 * as the receive chain but doesn't require a byte sequence (bseq). 5571 */ 5572 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5573 5574 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5575 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5576 pgbd->rx_bd_len = htole32(MCLBYTES); 5577 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5578 5579 /* Save the mbuf and update our counter. */ 5580 sc->pg_mbuf_ptr[prod_idx] = m_new; 5581 sc->free_pg_bd--; 5582 5583 DBRUNMSG(BCE_INSANE_RECV, 5584 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5585 5586 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5587 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5588 5589 bce_get_pg_buf_exit: 5590 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5591 5592 return(rc); 5593 } 5594 5595 5596 /****************************************************************************/ 5597 /* Initialize the TX context memory. */ 5598 /* */ 5599 /* Returns: */ 5600 /* Nothing */ 5601 /****************************************************************************/ 5602 static void 5603 bce_init_tx_context(struct bce_softc *sc) 5604 { 5605 u32 val; 5606 5607 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5608 5609 /* Initialize the context ID for an L2 TX chain. */ 5610 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5611 /* Set the CID type to support an L2 connection. */ 5612 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5613 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5614 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5615 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5616 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5617 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5618 5619 /* Point the hardware to the first page in the chain. */ 5620 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5621 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5622 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5623 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5624 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5625 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5626 } else { 5627 /* Set the CID type to support an L2 connection. */ 5628 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5629 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5630 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5631 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5632 5633 /* Point the hardware to the first page in the chain. */ 5634 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5635 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5636 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5637 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5638 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5639 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5640 } 5641 5642 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5643 } 5644 5645 5646 /****************************************************************************/ 5647 /* Allocate memory and initialize the TX data structures. */ 5648 /* */ 5649 /* Returns: */ 5650 /* 0 for success, positive value for failure. */ 5651 /****************************************************************************/ 5652 static int 5653 bce_init_tx_chain(struct bce_softc *sc) 5654 { 5655 struct tx_bd *txbd; 5656 int i, rc = 0; 5657 5658 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5659 5660 /* Set the initial TX producer/consumer indices. */ 5661 sc->tx_prod = 0; 5662 sc->tx_cons = 0; 5663 sc->tx_prod_bseq = 0; 5664 sc->used_tx_bd = 0; 5665 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5666 DBRUN(sc->tx_hi_watermark = 0); 5667 DBRUN(sc->tx_full_count = 0); 5668 5669 /* 5670 * The NetXtreme II supports a linked-list structre called 5671 * a Buffer Descriptor Chain (or BD chain). A BD chain 5672 * consists of a series of 1 or more chain pages, each of which 5673 * consists of a fixed number of BD entries. 5674 * The last BD entry on each page is a pointer to the next page 5675 * in the chain, and the last pointer in the BD chain 5676 * points back to the beginning of the chain. 5677 */ 5678 5679 /* Set the TX next pointer chain entries. */ 5680 for (i = 0; i < sc->tx_pages; i++) { 5681 int j; 5682 5683 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5684 5685 /* Check if we've reached the last page. */ 5686 if (i == (sc->tx_pages - 1)) 5687 j = 0; 5688 else 5689 j = i + 1; 5690 5691 txbd->tx_bd_haddr_hi = 5692 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5693 txbd->tx_bd_haddr_lo = 5694 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5695 } 5696 5697 bce_init_tx_context(sc); 5698 5699 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5700 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5701 5702 return(rc); 5703 } 5704 5705 5706 /****************************************************************************/ 5707 /* Free memory and clear the TX data structures. */ 5708 /* */ 5709 /* Returns: */ 5710 /* Nothing. */ 5711 /****************************************************************************/ 5712 static void 5713 bce_free_tx_chain(struct bce_softc *sc) 5714 { 5715 int i; 5716 5717 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5718 5719 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5720 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5721 if (sc->tx_mbuf_ptr[i] != NULL) { 5722 if (sc->tx_mbuf_map[i] != NULL) 5723 bus_dmamap_sync(sc->tx_mbuf_tag, 5724 sc->tx_mbuf_map[i], 5725 BUS_DMASYNC_POSTWRITE); 5726 m_freem(sc->tx_mbuf_ptr[i]); 5727 sc->tx_mbuf_ptr[i] = NULL; 5728 DBRUN(sc->debug_tx_mbuf_alloc--); 5729 } 5730 } 5731 5732 /* Clear each TX chain page. */ 5733 for (i = 0; i < sc->tx_pages; i++) 5734 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5735 5736 sc->used_tx_bd = 0; 5737 5738 /* Check if we lost any mbufs in the process. */ 5739 DBRUNIF((sc->debug_tx_mbuf_alloc), 5740 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5741 "from tx chain!\n", __FILE__, __LINE__, 5742 sc->debug_tx_mbuf_alloc)); 5743 5744 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5745 } 5746 5747 5748 /****************************************************************************/ 5749 /* Initialize the RX context memory. */ 5750 /* */ 5751 /* Returns: */ 5752 /* Nothing */ 5753 /****************************************************************************/ 5754 static void 5755 bce_init_rx_context(struct bce_softc *sc) 5756 { 5757 u32 val; 5758 5759 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5760 5761 /* Init the type, size, and BD cache levels for the RX context. */ 5762 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5763 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5764 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5765 5766 /* 5767 * Set the level for generating pause frames 5768 * when the number of available rx_bd's gets 5769 * too low (the low watermark) and the level 5770 * when pause frames can be stopped (the high 5771 * watermark). 5772 */ 5773 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5774 u32 lo_water, hi_water; 5775 5776 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5777 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5778 } else { 5779 lo_water = 0; 5780 } 5781 5782 if (lo_water >= USABLE_RX_BD_ALLOC) { 5783 lo_water = 0; 5784 } 5785 5786 hi_water = USABLE_RX_BD_ALLOC / 4; 5787 5788 if (hi_water <= lo_water) { 5789 lo_water = 0; 5790 } 5791 5792 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5793 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5794 5795 if (hi_water > 0xf) 5796 hi_water = 0xf; 5797 else if (hi_water == 0) 5798 lo_water = 0; 5799 5800 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5801 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5802 } 5803 5804 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5805 5806 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5807 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5808 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5809 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5810 } 5811 5812 /* Point the hardware to the first page in the chain. */ 5813 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5814 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5815 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5816 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5817 5818 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5819 } 5820 5821 5822 /****************************************************************************/ 5823 /* Allocate memory and initialize the RX data structures. */ 5824 /* */ 5825 /* Returns: */ 5826 /* 0 for success, positive value for failure. */ 5827 /****************************************************************************/ 5828 static int 5829 bce_init_rx_chain(struct bce_softc *sc) 5830 { 5831 struct rx_bd *rxbd; 5832 int i, rc = 0; 5833 5834 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5835 BCE_VERBOSE_CTX); 5836 5837 /* Initialize the RX producer and consumer indices. */ 5838 sc->rx_prod = 0; 5839 sc->rx_cons = 0; 5840 sc->rx_prod_bseq = 0; 5841 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5842 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5843 5844 /* Initialize the RX next pointer chain entries. */ 5845 for (i = 0; i < sc->rx_pages; i++) { 5846 int j; 5847 5848 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5849 5850 /* Check if we've reached the last page. */ 5851 if (i == (sc->rx_pages - 1)) 5852 j = 0; 5853 else 5854 j = i + 1; 5855 5856 /* Setup the chain page pointers. */ 5857 rxbd->rx_bd_haddr_hi = 5858 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5859 rxbd->rx_bd_haddr_lo = 5860 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5861 } 5862 5863 /* Fill up the RX chain. */ 5864 bce_fill_rx_chain(sc); 5865 5866 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5867 DBRUN(sc->rx_empty_count = 0); 5868 for (i = 0; i < sc->rx_pages; i++) { 5869 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5871 } 5872 5873 bce_init_rx_context(sc); 5874 5875 DBRUNMSG(BCE_EXTREME_RECV, 5876 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5877 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5878 BCE_VERBOSE_CTX); 5879 5880 /* ToDo: Are there possible failure modes here? */ 5881 5882 return(rc); 5883 } 5884 5885 5886 /****************************************************************************/ 5887 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5888 /* occurs. */ 5889 /* */ 5890 /* Returns: */ 5891 /* Nothing */ 5892 /****************************************************************************/ 5893 static void 5894 bce_fill_rx_chain(struct bce_softc *sc) 5895 { 5896 u16 prod, prod_idx; 5897 u32 prod_bseq; 5898 5899 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5900 BCE_VERBOSE_CTX); 5901 5902 /* Get the RX chain producer indices. */ 5903 prod = sc->rx_prod; 5904 prod_bseq = sc->rx_prod_bseq; 5905 5906 /* Keep filling the RX chain until it's full. */ 5907 while (sc->free_rx_bd > 0) { 5908 prod_idx = RX_CHAIN_IDX(prod); 5909 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5910 /* Bail out if we can't add an mbuf to the chain. */ 5911 break; 5912 } 5913 prod = NEXT_RX_BD(prod); 5914 } 5915 5916 /* Save the RX chain producer indices. */ 5917 sc->rx_prod = prod; 5918 sc->rx_prod_bseq = prod_bseq; 5919 5920 /* We should never end up pointing to a next page pointer. */ 5921 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5922 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5923 __FUNCTION__, rx_prod)); 5924 5925 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5926 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5927 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5928 5929 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5930 BCE_VERBOSE_CTX); 5931 } 5932 5933 5934 /****************************************************************************/ 5935 /* Free memory and clear the RX data structures. */ 5936 /* */ 5937 /* Returns: */ 5938 /* Nothing. */ 5939 /****************************************************************************/ 5940 static void 5941 bce_free_rx_chain(struct bce_softc *sc) 5942 { 5943 int i; 5944 5945 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5946 5947 /* Free any mbufs still in the RX mbuf chain. */ 5948 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5949 if (sc->rx_mbuf_ptr[i] != NULL) { 5950 if (sc->rx_mbuf_map[i] != NULL) 5951 bus_dmamap_sync(sc->rx_mbuf_tag, 5952 sc->rx_mbuf_map[i], 5953 BUS_DMASYNC_POSTREAD); 5954 m_freem(sc->rx_mbuf_ptr[i]); 5955 sc->rx_mbuf_ptr[i] = NULL; 5956 DBRUN(sc->debug_rx_mbuf_alloc--); 5957 } 5958 } 5959 5960 /* Clear each RX chain page. */ 5961 for (i = 0; i < sc->rx_pages; i++) 5962 if (sc->rx_bd_chain[i] != NULL) 5963 bzero((char *)sc->rx_bd_chain[i], 5964 BCE_RX_CHAIN_PAGE_SZ); 5965 5966 sc->free_rx_bd = sc->max_rx_bd; 5967 5968 /* Check if we lost any mbufs in the process. */ 5969 DBRUNIF((sc->debug_rx_mbuf_alloc), 5970 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5971 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5972 5973 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5974 } 5975 5976 5977 /****************************************************************************/ 5978 /* Allocate memory and initialize the page data structures. */ 5979 /* Assumes that bce_init_rx_chain() has not already been called. */ 5980 /* */ 5981 /* Returns: */ 5982 /* 0 for success, positive value for failure. */ 5983 /****************************************************************************/ 5984 static int 5985 bce_init_pg_chain(struct bce_softc *sc) 5986 { 5987 struct rx_bd *pgbd; 5988 int i, rc = 0; 5989 u32 val; 5990 5991 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5992 BCE_VERBOSE_CTX); 5993 5994 /* Initialize the page producer and consumer indices. */ 5995 sc->pg_prod = 0; 5996 sc->pg_cons = 0; 5997 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5998 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5999 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 6000 DBRUN(sc->pg_empty_count = 0); 6001 6002 /* Initialize the page next pointer chain entries. */ 6003 for (i = 0; i < sc->pg_pages; i++) { 6004 int j; 6005 6006 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 6007 6008 /* Check if we've reached the last page. */ 6009 if (i == (sc->pg_pages - 1)) 6010 j = 0; 6011 else 6012 j = i + 1; 6013 6014 /* Setup the chain page pointers. */ 6015 pgbd->rx_bd_haddr_hi = 6016 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 6017 pgbd->rx_bd_haddr_lo = 6018 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 6019 } 6020 6021 /* Setup the MQ BIN mapping for host_pg_bidx. */ 6022 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 6023 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 6024 6025 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 6026 6027 /* Configure the rx_bd and page chain mbuf cluster size. */ 6028 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 6029 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6030 6031 /* Configure the context reserved for jumbo support. */ 6032 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6033 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6034 6035 /* Point the hardware to the first page in the page chain. */ 6036 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6037 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6038 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6039 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6040 6041 /* Fill up the page chain. */ 6042 bce_fill_pg_chain(sc); 6043 6044 for (i = 0; i < sc->pg_pages; i++) { 6045 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6047 } 6048 6049 DBRUNMSG(BCE_EXTREME_RECV, 6050 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6051 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6052 BCE_VERBOSE_CTX); 6053 return(rc); 6054 } 6055 6056 6057 /****************************************************************************/ 6058 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6059 /* occurs. */ 6060 /* */ 6061 /* Returns: */ 6062 /* Nothing */ 6063 /****************************************************************************/ 6064 static void 6065 bce_fill_pg_chain(struct bce_softc *sc) 6066 { 6067 u16 prod, prod_idx; 6068 6069 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6070 BCE_VERBOSE_CTX); 6071 6072 /* Get the page chain prodcuer index. */ 6073 prod = sc->pg_prod; 6074 6075 /* Keep filling the page chain until it's full. */ 6076 while (sc->free_pg_bd > 0) { 6077 prod_idx = PG_CHAIN_IDX(prod); 6078 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6079 /* Bail out if we can't add an mbuf to the chain. */ 6080 break; 6081 } 6082 prod = NEXT_PG_BD(prod); 6083 } 6084 6085 /* Save the page chain producer index. */ 6086 sc->pg_prod = prod; 6087 6088 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6089 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6090 __FUNCTION__, pg_prod)); 6091 6092 /* 6093 * Write the mailbox and tell the chip about 6094 * the new rx_bd's in the page chain. 6095 */ 6096 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6097 prod); 6098 6099 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6100 BCE_VERBOSE_CTX); 6101 } 6102 6103 6104 /****************************************************************************/ 6105 /* Free memory and clear the RX data structures. */ 6106 /* */ 6107 /* Returns: */ 6108 /* Nothing. */ 6109 /****************************************************************************/ 6110 static void 6111 bce_free_pg_chain(struct bce_softc *sc) 6112 { 6113 int i; 6114 6115 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6116 6117 /* Free any mbufs still in the mbuf page chain. */ 6118 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6119 if (sc->pg_mbuf_ptr[i] != NULL) { 6120 if (sc->pg_mbuf_map[i] != NULL) 6121 bus_dmamap_sync(sc->pg_mbuf_tag, 6122 sc->pg_mbuf_map[i], 6123 BUS_DMASYNC_POSTREAD); 6124 m_freem(sc->pg_mbuf_ptr[i]); 6125 sc->pg_mbuf_ptr[i] = NULL; 6126 DBRUN(sc->debug_pg_mbuf_alloc--); 6127 } 6128 } 6129 6130 /* Clear each page chain pages. */ 6131 for (i = 0; i < sc->pg_pages; i++) 6132 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6133 6134 sc->free_pg_bd = sc->max_pg_bd; 6135 6136 /* Check if we lost any mbufs in the process. */ 6137 DBRUNIF((sc->debug_pg_mbuf_alloc), 6138 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6139 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6140 6141 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6142 } 6143 6144 6145 static u32 6146 bce_get_rphy_link(struct bce_softc *sc) 6147 { 6148 u32 advertise, link; 6149 int fdpx; 6150 6151 advertise = 0; 6152 fdpx = 0; 6153 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6154 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6155 else 6156 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6157 if (link & BCE_NETLINK_ANEG_ENB) 6158 advertise |= BCE_NETLINK_ANEG_ENB; 6159 if (link & BCE_NETLINK_SPEED_10HALF) 6160 advertise |= BCE_NETLINK_SPEED_10HALF; 6161 if (link & BCE_NETLINK_SPEED_10FULL) { 6162 advertise |= BCE_NETLINK_SPEED_10FULL; 6163 fdpx++; 6164 } 6165 if (link & BCE_NETLINK_SPEED_100HALF) 6166 advertise |= BCE_NETLINK_SPEED_100HALF; 6167 if (link & BCE_NETLINK_SPEED_100FULL) { 6168 advertise |= BCE_NETLINK_SPEED_100FULL; 6169 fdpx++; 6170 } 6171 if (link & BCE_NETLINK_SPEED_1000HALF) 6172 advertise |= BCE_NETLINK_SPEED_1000HALF; 6173 if (link & BCE_NETLINK_SPEED_1000FULL) { 6174 advertise |= BCE_NETLINK_SPEED_1000FULL; 6175 fdpx++; 6176 } 6177 if (link & BCE_NETLINK_SPEED_2500HALF) 6178 advertise |= BCE_NETLINK_SPEED_2500HALF; 6179 if (link & BCE_NETLINK_SPEED_2500FULL) { 6180 advertise |= BCE_NETLINK_SPEED_2500FULL; 6181 fdpx++; 6182 } 6183 if (fdpx) 6184 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6185 BCE_NETLINK_FC_PAUSE_ASYM; 6186 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6187 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6188 BCE_NETLINK_ETH_AT_WIRESPEED; 6189 6190 return (advertise); 6191 } 6192 6193 6194 /****************************************************************************/ 6195 /* Set media options. */ 6196 /* */ 6197 /* Returns: */ 6198 /* 0 for success, positive value for failure. */ 6199 /****************************************************************************/ 6200 static int 6201 bce_ifmedia_upd(struct ifnet *ifp) 6202 { 6203 struct bce_softc *sc = ifp->if_softc; 6204 int error; 6205 6206 DBENTER(BCE_VERBOSE); 6207 6208 BCE_LOCK(sc); 6209 error = bce_ifmedia_upd_locked(ifp); 6210 BCE_UNLOCK(sc); 6211 6212 DBEXIT(BCE_VERBOSE); 6213 return (error); 6214 } 6215 6216 6217 /****************************************************************************/ 6218 /* Set media options. */ 6219 /* */ 6220 /* Returns: */ 6221 /* Nothing. */ 6222 /****************************************************************************/ 6223 static int 6224 bce_ifmedia_upd_locked(struct ifnet *ifp) 6225 { 6226 struct bce_softc *sc = ifp->if_softc; 6227 struct mii_data *mii; 6228 struct mii_softc *miisc; 6229 struct ifmedia *ifm; 6230 u32 link; 6231 int error, fdx; 6232 6233 DBENTER(BCE_VERBOSE_PHY); 6234 6235 error = 0; 6236 BCE_LOCK_ASSERT(sc); 6237 6238 sc->bce_link_up = FALSE; 6239 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6240 ifm = &sc->bce_ifmedia; 6241 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6242 return (EINVAL); 6243 link = 0; 6244 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6245 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6246 case IFM_AUTO: 6247 /* 6248 * Check advertised link of remote PHY by reading 6249 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6250 * Always use the same link type of remote PHY. 6251 */ 6252 link = bce_get_rphy_link(sc); 6253 break; 6254 case IFM_2500_SX: 6255 if ((sc->bce_phy_flags & 6256 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6257 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6258 return (EINVAL); 6259 /* 6260 * XXX 6261 * Have to enable forced 2.5Gbps configuration. 6262 */ 6263 if (fdx != 0) 6264 link |= BCE_NETLINK_SPEED_2500FULL; 6265 else 6266 link |= BCE_NETLINK_SPEED_2500HALF; 6267 break; 6268 case IFM_1000_SX: 6269 if ((sc->bce_phy_flags & 6270 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6271 return (EINVAL); 6272 /* 6273 * XXX 6274 * Have to disable 2.5Gbps configuration. 6275 */ 6276 if (fdx != 0) 6277 link = BCE_NETLINK_SPEED_1000FULL; 6278 else 6279 link = BCE_NETLINK_SPEED_1000HALF; 6280 break; 6281 case IFM_1000_T: 6282 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6283 return (EINVAL); 6284 if (fdx != 0) 6285 link = BCE_NETLINK_SPEED_1000FULL; 6286 else 6287 link = BCE_NETLINK_SPEED_1000HALF; 6288 break; 6289 case IFM_100_TX: 6290 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6291 return (EINVAL); 6292 if (fdx != 0) 6293 link = BCE_NETLINK_SPEED_100FULL; 6294 else 6295 link = BCE_NETLINK_SPEED_100HALF; 6296 break; 6297 case IFM_10_T: 6298 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6299 return (EINVAL); 6300 if (fdx != 0) 6301 link = BCE_NETLINK_SPEED_10FULL; 6302 else 6303 link = BCE_NETLINK_SPEED_10HALF; 6304 break; 6305 default: 6306 return (EINVAL); 6307 } 6308 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6309 /* 6310 * XXX 6311 * Advertise pause capability for full-duplex media. 6312 */ 6313 if (fdx != 0) 6314 link |= BCE_NETLINK_FC_PAUSE_SYM | 6315 BCE_NETLINK_FC_PAUSE_ASYM; 6316 if ((sc->bce_phy_flags & 6317 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6318 link |= BCE_NETLINK_PHY_APP_REMOTE | 6319 BCE_NETLINK_ETH_AT_WIRESPEED; 6320 } 6321 6322 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6323 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6324 } else { 6325 mii = device_get_softc(sc->bce_miibus); 6326 6327 /* Make sure the MII bus has been enumerated. */ 6328 if (mii) { 6329 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6330 PHY_RESET(miisc); 6331 error = mii_mediachg(mii); 6332 } 6333 } 6334 6335 DBEXIT(BCE_VERBOSE_PHY); 6336 return (error); 6337 } 6338 6339 6340 static void 6341 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6342 { 6343 struct ifnet *ifp; 6344 u32 link; 6345 6346 ifp = sc->bce_ifp; 6347 BCE_LOCK_ASSERT(sc); 6348 6349 ifmr->ifm_status = IFM_AVALID; 6350 ifmr->ifm_active = IFM_ETHER; 6351 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6352 /* XXX Handle heart beat status? */ 6353 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6354 ifmr->ifm_status |= IFM_ACTIVE; 6355 else { 6356 ifmr->ifm_active |= IFM_NONE; 6357 ifp->if_baudrate = 0; 6358 return; 6359 } 6360 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6361 case BCE_LINK_STATUS_10HALF: 6362 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6363 ifp->if_baudrate = IF_Mbps(10UL); 6364 break; 6365 case BCE_LINK_STATUS_10FULL: 6366 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6367 ifp->if_baudrate = IF_Mbps(10UL); 6368 break; 6369 case BCE_LINK_STATUS_100HALF: 6370 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6371 ifp->if_baudrate = IF_Mbps(100UL); 6372 break; 6373 case BCE_LINK_STATUS_100FULL: 6374 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6375 ifp->if_baudrate = IF_Mbps(100UL); 6376 break; 6377 case BCE_LINK_STATUS_1000HALF: 6378 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6379 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6380 else 6381 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6382 ifp->if_baudrate = IF_Mbps(1000UL); 6383 break; 6384 case BCE_LINK_STATUS_1000FULL: 6385 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6386 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6387 else 6388 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6389 ifp->if_baudrate = IF_Mbps(1000UL); 6390 break; 6391 case BCE_LINK_STATUS_2500HALF: 6392 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6393 ifmr->ifm_active |= IFM_NONE; 6394 return; 6395 } else 6396 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6397 ifp->if_baudrate = IF_Mbps(2500UL); 6398 break; 6399 case BCE_LINK_STATUS_2500FULL: 6400 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6401 ifmr->ifm_active |= IFM_NONE; 6402 return; 6403 } else 6404 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6405 ifp->if_baudrate = IF_Mbps(2500UL); 6406 break; 6407 default: 6408 ifmr->ifm_active |= IFM_NONE; 6409 return; 6410 } 6411 6412 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6413 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6414 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6415 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6416 } 6417 6418 6419 /****************************************************************************/ 6420 /* Reports current media status. */ 6421 /* */ 6422 /* Returns: */ 6423 /* Nothing. */ 6424 /****************************************************************************/ 6425 static void 6426 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6427 { 6428 struct bce_softc *sc = ifp->if_softc; 6429 struct mii_data *mii; 6430 6431 DBENTER(BCE_VERBOSE_PHY); 6432 6433 BCE_LOCK(sc); 6434 6435 if ((ifp->if_flags & IFF_UP) == 0) { 6436 BCE_UNLOCK(sc); 6437 return; 6438 } 6439 6440 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6441 bce_ifmedia_sts_rphy(sc, ifmr); 6442 else { 6443 mii = device_get_softc(sc->bce_miibus); 6444 mii_pollstat(mii); 6445 ifmr->ifm_active = mii->mii_media_active; 6446 ifmr->ifm_status = mii->mii_media_status; 6447 } 6448 6449 BCE_UNLOCK(sc); 6450 6451 DBEXIT(BCE_VERBOSE_PHY); 6452 } 6453 6454 6455 /****************************************************************************/ 6456 /* Handles PHY generated interrupt events. */ 6457 /* */ 6458 /* Returns: */ 6459 /* Nothing. */ 6460 /****************************************************************************/ 6461 static void 6462 bce_phy_intr(struct bce_softc *sc) 6463 { 6464 u32 new_link_state, old_link_state; 6465 6466 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6467 6468 DBRUN(sc->phy_interrupts++); 6469 6470 new_link_state = sc->status_block->status_attn_bits & 6471 STATUS_ATTN_BITS_LINK_STATE; 6472 old_link_state = sc->status_block->status_attn_bits_ack & 6473 STATUS_ATTN_BITS_LINK_STATE; 6474 6475 /* Handle any changes if the link state has changed. */ 6476 if (new_link_state != old_link_state) { 6477 6478 /* Update the status_attn_bits_ack field. */ 6479 if (new_link_state) { 6480 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6481 STATUS_ATTN_BITS_LINK_STATE); 6482 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6483 __FUNCTION__); 6484 } else { 6485 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6486 STATUS_ATTN_BITS_LINK_STATE); 6487 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6488 __FUNCTION__); 6489 } 6490 6491 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6492 if (new_link_state) { 6493 if (bootverbose) 6494 if_printf(sc->bce_ifp, "link UP\n"); 6495 if_link_state_change(sc->bce_ifp, 6496 LINK_STATE_UP); 6497 } else { 6498 if (bootverbose) 6499 if_printf(sc->bce_ifp, "link DOWN\n"); 6500 if_link_state_change(sc->bce_ifp, 6501 LINK_STATE_DOWN); 6502 } 6503 } 6504 /* 6505 * Assume link is down and allow 6506 * tick routine to update the state 6507 * based on the actual media state. 6508 */ 6509 sc->bce_link_up = FALSE; 6510 callout_stop(&sc->bce_tick_callout); 6511 bce_tick(sc); 6512 } 6513 6514 /* Acknowledge the link change interrupt. */ 6515 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6516 6517 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6518 } 6519 6520 6521 /****************************************************************************/ 6522 /* Reads the receive consumer value from the status block (skipping over */ 6523 /* chain page pointer if necessary). */ 6524 /* */ 6525 /* Returns: */ 6526 /* hw_cons */ 6527 /****************************************************************************/ 6528 static inline u16 6529 bce_get_hw_rx_cons(struct bce_softc *sc) 6530 { 6531 u16 hw_cons; 6532 6533 rmb(); 6534 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6535 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6536 hw_cons++; 6537 6538 return hw_cons; 6539 } 6540 6541 /****************************************************************************/ 6542 /* Handles received frame interrupt events. */ 6543 /* */ 6544 /* Returns: */ 6545 /* Nothing. */ 6546 /****************************************************************************/ 6547 static void 6548 bce_rx_intr(struct bce_softc *sc) 6549 { 6550 struct ifnet *ifp = sc->bce_ifp; 6551 struct l2_fhdr *l2fhdr; 6552 struct ether_vlan_header *vh; 6553 unsigned int pkt_len; 6554 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6555 u32 status; 6556 unsigned int rem_len; 6557 u16 sw_pg_cons, sw_pg_cons_idx; 6558 6559 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6560 DBRUN(sc->interrupts_rx++); 6561 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6562 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6563 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6564 6565 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6566 for (int i = 0; i < sc->rx_pages; i++) 6567 bus_dmamap_sync(sc->rx_bd_chain_tag, 6568 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6569 6570 /* Prepare the page chain pages to be accessed by the host CPU. */ 6571 if (bce_hdr_split == TRUE) { 6572 for (int i = 0; i < sc->pg_pages; i++) 6573 bus_dmamap_sync(sc->pg_bd_chain_tag, 6574 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6575 } 6576 6577 /* Get the hardware's view of the RX consumer index. */ 6578 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6579 6580 /* Get working copies of the driver's view of the consumer indices. */ 6581 sw_rx_cons = sc->rx_cons; 6582 sw_pg_cons = sc->pg_cons; 6583 6584 /* Update some debug statistics counters */ 6585 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6586 sc->rx_low_watermark = sc->free_rx_bd); 6587 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6588 sc->rx_empty_count++); 6589 6590 /* Scan through the receive chain as long as there is work to do */ 6591 /* ToDo: Consider setting a limit on the number of packets processed. */ 6592 rmb(); 6593 while (sw_rx_cons != hw_rx_cons) { 6594 struct mbuf *m0; 6595 6596 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6597 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6598 6599 /* Unmap the mbuf from DMA space. */ 6600 bus_dmamap_sync(sc->rx_mbuf_tag, 6601 sc->rx_mbuf_map[sw_rx_cons_idx], 6602 BUS_DMASYNC_POSTREAD); 6603 bus_dmamap_unload(sc->rx_mbuf_tag, 6604 sc->rx_mbuf_map[sw_rx_cons_idx]); 6605 6606 /* Remove the mbuf from the RX chain. */ 6607 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6608 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6609 DBRUN(sc->debug_rx_mbuf_alloc--); 6610 sc->free_rx_bd++; 6611 6612 /* 6613 * Frames received on the NetXteme II are prepended 6614 * with an l2_fhdr structure which provides status 6615 * information about the received frame (including 6616 * VLAN tags and checksum info). The frames are 6617 * also automatically adjusted to word align the IP 6618 * header (i.e. two null bytes are inserted before 6619 * the Ethernet header). As a result the data 6620 * DMA'd by the controller into the mbuf looks 6621 * like this: 6622 * 6623 * +---------+-----+---------------------+-----+ 6624 * | l2_fhdr | pad | packet data | FCS | 6625 * +---------+-----+---------------------+-----+ 6626 * 6627 * The l2_fhdr needs to be checked and skipped and 6628 * the FCS needs to be stripped before sending the 6629 * packet up the stack. 6630 */ 6631 l2fhdr = mtod(m0, struct l2_fhdr *); 6632 6633 /* Get the packet data + FCS length and the status. */ 6634 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6635 status = l2fhdr->l2_fhdr_status; 6636 6637 /* 6638 * Skip over the l2_fhdr and pad, resulting in the 6639 * following data in the mbuf: 6640 * +---------------------+-----+ 6641 * | packet data | FCS | 6642 * +---------------------+-----+ 6643 */ 6644 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6645 6646 /* 6647 * When split header mode is used, an ethernet frame 6648 * may be split across the receive chain and the 6649 * page chain. If that occurs an mbuf cluster must be 6650 * reassembled from the individual mbuf pieces. 6651 */ 6652 if (bce_hdr_split == TRUE) { 6653 /* 6654 * Check whether the received frame fits in a single 6655 * mbuf or not (i.e. packet data + FCS <= 6656 * sc->rx_bd_mbuf_data_len bytes). 6657 */ 6658 if (pkt_len > m0->m_len) { 6659 /* 6660 * The received frame is larger than a single mbuf. 6661 * If the frame was a TCP frame then only the TCP 6662 * header is placed in the mbuf, the remaining 6663 * payload (including FCS) is placed in the page 6664 * chain, the SPLIT flag is set, and the header 6665 * length is placed in the IP checksum field. 6666 * If the frame is not a TCP frame then the mbuf 6667 * is filled and the remaining bytes are placed 6668 * in the page chain. 6669 */ 6670 6671 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6672 "packet.\n", __FUNCTION__); 6673 DBRUN(sc->split_header_frames_rcvd++); 6674 6675 /* 6676 * When the page chain is enabled and the TCP 6677 * header has been split from the TCP payload, 6678 * the ip_xsum structure will reflect the length 6679 * of the TCP header, not the IP checksum. Set 6680 * the packet length of the mbuf accordingly. 6681 */ 6682 if (status & L2_FHDR_STATUS_SPLIT) { 6683 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6684 DBRUN(sc->split_header_tcp_frames_rcvd++); 6685 } 6686 6687 rem_len = pkt_len - m0->m_len; 6688 6689 /* Pull mbufs off the page chain for any remaining data. */ 6690 while (rem_len > 0) { 6691 struct mbuf *m_pg; 6692 6693 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6694 6695 /* Remove the mbuf from the page chain. */ 6696 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6697 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6698 DBRUN(sc->debug_pg_mbuf_alloc--); 6699 sc->free_pg_bd++; 6700 6701 /* Unmap the page chain mbuf from DMA space. */ 6702 bus_dmamap_sync(sc->pg_mbuf_tag, 6703 sc->pg_mbuf_map[sw_pg_cons_idx], 6704 BUS_DMASYNC_POSTREAD); 6705 bus_dmamap_unload(sc->pg_mbuf_tag, 6706 sc->pg_mbuf_map[sw_pg_cons_idx]); 6707 6708 /* Adjust the mbuf length. */ 6709 if (rem_len < m_pg->m_len) { 6710 /* The mbuf chain is complete. */ 6711 m_pg->m_len = rem_len; 6712 rem_len = 0; 6713 } else { 6714 /* More packet data is waiting. */ 6715 rem_len -= m_pg->m_len; 6716 } 6717 6718 /* Concatenate the mbuf cluster to the mbuf. */ 6719 m_cat(m0, m_pg); 6720 6721 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6722 } 6723 6724 /* Set the total packet length. */ 6725 m0->m_pkthdr.len = pkt_len; 6726 6727 } else { 6728 /* 6729 * The received packet is small and fits in a 6730 * single mbuf (i.e. the l2_fhdr + pad + packet + 6731 * FCS <= MHLEN). In other words, the packet is 6732 * 154 bytes or less in size. 6733 */ 6734 6735 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6736 "packet.\n", __FUNCTION__); 6737 6738 /* Set the total packet length. */ 6739 m0->m_pkthdr.len = m0->m_len = pkt_len; 6740 } 6741 } else 6742 /* Set the total packet length. */ 6743 m0->m_pkthdr.len = m0->m_len = pkt_len; 6744 6745 /* Remove the trailing Ethernet FCS. */ 6746 m_adj(m0, -ETHER_CRC_LEN); 6747 6748 /* Check that the resulting mbuf chain is valid. */ 6749 DBRUN(m_sanity(m0, FALSE)); 6750 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6751 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6752 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6753 m_print(m0, 128)); 6754 6755 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6756 sc->l2fhdr_error_sim_count++; 6757 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6758 6759 /* Check the received frame for errors. */ 6760 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6761 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6762 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6763 6764 /* Log the error and release the mbuf. */ 6765 ifp->if_ierrors++; 6766 sc->l2fhdr_error_count++; 6767 6768 m_freem(m0); 6769 m0 = NULL; 6770 goto bce_rx_intr_next_rx; 6771 } 6772 6773 /* Send the packet to the appropriate interface. */ 6774 m0->m_pkthdr.rcvif = ifp; 6775 6776 /* Assume no hardware checksum. */ 6777 m0->m_pkthdr.csum_flags = 0; 6778 6779 /* Validate the checksum if offload enabled. */ 6780 if (ifp->if_capenable & IFCAP_RXCSUM) { 6781 /* Check for an IP datagram. */ 6782 if (!(status & L2_FHDR_STATUS_SPLIT) && 6783 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6784 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6785 DBRUN(sc->csum_offload_ip++); 6786 /* Check if the IP checksum is valid. */ 6787 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6788 m0->m_pkthdr.csum_flags |= 6789 CSUM_IP_VALID; 6790 } 6791 6792 /* Check for a valid TCP/UDP frame. */ 6793 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6794 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6795 6796 /* Check for a good TCP/UDP checksum. */ 6797 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6798 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6799 DBRUN(sc->csum_offload_tcp_udp++); 6800 m0->m_pkthdr.csum_data = 6801 l2fhdr->l2_fhdr_tcp_udp_xsum; 6802 m0->m_pkthdr.csum_flags |= 6803 (CSUM_DATA_VALID 6804 | CSUM_PSEUDO_HDR); 6805 } 6806 } 6807 } 6808 6809 /* Attach the VLAN tag. */ 6810 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6811 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6812 DBRUN(sc->vlan_tagged_frames_rcvd++); 6813 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6814 DBRUN(sc->vlan_tagged_frames_stripped++); 6815 #if __FreeBSD_version < 700000 6816 VLAN_INPUT_TAG(ifp, m0, 6817 l2fhdr->l2_fhdr_vlan_tag, continue); 6818 #else 6819 m0->m_pkthdr.ether_vtag = 6820 l2fhdr->l2_fhdr_vlan_tag; 6821 m0->m_flags |= M_VLANTAG; 6822 #endif 6823 } else { 6824 /* 6825 * bce(4) controllers can't disable VLAN 6826 * tag stripping if management firmware 6827 * (ASF/IPMI/UMP) is running. So we always 6828 * strip VLAN tag and manually reconstruct 6829 * the VLAN frame by appending stripped 6830 * VLAN tag in driver if VLAN tag stripping 6831 * was disabled. 6832 * 6833 * TODO: LLC SNAP handling. 6834 */ 6835 bcopy(mtod(m0, uint8_t *), 6836 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6837 ETHER_ADDR_LEN * 2); 6838 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6839 vh = mtod(m0, struct ether_vlan_header *); 6840 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6841 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6842 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6843 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6844 } 6845 } 6846 6847 /* Increment received packet statistics. */ 6848 ifp->if_ipackets++; 6849 6850 bce_rx_intr_next_rx: 6851 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6852 6853 /* If we have a packet, pass it up the stack */ 6854 if (m0) { 6855 /* Make sure we don't lose our place when we release the lock. */ 6856 sc->rx_cons = sw_rx_cons; 6857 sc->pg_cons = sw_pg_cons; 6858 6859 BCE_UNLOCK(sc); 6860 (*ifp->if_input)(ifp, m0); 6861 BCE_LOCK(sc); 6862 6863 /* Recover our place. */ 6864 sw_rx_cons = sc->rx_cons; 6865 sw_pg_cons = sc->pg_cons; 6866 } 6867 6868 /* Refresh hw_cons to see if there's new work */ 6869 if (sw_rx_cons == hw_rx_cons) 6870 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6871 } 6872 6873 /* No new packets. Refill the page chain. */ 6874 if (bce_hdr_split == TRUE) { 6875 sc->pg_cons = sw_pg_cons; 6876 bce_fill_pg_chain(sc); 6877 } 6878 6879 /* No new packets. Refill the RX chain. */ 6880 sc->rx_cons = sw_rx_cons; 6881 bce_fill_rx_chain(sc); 6882 6883 /* Prepare the page chain pages to be accessed by the NIC. */ 6884 for (int i = 0; i < sc->rx_pages; i++) 6885 bus_dmamap_sync(sc->rx_bd_chain_tag, 6886 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6887 6888 if (bce_hdr_split == TRUE) { 6889 for (int i = 0; i < sc->pg_pages; i++) 6890 bus_dmamap_sync(sc->pg_bd_chain_tag, 6891 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6892 } 6893 6894 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6895 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6896 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6897 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6898 } 6899 6900 6901 /****************************************************************************/ 6902 /* Reads the transmit consumer value from the status block (skipping over */ 6903 /* chain page pointer if necessary). */ 6904 /* */ 6905 /* Returns: */ 6906 /* hw_cons */ 6907 /****************************************************************************/ 6908 static inline u16 6909 bce_get_hw_tx_cons(struct bce_softc *sc) 6910 { 6911 u16 hw_cons; 6912 6913 mb(); 6914 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6915 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6916 hw_cons++; 6917 6918 return hw_cons; 6919 } 6920 6921 6922 /****************************************************************************/ 6923 /* Handles transmit completion interrupt events. */ 6924 /* */ 6925 /* Returns: */ 6926 /* Nothing. */ 6927 /****************************************************************************/ 6928 static void 6929 bce_tx_intr(struct bce_softc *sc) 6930 { 6931 struct ifnet *ifp = sc->bce_ifp; 6932 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6933 6934 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6935 DBRUN(sc->interrupts_tx++); 6936 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6937 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6938 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6939 6940 BCE_LOCK_ASSERT(sc); 6941 6942 /* Get the hardware's view of the TX consumer index. */ 6943 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6944 sw_tx_cons = sc->tx_cons; 6945 6946 /* Prevent speculative reads of the status block. */ 6947 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6948 BUS_SPACE_BARRIER_READ); 6949 6950 /* Cycle through any completed TX chain page entries. */ 6951 while (sw_tx_cons != hw_tx_cons) { 6952 #ifdef BCE_DEBUG 6953 struct tx_bd *txbd = NULL; 6954 #endif 6955 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6956 6957 DBPRINT(sc, BCE_INFO_SEND, 6958 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6959 "sw_tx_chain_cons = 0x%04X\n", 6960 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6961 6962 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6963 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6964 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6965 (int) MAX_TX_BD_ALLOC); 6966 bce_breakpoint(sc)); 6967 6968 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6969 [TX_IDX(sw_tx_chain_cons)]); 6970 6971 DBRUNIF((txbd == NULL), 6972 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6973 __FILE__, __LINE__, sw_tx_chain_cons); 6974 bce_breakpoint(sc)); 6975 6976 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6977 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6978 6979 /* 6980 * Free the associated mbuf. Remember 6981 * that only the last tx_bd of a packet 6982 * has an mbuf pointer and DMA map. 6983 */ 6984 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6985 6986 /* Validate that this is the last tx_bd. */ 6987 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6988 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6989 "txmbuf == NULL!\n", __FILE__, __LINE__); 6990 bce_breakpoint(sc)); 6991 6992 DBRUNMSG(BCE_INFO_SEND, 6993 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6994 "from tx_bd[0x%04X]\n", __FUNCTION__, 6995 sw_tx_chain_cons)); 6996 6997 /* Unmap the mbuf. */ 6998 bus_dmamap_unload(sc->tx_mbuf_tag, 6999 sc->tx_mbuf_map[sw_tx_chain_cons]); 7000 7001 /* Free the mbuf. */ 7002 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 7003 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 7004 DBRUN(sc->debug_tx_mbuf_alloc--); 7005 7006 ifp->if_opackets++; 7007 } 7008 7009 sc->used_tx_bd--; 7010 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 7011 7012 /* Refresh hw_cons to see if there's new work. */ 7013 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 7014 7015 /* Prevent speculative reads of the status block. */ 7016 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7017 BUS_SPACE_BARRIER_READ); 7018 } 7019 7020 /* Clear the TX timeout timer. */ 7021 sc->watchdog_timer = 0; 7022 7023 /* Clear the tx hardware queue full flag. */ 7024 if (sc->used_tx_bd < sc->max_tx_bd) { 7025 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 7026 DBPRINT(sc, BCE_INFO_SEND, 7027 "%s(): Open TX chain! %d/%d (used/total)\n", 7028 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 7029 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7030 } 7031 7032 sc->tx_cons = sw_tx_cons; 7033 7034 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7035 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7036 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7037 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7038 } 7039 7040 7041 /****************************************************************************/ 7042 /* Disables interrupt generation. */ 7043 /* */ 7044 /* Returns: */ 7045 /* Nothing. */ 7046 /****************************************************************************/ 7047 static void 7048 bce_disable_intr(struct bce_softc *sc) 7049 { 7050 DBENTER(BCE_VERBOSE_INTR); 7051 7052 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7053 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7054 7055 DBEXIT(BCE_VERBOSE_INTR); 7056 } 7057 7058 7059 /****************************************************************************/ 7060 /* Enables interrupt generation. */ 7061 /* */ 7062 /* Returns: */ 7063 /* Nothing. */ 7064 /****************************************************************************/ 7065 static void 7066 bce_enable_intr(struct bce_softc *sc, int coal_now) 7067 { 7068 DBENTER(BCE_VERBOSE_INTR); 7069 7070 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7071 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7072 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7073 7074 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7075 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7076 7077 /* Force an immediate interrupt (whether there is new data or not). */ 7078 if (coal_now) 7079 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7080 7081 DBEXIT(BCE_VERBOSE_INTR); 7082 } 7083 7084 7085 /****************************************************************************/ 7086 /* Handles controller initialization. */ 7087 /* */ 7088 /* Returns: */ 7089 /* Nothing. */ 7090 /****************************************************************************/ 7091 static void 7092 bce_init_locked(struct bce_softc *sc) 7093 { 7094 struct ifnet *ifp; 7095 u32 ether_mtu = 0; 7096 7097 DBENTER(BCE_VERBOSE_RESET); 7098 7099 BCE_LOCK_ASSERT(sc); 7100 7101 ifp = sc->bce_ifp; 7102 7103 /* Check if the driver is still running and bail out if it is. */ 7104 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7105 goto bce_init_locked_exit; 7106 7107 bce_stop(sc); 7108 7109 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7110 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7111 __FILE__, __LINE__); 7112 goto bce_init_locked_exit; 7113 } 7114 7115 if (bce_chipinit(sc)) { 7116 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7117 __FILE__, __LINE__); 7118 goto bce_init_locked_exit; 7119 } 7120 7121 if (bce_blockinit(sc)) { 7122 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7123 __FILE__, __LINE__); 7124 goto bce_init_locked_exit; 7125 } 7126 7127 /* Load our MAC address. */ 7128 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7129 bce_set_mac_addr(sc); 7130 7131 if (bce_hdr_split == FALSE) 7132 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7133 /* 7134 * Calculate and program the hardware Ethernet MTU 7135 * size. Be generous on the receive if we have room 7136 * and allowed by the user. 7137 */ 7138 if (bce_strict_rx_mtu == TRUE) 7139 ether_mtu = ifp->if_mtu; 7140 else { 7141 if (bce_hdr_split == TRUE) { 7142 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7143 ether_mtu = sc->rx_bd_mbuf_data_len + 7144 MCLBYTES; 7145 else 7146 ether_mtu = ifp->if_mtu; 7147 } else { 7148 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7149 ether_mtu = sc->rx_bd_mbuf_data_len; 7150 else 7151 ether_mtu = ifp->if_mtu; 7152 } 7153 } 7154 7155 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7156 7157 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7158 __FUNCTION__, ether_mtu); 7159 7160 /* Program the mtu, enabling jumbo frame support if necessary. */ 7161 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7162 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7163 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7164 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7165 else 7166 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7167 7168 /* Program appropriate promiscuous/multicast filtering. */ 7169 bce_set_rx_mode(sc); 7170 7171 if (bce_hdr_split == TRUE) { 7172 /* Init page buffer descriptor chain. */ 7173 bce_init_pg_chain(sc); 7174 } 7175 7176 /* Init RX buffer descriptor chain. */ 7177 bce_init_rx_chain(sc); 7178 7179 /* Init TX buffer descriptor chain. */ 7180 bce_init_tx_chain(sc); 7181 7182 /* Enable host interrupts. */ 7183 bce_enable_intr(sc, 1); 7184 7185 bce_ifmedia_upd_locked(ifp); 7186 7187 /* Let the OS know the driver is up and running. */ 7188 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7189 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7190 7191 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7192 7193 bce_init_locked_exit: 7194 DBEXIT(BCE_VERBOSE_RESET); 7195 } 7196 7197 7198 /****************************************************************************/ 7199 /* Initialize the controller just enough so that any management firmware */ 7200 /* running on the device will continue to operate correctly. */ 7201 /* */ 7202 /* Returns: */ 7203 /* Nothing. */ 7204 /****************************************************************************/ 7205 static void 7206 bce_mgmt_init_locked(struct bce_softc *sc) 7207 { 7208 struct ifnet *ifp; 7209 7210 DBENTER(BCE_VERBOSE_RESET); 7211 7212 BCE_LOCK_ASSERT(sc); 7213 7214 /* Bail out if management firmware is not running. */ 7215 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7216 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7217 "No management firmware running...\n"); 7218 goto bce_mgmt_init_locked_exit; 7219 } 7220 7221 ifp = sc->bce_ifp; 7222 7223 /* Enable all critical blocks in the MAC. */ 7224 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7225 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7226 DELAY(20); 7227 7228 bce_ifmedia_upd_locked(ifp); 7229 7230 bce_mgmt_init_locked_exit: 7231 DBEXIT(BCE_VERBOSE_RESET); 7232 } 7233 7234 7235 /****************************************************************************/ 7236 /* Handles controller initialization when called from an unlocked routine. */ 7237 /* */ 7238 /* Returns: */ 7239 /* Nothing. */ 7240 /****************************************************************************/ 7241 static void 7242 bce_init(void *xsc) 7243 { 7244 struct bce_softc *sc = xsc; 7245 7246 DBENTER(BCE_VERBOSE_RESET); 7247 7248 BCE_LOCK(sc); 7249 bce_init_locked(sc); 7250 BCE_UNLOCK(sc); 7251 7252 DBEXIT(BCE_VERBOSE_RESET); 7253 } 7254 7255 7256 /****************************************************************************/ 7257 /* Modifies an mbuf for TSO on the hardware. */ 7258 /* */ 7259 /* Returns: */ 7260 /* Pointer to a modified mbuf. */ 7261 /****************************************************************************/ 7262 static struct mbuf * 7263 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7264 { 7265 struct mbuf *m; 7266 struct ether_header *eh; 7267 struct ip *ip; 7268 struct tcphdr *th; 7269 u16 etype; 7270 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7271 7272 DBRUN(sc->tso_frames_requested++); 7273 7274 /* Controller may modify mbuf chains. */ 7275 if (M_WRITABLE(*m_head) == 0) { 7276 m = m_dup(*m_head, M_NOWAIT); 7277 m_freem(*m_head); 7278 if (m == NULL) { 7279 sc->mbuf_alloc_failed_count++; 7280 *m_head = NULL; 7281 return (NULL); 7282 } 7283 *m_head = m; 7284 } 7285 7286 /* 7287 * For TSO the controller needs two pieces of info, 7288 * the MSS and the IP+TCP options length. 7289 */ 7290 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7291 if (m == NULL) { 7292 *m_head = NULL; 7293 return (NULL); 7294 } 7295 eh = mtod(m, struct ether_header *); 7296 etype = ntohs(eh->ether_type); 7297 7298 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7299 switch (etype) { 7300 case ETHERTYPE_IP: 7301 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7302 /* TSO only supported for TCP protocol. */ 7303 if (ip->ip_p != IPPROTO_TCP) { 7304 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7305 __FILE__, __LINE__); 7306 m_freem(*m_head); 7307 *m_head = NULL; 7308 return (NULL); 7309 } 7310 7311 /* Get IP header length in bytes (min 20) */ 7312 ip_hlen = ip->ip_hl << 2; 7313 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7314 sizeof(struct tcphdr)); 7315 if (m == NULL) { 7316 *m_head = NULL; 7317 return (NULL); 7318 } 7319 7320 /* Get the TCP header length in bytes (min 20) */ 7321 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7322 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7323 tcp_hlen = (th->th_off << 2); 7324 7325 /* Make sure all IP/TCP options live in the same buffer. */ 7326 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7327 tcp_hlen); 7328 if (m == NULL) { 7329 *m_head = NULL; 7330 return (NULL); 7331 } 7332 7333 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7334 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7335 ip_len = ip->ip_len; 7336 ip->ip_len = 0; 7337 ip->ip_sum = 0; 7338 break; 7339 case ETHERTYPE_IPV6: 7340 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7341 __FILE__, __LINE__); 7342 m_freem(*m_head); 7343 *m_head = NULL; 7344 return (NULL); 7345 /* NOT REACHED */ 7346 default: 7347 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7348 __FILE__, __LINE__); 7349 m_freem(*m_head); 7350 *m_head = NULL; 7351 return (NULL); 7352 } 7353 7354 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7355 7356 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7357 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7358 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7359 tcp_hlen, ip_len); 7360 7361 /* Set the LSO flag in the TX BD */ 7362 *flags |= TX_BD_FLAGS_SW_LSO; 7363 7364 /* Set the length of IP + TCP options (in 32 bit words) */ 7365 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7366 sizeof(struct tcphdr)) >> 2) << 8); 7367 7368 DBRUN(sc->tso_frames_completed++); 7369 return (*m_head); 7370 } 7371 7372 7373 /****************************************************************************/ 7374 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7375 /* memory visible to the controller. */ 7376 /* */ 7377 /* Returns: */ 7378 /* 0 for success, positive value for failure. */ 7379 /* Modified: */ 7380 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7381 /****************************************************************************/ 7382 static int 7383 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7384 { 7385 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7386 bus_dmamap_t map; 7387 struct tx_bd *txbd = NULL; 7388 struct mbuf *m0; 7389 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7390 u32 prod_bseq; 7391 7392 #ifdef BCE_DEBUG 7393 u16 debug_prod; 7394 #endif 7395 7396 int i, error, nsegs, rc = 0; 7397 7398 DBENTER(BCE_VERBOSE_SEND); 7399 7400 /* Make sure we have room in the TX chain. */ 7401 if (sc->used_tx_bd >= sc->max_tx_bd) 7402 goto bce_tx_encap_exit; 7403 7404 /* Transfer any checksum offload flags to the bd. */ 7405 m0 = *m_head; 7406 if (m0->m_pkthdr.csum_flags) { 7407 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7408 m0 = bce_tso_setup(sc, m_head, &flags); 7409 if (m0 == NULL) { 7410 DBRUN(sc->tso_frames_failed++); 7411 goto bce_tx_encap_exit; 7412 } 7413 mss = htole16(m0->m_pkthdr.tso_segsz); 7414 } else { 7415 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7416 flags |= TX_BD_FLAGS_IP_CKSUM; 7417 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7418 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7419 } 7420 } 7421 7422 /* Transfer any VLAN tags to the bd. */ 7423 if (m0->m_flags & M_VLANTAG) { 7424 flags |= TX_BD_FLAGS_VLAN_TAG; 7425 vlan_tag = m0->m_pkthdr.ether_vtag; 7426 } 7427 7428 /* Map the mbuf into DMAable memory. */ 7429 prod = sc->tx_prod; 7430 chain_prod = TX_CHAIN_IDX(prod); 7431 map = sc->tx_mbuf_map[chain_prod]; 7432 7433 /* Map the mbuf into our DMA address space. */ 7434 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7435 segs, &nsegs, BUS_DMA_NOWAIT); 7436 7437 /* Check if the DMA mapping was successful */ 7438 if (error == EFBIG) { 7439 sc->mbuf_frag_count++; 7440 7441 /* Try to defrag the mbuf. */ 7442 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7443 if (m0 == NULL) { 7444 /* Defrag was unsuccessful */ 7445 m_freem(*m_head); 7446 *m_head = NULL; 7447 sc->mbuf_alloc_failed_count++; 7448 rc = ENOBUFS; 7449 goto bce_tx_encap_exit; 7450 } 7451 7452 /* Defrag was successful, try mapping again */ 7453 *m_head = m0; 7454 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7455 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7456 7457 /* Still getting an error after a defrag. */ 7458 if (error == ENOMEM) { 7459 /* Insufficient DMA buffers available. */ 7460 sc->dma_map_addr_tx_failed_count++; 7461 rc = error; 7462 goto bce_tx_encap_exit; 7463 } else if (error != 0) { 7464 /* Release it and return an error. */ 7465 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7466 "TX chain!\n", __FILE__, __LINE__); 7467 m_freem(m0); 7468 *m_head = NULL; 7469 sc->dma_map_addr_tx_failed_count++; 7470 rc = ENOBUFS; 7471 goto bce_tx_encap_exit; 7472 } 7473 } else if (error == ENOMEM) { 7474 /* Insufficient DMA buffers available. */ 7475 sc->dma_map_addr_tx_failed_count++; 7476 rc = error; 7477 goto bce_tx_encap_exit; 7478 } else if (error != 0) { 7479 m_freem(m0); 7480 *m_head = NULL; 7481 sc->dma_map_addr_tx_failed_count++; 7482 rc = error; 7483 goto bce_tx_encap_exit; 7484 } 7485 7486 /* Make sure there's room in the chain */ 7487 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7488 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7489 rc = ENOBUFS; 7490 goto bce_tx_encap_exit; 7491 } 7492 7493 /* prod points to an empty tx_bd at this point. */ 7494 prod_bseq = sc->tx_prod_bseq; 7495 7496 #ifdef BCE_DEBUG 7497 debug_prod = chain_prod; 7498 #endif 7499 7500 DBPRINT(sc, BCE_INFO_SEND, 7501 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7502 "prod_bseq = 0x%08X\n", 7503 __FUNCTION__, prod, chain_prod, prod_bseq); 7504 7505 /* 7506 * Cycle through each mbuf segment that makes up 7507 * the outgoing frame, gathering the mapping info 7508 * for that segment and creating a tx_bd for 7509 * the mbuf. 7510 */ 7511 for (i = 0; i < nsegs ; i++) { 7512 7513 chain_prod = TX_CHAIN_IDX(prod); 7514 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7515 [TX_IDX(chain_prod)]; 7516 7517 txbd->tx_bd_haddr_lo = 7518 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7519 txbd->tx_bd_haddr_hi = 7520 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7521 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7522 htole16(segs[i].ds_len); 7523 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7524 txbd->tx_bd_flags = htole16(flags); 7525 prod_bseq += segs[i].ds_len; 7526 if (i == 0) 7527 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7528 prod = NEXT_TX_BD(prod); 7529 } 7530 7531 /* Set the END flag on the last TX buffer descriptor. */ 7532 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7533 7534 DBRUNMSG(BCE_EXTREME_SEND, 7535 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7536 7537 /* 7538 * Ensure that the mbuf pointer for this transmission 7539 * is placed at the array index of the last 7540 * descriptor in this chain. This is done 7541 * because a single map is used for all 7542 * segments of the mbuf and we don't want to 7543 * unload the map before all of the segments 7544 * have been freed. 7545 */ 7546 sc->tx_mbuf_ptr[chain_prod] = m0; 7547 sc->used_tx_bd += nsegs; 7548 7549 /* Update some debug statistic counters */ 7550 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7551 sc->tx_hi_watermark = sc->used_tx_bd); 7552 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7553 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7554 7555 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7556 7557 /* prod points to the next free tx_bd at this point. */ 7558 sc->tx_prod = prod; 7559 sc->tx_prod_bseq = prod_bseq; 7560 7561 /* Tell the chip about the waiting TX frames. */ 7562 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7563 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7564 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7565 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7566 7567 bce_tx_encap_exit: 7568 DBEXIT(BCE_VERBOSE_SEND); 7569 return(rc); 7570 } 7571 7572 7573 /****************************************************************************/ 7574 /* Main transmit routine when called from another routine with a lock. */ 7575 /* */ 7576 /* Returns: */ 7577 /* Nothing. */ 7578 /****************************************************************************/ 7579 static void 7580 bce_start_locked(struct ifnet *ifp) 7581 { 7582 struct bce_softc *sc = ifp->if_softc; 7583 struct mbuf *m_head = NULL; 7584 int count = 0; 7585 u16 tx_prod, tx_chain_prod; 7586 7587 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7588 7589 BCE_LOCK_ASSERT(sc); 7590 7591 /* prod points to the next free tx_bd. */ 7592 tx_prod = sc->tx_prod; 7593 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7594 7595 DBPRINT(sc, BCE_INFO_SEND, 7596 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7597 "tx_prod_bseq = 0x%08X\n", 7598 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7599 7600 /* If there's no link or the transmit queue is empty then just exit. */ 7601 if (sc->bce_link_up == FALSE) { 7602 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7603 __FUNCTION__); 7604 goto bce_start_locked_exit; 7605 } 7606 7607 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7608 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7609 __FUNCTION__); 7610 goto bce_start_locked_exit; 7611 } 7612 7613 /* 7614 * Keep adding entries while there is space in the ring. 7615 */ 7616 while (sc->used_tx_bd < sc->max_tx_bd) { 7617 7618 /* Check for any frames to send. */ 7619 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7620 7621 /* Stop when the transmit queue is empty. */ 7622 if (m_head == NULL) 7623 break; 7624 7625 /* 7626 * Pack the data into the transmit ring. If we 7627 * don't have room, place the mbuf back at the 7628 * head of the queue and set the OACTIVE flag 7629 * to wait for the NIC to drain the chain. 7630 */ 7631 if (bce_tx_encap(sc, &m_head)) { 7632 if (m_head != NULL) 7633 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7634 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7635 DBPRINT(sc, BCE_INFO_SEND, 7636 "TX chain is closed for business! Total " 7637 "tx_bd used = %d\n", sc->used_tx_bd); 7638 break; 7639 } 7640 7641 count++; 7642 7643 /* Send a copy of the frame to any BPF listeners. */ 7644 ETHER_BPF_MTAP(ifp, m_head); 7645 } 7646 7647 /* Exit if no packets were dequeued. */ 7648 if (count == 0) { 7649 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7650 "dequeued\n", __FUNCTION__); 7651 goto bce_start_locked_exit; 7652 } 7653 7654 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7655 "send queue.\n", __FUNCTION__, count); 7656 7657 /* Set the tx timeout. */ 7658 sc->watchdog_timer = BCE_TX_TIMEOUT; 7659 7660 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7661 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7662 7663 bce_start_locked_exit: 7664 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7665 } 7666 7667 7668 /****************************************************************************/ 7669 /* Main transmit routine when called from another routine without a lock. */ 7670 /* */ 7671 /* Returns: */ 7672 /* Nothing. */ 7673 /****************************************************************************/ 7674 static void 7675 bce_start(struct ifnet *ifp) 7676 { 7677 struct bce_softc *sc = ifp->if_softc; 7678 7679 DBENTER(BCE_VERBOSE_SEND); 7680 7681 BCE_LOCK(sc); 7682 bce_start_locked(ifp); 7683 BCE_UNLOCK(sc); 7684 7685 DBEXIT(BCE_VERBOSE_SEND); 7686 } 7687 7688 7689 /****************************************************************************/ 7690 /* Handles any IOCTL calls from the operating system. */ 7691 /* */ 7692 /* Returns: */ 7693 /* 0 for success, positive value for failure. */ 7694 /****************************************************************************/ 7695 static int 7696 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7697 { 7698 struct bce_softc *sc = ifp->if_softc; 7699 struct ifreq *ifr = (struct ifreq *) data; 7700 struct mii_data *mii; 7701 int mask, error = 0; 7702 7703 DBENTER(BCE_VERBOSE_MISC); 7704 7705 switch(command) { 7706 7707 /* Set the interface MTU. */ 7708 case SIOCSIFMTU: 7709 /* Check that the MTU setting is supported. */ 7710 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7711 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7712 error = EINVAL; 7713 break; 7714 } 7715 7716 DBPRINT(sc, BCE_INFO_MISC, 7717 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7718 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7719 7720 BCE_LOCK(sc); 7721 ifp->if_mtu = ifr->ifr_mtu; 7722 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7723 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7724 bce_init_locked(sc); 7725 } 7726 BCE_UNLOCK(sc); 7727 break; 7728 7729 /* Set interface flags. */ 7730 case SIOCSIFFLAGS: 7731 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7732 7733 BCE_LOCK(sc); 7734 7735 /* Check if the interface is up. */ 7736 if (ifp->if_flags & IFF_UP) { 7737 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7738 /* Change promiscuous/multicast flags as necessary. */ 7739 bce_set_rx_mode(sc); 7740 } else { 7741 /* Start the HW */ 7742 bce_init_locked(sc); 7743 } 7744 } else { 7745 /* The interface is down, check if driver is running. */ 7746 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7747 bce_stop(sc); 7748 7749 /* If MFW is running, restart the controller a bit. */ 7750 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7751 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7752 bce_chipinit(sc); 7753 bce_mgmt_init_locked(sc); 7754 } 7755 } 7756 } 7757 7758 BCE_UNLOCK(sc); 7759 break; 7760 7761 /* Add/Delete multicast address */ 7762 case SIOCADDMULTI: 7763 case SIOCDELMULTI: 7764 DBPRINT(sc, BCE_VERBOSE_MISC, 7765 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7766 7767 BCE_LOCK(sc); 7768 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7769 bce_set_rx_mode(sc); 7770 BCE_UNLOCK(sc); 7771 7772 break; 7773 7774 /* Set/Get Interface media */ 7775 case SIOCSIFMEDIA: 7776 case SIOCGIFMEDIA: 7777 DBPRINT(sc, BCE_VERBOSE_MISC, 7778 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7779 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7780 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7781 command); 7782 else { 7783 mii = device_get_softc(sc->bce_miibus); 7784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7785 command); 7786 } 7787 break; 7788 7789 /* Set interface capability */ 7790 case SIOCSIFCAP: 7791 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7792 DBPRINT(sc, BCE_INFO_MISC, 7793 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7794 7795 /* Toggle the TX checksum capabilities enable flag. */ 7796 if (mask & IFCAP_TXCSUM && 7797 ifp->if_capabilities & IFCAP_TXCSUM) { 7798 ifp->if_capenable ^= IFCAP_TXCSUM; 7799 if (IFCAP_TXCSUM & ifp->if_capenable) 7800 ifp->if_hwassist |= BCE_IF_HWASSIST; 7801 else 7802 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7803 } 7804 7805 /* Toggle the RX checksum capabilities enable flag. */ 7806 if (mask & IFCAP_RXCSUM && 7807 ifp->if_capabilities & IFCAP_RXCSUM) 7808 ifp->if_capenable ^= IFCAP_RXCSUM; 7809 7810 /* Toggle the TSO capabilities enable flag. */ 7811 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7812 ifp->if_capabilities & IFCAP_TSO4) { 7813 ifp->if_capenable ^= IFCAP_TSO4; 7814 if (IFCAP_TSO4 & ifp->if_capenable) 7815 ifp->if_hwassist |= CSUM_TSO; 7816 else 7817 ifp->if_hwassist &= ~CSUM_TSO; 7818 } 7819 7820 if (mask & IFCAP_VLAN_HWCSUM && 7821 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7822 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7823 7824 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7825 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7826 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7827 /* 7828 * Don't actually disable VLAN tag stripping as 7829 * management firmware (ASF/IPMI/UMP) requires the 7830 * feature. If VLAN tag stripping is disabled driver 7831 * will manually reconstruct the VLAN frame by 7832 * appending stripped VLAN tag. 7833 */ 7834 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7835 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7836 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7837 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7838 == 0) 7839 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7840 } 7841 VLAN_CAPABILITIES(ifp); 7842 break; 7843 default: 7844 /* We don't know how to handle the IOCTL, pass it on. */ 7845 error = ether_ioctl(ifp, command, data); 7846 break; 7847 } 7848 7849 DBEXIT(BCE_VERBOSE_MISC); 7850 return(error); 7851 } 7852 7853 7854 /****************************************************************************/ 7855 /* Transmit timeout handler. */ 7856 /* */ 7857 /* Returns: */ 7858 /* Nothing. */ 7859 /****************************************************************************/ 7860 static void 7861 bce_watchdog(struct bce_softc *sc) 7862 { 7863 uint32_t status; 7864 7865 DBENTER(BCE_EXTREME_SEND); 7866 7867 BCE_LOCK_ASSERT(sc); 7868 7869 status = 0; 7870 /* If the watchdog timer hasn't expired then just exit. */ 7871 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7872 goto bce_watchdog_exit; 7873 7874 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7875 /* If pause frames are active then don't reset the hardware. */ 7876 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7877 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7878 /* 7879 * If link partner has us in XOFF state then wait for 7880 * the condition to clear. 7881 */ 7882 sc->watchdog_timer = BCE_TX_TIMEOUT; 7883 goto bce_watchdog_exit; 7884 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7885 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7886 /* 7887 * If we're not currently XOFF'ed but have recently 7888 * been XOFF'd/XON'd then assume that's delaying TX 7889 * this time around. 7890 */ 7891 sc->watchdog_timer = BCE_TX_TIMEOUT; 7892 goto bce_watchdog_exit; 7893 } 7894 /* 7895 * Any other condition is unexpected and the controller 7896 * should be reset. 7897 */ 7898 } 7899 7900 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7901 __FILE__, __LINE__); 7902 7903 DBRUNMSG(BCE_INFO, 7904 bce_dump_driver_state(sc); 7905 bce_dump_status_block(sc); 7906 bce_dump_stats_block(sc); 7907 bce_dump_ftqs(sc); 7908 bce_dump_txp_state(sc, 0); 7909 bce_dump_rxp_state(sc, 0); 7910 bce_dump_tpat_state(sc, 0); 7911 bce_dump_cp_state(sc, 0); 7912 bce_dump_com_state(sc, 0)); 7913 7914 DBRUN(bce_breakpoint(sc)); 7915 7916 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7917 7918 bce_init_locked(sc); 7919 sc->bce_ifp->if_oerrors++; 7920 7921 bce_watchdog_exit: 7922 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7923 DBEXIT(BCE_EXTREME_SEND); 7924 } 7925 7926 7927 /* 7928 * Interrupt handler. 7929 */ 7930 /****************************************************************************/ 7931 /* Main interrupt entry point. Verifies that the controller generated the */ 7932 /* interrupt and then calls a separate routine for handle the various */ 7933 /* interrupt causes (PHY, TX, RX). */ 7934 /* */ 7935 /* Returns: */ 7936 /* Nothing. */ 7937 /****************************************************************************/ 7938 static void 7939 bce_intr(void *xsc) 7940 { 7941 struct bce_softc *sc; 7942 struct ifnet *ifp; 7943 u32 status_attn_bits; 7944 u16 hw_rx_cons, hw_tx_cons; 7945 7946 sc = xsc; 7947 ifp = sc->bce_ifp; 7948 7949 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7950 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7951 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7952 7953 BCE_LOCK(sc); 7954 7955 DBRUN(sc->interrupts_generated++); 7956 7957 /* Synchnorize before we read from interface's status block */ 7958 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7959 7960 /* 7961 * If the hardware status block index matches the last value read 7962 * by the driver and we haven't asserted our interrupt then there's 7963 * nothing to do. This may only happen in case of INTx due to the 7964 * interrupt arriving at the CPU before the status block is updated. 7965 */ 7966 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7967 sc->status_block->status_idx == sc->last_status_idx && 7968 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7969 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7970 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7971 __FUNCTION__); 7972 goto bce_intr_exit; 7973 } 7974 7975 /* Ack the interrupt and stop others from occuring. */ 7976 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7977 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7978 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7979 7980 /* Check if the hardware has finished any work. */ 7981 hw_rx_cons = bce_get_hw_rx_cons(sc); 7982 hw_tx_cons = bce_get_hw_tx_cons(sc); 7983 7984 /* Keep processing data as long as there is work to do. */ 7985 for (;;) { 7986 7987 status_attn_bits = sc->status_block->status_attn_bits; 7988 7989 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7990 BCE_PRINTF("Simulating unexpected status attention " 7991 "bit set."); 7992 sc->unexpected_attention_sim_count++; 7993 status_attn_bits = status_attn_bits | 7994 STATUS_ATTN_BITS_PARITY_ERROR); 7995 7996 /* Was it a link change interrupt? */ 7997 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7998 (sc->status_block->status_attn_bits_ack & 7999 STATUS_ATTN_BITS_LINK_STATE)) { 8000 bce_phy_intr(sc); 8001 8002 /* Clear transient updates during link state change. */ 8003 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 8004 BCE_HC_COMMAND_COAL_NOW_WO_INT); 8005 REG_RD(sc, BCE_HC_COMMAND); 8006 } 8007 8008 /* If any other attention is asserted, the chip is toast. */ 8009 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 8010 (sc->status_block->status_attn_bits_ack & 8011 ~STATUS_ATTN_BITS_LINK_STATE))) { 8012 8013 sc->unexpected_attention_count++; 8014 8015 BCE_PRINTF("%s(%d): Fatal attention detected: " 8016 "0x%08X\n", __FILE__, __LINE__, 8017 sc->status_block->status_attn_bits); 8018 8019 DBRUNMSG(BCE_FATAL, 8020 if (unexpected_attention_sim_control == 0) 8021 bce_breakpoint(sc)); 8022 8023 bce_init_locked(sc); 8024 goto bce_intr_exit; 8025 } 8026 8027 /* Check for any completed RX frames. */ 8028 if (hw_rx_cons != sc->hw_rx_cons) 8029 bce_rx_intr(sc); 8030 8031 /* Check for any completed TX frames. */ 8032 if (hw_tx_cons != sc->hw_tx_cons) 8033 bce_tx_intr(sc); 8034 8035 /* Save status block index value for the next interrupt. */ 8036 sc->last_status_idx = sc->status_block->status_idx; 8037 8038 /* 8039 * Prevent speculative reads from getting 8040 * ahead of the status block. 8041 */ 8042 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8043 BUS_SPACE_BARRIER_READ); 8044 8045 /* 8046 * If there's no work left then exit the 8047 * interrupt service routine. 8048 */ 8049 hw_rx_cons = bce_get_hw_rx_cons(sc); 8050 hw_tx_cons = bce_get_hw_tx_cons(sc); 8051 8052 if ((hw_rx_cons == sc->hw_rx_cons) && 8053 (hw_tx_cons == sc->hw_tx_cons)) 8054 break; 8055 } 8056 8057 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8058 8059 /* Re-enable interrupts. */ 8060 bce_enable_intr(sc, 0); 8061 8062 /* Handle any frames that arrived while handling the interrupt. */ 8063 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8064 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8065 bce_start_locked(ifp); 8066 8067 bce_intr_exit: 8068 BCE_UNLOCK(sc); 8069 8070 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8071 } 8072 8073 8074 /****************************************************************************/ 8075 /* Programs the various packet receive modes (broadcast and multicast). */ 8076 /* */ 8077 /* Returns: */ 8078 /* Nothing. */ 8079 /****************************************************************************/ 8080 static void 8081 bce_set_rx_mode(struct bce_softc *sc) 8082 { 8083 struct ifnet *ifp; 8084 struct ifmultiaddr *ifma; 8085 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8086 u32 rx_mode, sort_mode; 8087 int h, i; 8088 8089 DBENTER(BCE_VERBOSE_MISC); 8090 8091 BCE_LOCK_ASSERT(sc); 8092 8093 ifp = sc->bce_ifp; 8094 8095 /* Initialize receive mode default settings. */ 8096 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8097 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8098 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8099 8100 /* 8101 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8102 * be enbled. 8103 */ 8104 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8105 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8106 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8107 8108 /* 8109 * Check for promiscuous, all multicast, or selected 8110 * multicast address filtering. 8111 */ 8112 if (ifp->if_flags & IFF_PROMISC) { 8113 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8114 8115 /* Enable promiscuous mode. */ 8116 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8117 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8118 } else if (ifp->if_flags & IFF_ALLMULTI) { 8119 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8120 8121 /* Enable all multicast addresses. */ 8122 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8123 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8124 0xffffffff); 8125 } 8126 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8127 } else { 8128 /* Accept one or more multicast(s). */ 8129 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8130 8131 if_maddr_rlock(ifp); 8132 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8133 if (ifma->ifma_addr->sa_family != AF_LINK) 8134 continue; 8135 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8136 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8137 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8138 } 8139 if_maddr_runlock(ifp); 8140 8141 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8142 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8143 8144 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8145 } 8146 8147 /* Only make changes if the recive mode has actually changed. */ 8148 if (rx_mode != sc->rx_mode) { 8149 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8150 "0x%08X\n", rx_mode); 8151 8152 sc->rx_mode = rx_mode; 8153 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8154 } 8155 8156 /* Disable and clear the exisitng sort before enabling a new sort. */ 8157 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8158 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8159 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8160 8161 DBEXIT(BCE_VERBOSE_MISC); 8162 } 8163 8164 8165 /****************************************************************************/ 8166 /* Called periodically to updates statistics from the controllers */ 8167 /* statistics block. */ 8168 /* */ 8169 /* Returns: */ 8170 /* Nothing. */ 8171 /****************************************************************************/ 8172 static void 8173 bce_stats_update(struct bce_softc *sc) 8174 { 8175 struct ifnet *ifp; 8176 struct statistics_block *stats; 8177 8178 DBENTER(BCE_EXTREME_MISC); 8179 8180 ifp = sc->bce_ifp; 8181 8182 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8183 8184 stats = (struct statistics_block *) sc->stats_block; 8185 8186 /* 8187 * Certain controllers don't report 8188 * carrier sense errors correctly. 8189 * See errata E11_5708CA0_1165. 8190 */ 8191 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8192 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8193 ifp->if_oerrors += 8194 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 8195 8196 /* 8197 * Update the sysctl statistics from the 8198 * hardware statistics. 8199 */ 8200 sc->stat_IfHCInOctets = 8201 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8202 (u64) stats->stat_IfHCInOctets_lo; 8203 8204 sc->stat_IfHCInBadOctets = 8205 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8206 (u64) stats->stat_IfHCInBadOctets_lo; 8207 8208 sc->stat_IfHCOutOctets = 8209 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8210 (u64) stats->stat_IfHCOutOctets_lo; 8211 8212 sc->stat_IfHCOutBadOctets = 8213 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8214 (u64) stats->stat_IfHCOutBadOctets_lo; 8215 8216 sc->stat_IfHCInUcastPkts = 8217 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8218 (u64) stats->stat_IfHCInUcastPkts_lo; 8219 8220 sc->stat_IfHCInMulticastPkts = 8221 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8222 (u64) stats->stat_IfHCInMulticastPkts_lo; 8223 8224 sc->stat_IfHCInBroadcastPkts = 8225 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8226 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8227 8228 sc->stat_IfHCOutUcastPkts = 8229 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8230 (u64) stats->stat_IfHCOutUcastPkts_lo; 8231 8232 sc->stat_IfHCOutMulticastPkts = 8233 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8234 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8235 8236 sc->stat_IfHCOutBroadcastPkts = 8237 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8238 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8239 8240 /* ToDo: Preserve counters beyond 32 bits? */ 8241 /* ToDo: Read the statistics from auto-clear regs? */ 8242 8243 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8244 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8245 8246 sc->stat_Dot3StatsCarrierSenseErrors = 8247 stats->stat_Dot3StatsCarrierSenseErrors; 8248 8249 sc->stat_Dot3StatsFCSErrors = 8250 stats->stat_Dot3StatsFCSErrors; 8251 8252 sc->stat_Dot3StatsAlignmentErrors = 8253 stats->stat_Dot3StatsAlignmentErrors; 8254 8255 sc->stat_Dot3StatsSingleCollisionFrames = 8256 stats->stat_Dot3StatsSingleCollisionFrames; 8257 8258 sc->stat_Dot3StatsMultipleCollisionFrames = 8259 stats->stat_Dot3StatsMultipleCollisionFrames; 8260 8261 sc->stat_Dot3StatsDeferredTransmissions = 8262 stats->stat_Dot3StatsDeferredTransmissions; 8263 8264 sc->stat_Dot3StatsExcessiveCollisions = 8265 stats->stat_Dot3StatsExcessiveCollisions; 8266 8267 sc->stat_Dot3StatsLateCollisions = 8268 stats->stat_Dot3StatsLateCollisions; 8269 8270 sc->stat_EtherStatsCollisions = 8271 stats->stat_EtherStatsCollisions; 8272 8273 sc->stat_EtherStatsFragments = 8274 stats->stat_EtherStatsFragments; 8275 8276 sc->stat_EtherStatsJabbers = 8277 stats->stat_EtherStatsJabbers; 8278 8279 sc->stat_EtherStatsUndersizePkts = 8280 stats->stat_EtherStatsUndersizePkts; 8281 8282 sc->stat_EtherStatsOversizePkts = 8283 stats->stat_EtherStatsOversizePkts; 8284 8285 sc->stat_EtherStatsPktsRx64Octets = 8286 stats->stat_EtherStatsPktsRx64Octets; 8287 8288 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8289 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8290 8291 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8292 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8293 8294 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8295 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8296 8297 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8298 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8299 8300 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8301 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8302 8303 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8304 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8305 8306 sc->stat_EtherStatsPktsTx64Octets = 8307 stats->stat_EtherStatsPktsTx64Octets; 8308 8309 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8310 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8311 8312 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8313 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8314 8315 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8316 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8317 8318 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8319 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8320 8321 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8322 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8323 8324 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8325 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8326 8327 sc->stat_XonPauseFramesReceived = 8328 stats->stat_XonPauseFramesReceived; 8329 8330 sc->stat_XoffPauseFramesReceived = 8331 stats->stat_XoffPauseFramesReceived; 8332 8333 sc->stat_OutXonSent = 8334 stats->stat_OutXonSent; 8335 8336 sc->stat_OutXoffSent = 8337 stats->stat_OutXoffSent; 8338 8339 sc->stat_FlowControlDone = 8340 stats->stat_FlowControlDone; 8341 8342 sc->stat_MacControlFramesReceived = 8343 stats->stat_MacControlFramesReceived; 8344 8345 sc->stat_XoffStateEntered = 8346 stats->stat_XoffStateEntered; 8347 8348 sc->stat_IfInFramesL2FilterDiscards = 8349 stats->stat_IfInFramesL2FilterDiscards; 8350 8351 sc->stat_IfInRuleCheckerDiscards = 8352 stats->stat_IfInRuleCheckerDiscards; 8353 8354 sc->stat_IfInFTQDiscards = 8355 stats->stat_IfInFTQDiscards; 8356 8357 sc->stat_IfInMBUFDiscards = 8358 stats->stat_IfInMBUFDiscards; 8359 8360 sc->stat_IfInRuleCheckerP4Hit = 8361 stats->stat_IfInRuleCheckerP4Hit; 8362 8363 sc->stat_CatchupInRuleCheckerDiscards = 8364 stats->stat_CatchupInRuleCheckerDiscards; 8365 8366 sc->stat_CatchupInFTQDiscards = 8367 stats->stat_CatchupInFTQDiscards; 8368 8369 sc->stat_CatchupInMBUFDiscards = 8370 stats->stat_CatchupInMBUFDiscards; 8371 8372 sc->stat_CatchupInRuleCheckerP4Hit = 8373 stats->stat_CatchupInRuleCheckerP4Hit; 8374 8375 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8376 8377 /* 8378 * Update the interface statistics from the 8379 * hardware statistics. 8380 */ 8381 ifp->if_collisions = 8382 (u_long) sc->stat_EtherStatsCollisions; 8383 8384 /* ToDo: This method loses soft errors. */ 8385 ifp->if_ierrors = 8386 (u_long) sc->stat_EtherStatsUndersizePkts + 8387 (u_long) sc->stat_EtherStatsOversizePkts + 8388 (u_long) sc->stat_IfInMBUFDiscards + 8389 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8390 (u_long) sc->stat_Dot3StatsFCSErrors + 8391 (u_long) sc->stat_IfInRuleCheckerDiscards + 8392 (u_long) sc->stat_IfInFTQDiscards + 8393 (u_long) sc->com_no_buffers; 8394 8395 /* ToDo: This method loses soft errors. */ 8396 ifp->if_oerrors = 8397 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8398 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8399 (u_long) sc->stat_Dot3StatsLateCollisions; 8400 8401 /* ToDo: Add additional statistics? */ 8402 8403 DBEXIT(BCE_EXTREME_MISC); 8404 } 8405 8406 8407 /****************************************************************************/ 8408 /* Periodic function to notify the bootcode that the driver is still */ 8409 /* present. */ 8410 /* */ 8411 /* Returns: */ 8412 /* Nothing. */ 8413 /****************************************************************************/ 8414 static void 8415 bce_pulse(void *xsc) 8416 { 8417 struct bce_softc *sc = xsc; 8418 u32 msg; 8419 8420 DBENTER(BCE_EXTREME_MISC); 8421 8422 BCE_LOCK_ASSERT(sc); 8423 8424 /* Tell the firmware that the driver is still running. */ 8425 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8426 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8427 8428 /* Update the bootcode condition. */ 8429 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8430 8431 /* Report whether the bootcode still knows the driver is running. */ 8432 if (bce_verbose || bootverbose) { 8433 if (sc->bce_drv_cardiac_arrest == FALSE) { 8434 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8435 sc->bce_drv_cardiac_arrest = TRUE; 8436 BCE_PRINTF("%s(): Warning: bootcode " 8437 "thinks driver is absent! " 8438 "(bc_state = 0x%08X)\n", 8439 __FUNCTION__, sc->bc_state); 8440 } 8441 } else { 8442 /* 8443 * Not supported by all bootcode versions. 8444 * (v5.0.11+ and v5.2.1+) Older bootcode 8445 * will require the driver to reset the 8446 * controller to clear this condition. 8447 */ 8448 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8449 sc->bce_drv_cardiac_arrest = FALSE; 8450 BCE_PRINTF("%s(): Bootcode found the " 8451 "driver pulse! (bc_state = 0x%08X)\n", 8452 __FUNCTION__, sc->bc_state); 8453 } 8454 } 8455 } 8456 8457 8458 /* Schedule the next pulse. */ 8459 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8460 8461 DBEXIT(BCE_EXTREME_MISC); 8462 } 8463 8464 8465 /****************************************************************************/ 8466 /* Periodic function to perform maintenance tasks. */ 8467 /* */ 8468 /* Returns: */ 8469 /* Nothing. */ 8470 /****************************************************************************/ 8471 static void 8472 bce_tick(void *xsc) 8473 { 8474 struct bce_softc *sc = xsc; 8475 struct mii_data *mii; 8476 struct ifnet *ifp; 8477 struct ifmediareq ifmr; 8478 8479 ifp = sc->bce_ifp; 8480 8481 DBENTER(BCE_EXTREME_MISC); 8482 8483 BCE_LOCK_ASSERT(sc); 8484 8485 /* Schedule the next tick. */ 8486 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8487 8488 /* Update the statistics from the hardware statistics block. */ 8489 bce_stats_update(sc); 8490 8491 /* Ensure page and RX chains get refilled in low-memory situations. */ 8492 if (bce_hdr_split == TRUE) 8493 bce_fill_pg_chain(sc); 8494 bce_fill_rx_chain(sc); 8495 8496 /* Check that chip hasn't hung. */ 8497 bce_watchdog(sc); 8498 8499 /* If link is up already up then we're done. */ 8500 if (sc->bce_link_up == TRUE) 8501 goto bce_tick_exit; 8502 8503 /* Link is down. Check what the PHY's doing. */ 8504 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8505 bzero(&ifmr, sizeof(ifmr)); 8506 bce_ifmedia_sts_rphy(sc, &ifmr); 8507 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8508 (IFM_ACTIVE | IFM_AVALID)) { 8509 sc->bce_link_up = TRUE; 8510 bce_miibus_statchg(sc->bce_dev); 8511 } 8512 } else { 8513 mii = device_get_softc(sc->bce_miibus); 8514 mii_tick(mii); 8515 /* Check if the link has come up. */ 8516 if ((mii->mii_media_status & IFM_ACTIVE) && 8517 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8518 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8519 __FUNCTION__); 8520 sc->bce_link_up = TRUE; 8521 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8522 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8523 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8524 (bce_verbose || bootverbose)) 8525 BCE_PRINTF("Gigabit link up!\n"); 8526 } 8527 8528 } 8529 if (sc->bce_link_up == TRUE) { 8530 /* Now that link is up, handle any outstanding TX traffic. */ 8531 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8532 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8533 "pending TX traffic.\n", __FUNCTION__); 8534 bce_start_locked(ifp); 8535 } 8536 } 8537 8538 bce_tick_exit: 8539 DBEXIT(BCE_EXTREME_MISC); 8540 } 8541 8542 static void 8543 bce_fw_cap_init(struct bce_softc *sc) 8544 { 8545 u32 ack, cap, link; 8546 8547 ack = 0; 8548 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8549 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8550 BCE_FW_CAP_SIGNATURE_MAGIC) 8551 return; 8552 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8553 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8554 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8555 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8556 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8557 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8558 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8559 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8560 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8561 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8562 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8563 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8564 BCE_FW_CAP_REMOTE_PHY_CAP; 8565 } 8566 8567 if (ack != 0) 8568 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8569 } 8570 8571 8572 #ifdef BCE_DEBUG 8573 /****************************************************************************/ 8574 /* Allows the driver state to be dumped through the sysctl interface. */ 8575 /* */ 8576 /* Returns: */ 8577 /* 0 for success, positive value for failure. */ 8578 /****************************************************************************/ 8579 static int 8580 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8581 { 8582 int error; 8583 int result; 8584 struct bce_softc *sc; 8585 8586 result = -1; 8587 error = sysctl_handle_int(oidp, &result, 0, req); 8588 8589 if (error || !req->newptr) 8590 return (error); 8591 8592 if (result == 1) { 8593 sc = (struct bce_softc *)arg1; 8594 bce_dump_driver_state(sc); 8595 } 8596 8597 return error; 8598 } 8599 8600 8601 /****************************************************************************/ 8602 /* Allows the hardware state to be dumped through the sysctl interface. */ 8603 /* */ 8604 /* Returns: */ 8605 /* 0 for success, positive value for failure. */ 8606 /****************************************************************************/ 8607 static int 8608 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8609 { 8610 int error; 8611 int result; 8612 struct bce_softc *sc; 8613 8614 result = -1; 8615 error = sysctl_handle_int(oidp, &result, 0, req); 8616 8617 if (error || !req->newptr) 8618 return (error); 8619 8620 if (result == 1) { 8621 sc = (struct bce_softc *)arg1; 8622 bce_dump_hw_state(sc); 8623 } 8624 8625 return error; 8626 } 8627 8628 8629 /****************************************************************************/ 8630 /* Allows the status block to be dumped through the sysctl interface. */ 8631 /* */ 8632 /* Returns: */ 8633 /* 0 for success, positive value for failure. */ 8634 /****************************************************************************/ 8635 static int 8636 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8637 { 8638 int error; 8639 int result; 8640 struct bce_softc *sc; 8641 8642 result = -1; 8643 error = sysctl_handle_int(oidp, &result, 0, req); 8644 8645 if (error || !req->newptr) 8646 return (error); 8647 8648 if (result == 1) { 8649 sc = (struct bce_softc *)arg1; 8650 bce_dump_status_block(sc); 8651 } 8652 8653 return error; 8654 } 8655 8656 8657 /****************************************************************************/ 8658 /* Allows the stats block to be dumped through the sysctl interface. */ 8659 /* */ 8660 /* Returns: */ 8661 /* 0 for success, positive value for failure. */ 8662 /****************************************************************************/ 8663 static int 8664 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8665 { 8666 int error; 8667 int result; 8668 struct bce_softc *sc; 8669 8670 result = -1; 8671 error = sysctl_handle_int(oidp, &result, 0, req); 8672 8673 if (error || !req->newptr) 8674 return (error); 8675 8676 if (result == 1) { 8677 sc = (struct bce_softc *)arg1; 8678 bce_dump_stats_block(sc); 8679 } 8680 8681 return error; 8682 } 8683 8684 8685 /****************************************************************************/ 8686 /* Allows the stat counters to be cleared without unloading/reloading the */ 8687 /* driver. */ 8688 /* */ 8689 /* Returns: */ 8690 /* 0 for success, positive value for failure. */ 8691 /****************************************************************************/ 8692 static int 8693 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8694 { 8695 int error; 8696 int result; 8697 struct bce_softc *sc; 8698 8699 result = -1; 8700 error = sysctl_handle_int(oidp, &result, 0, req); 8701 8702 if (error || !req->newptr) 8703 return (error); 8704 8705 if (result == 1) { 8706 sc = (struct bce_softc *)arg1; 8707 struct statistics_block *stats; 8708 8709 stats = (struct statistics_block *) sc->stats_block; 8710 bzero(stats, sizeof(struct statistics_block)); 8711 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8713 8714 /* Clear the internal H/W statistics counters. */ 8715 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8716 8717 /* Reset the driver maintained statistics. */ 8718 sc->interrupts_rx = 8719 sc->interrupts_tx = 0; 8720 sc->tso_frames_requested = 8721 sc->tso_frames_completed = 8722 sc->tso_frames_failed = 0; 8723 sc->rx_empty_count = 8724 sc->tx_full_count = 0; 8725 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8726 sc->tx_hi_watermark = 0; 8727 sc->l2fhdr_error_count = 8728 sc->l2fhdr_error_sim_count = 0; 8729 sc->mbuf_alloc_failed_count = 8730 sc->mbuf_alloc_failed_sim_count = 0; 8731 sc->dma_map_addr_rx_failed_count = 8732 sc->dma_map_addr_tx_failed_count = 0; 8733 sc->mbuf_frag_count = 0; 8734 sc->csum_offload_tcp_udp = 8735 sc->csum_offload_ip = 0; 8736 sc->vlan_tagged_frames_rcvd = 8737 sc->vlan_tagged_frames_stripped = 0; 8738 sc->split_header_frames_rcvd = 8739 sc->split_header_tcp_frames_rcvd = 0; 8740 8741 /* Clear firmware maintained statistics. */ 8742 REG_WR_IND(sc, 0x120084, 0); 8743 } 8744 8745 return error; 8746 } 8747 8748 8749 /****************************************************************************/ 8750 /* Allows the shared memory contents to be dumped through the sysctl . */ 8751 /* interface. */ 8752 /* */ 8753 /* Returns: */ 8754 /* 0 for success, positive value for failure. */ 8755 /****************************************************************************/ 8756 static int 8757 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8758 { 8759 int error; 8760 int result; 8761 struct bce_softc *sc; 8762 8763 result = -1; 8764 error = sysctl_handle_int(oidp, &result, 0, req); 8765 8766 if (error || !req->newptr) 8767 return (error); 8768 8769 if (result == 1) { 8770 sc = (struct bce_softc *)arg1; 8771 bce_dump_shmem_state(sc); 8772 } 8773 8774 return error; 8775 } 8776 8777 8778 /****************************************************************************/ 8779 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8780 /* */ 8781 /* Returns: */ 8782 /* 0 for success, positive value for failure. */ 8783 /****************************************************************************/ 8784 static int 8785 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8786 { 8787 int error; 8788 int result; 8789 struct bce_softc *sc; 8790 8791 result = -1; 8792 error = sysctl_handle_int(oidp, &result, 0, req); 8793 8794 if (error || !req->newptr) 8795 return (error); 8796 8797 if (result == 1) { 8798 sc = (struct bce_softc *)arg1; 8799 bce_dump_bc_state(sc); 8800 } 8801 8802 return error; 8803 } 8804 8805 8806 /****************************************************************************/ 8807 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8808 /* */ 8809 /* Returns: */ 8810 /* 0 for success, positive value for failure. */ 8811 /****************************************************************************/ 8812 static int 8813 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8814 { 8815 int error; 8816 int result; 8817 struct bce_softc *sc; 8818 8819 result = -1; 8820 error = sysctl_handle_int(oidp, &result, 0, req); 8821 8822 if (error || !req->newptr) 8823 return (error); 8824 8825 if (result == 1) { 8826 sc = (struct bce_softc *)arg1; 8827 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8828 } 8829 8830 return error; 8831 } 8832 8833 8834 /****************************************************************************/ 8835 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8836 /* */ 8837 /* Returns: */ 8838 /* 0 for success, positive value for failure. */ 8839 /****************************************************************************/ 8840 static int 8841 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8842 { 8843 int error; 8844 int result; 8845 struct bce_softc *sc; 8846 8847 result = -1; 8848 error = sysctl_handle_int(oidp, &result, 0, req); 8849 8850 if (error || !req->newptr) 8851 return (error); 8852 8853 if (result == 1) { 8854 sc = (struct bce_softc *)arg1; 8855 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8856 } 8857 8858 return error; 8859 } 8860 8861 8862 /****************************************************************************/ 8863 /* Provides a sysctl interface to allow dumping the TX chain. */ 8864 /* */ 8865 /* Returns: */ 8866 /* 0 for success, positive value for failure. */ 8867 /****************************************************************************/ 8868 static int 8869 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8870 { 8871 int error; 8872 int result; 8873 struct bce_softc *sc; 8874 8875 result = -1; 8876 error = sysctl_handle_int(oidp, &result, 0, req); 8877 8878 if (error || !req->newptr) 8879 return (error); 8880 8881 if (result == 1) { 8882 sc = (struct bce_softc *)arg1; 8883 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8884 } 8885 8886 return error; 8887 } 8888 8889 8890 /****************************************************************************/ 8891 /* Provides a sysctl interface to allow dumping the page chain. */ 8892 /* */ 8893 /* Returns: */ 8894 /* 0 for success, positive value for failure. */ 8895 /****************************************************************************/ 8896 static int 8897 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8898 { 8899 int error; 8900 int result; 8901 struct bce_softc *sc; 8902 8903 result = -1; 8904 error = sysctl_handle_int(oidp, &result, 0, req); 8905 8906 if (error || !req->newptr) 8907 return (error); 8908 8909 if (result == 1) { 8910 sc = (struct bce_softc *)arg1; 8911 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8912 } 8913 8914 return error; 8915 } 8916 8917 /****************************************************************************/ 8918 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8919 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8920 /* */ 8921 /* Returns: */ 8922 /* 0 for success, positive value for failure. */ 8923 /****************************************************************************/ 8924 static int 8925 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8926 { 8927 struct bce_softc *sc = (struct bce_softc *)arg1; 8928 int error; 8929 u32 result; 8930 u32 val[1]; 8931 u8 *data = (u8 *) val; 8932 8933 result = -1; 8934 error = sysctl_handle_int(oidp, &result, 0, req); 8935 if (error || (req->newptr == NULL)) 8936 return (error); 8937 8938 error = bce_nvram_read(sc, result, data, 4); 8939 8940 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8941 8942 return (error); 8943 } 8944 8945 8946 /****************************************************************************/ 8947 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8948 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8949 /* */ 8950 /* Returns: */ 8951 /* 0 for success, positive value for failure. */ 8952 /****************************************************************************/ 8953 static int 8954 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8955 { 8956 struct bce_softc *sc = (struct bce_softc *)arg1; 8957 int error; 8958 u32 val, result; 8959 8960 result = -1; 8961 error = sysctl_handle_int(oidp, &result, 0, req); 8962 if (error || (req->newptr == NULL)) 8963 return (error); 8964 8965 /* Make sure the register is accessible. */ 8966 if (result < 0x8000) { 8967 val = REG_RD(sc, result); 8968 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8969 } else if (result < 0x0280000) { 8970 val = REG_RD_IND(sc, result); 8971 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8972 } 8973 8974 return (error); 8975 } 8976 8977 8978 /****************************************************************************/ 8979 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8980 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8981 /* */ 8982 /* Returns: */ 8983 /* 0 for success, positive value for failure. */ 8984 /****************************************************************************/ 8985 static int 8986 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8987 { 8988 struct bce_softc *sc; 8989 device_t dev; 8990 int error, result; 8991 u16 val; 8992 8993 result = -1; 8994 error = sysctl_handle_int(oidp, &result, 0, req); 8995 if (error || (req->newptr == NULL)) 8996 return (error); 8997 8998 /* Make sure the register is accessible. */ 8999 if (result < 0x20) { 9000 sc = (struct bce_softc *)arg1; 9001 dev = sc->bce_dev; 9002 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 9003 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 9004 } 9005 return (error); 9006 } 9007 9008 9009 /****************************************************************************/ 9010 /* Provides a sysctl interface for dumping the nvram contents. */ 9011 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9012 /* */ 9013 /* Returns: */ 9014 /* 0 for success, positive errno for failure. */ 9015 /****************************************************************************/ 9016 static int 9017 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 9018 { 9019 struct bce_softc *sc = (struct bce_softc *)arg1; 9020 int error, i; 9021 9022 if (sc->nvram_buf == NULL) 9023 sc->nvram_buf = malloc(sc->bce_flash_size, 9024 M_TEMP, M_ZERO | M_WAITOK); 9025 9026 error = 0; 9027 if (req->oldlen == sc->bce_flash_size) { 9028 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 9029 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9030 } 9031 9032 if (error == 0) 9033 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9034 9035 return error; 9036 } 9037 9038 #ifdef BCE_NVRAM_WRITE_SUPPORT 9039 /****************************************************************************/ 9040 /* Provides a sysctl interface for writing to nvram. */ 9041 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9042 /* */ 9043 /* Returns: */ 9044 /* 0 for success, positive errno for failure. */ 9045 /****************************************************************************/ 9046 static int 9047 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9048 { 9049 struct bce_softc *sc = (struct bce_softc *)arg1; 9050 int error; 9051 9052 if (sc->nvram_buf == NULL) 9053 sc->nvram_buf = malloc(sc->bce_flash_size, 9054 M_TEMP, M_ZERO | M_WAITOK); 9055 else 9056 bzero(sc->nvram_buf, sc->bce_flash_size); 9057 9058 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9059 if (error == 0) 9060 return (error); 9061 9062 if (req->newlen == sc->bce_flash_size) 9063 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9064 sc->bce_flash_size); 9065 9066 9067 return error; 9068 } 9069 #endif 9070 9071 9072 /****************************************************************************/ 9073 /* Provides a sysctl interface to allow reading a CID. */ 9074 /* */ 9075 /* Returns: */ 9076 /* 0 for success, positive value for failure. */ 9077 /****************************************************************************/ 9078 static int 9079 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9080 { 9081 struct bce_softc *sc; 9082 int error, result; 9083 9084 result = -1; 9085 error = sysctl_handle_int(oidp, &result, 0, req); 9086 if (error || (req->newptr == NULL)) 9087 return (error); 9088 9089 /* Make sure the register is accessible. */ 9090 if (result <= TX_CID) { 9091 sc = (struct bce_softc *)arg1; 9092 bce_dump_ctx(sc, result); 9093 } 9094 9095 return (error); 9096 } 9097 9098 9099 /****************************************************************************/ 9100 /* Provides a sysctl interface to forcing the driver to dump state and */ 9101 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9102 /* */ 9103 /* Returns: */ 9104 /* 0 for success, positive value for failure. */ 9105 /****************************************************************************/ 9106 static int 9107 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9108 { 9109 int error; 9110 int result; 9111 struct bce_softc *sc; 9112 9113 result = -1; 9114 error = sysctl_handle_int(oidp, &result, 0, req); 9115 9116 if (error || !req->newptr) 9117 return (error); 9118 9119 if (result == 1) { 9120 sc = (struct bce_softc *)arg1; 9121 bce_breakpoint(sc); 9122 } 9123 9124 return error; 9125 } 9126 #endif 9127 9128 /****************************************************************************/ 9129 /* Adds any sysctl parameters for tuning or debugging purposes. */ 9130 /* */ 9131 /* Returns: */ 9132 /* 0 for success, positive value for failure. */ 9133 /****************************************************************************/ 9134 static void 9135 bce_add_sysctls(struct bce_softc *sc) 9136 { 9137 struct sysctl_ctx_list *ctx; 9138 struct sysctl_oid_list *children; 9139 9140 DBENTER(BCE_VERBOSE_MISC); 9141 9142 ctx = device_get_sysctl_ctx(sc->bce_dev); 9143 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9144 9145 #ifdef BCE_DEBUG 9146 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9147 "l2fhdr_error_sim_control", 9148 CTLFLAG_RW, &l2fhdr_error_sim_control, 9149 0, "Debug control to force l2fhdr errors"); 9150 9151 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9152 "l2fhdr_error_sim_count", 9153 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9154 0, "Number of simulated l2_fhdr errors"); 9155 #endif 9156 9157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9158 "l2fhdr_error_count", 9159 CTLFLAG_RD, &sc->l2fhdr_error_count, 9160 0, "Number of l2_fhdr errors"); 9161 9162 #ifdef BCE_DEBUG 9163 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9164 "mbuf_alloc_failed_sim_control", 9165 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9166 0, "Debug control to force mbuf allocation failures"); 9167 9168 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9169 "mbuf_alloc_failed_sim_count", 9170 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9171 0, "Number of simulated mbuf cluster allocation failures"); 9172 #endif 9173 9174 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9175 "mbuf_alloc_failed_count", 9176 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9177 0, "Number of mbuf allocation failures"); 9178 9179 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9180 "mbuf_frag_count", 9181 CTLFLAG_RD, &sc->mbuf_frag_count, 9182 0, "Number of fragmented mbufs"); 9183 9184 #ifdef BCE_DEBUG 9185 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9186 "dma_map_addr_failed_sim_control", 9187 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9188 0, "Debug control to force DMA mapping failures"); 9189 9190 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9191 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9192 "dma_map_addr_failed_sim_count", 9193 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9194 0, "Number of simulated DMA mapping failures"); 9195 9196 #endif 9197 9198 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9199 "dma_map_addr_rx_failed_count", 9200 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9201 0, "Number of RX DMA mapping failures"); 9202 9203 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9204 "dma_map_addr_tx_failed_count", 9205 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9206 0, "Number of TX DMA mapping failures"); 9207 9208 #ifdef BCE_DEBUG 9209 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9210 "unexpected_attention_sim_control", 9211 CTLFLAG_RW, &unexpected_attention_sim_control, 9212 0, "Debug control to simulate unexpected attentions"); 9213 9214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9215 "unexpected_attention_sim_count", 9216 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9217 0, "Number of simulated unexpected attentions"); 9218 #endif 9219 9220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9221 "unexpected_attention_count", 9222 CTLFLAG_RW, &sc->unexpected_attention_count, 9223 0, "Number of unexpected attentions"); 9224 9225 #ifdef BCE_DEBUG 9226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9227 "debug_bootcode_running_failure", 9228 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9229 0, "Debug control to force bootcode running failures"); 9230 9231 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9232 "rx_low_watermark", 9233 CTLFLAG_RD, &sc->rx_low_watermark, 9234 0, "Lowest level of free rx_bd's"); 9235 9236 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9237 "rx_empty_count", 9238 CTLFLAG_RD, &sc->rx_empty_count, 9239 "Number of times the RX chain was empty"); 9240 9241 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9242 "tx_hi_watermark", 9243 CTLFLAG_RD, &sc->tx_hi_watermark, 9244 0, "Highest level of used tx_bd's"); 9245 9246 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9247 "tx_full_count", 9248 CTLFLAG_RD, &sc->tx_full_count, 9249 "Number of times the TX chain was full"); 9250 9251 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9252 "tso_frames_requested", 9253 CTLFLAG_RD, &sc->tso_frames_requested, 9254 "Number of TSO frames requested"); 9255 9256 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9257 "tso_frames_completed", 9258 CTLFLAG_RD, &sc->tso_frames_completed, 9259 "Number of TSO frames completed"); 9260 9261 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9262 "tso_frames_failed", 9263 CTLFLAG_RD, &sc->tso_frames_failed, 9264 "Number of TSO frames failed"); 9265 9266 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9267 "csum_offload_ip", 9268 CTLFLAG_RD, &sc->csum_offload_ip, 9269 "Number of IP checksum offload frames"); 9270 9271 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9272 "csum_offload_tcp_udp", 9273 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9274 "Number of TCP/UDP checksum offload frames"); 9275 9276 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9277 "vlan_tagged_frames_rcvd", 9278 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9279 "Number of VLAN tagged frames received"); 9280 9281 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9282 "vlan_tagged_frames_stripped", 9283 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9284 "Number of VLAN tagged frames stripped"); 9285 9286 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9287 "interrupts_rx", 9288 CTLFLAG_RD, &sc->interrupts_rx, 9289 "Number of RX interrupts"); 9290 9291 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9292 "interrupts_tx", 9293 CTLFLAG_RD, &sc->interrupts_tx, 9294 "Number of TX interrupts"); 9295 9296 if (bce_hdr_split == TRUE) { 9297 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9298 "split_header_frames_rcvd", 9299 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9300 "Number of split header frames received"); 9301 9302 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9303 "split_header_tcp_frames_rcvd", 9304 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9305 "Number of split header TCP frames received"); 9306 } 9307 9308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9309 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9310 (void *)sc, 0, 9311 bce_sysctl_nvram_dump, "S", ""); 9312 9313 #ifdef BCE_NVRAM_WRITE_SUPPORT 9314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9315 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9316 (void *)sc, 0, 9317 bce_sysctl_nvram_write, "S", ""); 9318 #endif 9319 #endif /* BCE_DEBUG */ 9320 9321 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9322 "stat_IfHcInOctets", 9323 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9324 "Bytes received"); 9325 9326 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9327 "stat_IfHCInBadOctets", 9328 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9329 "Bad bytes received"); 9330 9331 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9332 "stat_IfHCOutOctets", 9333 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9334 "Bytes sent"); 9335 9336 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9337 "stat_IfHCOutBadOctets", 9338 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9339 "Bad bytes sent"); 9340 9341 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9342 "stat_IfHCInUcastPkts", 9343 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9344 "Unicast packets received"); 9345 9346 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9347 "stat_IfHCInMulticastPkts", 9348 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9349 "Multicast packets received"); 9350 9351 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9352 "stat_IfHCInBroadcastPkts", 9353 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9354 "Broadcast packets received"); 9355 9356 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9357 "stat_IfHCOutUcastPkts", 9358 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9359 "Unicast packets sent"); 9360 9361 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9362 "stat_IfHCOutMulticastPkts", 9363 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9364 "Multicast packets sent"); 9365 9366 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9367 "stat_IfHCOutBroadcastPkts", 9368 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9369 "Broadcast packets sent"); 9370 9371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9372 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9373 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9374 0, "Internal MAC transmit errors"); 9375 9376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9377 "stat_Dot3StatsCarrierSenseErrors", 9378 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9379 0, "Carrier sense errors"); 9380 9381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9382 "stat_Dot3StatsFCSErrors", 9383 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9384 0, "Frame check sequence errors"); 9385 9386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9387 "stat_Dot3StatsAlignmentErrors", 9388 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9389 0, "Alignment errors"); 9390 9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9392 "stat_Dot3StatsSingleCollisionFrames", 9393 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9394 0, "Single Collision Frames"); 9395 9396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9397 "stat_Dot3StatsMultipleCollisionFrames", 9398 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9399 0, "Multiple Collision Frames"); 9400 9401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9402 "stat_Dot3StatsDeferredTransmissions", 9403 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9404 0, "Deferred Transmissions"); 9405 9406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9407 "stat_Dot3StatsExcessiveCollisions", 9408 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9409 0, "Excessive Collisions"); 9410 9411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9412 "stat_Dot3StatsLateCollisions", 9413 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9414 0, "Late Collisions"); 9415 9416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9417 "stat_EtherStatsCollisions", 9418 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9419 0, "Collisions"); 9420 9421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9422 "stat_EtherStatsFragments", 9423 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9424 0, "Fragments"); 9425 9426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9427 "stat_EtherStatsJabbers", 9428 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9429 0, "Jabbers"); 9430 9431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9432 "stat_EtherStatsUndersizePkts", 9433 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9434 0, "Undersize packets"); 9435 9436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9437 "stat_EtherStatsOversizePkts", 9438 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9439 0, "stat_EtherStatsOversizePkts"); 9440 9441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9442 "stat_EtherStatsPktsRx64Octets", 9443 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9444 0, "Bytes received in 64 byte packets"); 9445 9446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9447 "stat_EtherStatsPktsRx65Octetsto127Octets", 9448 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9449 0, "Bytes received in 65 to 127 byte packets"); 9450 9451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9452 "stat_EtherStatsPktsRx128Octetsto255Octets", 9453 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9454 0, "Bytes received in 128 to 255 byte packets"); 9455 9456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9457 "stat_EtherStatsPktsRx256Octetsto511Octets", 9458 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9459 0, "Bytes received in 256 to 511 byte packets"); 9460 9461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9462 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9463 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9464 0, "Bytes received in 512 to 1023 byte packets"); 9465 9466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9467 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9468 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9469 0, "Bytes received in 1024 t0 1522 byte packets"); 9470 9471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9472 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9473 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9474 0, "Bytes received in 1523 to 9022 byte packets"); 9475 9476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9477 "stat_EtherStatsPktsTx64Octets", 9478 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9479 0, "Bytes sent in 64 byte packets"); 9480 9481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9482 "stat_EtherStatsPktsTx65Octetsto127Octets", 9483 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9484 0, "Bytes sent in 65 to 127 byte packets"); 9485 9486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9487 "stat_EtherStatsPktsTx128Octetsto255Octets", 9488 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9489 0, "Bytes sent in 128 to 255 byte packets"); 9490 9491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9492 "stat_EtherStatsPktsTx256Octetsto511Octets", 9493 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9494 0, "Bytes sent in 256 to 511 byte packets"); 9495 9496 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9497 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9498 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9499 0, "Bytes sent in 512 to 1023 byte packets"); 9500 9501 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9502 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9503 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9504 0, "Bytes sent in 1024 to 1522 byte packets"); 9505 9506 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9507 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9508 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9509 0, "Bytes sent in 1523 to 9022 byte packets"); 9510 9511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9512 "stat_XonPauseFramesReceived", 9513 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9514 0, "XON pause frames receved"); 9515 9516 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9517 "stat_XoffPauseFramesReceived", 9518 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9519 0, "XOFF pause frames received"); 9520 9521 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9522 "stat_OutXonSent", 9523 CTLFLAG_RD, &sc->stat_OutXonSent, 9524 0, "XON pause frames sent"); 9525 9526 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9527 "stat_OutXoffSent", 9528 CTLFLAG_RD, &sc->stat_OutXoffSent, 9529 0, "XOFF pause frames sent"); 9530 9531 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9532 "stat_FlowControlDone", 9533 CTLFLAG_RD, &sc->stat_FlowControlDone, 9534 0, "Flow control done"); 9535 9536 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9537 "stat_MacControlFramesReceived", 9538 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9539 0, "MAC control frames received"); 9540 9541 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9542 "stat_XoffStateEntered", 9543 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9544 0, "XOFF state entered"); 9545 9546 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9547 "stat_IfInFramesL2FilterDiscards", 9548 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9549 0, "Received L2 packets discarded"); 9550 9551 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9552 "stat_IfInRuleCheckerDiscards", 9553 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9554 0, "Received packets discarded by rule"); 9555 9556 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9557 "stat_IfInFTQDiscards", 9558 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9559 0, "Received packet FTQ discards"); 9560 9561 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9562 "stat_IfInMBUFDiscards", 9563 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9564 0, "Received packets discarded due to lack " 9565 "of controller buffer memory"); 9566 9567 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9568 "stat_IfInRuleCheckerP4Hit", 9569 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9570 0, "Received packets rule checker hits"); 9571 9572 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9573 "stat_CatchupInRuleCheckerDiscards", 9574 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9575 0, "Received packets discarded in Catchup path"); 9576 9577 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9578 "stat_CatchupInFTQDiscards", 9579 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9580 0, "Received packets discarded in FTQ in Catchup path"); 9581 9582 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9583 "stat_CatchupInMBUFDiscards", 9584 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9585 0, "Received packets discarded in controller " 9586 "buffer memory in Catchup path"); 9587 9588 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9589 "stat_CatchupInRuleCheckerP4Hit", 9590 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9591 0, "Received packets rule checker hits in Catchup path"); 9592 9593 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9594 "com_no_buffers", 9595 CTLFLAG_RD, &sc->com_no_buffers, 9596 0, "Valid packets received but no RX buffers available"); 9597 9598 #ifdef BCE_DEBUG 9599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9600 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9601 (void *)sc, 0, 9602 bce_sysctl_driver_state, "I", "Drive state information"); 9603 9604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9605 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9606 (void *)sc, 0, 9607 bce_sysctl_hw_state, "I", "Hardware state information"); 9608 9609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9610 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9611 (void *)sc, 0, 9612 bce_sysctl_status_block, "I", "Dump status block"); 9613 9614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9615 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9616 (void *)sc, 0, 9617 bce_sysctl_stats_block, "I", "Dump statistics block"); 9618 9619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9620 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9621 (void *)sc, 0, 9622 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9623 9624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9625 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9626 (void *)sc, 0, 9627 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9628 9629 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9630 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9631 (void *)sc, 0, 9632 bce_sysctl_bc_state, "I", "Bootcode state information"); 9633 9634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9635 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9636 (void *)sc, 0, 9637 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9638 9639 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9640 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9641 (void *)sc, 0, 9642 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9643 9644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9645 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9646 (void *)sc, 0, 9647 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9648 9649 if (bce_hdr_split == TRUE) { 9650 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9651 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9652 (void *)sc, 0, 9653 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9654 } 9655 9656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9657 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9658 (void *)sc, 0, 9659 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9660 9661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9662 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9663 (void *)sc, 0, 9664 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9665 9666 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9667 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9668 (void *)sc, 0, 9669 bce_sysctl_reg_read, "I", "Register read"); 9670 9671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9672 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9673 (void *)sc, 0, 9674 bce_sysctl_nvram_read, "I", "NVRAM read"); 9675 9676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9677 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9678 (void *)sc, 0, 9679 bce_sysctl_phy_read, "I", "PHY register read"); 9680 9681 #endif 9682 9683 DBEXIT(BCE_VERBOSE_MISC); 9684 } 9685 9686 9687 /****************************************************************************/ 9688 /* BCE Debug Routines */ 9689 /****************************************************************************/ 9690 #ifdef BCE_DEBUG 9691 9692 /****************************************************************************/ 9693 /* Freezes the controller to allow for a cohesive state dump. */ 9694 /* */ 9695 /* Returns: */ 9696 /* Nothing. */ 9697 /****************************************************************************/ 9698 static __attribute__ ((noinline)) void 9699 bce_freeze_controller(struct bce_softc *sc) 9700 { 9701 u32 val; 9702 val = REG_RD(sc, BCE_MISC_COMMAND); 9703 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9704 REG_WR(sc, BCE_MISC_COMMAND, val); 9705 } 9706 9707 9708 /****************************************************************************/ 9709 /* Unfreezes the controller after a freeze operation. This may not always */ 9710 /* work and the controller will require a reset! */ 9711 /* */ 9712 /* Returns: */ 9713 /* Nothing. */ 9714 /****************************************************************************/ 9715 static __attribute__ ((noinline)) void 9716 bce_unfreeze_controller(struct bce_softc *sc) 9717 { 9718 u32 val; 9719 val = REG_RD(sc, BCE_MISC_COMMAND); 9720 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9721 REG_WR(sc, BCE_MISC_COMMAND, val); 9722 } 9723 9724 9725 /****************************************************************************/ 9726 /* Prints out Ethernet frame information from an mbuf. */ 9727 /* */ 9728 /* Partially decode an Ethernet frame to look at some important headers. */ 9729 /* */ 9730 /* Returns: */ 9731 /* Nothing. */ 9732 /****************************************************************************/ 9733 static __attribute__ ((noinline)) void 9734 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9735 { 9736 struct ether_vlan_header *eh; 9737 u16 etype; 9738 int ehlen; 9739 struct ip *ip; 9740 struct tcphdr *th; 9741 struct udphdr *uh; 9742 struct arphdr *ah; 9743 9744 BCE_PRINTF( 9745 "-----------------------------" 9746 " Frame Decode " 9747 "-----------------------------\n"); 9748 9749 eh = mtod(m, struct ether_vlan_header *); 9750 9751 /* Handle VLAN encapsulation if present. */ 9752 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9753 etype = ntohs(eh->evl_proto); 9754 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9755 } else { 9756 etype = ntohs(eh->evl_encap_proto); 9757 ehlen = ETHER_HDR_LEN; 9758 } 9759 9760 /* ToDo: Add VLAN output. */ 9761 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9762 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9763 9764 switch (etype) { 9765 case ETHERTYPE_IP: 9766 ip = (struct ip *)(m->m_data + ehlen); 9767 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9768 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9769 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9770 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9771 9772 switch (ip->ip_p) { 9773 case IPPROTO_TCP: 9774 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9775 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9776 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9777 ntohs(th->th_dport), ntohs(th->th_sport), 9778 (th->th_off << 2), th->th_flags, 9779 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9780 "\02SYN\01FIN", ntohs(th->th_sum)); 9781 break; 9782 case IPPROTO_UDP: 9783 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9784 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9785 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9786 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9787 ntohs(uh->uh_sum)); 9788 break; 9789 case IPPROTO_ICMP: 9790 BCE_PRINTF("icmp:\n"); 9791 break; 9792 default: 9793 BCE_PRINTF("----: Other IP protocol.\n"); 9794 } 9795 break; 9796 case ETHERTYPE_IPV6: 9797 BCE_PRINTF("ipv6: No decode supported.\n"); 9798 break; 9799 case ETHERTYPE_ARP: 9800 BCE_PRINTF("-arp: "); 9801 ah = (struct arphdr *) (m->m_data + ehlen); 9802 switch (ntohs(ah->ar_op)) { 9803 case ARPOP_REVREQUEST: 9804 printf("reverse ARP request\n"); 9805 break; 9806 case ARPOP_REVREPLY: 9807 printf("reverse ARP reply\n"); 9808 break; 9809 case ARPOP_REQUEST: 9810 printf("ARP request\n"); 9811 break; 9812 case ARPOP_REPLY: 9813 printf("ARP reply\n"); 9814 break; 9815 default: 9816 printf("other ARP operation\n"); 9817 } 9818 break; 9819 default: 9820 BCE_PRINTF("----: Other protocol.\n"); 9821 } 9822 9823 BCE_PRINTF( 9824 "-----------------------------" 9825 "--------------" 9826 "-----------------------------\n"); 9827 } 9828 9829 9830 /****************************************************************************/ 9831 /* Prints out information about an mbuf. */ 9832 /* */ 9833 /* Returns: */ 9834 /* Nothing. */ 9835 /****************************************************************************/ 9836 static __attribute__ ((noinline)) void 9837 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9838 { 9839 struct mbuf *mp = m; 9840 9841 if (m == NULL) { 9842 BCE_PRINTF("mbuf: null pointer\n"); 9843 return; 9844 } 9845 9846 while (mp) { 9847 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9848 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9849 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9850 9851 if (mp->m_flags & M_PKTHDR) { 9852 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9853 "csum_flags = %b\n", mp->m_pkthdr.len, 9854 mp->m_flags, M_FLAG_PRINTF, 9855 mp->m_pkthdr.csum_flags, 9856 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP" 9857 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9858 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9859 "\14CSUM_PSEUDO_HDR"); 9860 } 9861 9862 if (mp->m_flags & M_EXT) { 9863 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9864 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9865 switch (mp->m_ext.ext_type) { 9866 case EXT_CLUSTER: 9867 printf("EXT_CLUSTER\n"); break; 9868 case EXT_SFBUF: 9869 printf("EXT_SFBUF\n"); break; 9870 case EXT_JUMBO9: 9871 printf("EXT_JUMBO9\n"); break; 9872 case EXT_JUMBO16: 9873 printf("EXT_JUMBO16\n"); break; 9874 case EXT_PACKET: 9875 printf("EXT_PACKET\n"); break; 9876 case EXT_MBUF: 9877 printf("EXT_MBUF\n"); break; 9878 case EXT_NET_DRV: 9879 printf("EXT_NET_DRV\n"); break; 9880 case EXT_MOD_TYPE: 9881 printf("EXT_MDD_TYPE\n"); break; 9882 case EXT_DISPOSABLE: 9883 printf("EXT_DISPOSABLE\n"); break; 9884 case EXT_EXTREF: 9885 printf("EXT_EXTREF\n"); break; 9886 default: 9887 printf("UNKNOWN\n"); 9888 } 9889 } 9890 9891 mp = mp->m_next; 9892 } 9893 } 9894 9895 9896 /****************************************************************************/ 9897 /* Prints out the mbufs in the TX mbuf chain. */ 9898 /* */ 9899 /* Returns: */ 9900 /* Nothing. */ 9901 /****************************************************************************/ 9902 static __attribute__ ((noinline)) void 9903 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9904 { 9905 struct mbuf *m; 9906 9907 BCE_PRINTF( 9908 "----------------------------" 9909 " tx mbuf data " 9910 "----------------------------\n"); 9911 9912 for (int i = 0; i < count; i++) { 9913 m = sc->tx_mbuf_ptr[chain_prod]; 9914 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9915 bce_dump_mbuf(sc, m); 9916 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9917 } 9918 9919 BCE_PRINTF( 9920 "----------------------------" 9921 "----------------" 9922 "----------------------------\n"); 9923 } 9924 9925 9926 /****************************************************************************/ 9927 /* Prints out the mbufs in the RX mbuf chain. */ 9928 /* */ 9929 /* Returns: */ 9930 /* Nothing. */ 9931 /****************************************************************************/ 9932 static __attribute__ ((noinline)) void 9933 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9934 { 9935 struct mbuf *m; 9936 9937 BCE_PRINTF( 9938 "----------------------------" 9939 " rx mbuf data " 9940 "----------------------------\n"); 9941 9942 for (int i = 0; i < count; i++) { 9943 m = sc->rx_mbuf_ptr[chain_prod]; 9944 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9945 bce_dump_mbuf(sc, m); 9946 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9947 } 9948 9949 9950 BCE_PRINTF( 9951 "----------------------------" 9952 "----------------" 9953 "----------------------------\n"); 9954 } 9955 9956 9957 /****************************************************************************/ 9958 /* Prints out the mbufs in the mbuf page chain. */ 9959 /* */ 9960 /* Returns: */ 9961 /* Nothing. */ 9962 /****************************************************************************/ 9963 static __attribute__ ((noinline)) void 9964 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9965 { 9966 struct mbuf *m; 9967 9968 BCE_PRINTF( 9969 "----------------------------" 9970 " pg mbuf data " 9971 "----------------------------\n"); 9972 9973 for (int i = 0; i < count; i++) { 9974 m = sc->pg_mbuf_ptr[chain_prod]; 9975 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9976 bce_dump_mbuf(sc, m); 9977 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9978 } 9979 9980 9981 BCE_PRINTF( 9982 "----------------------------" 9983 "----------------" 9984 "----------------------------\n"); 9985 } 9986 9987 9988 /****************************************************************************/ 9989 /* Prints out a tx_bd structure. */ 9990 /* */ 9991 /* Returns: */ 9992 /* Nothing. */ 9993 /****************************************************************************/ 9994 static __attribute__ ((noinline)) void 9995 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9996 { 9997 int i = 0; 9998 9999 if (idx > MAX_TX_BD_ALLOC) 10000 /* Index out of range. */ 10001 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 10002 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 10003 /* TX Chain page pointer. */ 10004 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10005 "pointer\n", idx, txbd->tx_bd_haddr_hi, 10006 txbd->tx_bd_haddr_lo); 10007 else { 10008 /* Normal tx_bd entry. */ 10009 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 10010 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 10011 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 10012 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 10013 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 10014 10015 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 10016 if (i>0) 10017 printf("|"); 10018 printf("CONN_FAULT"); 10019 i++; 10020 } 10021 10022 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 10023 if (i>0) 10024 printf("|"); 10025 printf("TCP_UDP_CKSUM"); 10026 i++; 10027 } 10028 10029 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10030 if (i>0) 10031 printf("|"); 10032 printf("IP_CKSUM"); 10033 i++; 10034 } 10035 10036 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10037 if (i>0) 10038 printf("|"); 10039 printf("VLAN"); 10040 i++; 10041 } 10042 10043 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10044 if (i>0) 10045 printf("|"); 10046 printf("COAL_NOW"); 10047 i++; 10048 } 10049 10050 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10051 if (i>0) 10052 printf("|"); 10053 printf("DONT_GEN_CRC"); 10054 i++; 10055 } 10056 10057 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10058 if (i>0) 10059 printf("|"); 10060 printf("START"); 10061 i++; 10062 } 10063 10064 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10065 if (i>0) 10066 printf("|"); 10067 printf("END"); 10068 i++; 10069 } 10070 10071 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10072 if (i>0) 10073 printf("|"); 10074 printf("LSO"); 10075 i++; 10076 } 10077 10078 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10079 if (i>0) 10080 printf("|"); 10081 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10082 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10083 } 10084 10085 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10086 if (i>0) 10087 printf("|"); 10088 printf("SW_FLAGS"); 10089 i++; 10090 } 10091 10092 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10093 if (i>0) 10094 printf("|"); 10095 printf("SNAP)"); 10096 } else { 10097 printf(")\n"); 10098 } 10099 } 10100 } 10101 10102 10103 /****************************************************************************/ 10104 /* Prints out a rx_bd structure. */ 10105 /* */ 10106 /* Returns: */ 10107 /* Nothing. */ 10108 /****************************************************************************/ 10109 static __attribute__ ((noinline)) void 10110 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10111 { 10112 if (idx > MAX_RX_BD_ALLOC) 10113 /* Index out of range. */ 10114 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10115 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10116 /* RX Chain page pointer. */ 10117 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10118 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10119 rxbd->rx_bd_haddr_lo); 10120 else 10121 /* Normal rx_bd entry. */ 10122 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10123 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10124 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10125 rxbd->rx_bd_flags); 10126 } 10127 10128 10129 /****************************************************************************/ 10130 /* Prints out a rx_bd structure in the page chain. */ 10131 /* */ 10132 /* Returns: */ 10133 /* Nothing. */ 10134 /****************************************************************************/ 10135 static __attribute__ ((noinline)) void 10136 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10137 { 10138 if (idx > MAX_PG_BD_ALLOC) 10139 /* Index out of range. */ 10140 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10141 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10142 /* Page Chain page pointer. */ 10143 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10144 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10145 else 10146 /* Normal rx_bd entry. */ 10147 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10148 "flags = 0x%08X\n", idx, 10149 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10150 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10151 } 10152 10153 10154 /****************************************************************************/ 10155 /* Prints out a l2_fhdr structure. */ 10156 /* */ 10157 /* Returns: */ 10158 /* Nothing. */ 10159 /****************************************************************************/ 10160 static __attribute__ ((noinline)) void 10161 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10162 { 10163 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10164 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10165 "tcp_udp_xsum = 0x%04X\n", idx, 10166 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10167 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10168 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10169 } 10170 10171 10172 /****************************************************************************/ 10173 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10174 /* */ 10175 /* Returns: */ 10176 /* Nothing. */ 10177 /****************************************************************************/ 10178 static __attribute__ ((noinline)) void 10179 bce_dump_ctx(struct bce_softc *sc, u16 cid) 10180 { 10181 if (cid > TX_CID) { 10182 BCE_PRINTF(" Unknown CID\n"); 10183 return; 10184 } 10185 10186 BCE_PRINTF( 10187 "----------------------------" 10188 " CTX Data " 10189 "----------------------------\n"); 10190 10191 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10192 10193 if (cid == RX_CID) { 10194 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10195 "producer index\n", 10196 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10197 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10198 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10199 BCE_L2CTX_RX_HOST_BSEQ)); 10200 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10201 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10202 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10203 "descriptor address\n", 10204 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10205 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10206 "descriptor address\n", 10207 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10208 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10209 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10210 BCE_L2CTX_RX_NX_BDIDX)); 10211 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10212 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10213 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10214 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10215 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10216 BCE_L2CTX_RX_PG_BUF_SIZE)); 10217 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10218 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10219 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10220 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10221 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10222 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10223 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10224 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10225 BCE_L2CTX_RX_NX_PG_BDIDX)); 10226 } else if (cid == TX_CID) { 10227 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10228 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10229 CTX_RD(sc, GET_CID_ADDR(cid), 10230 BCE_L2CTX_TX_TYPE_XI)); 10231 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10232 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10233 BCE_L2CTX_TX_CMD_TYPE_XI)); 10234 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10235 "h/w buffer descriptor address\n", 10236 CTX_RD(sc, GET_CID_ADDR(cid), 10237 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10238 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10239 "h/w buffer descriptor address\n", 10240 CTX_RD(sc, GET_CID_ADDR(cid), 10241 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10242 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10243 "host producer index\n", 10244 CTX_RD(sc, GET_CID_ADDR(cid), 10245 BCE_L2CTX_TX_HOST_BIDX_XI)); 10246 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10247 "host byte sequence\n", 10248 CTX_RD(sc, GET_CID_ADDR(cid), 10249 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10250 } else { 10251 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10252 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10253 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10254 CTX_RD(sc, GET_CID_ADDR(cid), 10255 BCE_L2CTX_TX_CMD_TYPE)); 10256 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10257 "h/w buffer descriptor address\n", 10258 CTX_RD(sc, GET_CID_ADDR(cid), 10259 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10260 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10261 "h/w buffer descriptor address\n", 10262 CTX_RD(sc, GET_CID_ADDR(cid), 10263 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10264 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10265 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10266 BCE_L2CTX_TX_HOST_BIDX)); 10267 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10268 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10269 BCE_L2CTX_TX_HOST_BSEQ)); 10270 } 10271 } 10272 10273 BCE_PRINTF( 10274 "----------------------------" 10275 " Raw CTX " 10276 "----------------------------\n"); 10277 10278 for (int i = 0x0; i < 0x300; i += 0x10) { 10279 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10280 CTX_RD(sc, GET_CID_ADDR(cid), i), 10281 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10282 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10283 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10284 } 10285 10286 10287 BCE_PRINTF( 10288 "----------------------------" 10289 "----------------" 10290 "----------------------------\n"); 10291 } 10292 10293 10294 /****************************************************************************/ 10295 /* Prints out the FTQ data. */ 10296 /* */ 10297 /* Returns: */ 10298 /* Nothing. */ 10299 /****************************************************************************/ 10300 static __attribute__ ((noinline)) void 10301 bce_dump_ftqs(struct bce_softc *sc) 10302 { 10303 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10304 10305 BCE_PRINTF( 10306 "----------------------------" 10307 " FTQ Data " 10308 "----------------------------\n"); 10309 10310 BCE_PRINTF(" FTQ Command Control Depth_Now " 10311 "Max_Depth Valid_Cnt \n"); 10312 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10313 "---------- ----------\n"); 10314 10315 /* Setup the generic statistic counters for the FTQ valid count. */ 10316 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10317 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10318 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10319 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10320 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10321 10322 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10323 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10324 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10325 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10326 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10327 10328 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10329 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10330 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10331 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10332 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10333 10334 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10335 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10336 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10337 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10338 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10339 10340 /* Input queue to the Receive Lookup state machine */ 10341 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10342 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10343 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10344 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10345 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10346 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10347 cmd, ctl, cur_depth, max_depth, valid_cnt); 10348 10349 /* Input queue to the Receive Processor */ 10350 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10351 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10352 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10353 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10354 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10355 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10356 cmd, ctl, cur_depth, max_depth, valid_cnt); 10357 10358 /* Input queue to the Recevie Processor */ 10359 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10360 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10361 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10362 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10363 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10364 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10365 cmd, ctl, cur_depth, max_depth, valid_cnt); 10366 10367 /* Input queue to the Receive Virtual to Physical state machine */ 10368 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10369 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10370 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10371 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10372 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10373 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10374 cmd, ctl, cur_depth, max_depth, valid_cnt); 10375 10376 /* Input queue to the Recevie Virtual to Physical state machine */ 10377 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10378 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10379 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10380 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10381 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10382 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10383 cmd, ctl, cur_depth, max_depth, valid_cnt); 10384 10385 /* Input queue to the Receive Virtual to Physical state machine */ 10386 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10387 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10388 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10389 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10390 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10391 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10392 cmd, ctl, cur_depth, max_depth, valid_cnt); 10393 10394 /* Input queue to the Receive DMA state machine */ 10395 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10396 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10397 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10398 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10399 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10400 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10401 cmd, ctl, cur_depth, max_depth, valid_cnt); 10402 10403 /* Input queue to the Transmit Scheduler state machine */ 10404 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10405 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10406 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10407 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10408 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10409 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10410 cmd, ctl, cur_depth, max_depth, valid_cnt); 10411 10412 /* Input queue to the Transmit Buffer Descriptor state machine */ 10413 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10414 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10415 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10416 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10417 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10418 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10419 cmd, ctl, cur_depth, max_depth, valid_cnt); 10420 10421 /* Input queue to the Transmit Processor */ 10422 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10423 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10424 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10425 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10426 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10427 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10428 cmd, ctl, cur_depth, max_depth, valid_cnt); 10429 10430 /* Input queue to the Transmit DMA state machine */ 10431 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10432 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10433 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10434 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10435 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10436 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10437 cmd, ctl, cur_depth, max_depth, valid_cnt); 10438 10439 /* Input queue to the Transmit Patch-Up Processor */ 10440 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10441 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10442 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10443 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10444 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10445 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10446 cmd, ctl, cur_depth, max_depth, valid_cnt); 10447 10448 /* Input queue to the Transmit Assembler state machine */ 10449 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10450 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10451 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10452 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10453 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10454 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10455 cmd, ctl, cur_depth, max_depth, valid_cnt); 10456 10457 /* Input queue to the Completion Processor */ 10458 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10459 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10460 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10461 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10462 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10463 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10464 cmd, ctl, cur_depth, max_depth, valid_cnt); 10465 10466 /* Input queue to the Completion Processor */ 10467 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10468 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10469 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10470 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10471 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10472 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10473 cmd, ctl, cur_depth, max_depth, valid_cnt); 10474 10475 /* Input queue to the Completion Processor */ 10476 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10477 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10478 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10479 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10480 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10481 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10482 cmd, ctl, cur_depth, max_depth, valid_cnt); 10483 10484 /* Setup the generic statistic counters for the FTQ valid count. */ 10485 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10486 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10487 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10488 10489 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10490 val = val | 10491 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10492 24); 10493 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10494 10495 /* Input queue to the Management Control Processor */ 10496 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10497 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10498 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10499 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10500 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10501 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10502 cmd, ctl, cur_depth, max_depth, valid_cnt); 10503 10504 /* Input queue to the Command Processor */ 10505 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10506 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10507 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10508 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10509 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10510 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10511 cmd, ctl, cur_depth, max_depth, valid_cnt); 10512 10513 /* Input queue to the Completion Scheduler state machine */ 10514 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10515 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10516 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10517 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10518 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10519 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10520 cmd, ctl, cur_depth, max_depth, valid_cnt); 10521 10522 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10523 /* Input queue to the RV2P Command Scheduler */ 10524 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10525 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10526 cur_depth = (ctl & 0xFFC00000) >> 22; 10527 max_depth = (ctl & 0x003FF000) >> 12; 10528 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10529 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10530 cmd, ctl, cur_depth, max_depth, valid_cnt); 10531 } 10532 10533 BCE_PRINTF( 10534 "----------------------------" 10535 "----------------" 10536 "----------------------------\n"); 10537 } 10538 10539 10540 /****************************************************************************/ 10541 /* Prints out the TX chain. */ 10542 /* */ 10543 /* Returns: */ 10544 /* Nothing. */ 10545 /****************************************************************************/ 10546 static __attribute__ ((noinline)) void 10547 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10548 { 10549 struct tx_bd *txbd; 10550 10551 /* First some info about the tx_bd chain structure. */ 10552 BCE_PRINTF( 10553 "----------------------------" 10554 " tx_bd chain " 10555 "----------------------------\n"); 10556 10557 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10558 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10559 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10560 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10561 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10562 10563 BCE_PRINTF( 10564 "----------------------------" 10565 " tx_bd data " 10566 "----------------------------\n"); 10567 10568 /* Now print out a decoded list of TX buffer descriptors. */ 10569 for (int i = 0; i < count; i++) { 10570 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10571 bce_dump_txbd(sc, tx_prod, txbd); 10572 tx_prod++; 10573 } 10574 10575 BCE_PRINTF( 10576 "----------------------------" 10577 "----------------" 10578 "----------------------------\n"); 10579 } 10580 10581 10582 /****************************************************************************/ 10583 /* Prints out the RX chain. */ 10584 /* */ 10585 /* Returns: */ 10586 /* Nothing. */ 10587 /****************************************************************************/ 10588 static __attribute__ ((noinline)) void 10589 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10590 { 10591 struct rx_bd *rxbd; 10592 10593 /* First some info about the rx_bd chain structure. */ 10594 BCE_PRINTF( 10595 "----------------------------" 10596 " rx_bd chain " 10597 "----------------------------\n"); 10598 10599 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10600 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10601 10602 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10603 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10604 10605 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10606 10607 BCE_PRINTF( 10608 "----------------------------" 10609 " rx_bd data " 10610 "----------------------------\n"); 10611 10612 /* Now print out the rx_bd's themselves. */ 10613 for (int i = 0; i < count; i++) { 10614 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10615 bce_dump_rxbd(sc, rx_prod, rxbd); 10616 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10617 } 10618 10619 BCE_PRINTF( 10620 "----------------------------" 10621 "----------------" 10622 "----------------------------\n"); 10623 } 10624 10625 10626 /****************************************************************************/ 10627 /* Prints out the page chain. */ 10628 /* */ 10629 /* Returns: */ 10630 /* Nothing. */ 10631 /****************************************************************************/ 10632 static __attribute__ ((noinline)) void 10633 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10634 { 10635 struct rx_bd *pgbd; 10636 10637 /* First some info about the page chain structure. */ 10638 BCE_PRINTF( 10639 "----------------------------" 10640 " page chain " 10641 "----------------------------\n"); 10642 10643 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10644 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10645 10646 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10647 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10648 10649 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10650 10651 BCE_PRINTF( 10652 "----------------------------" 10653 " page data " 10654 "----------------------------\n"); 10655 10656 /* Now print out the rx_bd's themselves. */ 10657 for (int i = 0; i < count; i++) { 10658 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10659 bce_dump_pgbd(sc, pg_prod, pgbd); 10660 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10661 } 10662 10663 BCE_PRINTF( 10664 "----------------------------" 10665 "----------------" 10666 "----------------------------\n"); 10667 } 10668 10669 10670 #define BCE_PRINT_RX_CONS(arg) \ 10671 if (sblk->status_rx_quick_consumer_index##arg) \ 10672 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10673 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10674 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10675 arg); 10676 10677 10678 #define BCE_PRINT_TX_CONS(arg) \ 10679 if (sblk->status_tx_quick_consumer_index##arg) \ 10680 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10681 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10682 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10683 arg); 10684 10685 /****************************************************************************/ 10686 /* Prints out the status block from host memory. */ 10687 /* */ 10688 /* Returns: */ 10689 /* Nothing. */ 10690 /****************************************************************************/ 10691 static __attribute__ ((noinline)) void 10692 bce_dump_status_block(struct bce_softc *sc) 10693 { 10694 struct status_block *sblk; 10695 10696 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10697 10698 sblk = sc->status_block; 10699 10700 BCE_PRINTF( 10701 "----------------------------" 10702 " Status Block " 10703 "----------------------------\n"); 10704 10705 /* Theses indices are used for normal L2 drivers. */ 10706 BCE_PRINTF(" 0x%08X - attn_bits\n", 10707 sblk->status_attn_bits); 10708 10709 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10710 sblk->status_attn_bits_ack); 10711 10712 BCE_PRINT_RX_CONS(0); 10713 BCE_PRINT_TX_CONS(0) 10714 10715 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10716 10717 /* Theses indices are not used for normal L2 drivers. */ 10718 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10719 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10720 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10721 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10722 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10723 10724 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10725 10726 if (sblk->status_completion_producer_index || 10727 sblk->status_cmd_consumer_index) 10728 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10729 sblk->status_completion_producer_index, 10730 sblk->status_cmd_consumer_index); 10731 10732 BCE_PRINTF( 10733 "----------------------------" 10734 "----------------" 10735 "----------------------------\n"); 10736 } 10737 10738 10739 #define BCE_PRINT_64BIT_STAT(arg) \ 10740 if (sblk->arg##_lo || sblk->arg##_hi) \ 10741 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10742 sblk->arg##_lo, #arg); 10743 10744 #define BCE_PRINT_32BIT_STAT(arg) \ 10745 if (sblk->arg) \ 10746 BCE_PRINTF(" 0x%08X : %s\n", \ 10747 sblk->arg, #arg); 10748 10749 /****************************************************************************/ 10750 /* Prints out the statistics block from host memory. */ 10751 /* */ 10752 /* Returns: */ 10753 /* Nothing. */ 10754 /****************************************************************************/ 10755 static __attribute__ ((noinline)) void 10756 bce_dump_stats_block(struct bce_softc *sc) 10757 { 10758 struct statistics_block *sblk; 10759 10760 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10761 10762 sblk = sc->stats_block; 10763 10764 BCE_PRINTF( 10765 "---------------" 10766 " Stats Block (All Stats Not Shown Are 0) " 10767 "---------------\n"); 10768 10769 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10770 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10771 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10772 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10773 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10774 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10775 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10776 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10777 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10778 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10779 BCE_PRINT_32BIT_STAT( 10780 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10781 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10782 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10783 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10784 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10785 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10786 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10787 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10788 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10789 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10790 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10791 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10792 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10793 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10794 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10795 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10796 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10797 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10798 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10799 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10800 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10801 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10802 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10803 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10804 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10805 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10806 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10807 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10808 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10809 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10810 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10811 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10812 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10813 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10814 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10815 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10816 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10817 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10818 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10819 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10820 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10821 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10822 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10823 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10824 10825 BCE_PRINTF( 10826 "----------------------------" 10827 "----------------" 10828 "----------------------------\n"); 10829 } 10830 10831 10832 /****************************************************************************/ 10833 /* Prints out a summary of the driver state. */ 10834 /* */ 10835 /* Returns: */ 10836 /* Nothing. */ 10837 /****************************************************************************/ 10838 static __attribute__ ((noinline)) void 10839 bce_dump_driver_state(struct bce_softc *sc) 10840 { 10841 u32 val_hi, val_lo; 10842 10843 BCE_PRINTF( 10844 "-----------------------------" 10845 " Driver State " 10846 "-----------------------------\n"); 10847 10848 val_hi = BCE_ADDR_HI(sc); 10849 val_lo = BCE_ADDR_LO(sc); 10850 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10851 "address\n", val_hi, val_lo); 10852 10853 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10854 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10855 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10856 "address\n", val_hi, val_lo); 10857 10858 val_hi = BCE_ADDR_HI(sc->status_block); 10859 val_lo = BCE_ADDR_LO(sc->status_block); 10860 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10861 "virtual address\n", val_hi, val_lo); 10862 10863 val_hi = BCE_ADDR_HI(sc->stats_block); 10864 val_lo = BCE_ADDR_LO(sc->stats_block); 10865 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10866 "virtual address\n", val_hi, val_lo); 10867 10868 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10869 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10870 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10871 "virtual adddress\n", val_hi, val_lo); 10872 10873 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10874 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10875 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10876 "virtual address\n", val_hi, val_lo); 10877 10878 if (bce_hdr_split == TRUE) { 10879 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10880 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10881 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10882 "virtual address\n", val_hi, val_lo); 10883 } 10884 10885 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10886 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10887 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10888 "virtual address\n", val_hi, val_lo); 10889 10890 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10891 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10892 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10893 "virtual address\n", val_hi, val_lo); 10894 10895 if (bce_hdr_split == TRUE) { 10896 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10897 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10898 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10899 "virtual address\n", val_hi, val_lo); 10900 } 10901 10902 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10903 "h/w intrs\n", 10904 (long long unsigned int) sc->interrupts_generated); 10905 10906 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10907 "rx interrupts handled\n", 10908 (long long unsigned int) sc->interrupts_rx); 10909 10910 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10911 "tx interrupts handled\n", 10912 (long long unsigned int) sc->interrupts_tx); 10913 10914 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10915 "phy interrupts handled\n", 10916 (long long unsigned int) sc->phy_interrupts); 10917 10918 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10919 "status block index\n", sc->last_status_idx); 10920 10921 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10922 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10923 10924 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10925 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10926 10927 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10928 "byte seq index\n", sc->tx_prod_bseq); 10929 10930 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10931 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10932 10933 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10934 "tx_bd's\n", sc->used_tx_bd); 10935 10936 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10937 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10938 10939 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10940 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10941 10942 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10943 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10944 10945 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10946 "byte seq index\n", sc->rx_prod_bseq); 10947 10948 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10949 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10950 10951 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10952 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10953 10954 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10955 "rx_bd's\n", sc->free_rx_bd); 10956 10957 if (bce_hdr_split == TRUE) { 10958 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10959 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10960 10961 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10962 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10963 10964 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10965 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10966 } 10967 10968 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10969 "rx_bd's\n", sc->free_pg_bd); 10970 10971 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10972 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10973 10974 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10975 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10976 10977 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10978 "bce mac flags\n", sc->bce_flags); 10979 10980 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10981 "bce phy flags\n", sc->bce_phy_flags); 10982 10983 BCE_PRINTF( 10984 "----------------------------" 10985 "----------------" 10986 "----------------------------\n"); 10987 } 10988 10989 10990 /****************************************************************************/ 10991 /* Prints out the hardware state through a summary of important register, */ 10992 /* followed by a complete register dump. */ 10993 /* */ 10994 /* Returns: */ 10995 /* Nothing. */ 10996 /****************************************************************************/ 10997 static __attribute__ ((noinline)) void 10998 bce_dump_hw_state(struct bce_softc *sc) 10999 { 11000 u32 val; 11001 11002 BCE_PRINTF( 11003 "----------------------------" 11004 " Hardware State " 11005 "----------------------------\n"); 11006 11007 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11008 11009 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 11010 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 11011 val, BCE_MISC_ENABLE_STATUS_BITS); 11012 11013 val = REG_RD(sc, BCE_DMA_STATUS); 11014 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 11015 val, BCE_DMA_STATUS); 11016 11017 val = REG_RD(sc, BCE_CTX_STATUS); 11018 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 11019 val, BCE_CTX_STATUS); 11020 11021 val = REG_RD(sc, BCE_EMAC_STATUS); 11022 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 11023 val, BCE_EMAC_STATUS); 11024 11025 val = REG_RD(sc, BCE_RPM_STATUS); 11026 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 11027 val, BCE_RPM_STATUS); 11028 11029 /* ToDo: Create a #define for this constant. */ 11030 val = REG_RD(sc, 0x2004); 11031 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11032 val, 0x2004); 11033 11034 val = REG_RD(sc, BCE_RV2P_STATUS); 11035 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11036 val, BCE_RV2P_STATUS); 11037 11038 /* ToDo: Create a #define for this constant. */ 11039 val = REG_RD(sc, 0x2c04); 11040 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11041 val, 0x2c04); 11042 11043 val = REG_RD(sc, BCE_TBDR_STATUS); 11044 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11045 val, BCE_TBDR_STATUS); 11046 11047 val = REG_RD(sc, BCE_TDMA_STATUS); 11048 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11049 val, BCE_TDMA_STATUS); 11050 11051 val = REG_RD(sc, BCE_HC_STATUS); 11052 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11053 val, BCE_HC_STATUS); 11054 11055 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11056 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11057 val, BCE_TXP_CPU_STATE); 11058 11059 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11060 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11061 val, BCE_TPAT_CPU_STATE); 11062 11063 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11064 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11065 val, BCE_RXP_CPU_STATE); 11066 11067 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11068 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11069 val, BCE_COM_CPU_STATE); 11070 11071 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11072 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11073 val, BCE_MCP_CPU_STATE); 11074 11075 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11076 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11077 val, BCE_CP_CPU_STATE); 11078 11079 BCE_PRINTF( 11080 "----------------------------" 11081 "----------------" 11082 "----------------------------\n"); 11083 11084 BCE_PRINTF( 11085 "----------------------------" 11086 " Register Dump " 11087 "----------------------------\n"); 11088 11089 for (int i = 0x400; i < 0x8000; i += 0x10) { 11090 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11091 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11092 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11093 } 11094 11095 BCE_PRINTF( 11096 "----------------------------" 11097 "----------------" 11098 "----------------------------\n"); 11099 } 11100 11101 11102 /****************************************************************************/ 11103 /* Prints out the contentst of shared memory which is used for host driver */ 11104 /* to bootcode firmware communication. */ 11105 /* */ 11106 /* Returns: */ 11107 /* Nothing. */ 11108 /****************************************************************************/ 11109 static __attribute__ ((noinline)) void 11110 bce_dump_shmem_state(struct bce_softc *sc) 11111 { 11112 BCE_PRINTF( 11113 "----------------------------" 11114 " Hardware State " 11115 "----------------------------\n"); 11116 11117 BCE_PRINTF("0x%08X - Shared memory base address\n", 11118 sc->bce_shmem_base); 11119 BCE_PRINTF("%s - bootcode version\n", 11120 sc->bce_bc_ver); 11121 11122 BCE_PRINTF( 11123 "----------------------------" 11124 " Shared Mem " 11125 "----------------------------\n"); 11126 11127 for (int i = 0x0; i < 0x200; i += 0x10) { 11128 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11129 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11130 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11131 } 11132 11133 BCE_PRINTF( 11134 "----------------------------" 11135 "----------------" 11136 "----------------------------\n"); 11137 } 11138 11139 11140 /****************************************************************************/ 11141 /* Prints out the mailbox queue registers. */ 11142 /* */ 11143 /* Returns: */ 11144 /* Nothing. */ 11145 /****************************************************************************/ 11146 static __attribute__ ((noinline)) void 11147 bce_dump_mq_regs(struct bce_softc *sc) 11148 { 11149 BCE_PRINTF( 11150 "----------------------------" 11151 " MQ Regs " 11152 "----------------------------\n"); 11153 11154 BCE_PRINTF( 11155 "----------------------------" 11156 "----------------" 11157 "----------------------------\n"); 11158 11159 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11160 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11161 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11162 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11163 } 11164 11165 BCE_PRINTF( 11166 "----------------------------" 11167 "----------------" 11168 "----------------------------\n"); 11169 } 11170 11171 11172 /****************************************************************************/ 11173 /* Prints out the bootcode state. */ 11174 /* */ 11175 /* Returns: */ 11176 /* Nothing. */ 11177 /****************************************************************************/ 11178 static __attribute__ ((noinline)) void 11179 bce_dump_bc_state(struct bce_softc *sc) 11180 { 11181 u32 val; 11182 11183 BCE_PRINTF( 11184 "----------------------------" 11185 " Bootcode State " 11186 "----------------------------\n"); 11187 11188 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11189 11190 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11191 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11192 val, BCE_BC_RESET_TYPE); 11193 11194 val = bce_shmem_rd(sc, BCE_BC_STATE); 11195 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11196 val, BCE_BC_STATE); 11197 11198 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11199 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11200 val, BCE_BC_STATE_CONDITION); 11201 11202 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11203 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11204 val, BCE_BC_STATE_DEBUG_CMD); 11205 11206 BCE_PRINTF( 11207 "----------------------------" 11208 "----------------" 11209 "----------------------------\n"); 11210 } 11211 11212 11213 /****************************************************************************/ 11214 /* Prints out the TXP processor state. */ 11215 /* */ 11216 /* Returns: */ 11217 /* Nothing. */ 11218 /****************************************************************************/ 11219 static __attribute__ ((noinline)) void 11220 bce_dump_txp_state(struct bce_softc *sc, int regs) 11221 { 11222 u32 val; 11223 u32 fw_version[3]; 11224 11225 BCE_PRINTF( 11226 "----------------------------" 11227 " TXP State " 11228 "----------------------------\n"); 11229 11230 for (int i = 0; i < 3; i++) 11231 fw_version[i] = htonl(REG_RD_IND(sc, 11232 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11233 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11234 11235 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11236 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11237 val, BCE_TXP_CPU_MODE); 11238 11239 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11240 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11241 val, BCE_TXP_CPU_STATE); 11242 11243 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11244 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11245 val, BCE_TXP_CPU_EVENT_MASK); 11246 11247 if (regs) { 11248 BCE_PRINTF( 11249 "----------------------------" 11250 " Register Dump " 11251 "----------------------------\n"); 11252 11253 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11254 /* Skip the big blank spaces */ 11255 if (i < 0x454000 && i > 0x5ffff) 11256 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11257 "0x%08X 0x%08X\n", i, 11258 REG_RD_IND(sc, i), 11259 REG_RD_IND(sc, i + 0x4), 11260 REG_RD_IND(sc, i + 0x8), 11261 REG_RD_IND(sc, i + 0xC)); 11262 } 11263 } 11264 11265 BCE_PRINTF( 11266 "----------------------------" 11267 "----------------" 11268 "----------------------------\n"); 11269 } 11270 11271 11272 /****************************************************************************/ 11273 /* Prints out the RXP processor state. */ 11274 /* */ 11275 /* Returns: */ 11276 /* Nothing. */ 11277 /****************************************************************************/ 11278 static __attribute__ ((noinline)) void 11279 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11280 { 11281 u32 val; 11282 u32 fw_version[3]; 11283 11284 BCE_PRINTF( 11285 "----------------------------" 11286 " RXP State " 11287 "----------------------------\n"); 11288 11289 for (int i = 0; i < 3; i++) 11290 fw_version[i] = htonl(REG_RD_IND(sc, 11291 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11292 11293 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11294 11295 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11296 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11297 val, BCE_RXP_CPU_MODE); 11298 11299 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11300 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11301 val, BCE_RXP_CPU_STATE); 11302 11303 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11304 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11305 val, BCE_RXP_CPU_EVENT_MASK); 11306 11307 if (regs) { 11308 BCE_PRINTF( 11309 "----------------------------" 11310 " Register Dump " 11311 "----------------------------\n"); 11312 11313 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11314 /* Skip the big blank sapces */ 11315 if (i < 0xc5400 && i > 0xdffff) 11316 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11317 "0x%08X 0x%08X\n", i, 11318 REG_RD_IND(sc, i), 11319 REG_RD_IND(sc, i + 0x4), 11320 REG_RD_IND(sc, i + 0x8), 11321 REG_RD_IND(sc, i + 0xC)); 11322 } 11323 } 11324 11325 BCE_PRINTF( 11326 "----------------------------" 11327 "----------------" 11328 "----------------------------\n"); 11329 } 11330 11331 11332 /****************************************************************************/ 11333 /* Prints out the TPAT processor state. */ 11334 /* */ 11335 /* Returns: */ 11336 /* Nothing. */ 11337 /****************************************************************************/ 11338 static __attribute__ ((noinline)) void 11339 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11340 { 11341 u32 val; 11342 u32 fw_version[3]; 11343 11344 BCE_PRINTF( 11345 "----------------------------" 11346 " TPAT State " 11347 "----------------------------\n"); 11348 11349 for (int i = 0; i < 3; i++) 11350 fw_version[i] = htonl(REG_RD_IND(sc, 11351 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11352 11353 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11354 11355 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11356 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11357 val, BCE_TPAT_CPU_MODE); 11358 11359 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11360 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11361 val, BCE_TPAT_CPU_STATE); 11362 11363 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11364 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11365 val, BCE_TPAT_CPU_EVENT_MASK); 11366 11367 if (regs) { 11368 BCE_PRINTF( 11369 "----------------------------" 11370 " Register Dump " 11371 "----------------------------\n"); 11372 11373 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11374 /* Skip the big blank spaces */ 11375 if (i < 0x854000 && i > 0x9ffff) 11376 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11377 "0x%08X 0x%08X\n", i, 11378 REG_RD_IND(sc, i), 11379 REG_RD_IND(sc, i + 0x4), 11380 REG_RD_IND(sc, i + 0x8), 11381 REG_RD_IND(sc, i + 0xC)); 11382 } 11383 } 11384 11385 BCE_PRINTF( 11386 "----------------------------" 11387 "----------------" 11388 "----------------------------\n"); 11389 } 11390 11391 11392 /****************************************************************************/ 11393 /* Prints out the Command Procesor (CP) state. */ 11394 /* */ 11395 /* Returns: */ 11396 /* Nothing. */ 11397 /****************************************************************************/ 11398 static __attribute__ ((noinline)) void 11399 bce_dump_cp_state(struct bce_softc *sc, int regs) 11400 { 11401 u32 val; 11402 u32 fw_version[3]; 11403 11404 BCE_PRINTF( 11405 "----------------------------" 11406 " CP State " 11407 "----------------------------\n"); 11408 11409 for (int i = 0; i < 3; i++) 11410 fw_version[i] = htonl(REG_RD_IND(sc, 11411 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11412 11413 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11414 11415 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11416 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11417 val, BCE_CP_CPU_MODE); 11418 11419 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11420 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11421 val, BCE_CP_CPU_STATE); 11422 11423 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11424 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11425 BCE_CP_CPU_EVENT_MASK); 11426 11427 if (regs) { 11428 BCE_PRINTF( 11429 "----------------------------" 11430 " Register Dump " 11431 "----------------------------\n"); 11432 11433 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11434 /* Skip the big blank spaces */ 11435 if (i < 0x185400 && i > 0x19ffff) 11436 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11437 "0x%08X 0x%08X\n", i, 11438 REG_RD_IND(sc, i), 11439 REG_RD_IND(sc, i + 0x4), 11440 REG_RD_IND(sc, i + 0x8), 11441 REG_RD_IND(sc, i + 0xC)); 11442 } 11443 } 11444 11445 BCE_PRINTF( 11446 "----------------------------" 11447 "----------------" 11448 "----------------------------\n"); 11449 } 11450 11451 11452 /****************************************************************************/ 11453 /* Prints out the Completion Procesor (COM) state. */ 11454 /* */ 11455 /* Returns: */ 11456 /* Nothing. */ 11457 /****************************************************************************/ 11458 static __attribute__ ((noinline)) void 11459 bce_dump_com_state(struct bce_softc *sc, int regs) 11460 { 11461 u32 val; 11462 u32 fw_version[4]; 11463 11464 BCE_PRINTF( 11465 "----------------------------" 11466 " COM State " 11467 "----------------------------\n"); 11468 11469 for (int i = 0; i < 3; i++) 11470 fw_version[i] = htonl(REG_RD_IND(sc, 11471 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11472 11473 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11474 11475 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11476 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11477 val, BCE_COM_CPU_MODE); 11478 11479 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11480 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11481 val, BCE_COM_CPU_STATE); 11482 11483 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11484 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11485 BCE_COM_CPU_EVENT_MASK); 11486 11487 if (regs) { 11488 BCE_PRINTF( 11489 "----------------------------" 11490 " Register Dump " 11491 "----------------------------\n"); 11492 11493 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11494 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11495 "0x%08X 0x%08X\n", i, 11496 REG_RD_IND(sc, i), 11497 REG_RD_IND(sc, i + 0x4), 11498 REG_RD_IND(sc, i + 0x8), 11499 REG_RD_IND(sc, i + 0xC)); 11500 } 11501 } 11502 11503 BCE_PRINTF( 11504 "----------------------------" 11505 "----------------" 11506 "----------------------------\n"); 11507 } 11508 11509 11510 /****************************************************************************/ 11511 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11512 /* */ 11513 /* Returns: */ 11514 /* Nothing. */ 11515 /****************************************************************************/ 11516 static __attribute__ ((noinline)) void 11517 bce_dump_rv2p_state(struct bce_softc *sc) 11518 { 11519 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11520 11521 BCE_PRINTF( 11522 "----------------------------" 11523 " RV2P State " 11524 "----------------------------\n"); 11525 11526 /* Stall the RV2P processors. */ 11527 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11528 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11529 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11530 11531 /* Read the firmware version. */ 11532 val = 0x00000001; 11533 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11534 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11535 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11536 BCE_RV2P_INSTR_HIGH_HIGH; 11537 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11538 fw_ver_high, fw_ver_low); 11539 11540 val = 0x00000001; 11541 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11542 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11543 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11544 BCE_RV2P_INSTR_HIGH_HIGH; 11545 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11546 fw_ver_high, fw_ver_low); 11547 11548 /* Resume the RV2P processors. */ 11549 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11550 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11551 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11552 11553 /* Fetch the program counter value. */ 11554 val = 0x68007800; 11555 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11556 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11557 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11558 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11559 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11560 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11561 11562 /* Fetch the program counter value again to see if it is advancing. */ 11563 val = 0x68007800; 11564 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11565 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11566 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11567 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11568 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11569 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11570 11571 BCE_PRINTF( 11572 "----------------------------" 11573 "----------------" 11574 "----------------------------\n"); 11575 } 11576 11577 11578 /****************************************************************************/ 11579 /* Prints out the driver state and then enters the debugger. */ 11580 /* */ 11581 /* Returns: */ 11582 /* Nothing. */ 11583 /****************************************************************************/ 11584 static __attribute__ ((noinline)) void 11585 bce_breakpoint(struct bce_softc *sc) 11586 { 11587 11588 /* 11589 * Unreachable code to silence compiler warnings 11590 * about unused functions. 11591 */ 11592 if (0) { 11593 bce_freeze_controller(sc); 11594 bce_unfreeze_controller(sc); 11595 bce_dump_enet(sc, NULL); 11596 bce_dump_txbd(sc, 0, NULL); 11597 bce_dump_rxbd(sc, 0, NULL); 11598 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11599 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11600 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11601 bce_dump_l2fhdr(sc, 0, NULL); 11602 bce_dump_ctx(sc, RX_CID); 11603 bce_dump_ftqs(sc); 11604 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11605 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11606 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11607 bce_dump_status_block(sc); 11608 bce_dump_stats_block(sc); 11609 bce_dump_driver_state(sc); 11610 bce_dump_hw_state(sc); 11611 bce_dump_bc_state(sc); 11612 bce_dump_txp_state(sc, 0); 11613 bce_dump_rxp_state(sc, 0); 11614 bce_dump_tpat_state(sc, 0); 11615 bce_dump_cp_state(sc, 0); 11616 bce_dump_com_state(sc, 0); 11617 bce_dump_rv2p_state(sc); 11618 bce_dump_pgbd(sc, 0, NULL); 11619 } 11620 11621 bce_dump_status_block(sc); 11622 bce_dump_driver_state(sc); 11623 11624 /* Call the debugger. */ 11625 breakpoint(); 11626 } 11627 #endif 11628