1 /*- 2 * Copyright (c) 2006-2008 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5716 C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <dev/bce/if_bcereg.h> 55 #include <dev/bce/if_bcefw.h> 56 57 /****************************************************************************/ 58 /* BCE Debug Options */ 59 /****************************************************************************/ 60 #ifdef BCE_DEBUG 61 u32 bce_debug = BCE_WARN; 62 63 /* 0 = Never */ 64 /* 1 = 1 in 2,147,483,648 */ 65 /* 256 = 1 in 8,388,608 */ 66 /* 2048 = 1 in 1,048,576 */ 67 /* 65536 = 1 in 32,768 */ 68 /* 1048576 = 1 in 2,048 */ 69 /* 268435456 = 1 in 8 */ 70 /* 536870912 = 1 in 4 */ 71 /* 1073741824 = 1 in 2 */ 72 73 /* Controls how often the l2_fhdr frame error check will fail. */ 74 int bce_debug_l2fhdr_status_check = 0; 75 76 /* Controls how often the unexpected attention check will fail. */ 77 int bce_debug_unexpected_attention = 0; 78 79 /* Controls how often to simulate an mbuf allocation failure. */ 80 int bce_debug_mbuf_allocation_failure = 0; 81 82 /* Controls how often to simulate a DMA mapping failure. */ 83 int bce_debug_dma_map_addr_failure = 0; 84 85 /* Controls how often to simulate a bootcode failure. */ 86 int bce_debug_bootcode_running_failure = 0; 87 #endif 88 89 /****************************************************************************/ 90 /* BCE Build Time Options */ 91 /****************************************************************************/ 92 #define BCE_USE_SPLIT_HEADER 1 93 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 94 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bce_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 #define BCE_DEVDESC_MAX 64 102 103 static struct bce_type bce_devs[] = { 104 /* BCM5706C Controllers and OEM boards. */ 105 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 106 "HP NC370T Multifunction Gigabit Server Adapter" }, 107 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 108 "HP NC370i Multifunction Gigabit Server Adapter" }, 109 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 110 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 111 112 /* BCM5706S controllers and OEM boards. */ 113 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 114 "HP NC370F Multifunction Gigabit Server Adapter" }, 115 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 116 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 117 118 /* BCM5708C controllers and OEM boards. */ 119 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 120 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 121 122 /* BCM5708S controllers and OEM boards. */ 123 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 124 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 125 126 /* BCM5709C controllers and OEM boards. */ 127 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 128 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 129 130 /* BCM5709S controllers and OEM boards. */ 131 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 132 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 133 134 /* BCM5716 controllers and OEM boards. */ 135 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 136 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 137 138 { 0, 0, 0, 0, NULL } 139 }; 140 141 142 /****************************************************************************/ 143 /* Supported Flash NVRAM device data. */ 144 /****************************************************************************/ 145 static struct flash_spec flash_table[] = 146 { 147 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 148 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 149 150 /* Slow EEPROM */ 151 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 152 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 153 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 154 "EEPROM - slow"}, 155 /* Expansion entry 0001 */ 156 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 159 "Entry 0001"}, 160 /* Saifun SA25F010 (non-buffered flash) */ 161 /* strap, cfg1, & write1 need updates */ 162 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 163 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 165 "Non-buffered flash (128kB)"}, 166 /* Saifun SA25F020 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 169 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 171 "Non-buffered flash (256kB)"}, 172 /* Expansion entry 0100 */ 173 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 174 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 175 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 176 "Entry 0100"}, 177 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 178 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 179 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 180 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 181 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 182 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 183 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 184 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 185 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 186 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 187 /* Saifun SA25F005 (non-buffered flash) */ 188 /* strap, cfg1, & write1 need updates */ 189 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 190 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 191 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 192 "Non-buffered flash (64kB)"}, 193 /* Fast EEPROM */ 194 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 195 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 196 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 197 "EEPROM - fast"}, 198 /* Expansion entry 1001 */ 199 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 200 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 202 "Entry 1001"}, 203 /* Expansion entry 1010 */ 204 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 207 "Entry 1010"}, 208 /* ATMEL AT45DB011B (buffered flash) */ 209 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 210 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 211 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 212 "Buffered flash (128kB)"}, 213 /* Expansion entry 1100 */ 214 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 216 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 217 "Entry 1100"}, 218 /* Expansion entry 1101 */ 219 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 222 "Entry 1101"}, 223 /* Ateml Expansion entry 1110 */ 224 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 225 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 226 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 227 "Entry 1110 (Atmel)"}, 228 /* ATMEL AT45DB021B (buffered flash) */ 229 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 230 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 231 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 232 "Buffered flash (256kB)"}, 233 }; 234 235 /* 236 * The BCM5709 controllers transparently handle the 237 * differences between Atmel 264 byte pages and all 238 * flash devices which use 256 byte pages, so no 239 * logical-to-physical mapping is required in the 240 * driver. 241 */ 242 static struct flash_spec flash_5709 = { 243 .flags = BCE_NV_BUFFERED, 244 .page_bits = BCM5709_FLASH_PAGE_BITS, 245 .page_size = BCM5709_FLASH_PAGE_SIZE, 246 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 247 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 248 .name = "5709 buffered flash (256kB)", 249 }; 250 251 252 /****************************************************************************/ 253 /* FreeBSD device entry points. */ 254 /****************************************************************************/ 255 static int bce_probe (device_t); 256 static int bce_attach (device_t); 257 static int bce_detach (device_t); 258 static int bce_shutdown (device_t); 259 260 261 /****************************************************************************/ 262 /* BCE Debug Data Structure Dump Routines */ 263 /****************************************************************************/ 264 #ifdef BCE_DEBUG 265 static u32 bce_reg_rd (struct bce_softc *, u32); 266 static void bce_reg_wr (struct bce_softc *, u32, u32); 267 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 268 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 269 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 270 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 271 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 272 #ifdef BCE_USE_SPLIT_HEADER 273 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 274 #endif 275 static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 276 static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 277 #ifdef BCE_USE_SPLIT_HEADER 278 static void bce_dump_pgbd (struct bce_softc *, int, struct rx_bd *); 279 #endif 280 static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 281 static void bce_dump_ctx (struct bce_softc *, u16); 282 static void bce_dump_ftqs (struct bce_softc *); 283 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 284 static void bce_dump_rx_chain (struct bce_softc *, u16, int); 285 #ifdef BCE_USE_SPLIT_HEADER 286 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 287 #endif 288 static void bce_dump_status_block (struct bce_softc *); 289 static void bce_dump_stats_block (struct bce_softc *); 290 static void bce_dump_driver_state (struct bce_softc *); 291 static void bce_dump_hw_state (struct bce_softc *); 292 static void bce_dump_mq_regs (struct bce_softc *); 293 static void bce_dump_bc_state (struct bce_softc *); 294 static void bce_dump_txp_state (struct bce_softc *, int); 295 static void bce_dump_rxp_state (struct bce_softc *, int); 296 static void bce_dump_tpat_state (struct bce_softc *, int); 297 static void bce_dump_cp_state (struct bce_softc *, int); 298 static void bce_dump_com_state (struct bce_softc *, int); 299 static void bce_breakpoint (struct bce_softc *); 300 #endif 301 302 303 /****************************************************************************/ 304 /* BCE Register/Memory Access Routines */ 305 /****************************************************************************/ 306 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 307 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 308 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 309 static int bce_miibus_read_reg (device_t, int, int); 310 static int bce_miibus_write_reg (device_t, int, int, int); 311 static void bce_miibus_statchg (device_t); 312 313 314 /****************************************************************************/ 315 /* BCE NVRAM Access Routines */ 316 /****************************************************************************/ 317 static int bce_acquire_nvram_lock (struct bce_softc *); 318 static int bce_release_nvram_lock (struct bce_softc *); 319 static void bce_enable_nvram_access (struct bce_softc *); 320 static void bce_disable_nvram_access(struct bce_softc *); 321 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 322 static int bce_init_nvram (struct bce_softc *); 323 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 324 static int bce_nvram_test (struct bce_softc *); 325 #ifdef BCE_NVRAM_WRITE_SUPPORT 326 static int bce_enable_nvram_write (struct bce_softc *); 327 static void bce_disable_nvram_write (struct bce_softc *); 328 static int bce_nvram_erase_page (struct bce_softc *, u32); 329 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 330 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 331 #endif 332 333 /****************************************************************************/ 334 /* */ 335 /****************************************************************************/ 336 static void bce_get_media (struct bce_softc *); 337 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 338 static int bce_dma_alloc (device_t); 339 static void bce_dma_free (struct bce_softc *); 340 static void bce_release_resources (struct bce_softc *); 341 342 /****************************************************************************/ 343 /* BCE Firmware Synchronization and Load */ 344 /****************************************************************************/ 345 static int bce_fw_sync (struct bce_softc *, u32); 346 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 347 static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 348 static void bce_init_rxp_cpu (struct bce_softc *); 349 static void bce_init_txp_cpu (struct bce_softc *); 350 static void bce_init_tpat_cpu (struct bce_softc *); 351 static void bce_init_cp_cpu (struct bce_softc *); 352 static void bce_init_com_cpu (struct bce_softc *); 353 static void bce_init_cpus (struct bce_softc *); 354 355 static void bce_print_adapter_info (struct bce_softc *); 356 static void bce_probe_pci_caps (device_t, struct bce_softc *); 357 static void bce_stop (struct bce_softc *); 358 static int bce_reset (struct bce_softc *, u32); 359 static int bce_chipinit (struct bce_softc *); 360 static int bce_blockinit (struct bce_softc *); 361 362 static int bce_init_tx_chain (struct bce_softc *); 363 static void bce_free_tx_chain (struct bce_softc *); 364 365 static int bce_get_rx_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 366 static int bce_init_rx_chain (struct bce_softc *); 367 static void bce_fill_rx_chain (struct bce_softc *); 368 static void bce_free_rx_chain (struct bce_softc *); 369 370 #ifdef BCE_USE_SPLIT_HEADER 371 static int bce_get_pg_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *); 372 static int bce_init_pg_chain (struct bce_softc *); 373 static void bce_fill_pg_chain (struct bce_softc *); 374 static void bce_free_pg_chain (struct bce_softc *); 375 #endif 376 377 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 378 static void bce_start_locked (struct ifnet *); 379 static void bce_start (struct ifnet *); 380 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 381 static void bce_watchdog (struct bce_softc *); 382 static int bce_ifmedia_upd (struct ifnet *); 383 static void bce_ifmedia_upd_locked (struct ifnet *); 384 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 385 static void bce_init_locked (struct bce_softc *); 386 static void bce_init (void *); 387 static void bce_mgmt_init_locked (struct bce_softc *sc); 388 389 static void bce_init_ctx (struct bce_softc *); 390 static void bce_get_mac_addr (struct bce_softc *); 391 static void bce_set_mac_addr (struct bce_softc *); 392 static void bce_phy_intr (struct bce_softc *); 393 static inline u16 bce_get_hw_rx_cons(struct bce_softc *); 394 static void bce_rx_intr (struct bce_softc *); 395 static void bce_tx_intr (struct bce_softc *); 396 static void bce_disable_intr (struct bce_softc *); 397 static void bce_enable_intr (struct bce_softc *, int); 398 399 static void bce_intr (void *); 400 static void bce_set_rx_mode (struct bce_softc *); 401 static void bce_stats_update (struct bce_softc *); 402 static void bce_tick (void *); 403 static void bce_pulse (void *); 404 static void bce_add_sysctls (struct bce_softc *); 405 406 407 /****************************************************************************/ 408 /* FreeBSD device dispatch table. */ 409 /****************************************************************************/ 410 static device_method_t bce_methods[] = { 411 /* Device interface (device_if.h) */ 412 DEVMETHOD(device_probe, bce_probe), 413 DEVMETHOD(device_attach, bce_attach), 414 DEVMETHOD(device_detach, bce_detach), 415 DEVMETHOD(device_shutdown, bce_shutdown), 416 /* Supported by device interface but not used here. */ 417 /* DEVMETHOD(device_identify, bce_identify), */ 418 /* DEVMETHOD(device_suspend, bce_suspend), */ 419 /* DEVMETHOD(device_resume, bce_resume), */ 420 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 421 422 /* Bus interface (bus_if.h) */ 423 DEVMETHOD(bus_print_child, bus_generic_print_child), 424 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 425 426 /* MII interface (miibus_if.h) */ 427 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 428 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 429 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 430 /* Supported by MII interface but not used here. */ 431 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 432 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 433 434 { 0, 0 } 435 }; 436 437 static driver_t bce_driver = { 438 "bce", 439 bce_methods, 440 sizeof(struct bce_softc) 441 }; 442 443 static devclass_t bce_devclass; 444 445 MODULE_DEPEND(bce, pci, 1, 1, 1); 446 MODULE_DEPEND(bce, ether, 1, 1, 1); 447 MODULE_DEPEND(bce, miibus, 1, 1, 1); 448 449 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 450 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 451 452 453 /****************************************************************************/ 454 /* Tunable device values */ 455 /****************************************************************************/ 456 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 457 458 /* Allowable values are TRUE or FALSE */ 459 static int bce_tso_enable = TRUE; 460 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 461 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 462 "TSO Enable/Disable"); 463 464 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 465 /* ToDo: Add MSI-X support. */ 466 static int bce_msi_enable = 1; 467 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 468 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 469 "MSI-X|MSI|INTx selector"); 470 471 /* ToDo: Add tunable to enable/disable strict MTU handling. */ 472 /* Currently allows "loose" RX MTU checking (i.e. sets the */ 473 /* h/w RX MTU to the size of the largest receive buffer, or */ 474 /* 2048 bytes). */ 475 476 477 /****************************************************************************/ 478 /* Device probe function. */ 479 /* */ 480 /* Compares the device to the driver's list of supported devices and */ 481 /* reports back to the OS whether this is the right driver for the device. */ 482 /* */ 483 /* Returns: */ 484 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 485 /****************************************************************************/ 486 static int 487 bce_probe(device_t dev) 488 { 489 struct bce_type *t; 490 struct bce_softc *sc; 491 char *descbuf; 492 u16 vid = 0, did = 0, svid = 0, sdid = 0; 493 494 t = bce_devs; 495 496 sc = device_get_softc(dev); 497 bzero(sc, sizeof(struct bce_softc)); 498 sc->bce_unit = device_get_unit(dev); 499 sc->bce_dev = dev; 500 501 /* Get the data for the device to be probed. */ 502 vid = pci_get_vendor(dev); 503 did = pci_get_device(dev); 504 svid = pci_get_subvendor(dev); 505 sdid = pci_get_subdevice(dev); 506 507 DBPRINT(sc, BCE_EXTREME_LOAD, 508 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 509 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 510 511 /* Look through the list of known devices for a match. */ 512 while(t->bce_name != NULL) { 513 514 if ((vid == t->bce_vid) && (did == t->bce_did) && 515 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 516 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 517 518 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 519 520 if (descbuf == NULL) 521 return(ENOMEM); 522 523 /* Print out the device identity. */ 524 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 525 t->bce_name, 526 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 527 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 528 529 device_set_desc_copy(dev, descbuf); 530 free(descbuf, M_TEMP); 531 return(BUS_PROBE_DEFAULT); 532 } 533 t++; 534 } 535 536 return(ENXIO); 537 } 538 539 540 /****************************************************************************/ 541 /* PCI Capabilities Probe Function. */ 542 /* */ 543 /* Walks the PCI capabiites list for the device to find what features are */ 544 /* supported. */ 545 /* */ 546 /* Returns: */ 547 /* None. */ 548 /****************************************************************************/ 549 static void 550 bce_print_adapter_info(struct bce_softc *sc) 551 { 552 DBENTER(BCE_VERBOSE_LOAD); 553 554 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 555 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 556 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 557 558 /* Bus info. */ 559 if (sc->bce_flags & BCE_PCIE_FLAG) { 560 printf("Bus (PCIe x%d, ", sc->link_width); 561 switch (sc->link_speed) { 562 case 1: printf("2.5Gbps); "); break; 563 case 2: printf("5Gbps); "); break; 564 default: printf("Unknown link speed); "); 565 } 566 } else { 567 printf("Bus (PCI%s, %s, %dMHz); ", 568 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 569 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 570 sc->bus_speed_mhz); 571 } 572 573 /* Firmware version and device features. */ 574 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver); 575 #ifdef BCE_USE_SPLIT_HEADER 576 printf("SPLT "); 577 #endif 578 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 579 printf("MFW "); 580 if (sc->bce_flags & BCE_USING_MSI_FLAG) 581 printf("MSI "); 582 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 583 printf("MSI-X "); 584 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 585 printf("2.5G "); 586 printf(")\n"); 587 588 DBEXIT(BCE_VERBOSE_LOAD); 589 } 590 591 592 /****************************************************************************/ 593 /* PCI Capabilities Probe Function. */ 594 /* */ 595 /* Walks the PCI capabiites list for the device to find what features are */ 596 /* supported. */ 597 /* */ 598 /* Returns: */ 599 /* None. */ 600 /****************************************************************************/ 601 static void 602 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 603 { 604 u32 reg; 605 606 DBENTER(BCE_VERBOSE_LOAD); 607 608 /* Check if PCI-X capability is enabled. */ 609 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 610 if (reg != 0) 611 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 612 } 613 614 /* Check if PCIe capability is enabled. */ 615 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 616 if (reg != 0) { 617 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 618 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = 0x%08X\n", 619 link_status); 620 sc->link_speed = link_status & 0xf; 621 sc->link_width = (link_status >> 4) & 0x3f; 622 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 623 sc->bce_flags |= BCE_PCIE_FLAG; 624 } 625 } 626 627 /* Check if MSI capability is enabled. */ 628 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 629 if (reg != 0) 630 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 631 } 632 633 /* Check if MSI-X capability is enabled. */ 634 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 635 if (reg != 0) 636 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 637 } 638 639 DBEXIT(BCE_VERBOSE_LOAD); 640 } 641 642 643 /****************************************************************************/ 644 /* Device attach function. */ 645 /* */ 646 /* Allocates device resources, performs secondary chip identification, */ 647 /* resets and initializes the hardware, and initializes driver instance */ 648 /* variables. */ 649 /* */ 650 /* Returns: */ 651 /* 0 on success, positive value on failure. */ 652 /****************************************************************************/ 653 static int 654 bce_attach(device_t dev) 655 { 656 struct bce_softc *sc; 657 struct ifnet *ifp; 658 u32 val; 659 int error, rid, rc = 0; 660 661 sc = device_get_softc(dev); 662 sc->bce_dev = dev; 663 664 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 665 666 sc->bce_unit = device_get_unit(dev); 667 668 /* Set initial device and PHY flags */ 669 sc->bce_flags = 0; 670 sc->bce_phy_flags = 0; 671 672 pci_enable_busmaster(dev); 673 674 /* Allocate PCI memory resources. */ 675 rid = PCIR_BAR(0); 676 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 677 &rid, RF_ACTIVE); 678 679 if (sc->bce_res_mem == NULL) { 680 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 681 __FILE__, __LINE__); 682 rc = ENXIO; 683 goto bce_attach_fail; 684 } 685 686 /* Get various resource handles. */ 687 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 688 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 689 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 690 691 bce_probe_pci_caps(dev, sc); 692 693 rid = 1; 694 #if 0 695 /* Try allocating MSI-X interrupts. */ 696 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 697 (bce_msi_enable >= 2) && 698 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 699 &rid, RF_ACTIVE)) != NULL)) { 700 701 msi_needed = sc->bce_msi_count = 1; 702 703 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 704 (sc->bce_msi_count != msi_needed)) { 705 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 706 "Received = %d, error = %d\n", __FILE__, __LINE__, 707 msi_needed, sc->bce_msi_count, error); 708 sc->bce_msi_count = 0; 709 pci_release_msi(dev); 710 bus_release_resource(dev, SYS_RES_MEMORY, rid, 711 sc->bce_res_irq); 712 sc->bce_res_irq = NULL; 713 } else { 714 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 715 __FUNCTION__); 716 sc->bce_flags |= BCE_USING_MSIX_FLAG; 717 sc->bce_intr = bce_intr; 718 } 719 } 720 #endif 721 722 /* Try allocating a MSI interrupt. */ 723 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 724 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 725 sc->bce_msi_count = 1; 726 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 727 BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n", 728 __FILE__, __LINE__, error); 729 sc->bce_msi_count = 0; 730 pci_release_msi(dev); 731 } else { 732 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n", 733 __FUNCTION__); 734 sc->bce_flags |= BCE_USING_MSI_FLAG; 735 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 736 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 737 sc->bce_irq_rid = 1; 738 sc->bce_intr = bce_intr; 739 } 740 } 741 742 /* Try allocating a legacy interrupt. */ 743 if (sc->bce_msi_count == 0) { 744 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 745 __FUNCTION__); 746 rid = 0; 747 sc->bce_intr = bce_intr; 748 } 749 750 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 751 &rid, RF_SHAREABLE | RF_ACTIVE); 752 753 sc->bce_irq_rid = rid; 754 755 /* Report any IRQ allocation errors. */ 756 if (sc->bce_res_irq == NULL) { 757 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 758 __FILE__, __LINE__); 759 rc = ENXIO; 760 goto bce_attach_fail; 761 } 762 763 /* Initialize mutex for the current device instance. */ 764 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 765 766 /* 767 * Configure byte swap and enable indirect register access. 768 * Rely on CPU to do target byte swapping on big endian systems. 769 * Access to registers outside of PCI configurtion space are not 770 * valid until this is done. 771 */ 772 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 773 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 774 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 775 776 /* Save ASIC revsion info. */ 777 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 778 779 /* Weed out any non-production controller revisions. */ 780 switch(BCE_CHIP_ID(sc)) { 781 case BCE_CHIP_ID_5706_A0: 782 case BCE_CHIP_ID_5706_A1: 783 case BCE_CHIP_ID_5708_A0: 784 case BCE_CHIP_ID_5708_B0: 785 case BCE_CHIP_ID_5709_A0: 786 case BCE_CHIP_ID_5709_B0: 787 case BCE_CHIP_ID_5709_B1: 788 case BCE_CHIP_ID_5709_B2: 789 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 790 __FILE__, __LINE__, 791 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 792 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 793 rc = ENODEV; 794 goto bce_attach_fail; 795 } 796 797 /* 798 * The embedded PCIe to PCI-X bridge (EPB) 799 * in the 5708 cannot address memory above 800 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 801 */ 802 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 803 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 804 else 805 sc->max_bus_addr = BUS_SPACE_MAXADDR; 806 807 /* 808 * Find the base address for shared memory access. 809 * Newer versions of bootcode use a signature and offset 810 * while older versions use a fixed address. 811 */ 812 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 813 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 814 /* Multi-port devices use different offsets in shared memory. */ 815 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 816 (pci_get_function(sc->bce_dev) << 2)); 817 else 818 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 819 820 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 821 __FUNCTION__, sc->bce_shmem_base); 822 823 /* Fetch the bootcode revision. */ 824 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + 825 BCE_DEV_INFO_BC_REV); 826 827 /* Check if any management firmware is running. */ 828 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 829 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) 830 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 831 832 /* Get PCI bus information (speed and type). */ 833 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 834 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 835 u32 clkreg; 836 837 sc->bce_flags |= BCE_PCIX_FLAG; 838 839 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 840 841 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 842 switch (clkreg) { 843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 844 sc->bus_speed_mhz = 133; 845 break; 846 847 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 848 sc->bus_speed_mhz = 100; 849 break; 850 851 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 852 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 853 sc->bus_speed_mhz = 66; 854 break; 855 856 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 857 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 858 sc->bus_speed_mhz = 50; 859 break; 860 861 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 862 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 863 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 864 sc->bus_speed_mhz = 33; 865 break; 866 } 867 } else { 868 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 869 sc->bus_speed_mhz = 66; 870 else 871 sc->bus_speed_mhz = 33; 872 } 873 874 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 875 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 876 877 /* Reset the controller and announce to bootcode that driver is present. */ 878 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 879 BCE_PRINTF("%s(%d): Controller reset failed!\n", 880 __FILE__, __LINE__); 881 rc = ENXIO; 882 goto bce_attach_fail; 883 } 884 885 /* Initialize the controller. */ 886 if (bce_chipinit(sc)) { 887 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 888 __FILE__, __LINE__); 889 rc = ENXIO; 890 goto bce_attach_fail; 891 } 892 893 /* Perform NVRAM test. */ 894 if (bce_nvram_test(sc)) { 895 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 896 __FILE__, __LINE__); 897 rc = ENXIO; 898 goto bce_attach_fail; 899 } 900 901 /* Fetch the permanent Ethernet MAC address. */ 902 bce_get_mac_addr(sc); 903 904 /* 905 * Trip points control how many BDs 906 * should be ready before generating an 907 * interrupt while ticks control how long 908 * a BD can sit in the chain before 909 * generating an interrupt. Set the default 910 * values for the RX and TX chains. 911 */ 912 913 #ifdef BCE_DEBUG 914 /* Force more frequent interrupts. */ 915 sc->bce_tx_quick_cons_trip_int = 1; 916 sc->bce_tx_quick_cons_trip = 1; 917 sc->bce_tx_ticks_int = 0; 918 sc->bce_tx_ticks = 0; 919 920 sc->bce_rx_quick_cons_trip_int = 1; 921 sc->bce_rx_quick_cons_trip = 1; 922 sc->bce_rx_ticks_int = 0; 923 sc->bce_rx_ticks = 0; 924 #else 925 /* Improve throughput at the expense of increased latency. */ 926 sc->bce_tx_quick_cons_trip_int = 20; 927 sc->bce_tx_quick_cons_trip = 20; 928 sc->bce_tx_ticks_int = 80; 929 sc->bce_tx_ticks = 80; 930 931 sc->bce_rx_quick_cons_trip_int = 6; 932 sc->bce_rx_quick_cons_trip = 6; 933 sc->bce_rx_ticks_int = 18; 934 sc->bce_rx_ticks = 18; 935 #endif 936 937 /* Update statistics once every second. */ 938 sc->bce_stats_ticks = 1000000 & 0xffff00; 939 940 /* Find the media type for the adapter. */ 941 bce_get_media(sc); 942 943 /* Store data needed by PHY driver for backplane applications */ 944 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 945 BCE_SHARED_HW_CFG_CONFIG); 946 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 947 BCE_PORT_HW_CFG_CONFIG); 948 949 /* Allocate DMA memory resources. */ 950 if (bce_dma_alloc(dev)) { 951 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 952 __FILE__, __LINE__); 953 rc = ENXIO; 954 goto bce_attach_fail; 955 } 956 957 /* Allocate an ifnet structure. */ 958 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 959 if (ifp == NULL) { 960 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 961 __FILE__, __LINE__); 962 rc = ENXIO; 963 goto bce_attach_fail; 964 } 965 966 /* Initialize the ifnet interface. */ 967 ifp->if_softc = sc; 968 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 970 ifp->if_ioctl = bce_ioctl; 971 ifp->if_start = bce_start; 972 ifp->if_init = bce_init; 973 ifp->if_mtu = ETHERMTU; 974 975 if (bce_tso_enable) { 976 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 977 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4; 978 } else { 979 ifp->if_hwassist = BCE_IF_HWASSIST; 980 ifp->if_capabilities = BCE_IF_CAPABILITIES; 981 } 982 983 ifp->if_capenable = ifp->if_capabilities; 984 985 /* 986 * Assume standard mbuf sizes for buffer allocation. 987 * This may change later if the MTU size is set to 988 * something other than 1500. 989 */ 990 #ifdef BCE_USE_SPLIT_HEADER 991 sc->rx_bd_mbuf_alloc_size = MHLEN; 992 /* Make sure offset is 16 byte aligned for hardware. */ 993 sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) - 994 (MSIZE - MHLEN); 995 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 996 sc->rx_bd_mbuf_align_pad; 997 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 998 #else 999 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1000 sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 1001 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1002 sc->rx_bd_mbuf_align_pad; 1003 #endif 1004 1005 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1006 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1007 IFQ_SET_READY(&ifp->if_snd); 1008 1009 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1010 ifp->if_baudrate = IF_Mbps(2500ULL); 1011 else 1012 ifp->if_baudrate = IF_Mbps(1000); 1013 1014 /* Check for an MII child bus by probing the PHY. */ 1015 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 1016 bce_ifmedia_sts)) { 1017 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 1018 __FILE__, __LINE__); 1019 rc = ENXIO; 1020 goto bce_attach_fail; 1021 } 1022 1023 /* Attach to the Ethernet interface list. */ 1024 ether_ifattach(ifp, sc->eaddr); 1025 1026 #if __FreeBSD_version < 500000 1027 callout_init(&sc->bce_tick_callout); 1028 callout_init(&sc->bce_pulse_callout); 1029 #else 1030 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1031 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1032 #endif 1033 1034 /* Hookup IRQ last. */ 1035 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1036 NULL, bce_intr, sc, &sc->bce_intrhand); 1037 1038 if (rc) { 1039 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1040 __FILE__, __LINE__); 1041 bce_detach(dev); 1042 goto bce_attach_exit; 1043 } 1044 1045 /* 1046 * At this point we've acquired all the resources 1047 * we need to run so there's no turning back, we're 1048 * cleared for launch. 1049 */ 1050 1051 /* Print some important debugging info. */ 1052 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1053 1054 /* Add the supported sysctls to the kernel. */ 1055 bce_add_sysctls(sc); 1056 1057 BCE_LOCK(sc); 1058 /* 1059 * The chip reset earlier notified the bootcode that 1060 * a driver is present. We now need to start our pulse 1061 * routine so that the bootcode is reminded that we're 1062 * still running. 1063 */ 1064 bce_pulse(sc); 1065 1066 bce_mgmt_init_locked(sc); 1067 BCE_UNLOCK(sc); 1068 1069 /* Finally, print some useful adapter info */ 1070 bce_print_adapter_info(sc); 1071 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1072 __FUNCTION__, sc); 1073 1074 goto bce_attach_exit; 1075 1076 bce_attach_fail: 1077 bce_release_resources(sc); 1078 1079 bce_attach_exit: 1080 1081 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1082 1083 return(rc); 1084 } 1085 1086 1087 /****************************************************************************/ 1088 /* Device detach function. */ 1089 /* */ 1090 /* Stops the controller, resets the controller, and releases resources. */ 1091 /* */ 1092 /* Returns: */ 1093 /* 0 on success, positive value on failure. */ 1094 /****************************************************************************/ 1095 static int 1096 bce_detach(device_t dev) 1097 { 1098 struct bce_softc *sc = device_get_softc(dev); 1099 struct ifnet *ifp; 1100 u32 msg; 1101 1102 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1103 1104 ifp = sc->bce_ifp; 1105 1106 /* Stop and reset the controller. */ 1107 BCE_LOCK(sc); 1108 1109 /* Stop the pulse so the bootcode can go to driver absent state. */ 1110 callout_stop(&sc->bce_pulse_callout); 1111 1112 bce_stop(sc); 1113 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1114 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1115 else 1116 msg = BCE_DRV_MSG_CODE_UNLOAD; 1117 bce_reset(sc, msg); 1118 1119 BCE_UNLOCK(sc); 1120 1121 ether_ifdetach(ifp); 1122 1123 /* If we have a child device on the MII bus remove it too. */ 1124 bus_generic_detach(dev); 1125 device_delete_child(dev, sc->bce_miibus); 1126 1127 /* Release all remaining resources. */ 1128 bce_release_resources(sc); 1129 1130 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1131 1132 return(0); 1133 } 1134 1135 1136 /****************************************************************************/ 1137 /* Device shutdown function. */ 1138 /* */ 1139 /* Stops and resets the controller. */ 1140 /* */ 1141 /* Returns: */ 1142 /* 0 on success, positive value on failure. */ 1143 /****************************************************************************/ 1144 static int 1145 bce_shutdown(device_t dev) 1146 { 1147 struct bce_softc *sc = device_get_softc(dev); 1148 u32 msg; 1149 1150 DBENTER(BCE_VERBOSE); 1151 1152 BCE_LOCK(sc); 1153 bce_stop(sc); 1154 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1155 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1156 else 1157 msg = BCE_DRV_MSG_CODE_UNLOAD; 1158 bce_reset(sc, msg); 1159 BCE_UNLOCK(sc); 1160 1161 DBEXIT(BCE_VERBOSE); 1162 1163 return (0); 1164 } 1165 1166 1167 #ifdef BCE_DEBUG 1168 /****************************************************************************/ 1169 /* Register read. */ 1170 /* */ 1171 /* Returns: */ 1172 /* The value of the register. */ 1173 /****************************************************************************/ 1174 static u32 1175 bce_reg_rd(struct bce_softc *sc, u32 offset) 1176 { 1177 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1178 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1179 __FUNCTION__, offset, val); 1180 return val; 1181 } 1182 1183 1184 /****************************************************************************/ 1185 /* Register write (16 bit). */ 1186 /* */ 1187 /* Returns: */ 1188 /* Nothing. */ 1189 /****************************************************************************/ 1190 static void 1191 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1192 { 1193 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1194 __FUNCTION__, offset, val); 1195 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1196 } 1197 1198 1199 /****************************************************************************/ 1200 /* Register write. */ 1201 /* */ 1202 /* Returns: */ 1203 /* Nothing. */ 1204 /****************************************************************************/ 1205 static void 1206 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1207 { 1208 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1209 __FUNCTION__, offset, val); 1210 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1211 } 1212 #endif 1213 1214 /****************************************************************************/ 1215 /* Indirect register read. */ 1216 /* */ 1217 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1218 /* configuration space. Using this mechanism avoids issues with posted */ 1219 /* reads but is much slower than memory-mapped I/O. */ 1220 /* */ 1221 /* Returns: */ 1222 /* The value of the register. */ 1223 /****************************************************************************/ 1224 static u32 1225 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1226 { 1227 device_t dev; 1228 dev = sc->bce_dev; 1229 1230 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1231 #ifdef BCE_DEBUG 1232 { 1233 u32 val; 1234 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1235 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1236 __FUNCTION__, offset, val); 1237 return val; 1238 } 1239 #else 1240 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1241 #endif 1242 } 1243 1244 1245 /****************************************************************************/ 1246 /* Indirect register write. */ 1247 /* */ 1248 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1249 /* configuration space. Using this mechanism avoids issues with posted */ 1250 /* writes but is muchh slower than memory-mapped I/O. */ 1251 /* */ 1252 /* Returns: */ 1253 /* Nothing. */ 1254 /****************************************************************************/ 1255 static void 1256 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1257 { 1258 device_t dev; 1259 dev = sc->bce_dev; 1260 1261 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1262 __FUNCTION__, offset, val); 1263 1264 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1265 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1266 } 1267 1268 1269 #ifdef BCE_DEBUG 1270 /****************************************************************************/ 1271 /* Context memory read. */ 1272 /* */ 1273 /* The NetXtreme II controller uses context memory to track connection */ 1274 /* information for L2 and higher network protocols. */ 1275 /* */ 1276 /* Returns: */ 1277 /* The requested 32 bit value of context memory. */ 1278 /****************************************************************************/ 1279 static u32 1280 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1281 { 1282 u32 idx, offset, retry_cnt = 5, val; 1283 1284 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1285 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1286 __FUNCTION__, cid_addr)); 1287 1288 offset = ctx_offset + cid_addr; 1289 1290 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1291 1292 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1293 1294 for (idx = 0; idx < retry_cnt; idx++) { 1295 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1296 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1297 break; 1298 DELAY(5); 1299 } 1300 1301 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1302 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1303 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1304 __FILE__, __LINE__, cid_addr, ctx_offset); 1305 1306 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1307 } else { 1308 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1309 val = REG_RD(sc, BCE_CTX_DATA); 1310 } 1311 1312 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1313 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1314 1315 return(val); 1316 } 1317 #endif 1318 1319 1320 /****************************************************************************/ 1321 /* Context memory write. */ 1322 /* */ 1323 /* The NetXtreme II controller uses context memory to track connection */ 1324 /* information for L2 and higher network protocols. */ 1325 /* */ 1326 /* Returns: */ 1327 /* Nothing. */ 1328 /****************************************************************************/ 1329 static void 1330 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1331 { 1332 u32 idx, offset = ctx_offset + cid_addr; 1333 u32 val, retry_cnt = 5; 1334 1335 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1336 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1337 1338 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1339 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1340 __FUNCTION__, cid_addr)); 1341 1342 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1343 1344 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1345 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1346 1347 for (idx = 0; idx < retry_cnt; idx++) { 1348 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1349 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1350 break; 1351 DELAY(5); 1352 } 1353 1354 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1355 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1356 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1357 __FILE__, __LINE__, cid_addr, ctx_offset); 1358 1359 } else { 1360 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1361 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1362 } 1363 } 1364 1365 1366 /****************************************************************************/ 1367 /* PHY register read. */ 1368 /* */ 1369 /* Implements register reads on the MII bus. */ 1370 /* */ 1371 /* Returns: */ 1372 /* The value of the register. */ 1373 /****************************************************************************/ 1374 static int 1375 bce_miibus_read_reg(device_t dev, int phy, int reg) 1376 { 1377 struct bce_softc *sc; 1378 u32 val; 1379 int i; 1380 1381 sc = device_get_softc(dev); 1382 1383 /* Make sure we are accessing the correct PHY address. */ 1384 if (phy != sc->bce_phy_addr) { 1385 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY read!\n", phy); 1386 return(0); 1387 } 1388 1389 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1390 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1391 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1392 1393 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1394 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1395 1396 DELAY(40); 1397 } 1398 1399 1400 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1401 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1402 BCE_EMAC_MDIO_COMM_START_BUSY; 1403 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1404 1405 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1406 DELAY(10); 1407 1408 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1409 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1410 DELAY(5); 1411 1412 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1413 val &= BCE_EMAC_MDIO_COMM_DATA; 1414 1415 break; 1416 } 1417 } 1418 1419 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1420 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1421 __FILE__, __LINE__, phy, reg); 1422 val = 0x0; 1423 } else { 1424 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1425 } 1426 1427 1428 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1429 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1430 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1431 1432 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1433 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1434 1435 DELAY(40); 1436 } 1437 1438 DB_PRINT_PHY_REG(reg, val); 1439 return (val & 0xffff); 1440 1441 } 1442 1443 1444 /****************************************************************************/ 1445 /* PHY register write. */ 1446 /* */ 1447 /* Implements register writes on the MII bus. */ 1448 /* */ 1449 /* Returns: */ 1450 /* The value of the register. */ 1451 /****************************************************************************/ 1452 static int 1453 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1454 { 1455 struct bce_softc *sc; 1456 u32 val1; 1457 int i; 1458 1459 sc = device_get_softc(dev); 1460 1461 /* Make sure we are accessing the correct PHY address. */ 1462 if (phy != sc->bce_phy_addr) { 1463 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY write!\n", phy); 1464 return(0); 1465 } 1466 1467 DB_PRINT_PHY_REG(reg, val); 1468 1469 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1470 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1471 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1472 1473 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1474 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1475 1476 DELAY(40); 1477 } 1478 1479 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1480 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1481 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1482 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1483 1484 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1485 DELAY(10); 1486 1487 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1488 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1489 DELAY(5); 1490 break; 1491 } 1492 } 1493 1494 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1495 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1496 __FILE__, __LINE__); 1497 1498 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1499 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1500 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1501 1502 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1503 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1504 1505 DELAY(40); 1506 } 1507 1508 return 0; 1509 } 1510 1511 1512 /****************************************************************************/ 1513 /* MII bus status change. */ 1514 /* */ 1515 /* Called by the MII bus driver when the PHY establishes link to set the */ 1516 /* MAC interface registers. */ 1517 /* */ 1518 /* Returns: */ 1519 /* Nothing. */ 1520 /****************************************************************************/ 1521 static void 1522 bce_miibus_statchg(device_t dev) 1523 { 1524 struct bce_softc *sc; 1525 struct mii_data *mii; 1526 int val; 1527 1528 sc = device_get_softc(dev); 1529 1530 DBENTER(BCE_VERBOSE_PHY); 1531 1532 mii = device_get_softc(sc->bce_miibus); 1533 1534 val = REG_RD(sc, BCE_EMAC_MODE); 1535 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1536 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1537 BCE_EMAC_MODE_25G); 1538 1539 /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1540 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1541 case IFM_10_T: 1542 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1543 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1544 val |= BCE_EMAC_MODE_PORT_MII_10; 1545 break; 1546 } 1547 /* fall-through */ 1548 case IFM_100_TX: 1549 DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1550 val |= BCE_EMAC_MODE_PORT_MII; 1551 break; 1552 case IFM_2500_SX: 1553 DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1554 val |= BCE_EMAC_MODE_25G; 1555 /* fall-through */ 1556 case IFM_1000_T: 1557 case IFM_1000_SX: 1558 DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n"); 1559 val |= BCE_EMAC_MODE_PORT_GMII; 1560 break; 1561 default: 1562 DBPRINT(sc, BCE_INFO, "Unknown speed, enabling default GMII " 1563 "interface.\n"); 1564 val |= BCE_EMAC_MODE_PORT_GMII; 1565 } 1566 1567 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1568 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1569 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1570 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1571 } else 1572 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1573 1574 REG_WR(sc, BCE_EMAC_MODE, val); 1575 1576 #if 0 1577 /* ToDo: Enable flow control support in brgphy and bge. */ 1578 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1579 if (mii->mii_media_active & IFM_FLAG0) 1580 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1581 if (mii->mii_media_active & IFM_FLAG1) 1582 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1583 #endif 1584 1585 DBEXIT(BCE_VERBOSE_PHY); 1586 } 1587 1588 1589 /****************************************************************************/ 1590 /* Acquire NVRAM lock. */ 1591 /* */ 1592 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1593 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1594 /* for use by the driver. */ 1595 /* */ 1596 /* Returns: */ 1597 /* 0 on success, positive value on failure. */ 1598 /****************************************************************************/ 1599 static int 1600 bce_acquire_nvram_lock(struct bce_softc *sc) 1601 { 1602 u32 val; 1603 int j, rc = 0; 1604 1605 DBENTER(BCE_VERBOSE_NVRAM); 1606 1607 /* Request access to the flash interface. */ 1608 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1609 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1610 val = REG_RD(sc, BCE_NVM_SW_ARB); 1611 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1612 break; 1613 1614 DELAY(5); 1615 } 1616 1617 if (j >= NVRAM_TIMEOUT_COUNT) { 1618 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1619 rc = EBUSY; 1620 } 1621 1622 DBEXIT(BCE_VERBOSE_NVRAM); 1623 return (rc); 1624 } 1625 1626 1627 /****************************************************************************/ 1628 /* Release NVRAM lock. */ 1629 /* */ 1630 /* When the caller is finished accessing NVRAM the lock must be released. */ 1631 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1632 /* for use by the driver. */ 1633 /* */ 1634 /* Returns: */ 1635 /* 0 on success, positive value on failure. */ 1636 /****************************************************************************/ 1637 static int 1638 bce_release_nvram_lock(struct bce_softc *sc) 1639 { 1640 u32 val; 1641 int j, rc = 0; 1642 1643 DBENTER(BCE_VERBOSE_NVRAM); 1644 1645 /* 1646 * Relinquish nvram interface. 1647 */ 1648 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1649 1650 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1651 val = REG_RD(sc, BCE_NVM_SW_ARB); 1652 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1653 break; 1654 1655 DELAY(5); 1656 } 1657 1658 if (j >= NVRAM_TIMEOUT_COUNT) { 1659 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1660 rc = EBUSY; 1661 } 1662 1663 DBEXIT(BCE_VERBOSE_NVRAM); 1664 return (rc); 1665 } 1666 1667 1668 #ifdef BCE_NVRAM_WRITE_SUPPORT 1669 /****************************************************************************/ 1670 /* Enable NVRAM write access. */ 1671 /* */ 1672 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1673 /* */ 1674 /* Returns: */ 1675 /* 0 on success, positive value on failure. */ 1676 /****************************************************************************/ 1677 static int 1678 bce_enable_nvram_write(struct bce_softc *sc) 1679 { 1680 u32 val; 1681 int rc = 0; 1682 1683 DBENTER(BCE_VERBOSE_NVRAM); 1684 1685 val = REG_RD(sc, BCE_MISC_CFG); 1686 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1687 1688 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1689 int j; 1690 1691 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1692 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1693 1694 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1695 DELAY(5); 1696 1697 val = REG_RD(sc, BCE_NVM_COMMAND); 1698 if (val & BCE_NVM_COMMAND_DONE) 1699 break; 1700 } 1701 1702 if (j >= NVRAM_TIMEOUT_COUNT) { 1703 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1704 rc = EBUSY; 1705 } 1706 } 1707 1708 DBENTER(BCE_VERBOSE_NVRAM); 1709 return (rc); 1710 } 1711 1712 1713 /****************************************************************************/ 1714 /* Disable NVRAM write access. */ 1715 /* */ 1716 /* When the caller is finished writing to NVRAM write access must be */ 1717 /* disabled. */ 1718 /* */ 1719 /* Returns: */ 1720 /* Nothing. */ 1721 /****************************************************************************/ 1722 static void 1723 bce_disable_nvram_write(struct bce_softc *sc) 1724 { 1725 u32 val; 1726 1727 DBENTER(BCE_VERBOSE_NVRAM); 1728 1729 val = REG_RD(sc, BCE_MISC_CFG); 1730 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1731 1732 DBEXIT(BCE_VERBOSE_NVRAM); 1733 1734 } 1735 #endif 1736 1737 1738 /****************************************************************************/ 1739 /* Enable NVRAM access. */ 1740 /* */ 1741 /* Before accessing NVRAM for read or write operations the caller must */ 1742 /* enabled NVRAM access. */ 1743 /* */ 1744 /* Returns: */ 1745 /* Nothing. */ 1746 /****************************************************************************/ 1747 static void 1748 bce_enable_nvram_access(struct bce_softc *sc) 1749 { 1750 u32 val; 1751 1752 DBENTER(BCE_VERBOSE_NVRAM); 1753 1754 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1755 /* Enable both bits, even on read. */ 1756 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1757 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1758 1759 DBEXIT(BCE_VERBOSE_NVRAM); 1760 } 1761 1762 1763 /****************************************************************************/ 1764 /* Disable NVRAM access. */ 1765 /* */ 1766 /* When the caller is finished accessing NVRAM access must be disabled. */ 1767 /* */ 1768 /* Returns: */ 1769 /* Nothing. */ 1770 /****************************************************************************/ 1771 static void 1772 bce_disable_nvram_access(struct bce_softc *sc) 1773 { 1774 u32 val; 1775 1776 DBENTER(BCE_VERBOSE_NVRAM); 1777 1778 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1779 1780 /* Disable both bits, even after read. */ 1781 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1782 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1783 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1784 1785 DBEXIT(BCE_VERBOSE_NVRAM); 1786 } 1787 1788 1789 #ifdef BCE_NVRAM_WRITE_SUPPORT 1790 /****************************************************************************/ 1791 /* Erase NVRAM page before writing. */ 1792 /* */ 1793 /* Non-buffered flash parts require that a page be erased before it is */ 1794 /* written. */ 1795 /* */ 1796 /* Returns: */ 1797 /* 0 on success, positive value on failure. */ 1798 /****************************************************************************/ 1799 static int 1800 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1801 { 1802 u32 cmd; 1803 int j, rc = 0; 1804 1805 DBENTER(BCE_VERBOSE_NVRAM); 1806 1807 /* Buffered flash doesn't require an erase. */ 1808 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 1809 goto bce_nvram_erase_page_exit; 1810 1811 /* Build an erase command. */ 1812 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1813 BCE_NVM_COMMAND_DOIT; 1814 1815 /* 1816 * Clear the DONE bit separately, set the NVRAM adress to erase, 1817 * and issue the erase command. 1818 */ 1819 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1820 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1821 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1822 1823 /* Wait for completion. */ 1824 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1825 u32 val; 1826 1827 DELAY(5); 1828 1829 val = REG_RD(sc, BCE_NVM_COMMAND); 1830 if (val & BCE_NVM_COMMAND_DONE) 1831 break; 1832 } 1833 1834 if (j >= NVRAM_TIMEOUT_COUNT) { 1835 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1836 rc = EBUSY; 1837 } 1838 1839 bce_nvram_erase_page_exit: 1840 DBEXIT(BCE_VERBOSE_NVRAM); 1841 return (rc); 1842 } 1843 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1844 1845 1846 /****************************************************************************/ 1847 /* Read a dword (32 bits) from NVRAM. */ 1848 /* */ 1849 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1850 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1851 /* */ 1852 /* Returns: */ 1853 /* 0 on success and the 32 bit value read, positive value on failure. */ 1854 /****************************************************************************/ 1855 static int 1856 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1857 u32 cmd_flags) 1858 { 1859 u32 cmd; 1860 int i, rc = 0; 1861 1862 DBENTER(BCE_EXTREME_NVRAM); 1863 1864 /* Build the command word. */ 1865 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1866 1867 /* Calculate the offset for buffered flash if translation is used. */ 1868 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 1869 offset = ((offset / sc->bce_flash_info->page_size) << 1870 sc->bce_flash_info->page_bits) + 1871 (offset % sc->bce_flash_info->page_size); 1872 } 1873 1874 /* 1875 * Clear the DONE bit separately, set the address to read, 1876 * and issue the read. 1877 */ 1878 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1879 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1880 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1881 1882 /* Wait for completion. */ 1883 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1884 u32 val; 1885 1886 DELAY(5); 1887 1888 val = REG_RD(sc, BCE_NVM_COMMAND); 1889 if (val & BCE_NVM_COMMAND_DONE) { 1890 val = REG_RD(sc, BCE_NVM_READ); 1891 1892 val = bce_be32toh(val); 1893 memcpy(ret_val, &val, 4); 1894 break; 1895 } 1896 } 1897 1898 /* Check for errors. */ 1899 if (i >= NVRAM_TIMEOUT_COUNT) { 1900 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1901 __FILE__, __LINE__, offset); 1902 rc = EBUSY; 1903 } 1904 1905 DBEXIT(BCE_EXTREME_NVRAM); 1906 return(rc); 1907 } 1908 1909 1910 #ifdef BCE_NVRAM_WRITE_SUPPORT 1911 /****************************************************************************/ 1912 /* Write a dword (32 bits) to NVRAM. */ 1913 /* */ 1914 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1915 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1916 /* enabled NVRAM write access. */ 1917 /* */ 1918 /* Returns: */ 1919 /* 0 on success, positive value on failure. */ 1920 /****************************************************************************/ 1921 static int 1922 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1923 u32 cmd_flags) 1924 { 1925 u32 cmd, val32; 1926 int j, rc = 0; 1927 1928 DBENTER(BCE_VERBOSE_NVRAM); 1929 1930 /* Build the command word. */ 1931 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1932 1933 /* Calculate the offset for buffered flash if translation is used. */ 1934 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 1935 offset = ((offset / sc->bce_flash_info->page_size) << 1936 sc->bce_flash_info->page_bits) + 1937 (offset % sc->bce_flash_info->page_size); 1938 } 1939 1940 /* 1941 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1942 * set the NVRAM address to write, and issue the write command 1943 */ 1944 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1945 memcpy(&val32, val, 4); 1946 val32 = htobe32(val32); 1947 REG_WR(sc, BCE_NVM_WRITE, val32); 1948 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1949 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1950 1951 /* Wait for completion. */ 1952 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1953 DELAY(5); 1954 1955 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1956 break; 1957 } 1958 if (j >= NVRAM_TIMEOUT_COUNT) { 1959 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1960 __FILE__, __LINE__, offset); 1961 rc = EBUSY; 1962 } 1963 1964 DBEXIT(BCE_VERBOSE_NVRAM); 1965 return (rc); 1966 } 1967 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1968 1969 1970 /****************************************************************************/ 1971 /* Initialize NVRAM access. */ 1972 /* */ 1973 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1974 /* access that device. */ 1975 /* */ 1976 /* Returns: */ 1977 /* 0 on success, positive value on failure. */ 1978 /****************************************************************************/ 1979 static int 1980 bce_init_nvram(struct bce_softc *sc) 1981 { 1982 u32 val; 1983 int j, entry_count, rc = 0; 1984 struct flash_spec *flash; 1985 1986 DBENTER(BCE_VERBOSE_NVRAM); 1987 1988 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1989 sc->bce_flash_info = &flash_5709; 1990 goto bce_init_nvram_get_flash_size; 1991 } 1992 1993 /* Determine the selected interface. */ 1994 val = REG_RD(sc, BCE_NVM_CFG1); 1995 1996 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1997 1998 /* 1999 * Flash reconfiguration is required to support additional 2000 * NVRAM devices not directly supported in hardware. 2001 * Check if the flash interface was reconfigured 2002 * by the bootcode. 2003 */ 2004 2005 if (val & 0x40000000) { 2006 /* Flash interface reconfigured by bootcode. */ 2007 2008 DBPRINT(sc,BCE_INFO_LOAD, 2009 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2010 2011 for (j = 0, flash = &flash_table[0]; j < entry_count; 2012 j++, flash++) { 2013 if ((val & FLASH_BACKUP_STRAP_MASK) == 2014 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2015 sc->bce_flash_info = flash; 2016 break; 2017 } 2018 } 2019 } else { 2020 /* Flash interface not yet reconfigured. */ 2021 u32 mask; 2022 2023 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2024 __FUNCTION__); 2025 2026 if (val & (1 << 23)) 2027 mask = FLASH_BACKUP_STRAP_MASK; 2028 else 2029 mask = FLASH_STRAP_MASK; 2030 2031 /* Look for the matching NVRAM device configuration data. */ 2032 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2033 2034 /* Check if the device matches any of the known devices. */ 2035 if ((val & mask) == (flash->strapping & mask)) { 2036 /* Found a device match. */ 2037 sc->bce_flash_info = flash; 2038 2039 /* Request access to the flash interface. */ 2040 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2041 return rc; 2042 2043 /* Reconfigure the flash interface. */ 2044 bce_enable_nvram_access(sc); 2045 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2046 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2047 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2048 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2049 bce_disable_nvram_access(sc); 2050 bce_release_nvram_lock(sc); 2051 2052 break; 2053 } 2054 } 2055 } 2056 2057 /* Check if a matching device was found. */ 2058 if (j == entry_count) { 2059 sc->bce_flash_info = NULL; 2060 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2061 __FILE__, __LINE__); 2062 rc = ENODEV; 2063 } 2064 2065 bce_init_nvram_get_flash_size: 2066 /* Write the flash config data to the shared memory interface. */ 2067 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 2068 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2069 if (val) 2070 sc->bce_flash_size = val; 2071 else 2072 sc->bce_flash_size = sc->bce_flash_info->total_size; 2073 2074 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2075 __FUNCTION__, sc->bce_flash_info->name, 2076 sc->bce_flash_info->total_size); 2077 2078 DBEXIT(BCE_VERBOSE_NVRAM); 2079 return rc; 2080 } 2081 2082 2083 /****************************************************************************/ 2084 /* Read an arbitrary range of data from NVRAM. */ 2085 /* */ 2086 /* Prepares the NVRAM interface for access and reads the requested data */ 2087 /* into the supplied buffer. */ 2088 /* */ 2089 /* Returns: */ 2090 /* 0 on success and the data read, positive value on failure. */ 2091 /****************************************************************************/ 2092 static int 2093 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2094 int buf_size) 2095 { 2096 int rc = 0; 2097 u32 cmd_flags, offset32, len32, extra; 2098 2099 DBENTER(BCE_VERBOSE_NVRAM); 2100 2101 if (buf_size == 0) 2102 goto bce_nvram_read_exit; 2103 2104 /* Request access to the flash interface. */ 2105 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2106 goto bce_nvram_read_exit; 2107 2108 /* Enable access to flash interface */ 2109 bce_enable_nvram_access(sc); 2110 2111 len32 = buf_size; 2112 offset32 = offset; 2113 extra = 0; 2114 2115 cmd_flags = 0; 2116 2117 if (offset32 & 3) { 2118 u8 buf[4]; 2119 u32 pre_len; 2120 2121 offset32 &= ~3; 2122 pre_len = 4 - (offset & 3); 2123 2124 if (pre_len >= len32) { 2125 pre_len = len32; 2126 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2127 } 2128 else { 2129 cmd_flags = BCE_NVM_COMMAND_FIRST; 2130 } 2131 2132 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2133 2134 if (rc) 2135 return rc; 2136 2137 memcpy(ret_buf, buf + (offset & 3), pre_len); 2138 2139 offset32 += 4; 2140 ret_buf += pre_len; 2141 len32 -= pre_len; 2142 } 2143 2144 if (len32 & 3) { 2145 extra = 4 - (len32 & 3); 2146 len32 = (len32 + 4) & ~3; 2147 } 2148 2149 if (len32 == 4) { 2150 u8 buf[4]; 2151 2152 if (cmd_flags) 2153 cmd_flags = BCE_NVM_COMMAND_LAST; 2154 else 2155 cmd_flags = BCE_NVM_COMMAND_FIRST | 2156 BCE_NVM_COMMAND_LAST; 2157 2158 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2159 2160 memcpy(ret_buf, buf, 4 - extra); 2161 } 2162 else if (len32 > 0) { 2163 u8 buf[4]; 2164 2165 /* Read the first word. */ 2166 if (cmd_flags) 2167 cmd_flags = 0; 2168 else 2169 cmd_flags = BCE_NVM_COMMAND_FIRST; 2170 2171 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2172 2173 /* Advance to the next dword. */ 2174 offset32 += 4; 2175 ret_buf += 4; 2176 len32 -= 4; 2177 2178 while (len32 > 4 && rc == 0) { 2179 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2180 2181 /* Advance to the next dword. */ 2182 offset32 += 4; 2183 ret_buf += 4; 2184 len32 -= 4; 2185 } 2186 2187 if (rc) 2188 goto bce_nvram_read_locked_exit; 2189 2190 cmd_flags = BCE_NVM_COMMAND_LAST; 2191 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2192 2193 memcpy(ret_buf, buf, 4 - extra); 2194 } 2195 2196 bce_nvram_read_locked_exit: 2197 /* Disable access to flash interface and release the lock. */ 2198 bce_disable_nvram_access(sc); 2199 bce_release_nvram_lock(sc); 2200 2201 bce_nvram_read_exit: 2202 DBEXIT(BCE_VERBOSE_NVRAM); 2203 return rc; 2204 } 2205 2206 2207 #ifdef BCE_NVRAM_WRITE_SUPPORT 2208 /****************************************************************************/ 2209 /* Write an arbitrary range of data from NVRAM. */ 2210 /* */ 2211 /* Prepares the NVRAM interface for write access and writes the requested */ 2212 /* data from the supplied buffer. The caller is responsible for */ 2213 /* calculating any appropriate CRCs. */ 2214 /* */ 2215 /* Returns: */ 2216 /* 0 on success, positive value on failure. */ 2217 /****************************************************************************/ 2218 static int 2219 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2220 int buf_size) 2221 { 2222 u32 written, offset32, len32; 2223 u8 *buf, start[4], end[4]; 2224 int rc = 0; 2225 int align_start, align_end; 2226 2227 DBENTER(BCE_VERBOSE_NVRAM); 2228 2229 buf = data_buf; 2230 offset32 = offset; 2231 len32 = buf_size; 2232 align_start = align_end = 0; 2233 2234 if ((align_start = (offset32 & 3))) { 2235 offset32 &= ~3; 2236 len32 += align_start; 2237 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2238 goto bce_nvram_write_exit; 2239 } 2240 2241 if (len32 & 3) { 2242 if ((len32 > 4) || !align_start) { 2243 align_end = 4 - (len32 & 3); 2244 len32 += align_end; 2245 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2246 end, 4))) { 2247 goto bce_nvram_write_exit; 2248 } 2249 } 2250 } 2251 2252 if (align_start || align_end) { 2253 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2254 if (buf == 0) { 2255 rc = ENOMEM; 2256 goto bce_nvram_write_exit; 2257 } 2258 2259 if (align_start) { 2260 memcpy(buf, start, 4); 2261 } 2262 2263 if (align_end) { 2264 memcpy(buf + len32 - 4, end, 4); 2265 } 2266 memcpy(buf + align_start, data_buf, buf_size); 2267 } 2268 2269 written = 0; 2270 while ((written < len32) && (rc == 0)) { 2271 u32 page_start, page_end, data_start, data_end; 2272 u32 addr, cmd_flags; 2273 int i; 2274 u8 flash_buffer[264]; 2275 2276 /* Find the page_start addr */ 2277 page_start = offset32 + written; 2278 page_start -= (page_start % sc->bce_flash_info->page_size); 2279 /* Find the page_end addr */ 2280 page_end = page_start + sc->bce_flash_info->page_size; 2281 /* Find the data_start addr */ 2282 data_start = (written == 0) ? offset32 : page_start; 2283 /* Find the data_end addr */ 2284 data_end = (page_end > offset32 + len32) ? 2285 (offset32 + len32) : page_end; 2286 2287 /* Request access to the flash interface. */ 2288 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2289 goto bce_nvram_write_exit; 2290 2291 /* Enable access to flash interface */ 2292 bce_enable_nvram_access(sc); 2293 2294 cmd_flags = BCE_NVM_COMMAND_FIRST; 2295 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2296 int j; 2297 2298 /* Read the whole page into the buffer 2299 * (non-buffer flash only) */ 2300 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2301 if (j == (sc->bce_flash_info->page_size - 4)) { 2302 cmd_flags |= BCE_NVM_COMMAND_LAST; 2303 } 2304 rc = bce_nvram_read_dword(sc, 2305 page_start + j, 2306 &flash_buffer[j], 2307 cmd_flags); 2308 2309 if (rc) 2310 goto bce_nvram_write_locked_exit; 2311 2312 cmd_flags = 0; 2313 } 2314 } 2315 2316 /* Enable writes to flash interface (unlock write-protect) */ 2317 if ((rc = bce_enable_nvram_write(sc)) != 0) 2318 goto bce_nvram_write_locked_exit; 2319 2320 /* Erase the page */ 2321 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2322 goto bce_nvram_write_locked_exit; 2323 2324 /* Re-enable the write again for the actual write */ 2325 bce_enable_nvram_write(sc); 2326 2327 /* Loop to write back the buffer data from page_start to 2328 * data_start */ 2329 i = 0; 2330 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2331 for (addr = page_start; addr < data_start; 2332 addr += 4, i += 4) { 2333 2334 rc = bce_nvram_write_dword(sc, addr, 2335 &flash_buffer[i], cmd_flags); 2336 2337 if (rc != 0) 2338 goto bce_nvram_write_locked_exit; 2339 2340 cmd_flags = 0; 2341 } 2342 } 2343 2344 /* Loop to write the new data from data_start to data_end */ 2345 for (addr = data_start; addr < data_end; addr += 4, i++) { 2346 if ((addr == page_end - 4) || 2347 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2348 (addr == data_end - 4))) { 2349 2350 cmd_flags |= BCE_NVM_COMMAND_LAST; 2351 } 2352 rc = bce_nvram_write_dword(sc, addr, buf, 2353 cmd_flags); 2354 2355 if (rc != 0) 2356 goto bce_nvram_write_locked_exit; 2357 2358 cmd_flags = 0; 2359 buf += 4; 2360 } 2361 2362 /* Loop to write back the buffer data from data_end 2363 * to page_end */ 2364 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2365 for (addr = data_end; addr < page_end; 2366 addr += 4, i += 4) { 2367 2368 if (addr == page_end-4) { 2369 cmd_flags = BCE_NVM_COMMAND_LAST; 2370 } 2371 rc = bce_nvram_write_dword(sc, addr, 2372 &flash_buffer[i], cmd_flags); 2373 2374 if (rc != 0) 2375 goto bce_nvram_write_locked_exit; 2376 2377 cmd_flags = 0; 2378 } 2379 } 2380 2381 /* Disable writes to flash interface (lock write-protect) */ 2382 bce_disable_nvram_write(sc); 2383 2384 /* Disable access to flash interface */ 2385 bce_disable_nvram_access(sc); 2386 bce_release_nvram_lock(sc); 2387 2388 /* Increment written */ 2389 written += data_end - data_start; 2390 } 2391 2392 goto bce_nvram_write_exit; 2393 2394 bce_nvram_write_locked_exit: 2395 bce_disable_nvram_write(sc); 2396 bce_disable_nvram_access(sc); 2397 bce_release_nvram_lock(sc); 2398 2399 bce_nvram_write_exit: 2400 if (align_start || align_end) 2401 free(buf, M_DEVBUF); 2402 2403 DBEXIT(BCE_VERBOSE_NVRAM); 2404 return (rc); 2405 } 2406 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2407 2408 2409 /****************************************************************************/ 2410 /* Verifies that NVRAM is accessible and contains valid data. */ 2411 /* */ 2412 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2413 /* correct. */ 2414 /* */ 2415 /* Returns: */ 2416 /* 0 on success, positive value on failure. */ 2417 /****************************************************************************/ 2418 static int 2419 bce_nvram_test(struct bce_softc *sc) 2420 { 2421 u32 buf[BCE_NVRAM_SIZE / 4]; 2422 u8 *data = (u8 *) buf; 2423 int rc = 0; 2424 u32 magic, csum; 2425 2426 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2427 2428 /* 2429 * Check that the device NVRAM is valid by reading 2430 * the magic value at offset 0. 2431 */ 2432 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2433 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__); 2434 goto bce_nvram_test_exit; 2435 } 2436 2437 /* 2438 * Verify that offset 0 of the NVRAM contains 2439 * a valid magic number. 2440 */ 2441 magic = bce_be32toh(buf[0]); 2442 if (magic != BCE_NVRAM_MAGIC) { 2443 rc = ENODEV; 2444 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 2445 "Found: 0x%08X\n", 2446 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2447 goto bce_nvram_test_exit; 2448 } 2449 2450 /* 2451 * Verify that the device NVRAM includes valid 2452 * configuration data. 2453 */ 2454 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2455 BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from " 2456 "NVRAM!\n", __FILE__, __LINE__); 2457 goto bce_nvram_test_exit; 2458 } 2459 2460 csum = ether_crc32_le(data, 0x100); 2461 if (csum != BCE_CRC32_RESIDUAL) { 2462 rc = ENODEV; 2463 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2464 "Expected: 0x%08X, Found: 0x%08X\n", 2465 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2466 goto bce_nvram_test_exit; 2467 } 2468 2469 csum = ether_crc32_le(data + 0x100, 0x100); 2470 if (csum != BCE_CRC32_RESIDUAL) { 2471 rc = ENODEV; 2472 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2473 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2474 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2475 } 2476 2477 bce_nvram_test_exit: 2478 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2479 return rc; 2480 } 2481 2482 2483 /****************************************************************************/ 2484 /* Identifies the current media type of the controller and sets the PHY */ 2485 /* address. */ 2486 /* */ 2487 /* Returns: */ 2488 /* Nothing. */ 2489 /****************************************************************************/ 2490 static void 2491 bce_get_media(struct bce_softc *sc) 2492 { 2493 u32 val; 2494 2495 DBENTER(BCE_VERBOSE); 2496 2497 sc->bce_phy_addr = 1; 2498 2499 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2500 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2501 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2502 u32 strap; 2503 2504 /* 2505 * The BCM5709S is software configurable 2506 * for Copper or SerDes operation. 2507 */ 2508 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2509 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for copper.\n"); 2510 goto bce_get_media_exit; 2511 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2512 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for dual media.\n"); 2513 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2514 goto bce_get_media_exit; 2515 } 2516 2517 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2518 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2519 else 2520 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2521 2522 if (pci_get_function(sc->bce_dev) == 0) { 2523 switch (strap) { 2524 case 0x4: 2525 case 0x5: 2526 case 0x6: 2527 DBPRINT(sc, BCE_INFO_LOAD, 2528 "BCM5709 s/w configured for SerDes.\n"); 2529 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2530 default: 2531 DBPRINT(sc, BCE_INFO_LOAD, 2532 "BCM5709 s/w configured for Copper.\n"); 2533 } 2534 } else { 2535 switch (strap) { 2536 case 0x1: 2537 case 0x2: 2538 case 0x4: 2539 DBPRINT(sc, BCE_INFO_LOAD, 2540 "BCM5709 s/w configured for SerDes.\n"); 2541 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2542 default: 2543 DBPRINT(sc, BCE_INFO_LOAD, 2544 "BCM5709 s/w configured for Copper.\n"); 2545 } 2546 } 2547 2548 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2549 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2550 2551 if (sc->bce_phy_flags && BCE_PHY_SERDES_FLAG) { 2552 sc->bce_flags |= BCE_NO_WOL_FLAG; 2553 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2554 sc->bce_phy_addr = 2; 2555 val = REG_RD_IND(sc, sc->bce_shmem_base + 2556 BCE_SHARED_HW_CFG_CONFIG); 2557 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2558 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 2559 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n"); 2560 } 2561 } 2562 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2563 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2564 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2565 2566 bce_get_media_exit: 2567 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2568 "Using PHY address %d.\n", sc->bce_phy_addr); 2569 2570 DBEXIT(BCE_VERBOSE); 2571 } 2572 2573 2574 /****************************************************************************/ 2575 /* Free any DMA memory owned by the driver. */ 2576 /* */ 2577 /* Scans through each data structre that requires DMA memory and frees */ 2578 /* the memory if allocated. */ 2579 /* */ 2580 /* Returns: */ 2581 /* Nothing. */ 2582 /****************************************************************************/ 2583 static void 2584 bce_dma_free(struct bce_softc *sc) 2585 { 2586 int i; 2587 2588 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2589 2590 /* Free, unmap, and destroy the status block. */ 2591 if (sc->status_block != NULL) { 2592 bus_dmamem_free( 2593 sc->status_tag, 2594 sc->status_block, 2595 sc->status_map); 2596 sc->status_block = NULL; 2597 } 2598 2599 if (sc->status_map != NULL) { 2600 bus_dmamap_unload( 2601 sc->status_tag, 2602 sc->status_map); 2603 bus_dmamap_destroy(sc->status_tag, 2604 sc->status_map); 2605 sc->status_map = NULL; 2606 } 2607 2608 if (sc->status_tag != NULL) { 2609 bus_dma_tag_destroy(sc->status_tag); 2610 sc->status_tag = NULL; 2611 } 2612 2613 2614 /* Free, unmap, and destroy the statistics block. */ 2615 if (sc->stats_block != NULL) { 2616 bus_dmamem_free( 2617 sc->stats_tag, 2618 sc->stats_block, 2619 sc->stats_map); 2620 sc->stats_block = NULL; 2621 } 2622 2623 if (sc->stats_map != NULL) { 2624 bus_dmamap_unload( 2625 sc->stats_tag, 2626 sc->stats_map); 2627 bus_dmamap_destroy(sc->stats_tag, 2628 sc->stats_map); 2629 sc->stats_map = NULL; 2630 } 2631 2632 if (sc->stats_tag != NULL) { 2633 bus_dma_tag_destroy(sc->stats_tag); 2634 sc->stats_tag = NULL; 2635 } 2636 2637 2638 /* Free, unmap and destroy all context memory pages. */ 2639 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2640 for (i = 0; i < sc->ctx_pages; i++ ) { 2641 if (sc->ctx_block[i] != NULL) { 2642 bus_dmamem_free( 2643 sc->ctx_tag, 2644 sc->ctx_block[i], 2645 sc->ctx_map[i]); 2646 sc->ctx_block[i] = NULL; 2647 } 2648 2649 if (sc->ctx_map[i] != NULL) { 2650 bus_dmamap_unload( 2651 sc->ctx_tag, 2652 sc->ctx_map[i]); 2653 bus_dmamap_destroy( 2654 sc->ctx_tag, 2655 sc->ctx_map[i]); 2656 sc->ctx_map[i] = NULL; 2657 } 2658 } 2659 2660 /* Destroy the context memory tag. */ 2661 if (sc->ctx_tag != NULL) { 2662 bus_dma_tag_destroy(sc->ctx_tag); 2663 sc->ctx_tag = NULL; 2664 } 2665 } 2666 2667 2668 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2669 for (i = 0; i < TX_PAGES; i++ ) { 2670 if (sc->tx_bd_chain[i] != NULL) { 2671 bus_dmamem_free( 2672 sc->tx_bd_chain_tag, 2673 sc->tx_bd_chain[i], 2674 sc->tx_bd_chain_map[i]); 2675 sc->tx_bd_chain[i] = NULL; 2676 } 2677 2678 if (sc->tx_bd_chain_map[i] != NULL) { 2679 bus_dmamap_unload( 2680 sc->tx_bd_chain_tag, 2681 sc->tx_bd_chain_map[i]); 2682 bus_dmamap_destroy( 2683 sc->tx_bd_chain_tag, 2684 sc->tx_bd_chain_map[i]); 2685 sc->tx_bd_chain_map[i] = NULL; 2686 } 2687 } 2688 2689 /* Destroy the TX buffer descriptor tag. */ 2690 if (sc->tx_bd_chain_tag != NULL) { 2691 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2692 sc->tx_bd_chain_tag = NULL; 2693 } 2694 2695 2696 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2697 for (i = 0; i < RX_PAGES; i++ ) { 2698 if (sc->rx_bd_chain[i] != NULL) { 2699 bus_dmamem_free( 2700 sc->rx_bd_chain_tag, 2701 sc->rx_bd_chain[i], 2702 sc->rx_bd_chain_map[i]); 2703 sc->rx_bd_chain[i] = NULL; 2704 } 2705 2706 if (sc->rx_bd_chain_map[i] != NULL) { 2707 bus_dmamap_unload( 2708 sc->rx_bd_chain_tag, 2709 sc->rx_bd_chain_map[i]); 2710 bus_dmamap_destroy( 2711 sc->rx_bd_chain_tag, 2712 sc->rx_bd_chain_map[i]); 2713 sc->rx_bd_chain_map[i] = NULL; 2714 } 2715 } 2716 2717 /* Destroy the RX buffer descriptor tag. */ 2718 if (sc->rx_bd_chain_tag != NULL) { 2719 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2720 sc->rx_bd_chain_tag = NULL; 2721 } 2722 2723 2724 #ifdef BCE_USE_SPLIT_HEADER 2725 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2726 for (i = 0; i < PG_PAGES; i++ ) { 2727 if (sc->pg_bd_chain[i] != NULL) { 2728 bus_dmamem_free( 2729 sc->pg_bd_chain_tag, 2730 sc->pg_bd_chain[i], 2731 sc->pg_bd_chain_map[i]); 2732 sc->pg_bd_chain[i] = NULL; 2733 } 2734 2735 if (sc->pg_bd_chain_map[i] != NULL) { 2736 bus_dmamap_unload( 2737 sc->pg_bd_chain_tag, 2738 sc->pg_bd_chain_map[i]); 2739 bus_dmamap_destroy( 2740 sc->pg_bd_chain_tag, 2741 sc->pg_bd_chain_map[i]); 2742 sc->pg_bd_chain_map[i] = NULL; 2743 } 2744 } 2745 2746 /* Destroy the page buffer descriptor tag. */ 2747 if (sc->pg_bd_chain_tag != NULL) { 2748 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 2749 sc->pg_bd_chain_tag = NULL; 2750 } 2751 #endif 2752 2753 2754 /* Unload and destroy the TX mbuf maps. */ 2755 for (i = 0; i < TOTAL_TX_BD; i++) { 2756 if (sc->tx_mbuf_map[i] != NULL) { 2757 bus_dmamap_unload(sc->tx_mbuf_tag, 2758 sc->tx_mbuf_map[i]); 2759 bus_dmamap_destroy(sc->tx_mbuf_tag, 2760 sc->tx_mbuf_map[i]); 2761 sc->tx_mbuf_map[i] = NULL; 2762 } 2763 } 2764 2765 /* Destroy the TX mbuf tag. */ 2766 if (sc->tx_mbuf_tag != NULL) { 2767 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2768 sc->tx_mbuf_tag = NULL; 2769 } 2770 2771 /* Unload and destroy the RX mbuf maps. */ 2772 for (i = 0; i < TOTAL_RX_BD; i++) { 2773 if (sc->rx_mbuf_map[i] != NULL) { 2774 bus_dmamap_unload(sc->rx_mbuf_tag, 2775 sc->rx_mbuf_map[i]); 2776 bus_dmamap_destroy(sc->rx_mbuf_tag, 2777 sc->rx_mbuf_map[i]); 2778 sc->rx_mbuf_map[i] = NULL; 2779 } 2780 } 2781 2782 /* Destroy the RX mbuf tag. */ 2783 if (sc->rx_mbuf_tag != NULL) { 2784 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2785 sc->rx_mbuf_tag = NULL; 2786 } 2787 2788 #ifdef BCE_USE_SPLIT_HEADER 2789 /* Unload and destroy the page mbuf maps. */ 2790 for (i = 0; i < TOTAL_PG_BD; i++) { 2791 if (sc->pg_mbuf_map[i] != NULL) { 2792 bus_dmamap_unload(sc->pg_mbuf_tag, 2793 sc->pg_mbuf_map[i]); 2794 bus_dmamap_destroy(sc->pg_mbuf_tag, 2795 sc->pg_mbuf_map[i]); 2796 sc->pg_mbuf_map[i] = NULL; 2797 } 2798 } 2799 2800 /* Destroy the page mbuf tag. */ 2801 if (sc->pg_mbuf_tag != NULL) { 2802 bus_dma_tag_destroy(sc->pg_mbuf_tag); 2803 sc->pg_mbuf_tag = NULL; 2804 } 2805 #endif 2806 2807 /* Destroy the parent tag */ 2808 if (sc->parent_tag != NULL) { 2809 bus_dma_tag_destroy(sc->parent_tag); 2810 sc->parent_tag = NULL; 2811 } 2812 2813 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2814 } 2815 2816 2817 /****************************************************************************/ 2818 /* Get DMA memory from the OS. */ 2819 /* */ 2820 /* Validates that the OS has provided DMA buffers in response to a */ 2821 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 2822 /* When the callback is used the OS will return 0 for the mapping function */ 2823 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2824 /* failures back to the caller. */ 2825 /* */ 2826 /* Returns: */ 2827 /* Nothing. */ 2828 /****************************************************************************/ 2829 static void 2830 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2831 { 2832 bus_addr_t *busaddr = arg; 2833 2834 /* Simulate a mapping failure. */ 2835 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2836 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2837 __FILE__, __LINE__); 2838 error = ENOMEM); 2839 2840 /* Check for an error and signal the caller that an error occurred. */ 2841 if (error) { 2842 printf("bce %s(%d): DMA mapping error! error = %d, " 2843 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2844 *busaddr = 0; 2845 return; 2846 } 2847 2848 *busaddr = segs->ds_addr; 2849 return; 2850 } 2851 2852 2853 /****************************************************************************/ 2854 /* Allocate any DMA memory needed by the driver. */ 2855 /* */ 2856 /* Allocates DMA memory needed for the various global structures needed by */ 2857 /* hardware. */ 2858 /* */ 2859 /* Memory alignment requirements: */ 2860 /* -----------------+----------+----------+ */ 2861 /* | 5706 | 5708 | 5709 | 5716 | */ 2862 /* -----------------+----------+----------+----------+----------+ */ 2863 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2864 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2865 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 2866 /* PG Buffers | none | none | none | none | */ 2867 /* TX Buffers | none | none | none | none | */ 2868 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 2869 /* -----------------+----------+----------+----------+----------+ */ 2870 /* */ 2871 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 2872 /* */ 2873 /* Returns: */ 2874 /* 0 for success, positive value for failure. */ 2875 /****************************************************************************/ 2876 static int 2877 bce_dma_alloc(device_t dev) 2878 { 2879 struct bce_softc *sc; 2880 int i, error, rc = 0; 2881 bus_addr_t busaddr; 2882 bus_size_t max_size, max_seg_size; 2883 int max_segments; 2884 2885 sc = device_get_softc(dev); 2886 2887 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 2888 2889 /* 2890 * Allocate the parent bus DMA tag appropriate for PCI. 2891 */ 2892 if (bus_dma_tag_create(NULL, 2893 1, 2894 BCE_DMA_BOUNDARY, 2895 sc->max_bus_addr, 2896 BUS_SPACE_MAXADDR, 2897 NULL, NULL, 2898 MAXBSIZE, 2899 BUS_SPACE_UNRESTRICTED, 2900 BUS_SPACE_MAXSIZE_32BIT, 2901 0, 2902 NULL, NULL, 2903 &sc->parent_tag)) { 2904 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 2905 __FILE__, __LINE__); 2906 rc = ENOMEM; 2907 goto bce_dma_alloc_exit; 2908 } 2909 2910 /* 2911 * Create a DMA tag for the status block, allocate and clear the 2912 * memory, map the memory into DMA space, and fetch the physical 2913 * address of the block. 2914 */ 2915 if (bus_dma_tag_create(sc->parent_tag, 2916 BCE_DMA_ALIGN, 2917 BCE_DMA_BOUNDARY, 2918 sc->max_bus_addr, 2919 BUS_SPACE_MAXADDR, 2920 NULL, NULL, 2921 BCE_STATUS_BLK_SZ, 2922 1, 2923 BCE_STATUS_BLK_SZ, 2924 0, 2925 NULL, NULL, 2926 &sc->status_tag)) { 2927 BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 2928 __FILE__, __LINE__); 2929 rc = ENOMEM; 2930 goto bce_dma_alloc_exit; 2931 } 2932 2933 if(bus_dmamem_alloc(sc->status_tag, 2934 (void **)&sc->status_block, 2935 BUS_DMA_NOWAIT, 2936 &sc->status_map)) { 2937 BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 2938 __FILE__, __LINE__); 2939 rc = ENOMEM; 2940 goto bce_dma_alloc_exit; 2941 } 2942 2943 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2944 2945 error = bus_dmamap_load(sc->status_tag, 2946 sc->status_map, 2947 sc->status_block, 2948 BCE_STATUS_BLK_SZ, 2949 bce_dma_map_addr, 2950 &busaddr, 2951 BUS_DMA_NOWAIT); 2952 2953 if (error) { 2954 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 2955 __FILE__, __LINE__); 2956 rc = ENOMEM; 2957 goto bce_dma_alloc_exit; 2958 } 2959 2960 sc->status_block_paddr = busaddr; 2961 /* DRC - Fix for 64 bit addresses. */ 2962 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2963 (u32) sc->status_block_paddr); 2964 2965 /* 2966 * Create a DMA tag for the statistics block, allocate and clear the 2967 * memory, map the memory into DMA space, and fetch the physical 2968 * address of the block. 2969 */ 2970 if (bus_dma_tag_create(sc->parent_tag, 2971 BCE_DMA_ALIGN, 2972 BCE_DMA_BOUNDARY, 2973 sc->max_bus_addr, 2974 BUS_SPACE_MAXADDR, 2975 NULL, NULL, 2976 BCE_STATS_BLK_SZ, 2977 1, 2978 BCE_STATS_BLK_SZ, 2979 0, 2980 NULL, NULL, 2981 &sc->stats_tag)) { 2982 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 2983 __FILE__, __LINE__); 2984 rc = ENOMEM; 2985 goto bce_dma_alloc_exit; 2986 } 2987 2988 if (bus_dmamem_alloc(sc->stats_tag, 2989 (void **)&sc->stats_block, 2990 BUS_DMA_NOWAIT, 2991 &sc->stats_map)) { 2992 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 2993 __FILE__, __LINE__); 2994 rc = ENOMEM; 2995 goto bce_dma_alloc_exit; 2996 } 2997 2998 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2999 3000 error = bus_dmamap_load(sc->stats_tag, 3001 sc->stats_map, 3002 sc->stats_block, 3003 BCE_STATS_BLK_SZ, 3004 bce_dma_map_addr, 3005 &busaddr, 3006 BUS_DMA_NOWAIT); 3007 3008 if(error) { 3009 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 3010 __FILE__, __LINE__); 3011 rc = ENOMEM; 3012 goto bce_dma_alloc_exit; 3013 } 3014 3015 sc->stats_block_paddr = busaddr; 3016 /* DRC - Fix for 64 bit address. */ 3017 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 3018 (u32) sc->stats_block_paddr); 3019 3020 /* BCM5709 uses host memory as cache for context memory. */ 3021 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3022 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3023 if (sc->ctx_pages == 0) 3024 sc->ctx_pages = 1; 3025 3026 DBRUNIF((sc->ctx_pages > 512), 3027 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3028 __FILE__, __LINE__, sc->ctx_pages)); 3029 3030 /* 3031 * Create a DMA tag for the context pages, 3032 * allocate and clear the memory, map the 3033 * memory into DMA space, and fetch the 3034 * physical address of the block. 3035 */ 3036 if(bus_dma_tag_create(sc->parent_tag, 3037 BCM_PAGE_SIZE, 3038 BCE_DMA_BOUNDARY, 3039 sc->max_bus_addr, 3040 BUS_SPACE_MAXADDR, 3041 NULL, NULL, 3042 BCM_PAGE_SIZE, 3043 1, 3044 BCM_PAGE_SIZE, 3045 0, 3046 NULL, NULL, 3047 &sc->ctx_tag)) { 3048 BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n", 3049 __FILE__, __LINE__); 3050 rc = ENOMEM; 3051 goto bce_dma_alloc_exit; 3052 } 3053 3054 for (i = 0; i < sc->ctx_pages; i++) { 3055 3056 if(bus_dmamem_alloc(sc->ctx_tag, 3057 (void **)&sc->ctx_block[i], 3058 BUS_DMA_NOWAIT, 3059 &sc->ctx_map[i])) { 3060 BCE_PRINTF("%s(%d): Could not allocate CTX " 3061 "DMA memory!\n", __FILE__, __LINE__); 3062 rc = ENOMEM; 3063 goto bce_dma_alloc_exit; 3064 } 3065 3066 bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE); 3067 3068 error = bus_dmamap_load(sc->ctx_tag, 3069 sc->ctx_map[i], 3070 sc->ctx_block[i], 3071 BCM_PAGE_SIZE, 3072 bce_dma_map_addr, 3073 &busaddr, 3074 BUS_DMA_NOWAIT); 3075 3076 if (error) { 3077 BCE_PRINTF("%s(%d): Could not map CTX DMA memory!\n", 3078 __FILE__, __LINE__); 3079 rc = ENOMEM; 3080 goto bce_dma_alloc_exit; 3081 } 3082 3083 sc->ctx_paddr[i] = busaddr; 3084 /* DRC - Fix for 64 bit systems. */ 3085 DBPRINT(sc, BCE_INFO, "ctx_paddr[%d] = 0x%08X\n", 3086 i, (u32) sc->ctx_paddr[i]); 3087 } 3088 } 3089 3090 /* 3091 * Create a DMA tag for the TX buffer descriptor chain, 3092 * allocate and clear the memory, and fetch the 3093 * physical address of the block. 3094 */ 3095 if(bus_dma_tag_create(sc->parent_tag, 3096 BCM_PAGE_SIZE, 3097 BCE_DMA_BOUNDARY, 3098 sc->max_bus_addr, 3099 BUS_SPACE_MAXADDR, 3100 NULL, NULL, 3101 BCE_TX_CHAIN_PAGE_SZ, 3102 1, 3103 BCE_TX_CHAIN_PAGE_SZ, 3104 0, 3105 NULL, NULL, 3106 &sc->tx_bd_chain_tag)) { 3107 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 3108 __FILE__, __LINE__); 3109 rc = ENOMEM; 3110 goto bce_dma_alloc_exit; 3111 } 3112 3113 for (i = 0; i < TX_PAGES; i++) { 3114 3115 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3116 (void **)&sc->tx_bd_chain[i], 3117 BUS_DMA_NOWAIT, 3118 &sc->tx_bd_chain_map[i])) { 3119 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3120 "chain DMA memory!\n", __FILE__, __LINE__); 3121 rc = ENOMEM; 3122 goto bce_dma_alloc_exit; 3123 } 3124 3125 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3126 sc->tx_bd_chain_map[i], 3127 sc->tx_bd_chain[i], 3128 BCE_TX_CHAIN_PAGE_SZ, 3129 bce_dma_map_addr, 3130 &busaddr, 3131 BUS_DMA_NOWAIT); 3132 3133 if (error) { 3134 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 3135 __FILE__, __LINE__); 3136 rc = ENOMEM; 3137 goto bce_dma_alloc_exit; 3138 } 3139 3140 sc->tx_bd_chain_paddr[i] = busaddr; 3141 /* DRC - Fix for 64 bit systems. */ 3142 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 3143 i, (u32) sc->tx_bd_chain_paddr[i]); 3144 } 3145 3146 /* Check the required size before mapping to conserve resources. */ 3147 if (bce_tso_enable) { 3148 max_size = BCE_TSO_MAX_SIZE; 3149 max_segments = BCE_MAX_SEGMENTS; 3150 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3151 } else { 3152 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3153 max_segments = BCE_MAX_SEGMENTS; 3154 max_seg_size = MCLBYTES; 3155 } 3156 3157 /* Create a DMA tag for TX mbufs. */ 3158 if (bus_dma_tag_create(sc->parent_tag, 3159 1, 3160 BCE_DMA_BOUNDARY, 3161 sc->max_bus_addr, 3162 BUS_SPACE_MAXADDR, 3163 NULL, NULL, 3164 max_size, 3165 max_segments, 3166 max_seg_size, 3167 0, 3168 NULL, NULL, 3169 &sc->tx_mbuf_tag)) { 3170 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3171 __FILE__, __LINE__); 3172 rc = ENOMEM; 3173 goto bce_dma_alloc_exit; 3174 } 3175 3176 /* Create DMA maps for the TX mbufs clusters. */ 3177 for (i = 0; i < TOTAL_TX_BD; i++) { 3178 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3179 &sc->tx_mbuf_map[i])) { 3180 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 3181 __FILE__, __LINE__); 3182 rc = ENOMEM; 3183 goto bce_dma_alloc_exit; 3184 } 3185 } 3186 3187 /* 3188 * Create a DMA tag for the RX buffer descriptor chain, 3189 * allocate and clear the memory, and fetch the physical 3190 * address of the blocks. 3191 */ 3192 if (bus_dma_tag_create(sc->parent_tag, 3193 BCM_PAGE_SIZE, 3194 BCE_DMA_BOUNDARY, 3195 BUS_SPACE_MAXADDR, 3196 sc->max_bus_addr, 3197 NULL, NULL, 3198 BCE_RX_CHAIN_PAGE_SZ, 3199 1, 3200 BCE_RX_CHAIN_PAGE_SZ, 3201 0, 3202 NULL, NULL, 3203 &sc->rx_bd_chain_tag)) { 3204 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 3205 __FILE__, __LINE__); 3206 rc = ENOMEM; 3207 goto bce_dma_alloc_exit; 3208 } 3209 3210 for (i = 0; i < RX_PAGES; i++) { 3211 3212 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3213 (void **)&sc->rx_bd_chain[i], 3214 BUS_DMA_NOWAIT, 3215 &sc->rx_bd_chain_map[i])) { 3216 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3217 "DMA memory!\n", __FILE__, __LINE__); 3218 rc = ENOMEM; 3219 goto bce_dma_alloc_exit; 3220 } 3221 3222 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3223 3224 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3225 sc->rx_bd_chain_map[i], 3226 sc->rx_bd_chain[i], 3227 BCE_RX_CHAIN_PAGE_SZ, 3228 bce_dma_map_addr, 3229 &busaddr, 3230 BUS_DMA_NOWAIT); 3231 3232 if (error) { 3233 BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 3234 __FILE__, __LINE__); 3235 rc = ENOMEM; 3236 goto bce_dma_alloc_exit; 3237 } 3238 3239 sc->rx_bd_chain_paddr[i] = busaddr; 3240 /* DRC - Fix for 64 bit systems. */ 3241 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 3242 i, (u32) sc->rx_bd_chain_paddr[i]); 3243 } 3244 3245 /* 3246 * Create a DMA tag for RX mbufs. 3247 */ 3248 #ifdef BCE_USE_SPLIT_HEADER 3249 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3250 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3251 #else 3252 max_size = max_seg_size = MJUM9BYTES; 3253 #endif 3254 3255 if (bus_dma_tag_create(sc->parent_tag, 3256 1, 3257 BCE_DMA_BOUNDARY, 3258 sc->max_bus_addr, 3259 BUS_SPACE_MAXADDR, 3260 NULL, NULL, 3261 max_size, 3262 1, 3263 max_seg_size, 3264 0, 3265 NULL, NULL, 3266 &sc->rx_mbuf_tag)) { 3267 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3268 __FILE__, __LINE__); 3269 rc = ENOMEM; 3270 goto bce_dma_alloc_exit; 3271 } 3272 3273 /* Create DMA maps for the RX mbuf clusters. */ 3274 for (i = 0; i < TOTAL_RX_BD; i++) { 3275 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3276 &sc->rx_mbuf_map[i])) { 3277 BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 3278 __FILE__, __LINE__); 3279 rc = ENOMEM; 3280 goto bce_dma_alloc_exit; 3281 } 3282 } 3283 3284 #ifdef BCE_USE_SPLIT_HEADER 3285 /* 3286 * Create a DMA tag for the page buffer descriptor chain, 3287 * allocate and clear the memory, and fetch the physical 3288 * address of the blocks. 3289 */ 3290 if (bus_dma_tag_create(sc->parent_tag, 3291 BCM_PAGE_SIZE, 3292 BCE_DMA_BOUNDARY, 3293 BUS_SPACE_MAXADDR, 3294 sc->max_bus_addr, 3295 NULL, NULL, 3296 BCE_PG_CHAIN_PAGE_SZ, 3297 1, 3298 BCE_PG_CHAIN_PAGE_SZ, 3299 0, 3300 NULL, NULL, 3301 &sc->pg_bd_chain_tag)) { 3302 BCE_PRINTF("%s(%d): Could not allocate page descriptor chain DMA tag!\n", 3303 __FILE__, __LINE__); 3304 rc = ENOMEM; 3305 goto bce_dma_alloc_exit; 3306 } 3307 3308 for (i = 0; i < PG_PAGES; i++) { 3309 3310 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3311 (void **)&sc->pg_bd_chain[i], 3312 BUS_DMA_NOWAIT, 3313 &sc->pg_bd_chain_map[i])) { 3314 BCE_PRINTF("%s(%d): Could not allocate page descriptor chain " 3315 "DMA memory!\n", __FILE__, __LINE__); 3316 rc = ENOMEM; 3317 goto bce_dma_alloc_exit; 3318 } 3319 3320 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 3321 3322 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3323 sc->pg_bd_chain_map[i], 3324 sc->pg_bd_chain[i], 3325 BCE_PG_CHAIN_PAGE_SZ, 3326 bce_dma_map_addr, 3327 &busaddr, 3328 BUS_DMA_NOWAIT); 3329 3330 if (error) { 3331 BCE_PRINTF("%s(%d): Could not map page descriptor chain DMA memory!\n", 3332 __FILE__, __LINE__); 3333 rc = ENOMEM; 3334 goto bce_dma_alloc_exit; 3335 } 3336 3337 sc->pg_bd_chain_paddr[i] = busaddr; 3338 /* DRC - Fix for 64 bit systems. */ 3339 DBPRINT(sc, BCE_INFO, "pg_bd_chain_paddr[%d] = 0x%08X\n", 3340 i, (u32) sc->pg_bd_chain_paddr[i]); 3341 } 3342 3343 /* 3344 * Create a DMA tag for page mbufs. 3345 */ 3346 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3347 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3348 3349 if (bus_dma_tag_create(sc->parent_tag, 3350 1, 3351 BCE_DMA_BOUNDARY, 3352 sc->max_bus_addr, 3353 BUS_SPACE_MAXADDR, 3354 NULL, NULL, 3355 max_size, 3356 1, 3357 max_seg_size, 3358 0, 3359 NULL, NULL, 3360 &sc->pg_mbuf_tag)) { 3361 BCE_PRINTF("%s(%d): Could not allocate page mbuf DMA tag!\n", 3362 __FILE__, __LINE__); 3363 rc = ENOMEM; 3364 goto bce_dma_alloc_exit; 3365 } 3366 3367 /* Create DMA maps for the page mbuf clusters. */ 3368 for (i = 0; i < TOTAL_PG_BD; i++) { 3369 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3370 &sc->pg_mbuf_map[i])) { 3371 BCE_PRINTF("%s(%d): Unable to create page mbuf DMA map!\n", 3372 __FILE__, __LINE__); 3373 rc = ENOMEM; 3374 goto bce_dma_alloc_exit; 3375 } 3376 } 3377 #endif 3378 3379 bce_dma_alloc_exit: 3380 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3381 return(rc); 3382 } 3383 3384 3385 /****************************************************************************/ 3386 /* Release all resources used by the driver. */ 3387 /* */ 3388 /* Releases all resources acquired by the driver including interrupts, */ 3389 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3390 /* */ 3391 /* Returns: */ 3392 /* Nothing. */ 3393 /****************************************************************************/ 3394 static void 3395 bce_release_resources(struct bce_softc *sc) 3396 { 3397 device_t dev; 3398 3399 DBENTER(BCE_VERBOSE_RESET); 3400 3401 dev = sc->bce_dev; 3402 3403 bce_dma_free(sc); 3404 3405 if (sc->bce_intrhand != NULL) { 3406 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3407 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3408 } 3409 3410 if (sc->bce_res_irq != NULL) { 3411 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3412 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3413 sc->bce_res_irq); 3414 } 3415 3416 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3417 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3418 pci_release_msi(dev); 3419 } 3420 3421 if (sc->bce_res_mem != NULL) { 3422 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3423 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 3424 } 3425 3426 if (sc->bce_ifp != NULL) { 3427 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3428 if_free(sc->bce_ifp); 3429 } 3430 3431 if (mtx_initialized(&sc->bce_mtx)) 3432 BCE_LOCK_DESTROY(sc); 3433 3434 DBEXIT(BCE_VERBOSE_RESET); 3435 } 3436 3437 3438 /****************************************************************************/ 3439 /* Firmware synchronization. */ 3440 /* */ 3441 /* Before performing certain events such as a chip reset, synchronize with */ 3442 /* the firmware first. */ 3443 /* */ 3444 /* Returns: */ 3445 /* 0 for success, positive value for failure. */ 3446 /****************************************************************************/ 3447 static int 3448 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3449 { 3450 int i, rc = 0; 3451 u32 val; 3452 3453 DBENTER(BCE_VERBOSE_RESET); 3454 3455 /* Don't waste any time if we've timed out before. */ 3456 if (sc->bce_fw_timed_out) { 3457 rc = EBUSY; 3458 goto bce_fw_sync_exit; 3459 } 3460 3461 /* Increment the message sequence number. */ 3462 sc->bce_fw_wr_seq++; 3463 msg_data |= sc->bce_fw_wr_seq; 3464 3465 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", 3466 msg_data); 3467 3468 /* Send the message to the bootcode driver mailbox. */ 3469 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 3470 3471 /* Wait for the bootcode to acknowledge the message. */ 3472 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3473 /* Check for a response in the bootcode firmware mailbox. */ 3474 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 3475 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3476 break; 3477 DELAY(1000); 3478 } 3479 3480 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 3481 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3482 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3483 3484 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3485 "msg_data = 0x%08X\n", 3486 __FILE__, __LINE__, msg_data); 3487 3488 msg_data &= ~BCE_DRV_MSG_CODE; 3489 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3490 3491 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 3492 3493 sc->bce_fw_timed_out = 1; 3494 rc = EBUSY; 3495 } 3496 3497 bce_fw_sync_exit: 3498 DBEXIT(BCE_VERBOSE_RESET); 3499 return (rc); 3500 } 3501 3502 3503 /****************************************************************************/ 3504 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3505 /* */ 3506 /* Returns: */ 3507 /* Nothing. */ 3508 /****************************************************************************/ 3509 static void 3510 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3511 u32 rv2p_code_len, u32 rv2p_proc) 3512 { 3513 int i; 3514 u32 val; 3515 3516 DBENTER(BCE_VERBOSE_RESET); 3517 3518 /* Set the page size used by RV2P. */ 3519 if (rv2p_proc == RV2P_PROC2) { 3520 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3521 } 3522 3523 for (i = 0; i < rv2p_code_len; i += 8) { 3524 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3525 rv2p_code++; 3526 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3527 rv2p_code++; 3528 3529 if (rv2p_proc == RV2P_PROC1) { 3530 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3531 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3532 } 3533 else { 3534 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3535 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3536 } 3537 } 3538 3539 /* Reset the processor, un-stall is done later. */ 3540 if (rv2p_proc == RV2P_PROC1) { 3541 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3542 } 3543 else { 3544 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3545 } 3546 3547 DBEXIT(BCE_VERBOSE_RESET); 3548 } 3549 3550 3551 /****************************************************************************/ 3552 /* Load RISC processor firmware. */ 3553 /* */ 3554 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3555 /* associated with a particular processor. */ 3556 /* */ 3557 /* Returns: */ 3558 /* Nothing. */ 3559 /****************************************************************************/ 3560 static void 3561 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3562 struct fw_info *fw) 3563 { 3564 u32 offset; 3565 u32 val; 3566 3567 DBENTER(BCE_VERBOSE_RESET); 3568 3569 /* Halt the CPU. */ 3570 val = REG_RD_IND(sc, cpu_reg->mode); 3571 val |= cpu_reg->mode_value_halt; 3572 REG_WR_IND(sc, cpu_reg->mode, val); 3573 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3574 3575 /* Load the Text area. */ 3576 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3577 if (fw->text) { 3578 int j; 3579 3580 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3581 REG_WR_IND(sc, offset, fw->text[j]); 3582 } 3583 } 3584 3585 /* Load the Data area. */ 3586 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3587 if (fw->data) { 3588 int j; 3589 3590 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3591 REG_WR_IND(sc, offset, fw->data[j]); 3592 } 3593 } 3594 3595 /* Load the SBSS area. */ 3596 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3597 if (fw->sbss) { 3598 int j; 3599 3600 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3601 REG_WR_IND(sc, offset, fw->sbss[j]); 3602 } 3603 } 3604 3605 /* Load the BSS area. */ 3606 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3607 if (fw->bss) { 3608 int j; 3609 3610 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3611 REG_WR_IND(sc, offset, fw->bss[j]); 3612 } 3613 } 3614 3615 /* Load the Read-Only area. */ 3616 offset = cpu_reg->spad_base + 3617 (fw->rodata_addr - cpu_reg->mips_view_base); 3618 if (fw->rodata) { 3619 int j; 3620 3621 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3622 REG_WR_IND(sc, offset, fw->rodata[j]); 3623 } 3624 } 3625 3626 /* Clear the pre-fetch instruction. */ 3627 REG_WR_IND(sc, cpu_reg->inst, 0); 3628 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3629 3630 /* Start the CPU. */ 3631 val = REG_RD_IND(sc, cpu_reg->mode); 3632 val &= ~cpu_reg->mode_value_halt; 3633 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3634 REG_WR_IND(sc, cpu_reg->mode, val); 3635 3636 DBEXIT(BCE_VERBOSE_RESET); 3637 } 3638 3639 3640 /****************************************************************************/ 3641 /* Initialize the RX CPU. */ 3642 /* */ 3643 /* Returns: */ 3644 /* Nothing. */ 3645 /****************************************************************************/ 3646 static void 3647 bce_init_rxp_cpu(struct bce_softc *sc) 3648 { 3649 struct cpu_reg cpu_reg; 3650 struct fw_info fw; 3651 3652 DBENTER(BCE_VERBOSE_RESET); 3653 3654 cpu_reg.mode = BCE_RXP_CPU_MODE; 3655 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3656 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3657 cpu_reg.state = BCE_RXP_CPU_STATE; 3658 cpu_reg.state_value_clear = 0xffffff; 3659 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3660 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3661 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3662 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3663 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3664 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3665 cpu_reg.mips_view_base = 0x8000000; 3666 3667 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3668 fw.ver_major = bce_RXP_b09FwReleaseMajor; 3669 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3670 fw.ver_fix = bce_RXP_b09FwReleaseFix; 3671 fw.start_addr = bce_RXP_b09FwStartAddr; 3672 3673 fw.text_addr = bce_RXP_b09FwTextAddr; 3674 fw.text_len = bce_RXP_b09FwTextLen; 3675 fw.text_index = 0; 3676 fw.text = bce_RXP_b09FwText; 3677 3678 fw.data_addr = bce_RXP_b09FwDataAddr; 3679 fw.data_len = bce_RXP_b09FwDataLen; 3680 fw.data_index = 0; 3681 fw.data = bce_RXP_b09FwData; 3682 3683 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3684 fw.sbss_len = bce_RXP_b09FwSbssLen; 3685 fw.sbss_index = 0; 3686 fw.sbss = bce_RXP_b09FwSbss; 3687 3688 fw.bss_addr = bce_RXP_b09FwBssAddr; 3689 fw.bss_len = bce_RXP_b09FwBssLen; 3690 fw.bss_index = 0; 3691 fw.bss = bce_RXP_b09FwBss; 3692 3693 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3694 fw.rodata_len = bce_RXP_b09FwRodataLen; 3695 fw.rodata_index = 0; 3696 fw.rodata = bce_RXP_b09FwRodata; 3697 } else { 3698 fw.ver_major = bce_RXP_b06FwReleaseMajor; 3699 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3700 fw.ver_fix = bce_RXP_b06FwReleaseFix; 3701 fw.start_addr = bce_RXP_b06FwStartAddr; 3702 3703 fw.text_addr = bce_RXP_b06FwTextAddr; 3704 fw.text_len = bce_RXP_b06FwTextLen; 3705 fw.text_index = 0; 3706 fw.text = bce_RXP_b06FwText; 3707 3708 fw.data_addr = bce_RXP_b06FwDataAddr; 3709 fw.data_len = bce_RXP_b06FwDataLen; 3710 fw.data_index = 0; 3711 fw.data = bce_RXP_b06FwData; 3712 3713 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3714 fw.sbss_len = bce_RXP_b06FwSbssLen; 3715 fw.sbss_index = 0; 3716 fw.sbss = bce_RXP_b06FwSbss; 3717 3718 fw.bss_addr = bce_RXP_b06FwBssAddr; 3719 fw.bss_len = bce_RXP_b06FwBssLen; 3720 fw.bss_index = 0; 3721 fw.bss = bce_RXP_b06FwBss; 3722 3723 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3724 fw.rodata_len = bce_RXP_b06FwRodataLen; 3725 fw.rodata_index = 0; 3726 fw.rodata = bce_RXP_b06FwRodata; 3727 } 3728 3729 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3730 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3731 3732 DBEXIT(BCE_VERBOSE_RESET); 3733 } 3734 3735 3736 /****************************************************************************/ 3737 /* Initialize the TX CPU. */ 3738 /* */ 3739 /* Returns: */ 3740 /* Nothing. */ 3741 /****************************************************************************/ 3742 static void 3743 bce_init_txp_cpu(struct bce_softc *sc) 3744 { 3745 struct cpu_reg cpu_reg; 3746 struct fw_info fw; 3747 3748 DBENTER(BCE_VERBOSE_RESET); 3749 3750 cpu_reg.mode = BCE_TXP_CPU_MODE; 3751 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3752 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3753 cpu_reg.state = BCE_TXP_CPU_STATE; 3754 cpu_reg.state_value_clear = 0xffffff; 3755 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3756 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3757 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3758 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3759 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3760 cpu_reg.spad_base = BCE_TXP_SCRATCH; 3761 cpu_reg.mips_view_base = 0x8000000; 3762 3763 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3764 fw.ver_major = bce_TXP_b09FwReleaseMajor; 3765 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3766 fw.ver_fix = bce_TXP_b09FwReleaseFix; 3767 fw.start_addr = bce_TXP_b09FwStartAddr; 3768 3769 fw.text_addr = bce_TXP_b09FwTextAddr; 3770 fw.text_len = bce_TXP_b09FwTextLen; 3771 fw.text_index = 0; 3772 fw.text = bce_TXP_b09FwText; 3773 3774 fw.data_addr = bce_TXP_b09FwDataAddr; 3775 fw.data_len = bce_TXP_b09FwDataLen; 3776 fw.data_index = 0; 3777 fw.data = bce_TXP_b09FwData; 3778 3779 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3780 fw.sbss_len = bce_TXP_b09FwSbssLen; 3781 fw.sbss_index = 0; 3782 fw.sbss = bce_TXP_b09FwSbss; 3783 3784 fw.bss_addr = bce_TXP_b09FwBssAddr; 3785 fw.bss_len = bce_TXP_b09FwBssLen; 3786 fw.bss_index = 0; 3787 fw.bss = bce_TXP_b09FwBss; 3788 3789 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 3790 fw.rodata_len = bce_TXP_b09FwRodataLen; 3791 fw.rodata_index = 0; 3792 fw.rodata = bce_TXP_b09FwRodata; 3793 } else { 3794 fw.ver_major = bce_TXP_b06FwReleaseMajor; 3795 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 3796 fw.ver_fix = bce_TXP_b06FwReleaseFix; 3797 fw.start_addr = bce_TXP_b06FwStartAddr; 3798 3799 fw.text_addr = bce_TXP_b06FwTextAddr; 3800 fw.text_len = bce_TXP_b06FwTextLen; 3801 fw.text_index = 0; 3802 fw.text = bce_TXP_b06FwText; 3803 3804 fw.data_addr = bce_TXP_b06FwDataAddr; 3805 fw.data_len = bce_TXP_b06FwDataLen; 3806 fw.data_index = 0; 3807 fw.data = bce_TXP_b06FwData; 3808 3809 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 3810 fw.sbss_len = bce_TXP_b06FwSbssLen; 3811 fw.sbss_index = 0; 3812 fw.sbss = bce_TXP_b06FwSbss; 3813 3814 fw.bss_addr = bce_TXP_b06FwBssAddr; 3815 fw.bss_len = bce_TXP_b06FwBssLen; 3816 fw.bss_index = 0; 3817 fw.bss = bce_TXP_b06FwBss; 3818 3819 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 3820 fw.rodata_len = bce_TXP_b06FwRodataLen; 3821 fw.rodata_index = 0; 3822 fw.rodata = bce_TXP_b06FwRodata; 3823 } 3824 3825 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 3826 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3827 3828 DBEXIT(BCE_VERBOSE_RESET); 3829 } 3830 3831 3832 /****************************************************************************/ 3833 /* Initialize the TPAT CPU. */ 3834 /* */ 3835 /* Returns: */ 3836 /* Nothing. */ 3837 /****************************************************************************/ 3838 static void 3839 bce_init_tpat_cpu(struct bce_softc *sc) 3840 { 3841 struct cpu_reg cpu_reg; 3842 struct fw_info fw; 3843 3844 DBENTER(BCE_VERBOSE_RESET); 3845 3846 cpu_reg.mode = BCE_TPAT_CPU_MODE; 3847 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 3848 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 3849 cpu_reg.state = BCE_TPAT_CPU_STATE; 3850 cpu_reg.state_value_clear = 0xffffff; 3851 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 3852 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 3853 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 3854 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 3855 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 3856 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 3857 cpu_reg.mips_view_base = 0x8000000; 3858 3859 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3860 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 3861 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 3862 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 3863 fw.start_addr = bce_TPAT_b09FwStartAddr; 3864 3865 fw.text_addr = bce_TPAT_b09FwTextAddr; 3866 fw.text_len = bce_TPAT_b09FwTextLen; 3867 fw.text_index = 0; 3868 fw.text = bce_TPAT_b09FwText; 3869 3870 fw.data_addr = bce_TPAT_b09FwDataAddr; 3871 fw.data_len = bce_TPAT_b09FwDataLen; 3872 fw.data_index = 0; 3873 fw.data = bce_TPAT_b09FwData; 3874 3875 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 3876 fw.sbss_len = bce_TPAT_b09FwSbssLen; 3877 fw.sbss_index = 0; 3878 fw.sbss = bce_TPAT_b09FwSbss; 3879 3880 fw.bss_addr = bce_TPAT_b09FwBssAddr; 3881 fw.bss_len = bce_TPAT_b09FwBssLen; 3882 fw.bss_index = 0; 3883 fw.bss = bce_TPAT_b09FwBss; 3884 3885 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 3886 fw.rodata_len = bce_TPAT_b09FwRodataLen; 3887 fw.rodata_index = 0; 3888 fw.rodata = bce_TPAT_b09FwRodata; 3889 } else { 3890 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 3891 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 3892 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 3893 fw.start_addr = bce_TPAT_b06FwStartAddr; 3894 3895 fw.text_addr = bce_TPAT_b06FwTextAddr; 3896 fw.text_len = bce_TPAT_b06FwTextLen; 3897 fw.text_index = 0; 3898 fw.text = bce_TPAT_b06FwText; 3899 3900 fw.data_addr = bce_TPAT_b06FwDataAddr; 3901 fw.data_len = bce_TPAT_b06FwDataLen; 3902 fw.data_index = 0; 3903 fw.data = bce_TPAT_b06FwData; 3904 3905 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 3906 fw.sbss_len = bce_TPAT_b06FwSbssLen; 3907 fw.sbss_index = 0; 3908 fw.sbss = bce_TPAT_b06FwSbss; 3909 3910 fw.bss_addr = bce_TPAT_b06FwBssAddr; 3911 fw.bss_len = bce_TPAT_b06FwBssLen; 3912 fw.bss_index = 0; 3913 fw.bss = bce_TPAT_b06FwBss; 3914 3915 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 3916 fw.rodata_len = bce_TPAT_b06FwRodataLen; 3917 fw.rodata_index = 0; 3918 fw.rodata = bce_TPAT_b06FwRodata; 3919 } 3920 3921 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 3922 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3923 3924 DBEXIT(BCE_VERBOSE_RESET); 3925 } 3926 3927 3928 /****************************************************************************/ 3929 /* Initialize the CP CPU. */ 3930 /* */ 3931 /* Returns: */ 3932 /* Nothing. */ 3933 /****************************************************************************/ 3934 static void 3935 bce_init_cp_cpu(struct bce_softc *sc) 3936 { 3937 struct cpu_reg cpu_reg; 3938 struct fw_info fw; 3939 3940 DBENTER(BCE_VERBOSE_RESET); 3941 3942 cpu_reg.mode = BCE_CP_CPU_MODE; 3943 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 3944 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 3945 cpu_reg.state = BCE_CP_CPU_STATE; 3946 cpu_reg.state_value_clear = 0xffffff; 3947 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 3948 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 3949 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 3950 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 3951 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 3952 cpu_reg.spad_base = BCE_CP_SCRATCH; 3953 cpu_reg.mips_view_base = 0x8000000; 3954 3955 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3956 fw.ver_major = bce_CP_b09FwReleaseMajor; 3957 fw.ver_minor = bce_CP_b09FwReleaseMinor; 3958 fw.ver_fix = bce_CP_b09FwReleaseFix; 3959 fw.start_addr = bce_CP_b09FwStartAddr; 3960 3961 fw.text_addr = bce_CP_b09FwTextAddr; 3962 fw.text_len = bce_CP_b09FwTextLen; 3963 fw.text_index = 0; 3964 fw.text = bce_CP_b09FwText; 3965 3966 fw.data_addr = bce_CP_b09FwDataAddr; 3967 fw.data_len = bce_CP_b09FwDataLen; 3968 fw.data_index = 0; 3969 fw.data = bce_CP_b09FwData; 3970 3971 fw.sbss_addr = bce_CP_b09FwSbssAddr; 3972 fw.sbss_len = bce_CP_b09FwSbssLen; 3973 fw.sbss_index = 0; 3974 fw.sbss = bce_CP_b09FwSbss; 3975 3976 fw.bss_addr = bce_CP_b09FwBssAddr; 3977 fw.bss_len = bce_CP_b09FwBssLen; 3978 fw.bss_index = 0; 3979 fw.bss = bce_CP_b09FwBss; 3980 3981 fw.rodata_addr = bce_CP_b09FwRodataAddr; 3982 fw.rodata_len = bce_CP_b09FwRodataLen; 3983 fw.rodata_index = 0; 3984 fw.rodata = bce_CP_b09FwRodata; 3985 } else { 3986 fw.ver_major = bce_CP_b06FwReleaseMajor; 3987 fw.ver_minor = bce_CP_b06FwReleaseMinor; 3988 fw.ver_fix = bce_CP_b06FwReleaseFix; 3989 fw.start_addr = bce_CP_b06FwStartAddr; 3990 3991 fw.text_addr = bce_CP_b06FwTextAddr; 3992 fw.text_len = bce_CP_b06FwTextLen; 3993 fw.text_index = 0; 3994 fw.text = bce_CP_b06FwText; 3995 3996 fw.data_addr = bce_CP_b06FwDataAddr; 3997 fw.data_len = bce_CP_b06FwDataLen; 3998 fw.data_index = 0; 3999 fw.data = bce_CP_b06FwData; 4000 4001 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4002 fw.sbss_len = bce_CP_b06FwSbssLen; 4003 fw.sbss_index = 0; 4004 fw.sbss = bce_CP_b06FwSbss; 4005 4006 fw.bss_addr = bce_CP_b06FwBssAddr; 4007 fw.bss_len = bce_CP_b06FwBssLen; 4008 fw.bss_index = 0; 4009 fw.bss = bce_CP_b06FwBss; 4010 4011 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4012 fw.rodata_len = bce_CP_b06FwRodataLen; 4013 fw.rodata_index = 0; 4014 fw.rodata = bce_CP_b06FwRodata; 4015 } 4016 4017 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4018 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4019 4020 DBEXIT(BCE_VERBOSE_RESET); 4021 } 4022 4023 4024 /****************************************************************************/ 4025 /* Initialize the COM CPU. */ 4026 /* */ 4027 /* Returns: */ 4028 /* Nothing. */ 4029 /****************************************************************************/ 4030 static void 4031 bce_init_com_cpu(struct bce_softc *sc) 4032 { 4033 struct cpu_reg cpu_reg; 4034 struct fw_info fw; 4035 4036 DBENTER(BCE_VERBOSE_RESET); 4037 4038 cpu_reg.mode = BCE_COM_CPU_MODE; 4039 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4040 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4041 cpu_reg.state = BCE_COM_CPU_STATE; 4042 cpu_reg.state_value_clear = 0xffffff; 4043 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4044 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4045 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4046 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4047 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4048 cpu_reg.spad_base = BCE_COM_SCRATCH; 4049 cpu_reg.mips_view_base = 0x8000000; 4050 4051 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4052 fw.ver_major = bce_COM_b09FwReleaseMajor; 4053 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4054 fw.ver_fix = bce_COM_b09FwReleaseFix; 4055 fw.start_addr = bce_COM_b09FwStartAddr; 4056 4057 fw.text_addr = bce_COM_b09FwTextAddr; 4058 fw.text_len = bce_COM_b09FwTextLen; 4059 fw.text_index = 0; 4060 fw.text = bce_COM_b09FwText; 4061 4062 fw.data_addr = bce_COM_b09FwDataAddr; 4063 fw.data_len = bce_COM_b09FwDataLen; 4064 fw.data_index = 0; 4065 fw.data = bce_COM_b09FwData; 4066 4067 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4068 fw.sbss_len = bce_COM_b09FwSbssLen; 4069 fw.sbss_index = 0; 4070 fw.sbss = bce_COM_b09FwSbss; 4071 4072 fw.bss_addr = bce_COM_b09FwBssAddr; 4073 fw.bss_len = bce_COM_b09FwBssLen; 4074 fw.bss_index = 0; 4075 fw.bss = bce_COM_b09FwBss; 4076 4077 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4078 fw.rodata_len = bce_COM_b09FwRodataLen; 4079 fw.rodata_index = 0; 4080 fw.rodata = bce_COM_b09FwRodata; 4081 } else { 4082 fw.ver_major = bce_COM_b06FwReleaseMajor; 4083 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4084 fw.ver_fix = bce_COM_b06FwReleaseFix; 4085 fw.start_addr = bce_COM_b06FwStartAddr; 4086 4087 fw.text_addr = bce_COM_b06FwTextAddr; 4088 fw.text_len = bce_COM_b06FwTextLen; 4089 fw.text_index = 0; 4090 fw.text = bce_COM_b06FwText; 4091 4092 fw.data_addr = bce_COM_b06FwDataAddr; 4093 fw.data_len = bce_COM_b06FwDataLen; 4094 fw.data_index = 0; 4095 fw.data = bce_COM_b06FwData; 4096 4097 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4098 fw.sbss_len = bce_COM_b06FwSbssLen; 4099 fw.sbss_index = 0; 4100 fw.sbss = bce_COM_b06FwSbss; 4101 4102 fw.bss_addr = bce_COM_b06FwBssAddr; 4103 fw.bss_len = bce_COM_b06FwBssLen; 4104 fw.bss_index = 0; 4105 fw.bss = bce_COM_b06FwBss; 4106 4107 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4108 fw.rodata_len = bce_COM_b06FwRodataLen; 4109 fw.rodata_index = 0; 4110 fw.rodata = bce_COM_b06FwRodata; 4111 } 4112 4113 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4114 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4115 4116 DBEXIT(BCE_VERBOSE_RESET); 4117 } 4118 4119 4120 /****************************************************************************/ 4121 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4122 /* */ 4123 /* Loads the firmware for each CPU and starts the CPU. */ 4124 /* */ 4125 /* Returns: */ 4126 /* Nothing. */ 4127 /****************************************************************************/ 4128 static void 4129 bce_init_cpus(struct bce_softc *sc) 4130 { 4131 DBENTER(BCE_VERBOSE_RESET); 4132 4133 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4134 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1), 4135 RV2P_PROC1); 4136 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2), 4137 RV2P_PROC2); 4138 } else { 4139 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), 4140 RV2P_PROC1); 4141 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), 4142 RV2P_PROC2); 4143 } 4144 4145 bce_init_rxp_cpu(sc); 4146 bce_init_txp_cpu(sc); 4147 bce_init_tpat_cpu(sc); 4148 bce_init_com_cpu(sc); 4149 bce_init_cp_cpu(sc); 4150 4151 DBEXIT(BCE_VERBOSE_RESET); 4152 } 4153 4154 4155 /****************************************************************************/ 4156 /* Initialize context memory. */ 4157 /* */ 4158 /* Clears the memory associated with each Context ID (CID). */ 4159 /* */ 4160 /* Returns: */ 4161 /* Nothing. */ 4162 /****************************************************************************/ 4163 static void 4164 bce_init_ctx(struct bce_softc *sc) 4165 { 4166 4167 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4168 4169 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4170 /* DRC: Replace this constant value with a #define. */ 4171 int i, retry_cnt = 10; 4172 u32 val; 4173 4174 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4175 4176 /* 4177 * BCM5709 context memory may be cached 4178 * in host memory so prepare the host memory 4179 * for access. 4180 */ 4181 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4182 val |= (BCM_PAGE_BITS - 8) << 16; 4183 REG_WR(sc, BCE_CTX_COMMAND, val); 4184 4185 /* Wait for mem init command to complete. */ 4186 for (i = 0; i < retry_cnt; i++) { 4187 val = REG_RD(sc, BCE_CTX_COMMAND); 4188 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4189 break; 4190 DELAY(2); 4191 } 4192 4193 /* ToDo: Consider returning an error here. */ 4194 DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT), 4195 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4196 __FUNCTION__)); 4197 4198 for (i = 0; i < sc->ctx_pages; i++) { 4199 int j; 4200 4201 /* Set the physical address of the context memory cache. */ 4202 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4203 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4204 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4205 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4206 BCE_ADDR_HI(sc->ctx_paddr[i])); 4207 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4208 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4209 4210 /* Verify that the context memory write was successful. */ 4211 for (j = 0; j < retry_cnt; j++) { 4212 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4213 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4214 break; 4215 DELAY(5); 4216 } 4217 4218 /* ToDo: Consider returning an error here. */ 4219 DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ), 4220 BCE_PRINTF("%s(): Failed to initialize context page %d!\n", 4221 __FUNCTION__, i)); 4222 } 4223 } else { 4224 u32 vcid_addr, offset; 4225 4226 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4227 4228 /* 4229 * For the 5706/5708, context memory is local to 4230 * the controller, so initialize the controller 4231 * context memory. 4232 */ 4233 4234 vcid_addr = GET_CID_ADDR(96); 4235 while (vcid_addr) { 4236 4237 vcid_addr -= PHY_CTX_SIZE; 4238 4239 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4240 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4241 4242 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4243 CTX_WR(sc, 0x00, offset, 0); 4244 } 4245 4246 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4247 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4248 } 4249 4250 } 4251 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4252 } 4253 4254 4255 /****************************************************************************/ 4256 /* Fetch the permanent MAC address of the controller. */ 4257 /* */ 4258 /* Returns: */ 4259 /* Nothing. */ 4260 /****************************************************************************/ 4261 static void 4262 bce_get_mac_addr(struct bce_softc *sc) 4263 { 4264 u32 mac_lo = 0, mac_hi = 0; 4265 4266 DBENTER(BCE_VERBOSE_RESET); 4267 /* 4268 * The NetXtreme II bootcode populates various NIC 4269 * power-on and runtime configuration items in a 4270 * shared memory area. The factory configured MAC 4271 * address is available from both NVRAM and the 4272 * shared memory area so we'll read the value from 4273 * shared memory for speed. 4274 */ 4275 4276 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 4277 BCE_PORT_HW_CFG_MAC_UPPER); 4278 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 4279 BCE_PORT_HW_CFG_MAC_LOWER); 4280 4281 if ((mac_lo == 0) && (mac_hi == 0)) { 4282 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4283 __FILE__, __LINE__); 4284 } else { 4285 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4286 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4287 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4288 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4289 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4290 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4291 } 4292 4293 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 4294 DBEXIT(BCE_VERBOSE_RESET); 4295 } 4296 4297 4298 /****************************************************************************/ 4299 /* Program the MAC address. */ 4300 /* */ 4301 /* Returns: */ 4302 /* Nothing. */ 4303 /****************************************************************************/ 4304 static void 4305 bce_set_mac_addr(struct bce_softc *sc) 4306 { 4307 u32 val; 4308 u8 *mac_addr = sc->eaddr; 4309 4310 /* ToDo: Add support for setting multiple MAC addresses. */ 4311 4312 DBENTER(BCE_VERBOSE_RESET); 4313 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 4314 4315 val = (mac_addr[0] << 8) | mac_addr[1]; 4316 4317 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4318 4319 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4320 (mac_addr[4] << 8) | mac_addr[5]; 4321 4322 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4323 4324 DBEXIT(BCE_VERBOSE_RESET); 4325 } 4326 4327 4328 /****************************************************************************/ 4329 /* Stop the controller. */ 4330 /* */ 4331 /* Returns: */ 4332 /* Nothing. */ 4333 /****************************************************************************/ 4334 static void 4335 bce_stop(struct bce_softc *sc) 4336 { 4337 struct ifnet *ifp; 4338 struct ifmedia_entry *ifm; 4339 struct mii_data *mii = NULL; 4340 int mtmp, itmp; 4341 4342 DBENTER(BCE_VERBOSE_RESET); 4343 4344 BCE_LOCK_ASSERT(sc); 4345 4346 ifp = sc->bce_ifp; 4347 4348 mii = device_get_softc(sc->bce_miibus); 4349 4350 callout_stop(&sc->bce_tick_callout); 4351 4352 /* Disable the transmit/receive blocks. */ 4353 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4354 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4355 DELAY(20); 4356 4357 bce_disable_intr(sc); 4358 4359 /* Free RX buffers. */ 4360 #ifdef BCE_USE_SPLIT_HEADER 4361 bce_free_pg_chain(sc); 4362 #endif 4363 bce_free_rx_chain(sc); 4364 4365 /* Free TX buffers. */ 4366 bce_free_tx_chain(sc); 4367 4368 /* 4369 * Isolate/power down the PHY, but leave the media selection 4370 * unchanged so that things will be put back to normal when 4371 * we bring the interface back up. 4372 */ 4373 4374 itmp = ifp->if_flags; 4375 ifp->if_flags |= IFF_UP; 4376 4377 /* If we are called from bce_detach(), mii is already NULL. */ 4378 if (mii != NULL) { 4379 ifm = mii->mii_media.ifm_cur; 4380 mtmp = ifm->ifm_media; 4381 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4382 mii_mediachg(mii); 4383 ifm->ifm_media = mtmp; 4384 } 4385 4386 ifp->if_flags = itmp; 4387 sc->watchdog_timer = 0; 4388 4389 sc->bce_link = 0; 4390 4391 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4392 4393 DBEXIT(BCE_VERBOSE_RESET); 4394 } 4395 4396 4397 static int 4398 bce_reset(struct bce_softc *sc, u32 reset_code) 4399 { 4400 u32 val; 4401 int i, rc = 0; 4402 4403 DBENTER(BCE_VERBOSE_RESET); 4404 4405 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4406 __FUNCTION__, reset_code); 4407 4408 /* Wait for pending PCI transactions to complete. */ 4409 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4410 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4411 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4412 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4413 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4414 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4415 DELAY(5); 4416 4417 /* Disable DMA */ 4418 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4419 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4420 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4421 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4422 } 4423 4424 /* Assume bootcode is running. */ 4425 sc->bce_fw_timed_out = 0; 4426 4427 /* Give the firmware a chance to prepare for the reset. */ 4428 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4429 if (rc) 4430 goto bce_reset_exit; 4431 4432 /* Set a firmware reminder that this is a soft reset. */ 4433 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 4434 BCE_DRV_RESET_SIGNATURE_MAGIC); 4435 4436 /* Dummy read to force the chip to complete all current transactions. */ 4437 val = REG_RD(sc, BCE_MISC_ID); 4438 4439 /* Chip reset. */ 4440 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4441 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4442 REG_RD(sc, BCE_MISC_COMMAND); 4443 DELAY(5); 4444 4445 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4446 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4447 4448 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4449 } else { 4450 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4451 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4452 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4453 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4454 4455 /* Allow up to 30us for reset to complete. */ 4456 for (i = 0; i < 10; i++) { 4457 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4458 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4459 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4460 break; 4461 } 4462 DELAY(10); 4463 } 4464 4465 /* Check that reset completed successfully. */ 4466 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4467 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4468 BCE_PRINTF("%s(%d): Reset failed!\n", 4469 __FILE__, __LINE__); 4470 rc = EBUSY; 4471 goto bce_reset_exit; 4472 } 4473 } 4474 4475 /* Make sure byte swapping is properly configured. */ 4476 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4477 if (val != 0x01020304) { 4478 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4479 __FILE__, __LINE__); 4480 rc = ENODEV; 4481 goto bce_reset_exit; 4482 } 4483 4484 /* Just completed a reset, assume that firmware is running again. */ 4485 sc->bce_fw_timed_out = 0; 4486 4487 /* Wait for the firmware to finish its initialization. */ 4488 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4489 if (rc) 4490 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 4491 __FILE__, __LINE__); 4492 4493 bce_reset_exit: 4494 DBEXIT(BCE_VERBOSE_RESET); 4495 return (rc); 4496 } 4497 4498 4499 static int 4500 bce_chipinit(struct bce_softc *sc) 4501 { 4502 u32 val; 4503 int rc = 0; 4504 4505 DBENTER(BCE_VERBOSE_RESET); 4506 4507 bce_disable_intr(sc); 4508 4509 /* 4510 * Initialize DMA byte/word swapping, configure the number of DMA 4511 * channels and PCI clock compensation delay. 4512 */ 4513 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4514 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4515 #if BYTE_ORDER == BIG_ENDIAN 4516 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4517 #endif 4518 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4519 DMA_READ_CHANS << 12 | 4520 DMA_WRITE_CHANS << 16; 4521 4522 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4523 4524 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4525 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4526 4527 /* 4528 * This setting resolves a problem observed on certain Intel PCI 4529 * chipsets that cannot handle multiple outstanding DMA operations. 4530 * See errata E9_5706A1_65. 4531 */ 4532 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4533 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4534 !(sc->bce_flags & BCE_PCIX_FLAG)) 4535 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4536 4537 REG_WR(sc, BCE_DMA_CONFIG, val); 4538 4539 /* Enable the RX_V2P and Context state machines before access. */ 4540 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4541 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4542 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4543 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4544 4545 /* Initialize context mapping and zero out the quick contexts. */ 4546 bce_init_ctx(sc); 4547 4548 /* Initialize the on-boards CPUs */ 4549 bce_init_cpus(sc); 4550 4551 /* Prepare NVRAM for access. */ 4552 if (bce_init_nvram(sc)) { 4553 rc = ENODEV; 4554 goto bce_chipinit_exit; 4555 } 4556 4557 /* Set the kernel bypass block size */ 4558 val = REG_RD(sc, BCE_MQ_CONFIG); 4559 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4560 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4561 4562 /* Enable bins used on the 5709. */ 4563 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4564 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4565 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4566 val |= BCE_MQ_CONFIG_HALT_DIS; 4567 } 4568 4569 REG_WR(sc, BCE_MQ_CONFIG, val); 4570 4571 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4572 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4573 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4574 4575 /* Set the page size and clear the RV2P processor stall bits. */ 4576 val = (BCM_PAGE_BITS - 8) << 24; 4577 REG_WR(sc, BCE_RV2P_CONFIG, val); 4578 4579 /* Configure page size. */ 4580 val = REG_RD(sc, BCE_TBDR_CONFIG); 4581 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4582 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4583 REG_WR(sc, BCE_TBDR_CONFIG, val); 4584 4585 /* Set the perfect match control register to default. */ 4586 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4587 4588 bce_chipinit_exit: 4589 DBEXIT(BCE_VERBOSE_RESET); 4590 4591 return(rc); 4592 } 4593 4594 4595 /****************************************************************************/ 4596 /* Initialize the controller in preparation to send/receive traffic. */ 4597 /* */ 4598 /* Returns: */ 4599 /* 0 for success, positive value for failure. */ 4600 /****************************************************************************/ 4601 static int 4602 bce_blockinit(struct bce_softc *sc) 4603 { 4604 u32 reg, val; 4605 int rc = 0; 4606 4607 DBENTER(BCE_VERBOSE_RESET); 4608 4609 /* Load the hardware default MAC address. */ 4610 bce_set_mac_addr(sc); 4611 4612 /* Set the Ethernet backoff seed value */ 4613 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4614 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4615 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4616 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4617 4618 sc->last_status_idx = 0; 4619 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4620 4621 /* Set up link change interrupt generation. */ 4622 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4623 4624 /* Program the physical address of the status block. */ 4625 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4626 BCE_ADDR_LO(sc->status_block_paddr)); 4627 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4628 BCE_ADDR_HI(sc->status_block_paddr)); 4629 4630 /* Program the physical address of the statistics block. */ 4631 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4632 BCE_ADDR_LO(sc->stats_block_paddr)); 4633 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4634 BCE_ADDR_HI(sc->stats_block_paddr)); 4635 4636 /* Program various host coalescing parameters. */ 4637 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4638 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4639 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4640 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4641 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4642 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4643 REG_WR(sc, BCE_HC_TX_TICKS, 4644 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4645 REG_WR(sc, BCE_HC_RX_TICKS, 4646 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4647 REG_WR(sc, BCE_HC_COM_TICKS, 4648 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4649 REG_WR(sc, BCE_HC_CMD_TICKS, 4650 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4651 REG_WR(sc, BCE_HC_STATS_TICKS, 4652 (sc->bce_stats_ticks & 0xffff00)); 4653 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4654 4655 /* Configure the Host Coalescing block. */ 4656 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4657 BCE_HC_CONFIG_COLLECT_STATS; 4658 4659 #if 0 4660 /* ToDo: Add MSI-X support. */ 4661 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4662 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4663 BCE_HC_SB_CONFIG_1; 4664 4665 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4666 4667 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4668 BCE_HC_SB_CONFIG_1_ONE_SHOT); 4669 4670 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4671 (sc->tx_quick_cons_trip_int << 16) | 4672 sc->tx_quick_cons_trip); 4673 4674 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4675 (sc->tx_ticks_int << 16) | sc->tx_ticks); 4676 4677 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4678 } 4679 4680 /* 4681 * Tell the HC block to automatically set the 4682 * INT_MASK bit after an MSI/MSI-X interrupt 4683 * is generated so the driver doesn't have to. 4684 */ 4685 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4686 val |= BCE_HC_CONFIG_ONE_SHOT; 4687 4688 /* Set the MSI-X status blocks to 128 byte boundaries. */ 4689 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4690 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4691 #endif 4692 4693 REG_WR(sc, BCE_HC_CONFIG, val); 4694 4695 /* Clear the internal statistics counters. */ 4696 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4697 4698 /* Verify that bootcode is running. */ 4699 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 4700 4701 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 4702 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4703 __FILE__, __LINE__); 4704 reg = 0); 4705 4706 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4707 BCE_DEV_INFO_SIGNATURE_MAGIC) { 4708 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4709 "Expected: 08%08X\n", __FILE__, __LINE__, 4710 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4711 BCE_DEV_INFO_SIGNATURE_MAGIC); 4712 rc = ENODEV; 4713 goto bce_blockinit_exit; 4714 } 4715 4716 /* Enable DMA */ 4717 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4718 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4719 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4720 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4721 } 4722 4723 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 4724 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 4725 4726 /* Enable link state change interrupt generation. */ 4727 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4728 4729 /* Enable all remaining blocks in the MAC. */ 4730 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 4731 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI); 4732 else 4733 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 4734 4735 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4736 DELAY(20); 4737 4738 /* Save the current host coalescing block settings. */ 4739 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 4740 4741 bce_blockinit_exit: 4742 DBEXIT(BCE_VERBOSE_RESET); 4743 4744 return (rc); 4745 } 4746 4747 4748 /****************************************************************************/ 4749 /* Encapsulate an mbuf into the rx_bd chain. */ 4750 /* */ 4751 /* Returns: */ 4752 /* 0 for success, positive value for failure. */ 4753 /****************************************************************************/ 4754 static int 4755 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4756 u16 *chain_prod, u32 *prod_bseq) 4757 { 4758 bus_dmamap_t map; 4759 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4760 struct mbuf *m_new = NULL; 4761 struct rx_bd *rxbd; 4762 int nsegs, error, rc = 0; 4763 #ifdef BCE_DEBUG 4764 u16 debug_chain_prod = *chain_prod; 4765 #endif 4766 4767 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4768 4769 /* Make sure the inputs are valid. */ 4770 DBRUNIF((*chain_prod > MAX_RX_BD), 4771 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 4772 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 4773 4774 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 4775 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 4776 4777 /* Update some debug statistic counters */ 4778 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4779 sc->rx_low_watermark = sc->free_rx_bd); 4780 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 4781 4782 /* Check whether this is a new mbuf allocation. */ 4783 if (m == NULL) { 4784 4785 /* Simulate an mbuf allocation failure. */ 4786 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 4787 sc->mbuf_alloc_failed++; 4788 sc->debug_mbuf_sim_alloc_failed++; 4789 rc = ENOBUFS; 4790 goto bce_get_rx_buf_exit); 4791 4792 /* This is a new mbuf allocation. */ 4793 #ifdef BCE_USE_SPLIT_HEADER 4794 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4795 #else 4796 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) 4797 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 4798 else 4799 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size); 4800 #endif 4801 4802 if (m_new == NULL) { 4803 sc->mbuf_alloc_failed++; 4804 rc = ENOBUFS; 4805 goto bce_get_rx_buf_exit; 4806 } 4807 4808 DBRUN(sc->debug_rx_mbuf_alloc++); 4809 } else { 4810 /* Reuse an existing mbuf. */ 4811 m_new = m; 4812 } 4813 4814 /* Make sure we have a valid packet header. */ 4815 M_ASSERTPKTHDR(m_new); 4816 4817 /* Initialize the mbuf size and pad if necessary for alignment. */ 4818 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 4819 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 4820 4821 /* ToDo: Consider calling m_fragment() to test error handling. */ 4822 4823 /* Map the mbuf cluster into device memory. */ 4824 map = sc->rx_mbuf_map[*chain_prod]; 4825 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 4826 segs, &nsegs, BUS_DMA_NOWAIT); 4827 4828 /* Handle any mapping errors. */ 4829 if (error) { 4830 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n", 4831 __FILE__, __LINE__, error); 4832 4833 m_freem(m_new); 4834 DBRUN(sc->debug_rx_mbuf_alloc--); 4835 4836 rc = ENOBUFS; 4837 goto bce_get_rx_buf_exit; 4838 } 4839 4840 /* All mbufs must map to a single segment. */ 4841 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 4842 __FUNCTION__, nsegs)); 4843 4844 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */ 4845 4846 /* Setup the rx_bd for the segment. */ 4847 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 4848 4849 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 4850 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 4851 rxbd->rx_bd_len = htole32(segs[0].ds_len); 4852 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 4853 *prod_bseq += segs[0].ds_len; 4854 4855 /* Save the mbuf and update our counter. */ 4856 sc->rx_mbuf_ptr[*chain_prod] = m_new; 4857 sc->free_rx_bd -= nsegs; 4858 4859 DBRUNMSG(BCE_INSANE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 4860 nsegs)); 4861 4862 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 4863 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 4864 4865 bce_get_rx_buf_exit: 4866 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4867 4868 return(rc); 4869 } 4870 4871 4872 #ifdef BCE_USE_SPLIT_HEADER 4873 /****************************************************************************/ 4874 /* Encapsulate an mbuf cluster into the page chain. */ 4875 /* */ 4876 /* Returns: */ 4877 /* 0 for success, positive value for failure. */ 4878 /****************************************************************************/ 4879 static int 4880 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4881 u16 *prod_idx) 4882 { 4883 bus_dmamap_t map; 4884 bus_addr_t busaddr; 4885 struct mbuf *m_new = NULL; 4886 struct rx_bd *pgbd; 4887 int error, rc = 0; 4888 #ifdef BCE_DEBUG 4889 u16 debug_prod_idx = *prod_idx; 4890 #endif 4891 4892 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4893 4894 /* Make sure the inputs are valid. */ 4895 DBRUNIF((*prod_idx > MAX_PG_BD), 4896 BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n", 4897 __FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD)); 4898 4899 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 4900 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 4901 4902 /* Update counters if we've hit a new low or run out of pages. */ 4903 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 4904 sc->pg_low_watermark = sc->free_pg_bd); 4905 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 4906 4907 /* Check whether this is a new mbuf allocation. */ 4908 if (m == NULL) { 4909 4910 /* Simulate an mbuf allocation failure. */ 4911 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 4912 sc->mbuf_alloc_failed++; 4913 sc->debug_mbuf_sim_alloc_failed++; 4914 rc = ENOBUFS; 4915 goto bce_get_pg_buf_exit); 4916 4917 /* This is a new mbuf allocation. */ 4918 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 4919 if (m_new == NULL) { 4920 sc->mbuf_alloc_failed++; 4921 rc = ENOBUFS; 4922 goto bce_get_pg_buf_exit; 4923 } 4924 4925 DBRUN(sc->debug_pg_mbuf_alloc++); 4926 } else { 4927 /* Reuse an existing mbuf. */ 4928 m_new = m; 4929 m_new->m_data = m_new->m_ext.ext_buf; 4930 } 4931 4932 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 4933 4934 /* ToDo: Consider calling m_fragment() to test error handling. */ 4935 4936 /* Map the mbuf cluster into device memory. */ 4937 map = sc->pg_mbuf_map[*prod_idx]; 4938 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 4939 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, &busaddr, BUS_DMA_NOWAIT); 4940 4941 /* Handle any mapping errors. */ 4942 if (error) { 4943 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 4944 __FILE__, __LINE__); 4945 4946 m_freem(m_new); 4947 DBRUN(sc->debug_pg_mbuf_alloc--); 4948 4949 rc = ENOBUFS; 4950 goto bce_get_pg_buf_exit; 4951 } 4952 4953 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */ 4954 4955 /* 4956 * The page chain uses the same rx_bd data structure 4957 * as the receive chain but doesn't require a byte sequence (bseq). 4958 */ 4959 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 4960 4961 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 4962 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 4963 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 4964 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 4965 4966 /* Save the mbuf and update our counter. */ 4967 sc->pg_mbuf_ptr[*prod_idx] = m_new; 4968 sc->free_pg_bd--; 4969 4970 DBRUNMSG(BCE_INSANE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 4971 1)); 4972 4973 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 4974 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 4975 4976 bce_get_pg_buf_exit: 4977 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4978 4979 return(rc); 4980 } 4981 #endif /* BCE_USE_SPLIT_HEADER */ 4982 4983 /****************************************************************************/ 4984 /* Initialize the TX context memory. */ 4985 /* */ 4986 /* Returns: */ 4987 /* Nothing */ 4988 /****************************************************************************/ 4989 static void 4990 bce_init_tx_context(struct bce_softc *sc) 4991 { 4992 u32 val; 4993 4994 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 4995 4996 /* Initialize the context ID for an L2 TX chain. */ 4997 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4998 /* Set the CID type to support an L2 connection. */ 4999 val = BCE_L2CTX_TYPE_TYPE_L2 | BCE_L2CTX_TYPE_SIZE_L2; 5000 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE_XI, val); 5001 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 5002 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE_XI, val); 5003 5004 /* Point the hardware to the first page in the chain. */ 5005 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5006 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI_XI, val); 5007 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5008 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO_XI, val); 5009 } else { 5010 /* Set the CID type to support an L2 connection. */ 5011 val = BCE_L2CTX_TYPE_TYPE_L2 | BCE_L2CTX_TYPE_SIZE_L2; 5012 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 5013 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 5014 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 5015 5016 /* Point the hardware to the first page in the chain. */ 5017 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5018 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 5019 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5020 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 5021 } 5022 5023 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5024 } 5025 5026 5027 /****************************************************************************/ 5028 /* Allocate memory and initialize the TX data structures. */ 5029 /* */ 5030 /* Returns: */ 5031 /* 0 for success, positive value for failure. */ 5032 /****************************************************************************/ 5033 static int 5034 bce_init_tx_chain(struct bce_softc *sc) 5035 { 5036 struct tx_bd *txbd; 5037 int i, rc = 0; 5038 5039 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5040 5041 /* Set the initial TX producer/consumer indices. */ 5042 sc->tx_prod = 0; 5043 sc->tx_cons = 0; 5044 sc->tx_prod_bseq = 0; 5045 sc->used_tx_bd = 0; 5046 sc->max_tx_bd = USABLE_TX_BD; 5047 DBRUN(sc->tx_hi_watermark = USABLE_TX_BD); 5048 DBRUN(sc->tx_full_count = 0); 5049 5050 /* 5051 * The NetXtreme II supports a linked-list structre called 5052 * a Buffer Descriptor Chain (or BD chain). A BD chain 5053 * consists of a series of 1 or more chain pages, each of which 5054 * consists of a fixed number of BD entries. 5055 * The last BD entry on each page is a pointer to the next page 5056 * in the chain, and the last pointer in the BD chain 5057 * points back to the beginning of the chain. 5058 */ 5059 5060 /* Set the TX next pointer chain entries. */ 5061 for (i = 0; i < TX_PAGES; i++) { 5062 int j; 5063 5064 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5065 5066 /* Check if we've reached the last page. */ 5067 if (i == (TX_PAGES - 1)) 5068 j = 0; 5069 else 5070 j = i + 1; 5071 5072 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5073 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5074 } 5075 5076 bce_init_tx_context(sc); 5077 5078 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5079 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5080 5081 return(rc); 5082 } 5083 5084 5085 /****************************************************************************/ 5086 /* Free memory and clear the TX data structures. */ 5087 /* */ 5088 /* Returns: */ 5089 /* Nothing. */ 5090 /****************************************************************************/ 5091 static void 5092 bce_free_tx_chain(struct bce_softc *sc) 5093 { 5094 int i; 5095 5096 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5097 5098 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5099 for (i = 0; i < TOTAL_TX_BD; i++) { 5100 if (sc->tx_mbuf_ptr[i] != NULL) { 5101 if (sc->tx_mbuf_map != NULL) 5102 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 5103 BUS_DMASYNC_POSTWRITE); 5104 m_freem(sc->tx_mbuf_ptr[i]); 5105 sc->tx_mbuf_ptr[i] = NULL; 5106 DBRUN(sc->debug_tx_mbuf_alloc--); 5107 } 5108 } 5109 5110 /* Clear each TX chain page. */ 5111 for (i = 0; i < TX_PAGES; i++) 5112 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5113 5114 sc->used_tx_bd = 0; 5115 5116 /* Check if we lost any mbufs in the process. */ 5117 DBRUNIF((sc->debug_tx_mbuf_alloc), 5118 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5119 "from tx chain!\n", 5120 __FILE__, __LINE__, sc->debug_tx_mbuf_alloc)); 5121 5122 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5123 } 5124 5125 5126 /****************************************************************************/ 5127 /* Initialize the RX context memory. */ 5128 /* */ 5129 /* Returns: */ 5130 /* Nothing */ 5131 /****************************************************************************/ 5132 static void 5133 bce_init_rx_context(struct bce_softc *sc) 5134 { 5135 u32 val; 5136 5137 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5138 5139 /* Initialize the context ID for an L2 RX chain. */ 5140 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5141 BCE_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 5142 5143 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5144 u32 lo_water, hi_water; 5145 5146 lo_water = BCE_L2CTX_LO_WATER_MARK_DEFAULT; 5147 hi_water = USABLE_RX_BD / 4; 5148 5149 lo_water /= BCE_L2CTX_LO_WATER_MARK_SCALE; 5150 hi_water /= BCE_L2CTX_HI_WATER_MARK_SCALE; 5151 5152 if (hi_water > 0xf) 5153 hi_water = 0xf; 5154 else if (hi_water == 0) 5155 lo_water = 0; 5156 val |= lo_water | (hi_water << BCE_L2CTX_HI_WATER_MARK_SHIFT); 5157 } 5158 5159 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 5160 5161 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5162 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5163 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5164 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5165 } 5166 5167 /* Point the hardware to the first page in the chain. */ 5168 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5169 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 5170 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5171 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 5172 5173 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5174 } 5175 5176 5177 /****************************************************************************/ 5178 /* Allocate memory and initialize the RX data structures. */ 5179 /* */ 5180 /* Returns: */ 5181 /* 0 for success, positive value for failure. */ 5182 /****************************************************************************/ 5183 static int 5184 bce_init_rx_chain(struct bce_softc *sc) 5185 { 5186 struct rx_bd *rxbd; 5187 int i, rc = 0; 5188 5189 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5190 BCE_VERBOSE_CTX); 5191 5192 /* Initialize the RX producer and consumer indices. */ 5193 sc->rx_prod = 0; 5194 sc->rx_cons = 0; 5195 sc->rx_prod_bseq = 0; 5196 sc->free_rx_bd = USABLE_RX_BD; 5197 sc->max_rx_bd = USABLE_RX_BD; 5198 DBRUN(sc->rx_low_watermark = sc->max_rx_bd); 5199 DBRUN(sc->rx_empty_count = 0); 5200 5201 /* Initialize the RX next pointer chain entries. */ 5202 for (i = 0; i < RX_PAGES; i++) { 5203 int j; 5204 5205 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5206 5207 /* Check if we've reached the last page. */ 5208 if (i == (RX_PAGES - 1)) 5209 j = 0; 5210 else 5211 j = i + 1; 5212 5213 /* Setup the chain page pointers. */ 5214 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5215 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5216 } 5217 5218 /* Fill up the RX chain. */ 5219 bce_fill_rx_chain(sc); 5220 5221 for (i = 0; i < RX_PAGES; i++) { 5222 bus_dmamap_sync( 5223 sc->rx_bd_chain_tag, 5224 sc->rx_bd_chain_map[i], 5225 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5226 } 5227 5228 bce_init_rx_context(sc); 5229 5230 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 5231 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5232 BCE_VERBOSE_CTX); 5233 /* ToDo: Are there possible failure modes here? */ 5234 return(rc); 5235 } 5236 5237 5238 /****************************************************************************/ 5239 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5240 /* occurs. */ 5241 /* */ 5242 /* Returns: */ 5243 /* Nothing */ 5244 /****************************************************************************/ 5245 static void 5246 bce_fill_rx_chain(struct bce_softc *sc) 5247 { 5248 u16 prod, prod_idx; 5249 u32 prod_bseq; 5250 5251 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5252 BCE_VERBOSE_CTX); 5253 5254 /* Get the RX chain producer indices. */ 5255 prod = sc->rx_prod; 5256 prod_bseq = sc->rx_prod_bseq; 5257 5258 /* Keep filling the RX chain until it's full. */ 5259 while (sc->free_rx_bd > 0) { 5260 prod_idx = RX_CHAIN_IDX(prod); 5261 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5262 /* Bail out if we can't add an mbuf to the chain. */ 5263 break; 5264 } 5265 prod = NEXT_RX_BD(prod); 5266 } 5267 5268 /* Save the RX chain producer indices. */ 5269 sc->rx_prod = prod; 5270 sc->rx_prod_bseq = prod_bseq; 5271 5272 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5273 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5274 __FUNCTION__, sc->rx_prod)); 5275 5276 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5277 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_BDIDX, 5278 sc->rx_prod); 5279 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_BSEQ, 5280 sc->rx_prod_bseq); 5281 5282 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5283 BCE_VERBOSE_CTX); 5284 } 5285 5286 5287 /****************************************************************************/ 5288 /* Free memory and clear the RX data structures. */ 5289 /* */ 5290 /* Returns: */ 5291 /* Nothing. */ 5292 /****************************************************************************/ 5293 static void 5294 bce_free_rx_chain(struct bce_softc *sc) 5295 { 5296 int i; 5297 5298 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5299 5300 /* Free any mbufs still in the RX mbuf chain. */ 5301 for (i = 0; i < TOTAL_RX_BD; i++) { 5302 if (sc->rx_mbuf_ptr[i] != NULL) { 5303 if (sc->rx_mbuf_map[i] != NULL) 5304 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 5305 BUS_DMASYNC_POSTREAD); 5306 m_freem(sc->rx_mbuf_ptr[i]); 5307 sc->rx_mbuf_ptr[i] = NULL; 5308 DBRUN(sc->debug_rx_mbuf_alloc--); 5309 } 5310 } 5311 5312 /* Clear each RX chain page. */ 5313 for (i = 0; i < RX_PAGES; i++) 5314 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 5315 5316 sc->free_rx_bd = sc->max_rx_bd; 5317 5318 /* Check if we lost any mbufs in the process. */ 5319 DBRUNIF((sc->debug_rx_mbuf_alloc), 5320 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5321 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5322 5323 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5324 } 5325 5326 5327 #ifdef BCE_USE_SPLIT_HEADER 5328 /****************************************************************************/ 5329 /* Allocate memory and initialize the page data structures. */ 5330 /* Assumes that bce_init_rx_chain() has not already been called. */ 5331 /* */ 5332 /* Returns: */ 5333 /* 0 for success, positive value for failure. */ 5334 /****************************************************************************/ 5335 static int 5336 bce_init_pg_chain(struct bce_softc *sc) 5337 { 5338 struct rx_bd *pgbd; 5339 int i, rc = 0; 5340 u32 val; 5341 5342 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5343 BCE_VERBOSE_CTX); 5344 5345 /* Initialize the page producer and consumer indices. */ 5346 sc->pg_prod = 0; 5347 sc->pg_cons = 0; 5348 sc->free_pg_bd = USABLE_PG_BD; 5349 sc->max_pg_bd = USABLE_PG_BD; 5350 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5351 DBRUN(sc->pg_empty_count = 0); 5352 5353 /* Initialize the page next pointer chain entries. */ 5354 for (i = 0; i < PG_PAGES; i++) { 5355 int j; 5356 5357 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5358 5359 /* Check if we've reached the last page. */ 5360 if (i == (PG_PAGES - 1)) 5361 j = 0; 5362 else 5363 j = i + 1; 5364 5365 /* Setup the chain page pointers. */ 5366 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5367 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5368 } 5369 5370 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5371 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5372 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5373 5374 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, 0); 5375 5376 /* Configure the rx_bd and page chain mbuf cluster size. */ 5377 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5378 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, val); 5379 5380 /* Configure the context reserved for jumbo support. */ 5381 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RBDC_KEY, 5382 BCE_L2CTX_RBDC_JUMBO_KEY); 5383 5384 /* Point the hardware to the first page in the page chain. */ 5385 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5386 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_HI, val); 5387 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5388 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_LO, val); 5389 5390 /* Fill up the page chain. */ 5391 bce_fill_pg_chain(sc); 5392 5393 for (i = 0; i < PG_PAGES; i++) { 5394 bus_dmamap_sync( 5395 sc->pg_bd_chain_tag, 5396 sc->pg_bd_chain_map[i], 5397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5398 } 5399 5400 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5401 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5402 BCE_VERBOSE_CTX); 5403 return(rc); 5404 } 5405 5406 5407 /****************************************************************************/ 5408 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5409 /* occurs. */ 5410 /* */ 5411 /* Returns: */ 5412 /* Nothing */ 5413 /****************************************************************************/ 5414 static void 5415 bce_fill_pg_chain(struct bce_softc *sc) 5416 { 5417 u16 prod, prod_idx; 5418 5419 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5420 BCE_VERBOSE_CTX); 5421 5422 /* Get the page chain prodcuer index. */ 5423 prod = sc->pg_prod; 5424 5425 /* Keep filling the page chain until it's full. */ 5426 while (sc->free_pg_bd > 0) { 5427 prod_idx = PG_CHAIN_IDX(prod); 5428 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5429 /* Bail out if we can't add an mbuf to the chain. */ 5430 break; 5431 } 5432 prod = NEXT_PG_BD(prod); 5433 } 5434 5435 /* Save the page chain producer index. */ 5436 sc->pg_prod = prod; 5437 5438 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5439 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5440 __FUNCTION__, sc->pg_prod)); 5441 5442 /* 5443 * Write the mailbox and tell the chip about 5444 * the new rx_bd's in the page chain. 5445 */ 5446 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_PG_BDIDX, 5447 sc->pg_prod); 5448 5449 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5450 BCE_VERBOSE_CTX); 5451 } 5452 5453 5454 /****************************************************************************/ 5455 /* Free memory and clear the RX data structures. */ 5456 /* */ 5457 /* Returns: */ 5458 /* Nothing. */ 5459 /****************************************************************************/ 5460 static void 5461 bce_free_pg_chain(struct bce_softc *sc) 5462 { 5463 int i; 5464 5465 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5466 5467 /* Free any mbufs still in the mbuf page chain. */ 5468 for (i = 0; i < TOTAL_PG_BD; i++) { 5469 if (sc->pg_mbuf_ptr[i] != NULL) { 5470 if (sc->pg_mbuf_map[i] != NULL) 5471 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i], 5472 BUS_DMASYNC_POSTREAD); 5473 m_freem(sc->pg_mbuf_ptr[i]); 5474 sc->pg_mbuf_ptr[i] = NULL; 5475 DBRUN(sc->debug_pg_mbuf_alloc--); 5476 } 5477 } 5478 5479 /* Clear each page chain pages. */ 5480 for (i = 0; i < PG_PAGES; i++) 5481 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5482 5483 sc->free_pg_bd = sc->max_pg_bd; 5484 5485 /* Check if we lost any mbufs in the process. */ 5486 DBRUNIF((sc->debug_pg_mbuf_alloc), 5487 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5488 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5489 5490 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5491 } 5492 #endif /* BCE_USE_SPLIT_HEADER */ 5493 5494 5495 /****************************************************************************/ 5496 /* Set media options. */ 5497 /* */ 5498 /* Returns: */ 5499 /* 0 for success, positive value for failure. */ 5500 /****************************************************************************/ 5501 static int 5502 bce_ifmedia_upd(struct ifnet *ifp) 5503 { 5504 struct bce_softc *sc = ifp->if_softc; 5505 5506 DBENTER(BCE_VERBOSE); 5507 5508 BCE_LOCK(sc); 5509 bce_ifmedia_upd_locked(ifp); 5510 BCE_UNLOCK(sc); 5511 5512 DBEXIT(BCE_VERBOSE); 5513 return (0); 5514 } 5515 5516 5517 /****************************************************************************/ 5518 /* Set media options. */ 5519 /* */ 5520 /* Returns: */ 5521 /* Nothing. */ 5522 /****************************************************************************/ 5523 static void 5524 bce_ifmedia_upd_locked(struct ifnet *ifp) 5525 { 5526 struct bce_softc *sc = ifp->if_softc; 5527 struct mii_data *mii; 5528 5529 DBENTER(BCE_VERBOSE); 5530 5531 BCE_LOCK_ASSERT(sc); 5532 5533 mii = device_get_softc(sc->bce_miibus); 5534 5535 /* Make sure the MII bus has been enumerated. */ 5536 if (mii) { 5537 sc->bce_link = 0; 5538 if (mii->mii_instance) { 5539 struct mii_softc *miisc; 5540 5541 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5542 mii_phy_reset(miisc); 5543 } 5544 mii_mediachg(mii); 5545 } 5546 5547 DBEXIT(BCE_VERBOSE); 5548 } 5549 5550 5551 /****************************************************************************/ 5552 /* Reports current media status. */ 5553 /* */ 5554 /* Returns: */ 5555 /* Nothing. */ 5556 /****************************************************************************/ 5557 static void 5558 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5559 { 5560 struct bce_softc *sc = ifp->if_softc; 5561 struct mii_data *mii; 5562 5563 DBENTER(BCE_VERBOSE); 5564 5565 BCE_LOCK(sc); 5566 5567 mii = device_get_softc(sc->bce_miibus); 5568 5569 mii_pollstat(mii); 5570 ifmr->ifm_active = mii->mii_media_active; 5571 ifmr->ifm_status = mii->mii_media_status; 5572 5573 BCE_UNLOCK(sc); 5574 5575 DBEXIT(BCE_VERBOSE); 5576 } 5577 5578 5579 /****************************************************************************/ 5580 /* Handles PHY generated interrupt events. */ 5581 /* */ 5582 /* Returns: */ 5583 /* Nothing. */ 5584 /****************************************************************************/ 5585 static void 5586 bce_phy_intr(struct bce_softc *sc) 5587 { 5588 u32 new_link_state, old_link_state; 5589 5590 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5591 5592 new_link_state = sc->status_block->status_attn_bits & 5593 STATUS_ATTN_BITS_LINK_STATE; 5594 old_link_state = sc->status_block->status_attn_bits_ack & 5595 STATUS_ATTN_BITS_LINK_STATE; 5596 5597 /* Handle any changes if the link state has changed. */ 5598 if (new_link_state != old_link_state) { 5599 5600 /* Update the status_attn_bits_ack field in the status block. */ 5601 if (new_link_state) { 5602 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5603 STATUS_ATTN_BITS_LINK_STATE); 5604 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5605 __FUNCTION__); 5606 } 5607 else { 5608 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5609 STATUS_ATTN_BITS_LINK_STATE); 5610 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5611 __FUNCTION__); 5612 } 5613 5614 /* 5615 * Assume link is down and allow 5616 * tick routine to update the state 5617 * based on the actual media state. 5618 */ 5619 sc->bce_link = 0; 5620 callout_stop(&sc->bce_tick_callout); 5621 bce_tick(sc); 5622 } 5623 5624 /* Acknowledge the link change interrupt. */ 5625 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5626 5627 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5628 } 5629 5630 5631 /****************************************************************************/ 5632 /* Reads the receive consumer value from the status block (skipping over */ 5633 /* chain page pointer if necessary). */ 5634 /* */ 5635 /* Returns: */ 5636 /* hw_cons */ 5637 /****************************************************************************/ 5638 static inline u16 5639 bce_get_hw_rx_cons(struct bce_softc *sc) 5640 { 5641 u16 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5642 5643 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5644 hw_cons++; 5645 5646 return hw_cons; 5647 } 5648 5649 /****************************************************************************/ 5650 /* Handles received frame interrupt events. */ 5651 /* */ 5652 /* Returns: */ 5653 /* Nothing. */ 5654 /****************************************************************************/ 5655 static void 5656 bce_rx_intr(struct bce_softc *sc) 5657 { 5658 struct ifnet *ifp = sc->bce_ifp; 5659 struct l2_fhdr *l2fhdr; 5660 unsigned int pkt_len; 5661 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5662 u32 status; 5663 #ifdef BCE_USE_SPLIT_HEADER 5664 unsigned int rem_len; 5665 u16 sw_pg_cons, sw_pg_cons_idx; 5666 #endif 5667 5668 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5669 DBRUN(sc->rx_interrupts++); 5670 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5671 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5672 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5673 5674 /* Prepare the RX chain pages to be accessed by the host CPU. */ 5675 for (int i = 0; i < RX_PAGES; i++) 5676 bus_dmamap_sync(sc->rx_bd_chain_tag, 5677 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 5678 5679 #ifdef BCE_USE_SPLIT_HEADER 5680 /* Prepare the page chain pages to be accessed by the host CPU. */ 5681 for (int i = 0; i < PG_PAGES; i++) 5682 bus_dmamap_sync(sc->pg_bd_chain_tag, 5683 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 5684 #endif 5685 5686 /* Get the hardware's view of the RX consumer index. */ 5687 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 5688 5689 /* Get working copies of the driver's view of the consumer indices. */ 5690 sw_rx_cons = sc->rx_cons; 5691 #ifdef BCE_USE_SPLIT_HEADER 5692 sw_pg_cons = sc->pg_cons; 5693 #endif 5694 5695 /* Update some debug statistics counters */ 5696 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5697 sc->rx_low_watermark = sc->free_rx_bd); 5698 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 5699 5700 /* Scan through the receive chain as long as there is work to do */ 5701 /* ToDo: Consider setting a limit on the number of packets processed. */ 5702 while (sw_rx_cons != hw_rx_cons) { 5703 struct mbuf *m0; 5704 5705 /* Convert the producer/consumer indices to an actual rx_bd index. */ 5706 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 5707 5708 /* Unmap the mbuf from DMA space. */ 5709 bus_dmamap_sync(sc->rx_mbuf_tag, 5710 sc->rx_mbuf_map[sw_rx_cons_idx], 5711 BUS_DMASYNC_POSTREAD); 5712 bus_dmamap_unload(sc->rx_mbuf_tag, 5713 sc->rx_mbuf_map[sw_rx_cons_idx]); 5714 5715 /* Remove the mbuf from the RX chain. */ 5716 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 5717 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 5718 DBRUN(sc->debug_rx_mbuf_alloc--); 5719 sc->free_rx_bd++; 5720 5721 /* 5722 * Frames received on the NetXteme II are prepended 5723 * with an l2_fhdr structure which provides status 5724 * information about the received frame (including 5725 * VLAN tags and checksum info). The frames are also 5726 * automatically adjusted to align the IP header 5727 * (i.e. two null bytes are inserted before the 5728 * Ethernet header). As a result the data DMA'd by 5729 * the controller into the mbuf is as follows: 5730 * +---------+-----+---------------------+-----+ 5731 * | l2_fhdr | pad | packet data | FCS | 5732 * +---------+-----+---------------------+-----+ 5733 * The l2_fhdr needs to be checked and skipped and 5734 * the FCS needs to be stripped before sending the 5735 * packet up the stack. 5736 */ 5737 l2fhdr = mtod(m0, struct l2_fhdr *); 5738 5739 /* Get the packet data + FCS length and the status. */ 5740 pkt_len = l2fhdr->l2_fhdr_pkt_len; 5741 status = l2fhdr->l2_fhdr_status; 5742 5743 /* 5744 * Skip over the l2_fhdr and pad, resulting in the 5745 * following data in the mbuf: 5746 * +---------------------+-----+ 5747 * | packet data | FCS | 5748 * +---------------------+-----+ 5749 */ 5750 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 5751 5752 #ifdef BCE_USE_SPLIT_HEADER 5753 /* 5754 * Check whether the received frame fits in a single 5755 * mbuf or not (i.e. packet data + FCS <= 5756 * sc->rx_bd_mbuf_data_len bytes). 5757 */ 5758 if (pkt_len > m0->m_len) { 5759 /* 5760 * The received frame is larger than a single mbuf. 5761 * If the frame was a TCP frame then only the TCP 5762 * header is placed in the mbuf, the remaining 5763 * payload (including FCS) is placed in the page 5764 * chain, the SPLIT flag is set, and the header 5765 * length is placed in the IP checksum field. 5766 * If the frame is not a TCP frame then the mbuf 5767 * is filled and the remaining bytes are placed 5768 * in the page chain. 5769 */ 5770 5771 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n", 5772 __FUNCTION__); 5773 5774 /* 5775 * When the page chain is enabled and the TCP 5776 * header has been split from the TCP payload, 5777 * the ip_xsum structure will reflect the length 5778 * of the TCP header, not the IP checksum. Set 5779 * the packet length of the mbuf accordingly. 5780 */ 5781 if (status & L2_FHDR_STATUS_SPLIT) 5782 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 5783 5784 rem_len = pkt_len - m0->m_len; 5785 5786 /* Pull mbufs off the page chain for the remaining data. */ 5787 while (rem_len > 0) { 5788 struct mbuf *m_pg; 5789 5790 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 5791 5792 /* Remove the mbuf from the page chain. */ 5793 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 5794 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 5795 DBRUN(sc->debug_pg_mbuf_alloc--); 5796 sc->free_pg_bd++; 5797 5798 /* Unmap the page chain mbuf from DMA space. */ 5799 bus_dmamap_sync(sc->pg_mbuf_tag, 5800 sc->pg_mbuf_map[sw_pg_cons_idx], 5801 BUS_DMASYNC_POSTREAD); 5802 bus_dmamap_unload(sc->pg_mbuf_tag, 5803 sc->pg_mbuf_map[sw_pg_cons_idx]); 5804 5805 /* Adjust the mbuf length. */ 5806 if (rem_len < m_pg->m_len) { 5807 /* The mbuf chain is complete. */ 5808 m_pg->m_len = rem_len; 5809 rem_len = 0; 5810 } else { 5811 /* More packet data is waiting. */ 5812 rem_len -= m_pg->m_len; 5813 } 5814 5815 /* Concatenate the mbuf cluster to the mbuf. */ 5816 m_cat(m0, m_pg); 5817 5818 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 5819 } 5820 5821 /* Set the total packet length. */ 5822 m0->m_pkthdr.len = pkt_len; 5823 5824 } else { 5825 /* 5826 * The received packet is small and fits in a 5827 * single mbuf (i.e. the l2_fhdr + pad + packet + 5828 * FCS <= MHLEN). In other words, the packet is 5829 * 154 bytes or less in size. 5830 */ 5831 5832 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small packet.\n", 5833 __FUNCTION__); 5834 5835 /* Set the total packet length. */ 5836 m0->m_pkthdr.len = m0->m_len = pkt_len; 5837 } 5838 #endif 5839 5840 /* Remove the trailing Ethernet FCS. */ 5841 m_adj(m0, -ETHER_CRC_LEN); 5842 5843 /* Check that the resulting mbuf chain is valid. */ 5844 DBRUN(m_sanity(m0, FALSE)); 5845 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 5846 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 5847 BCE_PRINTF("Invalid Ethernet frame size!\n"); 5848 m_print(m0, 128)); 5849 5850 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 5851 BCE_PRINTF("Simulating l2_fhdr status error.\n"); 5852 status = status | L2_FHDR_ERRORS_PHY_DECODE); 5853 5854 /* Check the received frame for errors. */ 5855 if (status & (L2_FHDR_ERRORS_BAD_CRC | 5856 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 5857 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 5858 5859 /* Log the error and release the mbuf. */ 5860 ifp->if_ierrors++; 5861 DBRUN(sc->l2fhdr_status_errors++); 5862 5863 m_freem(m0); 5864 m0 = NULL; 5865 goto bce_rx_int_next_rx; 5866 } 5867 5868 /* Send the packet to the appropriate interface. */ 5869 m0->m_pkthdr.rcvif = ifp; 5870 5871 /* Assume no hardware checksum. */ 5872 m0->m_pkthdr.csum_flags = 0; 5873 5874 /* Validate the checksum if offload enabled. */ 5875 if (ifp->if_capenable & IFCAP_RXCSUM) { 5876 5877 /* Check for an IP datagram. */ 5878 if (!(status & L2_FHDR_STATUS_SPLIT) && 5879 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 5880 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 5881 5882 /* Check if the IP checksum is valid. */ 5883 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 5884 m0->m_pkthdr.csum_flags |= CSUM_IP_VALID; 5885 } 5886 5887 /* Check for a valid TCP/UDP frame. */ 5888 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 5889 L2_FHDR_STATUS_UDP_DATAGRAM)) { 5890 5891 /* Check for a good TCP/UDP checksum. */ 5892 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 5893 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 5894 m0->m_pkthdr.csum_data = 5895 l2fhdr->l2_fhdr_tcp_udp_xsum; 5896 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 5897 | CSUM_PSEUDO_HDR); 5898 } 5899 } 5900 } 5901 5902 /* 5903 * If we received a packet with a vlan tag, 5904 * attach that information to the packet. 5905 */ 5906 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 5907 #if __FreeBSD_version < 700000 5908 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue); 5909 #else 5910 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 5911 m0->m_flags |= M_VLANTAG; 5912 #endif 5913 } 5914 5915 /* Pass the mbuf off to the upper layers. */ 5916 ifp->if_ipackets++; 5917 5918 bce_rx_int_next_rx: 5919 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 5920 5921 /* If we have a packet, pass it up the stack */ 5922 if (m0) { 5923 /* Make sure we don't lose our place when we release the lock. */ 5924 sc->rx_cons = sw_rx_cons; 5925 #ifdef BCE_USE_SPLIT_HEADER 5926 sc->pg_cons = sw_pg_cons; 5927 #endif 5928 5929 BCE_UNLOCK(sc); 5930 (*ifp->if_input)(ifp, m0); 5931 BCE_LOCK(sc); 5932 5933 /* Recover our place. */ 5934 sw_rx_cons = sc->rx_cons; 5935 #ifdef BCE_USE_SPLIT_HEADER 5936 sw_pg_cons = sc->pg_cons; 5937 #endif 5938 } 5939 5940 /* Refresh hw_cons to see if there's new work */ 5941 if (sw_rx_cons == hw_rx_cons) 5942 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 5943 } 5944 5945 /* No new packets to process. Refill the RX and page chains and exit. */ 5946 #ifdef BCE_USE_SPLIT_HEADER 5947 sc->pg_cons = sw_pg_cons; 5948 bce_fill_pg_chain(sc); 5949 #endif 5950 5951 sc->rx_cons = sw_rx_cons; 5952 bce_fill_rx_chain(sc); 5953 5954 for (int i = 0; i < RX_PAGES; i++) 5955 bus_dmamap_sync(sc->rx_bd_chain_tag, 5956 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 5957 5958 #ifdef BCE_USE_SPLIT_HEADER 5959 for (int i = 0; i < PG_PAGES; i++) 5960 bus_dmamap_sync(sc->pg_bd_chain_tag, 5961 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 5962 #endif 5963 5964 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 5965 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5966 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5967 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5968 } 5969 5970 5971 /****************************************************************************/ 5972 /* Reads the transmit consumer value from the status block (skipping over */ 5973 /* chain page pointer if necessary). */ 5974 /* */ 5975 /* Returns: */ 5976 /* hw_cons */ 5977 /****************************************************************************/ 5978 static inline u16 5979 bce_get_hw_tx_cons(struct bce_softc *sc) 5980 { 5981 u16 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 5982 5983 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5984 hw_cons++; 5985 5986 return hw_cons; 5987 } 5988 5989 5990 /****************************************************************************/ 5991 /* Handles transmit completion interrupt events. */ 5992 /* */ 5993 /* Returns: */ 5994 /* Nothing. */ 5995 /****************************************************************************/ 5996 static void 5997 bce_tx_intr(struct bce_softc *sc) 5998 { 5999 struct ifnet *ifp = sc->bce_ifp; 6000 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6001 6002 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6003 DBRUN(sc->tx_interrupts++); 6004 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6005 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6006 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6007 6008 BCE_LOCK_ASSERT(sc); 6009 6010 /* Get the hardware's view of the TX consumer index. */ 6011 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6012 sw_tx_cons = sc->tx_cons; 6013 6014 /* Prevent speculative reads from getting ahead of the status block. */ 6015 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6016 BUS_SPACE_BARRIER_READ); 6017 6018 /* Cycle through any completed TX chain page entries. */ 6019 while (sw_tx_cons != hw_tx_cons) { 6020 #ifdef BCE_DEBUG 6021 struct tx_bd *txbd = NULL; 6022 #endif 6023 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6024 6025 DBPRINT(sc, BCE_INFO_SEND, 6026 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6027 "sw_tx_chain_cons = 0x%04X\n", 6028 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6029 6030 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6031 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6032 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6033 (int) MAX_TX_BD); 6034 bce_breakpoint(sc)); 6035 6036 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6037 [TX_IDX(sw_tx_chain_cons)]); 6038 6039 DBRUNIF((txbd == NULL), 6040 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6041 __FILE__, __LINE__, sw_tx_chain_cons); 6042 bce_breakpoint(sc)); 6043 6044 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6045 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6046 6047 /* 6048 * Free the associated mbuf. Remember 6049 * that only the last tx_bd of a packet 6050 * has an mbuf pointer and DMA map. 6051 */ 6052 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6053 6054 /* Validate that this is the last tx_bd. */ 6055 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6056 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6057 "txmbuf == NULL!\n", __FILE__, __LINE__); 6058 bce_breakpoint(sc)); 6059 6060 DBRUNMSG(BCE_INFO_SEND, 6061 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6062 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 6063 6064 /* Unmap the mbuf. */ 6065 bus_dmamap_unload(sc->tx_mbuf_tag, 6066 sc->tx_mbuf_map[sw_tx_chain_cons]); 6067 6068 /* Free the mbuf. */ 6069 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6070 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6071 DBRUN(sc->debug_tx_mbuf_alloc--); 6072 6073 ifp->if_opackets++; 6074 } 6075 6076 sc->used_tx_bd--; 6077 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6078 6079 /* Refresh hw_cons to see if there's new work. */ 6080 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6081 6082 /* Prevent speculative reads from getting ahead of the status block. */ 6083 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6084 BUS_SPACE_BARRIER_READ); 6085 } 6086 6087 /* Clear the TX timeout timer. */ 6088 sc->watchdog_timer = 0; 6089 6090 /* Clear the tx hardware queue full flag. */ 6091 if (sc->used_tx_bd < sc->max_tx_bd) { 6092 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6093 DBPRINT(sc, BCE_INFO_SEND, 6094 "%s(): Open TX chain! %d/%d (used/total)\n", 6095 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6096 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6097 } 6098 6099 sc->tx_cons = sw_tx_cons; 6100 6101 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6102 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6103 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6104 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6105 } 6106 6107 6108 /****************************************************************************/ 6109 /* Disables interrupt generation. */ 6110 /* */ 6111 /* Returns: */ 6112 /* Nothing. */ 6113 /****************************************************************************/ 6114 static void 6115 bce_disable_intr(struct bce_softc *sc) 6116 { 6117 DBENTER(BCE_VERBOSE_INTR); 6118 6119 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6120 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6121 6122 DBEXIT(BCE_VERBOSE_INTR); 6123 } 6124 6125 6126 /****************************************************************************/ 6127 /* Enables interrupt generation. */ 6128 /* */ 6129 /* Returns: */ 6130 /* Nothing. */ 6131 /****************************************************************************/ 6132 static void 6133 bce_enable_intr(struct bce_softc *sc, int coal_now) 6134 { 6135 DBENTER(BCE_VERBOSE_INTR); 6136 6137 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6138 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6139 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6140 6141 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6142 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6143 6144 /* Force an immediate interrupt (whether there is new data or not). */ 6145 if (coal_now) 6146 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6147 6148 DBEXIT(BCE_VERBOSE_INTR); 6149 } 6150 6151 6152 /****************************************************************************/ 6153 /* Handles controller initialization. */ 6154 /* */ 6155 /* Returns: */ 6156 /* Nothing. */ 6157 /****************************************************************************/ 6158 static void 6159 bce_init_locked(struct bce_softc *sc) 6160 { 6161 struct ifnet *ifp; 6162 u32 ether_mtu = 0; 6163 6164 DBENTER(BCE_VERBOSE_RESET); 6165 6166 BCE_LOCK_ASSERT(sc); 6167 6168 ifp = sc->bce_ifp; 6169 6170 /* Check if the driver is still running and bail out if it is. */ 6171 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6172 goto bce_init_locked_exit; 6173 6174 bce_stop(sc); 6175 6176 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6177 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6178 __FILE__, __LINE__); 6179 goto bce_init_locked_exit; 6180 } 6181 6182 if (bce_chipinit(sc)) { 6183 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6184 __FILE__, __LINE__); 6185 goto bce_init_locked_exit; 6186 } 6187 6188 if (bce_blockinit(sc)) { 6189 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6190 __FILE__, __LINE__); 6191 goto bce_init_locked_exit; 6192 } 6193 6194 /* Load our MAC address. */ 6195 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6196 bce_set_mac_addr(sc); 6197 6198 /* 6199 * Calculate and program the hardware Ethernet MTU 6200 * size. Be generous on the receive if we have room. 6201 */ 6202 #ifdef BCE_USE_SPLIT_HEADER 6203 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size)) 6204 ether_mtu = sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size; 6205 #else 6206 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6207 ether_mtu = sc->rx_bd_mbuf_data_len; 6208 #endif 6209 else 6210 ether_mtu = ifp->if_mtu; 6211 6212 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6213 6214 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__, 6215 ether_mtu); 6216 6217 /* Program the mtu, enabling jumbo frame support if necessary. */ 6218 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6219 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6220 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6221 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6222 else 6223 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6224 6225 DBPRINT(sc, BCE_INFO_LOAD, 6226 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6227 "rx_bd_mbuf_align_pad = %d, pg_bd_mbuf_alloc_size = %d\n", 6228 __FUNCTION__, sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6229 sc->rx_bd_mbuf_align_pad, sc->pg_bd_mbuf_alloc_size); 6230 6231 /* Program appropriate promiscuous/multicast filtering. */ 6232 bce_set_rx_mode(sc); 6233 6234 #ifdef BCE_USE_SPLIT_HEADER 6235 /* Init page buffer descriptor chain. */ 6236 bce_init_pg_chain(sc); 6237 #endif 6238 6239 /* Init RX buffer descriptor chain. */ 6240 bce_init_rx_chain(sc); 6241 6242 /* Init TX buffer descriptor chain. */ 6243 bce_init_tx_chain(sc); 6244 6245 /* Enable host interrupts. */ 6246 bce_enable_intr(sc, 1); 6247 6248 bce_ifmedia_upd_locked(ifp); 6249 6250 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6252 6253 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6254 6255 bce_init_locked_exit: 6256 DBEXIT(BCE_VERBOSE_RESET); 6257 } 6258 6259 6260 /****************************************************************************/ 6261 /* Initialize the controller just enough so that any management firmware */ 6262 /* running on the device will continue to operate correctly. */ 6263 /* */ 6264 /* Returns: */ 6265 /* Nothing. */ 6266 /****************************************************************************/ 6267 static void 6268 bce_mgmt_init_locked(struct bce_softc *sc) 6269 { 6270 struct ifnet *ifp; 6271 6272 DBENTER(BCE_VERBOSE_RESET); 6273 6274 BCE_LOCK_ASSERT(sc); 6275 6276 /* Bail out if management firmware is not running. */ 6277 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6278 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6279 "No management firmware running...\n"); 6280 goto bce_mgmt_init_locked_exit; 6281 } 6282 6283 ifp = sc->bce_ifp; 6284 6285 /* Enable all critical blocks in the MAC. */ 6286 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6287 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6288 DELAY(20); 6289 6290 bce_ifmedia_upd_locked(ifp); 6291 6292 bce_mgmt_init_locked_exit: 6293 DBEXIT(BCE_VERBOSE_RESET); 6294 } 6295 6296 6297 /****************************************************************************/ 6298 /* Handles controller initialization when called from an unlocked routine. */ 6299 /* */ 6300 /* Returns: */ 6301 /* Nothing. */ 6302 /****************************************************************************/ 6303 static void 6304 bce_init(void *xsc) 6305 { 6306 struct bce_softc *sc = xsc; 6307 6308 DBENTER(BCE_VERBOSE_RESET); 6309 6310 BCE_LOCK(sc); 6311 bce_init_locked(sc); 6312 BCE_UNLOCK(sc); 6313 6314 DBEXIT(BCE_VERBOSE_RESET); 6315 } 6316 6317 6318 /****************************************************************************/ 6319 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6320 /* memory visible to the controller. */ 6321 /* */ 6322 /* Returns: */ 6323 /* 0 for success, positive value for failure. */ 6324 /* Modified: */ 6325 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6326 /****************************************************************************/ 6327 static int 6328 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6329 { 6330 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6331 bus_dmamap_t map; 6332 struct tx_bd *txbd = NULL; 6333 struct mbuf *m0; 6334 struct ether_vlan_header *eh; 6335 struct ip *ip; 6336 struct tcphdr *th; 6337 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0; 6338 u32 prod_bseq; 6339 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6340 6341 #ifdef BCE_DEBUG 6342 u16 debug_prod; 6343 #endif 6344 int i, error, nsegs, rc = 0; 6345 6346 DBENTER(BCE_VERBOSE_SEND); 6347 DBPRINT(sc, BCE_INFO_SEND, 6348 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = %04X, " 6349 "tx_prod_bseq = 0x%08X\n", 6350 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6351 sc->tx_prod_bseq); 6352 6353 /* Transfer any checksum offload flags to the bd. */ 6354 m0 = *m_head; 6355 if (m0->m_pkthdr.csum_flags) { 6356 if (m0->m_pkthdr.csum_flags & CSUM_IP) 6357 flags |= TX_BD_FLAGS_IP_CKSUM; 6358 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6359 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6360 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6361 /* For TSO the controller needs two pieces of info, */ 6362 /* the MSS and the IP+TCP options length. */ 6363 mss = htole16(m0->m_pkthdr.tso_segsz); 6364 6365 /* Map the header and find the Ethernet type & header length */ 6366 eh = mtod(m0, struct ether_vlan_header *); 6367 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 6368 etype = ntohs(eh->evl_proto); 6369 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 6370 } else { 6371 etype = ntohs(eh->evl_encap_proto); 6372 e_hlen = ETHER_HDR_LEN; 6373 } 6374 6375 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6376 switch (etype) { 6377 case ETHERTYPE_IP: 6378 ip = (struct ip *)(m0->m_data + e_hlen); 6379 6380 /* TSO only supported for TCP protocol */ 6381 if (ip->ip_p != IPPROTO_TCP) { 6382 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6383 __FILE__, __LINE__); 6384 goto bce_tx_encap_skip_tso; 6385 } 6386 6387 /* Get IP header length in bytes (min 20) */ 6388 ip_hlen = ip->ip_hl << 2; 6389 6390 /* Get the TCP header length in bytes (min 20) */ 6391 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6392 tcp_hlen = (th->th_off << 2); 6393 6394 /* IP header length and checksum will be calc'd by hardware */ 6395 ip_len = ip->ip_len; 6396 ip->ip_len = 0; 6397 ip->ip_sum = 0; 6398 break; 6399 case ETHERTYPE_IPV6: 6400 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6401 __FILE__, __LINE__); 6402 goto bce_tx_encap_skip_tso; 6403 default: 6404 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6405 __FILE__, __LINE__); 6406 goto bce_tx_encap_skip_tso; 6407 } 6408 6409 hdr_len = e_hlen + ip_hlen + tcp_hlen; 6410 6411 DBPRINT(sc, BCE_EXTREME_SEND, 6412 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6413 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len); 6414 6415 /* Set the LSO flag in the TX BD */ 6416 flags |= TX_BD_FLAGS_SW_LSO; 6417 /* Set the length of IP + TCP options (in 32 bit words) */ 6418 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8); 6419 6420 bce_tx_encap_skip_tso: 6421 DBRUN(sc->requested_tso_frames++); 6422 } 6423 } 6424 6425 /* Transfer any VLAN tags to the bd. */ 6426 if (m0->m_flags & M_VLANTAG) { 6427 flags |= TX_BD_FLAGS_VLAN_TAG; 6428 vlan_tag = m0->m_pkthdr.ether_vtag; 6429 } 6430 6431 /* Map the mbuf into DMAable memory. */ 6432 prod = sc->tx_prod; 6433 chain_prod = TX_CHAIN_IDX(prod); 6434 map = sc->tx_mbuf_map[chain_prod]; 6435 6436 /* Map the mbuf into our DMA address space. */ 6437 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6438 segs, &nsegs, BUS_DMA_NOWAIT); 6439 6440 /* Check if the DMA mapping was successful */ 6441 if (error == EFBIG) { 6442 6443 /* The mbuf is too fragmented for our DMA mapping. */ 6444 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 6445 __FUNCTION__, nsegs); 6446 DBRUN(bce_dump_mbuf(sc, m0);); 6447 6448 /* Try to defrag the mbuf. */ 6449 m0 = m_defrag(*m_head, M_DONTWAIT); 6450 if (m0 == NULL) { 6451 /* Defrag was unsuccessful */ 6452 m_freem(*m_head); 6453 *m_head = NULL; 6454 sc->mbuf_alloc_failed++; 6455 rc = ENOBUFS; 6456 goto bce_tx_encap_exit; 6457 } 6458 6459 /* Defrag was successful, try mapping again */ 6460 *m_head = m0; 6461 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6462 segs, &nsegs, BUS_DMA_NOWAIT); 6463 6464 /* Still getting an error after a defrag. */ 6465 if (error == ENOMEM) { 6466 /* Insufficient DMA buffers available. */ 6467 sc->tx_dma_map_failures++; 6468 rc = error; 6469 goto bce_tx_encap_exit; 6470 } else if (error != 0) { 6471 /* Still can't map the mbuf, release it and return an error. */ 6472 BCE_PRINTF( 6473 "%s(%d): Unknown error mapping mbuf into TX chain!\n", 6474 __FILE__, __LINE__); 6475 m_freem(m0); 6476 *m_head = NULL; 6477 sc->tx_dma_map_failures++; 6478 rc = ENOBUFS; 6479 goto bce_tx_encap_exit; 6480 } 6481 } else if (error == ENOMEM) { 6482 /* Insufficient DMA buffers available. */ 6483 sc->tx_dma_map_failures++; 6484 rc = error; 6485 goto bce_tx_encap_exit; 6486 } else if (error != 0) { 6487 m_freem(m0); 6488 *m_head = NULL; 6489 sc->tx_dma_map_failures++; 6490 rc = error; 6491 goto bce_tx_encap_exit; 6492 } 6493 6494 /* Make sure there's room in the chain */ 6495 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6496 bus_dmamap_unload(sc->tx_mbuf_tag, map); 6497 rc = ENOBUFS; 6498 goto bce_tx_encap_exit; 6499 } 6500 6501 /* prod points to an empty tx_bd at this point. */ 6502 prod_bseq = sc->tx_prod_bseq; 6503 6504 #ifdef BCE_DEBUG 6505 debug_prod = chain_prod; 6506 #endif 6507 6508 DBPRINT(sc, BCE_INFO_SEND, 6509 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6510 "prod_bseq = 0x%08X\n", 6511 __FUNCTION__, prod, chain_prod, prod_bseq); 6512 6513 /* 6514 * Cycle through each mbuf segment that makes up 6515 * the outgoing frame, gathering the mapping info 6516 * for that segment and creating a tx_bd for 6517 * the mbuf. 6518 */ 6519 for (i = 0; i < nsegs ; i++) { 6520 6521 chain_prod = TX_CHAIN_IDX(prod); 6522 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 6523 6524 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6525 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6526 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 6527 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6528 txbd->tx_bd_flags = htole16(flags); 6529 prod_bseq += segs[i].ds_len; 6530 if (i == 0) 6531 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6532 prod = NEXT_TX_BD(prod); 6533 } 6534 6535 /* Set the END flag on the last TX buffer descriptor. */ 6536 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6537 6538 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 6539 6540 DBPRINT(sc, BCE_INFO_SEND, 6541 "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, " 6542 "prod_bseq = 0x%08X\n", 6543 __FUNCTION__, prod, chain_prod, prod_bseq); 6544 6545 /* 6546 * Ensure that the mbuf pointer for this transmission 6547 * is placed at the array index of the last 6548 * descriptor in this chain. This is done 6549 * because a single map is used for all 6550 * segments of the mbuf and we don't want to 6551 * unload the map before all of the segments 6552 * have been freed. 6553 */ 6554 sc->tx_mbuf_ptr[chain_prod] = m0; 6555 sc->used_tx_bd += nsegs; 6556 6557 /* Update some debug statistic counters */ 6558 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6559 sc->tx_hi_watermark = sc->used_tx_bd); 6560 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6561 DBRUNIF(sc->debug_tx_mbuf_alloc++); 6562 6563 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6564 6565 /* prod points to the next free tx_bd at this point. */ 6566 sc->tx_prod = prod; 6567 sc->tx_prod_bseq = prod_bseq; 6568 6569 DBPRINT(sc, BCE_INFO_SEND, 6570 "%s(exit): prod = 0x%04X, chain_prod = %04X, " 6571 "prod_bseq = 0x%08X\n", 6572 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6573 sc->tx_prod_bseq); 6574 6575 bce_tx_encap_exit: 6576 DBEXIT(BCE_VERBOSE_SEND); 6577 return(rc); 6578 } 6579 6580 6581 /****************************************************************************/ 6582 /* Main transmit routine when called from another routine with a lock. */ 6583 /* */ 6584 /* Returns: */ 6585 /* Nothing. */ 6586 /****************************************************************************/ 6587 static void 6588 bce_start_locked(struct ifnet *ifp) 6589 { 6590 struct bce_softc *sc = ifp->if_softc; 6591 struct mbuf *m_head = NULL; 6592 int count = 0; 6593 u16 tx_prod, tx_chain_prod; 6594 6595 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 6596 6597 BCE_LOCK_ASSERT(sc); 6598 6599 /* prod points to the next free tx_bd. */ 6600 tx_prod = sc->tx_prod; 6601 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 6602 6603 DBPRINT(sc, BCE_INFO_SEND, 6604 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 6605 "tx_prod_bseq = 0x%08X\n", 6606 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 6607 6608 /* If there's no link or the transmit queue is empty then just exit. */ 6609 if (!sc->bce_link) { 6610 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 6611 __FUNCTION__); 6612 goto bce_start_locked_exit; 6613 } 6614 6615 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 6616 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 6617 __FUNCTION__); 6618 goto bce_start_locked_exit; 6619 } 6620 6621 /* 6622 * Keep adding entries while there is space in the ring. 6623 */ 6624 while (sc->used_tx_bd < sc->max_tx_bd) { 6625 6626 /* Check for any frames to send. */ 6627 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 6628 6629 /* Stop when the transmit queue is empty. */ 6630 if (m_head == NULL) 6631 break; 6632 6633 /* 6634 * Pack the data into the transmit ring. If we 6635 * don't have room, place the mbuf back at the 6636 * head of the queue and set the OACTIVE flag 6637 * to wait for the NIC to drain the chain. 6638 */ 6639 if (bce_tx_encap(sc, &m_head)) { 6640 /* No room, put the frame back on the transmit queue. */ 6641 if (m_head != NULL) 6642 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 6643 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 6644 DBPRINT(sc, BCE_INFO_SEND, 6645 "TX chain is closed for business! Total tx_bd used = %d\n", 6646 sc->used_tx_bd); 6647 break; 6648 } 6649 6650 count++; 6651 6652 /* Send a copy of the frame to any BPF listeners. */ 6653 ETHER_BPF_MTAP(ifp, m_head); 6654 } 6655 6656 /* Exit if no packets were dequeued. */ 6657 if (count == 0) { 6658 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 6659 __FUNCTION__); 6660 goto bce_start_locked_exit; 6661 } 6662 6663 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into send queue.\n", 6664 __FUNCTION__, count); 6665 6666 REG_WR(sc, BCE_MQ_COMMAND, REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR); 6667 6668 /* Write the mailbox and tell the chip about the waiting tx_bd's. */ 6669 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6670 "BCE_L2CTX_TX_HOST_BIDX = 0x%08X, sc->tx_prod = 0x%04X\n", 6671 __FUNCTION__, 6672 MB_GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 6673 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 6674 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6675 "BCE_L2CTX_TX_HOST_BSEQ = 0x%08X, sc->tx_prod_bseq = 0x%04X\n", 6676 __FUNCTION__, 6677 MB_GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 6678 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 6679 6680 /* Set the tx timeout. */ 6681 sc->watchdog_timer = BCE_TX_TIMEOUT; 6682 6683 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 6684 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 6685 6686 bce_start_locked_exit: 6687 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 6688 return; 6689 } 6690 6691 6692 /****************************************************************************/ 6693 /* Main transmit routine when called from another routine without a lock. */ 6694 /* */ 6695 /* Returns: */ 6696 /* Nothing. */ 6697 /****************************************************************************/ 6698 static void 6699 bce_start(struct ifnet *ifp) 6700 { 6701 struct bce_softc *sc = ifp->if_softc; 6702 6703 DBENTER(BCE_VERBOSE_SEND); 6704 6705 BCE_LOCK(sc); 6706 bce_start_locked(ifp); 6707 BCE_UNLOCK(sc); 6708 6709 DBEXIT(BCE_VERBOSE_SEND); 6710 } 6711 6712 6713 /****************************************************************************/ 6714 /* Handles any IOCTL calls from the operating system. */ 6715 /* */ 6716 /* Returns: */ 6717 /* 0 for success, positive value for failure. */ 6718 /****************************************************************************/ 6719 static int 6720 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 6721 { 6722 struct bce_softc *sc = ifp->if_softc; 6723 struct ifreq *ifr = (struct ifreq *) data; 6724 struct mii_data *mii; 6725 int mask, error = 0; 6726 6727 DBENTER(BCE_VERBOSE_MISC); 6728 6729 switch(command) { 6730 6731 /* Set the interface MTU. */ 6732 case SIOCSIFMTU: 6733 /* Check that the MTU setting is supported. */ 6734 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 6735 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 6736 error = EINVAL; 6737 break; 6738 } 6739 6740 DBPRINT(sc, BCE_INFO_MISC, 6741 "SIOCSIFMTU: Changing MTU from %d to %d\n", 6742 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 6743 6744 BCE_LOCK(sc); 6745 ifp->if_mtu = ifr->ifr_mtu; 6746 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6747 #ifdef BCE_USE_SPLIT_HEADER 6748 /* No buffer allocation size changes are necessary. */ 6749 #else 6750 /* Recalculate our buffer allocation sizes. */ 6751 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN) > MCLBYTES) { 6752 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 6753 sc->rx_bd_mbuf_align_pad = roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 6754 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 6755 sc->rx_bd_mbuf_align_pad; 6756 } else { 6757 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 6758 sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 6759 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 6760 sc->rx_bd_mbuf_align_pad; 6761 } 6762 #endif 6763 6764 bce_init_locked(sc); 6765 BCE_UNLOCK(sc); 6766 break; 6767 6768 /* Set interface flags. */ 6769 case SIOCSIFFLAGS: 6770 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 6771 6772 BCE_LOCK(sc); 6773 6774 /* Check if the interface is up. */ 6775 if (ifp->if_flags & IFF_UP) { 6776 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6777 /* Change promiscuous/multicast flags as necessary. */ 6778 bce_set_rx_mode(sc); 6779 } else { 6780 /* Start the HW */ 6781 bce_init_locked(sc); 6782 } 6783 } else { 6784 /* The interface is down, check if driver is running. */ 6785 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6786 bce_stop(sc); 6787 6788 /* If MFW is running, restart the controller a bit. */ 6789 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 6790 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 6791 bce_chipinit(sc); 6792 bce_mgmt_init_locked(sc); 6793 } 6794 } 6795 } 6796 6797 BCE_UNLOCK(sc); 6798 error = 0; 6799 6800 break; 6801 6802 /* Add/Delete multicast address */ 6803 case SIOCADDMULTI: 6804 case SIOCDELMULTI: 6805 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 6806 6807 BCE_LOCK(sc); 6808 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6809 bce_set_rx_mode(sc); 6810 error = 0; 6811 } 6812 BCE_UNLOCK(sc); 6813 6814 break; 6815 6816 /* Set/Get Interface media */ 6817 case SIOCSIFMEDIA: 6818 case SIOCGIFMEDIA: 6819 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 6820 6821 mii = device_get_softc(sc->bce_miibus); 6822 error = ifmedia_ioctl(ifp, ifr, 6823 &mii->mii_media, command); 6824 break; 6825 6826 /* Set interface capability */ 6827 case SIOCSIFCAP: 6828 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 6829 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 6830 6831 /* Toggle the TX checksum capabilites enable flag. */ 6832 if (mask & IFCAP_TXCSUM) { 6833 ifp->if_capenable ^= IFCAP_TXCSUM; 6834 if (IFCAP_TXCSUM & ifp->if_capenable) 6835 ifp->if_hwassist = BCE_IF_HWASSIST; 6836 else 6837 ifp->if_hwassist = 0; 6838 } 6839 6840 /* Toggle the RX checksum capabilities enable flag. */ 6841 if (mask & IFCAP_RXCSUM) { 6842 ifp->if_capenable ^= IFCAP_RXCSUM; 6843 if (IFCAP_RXCSUM & ifp->if_capenable) 6844 ifp->if_hwassist = BCE_IF_HWASSIST; 6845 else 6846 ifp->if_hwassist = 0; 6847 } 6848 6849 /* Toggle the TSO capabilities enable flag. */ 6850 if (bce_tso_enable && (mask & IFCAP_TSO4)) { 6851 ifp->if_capenable ^= IFCAP_TSO4; 6852 if (IFCAP_RXCSUM & ifp->if_capenable) 6853 ifp->if_hwassist = BCE_IF_HWASSIST; 6854 else 6855 ifp->if_hwassist = 0; 6856 } 6857 6858 /* Toggle VLAN_MTU capabilities enable flag. */ 6859 if (mask & IFCAP_VLAN_MTU) { 6860 BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n", 6861 __FILE__, __LINE__); 6862 } 6863 6864 /* Toggle VLANHWTAG capabilities enabled flag. */ 6865 if (mask & IFCAP_VLAN_HWTAGGING) { 6866 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 6867 BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while " 6868 "management firmware (ASF/IPMI/UMP) is running!\n", 6869 __FILE__, __LINE__); 6870 else 6871 BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n", 6872 __FILE__, __LINE__); 6873 } 6874 6875 break; 6876 default: 6877 /* We don't know how to handle the IOCTL, pass it on. */ 6878 error = ether_ioctl(ifp, command, data); 6879 break; 6880 } 6881 6882 DBEXIT(BCE_VERBOSE_MISC); 6883 return(error); 6884 } 6885 6886 6887 /****************************************************************************/ 6888 /* Transmit timeout handler. */ 6889 /* */ 6890 /* Returns: */ 6891 /* Nothing. */ 6892 /****************************************************************************/ 6893 static void 6894 bce_watchdog(struct bce_softc *sc) 6895 { 6896 DBENTER(BCE_EXTREME_SEND); 6897 6898 BCE_LOCK_ASSERT(sc); 6899 6900 /* If the watchdog timer hasn't expired then just exit. */ 6901 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 6902 goto bce_watchdog_exit; 6903 6904 /* If pause frames are active then don't reset the hardware. */ 6905 /* ToDo: Should we reset the timer here? */ 6906 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 6907 goto bce_watchdog_exit; 6908 6909 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 6910 __FILE__, __LINE__); 6911 6912 DBRUNMSG(BCE_INFO, 6913 bce_dump_driver_state(sc); 6914 bce_dump_status_block(sc); 6915 bce_dump_stats_block(sc); 6916 bce_dump_ftqs(sc); 6917 bce_dump_txp_state(sc, 0); 6918 bce_dump_rxp_state(sc, 0); 6919 bce_dump_tpat_state(sc, 0); 6920 bce_dump_cp_state(sc, 0); 6921 bce_dump_com_state(sc, 0)); 6922 6923 DBRUN(bce_breakpoint(sc)); 6924 6925 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6926 6927 bce_init_locked(sc); 6928 sc->bce_ifp->if_oerrors++; 6929 6930 bce_watchdog_exit: 6931 DBEXIT(BCE_EXTREME_SEND); 6932 } 6933 6934 6935 /* 6936 * Interrupt handler. 6937 */ 6938 /****************************************************************************/ 6939 /* Main interrupt entry point. Verifies that the controller generated the */ 6940 /* interrupt and then calls a separate routine for handle the various */ 6941 /* interrupt causes (PHY, TX, RX). */ 6942 /* */ 6943 /* Returns: */ 6944 /* 0 for success, positive value for failure. */ 6945 /****************************************************************************/ 6946 static void 6947 bce_intr(void *xsc) 6948 { 6949 struct bce_softc *sc; 6950 struct ifnet *ifp; 6951 u32 status_attn_bits; 6952 u16 hw_rx_cons, hw_tx_cons; 6953 6954 sc = xsc; 6955 ifp = sc->bce_ifp; 6956 6957 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6958 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 6959 6960 BCE_LOCK(sc); 6961 6962 DBRUN(sc->interrupts_generated++); 6963 6964 bus_dmamap_sync(sc->status_tag, sc->status_map, 6965 BUS_DMASYNC_POSTWRITE); 6966 6967 /* 6968 * If the hardware status block index 6969 * matches the last value read by the 6970 * driver and we haven't asserted our 6971 * interrupt then there's nothing to do. 6972 */ 6973 if ((sc->status_block->status_idx == sc->last_status_idx) && 6974 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 6975 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 6976 __FUNCTION__); 6977 goto bce_intr_exit; 6978 } 6979 6980 /* Ack the interrupt and stop others from occuring. */ 6981 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6982 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 6983 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6984 6985 /* Check if the hardware has finished any work. */ 6986 hw_rx_cons = bce_get_hw_rx_cons(sc); 6987 hw_tx_cons = bce_get_hw_tx_cons(sc); 6988 6989 /* Keep processing data as long as there is work to do. */ 6990 for (;;) { 6991 6992 status_attn_bits = sc->status_block->status_attn_bits; 6993 6994 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 6995 BCE_PRINTF("Simulating unexpected status attention bit set."); 6996 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 6997 6998 /* Was it a link change interrupt? */ 6999 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7000 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 7001 bce_phy_intr(sc); 7002 7003 /* Clear any transient status updates during link state change. */ 7004 REG_WR(sc, BCE_HC_COMMAND, 7005 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT); 7006 REG_RD(sc, BCE_HC_COMMAND); 7007 7008 /* If any other attention is asserted then the chip is toast. */ 7009 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7010 (sc->status_block->status_attn_bits_ack & 7011 ~STATUS_ATTN_BITS_LINK_STATE))) { 7012 7013 DBRUN(sc->unexpected_attentions++); 7014 7015 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 7016 __FILE__, __LINE__, sc->status_block->status_attn_bits); 7017 7018 DBRUNMSG(BCE_FATAL, 7019 if (bce_debug_unexpected_attention == 0) 7020 bce_breakpoint(sc)); 7021 7022 bce_init_locked(sc); 7023 goto bce_intr_exit; 7024 } 7025 7026 /* Check for any completed RX frames. */ 7027 if (hw_rx_cons != sc->hw_rx_cons) 7028 bce_rx_intr(sc); 7029 7030 /* Check for any completed TX frames. */ 7031 if (hw_tx_cons != sc->hw_tx_cons) 7032 bce_tx_intr(sc); 7033 7034 /* Save the status block index value for use during the next interrupt. */ 7035 sc->last_status_idx = sc->status_block->status_idx; 7036 7037 /* Prevent speculative reads from getting ahead of the status block. */ 7038 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7039 BUS_SPACE_BARRIER_READ); 7040 7041 /* If there's no work left then exit the interrupt service routine. */ 7042 hw_rx_cons = bce_get_hw_rx_cons(sc); 7043 hw_tx_cons = bce_get_hw_tx_cons(sc); 7044 7045 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons)) 7046 break; 7047 7048 } 7049 7050 bus_dmamap_sync(sc->status_tag, sc->status_map, 7051 BUS_DMASYNC_PREWRITE); 7052 7053 /* Re-enable interrupts. */ 7054 bce_enable_intr(sc, 0); 7055 7056 /* Handle any frames that arrived while handling the interrupt. */ 7057 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7058 bce_start_locked(ifp); 7059 7060 bce_intr_exit: 7061 BCE_UNLOCK(sc); 7062 7063 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7064 } 7065 7066 7067 /****************************************************************************/ 7068 /* Programs the various packet receive modes (broadcast and multicast). */ 7069 /* */ 7070 /* Returns: */ 7071 /* Nothing. */ 7072 /****************************************************************************/ 7073 static void 7074 bce_set_rx_mode(struct bce_softc *sc) 7075 { 7076 struct ifnet *ifp; 7077 struct ifmultiaddr *ifma; 7078 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7079 u32 rx_mode, sort_mode; 7080 int h, i; 7081 7082 DBENTER(BCE_VERBOSE_MISC); 7083 7084 BCE_LOCK_ASSERT(sc); 7085 7086 ifp = sc->bce_ifp; 7087 7088 /* Initialize receive mode default settings. */ 7089 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7090 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7091 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7092 7093 /* 7094 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7095 * be enbled. 7096 */ 7097 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7098 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7099 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7100 7101 /* 7102 * Check for promiscuous, all multicast, or selected 7103 * multicast address filtering. 7104 */ 7105 if (ifp->if_flags & IFF_PROMISC) { 7106 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7107 7108 /* Enable promiscuous mode. */ 7109 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7110 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7111 } else if (ifp->if_flags & IFF_ALLMULTI) { 7112 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7113 7114 /* Enable all multicast addresses. */ 7115 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7116 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7117 } 7118 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7119 } else { 7120 /* Accept one or more multicast(s). */ 7121 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7122 7123 IF_ADDR_LOCK(ifp); 7124 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7125 if (ifma->ifma_addr->sa_family != AF_LINK) 7126 continue; 7127 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7128 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7129 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7130 } 7131 IF_ADDR_UNLOCK(ifp); 7132 7133 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7134 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7135 7136 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7137 } 7138 7139 /* Only make changes if the recive mode has actually changed. */ 7140 if (rx_mode != sc->rx_mode) { 7141 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n", 7142 rx_mode); 7143 7144 sc->rx_mode = rx_mode; 7145 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7146 } 7147 7148 /* Disable and clear the exisitng sort before enabling a new sort. */ 7149 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7150 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7151 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7152 7153 DBEXIT(BCE_VERBOSE_MISC); 7154 } 7155 7156 7157 /****************************************************************************/ 7158 /* Called periodically to updates statistics from the controllers */ 7159 /* statistics block. */ 7160 /* */ 7161 /* Returns: */ 7162 /* Nothing. */ 7163 /****************************************************************************/ 7164 static void 7165 bce_stats_update(struct bce_softc *sc) 7166 { 7167 struct ifnet *ifp; 7168 struct statistics_block *stats; 7169 7170 DBENTER(BCE_EXTREME_MISC); 7171 7172 ifp = sc->bce_ifp; 7173 7174 stats = (struct statistics_block *) sc->stats_block; 7175 7176 /* 7177 * Certain controllers don't report 7178 * carrier sense errors correctly. 7179 * See errata E11_5708CA0_1165. 7180 */ 7181 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7182 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7183 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7184 7185 /* 7186 * Update the sysctl statistics from the 7187 * hardware statistics. 7188 */ 7189 sc->stat_IfHCInOctets = 7190 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7191 (u64) stats->stat_IfHCInOctets_lo; 7192 7193 sc->stat_IfHCInBadOctets = 7194 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7195 (u64) stats->stat_IfHCInBadOctets_lo; 7196 7197 sc->stat_IfHCOutOctets = 7198 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7199 (u64) stats->stat_IfHCOutOctets_lo; 7200 7201 sc->stat_IfHCOutBadOctets = 7202 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7203 (u64) stats->stat_IfHCOutBadOctets_lo; 7204 7205 sc->stat_IfHCInUcastPkts = 7206 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7207 (u64) stats->stat_IfHCInUcastPkts_lo; 7208 7209 sc->stat_IfHCInMulticastPkts = 7210 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7211 (u64) stats->stat_IfHCInMulticastPkts_lo; 7212 7213 sc->stat_IfHCInBroadcastPkts = 7214 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7215 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7216 7217 sc->stat_IfHCOutUcastPkts = 7218 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7219 (u64) stats->stat_IfHCOutUcastPkts_lo; 7220 7221 sc->stat_IfHCOutMulticastPkts = 7222 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7223 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7224 7225 sc->stat_IfHCOutBroadcastPkts = 7226 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7227 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7228 7229 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7230 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7231 7232 sc->stat_Dot3StatsCarrierSenseErrors = 7233 stats->stat_Dot3StatsCarrierSenseErrors; 7234 7235 sc->stat_Dot3StatsFCSErrors = 7236 stats->stat_Dot3StatsFCSErrors; 7237 7238 sc->stat_Dot3StatsAlignmentErrors = 7239 stats->stat_Dot3StatsAlignmentErrors; 7240 7241 sc->stat_Dot3StatsSingleCollisionFrames = 7242 stats->stat_Dot3StatsSingleCollisionFrames; 7243 7244 sc->stat_Dot3StatsMultipleCollisionFrames = 7245 stats->stat_Dot3StatsMultipleCollisionFrames; 7246 7247 sc->stat_Dot3StatsDeferredTransmissions = 7248 stats->stat_Dot3StatsDeferredTransmissions; 7249 7250 sc->stat_Dot3StatsExcessiveCollisions = 7251 stats->stat_Dot3StatsExcessiveCollisions; 7252 7253 sc->stat_Dot3StatsLateCollisions = 7254 stats->stat_Dot3StatsLateCollisions; 7255 7256 sc->stat_EtherStatsCollisions = 7257 stats->stat_EtherStatsCollisions; 7258 7259 sc->stat_EtherStatsFragments = 7260 stats->stat_EtherStatsFragments; 7261 7262 sc->stat_EtherStatsJabbers = 7263 stats->stat_EtherStatsJabbers; 7264 7265 sc->stat_EtherStatsUndersizePkts = 7266 stats->stat_EtherStatsUndersizePkts; 7267 7268 sc->stat_EtherStatsOverrsizePkts = 7269 stats->stat_EtherStatsOverrsizePkts; 7270 7271 sc->stat_EtherStatsPktsRx64Octets = 7272 stats->stat_EtherStatsPktsRx64Octets; 7273 7274 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7275 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7276 7277 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7278 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7279 7280 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7281 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7282 7283 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7284 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7285 7286 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7287 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7288 7289 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7290 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7291 7292 sc->stat_EtherStatsPktsTx64Octets = 7293 stats->stat_EtherStatsPktsTx64Octets; 7294 7295 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7296 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7297 7298 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7299 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7300 7301 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7302 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7303 7304 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7305 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7306 7307 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7308 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7309 7310 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7311 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7312 7313 sc->stat_XonPauseFramesReceived = 7314 stats->stat_XonPauseFramesReceived; 7315 7316 sc->stat_XoffPauseFramesReceived = 7317 stats->stat_XoffPauseFramesReceived; 7318 7319 sc->stat_OutXonSent = 7320 stats->stat_OutXonSent; 7321 7322 sc->stat_OutXoffSent = 7323 stats->stat_OutXoffSent; 7324 7325 sc->stat_FlowControlDone = 7326 stats->stat_FlowControlDone; 7327 7328 sc->stat_MacControlFramesReceived = 7329 stats->stat_MacControlFramesReceived; 7330 7331 sc->stat_XoffStateEntered = 7332 stats->stat_XoffStateEntered; 7333 7334 sc->stat_IfInFramesL2FilterDiscards = 7335 stats->stat_IfInFramesL2FilterDiscards; 7336 7337 sc->stat_IfInRuleCheckerDiscards = 7338 stats->stat_IfInRuleCheckerDiscards; 7339 7340 sc->stat_IfInFTQDiscards = 7341 stats->stat_IfInFTQDiscards; 7342 7343 sc->stat_IfInMBUFDiscards = 7344 stats->stat_IfInMBUFDiscards; 7345 7346 sc->stat_IfInRuleCheckerP4Hit = 7347 stats->stat_IfInRuleCheckerP4Hit; 7348 7349 sc->stat_CatchupInRuleCheckerDiscards = 7350 stats->stat_CatchupInRuleCheckerDiscards; 7351 7352 sc->stat_CatchupInFTQDiscards = 7353 stats->stat_CatchupInFTQDiscards; 7354 7355 sc->stat_CatchupInMBUFDiscards = 7356 stats->stat_CatchupInMBUFDiscards; 7357 7358 sc->stat_CatchupInRuleCheckerP4Hit = 7359 stats->stat_CatchupInRuleCheckerP4Hit; 7360 7361 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7362 7363 /* 7364 * Update the interface statistics from the 7365 * hardware statistics. 7366 */ 7367 ifp->if_collisions = (u_long) sc->stat_EtherStatsCollisions; 7368 7369 ifp->if_ierrors = (u_long) sc->stat_EtherStatsUndersizePkts + 7370 (u_long) sc->stat_EtherStatsOverrsizePkts + 7371 (u_long) sc->stat_IfInMBUFDiscards + 7372 (u_long) sc->stat_Dot3StatsAlignmentErrors + 7373 (u_long) sc->stat_Dot3StatsFCSErrors + 7374 (u_long) sc->stat_IfInFramesL2FilterDiscards + 7375 (u_long) sc->stat_IfInRuleCheckerDiscards + 7376 (u_long) sc->stat_IfInFTQDiscards + 7377 (u_long) sc->com_no_buffers; 7378 7379 ifp->if_oerrors = (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7380 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7381 (u_long) sc->stat_Dot3StatsLateCollisions; 7382 7383 DBEXIT(BCE_EXTREME_MISC); 7384 } 7385 7386 7387 /****************************************************************************/ 7388 /* Periodic function to notify the bootcode that the driver is still */ 7389 /* present. */ 7390 /* */ 7391 /* Returns: */ 7392 /* Nothing. */ 7393 /****************************************************************************/ 7394 static void 7395 bce_pulse(void *xsc) 7396 { 7397 struct bce_softc *sc = xsc; 7398 u32 msg; 7399 7400 DBENTER(BCE_EXTREME_MISC); 7401 7402 BCE_LOCK_ASSERT(sc); 7403 7404 /* Tell the firmware that the driver is still running. */ 7405 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7406 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 7407 7408 /* Schedule the next pulse. */ 7409 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7410 7411 DBEXIT(BCE_EXTREME_MISC); 7412 } 7413 7414 7415 /****************************************************************************/ 7416 /* Periodic function to perform maintenance tasks. */ 7417 /* */ 7418 /* Returns: */ 7419 /* Nothing. */ 7420 /****************************************************************************/ 7421 static void 7422 bce_tick(void *xsc) 7423 { 7424 struct bce_softc *sc = xsc; 7425 struct mii_data *mii; 7426 struct ifnet *ifp; 7427 7428 ifp = sc->bce_ifp; 7429 7430 DBENTER(BCE_EXTREME_MISC); 7431 7432 BCE_LOCK_ASSERT(sc); 7433 7434 /* Schedule the next tick. */ 7435 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7436 7437 /* Update the statistics from the hardware statistics block. */ 7438 bce_stats_update(sc); 7439 7440 /* Top off the receive and page chains. */ 7441 #ifdef BCE_USE_SPLIT_HEADER 7442 bce_fill_pg_chain(sc); 7443 #endif 7444 bce_fill_rx_chain(sc); 7445 7446 /* Check that chip hasn't hung. */ 7447 bce_watchdog(sc); 7448 7449 /* If link is up already up then we're done. */ 7450 if (sc->bce_link) 7451 goto bce_tick_exit; 7452 7453 mii = device_get_softc(sc->bce_miibus); 7454 mii_tick(mii); 7455 7456 /* Check if the link has come up. */ 7457 if ((mii->mii_media_status & IFM_ACTIVE) && 7458 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7459 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", __FUNCTION__); 7460 sc->bce_link++; 7461 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7462 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 7463 bootverbose) 7464 BCE_PRINTF("Gigabit link up!\n"); 7465 /* Now that link is up, handle any outstanding TX traffic. */ 7466 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7467 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found pending TX traffic.\n", 7468 __FUNCTION__); 7469 bce_start_locked(ifp); 7470 } 7471 } 7472 7473 bce_tick_exit: 7474 DBEXIT(BCE_EXTREME_MISC); 7475 return; 7476 } 7477 7478 7479 #ifdef BCE_DEBUG 7480 /****************************************************************************/ 7481 /* Allows the driver state to be dumped through the sysctl interface. */ 7482 /* */ 7483 /* Returns: */ 7484 /* 0 for success, positive value for failure. */ 7485 /****************************************************************************/ 7486 static int 7487 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7488 { 7489 int error; 7490 int result; 7491 struct bce_softc *sc; 7492 7493 result = -1; 7494 error = sysctl_handle_int(oidp, &result, 0, req); 7495 7496 if (error || !req->newptr) 7497 return (error); 7498 7499 if (result == 1) { 7500 sc = (struct bce_softc *)arg1; 7501 bce_dump_driver_state(sc); 7502 } 7503 7504 return error; 7505 } 7506 7507 7508 /****************************************************************************/ 7509 /* Allows the hardware state to be dumped through the sysctl interface. */ 7510 /* */ 7511 /* Returns: */ 7512 /* 0 for success, positive value for failure. */ 7513 /****************************************************************************/ 7514 static int 7515 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 7516 { 7517 int error; 7518 int result; 7519 struct bce_softc *sc; 7520 7521 result = -1; 7522 error = sysctl_handle_int(oidp, &result, 0, req); 7523 7524 if (error || !req->newptr) 7525 return (error); 7526 7527 if (result == 1) { 7528 sc = (struct bce_softc *)arg1; 7529 bce_dump_hw_state(sc); 7530 } 7531 7532 return error; 7533 } 7534 7535 7536 /****************************************************************************/ 7537 /* Allows the bootcode state to be dumped through the sysctl interface. */ 7538 /* */ 7539 /* Returns: */ 7540 /* 0 for success, positive value for failure. */ 7541 /****************************************************************************/ 7542 static int 7543 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 7544 { 7545 int error; 7546 int result; 7547 struct bce_softc *sc; 7548 7549 result = -1; 7550 error = sysctl_handle_int(oidp, &result, 0, req); 7551 7552 if (error || !req->newptr) 7553 return (error); 7554 7555 if (result == 1) { 7556 sc = (struct bce_softc *)arg1; 7557 bce_dump_bc_state(sc); 7558 } 7559 7560 return error; 7561 } 7562 7563 7564 /****************************************************************************/ 7565 /* Provides a sysctl interface to allow dumping the RX chain. */ 7566 /* */ 7567 /* Returns: */ 7568 /* 0 for success, positive value for failure. */ 7569 /****************************************************************************/ 7570 static int 7571 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 7572 { 7573 int error; 7574 int result; 7575 struct bce_softc *sc; 7576 7577 result = -1; 7578 error = sysctl_handle_int(oidp, &result, 0, req); 7579 7580 if (error || !req->newptr) 7581 return (error); 7582 7583 if (result == 1) { 7584 sc = (struct bce_softc *)arg1; 7585 bce_dump_rx_chain(sc, 0, TOTAL_RX_BD); 7586 } 7587 7588 return error; 7589 } 7590 7591 7592 /****************************************************************************/ 7593 /* Provides a sysctl interface to allow dumping the TX chain. */ 7594 /* */ 7595 /* Returns: */ 7596 /* 0 for success, positive value for failure. */ 7597 /****************************************************************************/ 7598 static int 7599 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 7600 { 7601 int error; 7602 int result; 7603 struct bce_softc *sc; 7604 7605 result = -1; 7606 error = sysctl_handle_int(oidp, &result, 0, req); 7607 7608 if (error || !req->newptr) 7609 return (error); 7610 7611 if (result == 1) { 7612 sc = (struct bce_softc *)arg1; 7613 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7614 } 7615 7616 return error; 7617 } 7618 7619 7620 #ifdef BCE_USE_SPLIT_HEADER 7621 /****************************************************************************/ 7622 /* Provides a sysctl interface to allow dumping the page chain. */ 7623 /* */ 7624 /* Returns: */ 7625 /* 0 for success, positive value for failure. */ 7626 /****************************************************************************/ 7627 static int 7628 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 7629 { 7630 int error; 7631 int result; 7632 struct bce_softc *sc; 7633 7634 result = -1; 7635 error = sysctl_handle_int(oidp, &result, 0, req); 7636 7637 if (error || !req->newptr) 7638 return (error); 7639 7640 if (result == 1) { 7641 sc = (struct bce_softc *)arg1; 7642 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 7643 } 7644 7645 return error; 7646 } 7647 #endif 7648 7649 /****************************************************************************/ 7650 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 7651 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7652 /* */ 7653 /* Returns: */ 7654 /* 0 for success, positive value for failure. */ 7655 /****************************************************************************/ 7656 static int 7657 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 7658 { 7659 struct bce_softc *sc = (struct bce_softc *)arg1; 7660 int error; 7661 u32 result; 7662 u32 val[1]; 7663 u8 *data = (u8 *) val; 7664 7665 result = -1; 7666 error = sysctl_handle_int(oidp, &result, 0, req); 7667 if (error || (req->newptr == NULL)) 7668 return (error); 7669 7670 bce_nvram_read(sc, result, data, 4); 7671 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 7672 7673 return (error); 7674 } 7675 7676 7677 /****************************************************************************/ 7678 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 7679 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7680 /* */ 7681 /* Returns: */ 7682 /* 0 for success, positive value for failure. */ 7683 /****************************************************************************/ 7684 static int 7685 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 7686 { 7687 struct bce_softc *sc = (struct bce_softc *)arg1; 7688 int error; 7689 u32 val, result; 7690 7691 result = -1; 7692 error = sysctl_handle_int(oidp, &result, 0, req); 7693 if (error || (req->newptr == NULL)) 7694 return (error); 7695 7696 /* Make sure the register is accessible. */ 7697 if (result < 0x8000) { 7698 val = REG_RD(sc, result); 7699 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 7700 } else if (result < 0x0280000) { 7701 val = REG_RD_IND(sc, result); 7702 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 7703 } 7704 7705 return (error); 7706 } 7707 7708 7709 /****************************************************************************/ 7710 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 7711 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7712 /* */ 7713 /* Returns: */ 7714 /* 0 for success, positive value for failure. */ 7715 /****************************************************************************/ 7716 static int 7717 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 7718 { 7719 struct bce_softc *sc; 7720 device_t dev; 7721 int error, result; 7722 u16 val; 7723 7724 result = -1; 7725 error = sysctl_handle_int(oidp, &result, 0, req); 7726 if (error || (req->newptr == NULL)) 7727 return (error); 7728 7729 /* Make sure the register is accessible. */ 7730 if (result < 0x20) { 7731 sc = (struct bce_softc *)arg1; 7732 dev = sc->bce_dev; 7733 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 7734 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 7735 } 7736 return (error); 7737 } 7738 7739 7740 /****************************************************************************/ 7741 /* Provides a sysctl interface to allow reading a CID. */ 7742 /* */ 7743 /* Returns: */ 7744 /* 0 for success, positive value for failure. */ 7745 /****************************************************************************/ 7746 static int 7747 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 7748 { 7749 struct bce_softc *sc; 7750 int error; 7751 u16 result; 7752 7753 result = -1; 7754 error = sysctl_handle_int(oidp, &result, 0, req); 7755 if (error || (req->newptr == NULL)) 7756 return (error); 7757 7758 /* Make sure the register is accessible. */ 7759 if (result <= TX_CID) { 7760 sc = (struct bce_softc *)arg1; 7761 bce_dump_ctx(sc, result); 7762 } 7763 7764 return (error); 7765 } 7766 7767 7768 /****************************************************************************/ 7769 /* Provides a sysctl interface to forcing the driver to dump state and */ 7770 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7771 /* */ 7772 /* Returns: */ 7773 /* 0 for success, positive value for failure. */ 7774 /****************************************************************************/ 7775 static int 7776 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 7777 { 7778 int error; 7779 int result; 7780 struct bce_softc *sc; 7781 7782 result = -1; 7783 error = sysctl_handle_int(oidp, &result, 0, req); 7784 7785 if (error || !req->newptr) 7786 return (error); 7787 7788 if (result == 1) { 7789 sc = (struct bce_softc *)arg1; 7790 bce_breakpoint(sc); 7791 } 7792 7793 return error; 7794 } 7795 #endif 7796 7797 7798 /****************************************************************************/ 7799 /* Adds any sysctl parameters for tuning or debugging purposes. */ 7800 /* */ 7801 /* Returns: */ 7802 /* 0 for success, positive value for failure. */ 7803 /****************************************************************************/ 7804 static void 7805 bce_add_sysctls(struct bce_softc *sc) 7806 { 7807 struct sysctl_ctx_list *ctx; 7808 struct sysctl_oid_list *children; 7809 7810 DBENTER(BCE_VERBOSE_MISC); 7811 7812 ctx = device_get_sysctl_ctx(sc->bce_dev); 7813 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 7814 7815 #ifdef BCE_DEBUG 7816 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7817 "rx_low_watermark", 7818 CTLFLAG_RD, &sc->rx_low_watermark, 7819 0, "Lowest level of free rx_bd's"); 7820 7821 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7822 "rx_empty_count", 7823 CTLFLAG_RD, &sc->rx_empty_count, 7824 0, "Number of times the RX chain was empty"); 7825 7826 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7827 "tx_hi_watermark", 7828 CTLFLAG_RD, &sc->tx_hi_watermark, 7829 0, "Highest level of used tx_bd's"); 7830 7831 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7832 "tx_full_count", 7833 CTLFLAG_RD, &sc->tx_full_count, 7834 0, "Number of times the TX chain was full"); 7835 7836 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7837 "l2fhdr_status_errors", 7838 CTLFLAG_RD, &sc->l2fhdr_status_errors, 7839 0, "l2_fhdr status errors"); 7840 7841 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7842 "unexpected_attentions", 7843 CTLFLAG_RD, &sc->unexpected_attentions, 7844 0, "Unexpected attentions"); 7845 7846 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7847 "lost_status_block_updates", 7848 CTLFLAG_RD, &sc->lost_status_block_updates, 7849 0, "Lost status block updates"); 7850 7851 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7852 "debug_mbuf_sim_alloc_failed", 7853 CTLFLAG_RD, &sc->debug_mbuf_sim_alloc_failed, 7854 0, "Simulated mbuf cluster allocation failures"); 7855 7856 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7857 "requested_tso_frames", 7858 CTLFLAG_RD, &sc->requested_tso_frames, 7859 0, "Number of TSO frames received"); 7860 7861 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7862 "rx_interrupts", 7863 CTLFLAG_RD, &sc->rx_interrupts, 7864 0, "Number of RX interrupts"); 7865 7866 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7867 "tx_interrupts", 7868 CTLFLAG_RD, &sc->tx_interrupts, 7869 0, "Number of TX interrupts"); 7870 7871 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7872 "rx_intr_time", 7873 CTLFLAG_RD, &sc->rx_intr_time, 7874 "RX interrupt time"); 7875 7876 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7877 "tx_intr_time", 7878 CTLFLAG_RD, &sc->tx_intr_time, 7879 "TX interrupt time"); 7880 #endif 7881 7882 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7883 "mbuf_alloc_failed", 7884 CTLFLAG_RD, &sc->mbuf_alloc_failed, 7885 0, "mbuf cluster allocation failures"); 7886 7887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7888 "tx_dma_map_failures", 7889 CTLFLAG_RD, &sc->tx_dma_map_failures, 7890 0, "tx dma mapping failures"); 7891 7892 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7893 "stat_IfHcInOctets", 7894 CTLFLAG_RD, &sc->stat_IfHCInOctets, 7895 "Bytes received"); 7896 7897 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7898 "stat_IfHCInBadOctets", 7899 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 7900 "Bad bytes received"); 7901 7902 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7903 "stat_IfHCOutOctets", 7904 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 7905 "Bytes sent"); 7906 7907 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7908 "stat_IfHCOutBadOctets", 7909 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 7910 "Bad bytes sent"); 7911 7912 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7913 "stat_IfHCInUcastPkts", 7914 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 7915 "Unicast packets received"); 7916 7917 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7918 "stat_IfHCInMulticastPkts", 7919 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 7920 "Multicast packets received"); 7921 7922 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7923 "stat_IfHCInBroadcastPkts", 7924 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 7925 "Broadcast packets received"); 7926 7927 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7928 "stat_IfHCOutUcastPkts", 7929 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 7930 "Unicast packets sent"); 7931 7932 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7933 "stat_IfHCOutMulticastPkts", 7934 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 7935 "Multicast packets sent"); 7936 7937 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 7938 "stat_IfHCOutBroadcastPkts", 7939 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 7940 "Broadcast packets sent"); 7941 7942 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7943 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 7944 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 7945 0, "Internal MAC transmit errors"); 7946 7947 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7948 "stat_Dot3StatsCarrierSenseErrors", 7949 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 7950 0, "Carrier sense errors"); 7951 7952 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7953 "stat_Dot3StatsFCSErrors", 7954 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 7955 0, "Frame check sequence errors"); 7956 7957 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7958 "stat_Dot3StatsAlignmentErrors", 7959 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 7960 0, "Alignment errors"); 7961 7962 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7963 "stat_Dot3StatsSingleCollisionFrames", 7964 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 7965 0, "Single Collision Frames"); 7966 7967 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7968 "stat_Dot3StatsMultipleCollisionFrames", 7969 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 7970 0, "Multiple Collision Frames"); 7971 7972 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7973 "stat_Dot3StatsDeferredTransmissions", 7974 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 7975 0, "Deferred Transmissions"); 7976 7977 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7978 "stat_Dot3StatsExcessiveCollisions", 7979 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 7980 0, "Excessive Collisions"); 7981 7982 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7983 "stat_Dot3StatsLateCollisions", 7984 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 7985 0, "Late Collisions"); 7986 7987 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7988 "stat_EtherStatsCollisions", 7989 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 7990 0, "Collisions"); 7991 7992 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7993 "stat_EtherStatsFragments", 7994 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 7995 0, "Fragments"); 7996 7997 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7998 "stat_EtherStatsJabbers", 7999 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8000 0, "Jabbers"); 8001 8002 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8003 "stat_EtherStatsUndersizePkts", 8004 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8005 0, "Undersize packets"); 8006 8007 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8008 "stat_EtherStatsOverrsizePkts", 8009 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 8010 0, "stat_EtherStatsOverrsizePkts"); 8011 8012 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8013 "stat_EtherStatsPktsRx64Octets", 8014 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8015 0, "Bytes received in 64 byte packets"); 8016 8017 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8018 "stat_EtherStatsPktsRx65Octetsto127Octets", 8019 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8020 0, "Bytes received in 65 to 127 byte packets"); 8021 8022 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8023 "stat_EtherStatsPktsRx128Octetsto255Octets", 8024 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8025 0, "Bytes received in 128 to 255 byte packets"); 8026 8027 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8028 "stat_EtherStatsPktsRx256Octetsto511Octets", 8029 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8030 0, "Bytes received in 256 to 511 byte packets"); 8031 8032 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8033 "stat_EtherStatsPktsRx512Octetsto1023Octets", 8034 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8035 0, "Bytes received in 512 to 1023 byte packets"); 8036 8037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8038 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8039 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8040 0, "Bytes received in 1024 t0 1522 byte packets"); 8041 8042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8043 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8044 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8045 0, "Bytes received in 1523 to 9022 byte packets"); 8046 8047 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8048 "stat_EtherStatsPktsTx64Octets", 8049 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8050 0, "Bytes sent in 64 byte packets"); 8051 8052 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8053 "stat_EtherStatsPktsTx65Octetsto127Octets", 8054 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8055 0, "Bytes sent in 65 to 127 byte packets"); 8056 8057 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8058 "stat_EtherStatsPktsTx128Octetsto255Octets", 8059 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8060 0, "Bytes sent in 128 to 255 byte packets"); 8061 8062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8063 "stat_EtherStatsPktsTx256Octetsto511Octets", 8064 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8065 0, "Bytes sent in 256 to 511 byte packets"); 8066 8067 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8068 "stat_EtherStatsPktsTx512Octetsto1023Octets", 8069 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8070 0, "Bytes sent in 512 to 1023 byte packets"); 8071 8072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8073 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8074 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8075 0, "Bytes sent in 1024 to 1522 byte packets"); 8076 8077 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8078 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8079 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8080 0, "Bytes sent in 1523 to 9022 byte packets"); 8081 8082 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8083 "stat_XonPauseFramesReceived", 8084 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8085 0, "XON pause frames receved"); 8086 8087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8088 "stat_XoffPauseFramesReceived", 8089 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8090 0, "XOFF pause frames received"); 8091 8092 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8093 "stat_OutXonSent", 8094 CTLFLAG_RD, &sc->stat_OutXonSent, 8095 0, "XON pause frames sent"); 8096 8097 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8098 "stat_OutXoffSent", 8099 CTLFLAG_RD, &sc->stat_OutXoffSent, 8100 0, "XOFF pause frames sent"); 8101 8102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8103 "stat_FlowControlDone", 8104 CTLFLAG_RD, &sc->stat_FlowControlDone, 8105 0, "Flow control done"); 8106 8107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8108 "stat_MacControlFramesReceived", 8109 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8110 0, "MAC control frames received"); 8111 8112 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8113 "stat_XoffStateEntered", 8114 CTLFLAG_RD, &sc->stat_XoffStateEntered, 8115 0, "XOFF state entered"); 8116 8117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8118 "stat_IfInFramesL2FilterDiscards", 8119 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8120 0, "Received L2 packets discarded"); 8121 8122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8123 "stat_IfInRuleCheckerDiscards", 8124 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8125 0, "Received packets discarded by rule"); 8126 8127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8128 "stat_IfInFTQDiscards", 8129 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8130 0, "Received packet FTQ discards"); 8131 8132 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8133 "stat_IfInMBUFDiscards", 8134 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8135 0, "Received packets discarded due to lack of controller buffer memory"); 8136 8137 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8138 "stat_IfInRuleCheckerP4Hit", 8139 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8140 0, "Received packets rule checker hits"); 8141 8142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8143 "stat_CatchupInRuleCheckerDiscards", 8144 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8145 0, "Received packets discarded in Catchup path"); 8146 8147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8148 "stat_CatchupInFTQDiscards", 8149 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8150 0, "Received packets discarded in FTQ in Catchup path"); 8151 8152 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8153 "stat_CatchupInMBUFDiscards", 8154 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8155 0, "Received packets discarded in controller buffer memory in Catchup path"); 8156 8157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8158 "stat_CatchupInRuleCheckerP4Hit", 8159 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8160 0, "Received packets rule checker hits in Catchup path"); 8161 8162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8163 "com_no_buffers", 8164 CTLFLAG_RD, &sc->com_no_buffers, 8165 0, "Valid packets received but no RX buffers available"); 8166 8167 #ifdef BCE_DEBUG 8168 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8169 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8170 (void *)sc, 0, 8171 bce_sysctl_driver_state, "I", "Drive state information"); 8172 8173 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8174 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8175 (void *)sc, 0, 8176 bce_sysctl_hw_state, "I", "Hardware state information"); 8177 8178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8179 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8180 (void *)sc, 0, 8181 bce_sysctl_bc_state, "I", "Bootcode state information"); 8182 8183 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8184 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 8185 (void *)sc, 0, 8186 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 8187 8188 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8189 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8190 (void *)sc, 0, 8191 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8192 8193 #ifdef BCE_USE_SPLIT_HEADER 8194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8195 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8196 (void *)sc, 0, 8197 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8198 #endif 8199 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8200 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8201 (void *)sc, 0, 8202 bce_sysctl_dump_ctx, "I", "Dump context memory"); 8203 8204 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8205 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8206 (void *)sc, 0, 8207 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8208 8209 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8210 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8211 (void *)sc, 0, 8212 bce_sysctl_reg_read, "I", "Register read"); 8213 8214 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8215 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8216 (void *)sc, 0, 8217 bce_sysctl_nvram_read, "I", "NVRAM read"); 8218 8219 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8220 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8221 (void *)sc, 0, 8222 bce_sysctl_phy_read, "I", "PHY register read"); 8223 8224 #endif 8225 8226 DBEXIT(BCE_VERBOSE_MISC); 8227 } 8228 8229 8230 /****************************************************************************/ 8231 /* BCE Debug Routines */ 8232 /****************************************************************************/ 8233 #ifdef BCE_DEBUG 8234 8235 /****************************************************************************/ 8236 /* Freezes the controller to allow for a cohesive state dump. */ 8237 /* */ 8238 /* Returns: */ 8239 /* Nothing. */ 8240 /****************************************************************************/ 8241 static void 8242 bce_freeze_controller(struct bce_softc *sc) 8243 { 8244 u32 val; 8245 val = REG_RD(sc, BCE_MISC_COMMAND); 8246 val |= BCE_MISC_COMMAND_DISABLE_ALL; 8247 REG_WR(sc, BCE_MISC_COMMAND, val); 8248 } 8249 8250 8251 /****************************************************************************/ 8252 /* Unfreezes the controller after a freeze operation. This may not always */ 8253 /* work and the controller will require a reset! */ 8254 /* */ 8255 /* Returns: */ 8256 /* Nothing. */ 8257 /****************************************************************************/ 8258 static void 8259 bce_unfreeze_controller(struct bce_softc *sc) 8260 { 8261 u32 val; 8262 val = REG_RD(sc, BCE_MISC_COMMAND); 8263 val |= BCE_MISC_COMMAND_ENABLE_ALL; 8264 REG_WR(sc, BCE_MISC_COMMAND, val); 8265 } 8266 8267 /****************************************************************************/ 8268 /* Prints out information about an mbuf. */ 8269 /* */ 8270 /* Returns: */ 8271 /* Nothing. */ 8272 /****************************************************************************/ 8273 static __attribute__ ((noinline)) void 8274 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 8275 { 8276 struct mbuf *mp = m; 8277 8278 if (m == NULL) { 8279 BCE_PRINTF("mbuf: null pointer\n"); 8280 return; 8281 } 8282 8283 while (mp) { 8284 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n", 8285 mp, mp->m_len, mp->m_flags, 8286 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", 8287 mp->m_data); 8288 8289 if (mp->m_flags & M_PKTHDR) { 8290 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n", 8291 mp->m_pkthdr.len, mp->m_flags, 8292 "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG" 8293 "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE", 8294 mp->m_pkthdr.csum_flags, 8295 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 8296 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 8297 "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR"); 8298 } 8299 8300 if (mp->m_flags & M_EXT) { 8301 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 8302 mp->m_ext.ext_buf, mp->m_ext.ext_size); 8303 switch (mp->m_ext.ext_type) { 8304 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 8305 case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 8306 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 8307 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 8308 case EXT_PACKET: printf("EXT_PACKET\n"); break; 8309 case EXT_MBUF: printf("EXT_MBUF\n"); break; 8310 case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 8311 case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 8312 case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 8313 case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 8314 default: printf("UNKNOWN\n"); 8315 } 8316 } 8317 8318 mp = mp->m_next; 8319 } 8320 } 8321 8322 8323 /****************************************************************************/ 8324 /* Prints out the mbufs in the TX mbuf chain. */ 8325 /* */ 8326 /* Returns: */ 8327 /* Nothing. */ 8328 /****************************************************************************/ 8329 static __attribute__ ((noinline)) void 8330 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8331 { 8332 struct mbuf *m; 8333 8334 BCE_PRINTF( 8335 "----------------------------" 8336 " tx mbuf data " 8337 "----------------------------\n"); 8338 8339 for (int i = 0; i < count; i++) { 8340 m = sc->tx_mbuf_ptr[chain_prod]; 8341 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 8342 bce_dump_mbuf(sc, m); 8343 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 8344 } 8345 8346 BCE_PRINTF( 8347 "----------------------------" 8348 "----------------" 8349 "----------------------------\n"); 8350 } 8351 8352 8353 /****************************************************************************/ 8354 /* Prints out the mbufs in the RX mbuf chain. */ 8355 /* */ 8356 /* Returns: */ 8357 /* Nothing. */ 8358 /****************************************************************************/ 8359 static __attribute__ ((noinline)) void 8360 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8361 { 8362 struct mbuf *m; 8363 8364 BCE_PRINTF( 8365 "----------------------------" 8366 " rx mbuf data " 8367 "----------------------------\n"); 8368 8369 for (int i = 0; i < count; i++) { 8370 m = sc->rx_mbuf_ptr[chain_prod]; 8371 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 8372 bce_dump_mbuf(sc, m); 8373 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 8374 } 8375 8376 8377 BCE_PRINTF( 8378 "----------------------------" 8379 "----------------" 8380 "----------------------------\n"); 8381 } 8382 8383 8384 #ifdef BCE_USE_SPLIT_HEADER 8385 /****************************************************************************/ 8386 /* Prints out the mbufs in the mbuf page chain. */ 8387 /* */ 8388 /* Returns: */ 8389 /* Nothing. */ 8390 /****************************************************************************/ 8391 static __attribute__ ((noinline)) void 8392 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8393 { 8394 struct mbuf *m; 8395 8396 BCE_PRINTF( 8397 "----------------------------" 8398 " pg mbuf data " 8399 "----------------------------\n"); 8400 8401 for (int i = 0; i < count; i++) { 8402 m = sc->pg_mbuf_ptr[chain_prod]; 8403 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 8404 bce_dump_mbuf(sc, m); 8405 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 8406 } 8407 8408 8409 BCE_PRINTF( 8410 "----------------------------" 8411 "----------------" 8412 "----------------------------\n"); 8413 } 8414 #endif 8415 8416 8417 /****************************************************************************/ 8418 /* Prints out a tx_bd structure. */ 8419 /* */ 8420 /* Returns: */ 8421 /* Nothing. */ 8422 /****************************************************************************/ 8423 static __attribute__ ((noinline)) void 8424 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 8425 { 8426 if (idx > MAX_TX_BD) 8427 /* Index out of range. */ 8428 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 8429 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 8430 /* TX Chain page pointer. */ 8431 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8432 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 8433 else { 8434 /* Normal tx_bd entry. */ 8435 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8436 "vlan tag= 0x%04X, flags = 0x%04X (", idx, 8437 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 8438 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 8439 txbd->tx_bd_flags); 8440 8441 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 8442 printf(" CONN_FAULT"); 8443 8444 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 8445 printf(" TCP_UDP_CKSUM"); 8446 8447 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 8448 printf(" IP_CKSUM"); 8449 8450 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 8451 printf(" VLAN"); 8452 8453 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 8454 printf(" COAL_NOW"); 8455 8456 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 8457 printf(" DONT_GEN_CRC"); 8458 8459 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 8460 printf(" START"); 8461 8462 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 8463 printf(" END"); 8464 8465 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 8466 printf(" LSO"); 8467 8468 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 8469 printf(" OPTION_WORD"); 8470 8471 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 8472 printf(" FLAGS"); 8473 8474 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 8475 printf(" SNAP"); 8476 8477 printf(" )\n"); 8478 } 8479 8480 } 8481 8482 8483 /****************************************************************************/ 8484 /* Prints out a rx_bd structure. */ 8485 /* */ 8486 /* Returns: */ 8487 /* Nothing. */ 8488 /****************************************************************************/ 8489 static __attribute__ ((noinline)) void 8490 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 8491 { 8492 if (idx > MAX_RX_BD) 8493 /* Index out of range. */ 8494 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 8495 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 8496 /* RX Chain page pointer. */ 8497 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8498 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 8499 else 8500 /* Normal rx_bd entry. */ 8501 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8502 "flags = 0x%08X\n", idx, 8503 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 8504 rxbd->rx_bd_len, rxbd->rx_bd_flags); 8505 } 8506 8507 8508 #ifdef BCE_USE_SPLIT_HEADER 8509 /****************************************************************************/ 8510 /* Prints out a rx_bd structure in the page chain. */ 8511 /* */ 8512 /* Returns: */ 8513 /* Nothing. */ 8514 /****************************************************************************/ 8515 static __attribute__ ((noinline)) void 8516 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 8517 { 8518 if (idx > MAX_PG_BD) 8519 /* Index out of range. */ 8520 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 8521 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 8522 /* Page Chain page pointer. */ 8523 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8524 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 8525 else 8526 /* Normal rx_bd entry. */ 8527 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8528 "flags = 0x%08X\n", idx, 8529 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 8530 pgbd->rx_bd_len, pgbd->rx_bd_flags); 8531 } 8532 #endif 8533 8534 8535 /****************************************************************************/ 8536 /* Prints out a l2_fhdr structure. */ 8537 /* */ 8538 /* Returns: */ 8539 /* Nothing. */ 8540 /****************************************************************************/ 8541 static __attribute__ ((noinline)) void 8542 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 8543 { 8544 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 8545 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 8546 "tcp_udp_xsum = 0x%04X\n", idx, 8547 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 8548 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 8549 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 8550 } 8551 8552 8553 /****************************************************************************/ 8554 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 8555 /* */ 8556 /* Returns: */ 8557 /* Nothing. */ 8558 /****************************************************************************/ 8559 static __attribute__ ((noinline)) void 8560 bce_dump_ctx(struct bce_softc *sc, u16 cid) 8561 { 8562 if (cid <= TX_CID) { 8563 BCE_PRINTF( 8564 "----------------------------" 8565 " CTX Data " 8566 "----------------------------\n"); 8567 8568 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 8569 8570 if (cid == RX_CID) { 8571 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BDIDX) host rx producer index\n", 8572 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BDIDX)); 8573 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BSEQ) host byte sequence\n", 8574 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BSEQ)); 8575 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BSEQ) h/w byte sequence\n", 8576 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BSEQ)); 8577 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_HI) h/w buffer descriptor address\n", 8578 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_HI)); 8579 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_LO) h/w buffer descriptor address\n", 8580 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_LO)); 8581 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDIDX) h/w rx consumer index\n", 8582 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDIDX)); 8583 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_PG_BDIDX) host page producer index\n", 8584 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_PG_BDIDX)); 8585 BCE_PRINTF(" 0x%08X - (L2CTX_PG_BUF_SIZE) host rx_bd/page buffer size\n", 8586 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_PG_BUF_SIZE)); 8587 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_HI) h/w page chain address\n", 8588 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_HI)); 8589 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_LO) h/w page chain address\n", 8590 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_LO)); 8591 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDIDX) h/w page consumer index\n", 8592 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDIDX)); 8593 } else if (cid == TX_CID) { 8594 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 8595 BCE_PRINTF(" 0x%08X - (L2CTX_TYPE_XI) ctx type\n", 8596 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TYPE_XI)); 8597 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TYPE_XI) ctx cmd\n", 8598 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_CMD_TYPE_XI)); 8599 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BDHADDR_HI_XI) h/w buffer descriptor address\n", 8600 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_HI_XI)); 8601 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BHADDR_LO_XI) h/w buffer descriptor address\n", 8602 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_LO_XI)); 8603 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) host producer index\n", 8604 CTX_RD(sc, GET_CID_ADDR(cid), 0x240)); 8605 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) host byte sequence\n", 8606 CTX_RD(sc, GET_CID_ADDR(cid), 0x248)); 8607 } else { 8608 BCE_PRINTF(" 0x%08X - (L2CTX_TYPE_TYPE_L2) ctx type\n", 8609 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TYPE_TYPE_L2)); 8610 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TYPE_TYPE_L2) ctx cmd\n", 8611 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_CMD_TYPE_TYPE_L2)); 8612 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BDHADDR_HI) h/w buffer descriptor address\n", 8613 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_HI)); 8614 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BHADDR_LO) h/w buffer descriptor address\n", 8615 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_LO)); 8616 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host producer index\n", 8617 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_HOST_BIDX)); 8618 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte sequence\n", 8619 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_HOST_BSEQ)); 8620 } 8621 } else 8622 BCE_PRINTF(" Unknown CID\n"); 8623 8624 BCE_PRINTF( 8625 "----------------------------" 8626 " Raw CTX " 8627 "----------------------------\n"); 8628 8629 for (int i = 0x0; i < 0x300; i += 0x10) { 8630 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 8631 i, 8632 CTX_RD(sc, GET_CID_ADDR(cid), i), 8633 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 8634 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 8635 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 8636 } 8637 8638 8639 BCE_PRINTF( 8640 "----------------------------" 8641 "----------------" 8642 "----------------------------\n"); 8643 } 8644 } 8645 8646 8647 /****************************************************************************/ 8648 /* Prints out the FTQ data. */ 8649 /* */ 8650 /* Returns: */ 8651 /* Nothing. */ 8652 /****************************************************************************/ 8653 static __attribute__ ((noinline)) void 8654 bce_dump_ftqs(struct bce_softc *sc) 8655 { 8656 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 8657 8658 BCE_PRINTF( 8659 "----------------------------" 8660 " FTQ Data " 8661 "----------------------------\n"); 8662 8663 BCE_PRINTF(" FTQ Command Control Depth_Now Max_Depth Valid_Cnt \n"); 8664 BCE_PRINTF(" ------- ---------- ---------- ---------- ---------- ----------\n"); 8665 8666 /* Setup the generic statistic counters for the FTQ valid count. */ 8667 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 8668 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 8669 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 8670 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 8671 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 8672 8673 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 8674 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 8675 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 8676 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 8677 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 8678 8679 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 8680 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 8681 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 8682 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 8683 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 8684 8685 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 8686 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 8687 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 8688 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 8689 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 8690 8691 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 8692 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 8693 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 8694 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 8695 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 8696 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8697 cmd, ctl, cur_depth, max_depth, valid_cnt); 8698 8699 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 8700 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 8701 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 8702 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 8703 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 8704 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8705 cmd, ctl, cur_depth, max_depth, valid_cnt); 8706 8707 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 8708 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 8709 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 8710 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 8711 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 8712 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8713 cmd, ctl, cur_depth, max_depth, valid_cnt); 8714 8715 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 8716 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 8717 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 8718 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 8719 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 8720 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8721 cmd, ctl, cur_depth, max_depth, valid_cnt); 8722 8723 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 8724 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 8725 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 8726 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 8727 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 8728 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8729 cmd, ctl, cur_depth, max_depth, valid_cnt); 8730 8731 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 8732 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 8733 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 8734 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 8735 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 8736 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8737 cmd, ctl, cur_depth, max_depth, valid_cnt); 8738 8739 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 8740 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 8741 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 8742 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 8743 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 8744 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8745 cmd, ctl, cur_depth, max_depth, valid_cnt); 8746 8747 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 8748 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 8749 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 8750 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 8751 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 8752 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8753 cmd, ctl, cur_depth, max_depth, valid_cnt); 8754 8755 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 8756 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 8757 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 8758 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 8759 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 8760 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8761 cmd, ctl, cur_depth, max_depth, valid_cnt); 8762 8763 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 8764 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 8765 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 8766 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 8767 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 8768 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8769 cmd, ctl, cur_depth, max_depth, valid_cnt); 8770 8771 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 8772 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 8773 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 8774 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 8775 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 8776 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8777 cmd, ctl, cur_depth, max_depth, valid_cnt); 8778 8779 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 8780 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 8781 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 8782 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 8783 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 8784 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8785 cmd, ctl, cur_depth, max_depth, valid_cnt); 8786 8787 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 8788 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 8789 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 8790 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 8791 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 8792 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8793 cmd, ctl, cur_depth, max_depth, valid_cnt); 8794 8795 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 8796 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 8797 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 8798 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 8799 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 8800 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8801 cmd, ctl, cur_depth, max_depth, valid_cnt); 8802 8803 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 8804 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 8805 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 8806 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 8807 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 8808 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8809 cmd, ctl, cur_depth, max_depth, valid_cnt); 8810 8811 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 8812 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 8813 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 8814 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 8815 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 8816 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8817 cmd, ctl, cur_depth, max_depth, valid_cnt); 8818 8819 /* Setup the generic statistic counters for the FTQ valid count. */ 8820 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 8821 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 8822 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 8823 8824 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 8825 val = val | (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 24); 8826 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 8827 8828 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 8829 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 8830 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 8831 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 8832 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 8833 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8834 cmd, ctl, cur_depth, max_depth, valid_cnt); 8835 8836 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 8837 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 8838 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 8839 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 8840 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 8841 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8842 cmd, ctl, cur_depth, max_depth, valid_cnt); 8843 8844 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 8845 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 8846 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 8847 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 8848 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 8849 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8850 cmd, ctl, cur_depth, max_depth, valid_cnt); 8851 8852 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 8853 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 8854 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 8855 cur_depth = (ctl & 0xFFC00000) >> 22; 8856 max_depth = (ctl & 0x003FF000) >> 12; 8857 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 8858 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8859 cmd, ctl, cur_depth, max_depth, valid_cnt); 8860 } 8861 8862 BCE_PRINTF( 8863 "----------------------------" 8864 "----------------" 8865 "----------------------------\n"); 8866 } 8867 8868 8869 /****************************************************************************/ 8870 /* Prints out the TX chain. */ 8871 /* */ 8872 /* Returns: */ 8873 /* Nothing. */ 8874 /****************************************************************************/ 8875 static __attribute__ ((noinline)) void 8876 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 8877 { 8878 struct tx_bd *txbd; 8879 8880 /* First some info about the tx_bd chain structure. */ 8881 BCE_PRINTF( 8882 "----------------------------" 8883 " tx_bd chain " 8884 "----------------------------\n"); 8885 8886 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 8887 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 8888 8889 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 8890 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 8891 8892 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 8893 8894 BCE_PRINTF( 8895 "----------------------------" 8896 " tx_bd data " 8897 "----------------------------\n"); 8898 8899 /* Now print out the tx_bd's themselves. */ 8900 for (int i = 0; i < count; i++) { 8901 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 8902 bce_dump_txbd(sc, tx_prod, txbd); 8903 tx_prod = NEXT_TX_BD(tx_prod); 8904 } 8905 8906 BCE_PRINTF( 8907 "----------------------------" 8908 "----------------" 8909 "----------------------------\n"); 8910 } 8911 8912 8913 /****************************************************************************/ 8914 /* Prints out the RX chain. */ 8915 /* */ 8916 /* Returns: */ 8917 /* Nothing. */ 8918 /****************************************************************************/ 8919 static __attribute__ ((noinline)) void 8920 bce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count) 8921 { 8922 struct rx_bd *rxbd; 8923 8924 /* First some info about the rx_bd chain structure. */ 8925 BCE_PRINTF( 8926 "----------------------------" 8927 " rx_bd chain " 8928 "----------------------------\n"); 8929 8930 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 8931 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 8932 8933 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 8934 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 8935 8936 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 8937 8938 BCE_PRINTF( 8939 "----------------------------" 8940 " rx_bd data " 8941 "----------------------------\n"); 8942 8943 /* Now print out the rx_bd's themselves. */ 8944 for (int i = 0; i < count; i++) { 8945 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 8946 bce_dump_rxbd(sc, rx_prod, rxbd); 8947 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 8948 } 8949 8950 BCE_PRINTF( 8951 "----------------------------" 8952 "----------------" 8953 "----------------------------\n"); 8954 } 8955 8956 8957 #ifdef BCE_USE_SPLIT_HEADER 8958 /****************************************************************************/ 8959 /* Prints out the page chain. */ 8960 /* */ 8961 /* Returns: */ 8962 /* Nothing. */ 8963 /****************************************************************************/ 8964 static __attribute__ ((noinline)) void 8965 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 8966 { 8967 struct rx_bd *pgbd; 8968 8969 /* First some info about the page chain structure. */ 8970 BCE_PRINTF( 8971 "----------------------------" 8972 " page chain " 8973 "----------------------------\n"); 8974 8975 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 8976 (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 8977 8978 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 8979 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 8980 8981 BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 8982 (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 8983 8984 BCE_PRINTF( 8985 "----------------------------" 8986 " page data " 8987 "----------------------------\n"); 8988 8989 /* Now print out the rx_bd's themselves. */ 8990 for (int i = 0; i < count; i++) { 8991 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 8992 bce_dump_pgbd(sc, pg_prod, pgbd); 8993 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 8994 } 8995 8996 BCE_PRINTF( 8997 "----------------------------" 8998 "----------------" 8999 "----------------------------\n"); 9000 } 9001 #endif 9002 9003 9004 /****************************************************************************/ 9005 /* Prints out the status block from host memory. */ 9006 /* */ 9007 /* Returns: */ 9008 /* Nothing. */ 9009 /****************************************************************************/ 9010 static __attribute__ ((noinline)) void 9011 bce_dump_status_block(struct bce_softc *sc) 9012 { 9013 struct status_block *sblk; 9014 9015 sblk = sc->status_block; 9016 9017 BCE_PRINTF( 9018 "----------------------------" 9019 " Status Block " 9020 "----------------------------\n"); 9021 9022 BCE_PRINTF(" 0x%08X - attn_bits\n", 9023 sblk->status_attn_bits); 9024 9025 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9026 sblk->status_attn_bits_ack); 9027 9028 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 9029 sblk->status_rx_quick_consumer_index0, 9030 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 9031 9032 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 9033 sblk->status_tx_quick_consumer_index0, 9034 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 9035 9036 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9037 9038 /* Theses indices are not used for normal L2 drivers. */ 9039 if (sblk->status_rx_quick_consumer_index1) 9040 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 9041 sblk->status_rx_quick_consumer_index1, 9042 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 9043 9044 if (sblk->status_tx_quick_consumer_index1) 9045 BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 9046 sblk->status_tx_quick_consumer_index1, 9047 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 9048 9049 if (sblk->status_rx_quick_consumer_index2) 9050 BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 9051 sblk->status_rx_quick_consumer_index2, 9052 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 9053 9054 if (sblk->status_tx_quick_consumer_index2) 9055 BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 9056 sblk->status_tx_quick_consumer_index2, 9057 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 9058 9059 if (sblk->status_rx_quick_consumer_index3) 9060 BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 9061 sblk->status_rx_quick_consumer_index3, 9062 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 9063 9064 if (sblk->status_tx_quick_consumer_index3) 9065 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 9066 sblk->status_tx_quick_consumer_index3, 9067 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 9068 9069 if (sblk->status_rx_quick_consumer_index4 || 9070 sblk->status_rx_quick_consumer_index5) 9071 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 9072 sblk->status_rx_quick_consumer_index4, 9073 sblk->status_rx_quick_consumer_index5); 9074 9075 if (sblk->status_rx_quick_consumer_index6 || 9076 sblk->status_rx_quick_consumer_index7) 9077 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 9078 sblk->status_rx_quick_consumer_index6, 9079 sblk->status_rx_quick_consumer_index7); 9080 9081 if (sblk->status_rx_quick_consumer_index8 || 9082 sblk->status_rx_quick_consumer_index9) 9083 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 9084 sblk->status_rx_quick_consumer_index8, 9085 sblk->status_rx_quick_consumer_index9); 9086 9087 if (sblk->status_rx_quick_consumer_index10 || 9088 sblk->status_rx_quick_consumer_index11) 9089 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 9090 sblk->status_rx_quick_consumer_index10, 9091 sblk->status_rx_quick_consumer_index11); 9092 9093 if (sblk->status_rx_quick_consumer_index12 || 9094 sblk->status_rx_quick_consumer_index13) 9095 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 9096 sblk->status_rx_quick_consumer_index12, 9097 sblk->status_rx_quick_consumer_index13); 9098 9099 if (sblk->status_rx_quick_consumer_index14 || 9100 sblk->status_rx_quick_consumer_index15) 9101 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 9102 sblk->status_rx_quick_consumer_index14, 9103 sblk->status_rx_quick_consumer_index15); 9104 9105 if (sblk->status_completion_producer_index || 9106 sblk->status_cmd_consumer_index) 9107 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 9108 sblk->status_completion_producer_index, 9109 sblk->status_cmd_consumer_index); 9110 9111 BCE_PRINTF( 9112 "----------------------------" 9113 "----------------" 9114 "----------------------------\n"); 9115 } 9116 9117 9118 /****************************************************************************/ 9119 /* Prints out the statistics block from host memory. */ 9120 /* */ 9121 /* Returns: */ 9122 /* Nothing. */ 9123 /****************************************************************************/ 9124 static __attribute__ ((noinline)) void 9125 bce_dump_stats_block(struct bce_softc *sc) 9126 { 9127 struct statistics_block *sblk; 9128 9129 sblk = sc->stats_block; 9130 9131 BCE_PRINTF( 9132 "---------------" 9133 " Stats Block (All Stats Not Shown Are 0) " 9134 "---------------\n"); 9135 9136 if (sblk->stat_IfHCInOctets_hi 9137 || sblk->stat_IfHCInOctets_lo) 9138 BCE_PRINTF("0x%08X:%08X : " 9139 "IfHcInOctets\n", 9140 sblk->stat_IfHCInOctets_hi, 9141 sblk->stat_IfHCInOctets_lo); 9142 9143 if (sblk->stat_IfHCInBadOctets_hi 9144 || sblk->stat_IfHCInBadOctets_lo) 9145 BCE_PRINTF("0x%08X:%08X : " 9146 "IfHcInBadOctets\n", 9147 sblk->stat_IfHCInBadOctets_hi, 9148 sblk->stat_IfHCInBadOctets_lo); 9149 9150 if (sblk->stat_IfHCOutOctets_hi 9151 || sblk->stat_IfHCOutOctets_lo) 9152 BCE_PRINTF("0x%08X:%08X : " 9153 "IfHcOutOctets\n", 9154 sblk->stat_IfHCOutOctets_hi, 9155 sblk->stat_IfHCOutOctets_lo); 9156 9157 if (sblk->stat_IfHCOutBadOctets_hi 9158 || sblk->stat_IfHCOutBadOctets_lo) 9159 BCE_PRINTF("0x%08X:%08X : " 9160 "IfHcOutBadOctets\n", 9161 sblk->stat_IfHCOutBadOctets_hi, 9162 sblk->stat_IfHCOutBadOctets_lo); 9163 9164 if (sblk->stat_IfHCInUcastPkts_hi 9165 || sblk->stat_IfHCInUcastPkts_lo) 9166 BCE_PRINTF("0x%08X:%08X : " 9167 "IfHcInUcastPkts\n", 9168 sblk->stat_IfHCInUcastPkts_hi, 9169 sblk->stat_IfHCInUcastPkts_lo); 9170 9171 if (sblk->stat_IfHCInBroadcastPkts_hi 9172 || sblk->stat_IfHCInBroadcastPkts_lo) 9173 BCE_PRINTF("0x%08X:%08X : " 9174 "IfHcInBroadcastPkts\n", 9175 sblk->stat_IfHCInBroadcastPkts_hi, 9176 sblk->stat_IfHCInBroadcastPkts_lo); 9177 9178 if (sblk->stat_IfHCInMulticastPkts_hi 9179 || sblk->stat_IfHCInMulticastPkts_lo) 9180 BCE_PRINTF("0x%08X:%08X : " 9181 "IfHcInMulticastPkts\n", 9182 sblk->stat_IfHCInMulticastPkts_hi, 9183 sblk->stat_IfHCInMulticastPkts_lo); 9184 9185 if (sblk->stat_IfHCOutUcastPkts_hi 9186 || sblk->stat_IfHCOutUcastPkts_lo) 9187 BCE_PRINTF("0x%08X:%08X : " 9188 "IfHcOutUcastPkts\n", 9189 sblk->stat_IfHCOutUcastPkts_hi, 9190 sblk->stat_IfHCOutUcastPkts_lo); 9191 9192 if (sblk->stat_IfHCOutBroadcastPkts_hi 9193 || sblk->stat_IfHCOutBroadcastPkts_lo) 9194 BCE_PRINTF("0x%08X:%08X : " 9195 "IfHcOutBroadcastPkts\n", 9196 sblk->stat_IfHCOutBroadcastPkts_hi, 9197 sblk->stat_IfHCOutBroadcastPkts_lo); 9198 9199 if (sblk->stat_IfHCOutMulticastPkts_hi 9200 || sblk->stat_IfHCOutMulticastPkts_lo) 9201 BCE_PRINTF("0x%08X:%08X : " 9202 "IfHcOutMulticastPkts\n", 9203 sblk->stat_IfHCOutMulticastPkts_hi, 9204 sblk->stat_IfHCOutMulticastPkts_lo); 9205 9206 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 9207 BCE_PRINTF(" 0x%08X : " 9208 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 9209 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 9210 9211 if (sblk->stat_Dot3StatsCarrierSenseErrors) 9212 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 9213 sblk->stat_Dot3StatsCarrierSenseErrors); 9214 9215 if (sblk->stat_Dot3StatsFCSErrors) 9216 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 9217 sblk->stat_Dot3StatsFCSErrors); 9218 9219 if (sblk->stat_Dot3StatsAlignmentErrors) 9220 BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 9221 sblk->stat_Dot3StatsAlignmentErrors); 9222 9223 if (sblk->stat_Dot3StatsSingleCollisionFrames) 9224 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 9225 sblk->stat_Dot3StatsSingleCollisionFrames); 9226 9227 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 9228 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 9229 sblk->stat_Dot3StatsMultipleCollisionFrames); 9230 9231 if (sblk->stat_Dot3StatsDeferredTransmissions) 9232 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 9233 sblk->stat_Dot3StatsDeferredTransmissions); 9234 9235 if (sblk->stat_Dot3StatsExcessiveCollisions) 9236 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 9237 sblk->stat_Dot3StatsExcessiveCollisions); 9238 9239 if (sblk->stat_Dot3StatsLateCollisions) 9240 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 9241 sblk->stat_Dot3StatsLateCollisions); 9242 9243 if (sblk->stat_EtherStatsCollisions) 9244 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 9245 sblk->stat_EtherStatsCollisions); 9246 9247 if (sblk->stat_EtherStatsFragments) 9248 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 9249 sblk->stat_EtherStatsFragments); 9250 9251 if (sblk->stat_EtherStatsJabbers) 9252 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 9253 sblk->stat_EtherStatsJabbers); 9254 9255 if (sblk->stat_EtherStatsUndersizePkts) 9256 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 9257 sblk->stat_EtherStatsUndersizePkts); 9258 9259 if (sblk->stat_EtherStatsOverrsizePkts) 9260 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 9261 sblk->stat_EtherStatsOverrsizePkts); 9262 9263 if (sblk->stat_EtherStatsPktsRx64Octets) 9264 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 9265 sblk->stat_EtherStatsPktsRx64Octets); 9266 9267 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 9268 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 9269 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 9270 9271 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 9272 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 9273 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 9274 9275 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 9276 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 9277 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 9278 9279 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 9280 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 9281 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 9282 9283 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 9284 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 9285 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 9286 9287 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 9288 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 9289 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 9290 9291 if (sblk->stat_EtherStatsPktsTx64Octets) 9292 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 9293 sblk->stat_EtherStatsPktsTx64Octets); 9294 9295 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 9296 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 9297 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 9298 9299 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 9300 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 9301 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 9302 9303 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 9304 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 9305 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 9306 9307 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 9308 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 9309 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 9310 9311 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 9312 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 9313 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 9314 9315 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 9316 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 9317 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 9318 9319 if (sblk->stat_XonPauseFramesReceived) 9320 BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 9321 sblk->stat_XonPauseFramesReceived); 9322 9323 if (sblk->stat_XoffPauseFramesReceived) 9324 BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 9325 sblk->stat_XoffPauseFramesReceived); 9326 9327 if (sblk->stat_OutXonSent) 9328 BCE_PRINTF(" 0x%08X : OutXonSent\n", 9329 sblk->stat_OutXonSent); 9330 9331 if (sblk->stat_OutXoffSent) 9332 BCE_PRINTF(" 0x%08X : OutXoffSent\n", 9333 sblk->stat_OutXoffSent); 9334 9335 if (sblk->stat_FlowControlDone) 9336 BCE_PRINTF(" 0x%08X : FlowControlDone\n", 9337 sblk->stat_FlowControlDone); 9338 9339 if (sblk->stat_MacControlFramesReceived) 9340 BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 9341 sblk->stat_MacControlFramesReceived); 9342 9343 if (sblk->stat_XoffStateEntered) 9344 BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 9345 sblk->stat_XoffStateEntered); 9346 9347 if (sblk->stat_IfInFramesL2FilterDiscards) 9348 BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 9349 sblk->stat_IfInFramesL2FilterDiscards); 9350 9351 if (sblk->stat_IfInRuleCheckerDiscards) 9352 BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 9353 sblk->stat_IfInRuleCheckerDiscards); 9354 9355 if (sblk->stat_IfInFTQDiscards) 9356 BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 9357 sblk->stat_IfInFTQDiscards); 9358 9359 if (sblk->stat_IfInMBUFDiscards) 9360 BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 9361 sblk->stat_IfInMBUFDiscards); 9362 9363 if (sblk->stat_IfInRuleCheckerP4Hit) 9364 BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 9365 sblk->stat_IfInRuleCheckerP4Hit); 9366 9367 if (sblk->stat_CatchupInRuleCheckerDiscards) 9368 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 9369 sblk->stat_CatchupInRuleCheckerDiscards); 9370 9371 if (sblk->stat_CatchupInFTQDiscards) 9372 BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 9373 sblk->stat_CatchupInFTQDiscards); 9374 9375 if (sblk->stat_CatchupInMBUFDiscards) 9376 BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 9377 sblk->stat_CatchupInMBUFDiscards); 9378 9379 if (sblk->stat_CatchupInRuleCheckerP4Hit) 9380 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 9381 sblk->stat_CatchupInRuleCheckerP4Hit); 9382 9383 BCE_PRINTF( 9384 "----------------------------" 9385 "----------------" 9386 "----------------------------\n"); 9387 } 9388 9389 9390 /****************************************************************************/ 9391 /* Prints out a summary of the driver state. */ 9392 /* */ 9393 /* Returns: */ 9394 /* Nothing. */ 9395 /****************************************************************************/ 9396 static __attribute__ ((noinline)) void 9397 bce_dump_driver_state(struct bce_softc *sc) 9398 { 9399 u32 val_hi, val_lo; 9400 9401 BCE_PRINTF( 9402 "-----------------------------" 9403 " Driver State " 9404 "-----------------------------\n"); 9405 9406 val_hi = BCE_ADDR_HI(sc); 9407 val_lo = BCE_ADDR_LO(sc); 9408 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 9409 val_hi, val_lo); 9410 9411 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 9412 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 9413 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 9414 val_hi, val_lo); 9415 9416 val_hi = BCE_ADDR_HI(sc->status_block); 9417 val_lo = BCE_ADDR_LO(sc->status_block); 9418 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 9419 val_hi, val_lo); 9420 9421 val_hi = BCE_ADDR_HI(sc->stats_block); 9422 val_lo = BCE_ADDR_LO(sc->stats_block); 9423 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 9424 val_hi, val_lo); 9425 9426 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 9427 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 9428 BCE_PRINTF( 9429 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 9430 val_hi, val_lo); 9431 9432 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 9433 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 9434 BCE_PRINTF( 9435 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 9436 val_hi, val_lo); 9437 9438 #ifdef BCE_USE_SPLIT_HEADER 9439 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 9440 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 9441 BCE_PRINTF( 9442 "0x%08X:%08X - (sc->pg_bd_chain) page chain virtual address\n", 9443 val_hi, val_lo); 9444 #endif 9445 9446 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 9447 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 9448 BCE_PRINTF( 9449 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 9450 val_hi, val_lo); 9451 9452 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 9453 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 9454 BCE_PRINTF( 9455 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 9456 val_hi, val_lo); 9457 9458 #ifdef BCE_USE_SPLIT_HEADER 9459 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 9460 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 9461 BCE_PRINTF( 9462 "0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n", 9463 val_hi, val_lo); 9464 #endif 9465 9466 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 9467 sc->interrupts_generated); 9468 9469 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 9470 sc->rx_interrupts); 9471 9472 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 9473 sc->tx_interrupts); 9474 9475 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 9476 sc->last_status_idx); 9477 9478 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 9479 sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 9480 9481 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 9482 sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 9483 9484 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 9485 sc->tx_prod_bseq); 9486 9487 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx mbufs allocated\n", 9488 sc->debug_tx_mbuf_alloc); 9489 9490 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 9491 sc->used_tx_bd); 9492 9493 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 9494 sc->tx_hi_watermark, sc->max_tx_bd); 9495 9496 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 9497 sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 9498 9499 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 9500 sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 9501 9502 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 9503 sc->rx_prod_bseq); 9504 9505 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx mbufs allocated\n", 9506 sc->debug_rx_mbuf_alloc); 9507 9508 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 9509 sc->free_rx_bd); 9510 9511 #ifdef BCE_USE_SPLIT_HEADER 9512 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer index\n", 9513 sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 9514 9515 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer index\n", 9516 sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 9517 9518 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page mbufs allocated\n", 9519 sc->debug_pg_mbuf_alloc); 9520 9521 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page rx_bd's\n", 9522 sc->free_pg_bd); 9523 9524 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n", 9525 sc->pg_low_watermark, sc->max_pg_bd); 9526 #endif 9527 9528 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) " 9529 "mbuf alloc failures\n", 9530 sc->mbuf_alloc_failed); 9531 9532 BCE_PRINTF(" 0x%08X - (sc->debug_mbuf_sim_alloc_failed) " 9533 "simulated mbuf alloc failures\n", 9534 sc->debug_mbuf_sim_alloc_failed); 9535 9536 BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n", 9537 sc->bce_flags); 9538 9539 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n", 9540 sc->bce_phy_flags); 9541 9542 BCE_PRINTF( 9543 "----------------------------" 9544 "----------------" 9545 "----------------------------\n"); 9546 } 9547 9548 9549 /****************************************************************************/ 9550 /* Prints out the hardware state through a summary of important register, */ 9551 /* followed by a complete register dump. */ 9552 /* */ 9553 /* Returns: */ 9554 /* Nothing. */ 9555 /****************************************************************************/ 9556 static __attribute__ ((noinline)) void 9557 bce_dump_hw_state(struct bce_softc *sc) 9558 { 9559 u32 val; 9560 9561 BCE_PRINTF( 9562 "----------------------------" 9563 " Hardware State " 9564 "----------------------------\n"); 9565 9566 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 9567 9568 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 9569 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 9570 val, BCE_MISC_ENABLE_STATUS_BITS); 9571 9572 val = REG_RD(sc, BCE_DMA_STATUS); 9573 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS); 9574 9575 val = REG_RD(sc, BCE_CTX_STATUS); 9576 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val, BCE_CTX_STATUS); 9577 9578 val = REG_RD(sc, BCE_EMAC_STATUS); 9579 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val, BCE_EMAC_STATUS); 9580 9581 val = REG_RD(sc, BCE_RPM_STATUS); 9582 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val, BCE_RPM_STATUS); 9583 9584 val = REG_RD(sc, 0x2004); 9585 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", val, 0x2004); 9586 9587 val = REG_RD(sc, BCE_RV2P_STATUS); 9588 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", val, BCE_RV2P_STATUS); 9589 9590 val = REG_RD(sc, 0x2c04); 9591 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", val, 0x2c04); 9592 9593 val = REG_RD(sc, BCE_TBDR_STATUS); 9594 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val, BCE_TBDR_STATUS); 9595 9596 val = REG_RD(sc, BCE_TDMA_STATUS); 9597 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val, BCE_TDMA_STATUS); 9598 9599 val = REG_RD(sc, BCE_HC_STATUS); 9600 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val, BCE_HC_STATUS); 9601 9602 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 9603 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 9604 9605 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 9606 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 9607 9608 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 9609 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 9610 9611 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 9612 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 9613 9614 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 9615 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE); 9616 9617 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 9618 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 9619 9620 BCE_PRINTF( 9621 "----------------------------" 9622 "----------------" 9623 "----------------------------\n"); 9624 9625 BCE_PRINTF( 9626 "----------------------------" 9627 " Register Dump " 9628 "----------------------------\n"); 9629 9630 for (int i = 0x400; i < 0x8000; i += 0x10) { 9631 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9632 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 9633 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 9634 } 9635 9636 BCE_PRINTF( 9637 "----------------------------" 9638 "----------------" 9639 "----------------------------\n"); 9640 } 9641 9642 9643 /****************************************************************************/ 9644 /* Prints out the mailbox queue registers. */ 9645 /* */ 9646 /* Returns: */ 9647 /* Nothing. */ 9648 /****************************************************************************/ 9649 static __attribute__ ((noinline)) void 9650 bce_dump_mq_regs(struct bce_softc *sc) 9651 { 9652 BCE_PRINTF( 9653 "----------------------------" 9654 " MQ Regs " 9655 "----------------------------\n"); 9656 9657 BCE_PRINTF( 9658 "----------------------------" 9659 "----------------" 9660 "----------------------------\n"); 9661 9662 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 9663 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9664 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 9665 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 9666 } 9667 9668 BCE_PRINTF( 9669 "----------------------------" 9670 "----------------" 9671 "----------------------------\n"); 9672 } 9673 9674 9675 /****************************************************************************/ 9676 /* Prints out the bootcode state. */ 9677 /* */ 9678 /* Returns: */ 9679 /* Nothing. */ 9680 /****************************************************************************/ 9681 static __attribute__ ((noinline)) void 9682 bce_dump_bc_state(struct bce_softc *sc) 9683 { 9684 u32 val; 9685 9686 BCE_PRINTF( 9687 "----------------------------" 9688 " Bootcode State " 9689 "----------------------------\n"); 9690 9691 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 9692 9693 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE); 9694 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 9695 val, BCE_BC_RESET_TYPE); 9696 9697 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE); 9698 BCE_PRINTF("0x%08X - (0x%06X) state\n", 9699 val, BCE_BC_STATE); 9700 9701 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION); 9702 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 9703 val, BCE_BC_CONDITION); 9704 9705 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD); 9706 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 9707 val, BCE_BC_STATE_DEBUG_CMD); 9708 9709 BCE_PRINTF( 9710 "----------------------------" 9711 "----------------" 9712 "----------------------------\n"); 9713 } 9714 9715 9716 /****************************************************************************/ 9717 /* Prints out the TXP processor state. */ 9718 /* */ 9719 /* Returns: */ 9720 /* Nothing. */ 9721 /****************************************************************************/ 9722 static __attribute__ ((noinline)) void 9723 bce_dump_txp_state(struct bce_softc *sc, int regs) 9724 { 9725 u32 val; 9726 9727 BCE_PRINTF( 9728 "----------------------------" 9729 " TXP State " 9730 "----------------------------\n"); 9731 9732 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 9733 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val, BCE_TXP_CPU_MODE); 9734 9735 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 9736 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 9737 9738 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 9739 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val, 9740 BCE_TXP_CPU_EVENT_MASK); 9741 9742 if (regs) { 9743 BCE_PRINTF( 9744 "----------------------------" 9745 " Register Dump " 9746 "----------------------------\n"); 9747 9748 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 9749 /* Skip the big blank spaces */ 9750 if (i < 0x454000 && i > 0x5ffff) 9751 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9752 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 9753 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 9754 } 9755 } 9756 9757 BCE_PRINTF( 9758 "----------------------------" 9759 "----------------" 9760 "----------------------------\n"); 9761 } 9762 9763 9764 /****************************************************************************/ 9765 /* Prints out the RXP processor state. */ 9766 /* */ 9767 /* Returns: */ 9768 /* Nothing. */ 9769 /****************************************************************************/ 9770 static __attribute__ ((noinline)) void 9771 bce_dump_rxp_state(struct bce_softc *sc, int regs) 9772 { 9773 u32 val; 9774 9775 BCE_PRINTF( 9776 "----------------------------" 9777 " RXP State " 9778 "----------------------------\n"); 9779 9780 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 9781 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val, BCE_RXP_CPU_MODE); 9782 9783 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 9784 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 9785 9786 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 9787 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val, 9788 BCE_RXP_CPU_EVENT_MASK); 9789 9790 if (regs) { 9791 BCE_PRINTF( 9792 "----------------------------" 9793 " Register Dump " 9794 "----------------------------\n"); 9795 9796 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 9797 /* Skip the big blank sapces */ 9798 if (i < 0xc5400 && i > 0xdffff) 9799 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9800 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 9801 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 9802 } 9803 } 9804 9805 BCE_PRINTF( 9806 "----------------------------" 9807 "----------------" 9808 "----------------------------\n"); 9809 } 9810 9811 9812 /****************************************************************************/ 9813 /* Prints out the TPAT processor state. */ 9814 /* */ 9815 /* Returns: */ 9816 /* Nothing. */ 9817 /****************************************************************************/ 9818 static __attribute__ ((noinline)) void 9819 bce_dump_tpat_state(struct bce_softc *sc, int regs) 9820 { 9821 u32 val; 9822 9823 BCE_PRINTF( 9824 "----------------------------" 9825 " TPAT State " 9826 "----------------------------\n"); 9827 9828 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 9829 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val, BCE_TPAT_CPU_MODE); 9830 9831 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 9832 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 9833 9834 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 9835 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val, 9836 BCE_TPAT_CPU_EVENT_MASK); 9837 9838 if (regs) { 9839 BCE_PRINTF( 9840 "----------------------------" 9841 " Register Dump " 9842 "----------------------------\n"); 9843 9844 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 9845 /* Skip the big blank spaces */ 9846 if (i < 0x854000 && i > 0x9ffff) 9847 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9848 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 9849 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 9850 } 9851 } 9852 9853 BCE_PRINTF( 9854 "----------------------------" 9855 "----------------" 9856 "----------------------------\n"); 9857 } 9858 9859 9860 /****************************************************************************/ 9861 /* Prints out the Command Procesor (CP) state. */ 9862 /* */ 9863 /* Returns: */ 9864 /* Nothing. */ 9865 /****************************************************************************/ 9866 static __attribute__ ((noinline)) void 9867 bce_dump_cp_state(struct bce_softc *sc, int regs) 9868 { 9869 u32 val; 9870 9871 BCE_PRINTF( 9872 "----------------------------" 9873 " CP State " 9874 "----------------------------\n"); 9875 9876 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 9877 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", val, BCE_CP_CPU_MODE); 9878 9879 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 9880 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 9881 9882 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 9883 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 9884 BCE_CP_CPU_EVENT_MASK); 9885 9886 if (regs) { 9887 BCE_PRINTF( 9888 "----------------------------" 9889 " Register Dump " 9890 "----------------------------\n"); 9891 9892 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 9893 /* Skip the big blank spaces */ 9894 if (i < 0x185400 && i > 0x19ffff) 9895 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9896 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 9897 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 9898 } 9899 } 9900 9901 BCE_PRINTF( 9902 "----------------------------" 9903 "----------------" 9904 "----------------------------\n"); 9905 } 9906 9907 9908 /****************************************************************************/ 9909 /* Prints out the Completion Procesor (COM) state. */ 9910 /* */ 9911 /* Returns: */ 9912 /* Nothing. */ 9913 /****************************************************************************/ 9914 static __attribute__ ((noinline)) void 9915 bce_dump_com_state(struct bce_softc *sc, int regs) 9916 { 9917 u32 val; 9918 9919 BCE_PRINTF( 9920 "----------------------------" 9921 " COM State " 9922 "----------------------------\n"); 9923 9924 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 9925 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", val, BCE_COM_CPU_MODE); 9926 9927 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 9928 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 9929 9930 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 9931 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 9932 BCE_COM_CPU_EVENT_MASK); 9933 9934 if (regs) { 9935 BCE_PRINTF( 9936 "----------------------------" 9937 " Register Dump " 9938 "----------------------------\n"); 9939 9940 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 9941 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9942 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 9943 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 9944 } 9945 } 9946 9947 BCE_PRINTF( 9948 "----------------------------" 9949 "----------------" 9950 "----------------------------\n"); 9951 } 9952 9953 9954 /****************************************************************************/ 9955 /* Prints out the driver state and then enters the debugger. */ 9956 /* */ 9957 /* Returns: */ 9958 /* Nothing. */ 9959 /****************************************************************************/ 9960 static void 9961 bce_breakpoint(struct bce_softc *sc) 9962 { 9963 9964 /* 9965 * Unreachable code to silence compiler warnings 9966 * about unused functions. 9967 */ 9968 if (0) { 9969 bce_freeze_controller(sc); 9970 bce_unfreeze_controller(sc); 9971 bce_dump_txbd(sc, 0, NULL); 9972 bce_dump_rxbd(sc, 0, NULL); 9973 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 9974 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 9975 bce_dump_l2fhdr(sc, 0, NULL); 9976 bce_dump_ctx(sc, RX_CID); 9977 bce_dump_ftqs(sc); 9978 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 9979 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 9980 bce_dump_status_block(sc); 9981 bce_dump_stats_block(sc); 9982 bce_dump_driver_state(sc); 9983 bce_dump_hw_state(sc); 9984 bce_dump_bc_state(sc); 9985 bce_dump_txp_state(sc, 0); 9986 bce_dump_rxp_state(sc, 0); 9987 bce_dump_tpat_state(sc, 0); 9988 bce_dump_cp_state(sc, 0); 9989 bce_dump_com_state(sc, 0); 9990 #ifdef BCE_USE_SPLIT_HEADER 9991 bce_dump_pgbd(sc, 0, NULL); 9992 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 9993 bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 9994 #endif 9995 } 9996 9997 bce_dump_status_block(sc); 9998 bce_dump_driver_state(sc); 9999 10000 /* Call the debugger. */ 10001 breakpoint(); 10002 10003 return; 10004 } 10005 #endif 10006 10007